diff -rup xf86-video-r128-master.orig/src/r128.h xf86-video-r128-master/src/r128.h
--- xf86-video-r128-master.orig/src/r128.h	2012-03-23 15:39:14.624681988 -0700
+++ xf86-video-r128-master/src/r128.h	2012-03-23 15:39:58.805365235 -0700
@@ -77,6 +77,8 @@
 #define R128_VBIOS_SIZE 0x00010000
 
 #if R128_DEBUG
+#include "r128_version.h"
+
 #define R128TRACE(x)                                          \
     do {                                                      \
 	ErrorF("(**) %s(%d): ", R128_NAME, pScrn->scrnIndex); \
diff -rup xf86-video-r128-master.orig/src/r128_driver.c xf86-video-r128-master/src/r128_driver.c
--- xf86-video-r128-master.orig/src/r128_driver.c	2012-03-23 15:39:14.631348758 -0700
+++ xf86-video-r128-master/src/r128_driver.c	2012-03-23 15:42:01.033922134 -0700
@@ -2897,16 +2897,6 @@ static void R128RestorePLL2Registers(Scr
 					| R128_P2PLL_ATOMIC_UPDATE_EN
 					| R128_P2PLL_VGA_ATOMIC_UPDATE_EN));
 
-    R128TRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
-	       restore->p2pll_ref_div,
-	       restore->p2pll_div_0,
-	       restore->htotal_cntl2,
-	       INPLL(pScrn, RADEON_P2PLL_CNTL)));
-    R128TRACE(("Wrote: rd=%d, fd=%d, pd=%d\n",
-	       restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
-	       restore->p2pll_div_0 & RADEON_P2PLL_FB3_DIV_MASK,
-	       (restore->p2pll_div_0 & RADEON_P2PLL_POST3_DIV_MASK) >>16));
-
     usleep(5000); /* Let the clock to lock */
 
     OUTPLLP(pScrn, R128_V2CLK_VCLKTV_CNTL,
@@ -3793,12 +3783,6 @@ static void R128InitPLL2Registers(R128Sa
 				     pll->reference_freq);
     save->post_div_2       = post_div->divider;
 
-    R128TRACE(("dc=%d, of=%d, fd=%d, pd=%d\n",
-	       save->dot_clock_freq_2,
-	       save->pll_output_freq_2,
-	       save->feedback_div_2,
-	       save->post_div_2));
-
     save->p2pll_ref_div   = pll->reference_div;
     save->p2pll_div_0    = (save->feedback_div_2 | (post_div->bitvalue<<16));
     save->htotal_cntl2    = 0;