diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d13e8a4..d1d3d6b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6215,6 +6215,9 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 			   fp == I915_READ(PCH_FP0(1))) {
 			intel_crtc->use_pll_a = false;
 			DRM_DEBUG_KMS("using pipe b dpll\n");
+		} else if (has_edp_encoder &&
+			   !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+			DRM_DEBUG_KMS("CPU eDP, no PCH PLL needed\n");
 		} else {
 			DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
 			return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 110552f..c4da390 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2417,6 +2417,10 @@ intel_dp_init(struct drm_device *dev, int output_reg)
 	}
 
 	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+
+	if (IS_IVYBRIDGE(dev) && output_reg == DP_A)
+		intel_encoder->crtc_mask = (1 << 2);
+
 	connector->interlace_allowed = true;
 	connector->doublescan_allowed = 0;