From d194ac5196d532f69a50970eaf7e3a1cbec295ef Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 16 Apr 2012 10:08:13 -0400 Subject: [PATCH] drm/radeon: fix tiling calculation on rs780/rs880 IGP chips have a fixed bank size. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=48747 Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/r600.c | 10 ++++++++-- 1 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 66d39ce..0fa57e1 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -1626,8 +1626,14 @@ void r600_gpu_init(struct radeon_device *rdev) break; } rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; - rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); - tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); + /* num banks is 8 on integrated asics. */ + if (rdev->flags & RADEON_IS_IGP) { + rdev->config.r600.tiling_nbanks = 4 << 1; + tiling_config |= BANK_TILING(1); + } else { + rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); + tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); + } tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) rdev->config.r600.tiling_group_size = 512; -- 1.7.7.5