ke_fdi_link_train], FDI_RX_IIR 0x100
[  302.643362] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  302.643518] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  302.643521] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  302.643524] [drm:ironlake_fdi_link_train], FDI train done
[  302.643527] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  302.643533] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  302.644748] [drm:intel_update_fbc], 
[  302.696978] [drm:intel_wait_for_vblank], vblank wait timed out
[  302.697290] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  302.698214] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  302.699037] [drm:intel_dp_start_link_train], clock recovery OK
[  302.704900] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  302.704931] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  302.704976] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  302.705989] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  302.705996] [drm:intel_crt_detect], CRT not detected via hotplug
[  302.706001] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  302.707941] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  302.707948] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  302.707954] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  302.708269] [drm:intel_dp_detect], DPCD: 110a840101000000
[  302.709301] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  302.721374] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  302.736658] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  302.763751] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  302.763757] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  302.763761] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  307.771031] [drm:drm_mode_addfb], [FB:100]
[  307.771056] [drm:drm_mode_setcrtc], [CRTC:3]
[  307.771063] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  307.771065] [drm:drm_crtc_helper_set_config], 
[  307.771066] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:100] #connectors=1 (x y) (0 0)
[  307.771071] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  307.771073] [drm:drm_mode_debug_printmodeline], Modeline 100:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
[  307.771076] [drm:drm_mode_debug_printmodeline], Modeline 101:"1440x576" 50 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
[  307.771079] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  307.771081] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  307.771083] [drm:drm_mode_debug_printmodeline], Modeline 101:"1440x576" 50 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
[  307.771086] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 27000KHz
[  307.771089] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  307.771091] [drm:intel_dp_mode_fixup], DP link bw required 64800 available 129600
[  307.771093] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  307.771301] [drm:intel_dp_link_down], 
[  307.841792] [drm:intel_wait_for_vblank], vblank wait timed out
[  307.943734] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  307.945706] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  307.945714] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  307.946126] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
[  307.946132] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  307.946138] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
[  307.946144] [drm:intel_update_fbc], 
[  307.946151] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  307.946156] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  307.946162] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  307.946166] [drm:drm_mode_debug_printmodeline], Modeline 101:"1440x576" 50 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
[  307.946174] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  307.946179] [drm:intel_get_pch_pll], switching PLL c6014 off
[  307.997750] [drm:intel_wait_for_vblank], vblank wait timed out
[  307.997757] [drm:ironlake_update_plane], Writing base 0B442000 00000000 0 0 5760
[  308.049727] [drm:intel_wait_for_vblank], vblank wait timed out
[  308.049732] [drm:intel_update_fbc], 
[  308.049736] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
[  308.049742] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  308.049747] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
[  308.049753] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:101:1440x576]
[  308.049759] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  308.049763] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  308.049768] [drm:ironlake_write_eld], ELD on pipe A
[  308.049772] [drm:ironlake_write_eld], Audio directed to unknown port
[  308.049775] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  308.049789] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
[  308.049793] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  308.049798] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
[  308.101662] [drm:intel_wait_for_vblank], vblank wait timed out
[  308.153645] [drm:intel_wait_for_vblank], vblank wait timed out
[  308.153955] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  308.153959] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  308.154115] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  308.154119] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  308.154121] [drm:ironlake_fdi_link_train], FDI train done
[  308.154125] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  308.154130] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  308.155345] [drm:intel_update_fbc], 
[  308.206618] [drm:intel_wait_for_vblank], vblank wait timed out
[  308.206930] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  308.207853] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  308.208675] [drm:intel_dp_start_link_train], clock recovery OK
[  308.214529] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  308.214537] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  308.214626] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  308.215566] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  308.215573] [drm:intel_crt_detect], CRT not detected via hotplug
[  308.215577] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  308.217590] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  308.217600] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  308.217607] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  308.217922] [drm:intel_dp_detect], DPCD: 110a840101000000
[  308.218964] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  308.234318] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  308.246098] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  308.273154] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  308.273160] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  308.273165] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  313.282744] [drm:drm_mode_addfb], [FB:101]
[  313.282767] [drm:drm_mode_setcrtc], [CRTC:3]
[  313.282771] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  313.282773] [drm:drm_crtc_helper_set_config], 
[  313.282775] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:101] #connectors=1 (x y) (0 0)
[  313.282780] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  313.282782] [drm:drm_mode_debug_printmodeline], Modeline 101:"1440x576" 50 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
[  313.282785] [drm:drm_mode_debug_printmodeline], Modeline 102:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
[  313.282789] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  313.282791] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  313.282792] [drm:drm_mode_debug_printmodeline], Modeline 102:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
[  313.282797] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 78800KHz
[  313.282800] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
[  313.282802] [drm:intel_dp_mode_fixup], DP link bw required 189120 available 216000
[  313.282804] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  313.283013] [drm:intel_dp_link_down], 
[  313.353390] [drm:intel_wait_for_vblank], vblank wait timed out
[  313.455415] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  313.457311] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  313.457317] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  313.457729] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
[  313.457734] [drm:ironlake_check_srwm], watermark 1: display plane 49, fbc lines 3, cursor 6
[  313.457739] [drm:ironlake_check_srwm], watermark 2: display plane 108, fbc lines 4, cursor 10
[  313.457744] [drm:intel_update_fbc], 
[  313.457750] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  313.457754] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  313.457759] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  313.457762] [drm:drm_mode_debug_printmodeline], Modeline 102:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
[  313.457768] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  313.457772] [drm:intel_get_pch_pll], switching PLL c6014 off
[  313.509348] [drm:intel_wait_for_vblank], vblank wait timed out
[  313.509355] [drm:ironlake_update_plane], Writing base 0B76C000 00000000 0 0 4096
[  313.561325] [drm:intel_wait_for_vblank], vblank wait timed out
[  313.561330] [drm:intel_update_fbc], 
[  313.561334] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
[  313.561339] [drm:ironlake_check_srwm], watermark 1: display plane 49, fbc lines 3, cursor 6
[  313.561344] [drm:ironlake_check_srwm], watermark 2: display plane 108, fbc lines 4, cursor 10
[  313.561350] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:102:1024x768]
[  313.561356] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  313.561360] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  313.561365] [drm:ironlake_write_eld], ELD on pipe A
[  313.561369] [drm:ironlake_write_eld], Audio directed to unknown port
[  313.561372] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  313.561386] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
[  313.561391] [drm:ironlake_check_srwm], watermark 1: display plane 49, fbc lines 3, cursor 6
[  313.561396] [drm:ironlake_check_srwm], watermark 2: display plane 108, fbc lines 4, cursor 10
[  313.613306] [drm:intel_wait_for_vblank], vblank wait timed out
[  313.665311] [drm:intel_wait_for_vblank], vblank wait timed out
[  313.665622] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  313.665625] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  313.665781] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  313.665785] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  313.665788] [drm:ironlake_fdi_link_train], FDI train done
[  313.665791] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  313.665796] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  313.667018] [drm:intel_update_fbc], 
[  313.719258] [drm:intel_wait_for_vblank], vblank wait timed out
[  313.719569] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  313.720398] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  313.721219] [drm:intel_dp_start_link_train], clock recovery OK
[  313.727060] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  313.727066] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  313.727146] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  313.728088] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  313.728095] [drm:intel_crt_detect], CRT not detected via hotplug
[  313.728100] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  313.729220] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  313.729227] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  313.729233] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  313.729548] [drm:intel_dp_detect], DPCD: 110a840101000000
[  313.730579] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  313.740238] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  313.757755] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  313.784951] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  313.784956] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  313.784961] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  318.792739] [drm:drm_mode_addfb], [FB:102]
[  318.792764] [drm:drm_mode_setcrtc], [CRTC:3]
[  318.792768] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  318.792771] [drm:drm_crtc_helper_set_config], 
[  318.792772] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:102] #connectors=1 (x y) (0 0)
[  318.792777] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  318.792779] [drm:drm_mode_debug_printmodeline], Modeline 102:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
[  318.792782] [drm:drm_mode_debug_printmodeline], Modeline 103:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
[  318.792786] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  318.792788] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  318.792790] [drm:drm_mode_debug_printmodeline], Modeline 103:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
[  318.792794] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 78750KHz
[  318.792797] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
[  318.792799] [drm:intel_dp_mode_fixup], DP link bw required 189000 available 216000
[  318.792801] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  318.793049] [drm:intel_dp_link_down], 
[  318.864097] [drm:intel_wait_for_vblank], vblank wait timed out
[  318.966053] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  318.967971] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  318.967979] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  318.968391] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
[  318.968397] [drm:ironlake_check_srwm], watermark 1: display plane 49, fbc lines 3, cursor 6
[  318.968404] [drm:ironlake_check_srwm], watermark 2: display plane 108, fbc lines 4, cursor 10
[  318.968410] [drm:intel_update_fbc], 
[  318.968416] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  318.968422] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  318.968427] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  318.968431] [drm:drm_mode_debug_printmodeline], Modeline 103:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
[  318.968439] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  318.968444] [drm:intel_get_pch_pll], switching PLL c6014 off
[  319.019988] [drm:intel_wait_for_vblank], vblank wait timed out
[  319.019995] [drm:ironlake_update_plane], Writing base 0BA6C000 00000000 0 0 4096
[  319.071966] [drm:intel_wait_for_vblank], vblank wait timed out
[  319.071971] [drm:intel_update_fbc], 
[  319.071975] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
[  319.071980] [drm:ironlake_check_srwm], watermark 1: display plane 49, fbc lines 3, cursor 6
[  319.071985] [drm:ironlake_check_srwm], watermark 2: display plane 108, fbc lines 4, cursor 10
[  319.071991] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:103:1024x768]
[  319.071997] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  319.072002] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  319.072006] [drm:ironlake_write_eld], ELD on pipe A
[  319.072010] [drm:ironlake_write_eld], Audio directed to unknown port
[  319.072014] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  319.072027] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
[  319.072031] [drm:ironlake_check_srwm], watermark 1: display plane 49, fbc lines 3, cursor 6
[  319.072036] [drm:ironlake_check_srwm], watermark 2: display plane 108, fbc lines 4, cursor 10
[  319.123982] [drm:intel_wait_for_vblank], vblank wait timed out
[  319.175963] [drm:intel_wait_for_vblank], vblank wait timed out
[  319.176273] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  319.176277] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  319.176433] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  319.176436] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  319.176439] [drm:ironlake_fdi_link_train], FDI train done
[  319.176442] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  319.176448] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  319.177663] [drm:intel_update_fbc], 
[  319.229896] [drm:intel_wait_for_vblank], vblank wait timed out
[  319.230208] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  319.231139] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  319.231962] [drm:intel_dp_start_link_train], clock recovery OK
[  319.237819] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  319.237888] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  319.237914] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  319.238854] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  319.238860] [drm:intel_crt_detect], CRT not detected via hotplug
[  319.238864] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  319.240834] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  319.240841] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  319.240847] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  319.241162] [drm:intel_dp_detect], DPCD: 110a840101000000
[  319.242193] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  319.250956] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  319.269477] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  319.296898] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  319.296904] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  319.296909] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  324.306082] [drm:drm_mode_addfb], [FB:103]
[  324.306107] [drm:drm_mode_setcrtc], [CRTC:3]
[  324.306114] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  324.306116] [drm:drm_crtc_helper_set_config], 
[  324.306117] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:103] #connectors=1 (x y) (0 0)
[  324.306122] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  324.306124] [drm:drm_mode_debug_printmodeline], Modeline 103:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
[  324.306127] [drm:drm_mode_debug_printmodeline], Modeline 104:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
[  324.306130] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  324.306132] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  324.306134] [drm:drm_mode_debug_printmodeline], Modeline 104:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
[  324.306138] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 75000KHz
[  324.306140] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
[  324.306142] [drm:intel_dp_mode_fixup], DP link bw required 180000 available 216000
[  324.306144] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  324.306352] [drm:intel_dp_link_down], 
[  324.376693] [drm:intel_wait_for_vblank], vblank wait timed out
[  324.478647] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  324.480690] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  324.480698] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  324.481110] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
[  324.481116] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6
[  324.481122] [drm:ironlake_check_srwm], watermark 2: display plane 103, fbc lines 4, cursor 10
[  324.481128] [drm:intel_update_fbc], 
[  324.481135] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  324.481141] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  324.481146] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  324.481150] [drm:drm_mode_debug_printmodeline], Modeline 104:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
[  324.481158] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  324.481163] [drm:intel_get_pch_pll], switching PLL c6014 off
[  324.532668] [drm:intel_wait_for_vblank], vblank wait timed out
[  324.532675] [drm:ironlake_update_plane], Writing base 0BD6C000 00000000 0 0 4096
[  324.584602] [drm:intel_wait_for_vblank], vblank wait timed out
[  324.584607] [drm:intel_update_fbc], 
[  324.584611] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
[  324.584616] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6
[  324.584622] [drm:ironlake_check_srwm], watermark 2: display plane 103, fbc lines 4, cursor 10
[  324.584628] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:104:1024x768]
[  324.584634] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  324.584638] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  324.584643] [drm:ironlake_write_eld], ELD on pipe A
[  324.584647] [drm:ironlake_write_eld], Audio directed to unknown port
[  324.584650] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  324.584664] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
[  324.584668] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6
[  324.584673] [drm:ironlake_check_srwm], watermark 2: display plane 103, fbc lines 4, cursor 10
[  324.636582] [drm:intel_wait_for_vblank], vblank wait timed out
[  324.688560] [drm:intel_wait_for_vblank], vblank wait timed out
[  324.688870] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  324.688873] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  324.689029] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  324.689033] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  324.689036] [drm:ironlake_fdi_link_train], FDI train done
[  324.689039] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  324.689045] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  324.690260] [drm:intel_update_fbc], 
[  324.741578] [drm:intel_wait_for_vblank], vblank wait timed out
[  324.741889] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  324.742813] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  324.743635] [drm:intel_dp_start_link_train], clock recovery OK
[  324.749459] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  324.749526] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  324.749560] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  324.750499] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  324.750504] [drm:intel_crt_detect], CRT not detected via hotplug
[  324.750509] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  324.752495] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  324.752502] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  324.752508] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  324.752823] [drm:intel_dp_detect], DPCD: 110a840101000000
[  324.753853] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  324.763535] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  324.781186] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  324.808535] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  324.808540] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  324.808545] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  329.822495] [drm:drm_mode_addfb], [FB:104]
[  329.822519] [drm:drm_mode_setcrtc], [CRTC:3]
[  329.822523] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  329.822529] [drm:drm_crtc_helper_set_config], 
[  329.822530] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:104] #connectors=1 (x y) (0 0)
[  329.822535] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  329.822537] [drm:drm_mode_debug_printmodeline], Modeline 104:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
[  329.822539] [drm:drm_mode_debug_printmodeline], Modeline 105:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
[  329.822543] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  329.822545] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  329.822546] [drm:drm_mode_debug_printmodeline], Modeline 105:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
[  329.822550] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 65000KHz
[  329.822553] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
[  329.822555] [drm:intel_dp_mode_fixup], DP link bw required 156000 available 216000
[  329.822557] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  329.822765] [drm:intel_dp_link_down], 
[  329.893330] [drm:intel_wait_for_vblank], vblank wait timed out
[  329.995285] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  329.999351] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  329.999358] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  329.999769] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
[  329.999774] [drm:ironlake_check_srwm], watermark 1: display plane 41, fbc lines 3, cursor 6
[  329.999779] [drm:ironlake_check_srwm], watermark 2: display plane 90, fbc lines 4, cursor 10
[  329.999784] [drm:intel_update_fbc], 
[  329.999790] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  329.999795] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  329.999799] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  329.999802] [drm:drm_mode_debug_printmodeline], Modeline 105:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
[  329.999809] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  329.999813] [drm:intel_get_pch_pll], switching PLL c6014 off
[  330.051303] [drm:intel_wait_for_vblank], vblank wait timed out
[  330.051310] [drm:ironlake_update_plane], Writing base 0C06C000 00000000 0 0 4096
[  330.103237] [drm:intel_wait_for_vblank], vblank wait timed out
[  330.103242] [drm:intel_update_fbc], 
[  330.103246] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
[  330.103251] [drm:ironlake_check_srwm], watermark 1: display plane 41, fbc lines 3, cursor 6
[  330.103256] [drm:ironlake_check_srwm], watermark 2: display plane 90, fbc lines 4, cursor 10
[  330.103262] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:105:1024x768]
[  330.103268] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  330.103273] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  330.103277] [drm:ironlake_write_eld], ELD on pipe A
[  330.103281] [drm:ironlake_write_eld], Audio directed to unknown port
[  330.103285] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  330.103298] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
[  330.103303] [drm:ironlake_check_srwm], watermark 1: display plane 41, fbc lines 3, cursor 6
[  330.103308] [drm:ironlake_check_srwm], watermark 2: display plane 90, fbc lines 4, cursor 10
[  330.155217] [drm:intel_wait_for_vblank], vblank wait timed out
[  330.207196] [drm:intel_wait_for_vblank], vblank wait timed out
[  330.207506] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  330.207510] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  330.207666] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  330.207669] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  330.207672] [drm:ironlake_fdi_link_train], FDI train done
[  330.207675] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  330.207681] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  330.208902] [drm:intel_update_fbc], 
[  330.260214] [drm:intel_wait_for_vblank], vblank wait timed out
[  330.260526] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  330.261449] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  330.262271] [drm:intel_dp_start_link_train], clock recovery OK
[  330.268080] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  330.268086] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  330.268126] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  330.269066] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  330.269072] [drm:intel_crt_detect], CRT not detected via hotplug
[  330.269076] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  330.270106] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  330.270112] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  330.270118] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  330.270433] [drm:intel_dp_detect], DPCD: 110a840101000000
[  330.271464] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  330.284564] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  330.298821] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  330.326149] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  330.326155] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  330.326160] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  335.316702] [drm:drm_mode_addfb], [FB:105]
[  335.316727] [drm:drm_mode_setcrtc], [CRTC:3]
[  335.316731] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  335.316733] [drm:drm_crtc_helper_set_config], 
[  335.316734] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:105] #connectors=1 (x y) (0 0)
[  335.316740] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  335.316742] [drm:drm_mode_debug_printmodeline], Modeline 105:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
[  335.316745] [drm:drm_mode_debug_printmodeline], Modeline 106:"1440x480" 60 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
[  335.316748] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  335.316751] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  335.316752] [drm:drm_mode_debug_printmodeline], Modeline 106:"1440x480" 60 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
[  335.316757] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 27000KHz
[  335.316760] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  335.316762] [drm:intel_dp_mode_fixup], DP link bw required 64800 available 129600
[  335.316764] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  335.316979] [drm:intel_dp_link_down], 
[  335.388017] [drm:intel_wait_for_vblank], vblank wait timed out
[  335.489926] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  335.491894] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  335.491902] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  335.492314] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
[  335.492320] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  335.492327] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
[  335.492332] [drm:intel_update_fbc], 
[  335.492340] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  335.492345] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  335.492350] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  335.492354] [drm:drm_mode_debug_printmodeline], Modeline 106:"1440x480" 60 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
[  335.492363] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  335.492367] [drm:intel_get_pch_pll], switching PLL c6014 off
[  335.543908] [drm:intel_wait_for_vblank], vblank wait timed out
[  335.543916] [drm:ironlake_update_plane], Writing base 0C36C000 00000000 0 0 5760
[  335.595927] [drm:intel_wait_for_vblank], vblank wait timed out
[  335.595932] [drm:intel_update_fbc], 
[  335.595936] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
[  335.595941] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  335.595947] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
[  335.595952] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:106:1440x480]
[  335.595958] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  335.595963] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  335.595967] [drm:ironlake_write_eld], ELD on pipe A
[  335.595971] [drm:ironlake_write_eld], Audio directed to unknown port
[  335.595975] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  335.595989] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
[  335.595993] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  335.595998] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
[  335.647908] [drm:intel_wait_for_vblank], vblank wait timed out
[  335.699841] [drm:intel_wait_for_vblank], vblank wait timed out
[  335.700152] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  335.700156] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  335.700312] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  335.700315] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  335.700318] [drm:ironlake_fdi_link_train], FDI train done
[  335.700321] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  335.700327] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  335.701543] [drm:intel_update_fbc], 
[  335.752816] [drm:intel_wait_for_vblank], vblank wait timed out
[  335.753027] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  335.753957] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  335.754779] [drm:intel_dp_start_link_train], clock recovery OK
[  335.760626] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  335.760634] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  335.760715] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  335.761659] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  335.761665] [drm:intel_crt_detect], CRT not detected via hotplug
[  335.761670] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  335.762777] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  335.762784] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  335.762790] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  335.763105] [drm:intel_dp_detect], DPCD: 110a840101000000
[  335.764136] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  335.777097] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  335.791189] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  335.818252] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  335.818257] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  335.818262] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  340.816414] [drm:drm_mode_addfb], [FB:106]
[  340.816434] [drm:drm_mode_setcrtc], [CRTC:3]
[  340.816438] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  340.816440] [drm:drm_crtc_helper_set_config], 
[  340.816441] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:106] #connectors=1 (x y) (0 0)
[  340.816446] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  340.816448] [drm:drm_mode_debug_printmodeline], Modeline 106:"1440x480" 60 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
[  340.816451] [drm:drm_mode_debug_printmodeline], Modeline 107:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
[  340.816455] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  340.816458] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  340.816459] [drm:drm_mode_debug_printmodeline], Modeline 107:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
[  340.816463] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 46970KHz
[  340.816466] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  340.816468] [drm:intel_dp_mode_fixup], DP link bw required 112728 available 129600
[  340.816470] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  340.816721] [drm:intel_dp_link_down], 
[  340.887613] [drm:intel_wait_for_vblank], vblank wait timed out
[  340.989573] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  340.991544] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  340.991552] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  340.991964] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
[  340.991970] [drm:ironlake_check_srwm], watermark 1: display plane 30, fbc lines 3, cursor 6
[  340.991976] [drm:ironlake_check_srwm], watermark 2: display plane 65, fbc lines 4, cursor 6
[  340.991982] [drm:intel_update_fbc], 
[  340.991988] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  340.991994] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  340.991999] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  340.992003] [drm:drm_mode_debug_printmodeline], Modeline 107:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
[  340.992011] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  340.992016] [drm:intel_get_pch_pll], switching PLL c6014 off
[  341.043593] [drm:intel_wait_for_vblank], vblank wait timed out
[  341.043600] [drm:ironlake_update_plane], Writing base 0C60F000 00000000 0 0 4096
[  341.095571] [drm:intel_wait_for_vblank], vblank wait timed out
[  341.095576] [drm:intel_update_fbc], 
[  341.095580] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
[  341.095585] [drm:ironlake_check_srwm], watermark 1: display plane 30, fbc lines 3, cursor 6
[  341.095590] [drm:ironlake_check_srwm], watermark 2: display plane 65, fbc lines 4, cursor 6
[  341.095596] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:107:1024x576]
[  341.095602] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  341.095606] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  341.095611] [drm:ironlake_write_eld], ELD on pipe A
[  341.095615] [drm:ironlake_write_eld], Audio directed to unknown port
[  341.095618] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  341.095632] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
[  341.095637] [drm:ironlake_check_srwm], watermark 1: display plane 30, fbc lines 3, cursor 6
[  341.095641] [drm:ironlake_check_srwm], watermark 2: display plane 65, fbc lines 4, cursor 6
[  341.147479] [drm:intel_wait_for_vblank], vblank wait timed out
[  341.199482] [drm:intel_wait_for_vblank], vblank wait timed out
[  341.199792] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  341.199796] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  341.199952] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  341.199956] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  341.199959] [drm:ironlake_fdi_link_train], FDI train done
[  341.199962] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  341.199967] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  341.201183] [drm:intel_update_fbc], 
[  341.252459] [drm:intel_wait_for_vblank], vblank wait timed out
[  341.252771] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  341.253695] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  341.254516] [drm:intel_dp_start_link_train], clock recovery OK
[  341.260369] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  341.260377] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  341.260452] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  341.261412] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  341.261420] [drm:intel_crt_detect], CRT not detected via hotplug
[  341.261425] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  341.263425] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  341.263432] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  341.263437] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  341.263752] [drm:intel_dp_detect], DPCD: 110a840101000000
[  341.264783] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  341.276868] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  341.291856] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  341.318970] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  341.318975] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  341.318980] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  346.314051] [drm:drm_mode_addfb], [FB:107]
[  346.314070] [drm:drm_mode_setcrtc], [CRTC:3]
[  346.314077] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  346.314079] [drm:drm_crtc_helper_set_config], 
[  346.314080] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:107] #connectors=1 (x y) (0 0)
[  346.314084] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  346.314086] [drm:drm_mode_debug_printmodeline], Modeline 107:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
[  346.314088] [drm:drm_mode_debug_printmodeline], Modeline 108:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
[  346.314092] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  346.314094] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  346.314095] [drm:drm_mode_debug_printmodeline], Modeline 108:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
[  346.314099] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 50000KHz
[  346.314101] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  346.314103] [drm:intel_dp_mode_fixup], DP link bw required 120000 available 129600
[  346.314105] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  346.314313] [drm:intel_dp_link_down], 
[  346.385262] [drm:intel_wait_for_vblank], vblank wait timed out
[  346.487219] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  346.493260] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  346.493266] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  346.493677] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6
[  346.493682] [drm:ironlake_check_srwm], watermark 1: display plane 32, fbc lines 3, cursor 6
[  346.493687] [drm:ironlake_check_srwm], watermark 2: display plane 70, fbc lines 4, cursor 10
[  346.493692] [drm:intel_update_fbc], 
[  346.493698] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  346.493703] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  346.493707] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  346.493710] [drm:drm_mode_debug_printmodeline], Modeline 108:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
[  346.493717] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  346.493721] [drm:intel_get_pch_pll], switching PLL c6014 off
[  346.545192] [drm:intel_wait_for_vblank], vblank wait timed out
[  346.545199] [drm:ironlake_update_plane], Writing base 0C84F000 00000000 0 0 3200
[  346.597167] [drm:intel_wait_for_vblank], vblank wait timed out
[  346.597172] [drm:intel_update_fbc], 
[  346.597176] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6
[  346.597181] [drm:ironlake_check_srwm], watermark 1: display plane 32, fbc lines 3, cursor 6
[  346.597186] [drm:ironlake_check_srwm], watermark 2: display plane 70, fbc lines 4, cursor 10
[  346.597192] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:108:800x600]
[  346.597198] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  346.597202] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  346.597207] [drm:ironlake_write_eld], ELD on pipe A
[  346.597211] [drm:ironlake_write_eld], Audio directed to unknown port
[  346.597214] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  346.597228] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6
[  346.597233] [drm:ironlake_check_srwm], watermark 1: display plane 32, fbc lines 3, cursor 6
[  346.597238] [drm:ironlake_check_srwm], watermark 2: display plane 70, fbc lines 4, cursor 10
[  346.649150] [drm:intel_wait_for_vblank], vblank wait timed out
[  346.701166] [drm:intel_wait_for_vblank], vblank wait timed out
[  346.701477] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  346.701481] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  346.701637] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  346.701640] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  346.701643] [drm:ironlake_fdi_link_train], FDI train done
[  346.701646] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  346.701652] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  346.702874] [drm:intel_update_fbc], 
[  346.755103] [drm:intel_wait_for_vblank], vblank wait timed out
[  346.755414] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  346.756345] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  346.757168] [drm:intel_dp_start_link_train], clock recovery OK
[  346.763024] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  346.763035] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  346.763060] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  346.763999] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  346.764005] [drm:intel_crt_detect], CRT not detected via hotplug
[  346.764010] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  346.765068] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  346.765074] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  346.765080] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  346.765395] [drm:intel_dp_detect], DPCD: 110a840101000000
[  346.766426] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  346.776710] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  346.793856] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  346.820949] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  346.820954] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  346.820959] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  351.818607] [drm:drm_mode_addfb], [FB:108]
[  351.818626] [drm:drm_mode_setcrtc], [CRTC:3]
[  351.818632] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  351.818634] [drm:drm_crtc_helper_set_config], 
[  351.818636] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:108] #connectors=1 (x y) (0 0)
[  351.818640] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  351.818642] [drm:drm_mode_debug_printmodeline], Modeline 108:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
[  351.818644] [drm:drm_mode_debug_printmodeline], Modeline 109:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
[  351.818647] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  351.818650] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  351.818651] [drm:drm_mode_debug_printmodeline], Modeline 109:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
[  351.818655] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 49500KHz
[  351.818657] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  351.818659] [drm:intel_dp_mode_fixup], DP link bw required 118800 available 129600
[  351.818661] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  351.818906] [drm:intel_dp_link_down], 
[  351.889945] [drm:intel_wait_for_vblank], vblank wait timed out
[  351.991902] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  351.995858] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  351.995865] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  351.996276] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6
[  351.996281] [drm:ironlake_check_srwm], watermark 1: display plane 32, fbc lines 3, cursor 6
[  351.996286] [drm:ironlake_check_srwm], watermark 2: display plane 69, fbc lines 4, cursor 10
[  351.996291] [drm:intel_update_fbc], 
[  351.996297] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  351.996302] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  351.996306] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  351.996309] [drm:drm_mode_debug_printmodeline], Modeline 109:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
[  351.996316] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  351.996320] [drm:intel_get_pch_pll], switching PLL c6014 off
[  352.047837] [drm:intel_wait_for_vblank], vblank wait timed out
[  352.047844] [drm:ironlake_update_plane], Writing base 0CA24000 00000000 0 0 3200
[  352.099856] [drm:intel_wait_for_vblank], vblank wait timed out
[  352.099861] [drm:intel_update_fbc], 
[  352.099865] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6
[  352.099870] [drm:ironlake_check_srwm], watermark 1: display plane 32, fbc lines 3, cursor 6
[  352.099875] [drm:ironlake_check_srwm], watermark 2: display plane 69, fbc lines 4, cursor 10
[  352.099881] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:109:800x600]
[  352.099887] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  352.099891] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  352.099896] [drm:ironlake_write_eld], ELD on pipe A
[  352.099900] [drm:ironlake_write_eld], Audio directed to unknown port
[  352.099903] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  352.099917] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6
[  352.099922] [drm:ironlake_check_srwm], watermark 1: display plane 32, fbc lines 3, cursor 6
[  352.099927] [drm:ironlake_check_srwm], watermark 2: display plane 69, fbc lines 4, cursor 10
[  352.151836] [drm:intel_wait_for_vblank], vblank wait timed out
[  352.203767] [drm:intel_wait_for_vblank], vblank wait timed out
[  352.204077] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  352.204081] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  352.204237] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  352.204240] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  352.204243] [drm:ironlake_fdi_link_train], FDI train done
[  352.204247] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  352.204252] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  352.205467] [drm:intel_update_fbc], 
[  352.256747] [drm:intel_wait_for_vblank], vblank wait timed out
[  352.257059] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  352.257989] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  352.258811] [drm:intel_dp_start_link_train], clock recovery OK
[  352.264669] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  352.264690] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  352.264741] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  352.265703] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  352.265710] [drm:intel_crt_detect], CRT not detected via hotplug
[  352.265715] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  352.267707] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  352.267714] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  352.267720] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  352.268034] [drm:intel_dp_detect], DPCD: 110a840101000000
[  352.269066] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  352.277830] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  352.296123] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  352.323188] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  352.323193] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  352.323198] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  357.318410] [drm:drm_mode_addfb], [FB:109]
[  357.318431] [drm:drm_mode_setcrtc], [CRTC:3]
[  357.318437] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  357.318440] [drm:drm_crtc_helper_set_config], 
[  357.318441] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:109] #connectors=1 (x y) (0 0)
[  357.318445] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  357.318447] [drm:drm_mode_debug_printmodeline], Modeline 109:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
[  357.318450] [drm:drm_mode_debug_printmodeline], Modeline 110:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
[  357.318453] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  357.318455] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  357.318457] [drm:drm_mode_debug_printmodeline], Modeline 110:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
[  357.318460] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 40000KHz
[  357.318463] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  357.318465] [drm:intel_dp_mode_fixup], DP link bw required 96000 available 129600
[  357.318467] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  357.318676] [drm:intel_dp_link_down], 
[  357.389589] [drm:intel_wait_for_vblank], vblank wait timed out
[  357.491478] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  357.495519] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  357.495526] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  357.495937] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
[  357.495942] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
[  357.495947] [drm:ironlake_check_srwm], watermark 2: display plane 52, fbc lines 4, cursor 6
[  357.495952] [drm:intel_update_fbc], 
[  357.495958] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  357.495962] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  357.495967] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  357.495970] [drm:drm_mode_debug_printmodeline], Modeline 110:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
[  357.495976] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  357.495980] [drm:intel_get_pch_pll], switching PLL c6014 off
[  357.547521] [drm:intel_wait_for_vblank], vblank wait timed out
[  357.547528] [drm:ironlake_update_plane], Writing base 0CBF9000 00000000 0 0 3200
[  357.599502] [drm:intel_wait_for_vblank], vblank wait timed out
[  357.599507] [drm:intel_update_fbc], 
[  357.599511] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
[  357.599516] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
[  357.599521] [drm:ironlake_check_srwm], watermark 2: display plane 52, fbc lines 4, cursor 6
[  357.599527] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:110:800x600]
[  357.599533] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  357.599538] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  357.599542] [drm:ironlake_write_eld], ELD on pipe A
[  357.599546] [drm:ironlake_write_eld], Audio directed to unknown port
[  357.599550] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  357.599563] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
[  357.599568] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
[  357.599573] [drm:ironlake_check_srwm], watermark 2: display plane 52, fbc lines 4, cursor 6
[  357.651446] [drm:intel_wait_for_vblank], vblank wait timed out
[  357.703413] [drm:intel_wait_for_vblank], vblank wait timed out
[  357.703723] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  357.703727] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  357.703883] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  357.703886] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  357.703889] [drm:ironlake_fdi_link_train], FDI train done
[  357.703892] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  357.703898] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  357.705114] [drm:intel_update_fbc], 
[  357.756432] [drm:intel_wait_for_vblank], vblank wait timed out
[  357.756743] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  357.757666] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  357.758488] [drm:intel_dp_start_link_train], clock recovery OK
[  357.764314] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  357.764384] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  357.764413] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  357.765352] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  357.765358] [drm:intel_crt_detect], CRT not detected via hotplug
[  357.765362] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  357.767326] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  357.767333] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  357.767338] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  357.767653] [drm:intel_dp_detect], DPCD: 110a840101000000
[  357.768683] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  357.780719] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  357.795889] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  357.823210] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  357.823216] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  357.823220] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  362.817023] [drm:drm_mode_addfb], [FB:110]
[  362.817042] [drm:drm_mode_setcrtc], [CRTC:3]
[  362.817046] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  362.817048] [drm:drm_crtc_helper_set_config], 
[  362.817049] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:110] #connectors=1 (x y) (0 0)
[  362.817054] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  362.817055] [drm:drm_mode_debug_printmodeline], Modeline 110:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
[  362.817059] [drm:drm_mode_debug_printmodeline], Modeline 111:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
[  362.817063] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  362.817065] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  362.817067] [drm:drm_mode_debug_printmodeline], Modeline 111:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
[  362.817071] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 36000KHz
[  362.817073] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  362.817075] [drm:intel_dp_mode_fixup], DP link bw required 86400 available 129600
[  362.817078] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  362.817287] [drm:intel_dp_link_down], 
[  362.888190] [drm:intel_wait_for_vblank], vblank wait timed out
[  362.990145] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  362.992113] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  362.992121] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  362.992533] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
[  362.992539] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
[  362.992545] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 4, cursor 6
[  362.992551] [drm:intel_update_fbc], 
[  362.992557] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  362.992562] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  362.992568] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  362.992572] [drm:drm_mode_debug_printmodeline], Modeline 111:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
[  362.992580] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  362.992584] [drm:intel_get_pch_pll], switching PLL c6014 off
[  363.044166] [drm:intel_wait_for_vblank], vblank wait timed out
[  363.044173] [drm:ironlake_update_plane], Writing base 0CDCE000 00000000 0 0 3200
[  363.096147] [drm:intel_wait_for_vblank], vblank wait timed out
[  363.096152] [drm:intel_update_fbc], 
[  363.096156] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
[  363.096161] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
[  363.096166] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 4, cursor 6
[  363.096172] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:111:800x600]
[  363.096177] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  363.096182] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  363.096186] [drm:ironlake_write_eld], ELD on pipe A
[  363.096190] [drm:ironlake_write_eld], Audio directed to unknown port
[  363.096193] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  363.096207] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
[  363.096212] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
[  363.096217] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 4, cursor 6
[  363.148078] [drm:intel_wait_for_vblank], vblank wait timed out
[  363.200055] [drm:intel_wait_for_vblank], vblank wait timed out
[  363.200366] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  363.200369] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  363.200525] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  363.200529] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  363.200532] [drm:ironlake_fdi_link_train], FDI train done
[  363.200535] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  363.200540] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  363.201756] [drm:intel_update_fbc], 
[  363.253033] [drm:intel_wait_for_vblank], vblank wait timed out
[  363.253344] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  363.254268] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  363.255090] [drm:intel_dp_start_link_train], clock recovery OK
[  363.260956] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  363.260987] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  363.261029] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  363.262036] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  363.262042] [drm:intel_crt_detect], CRT not detected via hotplug
[  363.262047] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  363.264003] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  363.264010] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  363.264016] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  363.264330] [drm:intel_dp_detect], DPCD: 110a840101000000
[  363.265362] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  363.278558] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  363.292614] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  363.319878] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  363.319883] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  363.319888] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  368.306743] [drm:drm_mode_addfb], [FB:111]
[  368.306760] [drm:drm_mode_setcrtc], [CRTC:3]
[  368.306764] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  368.306766] [drm:drm_crtc_helper_set_config], 
[  368.306767] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:111] #connectors=1 (x y) (0 0)
[  368.306771] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  368.306773] [drm:drm_mode_debug_printmodeline], Modeline 111:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
[  368.306777] [drm:drm_mode_debug_printmodeline], Modeline 112:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
[  368.306782] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  368.306784] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  368.306786] [drm:drm_mode_debug_printmodeline], Modeline 112:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
[  368.306790] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 27000KHz
[  368.306792] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  368.306795] [drm:intel_dp_mode_fixup], DP link bw required 64800 available 129600
[  368.306803] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  368.307026] [drm:intel_dp_link_down], 
[  368.377838] [drm:intel_wait_for_vblank], vblank wait timed out
[  368.479797] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  368.483859] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  368.483865] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  368.484276] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
[  368.484281] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  368.484286] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
[  368.484290] [drm:intel_update_fbc], 
[  368.484295] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  368.484300] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  368.484304] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  368.484307] [drm:drm_mode_debug_printmodeline], Modeline 112:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
[  368.484314] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  368.484318] [drm:intel_get_pch_pll], switching PLL c6014 off
[  368.535782] [drm:intel_wait_for_vblank], vblank wait timed out
[  368.535790] [drm:ironlake_update_plane], Writing base 0CFA3000 00000000 0 0 2880
[  368.587744] [drm:intel_wait_for_vblank], vblank wait timed out
[  368.587749] [drm:intel_update_fbc], 
[  368.587753] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
[  368.587758] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  368.587763] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
[  368.587769] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:112:720x576]
[  368.587775] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  368.587779] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  368.587783] [drm:ironlake_write_eld], ELD on pipe A
[  368.587787] [drm:ironlake_write_eld], Audio directed to unknown port
[  368.587790] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  368.587804] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
[  368.587809] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  368.587814] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
[  368.639727] [drm:intel_wait_for_vblank], vblank wait timed out
[  368.691747] [drm:intel_wait_for_vblank], vblank wait timed out
[  368.692057] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  368.692061] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  368.692217] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  368.692220] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  368.692223] [drm:ironlake_fdi_link_train], FDI train done
[  368.692226] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  368.692232] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  368.693454] [drm:intel_update_fbc], 
[  368.745654] [drm:intel_wait_for_vblank], vblank wait timed out
[  368.745967] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  368.746892] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  368.747720] [drm:intel_dp_start_link_train], clock recovery OK
[  368.753533] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  368.753538] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  368.753616] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  368.754566] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  368.754573] [drm:intel_crt_detect], CRT not detected via hotplug
[  368.754577] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  368.755638] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  368.755645] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  368.755651] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  368.755966] [drm:intel_dp_detect], DPCD: 110a840101000000
[  368.756995] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  368.773359] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  368.784281] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  368.811759] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  368.811763] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  368.811768] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  373.790527] [drm:drm_mode_addfb], [FB:112]
[  373.790546] [drm:drm_mode_setcrtc], [CRTC:3]
[  373.790549] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  373.790550] [drm:drm_crtc_helper_set_config], 
[  373.790551] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:112] #connectors=1 (x y) (0 0)
[  373.790558] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  373.790560] [drm:drm_mode_debug_printmodeline], Modeline 112:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
[  373.790562] [drm:drm_mode_debug_printmodeline], Modeline 113:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
[  373.790565] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  373.790567] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  373.790569] [drm:drm_mode_debug_printmodeline], Modeline 113:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
[  373.790572] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 33750KHz
[  373.790574] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  373.790576] [drm:intel_dp_mode_fixup], DP link bw required 81000 available 129600
[  373.790577] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  373.790785] [drm:intel_dp_link_down], 
[  373.861531] [drm:intel_wait_for_vblank], vblank wait timed out
[  373.963444] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  373.965406] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  373.965414] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  373.965825] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6
[  373.965831] [drm:ironlake_check_srwm], watermark 1: display plane 23, fbc lines 3, cursor 6
[  373.965837] [drm:ironlake_check_srwm], watermark 2: display plane 48, fbc lines 3, cursor 6
[  373.965843] [drm:intel_update_fbc], 
[  373.965849] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  373.965854] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  373.965859] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  373.965863] [drm:drm_mode_debug_printmodeline], Modeline 113:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
[  373.965871] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  373.965876] [drm:intel_get_pch_pll], switching PLL c6014 off
[  374.017420] [drm:intel_wait_for_vblank], vblank wait timed out
[  374.017427] [drm:ironlake_update_plane], Writing base 0D138000 00000000 0 0 3392
[  374.069445] [drm:intel_wait_for_vblank], vblank wait timed out
[  374.069450] [drm:intel_update_fbc], 
[  374.069454] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6
[  374.069459] [drm:ironlake_check_srwm], watermark 1: display plane 23, fbc lines 3, cursor 6
[  374.069464] [drm:ironlake_check_srwm], watermark 2: display plane 48, fbc lines 3, cursor 6
[  374.069470] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:113:848x480]
[  374.069476] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  374.069480] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  374.069485] [drm:ironlake_write_eld], ELD on pipe A
[  374.069489] [drm:ironlake_write_eld], Audio directed to unknown port
[  374.069492] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  374.069506] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6
[  374.069510] [drm:ironlake_check_srwm], watermark 1: display plane 23, fbc lines 3, cursor 6
[  374.069515] [drm:ironlake_check_srwm], watermark 2: display plane 48, fbc lines 3, cursor 6
[  374.121420] [drm:intel_wait_for_vblank], vblank wait timed out
[  374.173354] [drm:intel_wait_for_vblank], vblank wait timed out
[  374.173664] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  374.173667] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  374.173823] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  374.173827] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  374.173830] [drm:ironlake_fdi_link_train], FDI train done
[  374.173833] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  374.173838] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  374.175053] [drm:intel_update_fbc], 
[  374.226334] [drm:intel_wait_for_vblank], vblank wait timed out
[  374.226645] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  374.227576] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  374.228400] [drm:intel_dp_start_link_train], clock recovery OK
[  374.234255] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  374.234321] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  374.234347] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  374.235285] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  374.235291] [drm:intel_crt_detect], CRT not detected via hotplug
[  374.235296] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  374.237298] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  374.237305] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  374.237311] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  374.237625] [drm:intel_dp_detect], DPCD: 110a840101000000
[  374.238656] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  374.250749] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  374.265937] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  374.293304] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  374.293310] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  374.293315] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  379.273599] [drm:drm_mode_addfb], [FB:113]
[  379.273615] [drm:drm_mode_setcrtc], [CRTC:3]
[  379.273618] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  379.273620] [drm:drm_crtc_helper_set_config], 
[  379.273622] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:113] #connectors=1 (x y) (0 0)
[  379.273626] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  379.273628] [drm:drm_mode_debug_printmodeline], Modeline 113:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
[  379.273632] [drm:drm_mode_debug_printmodeline], Modeline 114:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
[  379.273636] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  379.273638] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  379.273640] [drm:drm_mode_debug_printmodeline], Modeline 114:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
[  379.273644] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 27000KHz
[  379.273647] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  379.273649] [drm:intel_dp_mode_fixup], DP link bw required 64800 available 129600
[  379.273651] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  379.273860] [drm:intel_dp_link_down], 
[  379.344138] [drm:intel_wait_for_vblank], vblank wait timed out
[  379.446098] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  379.448059] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  379.448067] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  379.448479] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
[  379.448485] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  379.448491] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
[  379.448497] [drm:intel_update_fbc], 
[  379.448503] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  379.448508] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  379.448514] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  379.448517] [drm:drm_mode_debug_printmodeline], Modeline 114:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
[  379.448525] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  379.448530] [drm:intel_get_pch_pll], switching PLL c6014 off
[  379.500115] [drm:intel_wait_for_vblank], vblank wait timed out
[  379.500122] [drm:ironlake_update_plane], Writing base 0D2C6000 00000000 0 0 2880
[  379.552050] [drm:intel_wait_for_vblank], vblank wait timed out
[  379.552055] [drm:intel_update_fbc], 
[  379.552058] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
[  379.552064] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  379.552069] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
[  379.552075] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:114:720x480]
[  379.552080] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  379.552085] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  379.552089] [drm:ironlake_write_eld], ELD on pipe A
[  379.552093] [drm:ironlake_write_eld], Audio directed to unknown port
[  379.552097] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  379.552110] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
[  379.552114] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  379.552119] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6
[  379.604027] [drm:intel_wait_for_vblank], vblank wait timed out
[  379.656007] [drm:intel_wait_for_vblank], vblank wait timed out
[  379.656318] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  379.656321] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  379.656477] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  379.656480] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  379.656483] [drm:ironlake_fdi_link_train], FDI train done
[  379.656486] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  379.656492] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  379.657714] [drm:intel_update_fbc], 
[  379.708977] [drm:intel_wait_for_vblank], vblank wait timed out
[  379.709290] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  379.710214] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  379.711037] [drm:intel_dp_start_link_train], clock recovery OK
[  379.716837] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  379.716842] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  379.716921] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  379.717867] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  379.717873] [drm:intel_crt_detect], CRT not detected via hotplug
[  379.717878] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  379.718942] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  379.718948] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  379.718954] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  379.719269] [drm:intel_dp_detect], DPCD: 110a840101000000
[  379.720299] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  379.733410] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  379.747505] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  379.774676] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  379.774681] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  379.774686] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  384.750588] [drm:drm_mode_addfb], [FB:114]
[  384.750606] [drm:drm_mode_setcrtc], [CRTC:3]
[  384.750609] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  384.750611] [drm:drm_crtc_helper_set_config], 
[  384.750612] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:114] #connectors=1 (x y) (0 0)
[  384.750617] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  384.750619] [drm:drm_mode_debug_printmodeline], Modeline 114:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
[  384.750623] [drm:drm_mode_debug_printmodeline], Modeline 115:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
[  384.750627] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  384.750629] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  384.750631] [drm:drm_mode_debug_printmodeline], Modeline 115:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
[  384.750635] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 31500KHz
[  384.750637] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  384.750640] [drm:intel_dp_mode_fixup], DP link bw required 75600 available 129600
[  384.750642] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  384.750850] [drm:intel_dp_link_down], 
[  384.821792] [drm:intel_wait_for_vblank], vblank wait timed out
[  384.923750] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  384.925713] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  384.925721] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  384.926133] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  384.926139] [drm:ironlake_check_srwm], watermark 1: display plane 21, fbc lines 3, cursor 6
[  384.926145] [drm:ironlake_check_srwm], watermark 2: display plane 42, fbc lines 4, cursor 6
[  384.926151] [drm:intel_update_fbc], 
[  384.926157] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  384.926162] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  384.926167] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  384.926171] [drm:drm_mode_debug_printmodeline], Modeline 115:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
[  384.926179] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  384.926184] [drm:intel_get_pch_pll], switching PLL c6014 off
[  384.977768] [drm:intel_wait_for_vblank], vblank wait timed out
[  384.977774] [drm:ironlake_update_plane], Writing base 0D418000 00000000 0 0 2560
[  385.029702] [drm:intel_wait_for_vblank], vblank wait timed out
[  385.029707] [drm:intel_update_fbc], 
[  385.029710] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  385.029715] [drm:ironlake_check_srwm], watermark 1: display plane 21, fbc lines 3, cursor 6
[  385.029721] [drm:ironlake_check_srwm], watermark 2: display plane 42, fbc lines 4, cursor 6
[  385.029726] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:115:640x480]
[  385.029732] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  385.029736] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  385.029740] [drm:ironlake_write_eld], ELD on pipe A
[  385.029744] [drm:ironlake_write_eld], Audio directed to unknown port
[  385.029748] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  385.029761] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  385.029766] [drm:ironlake_check_srwm], watermark 1: display plane 21, fbc lines 3, cursor 6
[  385.029771] [drm:ironlake_check_srwm], watermark 2: display plane 42, fbc lines 4, cursor 6
[  385.081678] [drm:intel_wait_for_vblank], vblank wait timed out
[  385.133659] [drm:intel_wait_for_vblank], vblank wait timed out
[  385.133969] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  385.133973] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  385.134129] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  385.134132] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  385.134135] [drm:ironlake_fdi_link_train], FDI train done
[  385.134138] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  385.134144] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  385.135367] [drm:intel_update_fbc], 
[  385.186678] [drm:intel_wait_for_vblank], vblank wait timed out
[  385.186990] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  385.187914] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  385.188737] [drm:intel_dp_start_link_train], clock recovery OK
[  385.194546] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  385.194552] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  385.194589] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  385.195529] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  385.195535] [drm:intel_crt_detect], CRT not detected via hotplug
[  385.195540] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  385.196603] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  385.196610] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  385.196616] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  385.196930] [drm:intel_dp_detect], DPCD: 110a840101000000
[  385.197962] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  385.207720] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  385.225135] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  385.252433] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  385.252439] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  385.252444] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  390.228344] [drm:drm_mode_addfb], [FB:115]
[  390.228363] [drm:drm_mode_setcrtc], [CRTC:3]
[  390.228367] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  390.228369] [drm:drm_crtc_helper_set_config], 
[  390.228370] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:115] #connectors=1 (x y) (0 0)
[  390.228376] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  390.228378] [drm:drm_mode_debug_printmodeline], Modeline 115:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
[  390.228381] [drm:drm_mode_debug_printmodeline], Modeline 116:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
[  390.228385] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  390.228388] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  390.228390] [drm:drm_mode_debug_printmodeline], Modeline 116:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
[  390.228394] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 31500KHz
[  390.228396] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  390.228399] [drm:intel_dp_mode_fixup], DP link bw required 75600 available 129600
[  390.228401] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  390.228616] [drm:intel_dp_link_down], 
[  390.299444] [drm:intel_wait_for_vblank], vblank wait timed out
[  390.401404] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  390.403365] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  390.403373] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  390.403784] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  390.403790] [drm:ironlake_check_srwm], watermark 1: display plane 21, fbc lines 3, cursor 6
[  390.403796] [drm:ironlake_check_srwm], watermark 2: display plane 42, fbc lines 4, cursor 6
[  390.403802] [drm:intel_update_fbc], 
[  390.403809] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  390.403814] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  390.403820] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  390.403824] [drm:drm_mode_debug_printmodeline], Modeline 116:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
[  390.403832] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  390.403836] [drm:intel_get_pch_pll], switching PLL c6014 off
[  390.455421] [drm:intel_wait_for_vblank], vblank wait timed out
[  390.455428] [drm:ironlake_update_plane], Writing base 0D544000 00000000 0 0 2560
[  390.507354] [drm:intel_wait_for_vblank], vblank wait timed out
[  390.507359] [drm:intel_update_fbc], 
[  390.507363] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  390.507368] [drm:ironlake_check_srwm], watermark 1: display plane 21, fbc lines 3, cursor 6
[  390.507373] [drm:ironlake_check_srwm], watermark 2: display plane 42, fbc lines 4, cursor 6
[  390.507379] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:116:640x480]
[  390.507385] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  390.507389] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  390.507394] [drm:ironlake_write_eld], ELD on pipe A
[  390.507398] [drm:ironlake_write_eld], Audio directed to unknown port
[  390.507401] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  390.507415] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  390.507420] [drm:ironlake_check_srwm], watermark 1: display plane 21, fbc lines 3, cursor 6
[  390.507424] [drm:ironlake_check_srwm], watermark 2: display plane 42, fbc lines 4, cursor 6
[  390.559329] [drm:intel_wait_for_vblank], vblank wait timed out
[  390.611313] [drm:intel_wait_for_vblank], vblank wait timed out
[  390.611623] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  390.611627] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  390.611783] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  390.611786] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  390.611789] [drm:ironlake_fdi_link_train], FDI train done
[  390.611792] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  390.611798] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  390.613018] [drm:intel_update_fbc], 
[  390.664331] [drm:intel_wait_for_vblank], vblank wait timed out
[  390.664542] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  390.665466] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  390.666288] [drm:intel_dp_start_link_train], clock recovery OK
[  390.672090] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  390.672095] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  390.672173] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  390.673114] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  390.673121] [drm:intel_crt_detect], CRT not detected via hotplug
[  390.673126] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  390.674253] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  390.674261] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  390.674267] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  390.674582] [drm:intel_dp_detect], DPCD: 110a840101000000
[  390.675613] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  390.685666] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  390.702788] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  390.730211] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  390.730217] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  390.730222] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  395.706128] [drm:drm_mode_addfb], [FB:116]
[  395.706143] [drm:drm_mode_setcrtc], [CRTC:3]
[  395.706146] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  395.706150] [drm:drm_crtc_helper_set_config], 
[  395.706152] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:116] #connectors=1 (x y) (0 0)
[  395.706155] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  395.706157] [drm:drm_mode_debug_printmodeline], Modeline 116:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
[  395.706160] [drm:drm_mode_debug_printmodeline], Modeline 117:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
[  395.706163] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  395.706164] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  395.706166] [drm:drm_mode_debug_printmodeline], Modeline 117:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
[  395.706169] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 25200KHz
[  395.706171] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  395.706173] [drm:intel_dp_mode_fixup], DP link bw required 60480 available 129600
[  395.706175] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  395.706382] [drm:intel_dp_link_down], 
[  395.777099] [drm:intel_wait_for_vblank], vblank wait timed out
[  395.879056] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  395.883069] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  395.883076] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  395.883486] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  395.883491] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
[  395.883496] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6
[  395.883501] [drm:intel_update_fbc], 
[  395.883506] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  395.883511] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  395.883515] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  395.883518] [drm:drm_mode_debug_printmodeline], Modeline 117:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
[  395.883525] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  395.883528] [drm:intel_get_pch_pll], switching PLL c6014 off
[  395.935031] [drm:intel_wait_for_vblank], vblank wait timed out
[  395.935038] [drm:ironlake_update_plane], Writing base 0D670000 00000000 0 0 2560
[  395.987009] [drm:intel_wait_for_vblank], vblank wait timed out
[  395.987014] [drm:intel_update_fbc], 
[  395.987018] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  395.987023] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
[  395.987028] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6
[  395.987034] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:117:640x480]
[  395.987039] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  395.987044] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  395.987048] [drm:ironlake_write_eld], ELD on pipe A
[  395.987052] [drm:ironlake_write_eld], Audio directed to unknown port
[  395.987055] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  395.987069] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  395.987074] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
[  395.987079] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6
[  396.038987] [drm:intel_wait_for_vblank], vblank wait timed out
[  396.091006] [drm:intel_wait_for_vblank], vblank wait timed out
[  396.091317] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  396.091320] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  396.091476] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  396.091480] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  396.091483] [drm:ironlake_fdi_link_train], FDI train done
[  396.091486] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  396.091491] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  396.092706] [drm:intel_update_fbc], 
[  396.144939] [drm:intel_wait_for_vblank], vblank wait timed out
[  396.145150] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  396.146080] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  396.146903] [drm:intel_dp_start_link_train], clock recovery OK
[  396.152740] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  396.152746] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  396.152825] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  396.153767] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  396.153773] [drm:intel_crt_detect], CRT not detected via hotplug
[  396.153778] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  396.154908] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  396.154915] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  396.154921] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  396.155236] [drm:intel_dp_detect], DPCD: 110a840101000000
[  396.156266] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  396.169288] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  396.183488] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  396.210758] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  396.210763] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  396.210768] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  401.185551] [drm:drm_mode_addfb], [FB:117]
[  401.185566] [drm:drm_mode_setcrtc], [CRTC:3]
[  401.185570] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  401.185572] [drm:drm_crtc_helper_set_config], 
[  401.185573] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:117] #connectors=1 (x y) (0 0)
[  401.185577] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  401.185579] [drm:drm_mode_debug_printmodeline], Modeline 117:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
[  401.185583] [drm:drm_mode_debug_printmodeline], Modeline 118:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
[  401.185587] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  401.185589] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  401.185591] [drm:drm_mode_debug_printmodeline], Modeline 118:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
[  401.185595] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 25175KHz
[  401.185598] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  401.185600] [drm:intel_dp_mode_fixup], DP link bw required 60420 available 129600
[  401.185602] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  401.185810] [drm:intel_dp_link_down], 
[  401.256749] [drm:intel_wait_for_vblank], vblank wait timed out
[  401.358749] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  401.360645] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  401.360652] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  401.361062] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  401.361067] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
[  401.361072] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6
[  401.361077] [drm:intel_update_fbc], 
[  401.361082] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  401.361087] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  401.361091] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  401.361094] [drm:drm_mode_debug_printmodeline], Modeline 118:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
[  401.361101] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  401.361105] [drm:intel_get_pch_pll], switching PLL c6014 off
[  401.412682] [drm:intel_wait_for_vblank], vblank wait timed out
[  401.412689] [drm:ironlake_update_plane], Writing base 0D79C000 00000000 0 0 2560
[  401.464659] [drm:intel_wait_for_vblank], vblank wait timed out
[  401.464665] [drm:intel_update_fbc], 
[  401.464668] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  401.464673] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
[  401.464679] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6
[  401.464684] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:118:640x480]
[  401.464690] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  401.464694] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  401.464699] [drm:ironlake_write_eld], ELD on pipe A
[  401.464703] [drm:ironlake_write_eld], Audio directed to unknown port
[  401.464706] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  401.464719] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  401.464724] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
[  401.464729] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6
[  401.516640] [drm:intel_wait_for_vblank], vblank wait timed out
[  401.568659] [drm:intel_wait_for_vblank], vblank wait timed out
[  401.568969] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  401.568973] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  401.569129] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  401.569132] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  401.569135] [drm:ironlake_fdi_link_train], FDI train done
[  401.569138] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  401.569144] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  401.570366] [drm:intel_update_fbc], 
[  401.622592] [drm:intel_wait_for_vblank], vblank wait timed out
[  401.622903] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  401.623827] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  401.624650] [drm:intel_dp_start_link_train], clock recovery OK
[  401.630511] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  401.630516] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  401.630546] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  401.631486] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  401.631491] [drm:intel_crt_detect], CRT not detected via hotplug
[  401.631496] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  401.632562] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  401.632569] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  401.632575] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  401.632889] [drm:intel_dp_detect], DPCD: 110a840101000000
[  401.633920] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  401.647022] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  401.661299] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  401.688573] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  401.688579] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  401.688583] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  406.663150] [drm:drm_mode_addfb], [FB:118]
[  406.663164] [drm:drm_mode_setcrtc], [CRTC:3]
[  406.663167] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  406.663169] [drm:drm_crtc_helper_set_config], 
[  406.663173] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:118] #connectors=1 (x y) (0 0)
[  406.663176] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  406.663178] [drm:drm_mode_debug_printmodeline], Modeline 118:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
[  406.663181] [drm:drm_mode_debug_printmodeline], Modeline 119:"640x480" 60 25175 640 656 752 800 480 489 492 525 0x40 0xa
[  406.663184] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  406.663185] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  406.663187] [drm:drm_mode_debug_printmodeline], Modeline 119:"640x480" 60 25175 640 656 752 800 480 489 492 525 0x40 0xa
[  406.663190] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 25175KHz
[  406.663192] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  406.663194] [drm:intel_dp_mode_fixup], DP link bw required 60420 available 129600
[  406.663196] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  406.663404] [drm:intel_dp_link_down], 
[  406.734402] [drm:intel_wait_for_vblank], vblank wait timed out
[  406.836402] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  406.838298] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  406.838304] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  406.838715] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  406.838720] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
[  406.838725] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6
[  406.838730] [drm:intel_update_fbc], 
[  406.838735] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  406.838739] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  406.838744] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  406.838747] [drm:drm_mode_debug_printmodeline], Modeline 119:"640x480" 60 25175 640 656 752 800 480 489 492 525 0x40 0xa
[  406.838753] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  406.838757] [drm:intel_get_pch_pll], switching PLL c6014 off
[  406.890336] [drm:intel_wait_for_vblank], vblank wait timed out
[  406.890342] [drm:ironlake_update_plane], Writing base 0D8C8000 00000000 0 0 2560
[  406.942312] [drm:intel_wait_for_vblank], vblank wait timed out
[  406.942317] [drm:intel_update_fbc], 
[  406.942321] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  406.942326] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
[  406.942332] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6
[  406.942337] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:119:640x480]
[  406.942343] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  406.942347] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  406.942352] [drm:ironlake_write_eld], ELD on pipe A
[  406.942356] [drm:ironlake_write_eld], Audio directed to unknown port
[  406.942359] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  406.942372] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
[  406.942377] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
[  406.942382] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6
[  406.994292] [drm:intel_wait_for_vblank], vblank wait timed out
[  407.046315] [drm:intel_wait_for_vblank], vblank wait timed out
[  407.046626] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  407.046629] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  407.046785] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  407.046789] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  407.046792] [drm:ironlake_fdi_link_train], FDI train done
[  407.046795] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  407.046800] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  407.048022] [drm:intel_update_fbc], 
[  407.100245] [drm:intel_wait_for_vblank], vblank wait timed out
[  407.100455] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  407.101387] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  407.102208] [drm:intel_dp_start_link_train], clock recovery OK
[  407.108045] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  407.108051] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  407.108128] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  407.109071] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  407.109077] [drm:intel_crt_detect], CRT not detected via hotplug
[  407.109082] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  407.110212] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  407.110219] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  407.110224] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  407.110539] [drm:intel_dp_detect], DPCD: 110a840101000000
[  407.111571] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  407.124559] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  407.138815] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  407.165868] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  407.165873] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  407.165878] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  412.137412] [drm:drm_mode_addfb], [FB:119]
[  412.137431] [drm:drm_mode_setcrtc], [CRTC:3]
[  412.137435] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1]
[  412.137440] [drm:drm_crtc_helper_set_config], 
[  412.137441] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:119] #connectors=1 (x y) (0 0)
[  412.137446] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  412.137448] [drm:drm_mode_debug_printmodeline], Modeline 119:"640x480" 60 25175 640 656 752 800 480 489 492 525 0x40 0xa
[  412.137450] [drm:drm_mode_debug_printmodeline], Modeline 120:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
[  412.137454] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  412.137456] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  412.137457] [drm:drm_mode_debug_printmodeline], Modeline 120:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
[  412.137461] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 28320KHz
[  412.137463] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24
[  412.137465] [drm:intel_dp_mode_fixup], DP link bw required 67968 available 129600
[  412.137467] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  412.137676] [drm:intel_dp_link_down], 
[  412.208060] [drm:intel_wait_for_vblank], vblank wait timed out
[  412.310016] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  412.311978] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  412.311986] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  412.312398] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
[  412.312404] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  412.312411] [drm:ironlake_check_srwm], watermark 2: display plane 40, fbc lines 3, cursor 6
[  412.312416] [drm:intel_update_fbc], 
[  412.312424] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  412.312429] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  412.312435] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  412.312439] [drm:drm_mode_debug_printmodeline], Modeline 120:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
[  412.312447] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
[  412.312451] [drm:intel_get_pch_pll], switching PLL c6014 off
[  412.364037] [drm:intel_wait_for_vblank], vblank wait timed out
[  412.364044] [drm:ironlake_update_plane], Writing base 0D9F4000 00000000 0 0 2880
[  412.416014] [drm:intel_wait_for_vblank], vblank wait timed out
[  412.416019] [drm:intel_update_fbc], 
[  412.416024] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
[  412.416029] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  412.416034] [drm:ironlake_check_srwm], watermark 2: display plane 40, fbc lines 3, cursor 6
[  412.416040] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:120:720x400]
[  412.416046] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  412.416050] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  412.416055] [drm:ironlake_write_eld], ELD on pipe A
[  412.416059] [drm:ironlake_write_eld], Audio directed to unknown port
[  412.416062] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  412.416076] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
[  412.416081] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6
[  412.416085] [drm:ironlake_check_srwm], watermark 2: display plane 40, fbc lines 3, cursor 6
[  412.467945] [drm:intel_wait_for_vblank], vblank wait timed out
[  412.519926] [drm:intel_wait_for_vblank], vblank wait timed out
[  412.520236] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  412.520239] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  412.520395] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  412.520399] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  412.520402] [drm:ironlake_fdi_link_train], FDI train done
[  412.520405] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  412.520410] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  412.521625] [drm:intel_update_fbc], 
[  412.572943] [drm:intel_wait_for_vblank], vblank wait timed out
[  412.573255] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  412.574077] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  412.574899] [drm:intel_dp_start_link_train], clock recovery OK
[  412.580714] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  412.580721] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  412.580745] [drm:i915_hotplug_work_func], running encoder hotplug functions
[  412.581683] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
[  412.581689] [drm:intel_crt_detect], CRT not detected via hotplug
[  412.581694] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2
[  412.582872] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  412.582879] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  412.582885] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2
[  412.583200] [drm:intel_dp_detect], DPCD: 110a840101000000
[  412.584231] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  412.594808] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[  412.611501] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  412.638879] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
[  412.638885] [drm:drm_detect_monitor_audio], Monitor has basic audio support
[  412.638889] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1
[  417.578737] [drm:drm_crtc_helper_set_config], 
[  417.578742] [drm:drm_crtc_helper_set_config], [CRTC:3] [NOFB]
[  417.578958] [drm:intel_dp_link_down], 
[  417.597747] [drm:ironlake_crtc_dpms], crtc 0/0 dpms off
[  417.597754] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[  417.649727] [drm:intel_wait_for_vblank], vblank wait timed out
[  417.751725] [drm:intel_wait_for_pipe_off], pipe_off wait timed out
[  417.755695] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
[  417.755702] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
[  417.756112] [drm:intel_update_fbc], 
[  417.756122] [drm:drm_mode_setcrtc], [CRTC:3]
[  417.756125] [drm:drm_mode_setcrtc], Count connectors is 1 but no mode or fb set
[  417.871440] [drm:drm_crtc_helper_set_config], 
[  417.871442] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:17] #connectors=1 (x y) (0 0)
[  417.871448] [drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
[  417.871449] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[  417.871451] [drm:drm_mode_debug_printmodeline], Modeline 120:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
[  417.871454] [drm:drm_mode_debug_printmodeline], Modeline 16:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
[  417.871457] [drm:drm_crtc_helper_set_config], encoder changed, full mode switch
[  417.871459] [drm:drm_crtc_helper_set_config], crtc changed, full mode switch
[  417.871461] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3]
[  417.871462] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[  417.871464] [drm:drm_mode_debug_printmodeline], Modeline 16:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
[  417.871469] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
[  417.871472] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 2 clock 270000 bpp 24
[  417.871473] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 432000
[  417.871475] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[  417.871694] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
[  417.871696] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[  417.871698] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
[  417.871699] [drm:drm_mode_debug_printmodeline], Modeline 16:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
[  417.871702] [drm:intel_get_pch_pll], CRTC:3 allocated PCH PLL c6014
[  417.871704] [drm:intel_get_pch_pll], using pll 0 for pipe 0
[  417.871705] [drm:intel_get_pch_pll], switching PLL c6014 off
[  417.923640] [drm:intel_wait_for_vblank], vblank wait timed out
[  417.923649] [drm:ironlake_update_plane], Writing base 00043000 00000000 0 0 7680
[  417.923657] [drm:intel_update_fbc], 
[  417.923661] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
[  417.923667] [drm:ironlake_check_srwm], watermark 1: display plane 94, fbc lines 3, cursor 6
[  417.923674] [drm:ironlake_check_srwm], watermark 2: display plane 209, fbc lines 4, cursor 10
[  417.923681] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:16:1920x1200]
[  417.923688] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
[  417.923693] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14]
[  417.923699] [drm:ironlake_write_eld], ELD on pipe A
[  417.923704] [drm:ironlake_write_eld], Audio directed to unknown port
[  417.923708] [drm:ironlake_write_eld], ELD: DisplayPort detected
[  417.923723] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
[  417.923728] [drm:ironlake_check_srwm], watermark 1: display plane 94, fbc lines 3, cursor 6
[  417.923734] [drm:ironlake_check_srwm], watermark 2: display plane 209, fbc lines 4, cursor 10
[  417.975585] [drm:intel_wait_for_vblank], vblank wait timed out
[  418.027561] [drm:intel_wait_for_vblank], vblank wait timed out
[  418.027872] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[  418.027875] [drm:ironlake_fdi_link_train], FDI train 1 done.
[  418.028032] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[  418.028035] [drm:ironlake_fdi_link_train], FDI train 2 done.
[  418.028038] [drm:ironlake_fdi_link_train], FDI train done
[  418.028041] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
[  418.028047] [drm:intel_enable_pch_pll], enabling PCH PLL c6014
[  418.029261] [drm:intel_update_fbc], 
[  418.080584] [drm:intel_wait_for_vblank], vblank wait timed out
[  418.080794] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
[  418.081718] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000
[  418.082546] [drm:intel_dp_start_link_train], clock recovery OK
[  418.088360] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[  418.088368] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:13:DP-1] set DPMS on
[  418.088382] [drm:drm_crtc_helper_set_config], 
[  418.088385] [drm:drm_crtc_helper_set_config], [CRTC:5] [NOFB]
[  418.104907] [drm:intel_prepare_page_flip], preparing flip with no unpin work?