From b812c9d98defac9554630a0553e6301b363bec05 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 10 May 2012 12:18:04 +0100 Subject: [PATCH] agp/intel: Insert a write barrier before flushing the chipset This is required if the backend performs no serialising of its own, such as gen3+. References: https://bugs.freedesktop.org/show_bug.cgi?id=21442 Signed-off-by: Chris Wilson --- drivers/char/agp/intel-gtt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index 1237e75..8dfc5e6 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -1574,6 +1574,7 @@ EXPORT_SYMBOL(intel_gtt_get); void intel_gtt_chipset_flush(void) { + wmb(); if (intel_private.driver->chipset_flush) intel_private.driver->chipset_flush(); } -- 1.7.10