From 004ae3bec31b25b890f20adca10f39ae304e4884 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Sun, 13 May 2012 20:16:01 +0200 Subject: [PATCH] debug patch v2 --- drivers/gpu/drm/i915/intel_display.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fb05d9d..70087e2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4034,6 +4034,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, else dspcntr |= DISPPLANE_SEL_PIPE_B; + printk("modeset on pipe %i, plane %i\n", pipe, plane); + if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { /* Enable pixel doubling when the dot clock is > 90% of the (display) * core speed. @@ -6257,9 +6259,10 @@ static void intel_sanitize_modesetting(struct drm_device *dev, { struct drm_i915_private *dev_priv = dev->dev_private; u32 reg, val; + int i; /* Clear any frame start delays used for debugging left by the BIOS */ - for_each_pipe(pipe) { + for_each_pipe(i) { reg = PIPECONF(pipe); I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); } @@ -6281,6 +6284,8 @@ static void intel_sanitize_modesetting(struct drm_device *dev, reg = DSPCNTR(plane); val = I915_READ(reg); + printk("sanitize modeset on pipe %i, plane %i, dspcntr: 0x%08x\n", pipe, plane, val); + if ((val & DISPLAY_PLANE_ENABLE) == 0) return; if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) @@ -6288,6 +6293,7 @@ static void intel_sanitize_modesetting(struct drm_device *dev, /* This display plane is active and attached to the other CPU pipe. */ pipe = !pipe; + printk("pipe wired up wrongly, disabling pipe %i, plane %i\n", pipe, plane); /* Disable the plane and wait for it to stop reading from the pipe. */ intel_disable_plane(dev_priv, plane, pipe); -- 1.7.10