call void @llvm.AMDGPU.store.output(float %4, i32 8) call void @llvm.AMDGPU.store.output(float %5, i32 9) call void @llvm.AMDGPU.store.output(float %6, i32 10) call void @llvm.AMDGPU.store.output(float %7, i32 11) ret void } declare void @llvm.AMDGPU.reserve.reg(i32) declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T1_X in %vreg0, %T1_Y in %vreg1, %T1_Z in %vreg2, %T1_W in %vreg3, %T2_X in %vreg4, %T2_Y in %vreg5, %T2_Z in %vreg6, %T2_W in %vreg7 Function Live Outs: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W BB#0: derived from LLVM BB %main_body Live Ins: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W RETURN %T1_X, %T1_Y, %T1_Z, %T1_W, %T2_X, %T2_Y, %T2_Z, %T2_W # End machine code for function main. bytecode 6 dw -- 3 gprs --------------------- 7 0000 00000000 CF ADDR:0 0001 89800000 CF INST:0x13 COND:0 POP_COUNT:0 0002 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1 0003 94000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:0 0004 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2 0005 94200688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) ret void } declare float @llvm.R600.load.input(i32) readnone # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body RETURN # End machine code for function main. bytecode 2 dw -- 1 gprs --------------------- 7 0000 C0000000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0 0001 94200FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ fixme:heap:HeapSetInformation (nil) 1 (nil) 0 fixme:win:EnumDisplayDevicesW ((null),0,0x32eaf8,0x00000000), stub! -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 88CD1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 D88D1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:1 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 988D1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:0 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.reserve.reg(i32 0) call void @llvm.AMDGPU.reserve.reg(i32 1) call void @llvm.AMDGPU.reserve.reg(i32 2) call void @llvm.AMDGPU.reserve.reg(i32 3) %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) call void @llvm.AMDGPU.store.output(float %0, i32 4) call void @llvm.AMDGPU.store.output(float %1, i32 5) call void @llvm.AMDGPU.store.output(float %2, i32 6) call void @llvm.AMDGPU.store.output(float %3, i32 7) call void @llvm.AMDGPU.store.output(float %4, i32 8) call void @llvm.AMDGPU.store.output(float %5, i32 9) call void @llvm.AMDGPU.store.output(float %6, i32 10) call void @llvm.AMDGPU.store.output(float %7, i32 11) ret void } declare void @llvm.AMDGPU.reserve.reg(i32) declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T1_X in %vreg0, %T1_Y in %vreg1, %T1_Z in %vreg2, %T1_W in %vreg3, %T2_X in %vreg4, %T2_Y in %vreg5, %T2_Z in %vreg6, %T2_W in %vreg7 Function Live Outs: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W BB#0: derived from LLVM BB %main_body Live Ins: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W RETURN %T1_X, %T1_Y, %T1_Z, %T1_W, %T2_X, %T2_Y, %T2_Z, %T2_W # End machine code for function main. bytecode 6 dw -- 3 gprs --------------------- 7 0000 00000000 CF ADDR:0 0001 89800000 CF INST:0x13 COND:0 POP_COUNT:0 0002 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1 0003 94000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:0 0004 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2 0005 94200688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) ret void } declare float @llvm.R600.load.input(i32) readnone # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body RETURN # End machine code for function main. bytecode 2 dw -- 1 gprs --------------------- 7 0000 C0000000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0 0001 94200FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ err:wgl:X11DRV_wglGetPixelFormatAttribivARB (0x354): unexpected iPixelFormat(0) vs nFormats(175), returns FALSE -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 88CD1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 D88D1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:1 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 988D1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:0 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.reserve.reg(i32 0) call void @llvm.AMDGPU.reserve.reg(i32 1) call void @llvm.AMDGPU.reserve.reg(i32 2) call void @llvm.AMDGPU.reserve.reg(i32 3) %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) call void @llvm.AMDGPU.store.output(float %0, i32 4) call void @llvm.AMDGPU.store.output(float %1, i32 5) call void @llvm.AMDGPU.store.output(float %2, i32 6) call void @llvm.AMDGPU.store.output(float %3, i32 7) call void @llvm.AMDGPU.store.output(float %4, i32 8) call void @llvm.AMDGPU.store.output(float %5, i32 9) call void @llvm.AMDGPU.store.output(float %6, i32 10) call void @llvm.AMDGPU.store.output(float %7, i32 11) ret void } declare void @llvm.AMDGPU.reserve.reg(i32) declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T1_X in %vreg0, %T1_Y in %vreg1, %T1_Z in %vreg2, %T1_W in %vreg3, %T2_X in %vreg4, %T2_Y in %vreg5, %T2_Z in %vreg6, %T2_W in %vreg7 Function Live Outs: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W BB#0: derived from LLVM BB %main_body Live Ins: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W RETURN %T1_X, %T1_Y, %T1_Z, %T1_W, %T2_X, %T2_Y, %T2_Z, %T2_W # End machine code for function main. bytecode 6 dw -- 3 gprs --------------------- 7 0000 00000000 CF ADDR:0 0001 89800000 CF INST:0x13 COND:0 POP_COUNT:0 0002 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1 0003 94000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:0 0004 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2 0005 94200688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) ret void } declare float @llvm.R600.load.input(i32) readnone # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body RETURN # End machine code for function main. bytecode 2 dw -- 1 gprs --------------------- 7 0000 C0000000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0 0001 94200FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ fixme:win:EnumDisplayDevicesW ((null),0,0x32e4cc,0x00000000), stub! fixme:win:EnumDisplayDevicesW ((null),1,0x32e4cc,0x00000000), stub! fixme:win:EnumDisplayDevicesW ((null),0,0x32eca0,0x00000000), stub! -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 88CD1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 D88D1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:1 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 988D1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:0 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.reserve.reg(i32 0) call void @llvm.AMDGPU.reserve.reg(i32 1) call void @llvm.AMDGPU.reserve.reg(i32 2) call void @llvm.AMDGPU.reserve.reg(i32 3) %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) call void @llvm.AMDGPU.store.output(float %0, i32 4) call void @llvm.AMDGPU.store.output(float %1, i32 5) call void @llvm.AMDGPU.store.output(float %2, i32 6) call void @llvm.AMDGPU.store.output(float %3, i32 7) call void @llvm.AMDGPU.store.output(float %4, i32 8) call void @llvm.AMDGPU.store.output(float %5, i32 9) call void @llvm.AMDGPU.store.output(float %6, i32 10) call void @llvm.AMDGPU.store.output(float %7, i32 11) ret void } declare void @llvm.AMDGPU.reserve.reg(i32) declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T1_X in %vreg0, %T1_Y in %vreg1, %T1_Z in %vreg2, %T1_W in %vreg3, %T2_X in %vreg4, %T2_Y in %vreg5, %T2_Z in %vreg6, %T2_W in %vreg7 Function Live Outs: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W BB#0: derived from LLVM BB %main_body Live Ins: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W RETURN %T1_X, %T1_Y, %T1_Z, %T1_W, %T2_X, %T2_Y, %T2_Z, %T2_W # End machine code for function main. bytecode 6 dw -- 3 gprs --------------------- 7 0000 00000000 CF ADDR:0 0001 89800000 CF INST:0x13 COND:0 POP_COUNT:0 0002 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1 0003 94000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:0 0004 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2 0005 94200688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) ret void } declare float @llvm.R600.load.input(i32) readnone # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body RETURN # End machine code for function main. bytecode 2 dw -- 1 gprs --------------------- 7 0000 C0000000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0 0001 94200FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ err:wgl:X11DRV_wglGetPixelFormatAttribivARB (0x370): unexpected iPixelFormat(0) vs nFormats(175), returns FALSE -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 88CD1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 D88D1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:1 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 988D1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:0 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.reserve.reg(i32 0) call void @llvm.AMDGPU.reserve.reg(i32 1) call void @llvm.AMDGPU.reserve.reg(i32 2) call void @llvm.AMDGPU.reserve.reg(i32 3) %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) call void @llvm.AMDGPU.store.output(float %0, i32 4) call void @llvm.AMDGPU.store.output(float %1, i32 5) call void @llvm.AMDGPU.store.output(float %2, i32 6) call void @llvm.AMDGPU.store.output(float %3, i32 7) call void @llvm.AMDGPU.store.output(float %4, i32 8) call void @llvm.AMDGPU.store.output(float %5, i32 9) call void @llvm.AMDGPU.store.output(float %6, i32 10) call void @llvm.AMDGPU.store.output(float %7, i32 11) ret void } declare void @llvm.AMDGPU.reserve.reg(i32) declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T1_X in %vreg0, %T1_Y in %vreg1, %T1_Z in %vreg2, %T1_W in %vreg3, %T2_X in %vreg4, %T2_Y in %vreg5, %T2_Z in %vreg6, %T2_W in %vreg7 Function Live Outs: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W BB#0: derived from LLVM BB %main_body Live Ins: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W RETURN %T1_X, %T1_Y, %T1_Z, %T1_W, %T2_X, %T2_Y, %T2_Z, %T2_W # End machine code for function main. bytecode 6 dw -- 3 gprs --------------------- 7 0000 00000000 CF ADDR:0 0001 89800000 CF INST:0x13 COND:0 POP_COUNT:0 0002 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1 0003 94000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:0 0004 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2 0005 94200688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) ret void } declare float @llvm.R600.load.input(i32) readnone # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body RETURN # End machine code for function main. bytecode 2 dw -- 1 gprs --------------------- 7 0000 C0000000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0 0001 94200FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ fixme:win:EnumDisplayDevicesW ((null),0,0xf0e294,0x00000000), stub! -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 88CD1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 D88D1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:1 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 988D1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:0 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.reserve.reg(i32 0) call void @llvm.AMDGPU.reserve.reg(i32 1) call void @llvm.AMDGPU.reserve.reg(i32 2) call void @llvm.AMDGPU.reserve.reg(i32 3) %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) call void @llvm.AMDGPU.store.output(float %0, i32 4) call void @llvm.AMDGPU.store.output(float %1, i32 5) call void @llvm.AMDGPU.store.output(float %2, i32 6) call void @llvm.AMDGPU.store.output(float %3, i32 7) call void @llvm.AMDGPU.store.output(float %4, i32 8) call void @llvm.AMDGPU.store.output(float %5, i32 9) call void @llvm.AMDGPU.store.output(float %6, i32 10) call void @llvm.AMDGPU.store.output(float %7, i32 11) ret void } declare void @llvm.AMDGPU.reserve.reg(i32) declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T1_X in %vreg0, %T1_Y in %vreg1, %T1_Z in %vreg2, %T1_W in %vreg3, %T2_X in %vreg4, %T2_Y in %vreg5, %T2_Z in %vreg6, %T2_W in %vreg7 Function Live Outs: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W BB#0: derived from LLVM BB %main_body Live Ins: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W RETURN %T1_X, %T1_Y, %T1_Z, %T1_W, %T2_X, %T2_Y, %T2_Z, %T2_W # End machine code for function main. bytecode 6 dw -- 3 gprs --------------------- 7 0000 00000000 CF ADDR:0 0001 89800000 CF INST:0x13 COND:0 POP_COUNT:0 0002 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1 0003 94000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:0 0004 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2 0005 94200688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) ret void } declare float @llvm.R600.load.input(i32) readnone # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body RETURN # End machine code for function main. bytecode 2 dw -- 1 gprs --------------------- 7 0000 C0000000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0 0001 94200FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ err:wgl:X11DRV_wglGetPixelFormatAttribivARB (0x370): unexpected iPixelFormat(0) vs nFormats(175), returns FALSE -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 88CD1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 D88D1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:1 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- bytecode 12 dw -- 0 gprs --------------------- 7 0000 00000002 TEX/VTX ADDR:4 0001 81000400 TEX/VTX INST:0x2 COUNT:2 0004 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0005 88CD1001 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1) 0006 00080000 ENDIAN:0 OFFSET:0 0007 00000000 0008 7C00A000 INST:0 FETCH_TYPE:0 BUFFER_ID:160 0009 988D1002 SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:0 MODE:1) 0010 00080010 ENDIAN:0 OFFSET:16 0011 00000000 0002 00000000 CF ADDR:0 0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.reserve.reg(i32 0) call void @llvm.AMDGPU.reserve.reg(i32 1) call void @llvm.AMDGPU.reserve.reg(i32 2) call void @llvm.AMDGPU.reserve.reg(i32 3) %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) call void @llvm.AMDGPU.store.output(float %0, i32 4) call void @llvm.AMDGPU.store.output(float %1, i32 5) call void @llvm.AMDGPU.store.output(float %2, i32 6) call void @llvm.AMDGPU.store.output(float %3, i32 7) call void @llvm.AMDGPU.store.output(float %4, i32 8) call void @llvm.AMDGPU.store.output(float %5, i32 9) call void @llvm.AMDGPU.store.output(float %6, i32 10) call void @llvm.AMDGPU.store.output(float %7, i32 11) ret void } declare void @llvm.AMDGPU.reserve.reg(i32) declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T1_X in %vreg0, %T1_Y in %vreg1, %T1_Z in %vreg2, %T1_W in %vreg3, %T2_X in %vreg4, %T2_Y in %vreg5, %T2_Z in %vreg6, %T2_W in %vreg7 Function Live Outs: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W BB#0: derived from LLVM BB %main_body Live Ins: %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W RETURN %T1_X, %T1_Y, %T1_Z, %T1_W, %T2_X, %T2_Y, %T2_Z, %T2_W # End machine code for function main. bytecode 6 dw -- 3 gprs --------------------- 7 0000 00000000 CF ADDR:0 0001 89800000 CF INST:0x13 COND:0 POP_COUNT:0 0002 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1 0003 94000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:0 0004 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2 0005 94200688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) ret void } declare float @llvm.R600.load.input(i32) readnone # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body RETURN # End machine code for function main. bytecode 2 dw -- 1 gprs --------------------- 7 0000 C0000000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0 0001 94200FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV_SAT OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = call float @llvm.AMDIL.clamp.(float %0, float 0.000000e+00, float 1.000000e+00) %5 = call float @llvm.AMDIL.clamp.(float %1, float 0.000000e+00, float 1.000000e+00) %6 = call float @llvm.AMDIL.clamp.(float %2, float 0.000000e+00, float 1.000000e+00) %7 = call float @llvm.AMDIL.clamp.(float %3, float 0.000000e+00, float 1.000000e+00) call void @llvm.AMDGPU.store.output(float %4, i32 0) call void @llvm.AMDGPU.store.output(float %5, i32 1) call void @llvm.AMDGPU.store.output(float %6, i32 2) call void @llvm.AMDGPU.store.output(float %7, i32 3) ret void } declare float @llvm.R600.load.input(i32) readnone declare float @llvm.AMDIL.clamp.(float, float, float) readnone declare void @llvm.AMDGPU.store.output(float, i32) # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T0_X in %vreg0, %T0_Y in %vreg2, %T0_Z in %vreg4, %T0_W in %vreg6 Function Live Outs: %T0_X %T0_Y %T0_Z %T0_W BB#0: derived from LLVM BB %main_body Live Ins: %T0_X %T0_Y %T0_Z %T0_W %T0_X[TF=1] = MOV %T0_X %T0_Y[TF=1] = MOV %T0_Y %T0_Z[TF=1] = MOV %T0_Z %T0_W[TF=1] = MOV %T0_W RETURN %T0_X, %T0_Y, %T0_Z, %T0_W # End machine code for function main. bytecode 12 dw -- 1 gprs --------------------- 7 0000 00000002 ALU ADDR:4 KCACHE_MODE0:0 KCACHE_BANK0:0 KCACHE_BANK1:0 0001 A00C0000 ALU INST:0x8 KCACHE_MODE1:0 KCACHE_ADDR0:0 KCACHE_ADDR1:0 COUNT:4 0004 00000000 SRC0(SEL:0 REL:0 CHAN:0 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) LAST:0) 0005 80000C90 INST:0x19 DST(SEL:0 CHAN:0 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0 0006 00000400 SRC0(SEL:0 REL:0 CHAN:1 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) LAST:0) 0007 A0000C90 INST:0x19 DST(SEL:0 CHAN:1 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0 0008 00000800 SRC0(SEL:0 REL:0 CHAN:2 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) LAST:0) 0009 C0000C90 INST:0x19 DST(SEL:0 CHAN:2 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0 0010 80000C00 SRC0(SEL:0 REL:0 CHAN:3 NEG:0) SRC1(SEL:0 REL:0 CHAN:0 NEG:0 IM:0) LAST:1) 0011 E0000C90 * INST:0x19 DST(SEL:0 CHAN:3 REL:0 CLAMP:1) BANK_SWIZZLE:0 SRC0_ABS:0 SRC1_ABS:0 WRITE_MASK:1 OMOD:0 EXECUTE_MASK:0 UPDATE_PRED:0 0002 C0000000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0 0003 94200688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV_SAT OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.reserve.reg(i32 0) call void @llvm.AMDGPU.reserve.reg(i32 1) call void @llvm.AMDGPU.reserve.reg(i32 2) call void @llvm.AMDGPU.reserve.reg(i32 3) %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = call float @llvm.AMDGPU.load.const(i32 0) %9 = call float @llvm.AMDGPU.mul(float %0, float %8) %10 = call float @llvm.AMDGPU.load.const(i32 1) %11 = call float @llvm.AMDGPU.mul(float %0, float %10) %12 = call float @llvm.AMDGPU.load.const(i32 2) %13 = call float @llvm.AMDGPU.mul(float %0, float %12) %14 = call float @llvm.AMDGPU.load.const(i32 3) %15 = call float @llvm.AMDGPU.mul(float %0, float %14) %16 = call float @llvm.AMDGPU.load.const(i32 4) %17 = call float @llvm.AMDIL.mad.(float %1, float %16, float %9) %18 = call float @llvm.AMDGPU.load.const(i32 5) %19 = call float @llvm.AMDIL.mad.(float %1, float %18, float %11) %20 = call float @llvm.AMDGPU.load.const(i32 6) %21 = call float @llvm.AMDIL.mad.(float %1, float %20, float %13) %22 = call float @llvm.AMDGPU.load.const(i32 7) %23 = call float @llvm.AMDIL.mad.(float %1, float %22, float %15) %24 = call float @llvm.AMDGPU.load.const(i32 8) %25 = call float @llvm.AMDIL.mad.(float %2, float %24, float %17) %26 = call float @llvm.AMDGPU.load.const(i32 9) %27 = call float @llvm.AMDIL.mad.(float %2, float %26, float %19) %28 = call float @llvm.AMDGPU.load.const(i32 10) %29 = call float @llvm.AMDIL.mad.(float %2, float %28, float %21) %30 = call float @llvm.AMDGPU.load.const(i32 11) %31 = call float @llvm.AMDIL.mad.(float %2, float %30, float %23) %32 = call float @llvm.AMDGPU.load.const(i32 12) %33 = call float @llvm.AMDIL.mad.(float %3, float %32, float %25) %34 = call float @llvm.AMDGPU.load.const(i32 13) %35 = call float @llvm.AMDIL.mad.(float %3, float %34, float %27) %36 = call float @llvm.AMDGPU.load.const(i32 14) %37 = call float @llvm.AMDIL.mad.(float %3, float %36, float %29) %38 = call float @llvm.AMDGPU.load.const(i32 15) %39 = call float @llvm.AMDIL.mad.(float %3, float %38, float %31) %40 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00) %41 = call float @llvm.AMDIL.clamp.(float %5, float 0.000000e+00, float 1.000000e+00) %42 = call float @llvm.AMDIL.clamp.(float %6, float 0.000000e+00, float 1.000000e+00) %43 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00) call void @llvm.AMDGPU.store.output(float %33, i32 4) call void @llvm.AMDGPU.store.output(float %35, i32 5) call void @llvm.AMDGPU.store.output(float %37, i32 6) call void @llvm.AMDGPU.store.output(float %39, i32 7) call void @llvm.AMDGPU.store.output(float %40, i32 8) call void @llvm.AMDGPU.store.output(float %41, i32 9) call void @llvm.AMDGPU.store.output(float %42, i32 10) call void @llvm.AMDGPU.store.output(float %43, i32 11) ret void } declare void @llvm.AMDGPU.reserve.reg(i32) declare float @llvm.R600.load.input(i32) readnone declare float @llvm.AMDGPU.load.const(i32) readnone declare float @llvm.AMDGPU.mul(float, float) readnone declare float @llvm.AMDIL.mad.(float, float, float) readnone declare float @llvm.AMDIL.clamp.(float, float, float) readnone declare void @llvm.AMDGPU.store.output(float, i32) Stack dump: 0. Running pass 'Function Pass Manager' on module 'tgsi'. 1. Running pass 'Post-RA pseudo instruction expansion pass' on function '@main' wine: Unhandled page fault on read access to 0xffffffff at address 0x7c91c9f4 (thread 0023), starting debugger...