[ 251.766066] [drm:ironlake_write_eld], Audio directed to unknown port [ 251.766068] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 251.766082] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6 [ 251.766086] [drm:ironlake_check_srwm], watermark 1: display plane 43, fbc lines 3, cursor 6 [ 251.766090] [drm:ironlake_check_srwm], watermark 2: display plane 94, fbc lines 4, cursor 10 [ 251.818006] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 251.869980] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 251.870289] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 251.870290] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 251.870444] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 251.870445] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 251.870446] [drm:ironlake_fdi_link_train], FDI train done [ 251.870447] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 251.870449] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 251.871661] [drm:intel_update_fbc], [ 251.922959] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 251.923269] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 251.924190] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 251.925011] [drm:intel_dp_start_link_train], clock recovery OK [ 251.930805] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 251.930806] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 251.930819] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 251.931749] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 251.931750] [drm:intel_crt_detect], CRT not detected via hotplug [ 251.931752] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 251.932919] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 251.932923] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 251.932929] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 251.933240] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 251.934266] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 251.947293] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 251.961388] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 251.988456] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 251.988458] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 251.988459] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 256.994096] [drm:drm_mode_addfb], [FB:96] [ 256.994131] [drm:drm_mode_setcrtc], [CRTC:3] [ 256.994138] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 256.994139] [drm:drm_crtc_helper_set_config], [ 256.994141] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:96] #connectors=1 (x y) (0 0) [ 256.994145] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 256.994148] [drm:drm_mode_debug_printmodeline], Modeline 96:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9 [ 256.994150] [drm:drm_mode_debug_printmodeline], Modeline 97:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 256.994152] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 256.994153] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 256.994155] [drm:drm_mode_debug_printmodeline], Modeline 97:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 256.994158] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz [ 256.994160] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24 [ 256.994161] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 216000 [ 256.994162] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 256.994371] [drm:intel_dp_link_down], [ 257.064763] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 257.166719] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 257.168660] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 257.168664] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 257.169073] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 257.169075] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6 [ 257.169077] [drm:ironlake_check_srwm], watermark 2: display plane 82, fbc lines 4, cursor 6 [ 257.169079] [drm:intel_update_fbc], [ 257.169082] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 257.169084] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 257.169085] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 257.169087] [drm:drm_mode_debug_printmodeline], Modeline 97:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 257.169088] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 257.169090] [drm:intel_get_pch_pll], switching PLL c6014 off [ 257.220696] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 257.220705] [drm:ironlake_update_plane], Writing base 0AD3A000 00000000 0 0 5120 [ 257.272674] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 257.272679] [drm:intel_update_fbc], [ 257.272684] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 257.272690] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6 [ 257.272695] [drm:ironlake_check_srwm], watermark 2: display plane 82, fbc lines 4, cursor 6 [ 257.272700] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:97:1280x720] [ 257.272705] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 257.272710] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 257.272714] [drm:ironlake_write_eld], ELD on pipe A [ 257.272718] [drm:ironlake_write_eld], Audio directed to unknown port [ 257.272721] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 257.272735] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 257.272739] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6 [ 257.272744] [drm:ironlake_check_srwm], watermark 2: display plane 82, fbc lines 4, cursor 6 [ 257.324651] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 257.376629] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 257.376940] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 257.376941] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 257.377095] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 257.377096] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 257.377097] [drm:ironlake_fdi_link_train], FDI train done [ 257.377099] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 257.377101] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 257.378312] [drm:intel_update_fbc], [ 257.429564] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 257.429874] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 257.430793] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 257.431611] [drm:intel_dp_start_link_train], clock recovery OK [ 257.437404] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 257.437406] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 257.457256] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 262.500615] [drm:drm_mode_addfb], [FB:97] [ 262.500650] [drm:drm_mode_setcrtc], [CRTC:3] [ 262.500657] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 262.500659] [drm:drm_crtc_helper_set_config], [ 262.500660] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:97] #connectors=1 (x y) (0 0) [ 262.500664] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 262.500667] [drm:drm_mode_debug_printmodeline], Modeline 97:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 262.500669] [drm:drm_mode_debug_printmodeline], Modeline 98:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 262.500671] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 262.500673] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 262.500675] [drm:drm_mode_debug_printmodeline], Modeline 98:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 262.500678] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz [ 262.500680] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24 [ 262.500681] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 216000 [ 262.500682] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 262.500890] [drm:intel_dp_link_down], [ 262.571404] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 262.673359] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 262.679361] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 262.679366] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 262.679775] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 262.679777] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6 [ 262.679779] [drm:ironlake_check_srwm], watermark 2: display plane 82, fbc lines 4, cursor 6 [ 262.679781] [drm:intel_update_fbc], [ 262.679784] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 262.679785] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 262.679787] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 262.679789] [drm:drm_mode_debug_printmodeline], Modeline 98:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 262.679790] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 262.679792] [drm:intel_get_pch_pll], switching PLL c6014 off [ 262.731335] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 262.731345] [drm:ironlake_update_plane], Writing base 0B0BE000 00000000 0 0 5120 [ 262.783309] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 262.783313] [drm:intel_update_fbc], [ 262.783317] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 262.783321] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6 [ 262.783325] [drm:ironlake_check_srwm], watermark 2: display plane 82, fbc lines 4, cursor 6 [ 262.783330] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:98:1280x720] [ 262.783334] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 262.783339] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 262.783341] [drm:ironlake_write_eld], ELD on pipe A [ 262.783345] [drm:ironlake_write_eld], Audio directed to unknown port [ 262.783347] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 262.783361] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 262.783365] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6 [ 262.783369] [drm:ironlake_check_srwm], watermark 2: display plane 82, fbc lines 4, cursor 6 [ 262.835286] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 262.887202] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 262.887513] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 262.887514] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 262.887668] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 262.887669] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 262.887670] [drm:ironlake_fdi_link_train], FDI train done [ 262.887671] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 262.887673] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 262.888884] [drm:intel_update_fbc], [ 262.940252] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 262.940562] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 262.941485] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 262.942303] [drm:intel_dp_start_link_train], clock recovery OK [ 262.948135] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 262.948137] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 262.948195] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 262.949125] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 262.949127] [drm:intel_crt_detect], CRT not detected via hotplug [ 262.949128] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 262.950203] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 262.950208] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 262.950213] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 262.950528] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 262.951554] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 262.964622] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 262.978652] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 263.005712] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 263.005715] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 263.005717] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 268.011352] [drm:drm_mode_addfb], [FB:98] [ 268.011383] [drm:drm_mode_setcrtc], [CRTC:3] [ 268.011388] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 268.011390] [drm:drm_crtc_helper_set_config], [ 268.011392] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:98] #connectors=1 (x y) (0 0) [ 268.011397] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 268.011400] [drm:drm_mode_debug_printmodeline], Modeline 98:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 268.011402] [drm:drm_mode_debug_printmodeline], Modeline 99:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 268.011404] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 268.011406] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 268.011408] [drm:drm_mode_debug_printmodeline], Modeline 99:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 268.011411] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 78800KHz [ 268.011413] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24 [ 268.011414] [drm:intel_dp_mode_fixup], DP link bw required 189120 available 216000 [ 268.011416] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 268.011625] [drm:intel_dp_link_down], [ 268.082042] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 268.183999] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 268.185959] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 268.185963] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 268.186372] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 268.186375] [drm:ironlake_check_srwm], watermark 1: display plane 49, fbc lines 3, cursor 6 [ 268.186376] [drm:ironlake_check_srwm], watermark 2: display plane 108, fbc lines 4, cursor 10 [ 268.186378] [drm:intel_update_fbc], [ 268.186382] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 268.186383] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 268.186385] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 268.186387] [drm:drm_mode_debug_printmodeline], Modeline 99:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 268.186388] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 268.186389] [drm:intel_get_pch_pll], switching PLL c6014 off [ 268.237975] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 268.237984] [drm:ironlake_update_plane], Writing base 0B442000 00000000 0 0 4096 [ 268.289952] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 268.289957] [drm:intel_update_fbc], [ 268.289962] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 268.289968] [drm:ironlake_check_srwm], watermark 1: display plane 49, fbc lines 3, cursor 6 [ 268.289973] [drm:ironlake_check_srwm], watermark 2: display plane 108, fbc lines 4, cursor 10 [ 268.289979] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:99:1024x768] [ 268.289983] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 268.289989] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 268.289992] [drm:ironlake_write_eld], ELD on pipe A [ 268.289996] [drm:ironlake_write_eld], Audio directed to unknown port [ 268.289999] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 268.290013] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 268.290018] [drm:ironlake_check_srwm], watermark 1: display plane 49, fbc lines 3, cursor 6 [ 268.290023] [drm:ironlake_check_srwm], watermark 2: display plane 108, fbc lines 4, cursor 10 [ 268.341930] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 268.393908] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 268.394218] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 268.394219] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 268.394373] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 268.394374] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 268.394375] [drm:ironlake_fdi_link_train], FDI train done [ 268.394376] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 268.394378] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 268.395590] [drm:intel_update_fbc], [ 268.446879] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 268.447189] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 268.448109] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 268.448927] [drm:intel_dp_start_link_train], clock recovery OK [ 268.454793] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 268.454794] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 268.454875] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 268.455813] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 268.455815] [drm:intel_crt_detect], CRT not detected via hotplug [ 268.455819] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 268.457844] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 268.457848] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 268.457854] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 268.458166] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 268.459191] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 268.467932] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 268.486240] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 268.513299] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 268.513300] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 268.513302] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 273.516368] [drm:drm_mode_addfb], [FB:99] [ 273.516402] [drm:drm_mode_setcrtc], [CRTC:3] [ 273.516406] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 273.516408] [drm:drm_crtc_helper_set_config], [ 273.516410] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:99] #connectors=1 (x y) (0 0) [ 273.516414] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 273.516417] [drm:drm_mode_debug_printmodeline], Modeline 99:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 273.516419] [drm:drm_mode_debug_printmodeline], Modeline 100:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 273.516421] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 273.516423] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 273.516425] [drm:drm_mode_debug_printmodeline], Modeline 100:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 273.516428] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 78750KHz [ 273.516430] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24 [ 273.516432] [drm:intel_dp_mode_fixup], DP link bw required 189000 available 216000 [ 273.516433] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 273.516679] [drm:intel_dp_link_down], [ 273.587676] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 273.689635] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 273.691576] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 273.691580] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 273.691988] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 273.691990] [drm:ironlake_check_srwm], watermark 1: display plane 49, fbc lines 3, cursor 6 [ 273.691992] [drm:ironlake_check_srwm], watermark 2: display plane 108, fbc lines 4, cursor 10 [ 273.691993] [drm:intel_update_fbc], [ 273.691997] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 273.691998] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 273.692000] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 273.692002] [drm:drm_mode_debug_printmodeline], Modeline 100:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 273.692003] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 273.692004] [drm:intel_get_pch_pll], switching PLL c6014 off [ 273.743612] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 273.743620] [drm:ironlake_update_plane], Writing base 0B742000 00000000 0 0 4096 [ 273.795589] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 273.795593] [drm:intel_update_fbc], [ 273.795598] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 273.795602] [drm:ironlake_check_srwm], watermark 1: display plane 49, fbc lines 3, cursor 6 [ 273.795606] [drm:ironlake_check_srwm], watermark 2: display plane 108, fbc lines 4, cursor 10 [ 273.795611] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:100:1024x768] [ 273.795615] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 273.795620] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 273.795622] [drm:ironlake_write_eld], ELD on pipe A [ 273.795626] [drm:ironlake_write_eld], Audio directed to unknown port [ 273.795628] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 273.795642] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 273.795646] [drm:ironlake_check_srwm], watermark 1: display plane 49, fbc lines 3, cursor 6 [ 273.795650] [drm:ironlake_check_srwm], watermark 2: display plane 108, fbc lines 4, cursor 10 [ 273.847567] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 273.899545] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 273.899854] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 273.899855] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 273.900009] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 273.900010] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 273.900011] [drm:ironlake_fdi_link_train], FDI train done [ 273.900013] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 273.900015] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 273.901226] [drm:intel_update_fbc], [ 273.952520] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 273.952830] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 273.953750] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 273.954568] [drm:intel_dp_start_link_train], clock recovery OK [ 273.960434] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 273.960435] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 273.960512] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 273.961450] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 273.961451] [drm:intel_crt_detect], CRT not detected via hotplug [ 273.961453] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 273.963484] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 273.963489] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 273.963494] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 273.963806] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 273.964831] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 273.973582] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 273.992085] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 274.019144] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 274.019146] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 274.019147] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 279.023661] [drm:drm_mode_addfb], [FB:100] [ 279.023689] [drm:drm_mode_setcrtc], [CRTC:3] [ 279.023695] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 279.023697] [drm:drm_crtc_helper_set_config], [ 279.023698] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:100] #connectors=1 (x y) (0 0) [ 279.023702] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 279.023704] [drm:drm_mode_debug_printmodeline], Modeline 100:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 279.023707] [drm:drm_mode_debug_printmodeline], Modeline 101:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 279.023708] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 279.023710] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 279.023712] [drm:drm_mode_debug_printmodeline], Modeline 101:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 279.023715] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 75000KHz [ 279.023717] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24 [ 279.023718] [drm:intel_dp_mode_fixup], DP link bw required 180000 available 216000 [ 279.023719] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 279.023927] [drm:intel_dp_link_down], [ 279.094284] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 279.196240] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 279.198218] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 279.198221] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 279.198631] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 279.198633] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6 [ 279.198635] [drm:ironlake_check_srwm], watermark 2: display plane 103, fbc lines 4, cursor 10 [ 279.198636] [drm:intel_update_fbc], [ 279.198639] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 279.198641] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 279.198642] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 279.198644] [drm:drm_mode_debug_printmodeline], Modeline 101:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 279.198645] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 279.198646] [drm:intel_get_pch_pll], switching PLL c6014 off [ 279.250216] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 279.250225] [drm:ironlake_update_plane], Writing base 0BA42000 00000000 0 0 4096 [ 279.302194] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 279.302198] [drm:intel_update_fbc], [ 279.302202] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 279.302208] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6 [ 279.302212] [drm:ironlake_check_srwm], watermark 2: display plane 103, fbc lines 4, cursor 10 [ 279.302218] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:101:1024x768] [ 279.302223] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 279.302229] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 279.302232] [drm:ironlake_write_eld], ELD on pipe A [ 279.302236] [drm:ironlake_write_eld], Audio directed to unknown port [ 279.302239] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 279.302253] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 279.302258] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6 [ 279.302262] [drm:ironlake_check_srwm], watermark 2: display plane 103, fbc lines 4, cursor 10 [ 279.354172] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 279.406185] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 279.406495] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 279.406496] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 279.406650] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 279.406651] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 279.406652] [drm:ironlake_fdi_link_train], FDI train done [ 279.406653] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 279.406655] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 279.407867] [drm:intel_update_fbc], [ 279.459126] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 279.459436] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 279.460357] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 279.461175] [drm:intel_dp_start_link_train], clock recovery OK [ 279.466969] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 279.466971] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 279.467027] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 279.467958] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 279.467960] [drm:intel_crt_detect], CRT not detected via hotplug [ 279.467961] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 279.469122] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 279.469126] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 279.469132] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 279.469443] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 279.470469] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 279.481062] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 279.497545] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 279.524714] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 279.524715] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 279.524717] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 284.528602] [drm:drm_mode_addfb], [FB:101] [ 284.528630] [drm:drm_mode_setcrtc], [CRTC:3] [ 284.528633] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 284.528638] [drm:drm_crtc_helper_set_config], [ 284.528639] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:101] #connectors=1 (x y) (0 0) [ 284.528643] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 284.528645] [drm:drm_mode_debug_printmodeline], Modeline 101:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 284.528648] [drm:drm_mode_debug_printmodeline], Modeline 102:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 284.528649] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 284.528651] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 284.528653] [drm:drm_mode_debug_printmodeline], Modeline 102:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 284.528655] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 65000KHz [ 284.528657] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24 [ 284.528658] [drm:intel_dp_mode_fixup], DP link bw required 156000 available 216000 [ 284.528660] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 284.528868] [drm:intel_dp_link_down], [ 284.598962] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 284.700917] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 284.704919] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 284.704923] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 284.705332] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6 [ 284.705334] [drm:ironlake_check_srwm], watermark 1: display plane 41, fbc lines 3, cursor 6 [ 284.705336] [drm:ironlake_check_srwm], watermark 2: display plane 90, fbc lines 4, cursor 10 [ 284.705337] [drm:intel_update_fbc], [ 284.705340] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 284.705341] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 284.705343] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 284.705345] [drm:drm_mode_debug_printmodeline], Modeline 102:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 284.705346] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 284.705347] [drm:intel_get_pch_pll], switching PLL c6014 off [ 284.756893] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 284.756901] [drm:ironlake_update_plane], Writing base 0BD42000 00000000 0 0 4096 [ 284.808871] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 284.808875] [drm:intel_update_fbc], [ 284.808879] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6 [ 284.808884] [drm:ironlake_check_srwm], watermark 1: display plane 41, fbc lines 3, cursor 6 [ 284.808888] [drm:ironlake_check_srwm], watermark 2: display plane 90, fbc lines 4, cursor 10 [ 284.808893] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:102:1024x768] [ 284.808897] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 284.808902] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 284.808905] [drm:ironlake_write_eld], ELD on pipe A [ 284.808908] [drm:ironlake_write_eld], Audio directed to unknown port [ 284.808910] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 284.808924] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6 [ 284.808928] [drm:ironlake_check_srwm], watermark 1: display plane 41, fbc lines 3, cursor 6 [ 284.808932] [drm:ironlake_check_srwm], watermark 2: display plane 90, fbc lines 4, cursor 10 [ 284.860849] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 284.912765] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 284.913075] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 284.913076] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 284.913230] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 284.913231] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 284.913232] [drm:ironlake_fdi_link_train], FDI train done [ 284.913233] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 284.913235] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 284.914446] [drm:intel_update_fbc], [ 284.965767] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 284.966077] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 284.966997] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 284.967816] [drm:intel_dp_start_link_train], clock recovery OK [ 284.973609] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 284.973611] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 284.973667] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 284.974597] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 284.974598] [drm:intel_crt_detect], CRT not detected via hotplug [ 284.974599] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 284.975762] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 284.975767] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 284.975773] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 284.976084] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 284.977109] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 284.990093] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 285.004311] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 285.031377] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 285.031379] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 285.031380] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 290.022902] [drm:drm_mode_addfb], [FB:102] [ 290.022927] [drm:drm_mode_setcrtc], [CRTC:3] [ 290.022932] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 290.022934] [drm:drm_crtc_helper_set_config], [ 290.022935] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:102] #connectors=1 (x y) (0 0) [ 290.022938] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 290.022940] [drm:drm_mode_debug_printmodeline], Modeline 102:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 290.022943] [drm:drm_mode_debug_printmodeline], Modeline 103:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6 [ 290.022944] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 290.022946] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 290.022948] [drm:drm_mode_debug_printmodeline], Modeline 103:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6 [ 290.022950] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 46970KHz [ 290.022952] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 290.022953] [drm:intel_dp_mode_fixup], DP link bw required 112728 available 129600 [ 290.022955] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 290.023162] [drm:intel_dp_link_down], [ 290.093604] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 290.195563] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 290.197504] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 290.197507] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 290.197916] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6 [ 290.197918] [drm:ironlake_check_srwm], watermark 1: display plane 30, fbc lines 3, cursor 6 [ 290.197919] [drm:ironlake_check_srwm], watermark 2: display plane 65, fbc lines 4, cursor 6 [ 290.197921] [drm:intel_update_fbc], [ 290.197923] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 290.197925] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 290.197926] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 290.197928] [drm:drm_mode_debug_printmodeline], Modeline 103:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6 [ 290.197929] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 290.197930] [drm:intel_get_pch_pll], switching PLL c6014 off [ 290.249540] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 290.249547] [drm:ironlake_update_plane], Writing base 0C042000 00000000 0 0 4096 [ 290.301517] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 290.301521] [drm:intel_update_fbc], [ 290.301526] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6 [ 290.301530] [drm:ironlake_check_srwm], watermark 1: display plane 30, fbc lines 3, cursor 6 [ 290.301534] [drm:ironlake_check_srwm], watermark 2: display plane 65, fbc lines 4, cursor 6 [ 290.301539] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:103:1024x576] [ 290.301543] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 290.301547] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 290.301550] [drm:ironlake_write_eld], ELD on pipe A [ 290.301553] [drm:ironlake_write_eld], Audio directed to unknown port [ 290.301555] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 290.301569] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6 [ 290.301573] [drm:ironlake_check_srwm], watermark 1: display plane 30, fbc lines 3, cursor 6 [ 290.301577] [drm:ironlake_check_srwm], watermark 2: display plane 65, fbc lines 4, cursor 6 [ 290.353495] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 290.405473] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 290.405783] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 290.405784] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 290.405937] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 290.405938] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 290.405939] [drm:ironlake_fdi_link_train], FDI train done [ 290.405941] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 290.405943] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 290.407154] [drm:intel_update_fbc], [ 290.458447] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 290.458757] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 290.459676] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 290.460494] [drm:intel_dp_start_link_train], clock recovery OK [ 290.466287] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 290.466289] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 290.466344] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 290.467275] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 290.467276] [drm:intel_crt_detect], CRT not detected via hotplug [ 290.467278] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 290.468409] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 290.468413] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 290.468419] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 290.468730] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 290.469755] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 290.482803] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 290.496932] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 290.524052] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 290.524054] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 290.524056] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 295.514109] [drm:drm_mode_addfb], [FB:103] [ 295.514129] [drm:drm_mode_setcrtc], [CRTC:3] [ 295.514132] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 295.514136] [drm:drm_crtc_helper_set_config], [ 295.514137] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:103] #connectors=1 (x y) (0 0) [ 295.514140] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 295.514142] [drm:drm_mode_debug_printmodeline], Modeline 103:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6 [ 295.514145] [drm:drm_mode_debug_printmodeline], Modeline 104:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 295.514146] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 295.514147] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 295.514150] [drm:drm_mode_debug_printmodeline], Modeline 104:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 295.514152] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 50000KHz [ 295.514154] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 295.514155] [drm:intel_dp_mode_fixup], DP link bw required 120000 available 129600 [ 295.514156] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 295.514364] [drm:intel_dp_link_down], [ 295.585252] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 295.687254] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 295.693207] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 295.693211] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 295.693619] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6 [ 295.693621] [drm:ironlake_check_srwm], watermark 1: display plane 32, fbc lines 3, cursor 6 [ 295.693623] [drm:ironlake_check_srwm], watermark 2: display plane 70, fbc lines 4, cursor 10 [ 295.693624] [drm:intel_update_fbc], [ 295.693627] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 295.693628] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 295.693630] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 295.693632] [drm:drm_mode_debug_printmodeline], Modeline 104:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 295.693633] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 295.693634] [drm:intel_get_pch_pll], switching PLL c6014 off [ 295.745182] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 295.745189] [drm:ironlake_update_plane], Writing base 0C282000 00000000 0 0 3200 [ 295.797160] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 295.797164] [drm:intel_update_fbc], [ 295.797168] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6 [ 295.797173] [drm:ironlake_check_srwm], watermark 1: display plane 32, fbc lines 3, cursor 6 [ 295.797177] [drm:ironlake_check_srwm], watermark 2: display plane 70, fbc lines 4, cursor 10 [ 295.797181] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:104:800x600] [ 295.797185] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 295.797189] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 295.797192] [drm:ironlake_write_eld], ELD on pipe A [ 295.797195] [drm:ironlake_write_eld], Audio directed to unknown port [ 295.797197] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 295.797211] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6 [ 295.797215] [drm:ironlake_check_srwm], watermark 1: display plane 32, fbc lines 3, cursor 6 [ 295.797219] [drm:ironlake_check_srwm], watermark 2: display plane 70, fbc lines 4, cursor 10 [ 295.849140] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 295.901118] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 295.901427] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 295.901428] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 295.901582] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 295.901583] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 295.901584] [drm:ironlake_fdi_link_train], FDI train done [ 295.901586] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 295.901588] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 295.902799] [drm:intel_update_fbc], [ 295.954092] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 295.954402] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 295.955322] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 295.956144] [drm:intel_dp_start_link_train], clock recovery OK [ 295.961935] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 295.961937] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 295.961993] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 295.962923] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 295.962924] [drm:intel_crt_detect], CRT not detected via hotplug [ 295.962926] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 295.964054] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 295.964058] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 295.964063] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 295.964375] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 295.965400] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 295.975627] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 295.992477] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 296.019567] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 296.019568] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 296.019570] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 301.009905] [drm:drm_mode_addfb], [FB:104] [ 301.009925] [drm:drm_mode_setcrtc], [CRTC:3] [ 301.009927] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 301.009931] [drm:drm_crtc_helper_set_config], [ 301.009933] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:104] #connectors=1 (x y) (0 0) [ 301.009936] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 301.009938] [drm:drm_mode_debug_printmodeline], Modeline 104:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 301.009940] [drm:drm_mode_debug_printmodeline], Modeline 105:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 301.009942] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 301.009943] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 301.009945] [drm:drm_mode_debug_printmodeline], Modeline 105:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 301.009948] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 49500KHz [ 301.009949] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 301.009951] [drm:intel_dp_mode_fixup], DP link bw required 118800 available 129600 [ 301.009952] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 301.010159] [drm:intel_dp_link_down], [ 301.080861] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 301.182858] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 301.186861] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 301.186865] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 301.187274] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6 [ 301.187276] [drm:ironlake_check_srwm], watermark 1: display plane 32, fbc lines 3, cursor 6 [ 301.187278] [drm:ironlake_check_srwm], watermark 2: display plane 69, fbc lines 4, cursor 10 [ 301.187279] [drm:intel_update_fbc], [ 301.187281] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 301.187283] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 301.187284] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 301.187286] [drm:drm_mode_debug_printmodeline], Modeline 105:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 301.187287] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 301.187288] [drm:intel_get_pch_pll], switching PLL c6014 off [ 301.238834] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 301.238843] [drm:ironlake_update_plane], Writing base 0C457000 00000000 0 0 3200 [ 301.290812] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 301.290817] [drm:intel_update_fbc], [ 301.290822] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6 [ 301.290827] [drm:ironlake_check_srwm], watermark 1: display plane 32, fbc lines 3, cursor 6 [ 301.290832] [drm:ironlake_check_srwm], watermark 2: display plane 69, fbc lines 4, cursor 10 [ 301.290838] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:105:800x600] [ 301.290842] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 301.290847] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 301.290851] [drm:ironlake_write_eld], ELD on pipe A [ 301.290855] [drm:ironlake_write_eld], Audio directed to unknown port [ 301.290857] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 301.290872] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6 [ 301.290877] [drm:ironlake_check_srwm], watermark 1: display plane 32, fbc lines 3, cursor 6 [ 301.290881] [drm:ironlake_check_srwm], watermark 2: display plane 69, fbc lines 4, cursor 10 [ 301.342790] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 301.394764] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 301.395073] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 301.395074] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 301.395228] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 301.395229] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 301.395230] [drm:ironlake_fdi_link_train], FDI train done [ 301.395232] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 301.395234] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 301.396445] [drm:intel_update_fbc], [ 301.447738] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 301.448048] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 301.448968] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 301.449787] [drm:intel_dp_start_link_train], clock recovery OK [ 301.455652] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 301.455654] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 301.455730] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 301.456661] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 301.456668] [drm:intel_crt_detect], CRT not detected via hotplug [ 301.456670] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 301.458703] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 301.458707] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 301.458713] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 301.459024] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 301.460049] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 301.468824] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 301.487246] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 301.514315] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 301.514316] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 301.514318] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 306.503698] [drm:drm_mode_addfb], [FB:105] [ 306.503719] [drm:drm_mode_setcrtc], [CRTC:3] [ 306.503725] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 306.503726] [drm:drm_crtc_helper_set_config], [ 306.503728] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:105] #connectors=1 (x y) (0 0) [ 306.503730] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 306.503732] [drm:drm_mode_debug_printmodeline], Modeline 105:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 306.503735] [drm:drm_mode_debug_printmodeline], Modeline 106:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 306.503736] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 306.503737] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 306.503739] [drm:drm_mode_debug_printmodeline], Modeline 106:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 306.503742] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 40000KHz [ 306.503743] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 306.503745] [drm:intel_dp_mode_fixup], DP link bw required 96000 available 129600 [ 306.503746] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 306.503954] [drm:intel_dp_link_down], [ 306.574507] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 306.676472] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 306.680467] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 306.680471] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 306.680880] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6 [ 306.680882] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6 [ 306.680884] [drm:ironlake_check_srwm], watermark 2: display plane 52, fbc lines 4, cursor 6 [ 306.680885] [drm:intel_update_fbc], [ 306.680888] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 306.680889] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 306.680891] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 306.680893] [drm:drm_mode_debug_printmodeline], Modeline 106:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 306.680894] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 306.680895] [drm:intel_get_pch_pll], switching PLL c6014 off [ 306.732441] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 306.732448] [drm:ironlake_update_plane], Writing base 0C62C000 00000000 0 0 3200 [ 306.784418] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 306.784422] [drm:intel_update_fbc], [ 306.784427] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6 [ 306.784432] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6 [ 306.784436] [drm:ironlake_check_srwm], watermark 2: display plane 52, fbc lines 4, cursor 6 [ 306.784442] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:106:800x600] [ 306.784446] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 306.784452] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 306.784455] [drm:ironlake_write_eld], ELD on pipe A [ 306.784458] [drm:ironlake_write_eld], Audio directed to unknown port [ 306.784461] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 306.784476] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6 [ 306.784481] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6 [ 306.784485] [drm:ironlake_check_srwm], watermark 2: display plane 52, fbc lines 4, cursor 6 [ 306.836396] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 306.888374] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 306.888683] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 306.888684] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 306.888838] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 306.888839] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 306.888840] [drm:ironlake_fdi_link_train], FDI train done [ 306.888841] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 306.888843] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 306.890055] [drm:intel_update_fbc], [ 306.941350] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 306.941660] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 306.942579] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 306.943398] [drm:intel_dp_start_link_train], clock recovery OK [ 306.949193] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 306.949195] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 306.949251] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 306.950181] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 306.950183] [drm:intel_crt_detect], CRT not detected via hotplug [ 306.950184] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 306.951346] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 306.951350] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 306.951356] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 306.951667] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 306.952693] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 306.965656] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 306.979893] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 307.006960] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 307.006961] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 307.006963] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 311.996888] [drm:drm_mode_addfb], [FB:106] [ 311.996909] [drm:drm_mode_setcrtc], [CRTC:3] [ 311.996914] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 311.996916] [drm:drm_crtc_helper_set_config], [ 311.996917] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:106] #connectors=1 (x y) (0 0) [ 311.996920] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 311.996923] [drm:drm_mode_debug_printmodeline], Modeline 106:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 311.996925] [drm:drm_mode_debug_printmodeline], Modeline 107:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 311.996927] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 311.996928] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 311.996930] [drm:drm_mode_debug_printmodeline], Modeline 107:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 311.996932] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 36000KHz [ 311.996934] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 311.996935] [drm:intel_dp_mode_fixup], DP link bw required 86400 available 129600 [ 311.996936] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 311.997143] [drm:intel_dp_link_down], [ 312.067195] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 312.169147] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 312.171113] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 312.171117] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 312.171526] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6 [ 312.171528] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6 [ 312.171529] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 4, cursor 6 [ 312.171531] [drm:intel_update_fbc], [ 312.171534] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 312.171535] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 312.171536] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 312.171538] [drm:drm_mode_debug_printmodeline], Modeline 107:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 312.171539] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 312.171540] [drm:intel_get_pch_pll], switching PLL c6014 off [ 312.223124] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 312.223132] [drm:ironlake_update_plane], Writing base 0C801000 00000000 0 0 3200 [ 312.275102] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 312.275106] [drm:intel_update_fbc], [ 312.275110] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6 [ 312.275115] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6 [ 312.275119] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 4, cursor 6 [ 312.275124] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:107:800x600] [ 312.275128] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 312.275132] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 312.275134] [drm:ironlake_write_eld], ELD on pipe A [ 312.275138] [drm:ironlake_write_eld], Audio directed to unknown port [ 312.275140] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 312.275153] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6 [ 312.275157] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6 [ 312.275161] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 4, cursor 6 [ 312.327080] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 312.379057] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 312.379367] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 312.379367] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 312.379521] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 312.379522] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 312.379523] [drm:ironlake_fdi_link_train], FDI train done [ 312.379525] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 312.379527] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 312.380738] [drm:intel_update_fbc], [ 312.432032] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 312.432342] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 312.433262] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 312.434083] [drm:intel_dp_start_link_train], clock recovery OK [ 312.439875] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 312.439876] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 312.439930] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 312.440861] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 312.440862] [drm:intel_crt_detect], CRT not detected via hotplug [ 312.440863] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 312.441993] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 312.441997] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 312.442003] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 312.442314] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 312.443340] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 312.457490] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 312.470466] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 312.497527] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 312.497529] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 312.497530] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 317.480608] [drm:drm_mode_addfb], [FB:107] [ 317.480627] [drm:drm_mode_setcrtc], [CRTC:3] [ 317.480629] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 317.480630] [drm:drm_crtc_helper_set_config], [ 317.480635] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:107] #connectors=1 (x y) (0 0) [ 317.480637] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 317.480640] [drm:drm_mode_debug_printmodeline], Modeline 107:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 317.480642] [drm:drm_mode_debug_printmodeline], Modeline 108:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 317.480643] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 317.480645] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 317.480647] [drm:drm_mode_debug_printmodeline], Modeline 108:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 317.480649] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 27000KHz [ 317.480650] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 317.480652] [drm:intel_dp_mode_fixup], DP link bw required 64800 available 129600 [ 317.480653] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 317.480861] [drm:intel_dp_link_down], [ 317.551839] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 317.653797] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 317.657799] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 317.657802] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 317.658211] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 317.658213] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6 [ 317.658215] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6 [ 317.658216] [drm:intel_update_fbc], [ 317.658218] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 317.658220] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 317.658221] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 317.658223] [drm:drm_mode_debug_printmodeline], Modeline 108:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 317.658225] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 317.658226] [drm:intel_get_pch_pll], switching PLL c6014 off [ 317.709773] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 317.709781] [drm:ironlake_update_plane], Writing base 0C9D6000 00000000 0 0 2880 [ 317.761751] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 317.761755] [drm:intel_update_fbc], [ 317.761759] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 317.761764] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6 [ 317.761768] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6 [ 317.761773] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:108:720x576] [ 317.761777] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 317.761781] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 317.761784] [drm:ironlake_write_eld], ELD on pipe A [ 317.761787] [drm:ironlake_write_eld], Audio directed to unknown port [ 317.761789] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 317.761802] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 317.761806] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6 [ 317.761810] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6 [ 317.813729] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 317.865707] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 317.866016] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 317.866017] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 317.866171] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 317.866172] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 317.866173] [drm:ironlake_fdi_link_train], FDI train done [ 317.866174] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 317.866176] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 317.867388] [drm:intel_update_fbc], [ 317.918646] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 317.918957] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 317.919877] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 317.920695] [drm:intel_dp_start_link_train], clock recovery OK [ 317.926489] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 317.926490] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 317.926543] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 317.927474] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 317.927475] [drm:intel_crt_detect], CRT not detected via hotplug [ 317.927477] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 317.928642] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 317.928647] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 317.928652] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 317.928964] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 317.929989] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 317.946325] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 317.957171] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 317.984236] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 317.984237] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 317.984239] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 322.960618] [drm:drm_mode_addfb], [FB:108] [ 322.960644] [drm:drm_mode_setcrtc], [CRTC:3] [ 322.960651] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 322.960652] [drm:drm_crtc_helper_set_config], [ 322.960654] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:108] #connectors=1 (x y) (0 0) [ 322.960657] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 322.960660] [drm:drm_mode_debug_printmodeline], Modeline 108:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 322.960662] [drm:drm_mode_debug_printmodeline], Modeline 109:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 322.960664] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 322.960666] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 322.960668] [drm:drm_mode_debug_printmodeline], Modeline 109:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 322.960670] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 33750KHz [ 322.960672] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 322.960673] [drm:intel_dp_mode_fixup], DP link bw required 81000 available 129600 [ 322.960675] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 322.960895] [drm:intel_dp_link_down], [ 323.031494] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 323.132453] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 323.136454] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 323.136458] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 323.136867] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6 [ 323.136870] [drm:ironlake_check_srwm], watermark 1: display plane 23, fbc lines 3, cursor 6 [ 323.136871] [drm:ironlake_check_srwm], watermark 2: display plane 48, fbc lines 3, cursor 6 [ 323.136873] [drm:intel_update_fbc], [ 323.136879] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 323.136881] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 323.136882] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 323.136885] [drm:drm_mode_debug_printmodeline], Modeline 109:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 323.136886] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 323.136887] [drm:intel_get_pch_pll], switching PLL c6014 off [ 323.188431] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 323.188442] [drm:ironlake_update_plane], Writing base 0CB6B000 00000000 0 0 3392 [ 323.240397] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 323.240402] [drm:intel_update_fbc], [ 323.240406] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6 [ 323.240411] [drm:ironlake_check_srwm], watermark 1: display plane 23, fbc lines 3, cursor 6 [ 323.240415] [drm:ironlake_check_srwm], watermark 2: display plane 48, fbc lines 3, cursor 6 [ 323.240420] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:109:848x480] [ 323.240424] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 323.240428] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 323.240431] [drm:ironlake_write_eld], ELD on pipe A [ 323.240435] [drm:ironlake_write_eld], Audio directed to unknown port [ 323.240437] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 323.240451] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6 [ 323.240455] [drm:ironlake_check_srwm], watermark 1: display plane 23, fbc lines 3, cursor 6 [ 323.240459] [drm:ironlake_check_srwm], watermark 2: display plane 48, fbc lines 3, cursor 6 [ 323.292381] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 323.344359] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 323.344669] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 323.344669] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 323.344823] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 323.344824] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 323.344825] [drm:ironlake_fdi_link_train], FDI train done [ 323.344827] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 323.344829] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 323.346041] [drm:intel_update_fbc], [ 323.397333] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 323.397643] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 323.398564] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 323.399382] [drm:intel_dp_start_link_train], clock recovery OK [ 323.405249] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 323.405251] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 323.405322] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 323.406256] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 323.406307] [drm:intel_crt_detect], CRT not detected via hotplug [ 323.406314] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 323.408276] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 323.408280] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 323.408285] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 323.408597] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 323.409624] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 323.421752] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 323.436719] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 323.463786] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 323.463787] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 323.463789] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 328.437323] [drm:drm_mode_addfb], [FB:109] [ 328.437347] [drm:drm_mode_setcrtc], [CRTC:3] [ 328.437350] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 328.437355] [drm:drm_crtc_helper_set_config], [ 328.437356] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:109] #connectors=1 (x y) (0 0) [ 328.437360] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 328.437362] [drm:drm_mode_debug_printmodeline], Modeline 109:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 328.437364] [drm:drm_mode_debug_printmodeline], Modeline 110:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 328.437366] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 328.437367] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 328.437369] [drm:drm_mode_debug_printmodeline], Modeline 110:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 328.437372] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 27000KHz [ 328.437374] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 328.437375] [drm:intel_dp_mode_fixup], DP link bw required 64800 available 129600 [ 328.437376] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 328.437584] [drm:intel_dp_link_down], [ 328.508147] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 328.610106] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 328.612069] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 328.612073] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 328.612482] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 328.612484] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6 [ 328.612486] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6 [ 328.612487] [drm:intel_update_fbc], [ 328.612491] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 328.612492] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 328.612494] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 328.612496] [drm:drm_mode_debug_printmodeline], Modeline 110:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 328.612497] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 328.612498] [drm:intel_get_pch_pll], switching PLL c6014 off [ 328.664095] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 328.664104] [drm:ironlake_update_plane], Writing base 0CCF9000 00000000 0 0 2880 [ 328.716061] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 328.716066] [drm:intel_update_fbc], [ 328.716071] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 328.716077] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6 [ 328.716082] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6 [ 328.716087] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:110:720x480] [ 328.716092] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 328.716097] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 328.716100] [drm:ironlake_write_eld], ELD on pipe A [ 328.716104] [drm:ironlake_write_eld], Audio directed to unknown port [ 328.716107] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 328.716121] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 328.716126] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6 [ 328.716131] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 6 [ 328.768039] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 328.820016] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 328.820327] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 328.820328] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 328.820482] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 328.820483] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 328.820484] [drm:ironlake_fdi_link_train], FDI train done [ 328.820485] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 328.820487] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 328.821699] [drm:intel_update_fbc], [ 328.872927] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 328.873237] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 328.874157] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 328.874975] [drm:intel_dp_start_link_train], clock recovery OK [ 328.880769] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 328.880771] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 328.880826] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 328.881756] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 328.881757] [drm:intel_crt_detect], CRT not detected via hotplug [ 328.881759] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 328.882949] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 328.882953] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 328.882959] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 328.883270] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 328.884296] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 328.897288] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 328.911498] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 328.938611] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 328.938613] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 328.938614] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 333.909996] [drm:drm_mode_addfb], [FB:110] [ 333.910015] [drm:drm_mode_setcrtc], [CRTC:3] [ 333.910017] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 333.910018] [drm:drm_crtc_helper_set_config], [ 333.910020] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:110] #connectors=1 (x y) (0 0) [ 333.910026] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 333.910028] [drm:drm_mode_debug_printmodeline], Modeline 110:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 333.910030] [drm:drm_mode_debug_printmodeline], Modeline 111:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 333.910032] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 333.910033] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 333.910035] [drm:drm_mode_debug_printmodeline], Modeline 111:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 333.910037] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 31500KHz [ 333.910039] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 333.910040] [drm:intel_dp_mode_fixup], DP link bw required 75600 available 129600 [ 333.910042] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 333.910249] [drm:intel_dp_link_down], [ 333.980802] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 334.082762] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 334.084723] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 334.084727] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 334.085136] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 334.085138] [drm:ironlake_check_srwm], watermark 1: display plane 21, fbc lines 3, cursor 6 [ 334.085140] [drm:ironlake_check_srwm], watermark 2: display plane 42, fbc lines 4, cursor 6 [ 334.085141] [drm:intel_update_fbc], [ 334.085144] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 334.085145] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 334.085147] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 334.085149] [drm:drm_mode_debug_printmodeline], Modeline 111:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 334.085150] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 334.085151] [drm:intel_get_pch_pll], switching PLL c6014 off [ 334.136738] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 334.136747] [drm:ironlake_update_plane], Writing base 0CE4B000 00000000 0 0 2560 [ 334.188716] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 334.188721] [drm:intel_update_fbc], [ 334.188726] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 334.188732] [drm:ironlake_check_srwm], watermark 1: display plane 21, fbc lines 3, cursor 6 [ 334.188737] [drm:ironlake_check_srwm], watermark 2: display plane 42, fbc lines 4, cursor 6 [ 334.188742] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:111:640x480] [ 334.188747] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 334.188752] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 334.188755] [drm:ironlake_write_eld], ELD on pipe A [ 334.188759] [drm:ironlake_write_eld], Audio directed to unknown port [ 334.188762] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 334.188776] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 334.188781] [drm:ironlake_check_srwm], watermark 1: display plane 21, fbc lines 3, cursor 6 [ 334.188785] [drm:ironlake_check_srwm], watermark 2: display plane 42, fbc lines 4, cursor 6 [ 334.240694] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 334.292671] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 334.292981] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 334.292982] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 334.293136] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 334.293137] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 334.293138] [drm:ironlake_fdi_link_train], FDI train done [ 334.293140] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 334.293142] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 334.294353] [drm:intel_update_fbc], [ 334.345608] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 334.345918] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 334.346838] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 334.347656] [drm:intel_dp_start_link_train], clock recovery OK [ 334.353537] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 334.353538] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 334.353597] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 334.354528] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 334.354529] [drm:intel_crt_detect], CRT not detected via hotplug [ 334.354531] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 334.355605] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 334.355609] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 334.355614] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 334.355926] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 334.356952] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 334.366708] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 334.384175] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 334.411320] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 334.411322] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 334.411323] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 339.383016] [drm:drm_mode_addfb], [FB:111] [ 339.383033] [drm:drm_mode_setcrtc], [CRTC:3] [ 339.383035] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 339.383036] [drm:drm_crtc_helper_set_config], [ 339.383040] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:111] #connectors=1 (x y) (0 0) [ 339.383043] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 339.383045] [drm:drm_mode_debug_printmodeline], Modeline 111:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 339.383048] [drm:drm_mode_debug_printmodeline], Modeline 112:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 339.383049] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 339.383051] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 339.383052] [drm:drm_mode_debug_printmodeline], Modeline 112:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 339.383055] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 31500KHz [ 339.383056] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 339.383058] [drm:intel_dp_mode_fixup], DP link bw required 75600 available 129600 [ 339.383059] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 339.383267] [drm:intel_dp_link_down], [ 339.453457] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 339.555416] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 339.557357] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 339.557361] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 339.557770] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 339.557772] [drm:ironlake_check_srwm], watermark 1: display plane 21, fbc lines 3, cursor 6 [ 339.557774] [drm:ironlake_check_srwm], watermark 2: display plane 42, fbc lines 4, cursor 6 [ 339.557775] [drm:intel_update_fbc], [ 339.557778] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 339.557779] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 339.557781] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 339.557783] [drm:drm_mode_debug_printmodeline], Modeline 112:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 339.557784] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 339.557785] [drm:intel_get_pch_pll], switching PLL c6014 off [ 339.609391] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 339.609400] [drm:ironlake_update_plane], Writing base 0CF77000 00000000 0 0 2560 [ 339.661367] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 339.661371] [drm:intel_update_fbc], [ 339.661376] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 339.661380] [drm:ironlake_check_srwm], watermark 1: display plane 21, fbc lines 3, cursor 6 [ 339.661384] [drm:ironlake_check_srwm], watermark 2: display plane 42, fbc lines 4, cursor 6 [ 339.661389] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:112:640x480] [ 339.661393] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 339.661397] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 339.661399] [drm:ironlake_write_eld], ELD on pipe A [ 339.661403] [drm:ironlake_write_eld], Audio directed to unknown port [ 339.661405] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 339.661419] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 339.661423] [drm:ironlake_check_srwm], watermark 1: display plane 21, fbc lines 3, cursor 6 [ 339.661426] [drm:ironlake_check_srwm], watermark 2: display plane 42, fbc lines 4, cursor 6 [ 339.713345] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 339.765322] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 339.765633] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 339.765633] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 339.765787] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 339.765788] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 339.765789] [drm:ironlake_fdi_link_train], FDI train done [ 339.765791] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 339.765792] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 339.767003] [drm:intel_update_fbc], [ 339.818263] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 339.818573] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 339.819493] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 339.820312] [drm:intel_dp_start_link_train], clock recovery OK [ 339.826106] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 339.826107] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 339.826161] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 339.827091] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 339.827092] [drm:intel_crt_detect], CRT not detected via hotplug [ 339.827094] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 339.828259] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 339.828263] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 339.828268] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 339.828580] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 339.829605] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 339.839678] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 339.856682] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 339.883771] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 339.883772] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 339.883774] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 344.855616] [drm:drm_mode_addfb], [FB:112] [ 344.855633] [drm:drm_mode_setcrtc], [CRTC:3] [ 344.855635] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 344.855636] [drm:drm_crtc_helper_set_config], [ 344.855637] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:112] #connectors=1 (x y) (0 0) [ 344.855643] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 344.855645] [drm:drm_mode_debug_printmodeline], Modeline 112:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 344.855647] [drm:drm_mode_debug_printmodeline], Modeline 113:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 344.855648] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 344.855650] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 344.855652] [drm:drm_mode_debug_printmodeline], Modeline 113:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 344.855654] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 25200KHz [ 344.855655] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 344.855657] [drm:intel_dp_mode_fixup], DP link bw required 60480 available 129600 [ 344.855658] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 344.855865] [drm:intel_dp_link_down], [ 344.926089] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 345.028072] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 345.032074] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 345.032078] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 345.032487] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 345.032489] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 345.032491] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6 [ 345.032492] [drm:intel_update_fbc], [ 345.032495] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 345.032496] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 345.032497] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 345.032499] [drm:drm_mode_debug_printmodeline], Modeline 113:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 345.032501] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 345.032502] [drm:intel_get_pch_pll], switching PLL c6014 off [ 345.084047] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 345.084056] [drm:ironlake_update_plane], Writing base 0D0A3000 00000000 0 0 2560 [ 345.136025] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 345.136030] [drm:intel_update_fbc], [ 345.136036] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 345.136041] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 345.136046] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6 [ 345.136051] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:113:640x480] [ 345.136056] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 345.136061] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 345.136064] [drm:ironlake_write_eld], ELD on pipe A [ 345.136068] [drm:ironlake_write_eld], Audio directed to unknown port [ 345.136071] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 345.136085] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 345.136090] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 345.136095] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6 [ 345.188003] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 345.239981] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 345.240291] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 345.240292] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 345.240446] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 345.240447] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 345.240448] [drm:ironlake_fdi_link_train], FDI train done [ 345.240449] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 345.240451] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 345.241662] [drm:intel_update_fbc], [ 345.292917] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 345.293227] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 345.294147] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 345.294966] [drm:intel_dp_start_link_train], clock recovery OK [ 345.300759] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 345.300760] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 345.300814] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 345.301744] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 345.301745] [drm:intel_crt_detect], CRT not detected via hotplug [ 345.301747] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 345.302913] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 345.302917] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 345.302922] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 345.303234] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 345.304259] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 345.317260] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 345.331311] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 345.358371] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 345.358373] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 345.358374] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 350.331260] [drm:drm_mode_addfb], [FB:113] [ 350.331277] [drm:drm_mode_setcrtc], [CRTC:3] [ 350.331279] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 350.331280] [drm:drm_crtc_helper_set_config], [ 350.331284] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:113] #connectors=1 (x y) (0 0) [ 350.331287] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 350.331289] [drm:drm_mode_debug_printmodeline], Modeline 113:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 350.331291] [drm:drm_mode_debug_printmodeline], Modeline 114:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 350.331293] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 350.331294] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 350.331296] [drm:drm_mode_debug_printmodeline], Modeline 114:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 350.331298] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 25175KHz [ 350.331300] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 350.331301] [drm:intel_dp_mode_fixup], DP link bw required 60420 available 129600 [ 350.331302] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 350.331509] [drm:intel_dp_link_down], [ 350.401766] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 350.503726] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 350.505665] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 350.505670] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 350.506078] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 350.506081] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 350.506082] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6 [ 350.506084] [drm:intel_update_fbc], [ 350.506087] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 350.506088] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 350.506089] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 350.506091] [drm:drm_mode_debug_printmodeline], Modeline 114:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 350.506092] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 350.506093] [drm:intel_get_pch_pll], switching PLL c6014 off [ 350.557702] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 350.557711] [drm:ironlake_update_plane], Writing base 0D1CF000 00000000 0 0 2560 [ 350.609680] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 350.609685] [drm:intel_update_fbc], [ 350.609691] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 350.609696] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 350.609701] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6 [ 350.609706] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:114:640x480] [ 350.609711] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 350.609716] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 350.609720] [drm:ironlake_write_eld], ELD on pipe A [ 350.609723] [drm:ironlake_write_eld], Audio directed to unknown port [ 350.609726] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 350.609740] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 350.609745] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 350.609749] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6 [ 350.661653] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 350.713632] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 350.713941] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 350.713942] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 350.714096] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 350.714097] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 350.714098] [drm:ironlake_fdi_link_train], FDI train done [ 350.714099] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 350.714101] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 350.715313] [drm:intel_update_fbc], [ 350.766606] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 350.766916] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 350.767836] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 350.768655] [drm:intel_dp_start_link_train], clock recovery OK [ 350.774447] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 350.774449] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 350.774504] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 350.775434] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 350.775435] [drm:intel_crt_detect], CRT not detected via hotplug [ 350.775436] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 350.776568] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 350.776572] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 350.776577] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 350.776888] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 350.777914] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 350.791008] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 350.805173] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 350.832233] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 350.832234] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 350.832236] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 355.803892] [drm:drm_mode_addfb], [FB:114] [ 355.803910] [drm:drm_mode_setcrtc], [CRTC:3] [ 355.803915] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 355.803916] [drm:drm_crtc_helper_set_config], [ 355.803917] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:114] #connectors=1 (x y) (0 0) [ 355.803920] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 355.803922] [drm:drm_mode_debug_printmodeline], Modeline 114:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 355.803924] [drm:drm_mode_debug_printmodeline], Modeline 115:"640x480" 60 25175 640 656 752 800 480 489 492 525 0x40 0xa [ 355.803926] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 355.803927] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 355.803929] [drm:drm_mode_debug_printmodeline], Modeline 115:"640x480" 60 25175 640 656 752 800 480 489 492 525 0x40 0xa [ 355.803931] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 25175KHz [ 355.803933] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 355.803934] [drm:intel_dp_mode_fixup], DP link bw required 60420 available 129600 [ 355.803936] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 355.804159] [drm:intel_dp_link_down], [ 355.874420] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 355.976376] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 355.978342] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 355.978346] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 355.978755] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 355.978757] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 355.978759] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6 [ 355.978760] [drm:intel_update_fbc], [ 355.978762] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 355.978764] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 355.978765] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 355.978767] [drm:drm_mode_debug_printmodeline], Modeline 115:"640x480" 60 25175 640 656 752 800 480 489 492 525 0x40 0xa [ 355.978768] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 355.978769] [drm:intel_get_pch_pll], switching PLL c6014 off [ 356.030354] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 356.030361] [drm:ironlake_update_plane], Writing base 0D2FB000 00000000 0 0 2560 [ 356.082331] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 356.082335] [drm:intel_update_fbc], [ 356.082340] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 356.082344] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 356.082348] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6 [ 356.082353] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:115:640x480] [ 356.082357] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 356.082361] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 356.082364] [drm:ironlake_write_eld], ELD on pipe A [ 356.082367] [drm:ironlake_write_eld], Audio directed to unknown port [ 356.082369] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 356.082383] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 356.082387] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 356.082391] [drm:ironlake_check_srwm], watermark 2: display plane 36, fbc lines 3, cursor 6 [ 356.134309] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 356.186286] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 356.186596] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 356.186597] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 356.186751] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 356.186752] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 356.186753] [drm:ironlake_fdi_link_train], FDI train done [ 356.186754] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 356.186756] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 356.187967] [drm:intel_update_fbc], [ 356.239226] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 356.239537] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 356.240457] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 356.241276] [drm:intel_dp_start_link_train], clock recovery OK [ 356.247069] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 356.247071] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 356.247126] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 356.248055] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 356.248057] [drm:intel_crt_detect], CRT not detected via hotplug [ 356.248058] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 356.249223] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 356.249227] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 356.249232] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 356.249544] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 356.250569] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 356.263587] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 356.277669] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 356.304735] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 356.304736] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 356.304738] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 361.273820] [drm:drm_mode_addfb], [FB:115] [ 361.273838] [drm:drm_mode_setcrtc], [CRTC:3] [ 361.273840] [drm:drm_mode_setcrtc], [CONNECTOR:13:DP-1] [ 361.273841] [drm:drm_crtc_helper_set_config], [ 361.273843] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:115] #connectors=1 (x y) (0 0) [ 361.273849] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 361.273851] [drm:drm_mode_debug_printmodeline], Modeline 115:"640x480" 60 25175 640 656 752 800 480 489 492 525 0x40 0xa [ 361.273853] [drm:drm_mode_debug_printmodeline], Modeline 116:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 361.273854] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 361.273856] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 361.273858] [drm:drm_mode_debug_printmodeline], Modeline 116:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 361.273860] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 28320KHz [ 361.273861] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 361.273863] [drm:intel_dp_mode_fixup], DP link bw required 67968 available 129600 [ 361.273864] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 361.274071] [drm:intel_dp_link_down], [ 361.345073] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 361.447033] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 361.448997] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 361.449002] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 361.449410] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 361.449412] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6 [ 361.449414] [drm:ironlake_check_srwm], watermark 2: display plane 40, fbc lines 3, cursor 6 [ 361.449415] [drm:intel_update_fbc], [ 361.449418] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 361.449419] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 361.449420] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 361.449422] [drm:drm_mode_debug_printmodeline], Modeline 116:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 361.449424] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 361.449425] [drm:intel_get_pch_pll], switching PLL c6014 off [ 361.501009] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 361.501016] [drm:ironlake_update_plane], Writing base 0D427000 00000000 0 0 2880 [ 361.552987] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 361.552991] [drm:intel_update_fbc], [ 361.552995] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 361.553000] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6 [ 361.553004] [drm:ironlake_check_srwm], watermark 2: display plane 40, fbc lines 3, cursor 6 [ 361.553008] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:116:720x400] [ 361.553012] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 361.553016] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 361.553019] [drm:ironlake_write_eld], ELD on pipe A [ 361.553022] [drm:ironlake_write_eld], Audio directed to unknown port [ 361.553024] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 361.553038] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 361.553042] [drm:ironlake_check_srwm], watermark 1: display plane 19, fbc lines 3, cursor 6 [ 361.553046] [drm:ironlake_check_srwm], watermark 2: display plane 40, fbc lines 3, cursor 6 [ 361.604962] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 361.656942] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 361.657252] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 361.657253] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 361.657407] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 361.657408] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 361.657409] [drm:ironlake_fdi_link_train], FDI train done [ 361.657410] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 361.657412] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 361.658624] [drm:intel_update_fbc], [ 361.709917] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 361.710227] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 361.711147] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 361.711965] [drm:intel_dp_start_link_train], clock recovery OK [ 361.717808] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 361.717810] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 361.717867] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 361.718798] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0 [ 361.718799] [drm:intel_crt_detect], CRT not detected via hotplug [ 361.718800] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 361.719879] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 361.719883] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 361.719888] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 361.720199] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 361.721225] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 361.731916] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 361.748403] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 361.775469] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 361.775471] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 361.775472] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 1 to 1 [ 366.715862] [drm:drm_crtc_helper_set_config], [ 366.715866] [drm:drm_crtc_helper_set_config], [CRTC:3] [NOFB] [ 366.716080] [drm:intel_dp_link_down], [ 366.734761] [drm:ironlake_crtc_dpms], crtc 0/0 dpms off [ 366.734766] [drm:i915_get_vblank_timestamp], crtc 0 is disabled [ 366.786742] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 366.888701] [drm:intel_wait_for_pipe_off], pipe_off wait timed out [ 366.892711] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 366.892715] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 366.893123] [drm:intel_update_fbc], [ 366.893128] [drm:drm_mode_setcrtc], [CRTC:3] [ 366.893129] [drm:drm_mode_setcrtc], Count connectors is 1 but no mode or fb set [ 366.996876] [drm:drm_crtc_helper_set_config], [ 366.996878] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:17] #connectors=1 (x y) (0 0) [ 366.996883] [drm:drm_crtc_helper_set_config], crtc has no fb, full mode set [ 366.996884] [drm:drm_crtc_helper_set_config], modes are different, full mode set [ 366.996887] [drm:drm_mode_debug_printmodeline], Modeline 116:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 366.996889] [drm:drm_mode_debug_printmodeline], Modeline 16:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [ 366.996890] [drm:drm_crtc_helper_set_config], encoder changed, full mode switch [ 366.996892] [drm:drm_crtc_helper_set_config], crtc changed, full mode switch [ 366.996893] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] to [CRTC:3] [ 366.996895] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 366.996897] [drm:drm_mode_debug_printmodeline], Modeline 16:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [ 366.996901] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz [ 366.996903] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 2 clock 270000 bpp 24 [ 366.996904] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 432000 [ 366.996906] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 366.997124] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 366.997125] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 366.997127] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 366.997128] [drm:drm_mode_debug_printmodeline], Modeline 16:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [ 366.997130] [drm:intel_get_pch_pll], CRTC:3 using pre-allocated PCH PLL c6014 [ 366.997131] [drm:intel_get_pch_pll], using pll 0 for pipe 0 [ 366.997132] [drm:intel_get_pch_pll], switching PLL c6014 off [ 367.048636] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 367.048646] [drm:ironlake_update_plane], Writing base 00043000 00000000 0 0 7680 [ 367.048651] [drm:intel_update_fbc], [ 367.048655] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6 [ 367.048661] [drm:ironlake_check_srwm], watermark 1: display plane 94, fbc lines 3, cursor 6 [ 367.048666] [drm:ironlake_check_srwm], watermark 2: display plane 209, fbc lines 4, cursor 10 [ 367.048672] [drm:drm_crtc_helper_set_mode], [ENCODER:14:TMDS-14] set [MODE:16:1920x1200] [ 367.048676] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 367.048682] [drm:intel_write_eld], ELD on [CONNECTOR:13:DP-1], [ENCODER:14:TMDS-14] [ 367.048686] [drm:ironlake_write_eld], ELD on pipe A [ 367.048689] [drm:ironlake_write_eld], Audio directed to unknown port [ 367.048692] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 367.048706] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6 [ 367.048711] [drm:ironlake_check_srwm], watermark 1: display plane 94, fbc lines 3, cursor 6 [ 367.048716] [drm:ironlake_check_srwm], watermark 2: display plane 209, fbc lines 4, cursor 10 [ 367.100614] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 367.152583] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 367.152894] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100 [ 367.152895] [drm:ironlake_fdi_link_train], FDI train 1 done. [ 367.153048] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600 [ 367.153049] [drm:ironlake_fdi_link_train], FDI train 2 done. [ 367.153050] [drm:ironlake_fdi_link_train], FDI train done [ 367.153052] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 367.153054] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 367.154265] [drm:intel_update_fbc], [ 367.205560] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 367.205869] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 367.206789] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 367.207608] [drm:intel_dp_start_link_train], clock recovery OK [ 367.213399] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 367.213400] [drm:drm_crtc_helper_set_config], [CONNECTOR:13:DP-1] set DPMS on [ 367.213408] [drm:drm_crtc_helper_set_config], [ 367.213409] [drm:drm_crtc_helper_set_config], [CRTC:5] [NOFB] [ 367.229932] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 623.422008] [drm:intel_dp_link_down], [ 623.440768] [drm:ironlake_crtc_dpms], crtc 0/0 dpms on