[   69.702788] [drm:i915_ring_stop_write], Stopping rings 0x0000000f
[   70.128584] [drm:i915_driver_open], 
[   70.129532] [drm:gen6_sanitize_pm] *ERROR* Power management discrepancy: GEN6_RP_INTERRUPT_LIMITS expected 12000000, was 12060000
[   76.138972] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
[   76.143053] [drm] capturing error event; look for more information in /debug/dri/0/i915_error_state
[   76.152268] kobject: 'card0' (ffff880148549a88): kobject_uevent_env
[   76.152396] kobject: 'card0' (ffff880148549a88): fill_kobj_path: path = '/devices/pci0000:00/0000:00:02.0/drm/card0'
[   76.153417] [drm:i915_error_work_func], resetting chip
[   76.153423] kobject: 'card0' (ffff880148549a88): kobject_uevent_env
[   76.153496] kobject: 'card0' (ffff880148549a88): fill_kobj_path: path = '/devices/pci0000:00/0000:00:02.0/drm/card0'
[   76.655465] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head 00000000 tail 00000000 start 00000000 gtt ofs 00001000
[   76.659639] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
[   76.659644] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
[   76.661779] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[   76.683417] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
[   76.683424] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
[   76.683867] kobject: 'card0' (ffff880148549a88): kobject_uevent_env
[   76.683946] kobject: 'card0' (ffff880148549a88): fill_kobj_path: path = '/devices/pci0000:00/0000:00:02.0/drm/card0'
[   76.685929] [drm:drm_crtc_helper_set_config], 
[   76.685934] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:23] #connectors=1 (x y) (0 0)
[   76.686103] [drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [CRTC:3]
[   76.686253] [drm:drm_crtc_helper_set_config], 
[   76.686256] [drm:drm_crtc_helper_set_config], [CRTC:5] [NOFB]
[   76.686275] [drm:drm_crtc_helper_set_config], 
[   76.686278] [drm:drm_crtc_helper_set_config], [CRTC:7] [NOFB]
[   76.686297] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
[   76.686302] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
[   76.686307] [drm:ironlake_check_srwm], watermark 2: display plane 87, fbc lines 3, cursor 6
[   76.686311] [drm:ironlake_check_srwm], watermark 3: display plane 184, fbc lines 4, cursor 10
[   76.686317] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
[   76.686322] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
[   76.686326] [drm:ironlake_check_srwm], watermark 2: display plane 87, fbc lines 3, cursor 6
[   76.686331] [drm:ironlake_check_srwm], watermark 3: display plane 184, fbc lines 4, cursor 10
[   76.686336] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
[   76.686341] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
[   76.686366] [drm:ironlake_check_srwm], watermark 2: display plane 87, fbc lines 3, cursor 6
[   76.686371] [drm:ironlake_check_srwm], watermark 3: display plane 184, fbc lines 4, cursor 10
[   76.686465] [drm:i915_driver_open], 
[   82.695767] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
[   82.699794] kobject: 'card0' (ffff880148549a88): kobject_uevent_env
[   82.699873] kobject: 'card0' (ffff880148549a88): fill_kobj_path: path = '/devices/pci0000:00/0000:00:02.0/drm/card0'
[   82.700546] [drm:i915_error_work_func], resetting chip
[   82.700552] kobject: 'card0' (ffff880148549a88): kobject_uevent_env
[   82.700627] kobject: 'card0' (ffff880148549a88): fill_kobj_path: path = '/devices/pci0000:00/0000:00:02.0/drm/card0'
[   83.202271] [drm:init_ring_common] *ERROR* render ring initialization failed ctl 00000000 head 00000000 tail 00000000 start 00000000 gtt ofs 00001000
[   83.206487] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
[   83.206492] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
[   83.208426] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[   83.230232] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
[   83.230239] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
[   83.230600] kobject: 'card0' (ffff880148549a88): kobject_uevent_env
[   83.230677] kobject: 'card0' (ffff880148549a88): fill_kobj_path: path = '/devices/pci0000:00/0000:00:02.0/drm/card0'
[   83.231724] [drm:gen6_sanitize_pm] *ERROR* Power management discrepancy: GEN6_RP_INTERRUPT_LIMITS expected 12080000, was 12060000
[   89.244581] [drm:i915_hangcheck_hung] *ERROR* Hangcheck timer elapsed... GPU hung
[   89.248887] kobject: 'card0' (ffff880148549a88): kobject_uevent_env
[   89.248962] kobject: 'card0' (ffff880148549a88): fill_kobj_path: path = '/devices/pci0000:00/0000:00:02.0/drm/card0'
[   89.249670] [drm:i915_error_work_func], resetting chip
[   89.249678] kobject: 'card0' (ffff880148549a88): kobject_uevent_env
[   89.249764] kobject: 'card0' (ffff880148549a88): fill_kobj_path: path = '/devices/pci0000:00/0000:00:02.0/drm/card0'
[   89.250717] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
[   89.250723] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
[   89.256590] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[   89.274576] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
[   89.274583] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
[   89.274943] kobject: 'card0' (ffff880148549a88): kobject_uevent_env
[   89.275021] kobject: 'card0' (ffff880148549a88): fill_kobj_path: path = '/devices/pci0000:00/0000:00:02.0/drm/card0'
[  128.925737] [drm:drm_crtc_helper_set_config], 
[  128.925741] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:23] #connectors=1 (x y) (0 0)
[  128.925843] [drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [CRTC:3]
[  128.925935] [drm:drm_crtc_helper_set_config], 
[  128.925937] [drm:drm_crtc_helper_set_config], [CRTC:5] [NOFB]
[  128.925987] [drm:drm_crtc_helper_set_config], 
[  128.925990] [drm:drm_crtc_helper_set_config], [CRTC:7] [NOFB]
[  128.926006] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
[  128.926010] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
[  128.926014] [drm:ironlake_check_srwm], watermark 2: display plane 87, fbc lines 3, cursor 6
[  128.926018] [drm:ironlake_check_srwm], watermark 3: display plane 184, fbc lines 4, cursor 10
[  128.926023] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
[  128.926026] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
[  128.926030] [drm:ironlake_check_srwm], watermark 2: display plane 87, fbc lines 3, cursor 6
[  128.926034] [drm:ironlake_check_srwm], watermark 3: display plane 184, fbc lines 4, cursor 10
[  128.926038] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
[  128.926042] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
[  128.926058] [drm:ironlake_check_srwm], watermark 2: display plane 87, fbc lines 3, cursor 6
[  128.926061] [drm:ironlake_check_srwm], watermark 3: display plane 184, fbc lines 4, cursor 10
[  128.985373] [drm:i915_error_state_write], Resetting error state