diff -urN a/src/mesa/drivers/dri/r200/r200_blit.c b/src/mesa/drivers/dri/r200/r200_blit.c --- a/src/mesa/drivers/dri/r200/r200_blit.c 2012-03-22 17:10:07.000000000 +0000 +++ b/src/mesa/drivers/dri/r200/r200_blit.c 2012-06-09 00:57:27.205853378 +0100 @@ -94,6 +94,10 @@ RADEON_ROUND_MODE_ROUND | RADEON_ROUND_PREC_4TH_PIX)); END_BATCH(); + + r200->hw.vtx.dirty = GL_TRUE; + r200->hw.vap.dirty = GL_TRUE; + r200->hw.vte.dirty = GL_TRUE; } static void inline emit_tx_setup(struct r200_context *r200, @@ -181,6 +185,7 @@ OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0)); END_BATCH(); + r200->hw.pix[0].dirty = GL_TRUE; break; case MESA_FORMAT_RGBA8888: BEGIN_BATCH(10); @@ -201,6 +206,7 @@ (R200_TXA_REPL_RED << R200_TXA_REPL_ARG_C_SHIFT) | R200_TXA_OUTPUT_REG_R0)); END_BATCH(); + r200->hw.pix[0].dirty = GL_TRUE; break; case MESA_FORMAT_RGBA8888_REV: BEGIN_BATCH(34); @@ -272,6 +278,10 @@ OUT_BATCH_REGVAL(R200_PP_TXABLEND2_3, (R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0)); END_BATCH(); + + for (int i = 0; i <= 3; i++) { + r200->hw.pix[i].dirty = GL_TRUE; + } break; } @@ -289,9 +299,13 @@ OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch * _mesa_get_format_bytes(src_mesa_format) - 32); OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1); + OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); END_BATCH(); + + r200->hw.ctx.dirty = GL_TRUE; + r200->hw.tex[0].dirty = GL_TRUE; } static inline void emit_cb_setup(struct r200_context *r200, @@ -353,6 +367,10 @@ OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); + + r200->hw.sci.dirty = GL_TRUE; + r200->hw.set.dirty = GL_TRUE; + r200->hw.msk.dirty = GL_TRUE; } static GLboolean validate_buffers(struct r200_context *r200,