From d6337d5770ae0e305188084e2637b66acff72353 Mon Sep 17 00:00:00 2001 From: Anisse Astier Date: Wed, 4 Jul 2012 10:49:06 +0200 Subject: [PATCH] gma500: fix display clock selection on some cdv devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some ODM-made CDV netbooks exhibit modesetting problems, the display clock isn't set at a proper rate. The problem seems to be that the code chooses a refclk at 27 MHz, while it should be at 96MHz (or 100 with an SSC). Setting to 96 MHz or 100 MHz both work. We can see that the variable is named dplla_96MHz; but pipe is set to 1, which means we use DPLLB. Also, on the datasheet "Intel® Atom™ Processor D2000 and N2000 Series, Vol. 1", Doc ID 326136-002, Table 4-28, we can see that DPLL0 is for frequency 27, 96, and 100, non SSC. While DPLL1 is for 100 SSC. Of course, it also states that DPLL0 and DPLL1 can use each other's reference clock internally, but we'll ignore that for the purpose of this patch. The conclusion is that if we're using pipe B, we'll set the clock to 96MHz, which we have tested to be identical to 100 MHz SSC. This should solve the problem in case the BIOS "forgot" to tell us to use SSC. Signed-off-by: Anisse Astier --- drivers/gpu/drm/gma500/cdv_intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c index c3e9a0f..8e5b2b2 100644 --- a/drivers/gpu/drm/gma500/cdv_intel_display.c +++ b/drivers/gpu/drm/gma500/cdv_intel_display.c @@ -980,7 +980,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, } } - if (dev_priv->dplla_96mhz) + if (dev_priv->dplla_96mhz || pipe != 0) /* low-end sku, 96/100 mhz */ refclk = 96000; else -- 1.7.10.3