{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf360
{\fonttbl\f0\fswiss\fcharset0 Helvetica;}
{\colortbl;\red255\green255\blue255;}
\paperw11900\paperh16840\margl1440\margr1440\vieww9000\viewh8400\viewkind0
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\f0\fs24 \cf0 belly@jelly ~/mesa $ DISPLAY=:0 LD_LIBRARY_PATH="/home/belly/mesa/lib64/" LIBGL_DRIVERS_PATH="/home/belly/mesa/lib64/gallium" LIBGL_DEBUG=verbose R600_DUMP_SHADERS=1 glxgears\
libGL: OpenDriver: trying /home/belly/mesa/lib64/gallium/tls/r600_dri.so\
libGL: OpenDriver: trying /home/belly/mesa/lib64/gallium/r600_dri.so\
libGL: Can't open configuration file /etc/drirc: No such file or directory.\
libGL: Can't open configuration file /home/belly/.drirc: No such file or directory.\
libGL: Can't open configuration file /etc/drirc: No such file or directory.\
libGL: Can't open configuration file /home/belly/.drirc: No such file or directory.\
--------------------------------------------------------------\
bytecode 12 dw -- 3 gprs ---------------------\
     6\
0000 00000002 TEX/VTX ADDR:4\
0001 81000400 TEX/VTX INST:0x2 COUNT:2\
0004 7C00A000   INST:0 FETCH_TYPE:0 BUFFER_ID:160\
0005 88CD1001   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)\
0006 00080000   ENDIAN:0 OFFSET:0\
0007 00000000   \
0008 7C00A000   INST:0 FETCH_TYPE:0 BUFFER_ID:160\
0009 88CD1002   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)\
0010 00080010   ENDIAN:0 OFFSET:16\
0011 00000000   \
0002 00000000 CF ADDR:0\
0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0\
--------------------------------------\
______________________________________________________________\
--------------------------------------------------------------\
bytecode 12 dw -- 3 gprs ---------------------\
     6\
0000 00000002 TEX/VTX ADDR:4\
0001 81000400 TEX/VTX INST:0x2 COUNT:2\
0004 7C00A000   INST:0 FETCH_TYPE:0 BUFFER_ID:160\
0005 88CD1001   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)\
0006 00080000   ENDIAN:0 OFFSET:0\
0007 00000000   \
0008 7C00A000   INST:0 FETCH_TYPE:0 BUFFER_ID:160\
0009 D88D1002   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:1 MODE:1)\
0010 00080010   ENDIAN:0 OFFSET:16\
0011 00000000   \
0002 00000000 CF ADDR:0\
0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0\
--------------------------------------\
______________________________________________________________\
--------------------------------------------------------------\
bytecode 12 dw -- 3 gprs ---------------------\
     6\
0000 00000002 TEX/VTX ADDR:4\
0001 81000400 TEX/VTX INST:0x2 COUNT:2\
0004 7C00A000   INST:0 FETCH_TYPE:0 BUFFER_ID:160\
0005 88CD1001   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:35 NUM:0 COMP:0 MODE:1)\
0006 00080000   ENDIAN:0 OFFSET:0\
0007 00000000   \
0008 7C00A000   INST:0 FETCH_TYPE:0 BUFFER_ID:160\
0009 988D1002   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:2 SEL_X:0 SEL_Y:1 SEL_Z:2 SEL_W:3) USE_CONST_FIELDS:0 FORMAT(DATA:34 NUM:1 COMP:0 MODE:1)\
0010 00080010   ENDIAN:0 OFFSET:16\
0011 00000000   \
0002 00000000 CF ADDR:0\
0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0\
--------------------------------------\
______________________________________________________________\
--------------------------------------------------------------\
bytecode 8 dw -- 2 gprs ---------------------\
     6\
0000 00000002 TEX/VTX ADDR:4\
0001 81000000 TEX/VTX INST:0x2 COUNT:1\
0004 7C00A000   INST:0 FETCH_TYPE:0 BUFFER_ID:160\
0005 93564001   SRC(GPR:0 SEL_X:0) MEGA_FETCH_COUNT:31 DST(GPR:1 SEL_X:0 SEL_Y:4 SEL_Z:4 SEL_W:5) USE_CONST_FIELDS:0 FORMAT(DATA:13 NUM:1 COMP:0 MODE:1)\
0006 00080000   ENDIAN:0 OFFSET:0\
0007 00000000   \
0002 00000000 CF ADDR:0\
0003 8A000000 CF INST:0x14 COND:0 POP_COUNT:0\
--------------------------------------\
______________________________________________________________\
--------------------------------------------------------------\
VERT\
DCL IN[0]\
DCL IN[1]\
DCL OUT[0], POSITION\
DCL OUT[1], GENERIC[0]\
  0: MOV OUT[0], IN[0]\
  1: MOV OUT[1], IN[1]\
  2: END\
; ModuleID = 'tgsi'\
\
define void @main() \{\
main_body:\
  call void @llvm.AMDGPU.reserve.reg(i32 0)\
  call void @llvm.AMDGPU.reserve.reg(i32 1)\
  call void @llvm.AMDGPU.reserve.reg(i32 2)\
  call void @llvm.AMDGPU.reserve.reg(i32 3)\
  %0 = call float @llvm.R600.load.input(i32 4)\
  %1 = call float @llvm.R600.load.input(i32 5)\
  %2 = call float @llvm.R600.load.input(i32 6)\
  %3 = call float @llvm.R600.load.input(i32 7)\
  %4 = call float @llvm.R600.load.input(i32 8)\
  %5 = call float @llvm.R600.load.input(i32 9)\
  %6 = call float @llvm.R600.load.input(i32 10)\
  %7 = call float @llvm.R600.load.input(i32 11)\
  call void @llvm.AMDGPU.store.output(float %0, i32 4)\
  call void @llvm.AMDGPU.store.output(float %1, i32 5)\
  call void @llvm.AMDGPU.store.output(float %2, i32 6)\
  call void @llvm.AMDGPU.store.output(float %3, i32 7)\
  call void @llvm.AMDGPU.store.output(float %4, i32 8)\
  call void @llvm.AMDGPU.store.output(float %5, i32 9)\
  call void @llvm.AMDGPU.store.output(float %6, i32 10)\
  call void @llvm.AMDGPU.store.output(float %7, i32 11)\
  ret void\
\}\
\
declare void @llvm.AMDGPU.reserve.reg(i32)\
\
declare float @llvm.R600.load.input(i32) readnone\
\
declare void @llvm.AMDGPU.store.output(float, i32)\
# Machine code for function main: Post SSA, not tracking liveness\
Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7\
Function Live Outs: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X\
\
BB#0: derived from LLVM BB %main_body\
    Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X\
	RETURN %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>, %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>\
\
# End machine code for function main.\
\
bytecode 6 dw -- 3 gprs ---------------------\
     6\
0000 00000000 CF ADDR:0\
0001 89800000 CF INST:0x13 COND:0 POP_COUNT:0\
0002 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1\
0003 94000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:0\
0004 C0014000 EXPORT GPR:2 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2\
0005 94200688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1\
--------------------------------------\
______________________________________________________________\
--------------------------------------------------------------\
VERT\
DCL IN[0]\
DCL OUT[0], POSITION\
  0: MOV OUT[0], IN[0]\
  1: END\
STREAMOUT\
  0: MEM_STREAM0_BUF0 OUT[0].x___\
; ModuleID = 'tgsi'\
\
define void @main() \{\
main_body:\
  call void @llvm.AMDGPU.reserve.reg(i32 0)\
  call void @llvm.AMDGPU.reserve.reg(i32 1)\
  call void @llvm.AMDGPU.reserve.reg(i32 2)\
  call void @llvm.AMDGPU.reserve.reg(i32 3)\
  %0 = call float @llvm.R600.load.input(i32 4)\
  %1 = call float @llvm.R600.load.input(i32 5)\
  %2 = call float @llvm.R600.load.input(i32 6)\
  %3 = call float @llvm.R600.load.input(i32 7)\
  call void @llvm.AMDGPU.store.output(float %0, i32 4)\
  call void @llvm.AMDGPU.store.output(float %1, i32 5)\
  call void @llvm.AMDGPU.store.output(float %2, i32 6)\
  call void @llvm.AMDGPU.store.output(float %3, i32 7)\
  ret void\
\}\
\
declare void @llvm.AMDGPU.reserve.reg(i32)\
\
declare float @llvm.R600.load.input(i32) readnone\
\
declare void @llvm.AMDGPU.store.output(float, i32)\
# Machine code for function main: Post SSA, not tracking liveness\
Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3\
Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X\
\
BB#0: derived from LLVM BB %main_body\
    Live Ins: %T1_W %T1_Z %T1_Y %T1_X\
	RETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>\
\
# End machine code for function main.\
\
bytecode 8 dw -- 2 gprs ---------------------\
     6\
0000 00000000 CF ADDR:0\
0001 89800000 CF INST:0x13 COND:0 POP_COUNT:0\
0002 00008000 EXPORT MEM_STREAM0 GPR:1 ELEM_SIZE:0 ARRAY_BASE:0 TYPE:0\
0003 90001FFF EXPORT MEM_STREAM0 ARRAY_SIZE:4095 COMP_MASK:1 BARRIER:1 INST:268435456 BURST_COUNT:1 EOP:0\
0004 C000A03C EXPORT GPR:1 ELEM_SIZE:3 ARRAY_BASE:3C TYPE:1\
0005 94000688 EXPORT SWIZ_X:0 SWIZ_Y:1 SWIZ_Z:2 SWIZ_W:3 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:0\
0006 C0004000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:2\
0007 94200FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1\
--------------------------------------\
______________________________________________________________\
--------------------------------------------------------------\
FRAG\
DCL IN[0], GENERIC[0], CONSTANT\
  0: END\
; ModuleID = 'tgsi'\
\
define void @main() \{\
main_body:\
  %0 = call float @llvm.R600.load.input(i32 0)\
  %1 = call float @llvm.R600.load.input(i32 1)\
  %2 = call float @llvm.R600.load.input(i32 2)\
  %3 = call float @llvm.R600.load.input(i32 3)\
  ret void\
\}\
\
declare float @llvm.R600.load.input(i32) readnone\
# Machine code for function main: Post SSA, not tracking liveness\
\
BB#0: derived from LLVM BB %main_body\
	RETURN\
\
# End machine code for function main.\
\
bytecode 2 dw -- 1 gprs ---------------------\
     6\
0000 C0000000 EXPORT GPR:0 ELEM_SIZE:3 ARRAY_BASE:0 TYPE:0\
0001 94200FFF EXPORT SWIZ_X:7 SWIZ_Y:7 SWIZ_Z:7 SWIZ_W:7 BARRIER:1 INST:0x28 BURST_COUNT:1 EOP:1\
--------------------------------------\
______________________________________________________________\
Running synchronized to the vertical refresh.  The framerate should be\
approximately the same as the monitor refresh rate.\
--------------------------------------------------------------\
FRAG\
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1\
DCL IN[0], COLOR, COLOR\
DCL OUT[0], COLOR\
  0: MOV_SAT OUT[0], IN[0]\
  1: END\
; ModuleID = 'tgsi'\
\
define void @main() \{\
main_body:\
  %0 = call float @llvm.R600.load.input(i32 0)\
  %1 = call float @llvm.R600.load.input(i32 1)\
  %2 = call float @llvm.R600.load.input(i32 2)\
  %3 = call float @llvm.R600.load.input(i32 3)\
  %4 = call float @llvm.AMDIL.clamp.(float %0, float 0.000000e+00, float 1.000000e+00)\
  %5 = call float @llvm.AMDIL.clamp.(float %1, float 0.000000e+00, float 1.000000e+00)\
  %6 = call float @llvm.AMDIL.clamp.(float %2, float 0.000000e+00, float 1.000000e+00)\
  %7 = call float @llvm.AMDIL.clamp.(float %3, float 0.000000e+00, float 1.000000e+00)\
  call void @llvm.AMDGPU.store.output(float %4, i32 0)\
  call void @llvm.AMDGPU.store.output(float %5, i32 1)\
  call void @llvm.AMDGPU.store.output(float %6, i32 2)\
  call void @llvm.AMDGPU.store.output(float %7, i32 3)\
  ret void\
\}\
\
declare float @llvm.R600.load.input(i32) readnone\
\
declare float @llvm.AMDIL.clamp.(float, float, float) readnone\
\
declare void @llvm.AMDGPU.store.output(float, i32)\
# Machine code for function main: Post SSA, not tracking liveness\
Function Live Ins: %T0_W in %vreg0, %T0_Z in %vreg1, %T0_Y in %vreg2, %T0_X in %vreg3\
Function Live Outs: %T0_W %T0_Z %T0_Y %T0_X\
\
BB#0: derived from LLVM BB %main_body\
    Live Ins: %T0_W %T0_Z %T0_Y %T0_X\
	%T0_X<def> = MOV %T0_X<kill>, 1, pred:%PRED_SEL_OFF\
	%T0_Y<def> = MOV %T0_Y<kill>, 1, pred:%PRED_SEL_OFF\
	%T0_Z<def> = MOV %T0_Z<kill>, 1, pred:%PRED_SEL_OFF\
	%T0_W<def> = MOV %T0_W<kill>, 1, pred:%PRED_SEL_OFF\
	RETURN %T0_W<imp-use,kill>, %T0_Z<imp-use,kill>, %T0_Y<imp-use,kill>, %T0_X<imp-use,kill>\
\
# End machine code for function main.\
\
EE r600_asm.c:121 r600_bytecode_get_num_operands - Need instruction operand number for 0xc.\
EE r600_asm.c:121 r600_bytecode_get_num_operands - Need instruction operand number for 0xc.\
EE r600_asm.c:121 r600_bytecode_get_num_operands - Need instruction operand number for 0xc.\
EE r600_asm.c:121 r600_bytecode_get_num_operands - Need instruction operand number for 0xc.\
\'85\
\'85}