[ 7.946932] [drm:radeon_pm_print_states], 4 Power State(s) [ 7.946934] [drm:radeon_pm_print_states], State 0: Default [ 7.946935] [drm:radeon_pm_print_states], Default [ 7.946936] [drm:radeon_pm_print_states], [ 7.946938] [drm:radeon_pm_print_states], 3 Clock Mode(s) [ 7.946939] [drm:radeon_pm_print_states], 0 e: 900000 m: 1050000 v: 1175 No display only [ 7.946940] [drm:radeon_pm_print_states], 1 e: 900000 m: 1050000 v: 1175 [ 7.946942] [drm:radeon_pm_print_states], 2 e: 900000 m: 1050000 v: 1175 [ 7.946943] [drm:radeon_pm_print_states], State 1: Performance [ 7.946944] [drm:radeon_pm_print_states], 16 PCIE Lanes [ 7.946945] [drm:radeon_pm_print_states], 3 Clock Mode(s) [ 7.946946] [drm:radeon_pm_print_states], 0 e: 100000 m: 150000 v: 950 No display only [ 7.946947] [drm:radeon_pm_print_states], 1 e: 775000 m: 1050000 v: 1100 [ 7.946948] [drm:radeon_pm_print_states], 2 e: 900000 m: 1050000 v: 1175 [ 7.946950] [drm:radeon_pm_print_states], State 2: Default [ 7.946950] [drm:radeon_pm_print_states], 16 PCIE Lanes [ 7.946951] [drm:radeon_pm_print_states], 3 Clock Mode(s) [ 7.946952] [drm:radeon_pm_print_states], 0 e: 300000 m: 1050000 v: 950 No display only [ 7.946953] [drm:radeon_pm_print_states], 1 e: 300000 m: 1050000 v: 950 [ 7.946955] [drm:radeon_pm_print_states], 2 e: 900000 m: 1050000 v: 1175 [ 7.946956] [drm:radeon_pm_print_states], State 3: Default [ 7.946957] [drm:radeon_pm_print_states], 16 PCIE Lanes [ 7.946958] [drm:radeon_pm_print_states], 3 Clock Mode(s) [ 7.946959] [drm:radeon_pm_print_states], 0 e: 600000 m: 1050000 v: 1000 No display only [ 7.946960] [drm:radeon_pm_print_states], 1 e: 600000 m: 1050000 v: 1000 [ 7.946961] [drm:radeon_pm_print_states], 2 e: 900000 m: 1050000 v: 1175