From: Egbert Eich Date: Tue Oct 9 16:48:46 2012 +0200 Subject: On GEN2 map GTT Aperture non-cached. Git-commit: cd2d616af9825e8b0986d7d26d25209ed80b9d72 Signed-off-by: Egbert Eich On GEN2 the GTT aperture sits on the same BAR as the MMIO registers right in the middle of that range. The Intel driver maps the entire BAR uncached to have access to all registers. This does not work if the intel-gtt module has mapped the GTT aperture WC. A simple workaround is to map the GTT uncached also. Signed-off-by: Egbert Eich --- drivers/char/agp/intel-gtt.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index e01f5ea..797af72 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -667,7 +667,7 @@ static int intel_gtt_init(void) gtt_map_size = intel_private.base.gtt_total_entries * 4; intel_private.gtt = NULL; - if (INTEL_GTT_GEN < 6) + if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN != 2) intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr, gtt_map_size); if (intel_private.gtt == NULL)