[ 355.664829] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6 [ 355.664832] [drm:ironlake_check_srwm], watermark 3: display plane 73, fbc lines 3, cursor 6 [ 355.664838] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 355.664841] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 355.664843] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 355.664844] [drm:drm_mode_debug_printmodeline], Modeline 90:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6 [ 355.664848] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 355.664850] [drm:intel_get_pch_pll], switching PLL c6014 off [ 355.716325] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 355.718430] [drm:ironlake_update_plane], Writing base 088C7000 00000000 0 0 5120 [ 355.770237] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 355.770244] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 355.770256] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6 [ 355.770258] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 355.770261] [drm:ironlake_check_srwm], watermark 3: display plane 57, fbc lines 3, cursor 6 [ 355.770264] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:90:1280x768] [ 355.770268] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 355.770271] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 355.770273] [drm:ironlake_write_eld], ELD on pipe A [ 355.770276] [drm:ironlake_write_eld], Audio directed to unknown port [ 355.770278] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 355.770294] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 355.770297] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6 [ 355.770299] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 355.770302] [drm:ironlake_check_srwm], watermark 3: display plane 57, fbc lines 3, cursor 6 [ 355.822192] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 355.874109] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 355.874935] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 355.874939] [drm:gen6_fdi_link_train], FDI train 1 done. [ 355.875595] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 355.875598] [drm:gen6_fdi_link_train], FDI train 2 done. [ 355.875600] [drm:gen6_fdi_link_train], FDI train done. [ 355.875602] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 355.875605] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 355.877256] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 355.878192] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 355.879033] [drm:intel_dp_start_link_train], clock recovery OK [ 355.901497] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 355.903103] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 355.903110] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 355.903114] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 355.903117] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 355.903121] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 355.903124] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 355.903127] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 355.903131] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 355.903135] [drm:intel_modeset_check_state], [CRTC:3] [ 355.903136] [drm:intel_modeset_check_state], [CRTC:5] [ 365.942755] [drm:drm_mode_addfb], [FB:90] [ 365.942804] [drm:drm_mode_setcrtc], [CRTC:3] [ 365.942809] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 365.942812] [drm:intel_crtc_set_config], [CRTC:3] [FB:90] #connectors=1 (x y) (0 0) [ 365.942815] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 365.942817] [drm:drm_mode_debug_printmodeline], Modeline 90:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6 [ 365.942821] [drm:drm_mode_debug_printmodeline], Modeline 91:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 365.942824] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 365.942827] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 365.942828] [drm:drm_mode_debug_printmodeline], Modeline 91:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 365.942831] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 365.942835] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz [ 365.942837] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24 [ 365.942840] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 259200 [ 365.942842] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 365.943056] [drm:intel_dp_link_down], [ 365.976890] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 366.012006] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 366.012020] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 366.012432] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 366.012435] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6 [ 366.012437] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 366.012440] [drm:ironlake_check_srwm], watermark 3: display plane 57, fbc lines 3, cursor 6 [ 366.012446] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 366.012449] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 366.012451] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 366.012453] [drm:drm_mode_debug_printmodeline], Modeline 91:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 366.012456] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 366.012458] [drm:intel_get_pch_pll], switching PLL c6014 off [ 366.063936] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 366.065895] [drm:ironlake_update_plane], Writing base 08C87000 00000000 0 0 5120 [ 366.117854] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 366.117862] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 366.117873] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6 [ 366.117876] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 366.117878] [drm:ironlake_check_srwm], watermark 3: display plane 54, fbc lines 3, cursor 6 [ 366.117881] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:91:1280x720] [ 366.117885] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 366.117888] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 366.117890] [drm:ironlake_write_eld], ELD on pipe A [ 366.117893] [drm:ironlake_write_eld], Audio directed to unknown port [ 366.117895] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 366.117912] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 366.117914] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6 [ 366.117916] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 366.117919] [drm:ironlake_check_srwm], watermark 3: display plane 54, fbc lines 3, cursor 6 [ 366.169796] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 366.221721] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 366.222548] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 366.222551] [drm:gen6_fdi_link_train], FDI train 1 done. [ 366.223208] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 366.223211] [drm:gen6_fdi_link_train], FDI train 2 done. [ 366.223213] [drm:gen6_fdi_link_train], FDI train done. [ 366.223214] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 366.223218] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 366.224869] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 366.225807] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 366.226641] [drm:intel_dp_start_link_train], clock recovery OK [ 366.252400] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 366.252692] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 366.252701] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 366.252705] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 366.252709] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 366.252712] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 366.252718] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 366.252721] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 366.252726] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 366.252729] [drm:intel_modeset_check_state], [CRTC:3] [ 366.252731] [drm:intel_modeset_check_state], [CRTC:5] [ 376.292384] [drm:drm_mode_addfb], [FB:91] [ 376.292432] [drm:drm_mode_setcrtc], [CRTC:3] [ 376.292438] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 376.292440] [drm:intel_crtc_set_config], [CRTC:3] [FB:91] #connectors=1 (x y) (0 0) [ 376.292444] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 376.292445] [drm:drm_mode_debug_printmodeline], Modeline 91:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 376.292449] [drm:drm_mode_debug_printmodeline], Modeline 92:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 376.292452] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 376.292455] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 376.292457] [drm:drm_mode_debug_printmodeline], Modeline 92:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 376.292460] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 376.292463] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz [ 376.292466] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24 [ 376.292468] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 259200 [ 376.292470] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 376.292683] [drm:intel_dp_link_down], [ 376.319305] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 376.359609] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 376.359624] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 376.360036] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 376.360039] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6 [ 376.360042] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 376.360044] [drm:ironlake_check_srwm], watermark 3: display plane 54, fbc lines 3, cursor 6 [ 376.360051] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 376.360053] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 376.360055] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 376.360057] [drm:drm_mode_debug_printmodeline], Modeline 92:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 376.360061] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 376.360062] [drm:intel_get_pch_pll], switching PLL c6014 off [ 376.411542] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 376.413513] [drm:ironlake_update_plane], Writing base 0900B000 00000000 0 0 5120 [ 376.465474] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 376.465481] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 376.465492] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6 [ 376.465495] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 376.465498] [drm:ironlake_check_srwm], watermark 3: display plane 54, fbc lines 3, cursor 6 [ 376.465501] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:92:1280x720] [ 376.465505] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 376.465507] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 376.465510] [drm:ironlake_write_eld], ELD on pipe A [ 376.465513] [drm:ironlake_write_eld], Audio directed to unknown port [ 376.465514] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 376.465531] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 376.465533] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6 [ 376.465536] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 376.465538] [drm:ironlake_check_srwm], watermark 3: display plane 54, fbc lines 3, cursor 6 [ 376.517410] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 376.569341] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 376.570168] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 376.570172] [drm:gen6_fdi_link_train], FDI train 1 done. [ 376.570827] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 376.570831] [drm:gen6_fdi_link_train], FDI train 2 done. [ 376.570832] [drm:gen6_fdi_link_train], FDI train done. [ 376.570834] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 376.570838] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 376.572492] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 376.573431] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 376.574264] [drm:intel_dp_start_link_train], clock recovery OK [ 376.596690] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 376.598313] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 376.598320] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 376.598324] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 376.598327] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 376.598330] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 376.598334] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 376.598337] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 376.598341] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 376.598345] [drm:intel_modeset_check_state], [CRTC:3] [ 376.598346] [drm:intel_modeset_check_state], [CRTC:5] [ 386.636917] [drm:drm_mode_addfb], [FB:92] [ 386.636963] [drm:drm_mode_setcrtc], [CRTC:3] [ 386.636969] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 386.636972] [drm:intel_crtc_set_config], [CRTC:3] [FB:92] #connectors=1 (x y) (0 0) [ 386.636975] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 386.636977] [drm:drm_mode_debug_printmodeline], Modeline 92:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 386.636980] [drm:drm_mode_debug_printmodeline], Modeline 93:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 386.636984] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 386.636986] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 386.636988] [drm:drm_mode_debug_printmodeline], Modeline 93:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 386.636991] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 386.636995] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 78800KHz [ 386.636997] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24 [ 386.636999] [drm:intel_dp_mode_fixup], DP link bw required 189120 available 259200 [ 386.637002] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 386.637215] [drm:intel_dp_link_down], [ 386.666925] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 386.701214] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 386.701226] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 386.701639] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 386.701642] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6 [ 386.701644] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 386.701647] [drm:ironlake_check_srwm], watermark 3: display plane 54, fbc lines 3, cursor 6 [ 386.701653] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 386.701656] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 386.701658] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 386.701660] [drm:drm_mode_debug_printmodeline], Modeline 93:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 386.701663] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 386.701665] [drm:intel_get_pch_pll], switching PLL c6014 off [ 386.753162] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 386.754830] [drm:ironlake_update_plane], Writing base 0938F000 00000000 0 0 4096 [ 386.806093] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 386.806101] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 386.806111] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6 [ 386.806114] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 386.806117] [drm:ironlake_check_srwm], watermark 3: display plane 57, fbc lines 3, cursor 6 [ 386.806120] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:93:1024x768] [ 386.806123] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 386.806125] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 386.806128] [drm:ironlake_write_eld], ELD on pipe A [ 386.806131] [drm:ironlake_write_eld], Audio directed to unknown port [ 386.806133] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 386.806149] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 386.806152] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6 [ 386.806154] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 386.806156] [drm:ironlake_check_srwm], watermark 3: display plane 57, fbc lines 3, cursor 6 [ 386.858021] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 386.909959] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 386.910785] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 386.910788] [drm:gen6_fdi_link_train], FDI train 1 done. [ 386.911444] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 386.911448] [drm:gen6_fdi_link_train], FDI train 2 done. [ 386.911449] [drm:gen6_fdi_link_train], FDI train done. [ 386.911451] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 386.911455] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 386.913110] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 386.914047] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 386.914883] [drm:intel_dp_start_link_train], clock recovery OK [ 386.933967] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 386.934913] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 386.934929] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 386.934933] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 386.934938] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 386.934941] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 386.934946] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 386.934949] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 386.934955] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 386.934958] [drm:intel_modeset_check_state], [CRTC:3] [ 386.934960] [drm:intel_modeset_check_state], [CRTC:5] [ 396.973555] [drm:drm_mode_addfb], [FB:93] [ 396.973603] [drm:drm_mode_setcrtc], [CRTC:3] [ 396.973609] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 396.973611] [drm:intel_crtc_set_config], [CRTC:3] [FB:93] #connectors=1 (x y) (0 0) [ 396.973615] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 396.973617] [drm:drm_mode_debug_printmodeline], Modeline 93:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 396.973620] [drm:drm_mode_debug_printmodeline], Modeline 94:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 396.973624] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 396.973626] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 396.973628] [drm:drm_mode_debug_printmodeline], Modeline 94:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 396.973631] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 396.973634] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 75000KHz [ 396.973637] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24 [ 396.973639] [drm:intel_dp_mode_fixup], DP link bw required 180000 available 259200 [ 396.973641] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 396.973854] [drm:intel_dp_link_down], [ 397.003913] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 397.031862] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 397.031877] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 397.032289] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 397.032292] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6 [ 397.032295] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 397.032297] [drm:ironlake_check_srwm], watermark 3: display plane 57, fbc lines 3, cursor 6 [ 397.032303] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 397.032305] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 397.032308] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 397.032309] [drm:drm_mode_debug_printmodeline], Modeline 94:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 397.032312] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 397.032315] [drm:intel_get_pch_pll], switching PLL c6014 off [ 397.083788] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 397.085452] [drm:ironlake_update_plane], Writing base 0968F000 00000000 0 0 4096 [ 397.136721] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 397.136728] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 397.136740] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6 [ 397.136742] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 397.136745] [drm:ironlake_check_srwm], watermark 3: display plane 54, fbc lines 3, cursor 6 [ 397.136748] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:94:1024x768] [ 397.136752] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 397.136754] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 397.136757] [drm:ironlake_write_eld], ELD on pipe A [ 397.136760] [drm:ironlake_write_eld], Audio directed to unknown port [ 397.136762] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 397.136778] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 397.136781] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6 [ 397.136783] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 397.136785] [drm:ironlake_check_srwm], watermark 3: display plane 54, fbc lines 3, cursor 6 [ 397.188649] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 397.240590] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 397.241417] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 397.241420] [drm:gen6_fdi_link_train], FDI train 1 done. [ 397.242077] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 397.242080] [drm:gen6_fdi_link_train], FDI train 2 done. [ 397.242082] [drm:gen6_fdi_link_train], FDI train done. [ 397.242083] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 397.242087] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 397.243741] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 397.244681] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 397.245514] [drm:intel_dp_start_link_train], clock recovery OK [ 397.265541] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 397.265570] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 397.265579] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 397.265591] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 397.265595] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 397.265598] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 397.265601] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 397.265605] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 397.265609] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 397.265612] [drm:intel_modeset_check_state], [CRTC:3] [ 397.265614] [drm:intel_modeset_check_state], [CRTC:5] [ 397.265651] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 397.266608] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40000, result 0 [ 397.266611] [drm:intel_crt_detect], CRT not detected via hotplug [ 397.267014] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb [ 397.267017] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] [ 397.267019] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 397.267420] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb [ 397.267423] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 397.269979] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 397.274062] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 397.278054] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 397.279495] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 397.279500] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 2 to 2 [ 397.281503] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 397.281510] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 397.281515] [drm:output_poll_execute], [CONNECTOR:16:HDMI-A-2] status updated from 2 to 2 [ 397.283501] [drm:gmbus_xfer], GMBUS [i915 gmbus dpd] NAK for addr: 0050 r(1) [ 397.283508] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpd [ 397.283512] [drm:output_poll_execute], [CONNECTOR:18:HDMI-A-3] status updated from 2 to 2 [ 397.283838] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 397.284885] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 397.312432] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 397.339979] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 397.339982] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 397.339984] [drm:output_poll_execute], [CONNECTOR:19:DP-2] status updated from 1 to 1 [ 397.342541] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 397.346971] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 397.350964] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 397.352405] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 397.352410] [drm:output_poll_execute], [CONNECTOR:21:DP-3] status updated from 2 to 2 [ 407.304318] [drm:drm_mode_addfb], [FB:94] [ 407.304365] [drm:drm_mode_setcrtc], [CRTC:3] [ 407.304371] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 407.304374] [drm:intel_crtc_set_config], [CRTC:3] [FB:94] #connectors=1 (x y) (0 0) [ 407.304377] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 407.304379] [drm:drm_mode_debug_printmodeline], Modeline 94:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 407.304383] [drm:drm_mode_debug_printmodeline], Modeline 95:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 407.304386] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 407.304389] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 407.304391] [drm:drm_mode_debug_printmodeline], Modeline 95:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 407.304394] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 407.304397] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 65000KHz [ 407.304400] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24 [ 407.304402] [drm:intel_dp_mode_fixup], DP link bw required 156000 available 259200 [ 407.304404] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 407.304629] [drm:intel_dp_link_down], [ 407.328175] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 407.357500] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 407.357514] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 407.357926] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 407.357929] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6 [ 407.357932] [drm:ironlake_check_srwm], watermark 2: display plane 12, fbc lines 3, cursor 6 [ 407.357934] [drm:ironlake_check_srwm], watermark 3: display plane 54, fbc lines 3, cursor 6 [ 407.357940] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 407.357943] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 407.357945] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 407.357947] [drm:drm_mode_debug_printmodeline], Modeline 95:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 407.357950] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 407.357952] [drm:intel_get_pch_pll], switching PLL c6014 off [ 407.409426] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 407.411091] [drm:ironlake_update_plane], Writing base 0998F000 00000000 0 0 4096 [ 407.462340] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 407.462348] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6 [ 407.462360] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6 [ 407.462362] [drm:ironlake_check_srwm], watermark 2: display plane 11, fbc lines 3, cursor 6 [ 407.462365] [drm:ironlake_check_srwm], watermark 3: display plane 47, fbc lines 3, cursor 6 [ 407.462368] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:95:1024x768] [ 407.462372] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 407.462374] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 407.462377] [drm:ironlake_write_eld], ELD on pipe A [ 407.462379] [drm:ironlake_write_eld], Audio directed to unknown port [ 407.462381] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 407.462398] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6 [ 407.462400] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6 [ 407.462403] [drm:ironlake_check_srwm], watermark 2: display plane 11, fbc lines 3, cursor 6 [ 407.462405] [drm:ironlake_check_srwm], watermark 3: display plane 47, fbc lines 3, cursor 6 [ 407.514295] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 407.566206] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 407.567033] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 407.567037] [drm:gen6_fdi_link_train], FDI train 1 done. [ 407.567693] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 407.567697] [drm:gen6_fdi_link_train], FDI train 2 done. [ 407.567698] [drm:gen6_fdi_link_train], FDI train done. [ 407.567700] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 407.567703] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 407.569354] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 407.570292] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 407.571126] [drm:intel_dp_start_link_train], clock recovery OK [ 407.593537] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 407.595190] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 407.595197] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 407.595201] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 407.595204] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 407.595208] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 407.595211] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 407.595214] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 407.595218] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 407.595222] [drm:intel_modeset_check_state], [CRTC:3] [ 407.595224] [drm:intel_modeset_check_state], [CRTC:5] [ 417.630048] [drm:drm_mode_addfb], [FB:95] [ 417.630096] [drm:drm_mode_setcrtc], [CRTC:3] [ 417.630102] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 417.630104] [drm:intel_crtc_set_config], [CRTC:3] [FB:95] #connectors=1 (x y) (0 0) [ 417.630108] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 417.630109] [drm:drm_mode_debug_printmodeline], Modeline 95:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 417.630113] [drm:drm_mode_debug_printmodeline], Modeline 96:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6 [ 417.630117] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 417.630119] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 417.630121] [drm:drm_mode_debug_printmodeline], Modeline 96:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6 [ 417.630124] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 417.630127] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 46970KHz [ 417.630130] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 417.630132] [drm:intel_dp_mode_fixup], DP link bw required 112728 available 129600 [ 417.630134] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 417.630347] [drm:intel_dp_link_down], [ 417.663140] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 417.697096] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 417.697110] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 417.697522] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6 [ 417.697525] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6 [ 417.697528] [drm:ironlake_check_srwm], watermark 2: display plane 11, fbc lines 3, cursor 6 [ 417.697530] [drm:ironlake_check_srwm], watermark 3: display plane 47, fbc lines 3, cursor 6 [ 417.697536] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 417.697539] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 417.697541] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 417.697543] [drm:drm_mode_debug_printmodeline], Modeline 96:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6 [ 417.697546] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 417.697548] [drm:intel_get_pch_pll], switching PLL c6014 off [ 417.749046] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 417.750284] [drm:ironlake_update_plane], Writing base 09C8F000 00000000 0 0 4096 [ 417.801955] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 417.801962] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6 [ 417.801974] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6 [ 417.801976] [drm:ironlake_check_srwm], watermark 2: display plane 8, fbc lines 3, cursor 6 [ 417.801979] [drm:ironlake_check_srwm], watermark 3: display plane 35, fbc lines 3, cursor 6 [ 417.801982] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:96:1024x576] [ 417.801986] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 417.801988] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 417.801990] [drm:ironlake_write_eld], ELD on pipe A [ 417.801993] [drm:ironlake_write_eld], Audio directed to unknown port [ 417.801995] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 417.802012] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6 [ 417.802014] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6 [ 417.802016] [drm:ironlake_check_srwm], watermark 2: display plane 8, fbc lines 3, cursor 6 [ 417.802019] [drm:ironlake_check_srwm], watermark 3: display plane 35, fbc lines 3, cursor 6 [ 417.853910] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 417.905821] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 417.906648] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 417.906651] [drm:gen6_fdi_link_train], FDI train 1 done. [ 417.907308] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 417.907311] [drm:gen6_fdi_link_train], FDI train 2 done. [ 417.907312] [drm:gen6_fdi_link_train], FDI train done. [ 417.907314] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 417.907318] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 417.908968] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 417.909806] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 417.910641] [drm:intel_dp_start_link_train], clock recovery OK [ 417.933070] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 417.934804] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 417.934812] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 417.934815] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 417.934819] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 417.934822] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 417.934825] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 417.934829] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 417.934833] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 417.934836] [drm:intel_modeset_check_state], [CRTC:3] [ 417.934838] [drm:intel_modeset_check_state], [CRTC:5] [ 427.969519] [drm:drm_mode_addfb], [FB:96] [ 427.969566] [drm:drm_mode_setcrtc], [CRTC:3] [ 427.969572] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 427.969575] [drm:intel_crtc_set_config], [CRTC:3] [FB:96] #connectors=1 (x y) (0 0) [ 427.969578] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 427.969580] [drm:drm_mode_debug_printmodeline], Modeline 96:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6 [ 427.969583] [drm:drm_mode_debug_printmodeline], Modeline 97:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 427.969587] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 427.969589] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 427.969591] [drm:drm_mode_debug_printmodeline], Modeline 97:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 427.969594] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 427.969597] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 50000KHz [ 427.969600] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 427.969602] [drm:intel_dp_mode_fixup], DP link bw required 120000 available 129600 [ 427.969604] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 427.969818] [drm:intel_dp_link_down], [ 427.992209] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 428.026730] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 428.026743] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 428.027156] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6 [ 428.027158] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6 [ 428.027161] [drm:ironlake_check_srwm], watermark 2: display plane 8, fbc lines 3, cursor 6 [ 428.027163] [drm:ironlake_check_srwm], watermark 3: display plane 35, fbc lines 3, cursor 6 [ 428.027170] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 428.027172] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 428.027174] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 428.027176] [drm:drm_mode_debug_printmodeline], Modeline 97:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 428.027179] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 428.027181] [drm:intel_get_pch_pll], switching PLL c6014 off [ 428.078678] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 428.079665] [drm:ironlake_update_plane], Writing base 09ECF000 00000000 0 0 3200 [ 428.131588] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 428.131596] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6 [ 428.131608] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6 [ 428.131611] [drm:ironlake_check_srwm], watermark 2: display plane 9, fbc lines 3, cursor 6 [ 428.131613] [drm:ironlake_check_srwm], watermark 3: display plane 37, fbc lines 3, cursor 6 [ 428.131616] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:97:800x600] [ 428.131620] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 428.131622] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 428.131624] [drm:ironlake_write_eld], ELD on pipe A [ 428.131627] [drm:ironlake_write_eld], Audio directed to unknown port [ 428.131629] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 428.131645] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6 [ 428.131648] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6 [ 428.131650] [drm:ironlake_check_srwm], watermark 2: display plane 9, fbc lines 3, cursor 6 [ 428.131653] [drm:ironlake_check_srwm], watermark 3: display plane 37, fbc lines 3, cursor 6 [ 428.183545] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 428.235457] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 428.236284] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 428.236288] [drm:gen6_fdi_link_train], FDI train 1 done. [ 428.236944] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 428.236947] [drm:gen6_fdi_link_train], FDI train 2 done. [ 428.236949] [drm:gen6_fdi_link_train], FDI train done. [ 428.236950] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 428.236954] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 428.238605] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 428.239440] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 428.240274] [drm:intel_dp_start_link_train], clock recovery OK [ 428.259889] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 428.260476] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 428.260484] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 428.260488] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 428.260491] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 428.260494] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 428.260498] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 428.260501] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 428.260505] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 428.260508] [drm:intel_modeset_check_state], [CRTC:3] [ 428.260510] [drm:intel_modeset_check_state], [CRTC:5] [ 438.295063] [drm:drm_mode_addfb], [FB:97] [ 438.295110] [drm:drm_mode_setcrtc], [CRTC:3] [ 438.295116] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 438.295118] [drm:intel_crtc_set_config], [CRTC:3] [FB:97] #connectors=1 (x y) (0 0) [ 438.295122] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 438.295124] [drm:drm_mode_debug_printmodeline], Modeline 97:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 438.295127] [drm:drm_mode_debug_printmodeline], Modeline 98:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 438.295131] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 438.295133] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 438.295135] [drm:drm_mode_debug_printmodeline], Modeline 98:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 438.295138] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 438.295141] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 49500KHz [ 438.295144] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 438.295146] [drm:intel_dp_mode_fixup], DP link bw required 118800 available 129600 [ 438.295148] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 438.295362] [drm:intel_dp_link_down], [ 438.317781] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 438.347394] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 438.347408] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 438.347821] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6 [ 438.347824] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6 [ 438.347826] [drm:ironlake_check_srwm], watermark 2: display plane 9, fbc lines 3, cursor 6 [ 438.347829] [drm:ironlake_check_srwm], watermark 3: display plane 37, fbc lines 3, cursor 6 [ 438.347835] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 438.347837] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 438.347839] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 438.347841] [drm:drm_mode_debug_printmodeline], Modeline 98:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 438.347844] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 438.347846] [drm:intel_get_pch_pll], switching PLL c6014 off [ 438.399304] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 438.400193] [drm:ironlake_update_plane], Writing base 0A0A4000 00000000 0 0 3200 [ 438.451233] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 438.451241] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6 [ 438.451252] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6 [ 438.451254] [drm:ironlake_check_srwm], watermark 2: display plane 9, fbc lines 3, cursor 6 [ 438.451257] [drm:ironlake_check_srwm], watermark 3: display plane 37, fbc lines 3, cursor 6 [ 438.451260] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:98:800x600] [ 438.451264] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 438.451266] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 438.451269] [drm:ironlake_write_eld], ELD on pipe A [ 438.451272] [drm:ironlake_write_eld], Audio directed to unknown port [ 438.451274] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 438.451290] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6 [ 438.451293] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6 [ 438.451295] [drm:ironlake_check_srwm], watermark 2: display plane 9, fbc lines 3, cursor 6 [ 438.451297] [drm:ironlake_check_srwm], watermark 3: display plane 37, fbc lines 3, cursor 6 [ 438.503170] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 438.555123] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 438.555950] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 438.555954] [drm:gen6_fdi_link_train], FDI train 1 done. [ 438.556610] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 438.556613] [drm:gen6_fdi_link_train], FDI train 2 done. [ 438.556615] [drm:gen6_fdi_link_train], FDI train done. [ 438.556616] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 438.556620] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 438.558275] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 438.559113] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 438.559948] [drm:intel_dp_start_link_train], clock recovery OK [ 438.579065] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 438.580133] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 438.580141] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 438.580145] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 438.580148] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 438.580151] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 438.580155] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 438.580158] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 438.580163] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 438.580165] [drm:intel_modeset_check_state], [CRTC:3] [ 438.580167] [drm:intel_modeset_check_state], [CRTC:5] [ 448.614760] [drm:drm_mode_addfb], [FB:98] [ 448.614808] [drm:drm_mode_setcrtc], [CRTC:3] [ 448.614814] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 448.614816] [drm:intel_crtc_set_config], [CRTC:3] [FB:98] #connectors=1 (x y) (0 0) [ 448.614819] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 448.614821] [drm:drm_mode_debug_printmodeline], Modeline 98:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 448.614825] [drm:drm_mode_debug_printmodeline], Modeline 99:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 448.614828] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 448.614831] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 448.614833] [drm:drm_mode_debug_printmodeline], Modeline 99:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 448.614836] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 448.614839] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 40000KHz [ 448.614842] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 448.614844] [drm:intel_dp_mode_fixup], DP link bw required 96000 available 129600 [ 448.614846] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 448.615066] [drm:intel_dp_link_down], [ 448.645979] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 448.674010] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 448.674024] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 448.674437] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 33, cursor: 6 [ 448.674439] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6 [ 448.674442] [drm:ironlake_check_srwm], watermark 2: display plane 9, fbc lines 3, cursor 6 [ 448.674444] [drm:ironlake_check_srwm], watermark 3: display plane 37, fbc lines 3, cursor 6 [ 448.674451] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 448.674453] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 448.674455] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 448.674457] [drm:drm_mode_debug_printmodeline], Modeline 99:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 448.674460] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 448.674462] [drm:intel_get_pch_pll], switching PLL c6014 off [ 448.725961] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 448.726834] [drm:ironlake_update_plane], Writing base 0A279000 00000000 0 0 3200 [ 448.777873] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 448.777887] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6 [ 448.777890] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6 [ 448.777893] [drm:ironlake_check_srwm], watermark 2: display plane 7, fbc lines 3, cursor 6 [ 448.777895] [drm:ironlake_check_srwm], watermark 3: display plane 30, fbc lines 3, cursor 6 [ 448.777899] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:99:800x600] [ 448.777902] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 448.777905] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 448.777907] [drm:ironlake_write_eld], ELD on pipe A [ 448.777910] [drm:ironlake_write_eld], Audio directed to unknown port [ 448.777912] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 448.777928] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6 [ 448.777930] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6 [ 448.777933] [drm:ironlake_check_srwm], watermark 2: display plane 7, fbc lines 3, cursor 6 [ 448.777935] [drm:ironlake_check_srwm], watermark 3: display plane 30, fbc lines 3, cursor 6 [ 448.829826] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 448.881741] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 448.882568] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 448.882572] [drm:gen6_fdi_link_train], FDI train 1 done. [ 448.883228] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 448.883232] [drm:gen6_fdi_link_train], FDI train 2 done. [ 448.883233] [drm:gen6_fdi_link_train], FDI train done. [ 448.883235] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 448.883239] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 448.884889] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 448.885726] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 448.886570] [drm:intel_dp_start_link_train], clock recovery OK [ 448.908908] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 448.910698] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 448.910715] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 448.910719] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 448.910722] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 448.910725] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 448.910729] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 448.910732] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 448.910736] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 448.910739] [drm:intel_modeset_check_state], [CRTC:3] [ 448.910741] [drm:intel_modeset_check_state], [CRTC:5] [ 458.945533] [drm:drm_mode_addfb], [FB:99] [ 458.945579] [drm:drm_mode_setcrtc], [CRTC:3] [ 458.945585] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 458.945587] [drm:intel_crtc_set_config], [CRTC:3] [FB:99] #connectors=1 (x y) (0 0) [ 458.945591] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 458.945593] [drm:drm_mode_debug_printmodeline], Modeline 99:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 458.945596] [drm:drm_mode_debug_printmodeline], Modeline 100:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 458.945600] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 458.945602] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 458.945604] [drm:drm_mode_debug_printmodeline], Modeline 100:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 458.945607] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 458.945610] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 36000KHz [ 458.945613] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 458.945615] [drm:intel_dp_mode_fixup], DP link bw required 86400 available 129600 [ 458.945617] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 458.945830] [drm:intel_dp_link_down], [ 458.975986] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 459.010655] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 459.010668] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 459.011081] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6 [ 459.011083] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6 [ 459.011086] [drm:ironlake_check_srwm], watermark 2: display plane 7, fbc lines 3, cursor 6 [ 459.011088] [drm:ironlake_check_srwm], watermark 3: display plane 30, fbc lines 3, cursor 6 [ 459.011095] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 459.011097] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 459.011099] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 459.011101] [drm:drm_mode_debug_printmodeline], Modeline 100:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 459.011104] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 459.011106] [drm:intel_get_pch_pll], switching PLL c6014 off [ 459.062583] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 459.063436] [drm:ironlake_update_plane], Writing base 0A44E000 00000000 0 0 3200 [ 459.114513] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 459.114521] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6 [ 459.114532] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6 [ 459.114535] [drm:ironlake_check_srwm], watermark 2: display plane 7, fbc lines 3, cursor 6 [ 459.114537] [drm:ironlake_check_srwm], watermark 3: display plane 27, fbc lines 3, cursor 6 [ 459.114540] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:100:800x600] [ 459.114544] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 459.114546] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 459.114549] [drm:ironlake_write_eld], ELD on pipe A [ 459.114552] [drm:ironlake_write_eld], Audio directed to unknown port [ 459.114553] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 459.114570] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6 [ 459.114572] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6 [ 459.114575] [drm:ironlake_check_srwm], watermark 2: display plane 7, fbc lines 3, cursor 6 [ 459.114577] [drm:ironlake_check_srwm], watermark 3: display plane 27, fbc lines 3, cursor 6 [ 459.166447] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 459.218357] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 459.219176] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 459.219179] [drm:gen6_fdi_link_train], FDI train 1 done. [ 459.219837] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 459.219840] [drm:gen6_fdi_link_train], FDI train 2 done. [ 459.219842] [drm:gen6_fdi_link_train], FDI train done. [ 459.219843] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 459.219847] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 459.221498] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 459.222336] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 459.223173] [drm:intel_dp_start_link_train], clock recovery OK [ 459.246721] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 459.247338] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 459.247353] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 459.247357] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 459.247360] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 459.247365] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 459.247369] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 459.247372] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 459.247378] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 459.247382] [drm:intel_modeset_check_state], [CRTC:3] [ 459.247384] [drm:intel_modeset_check_state], [CRTC:5] [ 469.274857] [drm:drm_mode_addfb], [FB:100] [ 469.274903] [drm:drm_mode_setcrtc], [CRTC:3] [ 469.274908] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 469.274911] [drm:intel_crtc_set_config], [CRTC:3] [FB:100] #connectors=1 (x y) (0 0) [ 469.274914] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 469.274916] [drm:drm_mode_debug_printmodeline], Modeline 100:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 469.274919] [drm:drm_mode_debug_printmodeline], Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 469.274922] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 469.274925] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 469.274926] [drm:drm_mode_debug_printmodeline], Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 469.274929] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 469.274933] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 27000KHz [ 469.274935] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 469.274937] [drm:intel_dp_mode_fixup], DP link bw required 64800 available 129600 [ 469.274939] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 469.275153] [drm:intel_dp_link_down], [ 469.295854] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 469.333294] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 469.333308] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 469.333720] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6 [ 469.333723] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6 [ 469.333725] [drm:ironlake_check_srwm], watermark 2: display plane 7, fbc lines 3, cursor 6 [ 469.333727] [drm:ironlake_check_srwm], watermark 3: display plane 27, fbc lines 3, cursor 6 [ 469.333734] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 469.333736] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 469.333739] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 469.333740] [drm:drm_mode_debug_printmodeline], Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 469.333744] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 469.333745] [drm:intel_get_pch_pll], switching PLL c6014 off [ 469.385222] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 469.386065] [drm:ironlake_update_plane], Writing base 0A623000 00000000 0 0 2880 [ 469.437154] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 469.437161] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 469.437173] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 469.437176] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 469.437178] [drm:ironlake_check_srwm], watermark 3: display plane 21, fbc lines 3, cursor 6 [ 469.437181] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:101:720x576] [ 469.437185] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 469.437188] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 469.437190] [drm:ironlake_write_eld], ELD on pipe A [ 469.437193] [drm:ironlake_write_eld], Audio directed to unknown port [ 469.437195] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 469.437212] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 469.437214] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 469.437216] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 469.437219] [drm:ironlake_check_srwm], watermark 3: display plane 21, fbc lines 3, cursor 6 [ 469.489087] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 469.541020] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 469.541846] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 469.541850] [drm:gen6_fdi_link_train], FDI train 1 done. [ 469.542506] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 469.542510] [drm:gen6_fdi_link_train], FDI train 2 done. [ 469.542511] [drm:gen6_fdi_link_train], FDI train done. [ 469.542513] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 469.542517] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 469.544168] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 469.545002] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 469.545837] [drm:intel_dp_start_link_train], clock recovery OK [ 469.571604] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 469.571993] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 469.572009] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 469.572012] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 469.572016] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 469.572021] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 469.572025] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 469.572028] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 469.572033] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 469.572036] [drm:intel_modeset_check_state], [CRTC:3] [ 469.572039] [drm:intel_modeset_check_state], [CRTC:5] [ 479.593366] [drm:drm_mode_addfb], [FB:101] [ 479.593412] [drm:drm_mode_setcrtc], [CRTC:3] [ 479.593418] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 479.593420] [drm:intel_crtc_set_config], [CRTC:3] [FB:101] #connectors=1 (x y) (0 0) [ 479.593423] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 479.593425] [drm:drm_mode_debug_printmodeline], Modeline 101:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 479.593428] [drm:drm_mode_debug_printmodeline], Modeline 102:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 479.593432] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 479.593434] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 479.593436] [drm:drm_mode_debug_printmodeline], Modeline 102:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 479.593439] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 479.593442] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 33750KHz [ 479.593445] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 479.593447] [drm:intel_dp_mode_fixup], DP link bw required 81000 available 129600 [ 479.593449] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 479.593662] [drm:intel_dp_link_down], [ 479.618521] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 479.659929] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 479.659943] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 479.660356] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 479.660358] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 479.660361] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 479.660363] [drm:ironlake_check_srwm], watermark 3: display plane 21, fbc lines 3, cursor 6 [ 479.660370] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 479.660372] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 479.660374] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 479.660376] [drm:drm_mode_debug_printmodeline], Modeline 102:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 479.660379] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 479.660381] [drm:intel_get_pch_pll], switching PLL c6014 off [ 479.711858] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 479.712705] [drm:ironlake_update_plane], Writing base 0A7B8000 00000000 0 0 3392 [ 479.763791] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 479.763799] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6 [ 479.763811] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6 [ 479.763814] [drm:ironlake_check_srwm], watermark 2: display plane 7, fbc lines 3, cursor 6 [ 479.763816] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6 [ 479.763819] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:102:848x480] [ 479.763823] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 479.763826] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 479.763828] [drm:ironlake_write_eld], ELD on pipe A [ 479.763831] [drm:ironlake_write_eld], Audio directed to unknown port [ 479.763833] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 479.763849] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6 [ 479.763851] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6 [ 479.763854] [drm:ironlake_check_srwm], watermark 2: display plane 7, fbc lines 3, cursor 6 [ 479.763856] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6 [ 479.815727] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 479.867660] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 479.868487] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 479.868490] [drm:gen6_fdi_link_train], FDI train 1 done. [ 479.869146] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 479.869150] [drm:gen6_fdi_link_train], FDI train 2 done. [ 479.869151] [drm:gen6_fdi_link_train], FDI train done. [ 479.869153] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 479.869157] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 479.870812] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 479.871647] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 479.872482] [drm:intel_dp_start_link_train], clock recovery OK [ 479.894903] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 479.896619] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 479.896626] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 479.896630] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 479.896633] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 479.896637] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 479.896640] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 479.896643] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 479.896647] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 479.896651] [drm:intel_modeset_check_state], [CRTC:3] [ 479.896652] [drm:intel_modeset_check_state], [CRTC:5] [ 479.896689] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 479.897644] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40000, result 0 [ 479.897647] [drm:intel_crt_detect], CRT not detected via hotplug [ 479.898050] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb [ 479.898052] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] [ 479.898055] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 479.898457] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb [ 479.898459] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 479.901022] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 479.905130] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 479.909123] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 479.910563] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 479.910569] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 2 to 2 [ 479.912570] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 479.912577] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 479.912582] [drm:output_poll_execute], [CONNECTOR:16:HDMI-A-2] status updated from 2 to 2 [ 479.914567] [drm:gmbus_xfer], GMBUS [i915 gmbus dpd] NAK for addr: 0050 r(1) [ 479.914574] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpd [ 479.914578] [drm:output_poll_execute], [CONNECTOR:18:HDMI-A-3] status updated from 2 to 2 [ 479.914903] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 479.915951] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 479.943496] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 479.971044] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 479.971047] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 479.971049] [drm:output_poll_execute], [CONNECTOR:19:DP-2] status updated from 1 to 1 [ 479.973606] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 479.978030] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 479.982028] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 479.983467] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 479.983472] [drm:output_poll_execute], [CONNECTOR:21:DP-3] status updated from 2 to 2 [ 489.915959] [drm:drm_mode_addfb], [FB:102] [ 489.916006] [drm:drm_mode_setcrtc], [CRTC:3] [ 489.916011] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 489.916014] [drm:intel_crtc_set_config], [CRTC:3] [FB:102] #connectors=1 (x y) (0 0) [ 489.916017] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 489.916019] [drm:drm_mode_debug_printmodeline], Modeline 102:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 489.916023] [drm:drm_mode_debug_printmodeline], Modeline 103:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 489.916026] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 489.916028] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 489.916030] [drm:drm_mode_debug_printmodeline], Modeline 103:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 489.916033] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 489.916037] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 27000KHz [ 489.916039] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 489.916041] [drm:intel_dp_mode_fixup], DP link bw required 64800 available 129600 [ 489.916043] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 489.916257] [drm:intel_dp_link_down], [ 489.948417] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 489.982572] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 489.982585] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 489.982998] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6 [ 489.983000] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6 [ 489.983003] [drm:ironlake_check_srwm], watermark 2: display plane 7, fbc lines 3, cursor 6 [ 489.983005] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6 [ 489.983012] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 489.983014] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 489.983016] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 489.983018] [drm:drm_mode_debug_printmodeline], Modeline 103:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 489.983021] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 489.983023] [drm:intel_get_pch_pll], switching PLL c6014 off [ 490.034499] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 490.035210] [drm:ironlake_update_plane], Writing base 0A946000 00000000 0 0 2880 [ 490.086431] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 490.086438] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 490.086450] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 490.086452] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 490.086455] [drm:ironlake_check_srwm], watermark 3: display plane 21, fbc lines 3, cursor 6 [ 490.086458] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:103:720x480] [ 490.086462] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 490.086464] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 490.086466] [drm:ironlake_write_eld], ELD on pipe A [ 490.086469] [drm:ironlake_write_eld], Audio directed to unknown port [ 490.086471] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 490.086488] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 490.086490] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 490.086492] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 490.086495] [drm:ironlake_check_srwm], watermark 3: display plane 21, fbc lines 3, cursor 6 [ 490.138364] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 490.190300] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 490.191127] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 490.191131] [drm:gen6_fdi_link_train], FDI train 1 done. [ 490.191787] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 490.191790] [drm:gen6_fdi_link_train], FDI train 2 done. [ 490.191792] [drm:gen6_fdi_link_train], FDI train done. [ 490.191794] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 490.191797] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 490.193452] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 490.194286] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 490.195121] [drm:intel_dp_start_link_train], clock recovery OK [ 490.217554] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 490.219257] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 490.219264] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 490.219268] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 490.219272] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 490.219275] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 490.219278] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 490.219281] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 490.219286] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 490.219289] [drm:intel_modeset_check_state], [CRTC:3] [ 490.219291] [drm:intel_modeset_check_state], [CRTC:5] [ 490.219327] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 490.220282] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40000, result 0 [ 490.220285] [drm:intel_crt_detect], CRT not detected via hotplug [ 490.220688] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb [ 490.220690] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] [ 490.220692] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 490.221094] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb [ 490.221096] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 490.223652] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 490.227771] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 490.231764] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 490.233204] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 490.233209] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 2 to 2 [ 490.235210] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 490.235217] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 490.235222] [drm:output_poll_execute], [CONNECTOR:16:HDMI-A-2] status updated from 2 to 2 [ 490.237208] [drm:gmbus_xfer], GMBUS [i915 gmbus dpd] NAK for addr: 0050 r(1) [ 490.237215] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpd [ 490.237220] [drm:output_poll_execute], [CONNECTOR:18:HDMI-A-3] status updated from 2 to 2 [ 490.237545] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 490.238593] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 490.266139] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 490.293789] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 490.293791] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 490.293794] [drm:output_poll_execute], [CONNECTOR:19:DP-2] status updated from 1 to 1 [ 490.296350] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 490.300675] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 490.304669] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 490.306110] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 490.306115] [drm:output_poll_execute], [CONNECTOR:21:DP-3] status updated from 2 to 2 [ 500.236728] [drm:drm_mode_addfb], [FB:103] [ 500.236773] [drm:drm_mode_setcrtc], [CRTC:3] [ 500.236778] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 500.236781] [drm:intel_crtc_set_config], [CRTC:3] [FB:103] #connectors=1 (x y) (0 0) [ 500.236784] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 500.236786] [drm:drm_mode_debug_printmodeline], Modeline 103:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 500.236789] [drm:drm_mode_debug_printmodeline], Modeline 104:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 500.236793] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 500.236795] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 500.236797] [drm:drm_mode_debug_printmodeline], Modeline 104:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 500.236800] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 500.236803] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 31500KHz [ 500.236806] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 500.236808] [drm:intel_dp_mode_fixup], DP link bw required 75600 available 129600 [ 500.236810] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 500.237023] [drm:intel_dp_link_down], [ 500.264554] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 500.299225] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 500.299237] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 500.299650] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 500.299652] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 500.299655] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 500.299657] [drm:ironlake_check_srwm], watermark 3: display plane 21, fbc lines 3, cursor 6 [ 500.299664] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 500.299666] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 500.299668] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 500.299670] [drm:drm_mode_debug_printmodeline], Modeline 104:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 500.299673] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 500.299675] [drm:intel_get_pch_pll], switching PLL c6014 off [ 500.351131] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 500.351757] [drm:ironlake_update_plane], Writing base 0AA98000 00000000 0 0 2560 [ 500.403083] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 500.403090] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 500.403101] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 500.403104] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 500.403106] [drm:ironlake_check_srwm], watermark 3: display plane 24, fbc lines 3, cursor 6 [ 500.403109] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:104:640x480] [ 500.403113] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 500.403116] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 500.403118] [drm:ironlake_write_eld], ELD on pipe A [ 500.403121] [drm:ironlake_write_eld], Audio directed to unknown port [ 500.403123] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 500.403139] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 500.403142] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 500.403144] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 500.403146] [drm:ironlake_check_srwm], watermark 3: display plane 24, fbc lines 3, cursor 6 [ 500.454995] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 500.506949] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 500.507776] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 500.507780] [drm:gen6_fdi_link_train], FDI train 1 done. [ 500.508436] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 500.508439] [drm:gen6_fdi_link_train], FDI train 2 done. [ 500.508441] [drm:gen6_fdi_link_train], FDI train done. [ 500.508442] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 500.508446] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 500.510100] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 500.510938] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 500.511772] [drm:intel_dp_start_link_train], clock recovery OK [ 500.531279] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 500.531917] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 500.531925] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 500.531928] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 500.531932] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 500.531937] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 500.531940] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 500.531944] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 500.531948] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 500.531953] [drm:intel_modeset_check_state], [CRTC:3] [ 500.531955] [drm:intel_modeset_check_state], [CRTC:5] [ 510.549215] [drm:drm_mode_addfb], [FB:104] [ 510.549260] [drm:drm_mode_setcrtc], [CRTC:3] [ 510.549266] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 510.549268] [drm:intel_crtc_set_config], [CRTC:3] [FB:104] #connectors=1 (x y) (0 0) [ 510.549272] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 510.549273] [drm:drm_mode_debug_printmodeline], Modeline 104:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 510.549277] [drm:drm_mode_debug_printmodeline], Modeline 105:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 510.549280] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 510.549282] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 510.549284] [drm:drm_mode_debug_printmodeline], Modeline 105:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 510.549287] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 510.549290] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 31500KHz [ 510.549293] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 510.549295] [drm:intel_dp_mode_fixup], DP link bw required 75600 available 129600 [ 510.549297] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 510.549510] [drm:intel_dp_link_down], [ 510.571909] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 510.599889] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 510.599903] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 510.600315] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 510.600318] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 510.600321] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 510.600323] [drm:ironlake_check_srwm], watermark 3: display plane 24, fbc lines 3, cursor 6 [ 510.600329] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 510.600332] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 510.600334] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 510.600336] [drm:drm_mode_debug_printmodeline], Modeline 105:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 510.600339] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 510.600341] [drm:intel_get_pch_pll], switching PLL c6014 off [ 510.651817] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 510.652445] [drm:ironlake_update_plane], Writing base 0ABC4000 00000000 0 0 2560 [ 510.703749] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 510.703757] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 510.703768] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 510.703771] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 510.703773] [drm:ironlake_check_srwm], watermark 3: display plane 24, fbc lines 3, cursor 6 [ 510.703777] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:105:640x480] [ 510.703780] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 510.703783] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 510.703785] [drm:ironlake_write_eld], ELD on pipe A [ 510.703788] [drm:ironlake_write_eld], Audio directed to unknown port [ 510.703790] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 510.703806] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 510.703809] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 510.703811] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 510.703813] [drm:ironlake_check_srwm], watermark 3: display plane 24, fbc lines 3, cursor 6 [ 510.755683] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 510.807618] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 510.808445] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 510.808448] [drm:gen6_fdi_link_train], FDI train 1 done. [ 510.809105] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 510.809108] [drm:gen6_fdi_link_train], FDI train 2 done. [ 510.809109] [drm:gen6_fdi_link_train], FDI train done. [ 510.809111] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 510.809115] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 510.810769] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 510.811605] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 510.812440] [drm:intel_dp_start_link_train], clock recovery OK [ 510.831546] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 510.832596] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 510.832603] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 510.832607] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 510.832612] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 510.832617] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 510.832620] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 510.832623] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 510.832629] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 510.832633] [drm:intel_modeset_check_state], [CRTC:3] [ 510.832635] [drm:intel_modeset_check_state], [CRTC:5] [ 510.832672] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 510.833628] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40000, result 0 [ 510.833631] [drm:intel_crt_detect], CRT not detected via hotplug [ 510.834033] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb [ 510.834035] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] [ 510.834037] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 510.834439] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb [ 510.834441] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 510.836998] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 510.841095] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 510.845088] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 510.846528] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 510.846533] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 2 to 2 [ 510.848532] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 510.848539] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 510.848543] [drm:output_poll_execute], [CONNECTOR:16:HDMI-A-2] status updated from 2 to 2 [ 510.850529] [drm:gmbus_xfer], GMBUS [i915 gmbus dpd] NAK for addr: 0050 r(1) [ 510.850536] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpd [ 510.850540] [drm:output_poll_execute], [CONNECTOR:18:HDMI-A-3] status updated from 2 to 2 [ 510.850867] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 510.851914] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 510.879462] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 510.907008] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 510.907011] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 510.907013] [drm:output_poll_execute], [CONNECTOR:19:DP-2] status updated from 1 to 1 [ 510.909569] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 510.913998] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 510.917993] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 510.919434] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 510.919439] [drm:output_poll_execute], [CONNECTOR:21:DP-3] status updated from 2 to 2 [ 520.850005] [drm:drm_mode_addfb], [FB:105] [ 520.850050] [drm:drm_mode_setcrtc], [CRTC:3] [ 520.850056] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 520.850058] [drm:intel_crtc_set_config], [CRTC:3] [FB:105] #connectors=1 (x y) (0 0) [ 520.850062] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 520.850064] [drm:drm_mode_debug_printmodeline], Modeline 105:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 520.850067] [drm:drm_mode_debug_printmodeline], Modeline 106:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 520.850070] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 520.850073] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 520.850075] [drm:drm_mode_debug_printmodeline], Modeline 106:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 520.850078] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 520.850081] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 25200KHz [ 520.850083] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 520.850086] [drm:intel_dp_mode_fixup], DP link bw required 60480 available 129600 [ 520.850088] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 520.850301] [drm:intel_dp_link_down], [ 520.871805] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 520.898566] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 520.898578] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 520.898991] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 520.898993] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 520.898996] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 520.898998] [drm:ironlake_check_srwm], watermark 3: display plane 24, fbc lines 3, cursor 6 [ 520.899005] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 520.899007] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 520.899009] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 520.899011] [drm:drm_mode_debug_printmodeline], Modeline 106:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 520.899014] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 520.899016] [drm:intel_get_pch_pll], switching PLL c6014 off [ 520.950493] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 520.951119] [drm:ironlake_update_plane], Writing base 0ACF0000 00000000 0 0 2560 [ 521.002426] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 521.002440] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 521.002443] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 521.002445] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 521.002448] [drm:ironlake_check_srwm], watermark 3: display plane 20, fbc lines 3, cursor 6 [ 521.002451] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:106:640x480] [ 521.002455] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 521.002457] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 521.002460] [drm:ironlake_write_eld], ELD on pipe A [ 521.002463] [drm:ironlake_write_eld], Audio directed to unknown port [ 521.002464] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 521.002481] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 521.002483] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 521.002485] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 521.002488] [drm:ironlake_check_srwm], watermark 3: display plane 20, fbc lines 3, cursor 6 [ 521.054358] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 521.106289] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 521.107116] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 521.107119] [drm:gen6_fdi_link_train], FDI train 1 done. [ 521.107776] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 521.107779] [drm:gen6_fdi_link_train], FDI train 2 done. [ 521.107781] [drm:gen6_fdi_link_train], FDI train done. [ 521.107782] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 521.107786] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 521.109441] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 521.110276] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 521.111110] [drm:intel_dp_start_link_train], clock recovery OK [ 521.133513] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 521.135249] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 521.135256] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 521.135260] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 521.135264] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 521.135267] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 521.135270] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 521.135273] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 521.135278] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 521.135281] [drm:intel_modeset_check_state], [CRTC:3] [ 521.135283] [drm:intel_modeset_check_state], [CRTC:5] [ 531.152672] [drm:drm_mode_addfb], [FB:106] [ 531.152719] [drm:drm_mode_setcrtc], [CRTC:3] [ 531.152725] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 531.152727] [drm:intel_crtc_set_config], [CRTC:3] [FB:106] #connectors=1 (x y) (0 0) [ 531.152731] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 531.152733] [drm:drm_mode_debug_printmodeline], Modeline 106:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 531.152736] [drm:drm_mode_debug_printmodeline], Modeline 107:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 531.152740] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 531.152742] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 531.152744] [drm:drm_mode_debug_printmodeline], Modeline 107:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 531.152747] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 531.152750] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 25175KHz [ 531.152753] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 531.152755] [drm:intel_dp_mode_fixup], DP link bw required 60420 available 129600 [ 531.152757] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 531.152970] [drm:intel_dp_link_down], [ 531.187134] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 531.221202] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 531.221216] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 531.221629] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 531.221632] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 531.221634] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 531.221637] [drm:ironlake_check_srwm], watermark 3: display plane 20, fbc lines 3, cursor 6 [ 531.221643] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 531.221646] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 531.221648] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 531.221649] [drm:drm_mode_debug_printmodeline], Modeline 107:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 531.221653] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 531.221655] [drm:intel_get_pch_pll], switching PLL c6014 off [ 531.273130] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 531.273758] [drm:ironlake_update_plane], Writing base 0AE1C000 00000000 0 0 2560 [ 531.325063] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 531.325070] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 531.325081] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 531.325084] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 531.325086] [drm:ironlake_check_srwm], watermark 3: display plane 20, fbc lines 3, cursor 6 [ 531.325090] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:107:640x480] [ 531.325093] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 531.325096] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 531.325098] [drm:ironlake_write_eld], ELD on pipe A [ 531.325101] [drm:ironlake_write_eld], Audio directed to unknown port [ 531.325103] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 531.325120] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 531.325122] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 531.325125] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 531.325127] [drm:ironlake_check_srwm], watermark 3: display plane 20, fbc lines 3, cursor 6 [ 531.376995] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 531.428928] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 531.429747] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 531.429750] [drm:gen6_fdi_link_train], FDI train 1 done. [ 531.430407] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 531.430411] [drm:gen6_fdi_link_train], FDI train 2 done. [ 531.430412] [drm:gen6_fdi_link_train], FDI train done. [ 531.430414] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 531.430418] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 531.432069] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 531.432904] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 531.433742] [drm:intel_dp_start_link_train], clock recovery OK [ 531.456165] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 531.457890] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 531.457897] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 531.457901] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 531.457904] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 531.457908] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 531.457911] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 531.457914] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 531.457918] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 531.457922] [drm:intel_modeset_check_state], [CRTC:3] [ 531.457923] [drm:intel_modeset_check_state], [CRTC:5] [ 541.472319] [drm:drm_mode_addfb], [FB:107] [ 541.472365] [drm:drm_mode_setcrtc], [CRTC:3] [ 541.472370] [drm:drm_mode_setcrtc], [CONNECTOR:19:DP-2] [ 541.472373] [drm:intel_crtc_set_config], [CRTC:3] [FB:107] #connectors=1 (x y) (0 0) [ 541.472376] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 541.472378] [drm:drm_mode_debug_printmodeline], Modeline 107:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 541.472381] [drm:drm_mode_debug_printmodeline], Modeline 108:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 541.472385] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 541.472387] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 541.472389] [drm:drm_mode_debug_printmodeline], Modeline 108:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 541.472392] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 541.472395] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 28320KHz [ 541.472398] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 1 clock 162000 bpp 24 [ 541.472400] [drm:intel_dp_mode_fixup], DP link bw required 67968 available 129600 [ 541.472402] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 541.472615] [drm:intel_dp_link_down], [ 541.503085] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 541.536830] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 541.536844] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 541.537257] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6 [ 541.537259] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 541.537262] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 541.537264] [drm:ironlake_check_srwm], watermark 3: display plane 20, fbc lines 3, cursor 6 [ 541.537271] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 541.537273] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 541.537275] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 541.537277] [drm:drm_mode_debug_printmodeline], Modeline 108:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 541.537280] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014 [ 541.537282] [drm:intel_get_pch_pll], switching PLL c6014 off [ 541.588780] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 541.589374] [drm:ironlake_update_plane], Writing base 0AF48000 00000000 0 0 2880 [ 541.640691] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 541.640698] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 541.640710] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 541.640713] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 541.640715] [drm:ironlake_check_srwm], watermark 3: display plane 22, fbc lines 3, cursor 6 [ 541.640718] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:108:720x400] [ 541.640722] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 541.640724] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 541.640727] [drm:ironlake_write_eld], ELD on pipe A [ 541.640729] [drm:ironlake_write_eld], Audio directed to unknown port [ 541.640731] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 541.640748] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 541.640750] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 541.640752] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 541.640755] [drm:ironlake_check_srwm], watermark 3: display plane 22, fbc lines 3, cursor 6 [ 541.692646] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 541.744555] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 541.745374] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 541.745377] [drm:gen6_fdi_link_train], FDI train 1 done. [ 541.746036] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 541.746040] [drm:gen6_fdi_link_train], FDI train 2 done. [ 541.746041] [drm:gen6_fdi_link_train], FDI train done. [ 541.746043] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 541.746047] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 541.747697] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 541.748534] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 541.749368] [drm:intel_dp_start_link_train], clock recovery OK [ 541.769373] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 541.769543] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 541.769550] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 541.769554] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 541.769558] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 541.769561] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 541.769565] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 541.769568] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 541.769573] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 541.769578] [drm:intel_modeset_check_state], [CRTC:3] [ 541.769580] [drm:intel_modeset_check_state], [CRTC:5] [ 551.756925] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] [ 551.756939] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [NOCRTC] [ 551.756941] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 551.756943] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 551.756945] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 551.757159] [drm:intel_dp_link_down], [ 551.787485] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 551.817547] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 551.817561] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 551.817973] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6 [ 551.817976] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6 [ 551.817979] [drm:ironlake_check_srwm], watermark 2: display plane 6, fbc lines 3, cursor 6 [ 551.817981] [drm:ironlake_check_srwm], watermark 3: display plane 22, fbc lines 3, cursor 6 [ 551.817994] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 551.817998] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 551.818001] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 551.818005] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 551.818008] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 551.818011] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 551.818014] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 551.818017] [drm:intel_modeset_check_state], [CRTC:3] [ 551.818019] [drm:intel_modeset_check_state], [CRTC:5] [ 551.818027] [drm:drm_mode_setcrtc], [CRTC:3] [ 551.818029] [drm:drm_mode_setcrtc], Count connectors is 1 but no mode or fb set [ 551.818038] [drm:drm_mode_getconnector], [CONNECTOR:21:?] [ 551.818041] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-3] [ 551.820598] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 551.825056] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 551.829050] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 551.830489] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 551.830496] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-3] disconnected [ 551.830505] [drm:drm_mode_getconnector], [CONNECTOR:21:?] [ 551.830511] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-3] [ 551.833076] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 551.837039] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 551.841034] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 551.842474] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 551.842479] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-3] disconnected [ 551.849393] [drm:intel_crtc_set_config], [CRTC:3] [FB:26] #connectors=1 (x y) (0 0) [ 551.849398] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 551.849400] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 551.849402] [drm:drm_mode_debug_printmodeline], Modeline 108:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 551.849405] [drm:drm_mode_debug_printmodeline], Modeline 25:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [ 551.849409] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 551.849411] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 551.849414] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 551.849416] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 551.849417] [drm:drm_mode_debug_printmodeline], Modeline 25:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [ 551.849420] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 551.849427] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz [ 551.849430] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24 [ 551.849432] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400 [ 551.849434] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 551.849442] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10 [ 551.849444] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8) [ 551.849446] [drm:ironlake_crtc_mode_set], Mode for pipe 0: [ 551.849448] [drm:drm_mode_debug_printmodeline], Modeline 25:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [ 551.849460] [drm:intel_get_pch_pll], CRTC:3 allocated PCH PLL c6014 [ 551.849462] [drm:intel_get_pch_pll], using pll 0 for pipe 0 [ 551.849464] [drm:intel_get_pch_pll], switching PLL c6014 off [ 551.901434] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 551.901443] [drm:ironlake_update_plane], Writing base 00072000 00000000 0 0 7680 [ 551.901455] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6 [ 551.901458] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 551.901461] [drm:ironlake_check_srwm], watermark 2: display plane 22, fbc lines 3, cursor 6 [ 551.901463] [drm:ironlake_check_srwm], watermark 3: display plane 108, fbc lines 3, cursor 6 [ 551.901466] [drm:intel_set_mode], [ENCODER:20:TMDS-20] set [MODE:25:1920x1200] [ 551.901470] [drm:intel_dp_mode_set], Enabling DP audio on pipe A [ 551.901473] [drm:intel_write_eld], ELD on [CONNECTOR:19:DP-2], [ENCODER:20:TMDS-20] [ 551.901476] [drm:ironlake_write_eld], ELD on pipe A [ 551.901479] [drm:ironlake_write_eld], Audio directed to unknown port [ 551.901480] [drm:ironlake_write_eld], ELD: DisplayPort detected [ 551.901497] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6 [ 551.901500] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 551.901502] [drm:ironlake_check_srwm], watermark 2: display plane 22, fbc lines 3, cursor 6 [ 551.901504] [drm:ironlake_check_srwm], watermark 3: display plane 108, fbc lines 3, cursor 6 [ 551.953367] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 552.005300] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 552.006118] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x100 [ 552.006122] [drm:gen6_fdi_link_train], FDI train 1 done. [ 552.006778] [drm:gen6_fdi_link_train], FDI_RX_IIR 0x600 [ 552.006782] [drm:gen6_fdi_link_train], FDI train 2 done. [ 552.006783] [drm:gen6_fdi_link_train], FDI train done. [ 552.006785] [drm:intel_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3 [ 552.006789] [drm:intel_enable_pch_pll], enabling PCH PLL c6014 [ 552.008440] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000 [ 552.009379] [drm:intel_dp_start_link_train], training pattern 1 signal levels 02800000 [ 552.010214] [drm:intel_dp_start_link_train], clock recovery OK [ 552.032645] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 552.034273] [drm:intel_connector_check_state], [CONNECTOR:19:DP-2] [ 552.034281] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 552.034284] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 552.034288] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 552.034291] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 552.034294] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 552.034298] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 552.034302] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 552.034305] [drm:intel_modeset_check_state], [CRTC:3] [ 552.034307] [drm:intel_modeset_check_state], [CRTC:5] [ 552.034310] [drm:intel_crtc_set_config], [CRTC:5] [NOFB] [ 552.034313] [drm:intel_modeset_stage_output_state], [CONNECTOR:19:DP-2] to [CRTC:3] [ 561.847746] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40000, result 0 [ 561.847750] [drm:intel_crt_detect], CRT not detected via hotplug [ 561.848154] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb [ 561.848156] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] [ 561.848159] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 561.848568] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb [ 561.848570] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 561.851128] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 561.855078] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 561.859070] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 561.860510] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 561.860516] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 2 to 2 [ 561.862514] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 561.862521] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 561.862526] [drm:output_poll_execute], [CONNECTOR:16:HDMI-A-2] status updated from 2 to 2 [ 561.864511] [drm:gmbus_xfer], GMBUS [i915 gmbus dpd] NAK for addr: 0050 r(1) [ 561.864518] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpd [ 561.864523] [drm:output_poll_execute], [CONNECTOR:18:HDMI-A-3] status updated from 2 to 2 [ 561.864849] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 561.865897] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 561.893442] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 561.920990] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 561.920993] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 561.920995] [drm:output_poll_execute], [CONNECTOR:19:DP-2] status updated from 1 to 1 [ 561.923552] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 561.927991] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 561.931974] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 561.933426] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 561.933430] [drm:output_poll_execute], [CONNECTOR:21:DP-3] status updated from 2 to 2 [ 606.526174] [drm:intel_dp_link_down], [ 606.557064] [drm:intel_prepare_page_flip], preparing flip with no unpin work? [ 606.590667] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3 [ 606.590677] [drm:intel_disable_pch_pll], disabling PCH PLL c6014 [ 606.591089] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6 [ 606.591092] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 606.591094] [drm:ironlake_check_srwm], watermark 2: display plane 22, fbc lines 3, cursor 6 [ 606.591096] [drm:ironlake_check_srwm], watermark 3: display plane 108, fbc lines 3, cursor 6 [ 606.591107] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 606.591110] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 606.591113] [drm:intel_modeset_check_state], [ENCODER:14:TMDS-14] [ 606.591116] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15] [ 606.591118] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17] [ 606.591121] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 606.591124] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22] [ 606.591126] [drm:intel_modeset_check_state], [CRTC:3] [ 606.591128] [drm:intel_modeset_check_state], [CRTC:5] [ 606.591218] [drm:i915_hotplug_work_func], running encoder hotplug functions [ 606.591233] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40000, result 0 [ 606.591236] [drm:intel_crt_detect], CRT not detected via hotplug [ 606.591659] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb [ 606.591664] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] [ 606.591668] [drm:output_poll_execute], [CONNECTOR:7:VGA-1] status updated from 2 to 2 [ 606.592073] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb [ 606.592075] [drm:output_poll_execute], [CONNECTOR:10:HDMI-A-1] status updated from 2 to 2 [ 606.594632] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 606.599173] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 606.603164] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 606.604606] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 606.604611] [drm:output_poll_execute], [CONNECTOR:13:DP-1] status updated from 2 to 2 [ 606.606611] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 606.606618] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 606.606622] [drm:output_poll_execute], [CONNECTOR:16:HDMI-A-2] status updated from 2 to 2 [ 606.608610] [drm:gmbus_xfer], GMBUS [i915 gmbus dpd] NAK for addr: 0050 r(1) [ 606.608617] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpd [ 606.608621] [drm:output_poll_execute], [CONNECTOR:18:HDMI-A-3] status updated from 2 to 2 [ 606.608946] [drm:intel_dp_detect], DPCD: 110a840101000000 [ 606.609995] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 606.637558] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 606.665120] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2 [ 606.665123] [drm:drm_detect_monitor_audio], Monitor has basic audio support [ 606.665125] [drm:output_poll_execute], [CONNECTOR:19:DP-2] status updated from 1 to 1 [ 606.667690] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 606.672075] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 606.676069] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003f [ 606.677510] [drm:intel_dp_detect], DPCD: 0000000000000000 [ 606.677515] [drm:output_poll_execute], [CONNECTOR:21:DP-3] status updated from 2 to 2