From 58ec6436938a1ba705bcf172f8f7e895e9daa617 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 18 Oct 2012 10:08:52 -0400 Subject: [PATCH] drm/radeon: adjust evergreen_mc_resume() order Adjust the crtc base addresses after re-enabling the MC. May fix: https://bugs.freedesktop.org/show_bug.cgi?id=56139 Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org --- drivers/gpu/drm/radeon/evergreen.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index f49054e..02fdbbb 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -1567,6 +1567,13 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s u32 tmp, frame_count; int i, j; + /* unblackout the MC */ + tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); + tmp &= ~BLACKOUT_MODE_MASK; + WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); + /* allow CPU access */ + WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); + /* update crtc base addresses */ for (i = 0; i < rdev->num_crtc; i++) { WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], @@ -1581,13 +1588,6 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); - /* unblackout the MC */ - tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); - tmp &= ~BLACKOUT_MODE_MASK; - WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); - /* allow CPU access */ - WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); - for (i = 0; i < rdev->num_crtc; i++) { if (save->crtc_enabled) { if (ASIC_IS_DCE6(rdev)) { -- 1.7.7.5