diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index af31f82..1cda3a7 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1297,37 +1297,55 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
 {
 	u32 crtc_enabled, tmp, frame_count, blackout;
 	int i, j;
+	printk(KERN_INFO "DEBUG: Passed %s %d \n", __FUNCTION__, __LINE__);
 
 	save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
+	printk(KERN_INFO "VGA_RENDER_CONTROL (0x%08X) saved to save->vga_render_control: %d\n", VGA_RENDER_CONTROL, save->vga_render_control);
 	save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
+	printk(KERN_INFO "VGA_HDP_CONTROL (0x%08X) saved to save->vga_hdp_control: %d\n", VGA_HDP_CONTROL, save->vga_hdp_control);
 
 	/* disable VGA render */
 	WREG32(VGA_RENDER_CONTROL, 0);
+	mdelay(1);
+	WREG32(VGA_HDP_CONTROL, 0);
 	/* blank the display controllers */
 	for (i = 0; i < rdev->num_crtc; i++) {
 		crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
 		if (crtc_enabled) {
+			printk(KERN_INFO "crtc[%d] enabled. Saving state.\n", i);
 			save->crtc_enabled[i] = true;
 			if (ASIC_IS_DCE6(rdev)) {
+				printk(KERN_INFO "ASIC IS DCE6\n");
 				tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
+				printk(KERN_INFO "Reading from EVERGREEN_CRTC_BLANK_CONTROL (0x%08X) + crtc_offsets[%d] (0x%08X) tmp value: %d\n", EVERGREEN_CRTC_BLANK_CONTROL, i, crtc_offsets[i], tmp);
 				if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
 					radeon_wait_for_vblank(rdev, i);
 					tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
+					printk(KERN_INFO "tmp |= EVERGREEN_CRTC_BLANK_DATA_EN value: %d\n", tmp);
+					printk(KERN_INFO "Waiting for vblank before writing tmp (%d) to EVERGREEN_CRTC_BLANK_CONTROL (0x%08X) + crtc_offset[%d] (0x%08X)\n", tmp, EVERGREEN_CRTC_BLANK_CONTROL, i, crtc_offsets[i]);
 					WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 				}
 			} else {
+				printk(KERN_INFO "ASIC IS NOT DCE6\n");
 				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
+				printk(KERN_INFO "Reading from EVERGREEN_CRTC_CONTROL (0x%08X) + crtc_offsets[%d] (0x%08X) tmp value: %d\n", EVERGREEN_CRTC_CONTROL, i, crtc_offsets[i], tmp);
 				if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
 					radeon_wait_for_vblank(rdev, i);
 					tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
+					/* tmp = 0; */
+					printk(KERN_INFO "tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE value: %d\n", tmp);
+					printk(KERN_INFO "Waiting for vblank before writing tmp (%d) to EVERGREEN_CRTC_CONTROL (0x%08X) + crtc_offset[%d] (0x%08X)\n", tmp, EVERGREEN_CRTC_CONTROL, i, crtc_offsets[i]);
 					WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
 				}
 			}
 			/* wait for the next frame */
 			frame_count = radeon_get_vblank_counter(rdev, i);
 			for (j = 0; j < rdev->usec_timeout; j++) {
-				if (radeon_get_vblank_counter(rdev, i) != frame_count)
+//				printk(KERN_INFO "Counting until timeout (%d of %d)\n", j, rdev->usec_timeout);
+				if (radeon_get_vblank_counter(rdev, i) != frame_count) {
+					printk(KERN_INFO "vblank_counter (%d) is different from frame_count(%d)\n", radeon_get_vblank_counter(rdev, i), frame_count);
 					break;
+				}
 				udelay(1);
 			}
 		}
@@ -1336,11 +1354,13 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
 	radeon_mc_wait_for_idle(rdev);
 
 	blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
+	printk(KERN_INFO "blackout value: %d\n",blackout);
 	if ((blackout & BLACKOUT_MODE_MASK) != 1) {
 		/* Block CPU access */
 		WREG32(BIF_FB_EN, 0);
 		/* blackout the MC */
 		blackout &= ~BLACKOUT_MODE_MASK;
+		printk(KERN_INFO "Writing blackout &= ~BLACKOUT_MODE_MASK (%d) | 1 to MC_SHARED_BLACKOUT_CNTL (0x%08X)\n", blackout, MC_SHARED_BLACKOUT_CNTL);
 		WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
 	}
 }
@@ -1349,51 +1369,73 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
 {
 	u32 tmp, frame_count;
 	int i, j;
+	printk(KERN_INFO "DEBUG: Passed %s %d \n", __FUNCTION__, __LINE__);
 
 	/* update crtc base addresses */
 	for (i = 0; i < rdev->num_crtc; i++) {
+		printk(KERN_INFO "Writing upper_32_bits(rdev->mc.vram_start) (0x%08X) to EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[%d] (0x%08X)\n", upper_32_bits(rdev->mc.vram_start), i, crtc_offsets[i]);
 		WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 		       upper_32_bits(rdev->mc.vram_start));
+		printk(KERN_INFO "Writing upper_32_bits(rdev->mc.vram_start) (0x%08X) to EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[%d] (0x%08X)\n", upper_32_bits(rdev->mc.vram_start), i, crtc_offsets[i]);
 		WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 		       upper_32_bits(rdev->mc.vram_start));
+		printk(KERN_INFO "Writing (u32)rdev->mc.vram_start (0x%08X) to EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[%d] (0x%08X)\n", (u32)rdev->mc.vram_start, i, crtc_offsets[i]);
 		WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 		       (u32)rdev->mc.vram_start);
+		printk(KERN_INFO "Writing (u32)rdev->mc.vram_start (0x%08X) to EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[%d] (0x%08X)\n", (u32)rdev->mc.vram_start, i, crtc_offsets[i]);
 		WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 		       (u32)rdev->mc.vram_start);
 	}
+	printk(KERN_INFO "Writing upper_32_bits(rdev->mc.vram_start) (0x%08X) to EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH (0x%08X)\n", upper_32_bits(rdev->mc.vram_start), EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH);
 	WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
+	printk(KERN_INFO "Writing (u32)rdev->mc.vram_start (0x%08X) to EVERGREEN_VGA_MEMORY_BASE_ADDRESS (0x%08X)\n", (u32)rdev->mc.vram_start, EVERGREEN_VGA_MEMORY_BASE_ADDRESS);
 	WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
 
 	/* unblackout the MC */
 	tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
+	printk(KERN_INFO "Reading MC_SHARED_BLACKOUT_CNTL (0x%08X) tmp value: %d\n", MC_SHARED_BLACKOUT_CNTL, tmp);
 	tmp &= ~BLACKOUT_MODE_MASK;
+	printk(KERN_INFO "Writing tmp &= ~BLACKOUT_MODE_MASK (%d) to MC_SHARED_BLACKOUT_CNTL (0x%08X)\n", tmp, MC_SHARED_BLACKOUT_CNTL);
 	WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
 	/* allow CPU access */
+	printk(KERN_INFO "Writing FB_READ_EN | FB_WRITE_EN (%d) to BIF_FB_EN (0x%08X)\n", FB_READ_EN | FB_WRITE_EN, BIF_FB_EN);
 	WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
 
 	for (i = 0; i < rdev->num_crtc; i++) {
 		if (save->crtc_enabled[i]) {
+			printk(KERN_INFO "Restoring crtc[%d] since it was enabled.\n", i);
 			if (ASIC_IS_DCE6(rdev)) {
+				printk(KERN_INFO "ASIC IS DCE6\n");
 				tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
+				printk(KERN_INFO "Reading EVERGREEN_CRTC_CONTROL (0x%08X) + crtc_offsets[%d] (0x%08X) tmp value: %d\n", EVERGREEN_CRTC_CONTROL, i, crtc_offsets[i], tmp);
 				tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
+				printk(KERN_INFO "Writing tmp |= EVERGREEN_CRTC_BLANK_DATA_EN (%d) to EVERGREEN_CRTC_BLANK_CONTROL (0x%08X) + crtc_offsets[%d] (0x%08X)\n", tmp, EVERGREEN_CRTC_BLANK_CONTROL, i, crtc_offsets[i]);
 				WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 			} else {
+				printk(KERN_INFO "ASIC IS NOT DCE6\n");
 				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
+				printk(KERN_INFO "Reading EVERGREEN_CRTC_CONTROL (0x%08X) + crtc_offsets[%d] (0x%08X) tmp value: %d\n", EVERGREEN_CRTC_CONTROL, i, crtc_offsets[i], tmp);
 				tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
+				printk(KERN_INFO "Writing tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (%d) to EVERGREEN_CRTC_CONTROL (0x%08X) + crtc_offsets[%d] (0x%08X)\n", tmp, EVERGREEN_CRTC_CONTROL, i, crtc_offsets[i]);
 				WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
 			}
 			/* wait for the next frame */
 			frame_count = radeon_get_vblank_counter(rdev, i);
 			for (j = 0; j < rdev->usec_timeout; j++) {
-				if (radeon_get_vblank_counter(rdev, i) != frame_count)
+//				printk(KERN_INFO "Counting until timeout (%d of %d)\n", j, rdev->usec_timeout);
+				if (radeon_get_vblank_counter(rdev, i) != frame_count) {
+					printk(KERN_INFO "vblank_counter (%d) is different from frame_count(%d)\n", radeon_get_vblank_counter(rdev, i), frame_count);
 					break;
+				}
 				udelay(1);
 			}
 		}
 	}
 	/* Unlock vga access */
+	printk(KERN_INFO "Restoring save->vga_hdp_control (%d) to VGA_HDP_CONTROL (0x%08X)\n", save->vga_hdp_control, VGA_HDP_CONTROL);
 	WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
 	mdelay(1);
+	printk(KERN_INFO "Restoring save->vga_render_control (%d) to VGA_RENDER_CONTROL (0x%08X)\n", save->vga_render_control, VGA_RENDER_CONTROL);
 	WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
 }
 
@@ -1403,6 +1445,8 @@ void evergreen_mc_program(struct radeon_device *rdev)
 	u32 tmp;
 	int i, j;
 
+	printk(KERN_INFO "DEBUG: Passed %s %d \n", __FUNCTION__, __LINE__);
+
 	/* Initialize HDP */
 	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 		WREG32((0x2c14 + j), 0x00000000);