[ 233.591247] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 233.591249] [drm:drm_mode_debug_printmodeline], Modeline 95:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [ 233.591252] [drm:drm_mode_debug_printmodeline], Modeline 99:"1920x1080" 60 172780 1920 2040 2248 2576 1080 1081 1084 1118 0x0 0x6 [ 233.591255] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 233.591256] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 233.591257] [drm:drm_mode_debug_printmodeline], Modeline 99:"1920x1080" 60 172780 1920 2040 2248 2576 1080 1081 1084 1118 0x0 0x6 [ 233.591260] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 233.591263] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 233.611090] [drm:g4x_check_srwm], SR watermark: display plane 118, cursor 6 [ 233.611093] [drm:g4x_check_srwm], display watermark is too large(118/63), disabling [ 233.611096] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=51, cursor=6, B: plane=2, cursor=2, SR: plane=118, cursor=6 [ 233.611419] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 233.611421] [drm:drm_mode_debug_printmodeline], Modeline 99:"1920x1080" 60 172780 1920 2040 2248 2576 1080 1081 1084 1118 0x0 0x6 [ 233.611423] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 233.629091] [drm:i9xx_update_plane], Writing base 011DA000 00000000 0 0 7680 [ 233.645090] [drm:g4x_check_srwm], SR watermark: display plane 122, cursor 6 [ 233.645093] [drm:g4x_check_srwm], display watermark is too large(122/63), disabling [ 233.645095] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=56, cursor=6, B: plane=2, cursor=2, SR: plane=122, cursor=6 [ 233.645100] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:99:1920x1080] [ 233.645103] [drm:g4x_check_srwm], SR watermark: display plane 122, cursor 6 [ 233.645105] [drm:g4x_check_srwm], display watermark is too large(122/63), disabling [ 233.645107] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=56, cursor=6, B: plane=2, cursor=2, SR: plane=122, cursor=6 [ 233.663130] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 233.664629] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 233.667232] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 233.667234] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 233.668719] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 233.671319] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 233.672804] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 233.675405] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 233.676890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 233.679491] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 233.680976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 233.683578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 233.683580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 233.683581] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 233.683583] [drm:intel_modeset_check_state], [CRTC:3] [ 233.683584] [drm:intel_modeset_check_state], [CRTC:4] [ 234.464084] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 234.465578] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 234.520680] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 234.520683] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 238.729515] [drm:drm_mode_addfb], [FB:99] [ 238.729548] [drm:drm_mode_setcrtc], [CRTC:3] [ 238.729553] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 238.729555] [drm:intel_crtc_set_config], [CRTC:3] [FB:99] #connectors=1 (x y) (0 0) [ 238.729559] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 238.729561] [drm:drm_mode_debug_printmodeline], Modeline 99:"1920x1080" 60 172780 1920 2040 2248 2576 1080 1081 1084 1118 0x0 0x6 [ 238.729563] [drm:drm_mode_debug_printmodeline], Modeline 100:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 238.729566] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 238.729568] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 238.729569] [drm:drm_mode_debug_printmodeline], Modeline 100:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 238.729572] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 238.729576] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 238.763086] [drm:g4x_check_srwm], SR watermark: display plane 122, cursor 6 [ 238.763089] [drm:g4x_check_srwm], display watermark is too large(122/63), disabling [ 238.763092] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=56, cursor=6, B: plane=2, cursor=2, SR: plane=122, cursor=6 [ 238.763431] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 238.763432] [drm:drm_mode_debug_printmodeline], Modeline 100:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 238.763435] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 238.781083] [drm:i9xx_update_plane], Writing base 019C3000 00000000 0 0 6400 [ 238.797083] [drm:g4x_check_srwm], SR watermark: display plane 102, cursor 6 [ 238.797085] [drm:g4x_check_srwm], display watermark is too large(102/63), disabling [ 238.797088] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=53, cursor=6, B: plane=2, cursor=2, SR: plane=102, cursor=6 [ 238.797092] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:100:1600x1200] [ 238.797096] [drm:g4x_check_srwm], SR watermark: display plane 102, cursor 6 [ 238.797098] [drm:g4x_check_srwm], display watermark is too large(102/63), disabling [ 238.797100] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=53, cursor=6, B: plane=2, cursor=2, SR: plane=102, cursor=6 [ 238.815121] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 238.816613] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 238.819215] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 238.819217] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 238.820703] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 238.823301] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 238.824785] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 238.827383] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 238.828868] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 238.831469] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 238.832954] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 238.835556] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 238.835557] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 238.835559] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 238.835560] [drm:intel_modeset_check_state], [CRTC:3] [ 238.835562] [drm:intel_modeset_check_state], [CRTC:4] [ 243.880658] [drm:drm_mode_addfb], [FB:100] [ 243.880692] [drm:drm_mode_setcrtc], [CRTC:3] [ 243.880696] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 243.880698] [drm:intel_crtc_set_config], [CRTC:3] [FB:100] #connectors=1 (x y) (0 0) [ 243.880702] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 243.880703] [drm:drm_mode_debug_printmodeline], Modeline 100:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 243.880706] [drm:drm_mode_debug_printmodeline], Modeline 101:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6 [ 243.880709] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 243.880711] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 243.880712] [drm:drm_mode_debug_printmodeline], Modeline 101:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6 [ 243.880715] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 243.880718] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 243.914092] [drm:g4x_check_srwm], SR watermark: display plane 102, cursor 6 [ 243.914096] [drm:g4x_check_srwm], display watermark is too large(102/63), disabling [ 243.914098] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=53, cursor=6, B: plane=2, cursor=2, SR: plane=102, cursor=6 [ 243.914437] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 243.914438] [drm:drm_mode_debug_printmodeline], Modeline 101:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6 [ 243.914441] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 243.932091] [drm:i9xx_update_plane], Writing base 02116000 00000000 0 0 6720 [ 243.948090] [drm:g4x_check_srwm], SR watermark: display plane 107, cursor 6 [ 243.948093] [drm:g4x_check_srwm], display watermark is too large(107/63), disabling [ 243.948095] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=48, cursor=6, B: plane=2, cursor=2, SR: plane=107, cursor=6 [ 243.948099] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:101:1680x1050] [ 243.948103] [drm:g4x_check_srwm], SR watermark: display plane 107, cursor 6 [ 243.948105] [drm:g4x_check_srwm], display watermark is too large(107/63), disabling [ 243.948107] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=48, cursor=6, B: plane=2, cursor=2, SR: plane=107, cursor=6 [ 243.966130] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 243.967628] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 243.970232] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 243.970234] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 243.971719] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 243.974319] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 243.975804] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 243.978406] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 243.979890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 243.982492] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 243.983976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 243.986578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 243.986580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 243.986581] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 243.986583] [drm:intel_modeset_check_state], [CRTC:3] [ 243.986584] [drm:intel_modeset_check_state], [CRTC:4] [ 244.544075] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 244.545569] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 244.600680] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 244.600682] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 249.030456] [drm:drm_mode_addfb], [FB:101] [ 249.030486] [drm:drm_mode_setcrtc], [CRTC:3] [ 249.030490] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 249.030492] [drm:intel_crtc_set_config], [CRTC:3] [FB:101] #connectors=1 (x y) (0 0) [ 249.030495] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 249.030497] [drm:drm_mode_debug_printmodeline], Modeline 101:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6 [ 249.030500] [drm:drm_mode_debug_printmodeline], Modeline 102:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6 [ 249.030503] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 249.030504] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 249.030506] [drm:drm_mode_debug_printmodeline], Modeline 102:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6 [ 249.030509] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 249.030512] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 249.064093] [drm:g4x_check_srwm], SR watermark: display plane 107, cursor 6 [ 249.064096] [drm:g4x_check_srwm], display watermark is too large(107/63), disabling [ 249.064099] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=48, cursor=6, B: plane=2, cursor=2, SR: plane=107, cursor=6 [ 249.064437] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 249.064438] [drm:drm_mode_debug_printmodeline], Modeline 102:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6 [ 249.064441] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 249.082093] [drm:i9xx_update_plane], Writing base 027D1000 00000000 0 0 6720 [ 249.098093] [drm:g4x_check_srwm], SR watermark: display plane 101, cursor 6 [ 249.098095] [drm:g4x_check_srwm], display watermark is too large(101/63), disabling [ 249.098098] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=44, cursor=6, B: plane=2, cursor=2, SR: plane=101, cursor=6 [ 249.098102] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:102:1680x945] [ 249.098105] [drm:g4x_check_srwm], SR watermark: display plane 101, cursor 6 [ 249.098107] [drm:g4x_check_srwm], display watermark is too large(101/63), disabling [ 249.098110] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=44, cursor=6, B: plane=2, cursor=2, SR: plane=101, cursor=6 [ 249.116127] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 249.117628] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 249.120232] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 249.120233] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 249.121719] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 249.124319] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 249.125804] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 249.128407] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 249.129898] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 249.132497] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 249.133984] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 249.136582] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 249.136584] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 249.136586] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 249.136587] [drm:intel_modeset_check_state], [CRTC:3] [ 249.136589] [drm:intel_modeset_check_state], [CRTC:4] [ 254.179608] [drm:drm_mode_addfb], [FB:102] [ 254.179646] [drm:drm_mode_setcrtc], [CRTC:3] [ 254.179650] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 254.179652] [drm:intel_crtc_set_config], [CRTC:3] [FB:102] #connectors=1 (x y) (0 0) [ 254.179655] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 254.179657] [drm:drm_mode_debug_printmodeline], Modeline 102:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6 [ 254.179660] [drm:drm_mode_debug_printmodeline], Modeline 103:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6 [ 254.179663] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 254.179664] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 254.179666] [drm:drm_mode_debug_printmodeline], Modeline 103:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6 [ 254.179669] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 254.179672] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 254.211093] [drm:g4x_check_srwm], SR watermark: display plane 101, cursor 6 [ 254.211096] [drm:g4x_check_srwm], display watermark is too large(101/63), disabling [ 254.211099] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=44, cursor=6, B: plane=2, cursor=2, SR: plane=101, cursor=6 [ 254.211452] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 254.211454] [drm:drm_mode_debug_printmodeline], Modeline 103:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6 [ 254.211456] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 254.229095] [drm:i9xx_update_plane], Writing base 02DE0000 00000000 0 0 5632 [ 254.245094] [drm:g4x_check_srwm], SR watermark: display plane 90, cursor 6 [ 254.245097] [drm:g4x_check_srwm], display watermark is too large(90/63), disabling [ 254.245099] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=41, cursor=6, B: plane=2, cursor=2, SR: plane=90, cursor=6 [ 254.245103] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:103:1400x1050] [ 254.245107] [drm:g4x_check_srwm], SR watermark: display plane 90, cursor 6 [ 254.245109] [drm:g4x_check_srwm], display watermark is too large(90/63), disabling [ 254.245111] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=41, cursor=6, B: plane=2, cursor=2, SR: plane=90, cursor=6 [ 254.263127] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 254.264628] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 254.267232] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 254.267234] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 254.268719] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 254.271319] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 254.272804] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 254.275405] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 254.276890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 254.279492] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 254.280976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 254.283578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 254.283580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 254.283582] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 254.283583] [drm:intel_modeset_check_state], [CRTC:3] [ 254.283584] [drm:intel_modeset_check_state], [CRTC:4] [ 254.624086] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 254.625585] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 254.680675] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 254.680677] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 259.326584] [drm:drm_mode_addfb], [FB:103] [ 259.326622] [drm:drm_mode_setcrtc], [CRTC:3] [ 259.326626] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 259.326628] [drm:intel_crtc_set_config], [CRTC:3] [FB:103] #connectors=1 (x y) (0 0) [ 259.326632] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 259.326633] [drm:drm_mode_debug_printmodeline], Modeline 103:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6 [ 259.326636] [drm:drm_mode_debug_printmodeline], Modeline 104:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6 [ 259.326639] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 259.326641] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 259.326642] [drm:drm_mode_debug_printmodeline], Modeline 104:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6 [ 259.326645] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 259.326648] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 259.358093] [drm:g4x_check_srwm], SR watermark: display plane 90, cursor 6 [ 259.358096] [drm:g4x_check_srwm], display watermark is too large(90/63), disabling [ 259.358098] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=41, cursor=6, B: plane=2, cursor=2, SR: plane=90, cursor=6 [ 259.358452] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 259.358453] [drm:drm_mode_debug_printmodeline], Modeline 104:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6 [ 259.358456] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 259.376093] [drm:i9xx_update_plane], Writing base 03384000 00000000 0 0 6400 [ 259.392092] [drm:g4x_check_srwm], SR watermark: display plane 92, cursor 6 [ 259.392095] [drm:g4x_check_srwm], display watermark is too large(92/63), disabling [ 259.392097] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=40, cursor=6, B: plane=2, cursor=2, SR: plane=92, cursor=6 [ 259.392102] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:104:1600x900] [ 259.392105] [drm:g4x_check_srwm], SR watermark: display plane 92, cursor 6 [ 259.392107] [drm:g4x_check_srwm], display watermark is too large(92/63), disabling [ 259.392110] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=40, cursor=6, B: plane=2, cursor=2, SR: plane=92, cursor=6 [ 259.410116] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 259.411611] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 259.414211] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 259.414213] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 259.415698] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 259.418297] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 259.419784] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 259.422383] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 259.423868] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 259.426469] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 259.427955] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 259.430556] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 259.430558] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 259.430559] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 259.430561] [drm:intel_modeset_check_state], [CRTC:3] [ 259.430562] [drm:intel_modeset_check_state], [CRTC:4] [ 264.472696] [drm:drm_mode_addfb], [FB:104] [ 264.472732] [drm:drm_mode_setcrtc], [CRTC:3] [ 264.472736] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 264.472738] [drm:intel_crtc_set_config], [CRTC:3] [FB:104] #connectors=1 (x y) (0 0) [ 264.472742] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 264.472743] [drm:drm_mode_debug_printmodeline], Modeline 104:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6 [ 264.472746] [drm:drm_mode_debug_printmodeline], Modeline 105:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 264.472749] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 264.472751] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 264.472752] [drm:drm_mode_debug_printmodeline], Modeline 105:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 264.472755] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 264.472758] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 264.490092] [drm:g4x_check_srwm], SR watermark: display plane 92, cursor 6 [ 264.490096] [drm:g4x_check_srwm], display watermark is too large(92/63), disabling [ 264.490098] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=40, cursor=6, B: plane=2, cursor=2, SR: plane=92, cursor=6 [ 264.490437] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 264.490438] [drm:drm_mode_debug_printmodeline], Modeline 105:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 264.490441] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 264.504094] [drm:i9xx_update_plane], Writing base 03903000 00000000 0 0 5120 [ 264.518094] [drm:g4x_check_srwm], SR watermark: display plane 104, cursor 10 [ 264.518097] [drm:g4x_check_srwm], display watermark is too large(104/63), disabling [ 264.518100] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=45, cursor=6, B: plane=2, cursor=2, SR: plane=104, cursor=10 [ 264.518104] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:105:1280x1024] [ 264.518107] [drm:g4x_check_srwm], SR watermark: display plane 104, cursor 10 [ 264.518110] [drm:g4x_check_srwm], display watermark is too large(104/63), disabling [ 264.518112] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=45, cursor=6, B: plane=2, cursor=2, SR: plane=104, cursor=10 [ 264.532116] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 264.533612] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 264.536215] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 264.536217] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 264.537703] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 264.540301] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 264.541786] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 264.544388] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 264.545875] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 264.548474] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 264.549962] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 264.552561] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 264.552563] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 264.552564] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 264.552566] [drm:intel_modeset_check_state], [CRTC:3] [ 264.552567] [drm:intel_modeset_check_state], [CRTC:4] [ 264.704089] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 264.705587] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 264.760686] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 264.760687] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 269.594734] [drm:drm_mode_addfb], [FB:105] [ 269.594765] [drm:drm_mode_setcrtc], [CRTC:3] [ 269.594770] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 269.594772] [drm:intel_crtc_set_config], [CRTC:3] [FB:105] #connectors=1 (x y) (0 0) [ 269.594776] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 269.594777] [drm:drm_mode_debug_printmodeline], Modeline 105:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 269.594780] [drm:drm_mode_debug_printmodeline], Modeline 106:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 269.594783] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 269.594785] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 269.594786] [drm:drm_mode_debug_printmodeline], Modeline 106:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 269.594789] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 269.594792] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 269.614090] [drm:g4x_check_srwm], SR watermark: display plane 104, cursor 10 [ 269.614093] [drm:g4x_check_srwm], display watermark is too large(104/63), disabling [ 269.614096] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=45, cursor=6, B: plane=2, cursor=2, SR: plane=104, cursor=10 [ 269.614435] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 269.614436] [drm:drm_mode_debug_printmodeline], Modeline 106:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 269.614438] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 269.632076] [drm:i9xx_update_plane], Writing base 03E03000 00000000 0 0 5120 [ 269.648090] [drm:g4x_check_srwm], SR watermark: display plane 82, cursor 6 [ 269.648093] [drm:g4x_check_srwm], display watermark is too large(82/63), disabling [ 269.648095] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=82, cursor=6 [ 269.648100] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:106:1280x1024] [ 269.648103] [drm:g4x_check_srwm], SR watermark: display plane 82, cursor 6 [ 269.648105] [drm:g4x_check_srwm], display watermark is too large(82/63), disabling [ 269.648108] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=82, cursor=6 [ 269.666130] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 269.667629] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 269.670232] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 269.670234] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 269.671719] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 269.674318] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 269.675805] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 269.678406] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 269.679890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 269.682491] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 269.683976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 269.686578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 269.686580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 269.686582] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 269.686583] [drm:intel_modeset_check_state], [CRTC:3] [ 269.686584] [drm:intel_modeset_check_state], [CRTC:4] [ 274.728338] [drm:drm_mode_addfb], [FB:106] [ 274.728369] [drm:drm_mode_setcrtc], [CRTC:3] [ 274.728373] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 274.728374] [drm:intel_crtc_set_config], [CRTC:3] [FB:106] #connectors=1 (x y) (0 0) [ 274.728378] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 274.728379] [drm:drm_mode_debug_printmodeline], Modeline 106:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 274.728382] [drm:drm_mode_debug_printmodeline], Modeline 107:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6 [ 274.728385] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 274.728387] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 274.728388] [drm:drm_mode_debug_printmodeline], Modeline 107:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6 [ 274.728391] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 274.728394] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 274.746092] [drm:g4x_check_srwm], SR watermark: display plane 82, cursor 6 [ 274.746095] [drm:g4x_check_srwm], display watermark is too large(82/63), disabling [ 274.746097] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=82, cursor=6 [ 274.746436] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 274.746437] [drm:drm_mode_debug_printmodeline], Modeline 107:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6 [ 274.746439] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 274.760091] [drm:i9xx_update_plane], Writing base 04303000 00000000 0 0 5760 [ 274.774090] [drm:g4x_check_srwm], SR watermark: display plane 92, cursor 6 [ 274.774093] [drm:g4x_check_srwm], display watermark is too large(92/63), disabling [ 274.774095] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=45, cursor=6, B: plane=2, cursor=2, SR: plane=92, cursor=6 [ 274.774100] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:107:1440x900] [ 274.774103] [drm:g4x_check_srwm], SR watermark: display plane 92, cursor 6 [ 274.774105] [drm:g4x_check_srwm], display watermark is too large(92/63), disabling [ 274.774108] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=45, cursor=6, B: plane=2, cursor=2, SR: plane=92, cursor=6 [ 274.788128] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 274.789628] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 274.792232] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 274.792234] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 274.793719] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 274.796328] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 274.797814] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 274.800415] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 274.801902] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 274.804502] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 274.805988] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 274.808588] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 274.808589] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 274.808591] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 274.808592] [drm:intel_modeset_check_state], [CRTC:3] [ 274.808594] [drm:intel_modeset_check_state], [CRTC:4] [ 274.808610] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 274.810101] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 274.865686] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 274.865688] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 279.850422] [drm:drm_mode_addfb], [FB:107] [ 279.850457] [drm:drm_mode_setcrtc], [CRTC:3] [ 279.850461] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 279.850463] [drm:intel_crtc_set_config], [CRTC:3] [FB:107] #connectors=1 (x y) (0 0) [ 279.850466] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 279.850468] [drm:drm_mode_debug_printmodeline], Modeline 107:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6 [ 279.850470] [drm:drm_mode_debug_printmodeline], Modeline 108:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6 [ 279.850473] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 279.850475] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 279.850476] [drm:drm_mode_debug_printmodeline], Modeline 108:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6 [ 279.850479] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 279.850482] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 279.866091] [drm:g4x_check_srwm], SR watermark: display plane 92, cursor 6 [ 279.866094] [drm:g4x_check_srwm], display watermark is too large(92/63), disabling [ 279.866097] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=45, cursor=6, B: plane=2, cursor=2, SR: plane=92, cursor=6 [ 279.866435] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 279.866436] [drm:drm_mode_debug_printmodeline], Modeline 108:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6 [ 279.866439] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 279.884091] [drm:i9xx_update_plane], Writing base 047F5000 00000000 0 0 5760 [ 279.900091] [drm:g4x_check_srwm], SR watermark: display plane 82, cursor 6 [ 279.900093] [drm:g4x_check_srwm], display watermark is too large(82/63), disabling [ 279.900096] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=82, cursor=6 [ 279.900100] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:108:1440x900] [ 279.900103] [drm:g4x_check_srwm], SR watermark: display plane 82, cursor 6 [ 279.900106] [drm:g4x_check_srwm], display watermark is too large(82/63), disabling [ 279.900108] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=82, cursor=6 [ 279.918129] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 279.919621] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 279.922222] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 279.922224] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 279.923714] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 279.926313] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 279.927801] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 279.930404] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 279.931890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 279.934491] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 279.935976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 279.938577] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 279.938579] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 279.938581] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 279.938582] [drm:intel_modeset_check_state], [CRTC:3] [ 279.938583] [drm:intel_modeset_check_state], [CRTC:4] [ 284.896082] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 284.897586] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 284.952663] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 284.952665] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 284.980642] [drm:drm_mode_addfb], [FB:108] [ 284.980674] [drm:drm_mode_setcrtc], [CRTC:3] [ 284.980678] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 284.980680] [drm:intel_crtc_set_config], [CRTC:3] [FB:108] #connectors=1 (x y) (0 0) [ 284.980683] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 284.980685] [drm:drm_mode_debug_printmodeline], Modeline 108:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6 [ 284.980687] [drm:drm_mode_debug_printmodeline], Modeline 109:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 [ 284.980690] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 284.980692] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 284.980693] [drm:drm_mode_debug_printmodeline], Modeline 109:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 [ 284.980696] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 284.980699] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 284.998078] [drm:g4x_check_srwm], SR watermark: display plane 82, cursor 6 [ 284.998081] [drm:g4x_check_srwm], display watermark is too large(82/63), disabling [ 284.998083] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=82, cursor=6 [ 284.998422] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 284.998423] [drm:drm_mode_debug_printmodeline], Modeline 109:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 [ 284.998426] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 285.016079] [drm:i9xx_update_plane], Writing base 04CE7000 00000000 0 0 5120 [ 285.033077] [drm:g4x_check_srwm], SR watermark: display plane 82, cursor 6 [ 285.033080] [drm:g4x_check_srwm], display watermark is too large(82/63), disabling [ 285.033082] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=82, cursor=6 [ 285.033087] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:109:1280x960] [ 285.033091] [drm:g4x_check_srwm], SR watermark: display plane 82, cursor 6 [ 285.033093] [drm:g4x_check_srwm], display watermark is too large(82/63), disabling [ 285.033096] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=82, cursor=6 [ 285.049113] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 285.050606] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 285.053205] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 285.053207] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 285.054697] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 285.057296] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 285.058784] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 285.061383] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 285.062868] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 285.065469] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 285.066955] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 285.069556] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 285.069558] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 285.069560] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 285.069561] [drm:intel_modeset_check_state], [CRTC:3] [ 285.069562] [drm:intel_modeset_check_state], [CRTC:4] [ 290.110475] [drm:drm_mode_addfb], [FB:109] [ 290.110508] [drm:drm_mode_setcrtc], [CRTC:3] [ 290.110512] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 290.110514] [drm:intel_crtc_set_config], [CRTC:3] [FB:109] #connectors=1 (x y) (0 0) [ 290.110518] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 290.110519] [drm:drm_mode_debug_printmodeline], Modeline 109:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5 [ 290.110522] [drm:drm_mode_debug_printmodeline], Modeline 110:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6 [ 290.110525] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 290.110527] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 290.110528] [drm:drm_mode_debug_printmodeline], Modeline 110:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6 [ 290.110531] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 290.110534] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 290.132093] [drm:g4x_check_srwm], SR watermark: display plane 82, cursor 6 [ 290.132096] [drm:g4x_check_srwm], display watermark is too large(82/63), disabling [ 290.132099] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=82, cursor=6 [ 290.132422] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 290.132424] [drm:drm_mode_debug_printmodeline], Modeline 110:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6 [ 290.132426] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 290.150091] [drm:i9xx_update_plane], Writing base 05197000 00000000 0 0 5504 [ 290.166091] [drm:g4x_check_srwm], SR watermark: display plane 67, cursor 6 [ 290.166093] [drm:g4x_check_srwm], display watermark is too large(67/63), disabling [ 290.166096] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=29, cursor=6, B: plane=2, cursor=2, SR: plane=67, cursor=6 [ 290.166100] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:110:1366x768] [ 290.166103] [drm:g4x_check_srwm], SR watermark: display plane 67, cursor 6 [ 290.166106] [drm:g4x_check_srwm], display watermark is too large(67/63), disabling [ 290.166108] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=29, cursor=6, B: plane=2, cursor=2, SR: plane=67, cursor=6 [ 290.184131] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 290.185629] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 290.188232] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 290.188234] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 290.189719] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 290.192319] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 290.193805] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 290.196415] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 290.197902] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 290.200502] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 290.201988] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 290.204612] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 290.204614] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 290.204616] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 290.204617] [drm:intel_modeset_check_state], [CRTC:3] [ 290.204619] [drm:intel_modeset_check_state], [CRTC:4] [ 294.976078] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 294.977577] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 295.032678] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 295.032680] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 295.245381] [drm:drm_mode_addfb], [FB:110] [ 295.245411] [drm:drm_mode_setcrtc], [CRTC:3] [ 295.245415] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 295.245417] [drm:intel_crtc_set_config], [CRTC:3] [FB:110] #connectors=1 (x y) (0 0) [ 295.245420] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 295.245422] [drm:drm_mode_debug_printmodeline], Modeline 110:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6 [ 295.245424] [drm:drm_mode_debug_printmodeline], Modeline 111:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5 [ 295.245427] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 295.245429] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 295.245430] [drm:drm_mode_debug_printmodeline], Modeline 111:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5 [ 295.245434] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 295.245436] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 295.265092] [drm:g4x_check_srwm], SR watermark: display plane 67, cursor 6 [ 295.265095] [drm:g4x_check_srwm], display watermark is too large(67/63), disabling [ 295.265097] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=29, cursor=6, B: plane=2, cursor=2, SR: plane=67, cursor=6 [ 295.265420] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 295.265422] [drm:drm_mode_debug_printmodeline], Modeline 111:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5 [ 295.265424] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 295.283092] [drm:i9xx_update_plane], Writing base 0559F000 00000000 0 0 5440 [ 295.299091] [drm:g4x_check_srwm], SR watermark: display plane 67, cursor 6 [ 295.299094] [drm:g4x_check_srwm], display watermark is too large(67/63), disabling [ 295.299096] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=29, cursor=6, B: plane=2, cursor=2, SR: plane=67, cursor=6 [ 295.299100] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:111:1360x768] [ 295.299104] [drm:g4x_check_srwm], SR watermark: display plane 67, cursor 6 [ 295.299106] [drm:g4x_check_srwm], display watermark is too large(67/63), disabling [ 295.299108] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=29, cursor=6, B: plane=2, cursor=2, SR: plane=67, cursor=6 [ 295.317129] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 295.318621] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 295.321225] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 295.321227] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 295.322714] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 295.325317] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 295.326805] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 295.329405] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 295.330890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 295.333492] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 295.334976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 295.337578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 295.337580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 295.337582] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 295.337583] [drm:intel_modeset_check_state], [CRTC:3] [ 295.337585] [drm:intel_modeset_check_state], [CRTC:4] [ 300.378100] [drm:drm_mode_addfb], [FB:111] [ 300.378131] [drm:drm_mode_setcrtc], [CRTC:3] [ 300.378134] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 300.378136] [drm:intel_crtc_set_config], [CRTC:3] [FB:111] #connectors=1 (x y) (0 0) [ 300.378140] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 300.378141] [drm:drm_mode_debug_printmodeline], Modeline 111:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5 [ 300.378144] [drm:drm_mode_debug_printmodeline], Modeline 112:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6 [ 300.378147] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 300.378149] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 300.378150] [drm:drm_mode_debug_printmodeline], Modeline 112:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6 [ 300.378153] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 300.378156] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 300.410075] [drm:g4x_check_srwm], SR watermark: display plane 67, cursor 6 [ 300.410079] [drm:g4x_check_srwm], display watermark is too large(67/63), disabling [ 300.410081] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=29, cursor=6, B: plane=2, cursor=2, SR: plane=67, cursor=6 [ 300.410420] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 300.410421] [drm:drm_mode_debug_printmodeline], Modeline 112:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6 [ 300.410424] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 300.424075] [drm:i9xx_update_plane], Writing base 0599B000 00000000 0 0 5120 [ 300.438077] [drm:g4x_check_srwm], SR watermark: display plane 82, cursor 6 [ 300.438080] [drm:g4x_check_srwm], display watermark is too large(82/63), disabling [ 300.438082] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=82, cursor=6 [ 300.438086] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:112:1280x800] [ 300.438090] [drm:g4x_check_srwm], SR watermark: display plane 82, cursor 6 [ 300.438092] [drm:g4x_check_srwm], display watermark is too large(82/63), disabling [ 300.438094] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=82, cursor=6 [ 300.452115] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 300.453611] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 300.456222] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 300.456224] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 300.457713] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 300.460313] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 300.461800] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 300.464399] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 300.465885] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 300.468486] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 300.469971] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 300.472572] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 300.472574] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 300.472575] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 300.472577] [drm:intel_modeset_check_state], [CRTC:3] [ 300.472578] [drm:intel_modeset_check_state], [CRTC:4] [ 305.056078] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 305.057574] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 305.112675] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 305.112677] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 305.513244] [drm:drm_mode_addfb], [FB:112] [ 305.513276] [drm:drm_mode_setcrtc], [CRTC:3] [ 305.513280] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 305.513282] [drm:intel_crtc_set_config], [CRTC:3] [FB:112] #connectors=1 (x y) (0 0) [ 305.513285] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 305.513286] [drm:drm_mode_debug_printmodeline], Modeline 112:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6 [ 305.513289] [drm:drm_mode_debug_printmodeline], Modeline 113:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9 [ 305.513292] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 305.513294] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 305.513295] [drm:drm_mode_debug_printmodeline], Modeline 113:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9 [ 305.513298] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 305.513301] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 305.541082] [drm:g4x_check_srwm], SR watermark: display plane 82, cursor 6 [ 305.541086] [drm:g4x_check_srwm], display watermark is too large(82/63), disabling [ 305.541088] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=82, cursor=6 [ 305.541411] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 305.541412] [drm:drm_mode_debug_printmodeline], Modeline 113:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9 [ 305.541415] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 305.559083] [drm:i9xx_update_plane], Writing base 05D83000 00000000 0 0 5120 [ 305.575074] [drm:g4x_check_srwm], SR watermark: display plane 65, cursor 6 [ 305.575077] [drm:g4x_check_srwm], display watermark is too large(65/63), disabling [ 305.575080] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=29, cursor=6, B: plane=2, cursor=2, SR: plane=65, cursor=6 [ 305.575084] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:113:1280x800] [ 305.575087] [drm:g4x_check_srwm], SR watermark: display plane 65, cursor 6 [ 305.575089] [drm:g4x_check_srwm], display watermark is too large(65/63), disabling [ 305.575092] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=29, cursor=6, B: plane=2, cursor=2, SR: plane=65, cursor=6 [ 305.593120] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 305.594616] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 305.597216] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 305.597218] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 305.598703] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 305.601301] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 305.602785] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 305.605383] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 305.606868] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 305.609469] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 305.610955] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 305.613556] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 305.613557] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 305.613559] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 305.613561] [drm:intel_modeset_check_state], [CRTC:3] [ 305.613562] [drm:intel_modeset_check_state], [CRTC:4] [ 310.653431] [drm:drm_mode_addfb], [FB:113] [ 310.653460] [drm:drm_mode_setcrtc], [CRTC:3] [ 310.653464] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 310.653466] [drm:intel_crtc_set_config], [CRTC:3] [FB:113] #connectors=1 (x y) (0 0) [ 310.653469] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 310.653471] [drm:drm_mode_debug_printmodeline], Modeline 113:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9 [ 310.653473] [drm:drm_mode_debug_printmodeline], Modeline 114:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 310.653476] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 310.653478] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 310.653479] [drm:drm_mode_debug_printmodeline], Modeline 114:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 310.653482] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 310.653485] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 310.677093] [drm:g4x_check_srwm], SR watermark: display plane 65, cursor 6 [ 310.677097] [drm:g4x_check_srwm], display watermark is too large(65/63), disabling [ 310.677099] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=29, cursor=6, B: plane=2, cursor=2, SR: plane=65, cursor=6 [ 310.677438] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 310.677439] [drm:drm_mode_debug_printmodeline], Modeline 114:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 310.677442] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 310.691095] [drm:i9xx_update_plane], Writing base 0616B000 00000000 0 0 4608 [ 310.705090] [drm:g4x_check_srwm], SR watermark: display plane 74, cursor 6 [ 310.705093] [drm:g4x_check_srwm], display watermark is too large(74/63), disabling [ 310.705095] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=74, cursor=6 [ 310.705099] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:114:1152x864] [ 310.705102] [drm:g4x_check_srwm], SR watermark: display plane 74, cursor 6 [ 310.705105] [drm:g4x_check_srwm], display watermark is too large(74/63), disabling [ 310.705107] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=74, cursor=6 [ 310.719130] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 310.720628] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 310.723232] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 310.723234] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 310.724719] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 310.727319] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 310.728805] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 310.731406] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 310.732891] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 310.735492] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 310.736976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 310.739578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 310.739580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 310.739581] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 310.739583] [drm:intel_modeset_check_state], [CRTC:3] [ 310.739584] [drm:intel_modeset_check_state], [CRTC:4] [ 315.136088] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 315.137584] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 315.192675] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 315.192677] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 315.779717] [drm:drm_mode_addfb], [FB:114] [ 315.779746] [drm:drm_mode_setcrtc], [CRTC:3] [ 315.779750] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 315.779752] [drm:intel_crtc_set_config], [CRTC:3] [FB:114] #connectors=1 (x y) (0 0) [ 315.779755] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 315.779757] [drm:drm_mode_debug_printmodeline], Modeline 114:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 315.779760] [drm:drm_mode_debug_printmodeline], Modeline 115:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9 [ 315.779763] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 315.779764] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 315.779765] [drm:drm_mode_debug_printmodeline], Modeline 115:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9 [ 315.779768] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 315.779771] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 315.799093] [drm:g4x_check_srwm], SR watermark: display plane 74, cursor 6 [ 315.799096] [drm:g4x_check_srwm], display watermark is too large(74/63), disabling [ 315.799098] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=36, cursor=6, B: plane=2, cursor=2, SR: plane=74, cursor=6 [ 315.799437] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 315.799438] [drm:drm_mode_debug_printmodeline], Modeline 115:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9 [ 315.799440] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 315.813092] [drm:i9xx_update_plane], Writing base 06537000 00000000 0 0 5120 [ 315.827091] [drm:g4x_check_srwm], SR watermark: display plane 79, cursor 6 [ 315.827093] [drm:g4x_check_srwm], display watermark is too large(79/63), disabling [ 315.827096] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=34, cursor=6, B: plane=2, cursor=2, SR: plane=79, cursor=6 [ 315.827100] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:115:1280x768] [ 315.827103] [drm:g4x_check_srwm], SR watermark: display plane 79, cursor 6 [ 315.827105] [drm:g4x_check_srwm], display watermark is too large(79/63), disabling [ 315.827108] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=34, cursor=6, B: plane=2, cursor=2, SR: plane=79, cursor=6 [ 315.841128] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 315.842621] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 315.845222] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 315.845224] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 315.846714] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 315.849317] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 315.850804] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 315.853405] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 315.854890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 315.857492] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 315.858976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 315.861578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 315.861580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 315.861582] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 315.861583] [drm:intel_modeset_check_state], [CRTC:3] [ 315.861584] [drm:intel_modeset_check_state], [CRTC:4] [ 320.901834] [drm:drm_mode_addfb], [FB:115] [ 320.901864] [drm:drm_mode_setcrtc], [CRTC:3] [ 320.901867] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 320.901869] [drm:intel_crtc_set_config], [CRTC:3] [FB:115] #connectors=1 (x y) (0 0) [ 320.901872] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 320.901874] [drm:drm_mode_debug_printmodeline], Modeline 115:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9 [ 320.901877] [drm:drm_mode_debug_printmodeline], Modeline 116:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6 [ 320.901879] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 320.901881] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 320.901882] [drm:drm_mode_debug_printmodeline], Modeline 116:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6 [ 320.901885] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 320.901888] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 320.921092] [drm:g4x_check_srwm], SR watermark: display plane 79, cursor 6 [ 320.921095] [drm:g4x_check_srwm], display watermark is too large(79/63), disabling [ 320.921097] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=34, cursor=6, B: plane=2, cursor=2, SR: plane=79, cursor=6 [ 320.921436] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 320.921437] [drm:drm_mode_debug_printmodeline], Modeline 116:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6 [ 320.921439] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 320.939092] [drm:i9xx_update_plane], Writing base 068F7000 00000000 0 0 5120 [ 320.955074] [drm:g4x_check_srwm], SR watermark: display plane 62, cursor 6 [ 320.955077] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=27, cursor=6, B: plane=2, cursor=2, SR: plane=62, cursor=6 [ 320.955081] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:116:1280x768] [ 320.955085] [drm:g4x_check_srwm], SR watermark: display plane 62, cursor 6 [ 320.955087] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=27, cursor=6, B: plane=2, cursor=2, SR: plane=62, cursor=6 [ 320.973130] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 320.974621] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 320.977222] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 320.977224] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 320.978714] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 320.981318] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 320.982805] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 320.985405] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 320.986890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 320.989492] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 320.990976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 320.993578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 320.993580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 320.993582] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 320.993583] [drm:intel_modeset_check_state], [CRTC:3] [ 320.993584] [drm:intel_modeset_check_state], [CRTC:4] [ 325.216086] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 325.217578] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 325.272674] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 325.272677] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 326.032379] [drm:drm_mode_addfb], [FB:116] [ 326.032403] [drm:drm_mode_setcrtc], [CRTC:3] [ 326.032407] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 326.032408] [drm:intel_crtc_set_config], [CRTC:3] [FB:116] #connectors=1 (x y) (0 0) [ 326.032412] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 326.032413] [drm:drm_mode_debug_printmodeline], Modeline 116:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6 [ 326.032416] [drm:drm_mode_debug_printmodeline], Modeline 117:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 326.032419] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 326.032421] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 326.032422] [drm:drm_mode_debug_printmodeline], Modeline 117:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 326.032425] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 326.032428] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 326.064091] [drm:g4x_check_srwm], SR watermark: display plane 62, cursor 6 [ 326.064094] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=27, cursor=6, B: plane=2, cursor=2, SR: plane=62, cursor=6 [ 326.064432] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 326.064434] [drm:drm_mode_debug_printmodeline], Modeline 117:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 326.064436] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 326.078093] [drm:i9xx_update_plane], Writing base 06CB7000 00000000 0 0 4096 [ 326.092092] [drm:g4x_check_srwm], SR watermark: display plane 62, cursor 6 [ 326.092095] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=27, cursor=6, B: plane=2, cursor=2, SR: plane=62, cursor=6 [ 326.092099] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:117:1024x768] [ 326.092102] [drm:g4x_check_srwm], SR watermark: display plane 62, cursor 6 [ 326.092105] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=27, cursor=6, B: plane=2, cursor=2, SR: plane=62, cursor=6 [ 326.106129] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 326.107621] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 326.110222] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 326.110224] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 326.111714] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 326.114317] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 326.115805] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 326.118406] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 326.119890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 326.122492] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 326.123976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 326.126578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 326.126580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 326.126582] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 326.126583] [drm:intel_modeset_check_state], [CRTC:3] [ 326.126584] [drm:intel_modeset_check_state], [CRTC:4] [ 331.165313] [drm:drm_mode_addfb], [FB:117] [ 331.165337] [drm:drm_mode_setcrtc], [CRTC:3] [ 331.165341] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 331.165343] [drm:intel_crtc_set_config], [CRTC:3] [FB:117] #connectors=1 (x y) (0 0) [ 331.165345] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 331.165347] [drm:drm_mode_debug_printmodeline], Modeline 117:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 331.165349] [drm:drm_mode_debug_printmodeline], Modeline 118:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 331.165352] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 331.165354] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 331.165355] [drm:drm_mode_debug_printmodeline], Modeline 118:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 331.165358] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 331.165361] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 331.179094] [drm:g4x_check_srwm], SR watermark: display plane 62, cursor 6 [ 331.179097] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=27, cursor=6, B: plane=2, cursor=2, SR: plane=62, cursor=6 [ 331.179434] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 331.179436] [drm:drm_mode_debug_printmodeline], Modeline 118:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 331.179438] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 331.195092] [drm:i9xx_update_plane], Writing base 06FB7000 00000000 0 0 4096 [ 331.209085] [drm:g4x_check_srwm], SR watermark: display plane 59, cursor 6 [ 331.209089] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=26, cursor=6, B: plane=2, cursor=2, SR: plane=59, cursor=6 [ 331.209093] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:118:1024x768] [ 331.209097] [drm:g4x_check_srwm], SR watermark: display plane 59, cursor 6 [ 331.209099] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=26, cursor=6, B: plane=2, cursor=2, SR: plane=59, cursor=6 [ 331.223124] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 331.224620] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 331.227226] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 331.227228] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 331.228714] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 331.231313] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 331.232801] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 331.235400] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 331.236886] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 331.239486] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 331.240971] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 331.243572] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 331.243573] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 331.243575] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 331.243576] [drm:intel_modeset_check_state], [CRTC:3] [ 331.243578] [drm:intel_modeset_check_state], [CRTC:4] [ 335.296087] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 335.297578] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 335.352674] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 335.352676] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 336.282406] [drm:drm_mode_addfb], [FB:118] [ 336.282433] [drm:drm_mode_setcrtc], [CRTC:3] [ 336.282437] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 336.282438] [drm:intel_crtc_set_config], [CRTC:3] [FB:118] #connectors=1 (x y) (0 0) [ 336.282441] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 336.282443] [drm:drm_mode_debug_printmodeline], Modeline 118:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa [ 336.282445] [drm:drm_mode_debug_printmodeline], Modeline 119:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 336.282448] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 336.282450] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 336.282451] [drm:drm_mode_debug_printmodeline], Modeline 119:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 336.282454] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 336.282457] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 336.304092] [drm:g4x_check_srwm], SR watermark: display plane 59, cursor 6 [ 336.304096] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=26, cursor=6, B: plane=2, cursor=2, SR: plane=59, cursor=6 [ 336.304434] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 336.304435] [drm:drm_mode_debug_printmodeline], Modeline 119:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 336.304437] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 336.322092] [drm:i9xx_update_plane], Writing base 072B7000 00000000 0 0 4096 [ 336.338091] [drm:g4x_check_srwm], SR watermark: display plane 51, cursor 6 [ 336.338094] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=23, cursor=6, B: plane=2, cursor=2, SR: plane=51, cursor=6 [ 336.338098] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:119:1024x768] [ 336.338102] [drm:g4x_check_srwm], SR watermark: display plane 51, cursor 6 [ 336.338104] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=23, cursor=6, B: plane=2, cursor=2, SR: plane=51, cursor=6 [ 336.356130] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 336.357621] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 336.360222] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 336.360224] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 336.361714] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 336.364317] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 336.365805] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 336.368405] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 336.369890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 336.372492] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 336.373976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 336.376578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 336.376580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 336.376582] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 336.376583] [drm:intel_modeset_check_state], [CRTC:3] [ 336.376584] [drm:intel_modeset_check_state], [CRTC:4] [ 341.414294] [drm:drm_mode_addfb], [FB:119] [ 341.414315] [drm:drm_mode_setcrtc], [CRTC:3] [ 341.414318] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 341.414320] [drm:intel_crtc_set_config], [CRTC:3] [FB:119] #connectors=1 (x y) (0 0) [ 341.414322] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 341.414324] [drm:drm_mode_debug_printmodeline], Modeline 119:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 341.414327] [drm:drm_mode_debug_printmodeline], Modeline 120:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6 [ 341.414330] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 341.414331] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 341.414332] [drm:drm_mode_debug_printmodeline], Modeline 120:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6 [ 341.414335] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 341.414337] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 341.438090] [drm:g4x_check_srwm], SR watermark: display plane 51, cursor 6 [ 341.438093] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=23, cursor=6, B: plane=2, cursor=2, SR: plane=51, cursor=6 [ 341.438430] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 341.438432] [drm:drm_mode_debug_printmodeline], Modeline 120:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6 [ 341.438434] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 341.456077] [drm:i9xx_update_plane], Writing base 075B7000 00000000 0 0 4096 [ 341.472092] [drm:g4x_check_srwm], SR watermark: display plane 38, cursor 6 [ 341.472095] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=17, cursor=6, B: plane=2, cursor=2, SR: plane=38, cursor=6 [ 341.472099] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:120:1024x576] [ 341.472102] [drm:g4x_check_srwm], SR watermark: display plane 38, cursor 6 [ 341.472104] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=17, cursor=6, B: plane=2, cursor=2, SR: plane=38, cursor=6 [ 341.490128] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 341.491621] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 341.494226] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 341.494227] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 341.495713] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 341.498318] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 341.499805] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 341.502406] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 341.503890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 341.506492] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 341.507976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 341.510578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 341.510580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 341.510582] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 341.510583] [drm:intel_modeset_check_state], [CRTC:3] [ 341.510584] [drm:intel_modeset_check_state], [CRTC:4] [ 345.376087] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 345.377578] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 345.432680] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 345.432682] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 346.547864] [drm:drm_mode_addfb], [FB:120] [ 346.547884] [drm:drm_mode_setcrtc], [CRTC:3] [ 346.547887] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 346.547888] [drm:intel_crtc_set_config], [CRTC:3] [FB:120] #connectors=1 (x y) (0 0) [ 346.547891] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 346.547892] [drm:drm_mode_debug_printmodeline], Modeline 120:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6 [ 346.547895] [drm:drm_mode_debug_printmodeline], Modeline 121:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 346.547897] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 346.547899] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 346.547900] [drm:drm_mode_debug_printmodeline], Modeline 121:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 346.547903] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 346.547905] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 346.575091] [drm:g4x_check_srwm], SR watermark: display plane 38, cursor 6 [ 346.575094] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=17, cursor=6, B: plane=2, cursor=2, SR: plane=38, cursor=6 [ 346.575416] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 346.575417] [drm:drm_mode_debug_printmodeline], Modeline 121:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 346.575419] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 346.591091] [drm:i9xx_update_plane], Writing base 077F7000 00000000 0 0 3200 [ 346.605090] [drm:g4x_check_srwm], SR watermark: display plane 40, cursor 6 [ 346.605093] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=45, cursor=6, B: plane=2, cursor=2, SR: plane=40, cursor=6 [ 346.605097] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:121:800x600] [ 346.605100] [drm:g4x_check_srwm], SR watermark: display plane 40, cursor 6 [ 346.605103] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=45, cursor=6, B: plane=2, cursor=2, SR: plane=40, cursor=6 [ 346.619127] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 346.620621] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 346.623222] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 346.623224] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 346.624714] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 346.627317] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 346.628804] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 346.631405] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 346.632890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 346.635492] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 346.636976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 346.639578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 346.639580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 346.639581] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 346.639583] [drm:intel_modeset_check_state], [CRTC:3] [ 346.639584] [drm:intel_modeset_check_state], [CRTC:4] [ 351.676852] [drm:drm_mode_addfb], [FB:121] [ 351.676871] [drm:drm_mode_setcrtc], [CRTC:3] [ 351.676874] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 351.676876] [drm:intel_crtc_set_config], [CRTC:3] [FB:121] #connectors=1 (x y) (0 0) [ 351.676878] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 351.676880] [drm:drm_mode_debug_printmodeline], Modeline 121:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5 [ 351.676882] [drm:drm_mode_debug_printmodeline], Modeline 122:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 351.676885] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 351.676887] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 351.676888] [drm:drm_mode_debug_printmodeline], Modeline 122:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 351.676891] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 351.676893] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 351.692091] [drm:g4x_check_srwm], SR watermark: display plane 40, cursor 6 [ 351.692094] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=45, cursor=6, B: plane=2, cursor=2, SR: plane=40, cursor=6 [ 351.692416] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 351.692417] [drm:drm_mode_debug_printmodeline], Modeline 122:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 351.692419] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 351.706084] [drm:i9xx_update_plane], Writing base 079CC000 00000000 0 0 3200 [ 351.720083] [drm:g4x_check_srwm], SR watermark: display plane 40, cursor 6 [ 351.720086] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=45, cursor=6, B: plane=2, cursor=2, SR: plane=40, cursor=6 [ 351.720090] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:122:800x600] [ 351.720093] [drm:g4x_check_srwm], SR watermark: display plane 40, cursor 6 [ 351.720096] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=45, cursor=6, B: plane=2, cursor=2, SR: plane=40, cursor=6 [ 351.734119] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 351.735613] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 351.738211] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 351.738213] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 351.739698] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 351.742297] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 351.743784] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 351.746383] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 351.747868] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 351.750469] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 351.751954] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 351.754555] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 351.754557] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 351.754559] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 351.754560] [drm:intel_modeset_check_state], [CRTC:3] [ 351.754561] [drm:intel_modeset_check_state], [CRTC:4] [ 355.456077] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 355.457572] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 355.512674] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 355.512676] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 356.791957] [drm:drm_mode_addfb], [FB:122] [ 356.791978] [drm:drm_mode_setcrtc], [CRTC:3] [ 356.791981] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 356.791982] [drm:intel_crtc_set_config], [CRTC:3] [FB:122] #connectors=1 (x y) (0 0) [ 356.791985] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 356.791987] [drm:drm_mode_debug_printmodeline], Modeline 122:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 356.791989] [drm:drm_mode_debug_printmodeline], Modeline 123:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 356.791992] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 356.791994] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 356.791995] [drm:drm_mode_debug_printmodeline], Modeline 123:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 356.791997] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 356.792044] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 356.814076] [drm:g4x_check_srwm], SR watermark: display plane 40, cursor 6 [ 356.814080] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=45, cursor=6, B: plane=2, cursor=2, SR: plane=40, cursor=6 [ 356.814417] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 356.814418] [drm:drm_mode_debug_printmodeline], Modeline 123:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 356.814421] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 356.832091] [drm:i9xx_update_plane], Writing base 07BA1000 00000000 0 0 3200 [ 356.848090] [drm:g4x_check_srwm], SR watermark: display plane 32, cursor 6 [ 356.848093] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=42, cursor=6, B: plane=2, cursor=2, SR: plane=32, cursor=6 [ 356.848097] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:123:800x600] [ 356.848100] [drm:g4x_check_srwm], SR watermark: display plane 32, cursor 6 [ 356.848103] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=42, cursor=6, B: plane=2, cursor=2, SR: plane=32, cursor=6 [ 356.866128] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 356.867621] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 356.870222] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 356.870224] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 356.871714] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 356.874318] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 356.875804] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 356.878405] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 356.879890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 356.882492] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 356.883976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 356.886578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 356.886580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 356.886581] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 356.886583] [drm:intel_modeset_check_state], [CRTC:3] [ 356.886584] [drm:intel_modeset_check_state], [CRTC:4] [ 361.923994] [drm:drm_mode_addfb], [FB:123] [ 361.924063] [drm:drm_mode_setcrtc], [CRTC:3] [ 361.924066] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 361.924068] [drm:intel_crtc_set_config], [CRTC:3] [FB:123] #connectors=1 (x y) (0 0) [ 361.924071] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 361.924072] [drm:drm_mode_debug_printmodeline], Modeline 123:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 361.924075] [drm:drm_mode_debug_printmodeline], Modeline 124:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 361.924077] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 361.924079] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 361.924080] [drm:drm_mode_debug_printmodeline], Modeline 124:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 361.924083] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 361.924085] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 361.952094] [drm:g4x_check_srwm], SR watermark: display plane 32, cursor 6 [ 361.952097] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=42, cursor=6, B: plane=2, cursor=2, SR: plane=32, cursor=6 [ 361.952434] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 361.952435] [drm:drm_mode_debug_printmodeline], Modeline 124:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 361.952438] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 361.972091] [drm:i9xx_update_plane], Writing base 07D76000 00000000 0 0 3200 [ 361.988090] [drm:g4x_check_srwm], SR watermark: display plane 29, cursor 6 [ 361.988093] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=41, cursor=6, B: plane=2, cursor=2, SR: plane=29, cursor=6 [ 361.988097] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:124:800x600] [ 361.988100] [drm:g4x_check_srwm], SR watermark: display plane 29, cursor 6 [ 361.988102] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=41, cursor=6, B: plane=2, cursor=2, SR: plane=29, cursor=6 [ 362.006120] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 362.007614] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 362.010217] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 362.010219] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 362.011706] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 362.014314] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 362.015800] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 362.018406] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 362.019890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 362.022497] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 362.023985] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 362.026585] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 362.026587] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 362.026589] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 362.026590] [drm:intel_modeset_check_state], [CRTC:3] [ 362.026591] [drm:intel_modeset_check_state], [CRTC:4] [ 365.536025] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 365.537521] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 365.592674] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 365.592676] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 367.061054] [drm:drm_mode_addfb], [FB:124] [ 367.061072] [drm:drm_mode_setcrtc], [CRTC:3] [ 367.061075] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 367.061076] [drm:intel_crtc_set_config], [CRTC:3] [FB:124] #connectors=1 (x y) (0 0) [ 367.061078] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 367.061080] [drm:drm_mode_debug_printmodeline], Modeline 124:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 367.061083] [drm:drm_mode_debug_printmodeline], Modeline 125:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 367.061085] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 367.061087] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 367.061088] [drm:drm_mode_debug_printmodeline], Modeline 125:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 367.061091] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 367.061093] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 367.091091] [drm:g4x_check_srwm], SR watermark: display plane 29, cursor 6 [ 367.091094] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=41, cursor=6, B: plane=2, cursor=2, SR: plane=29, cursor=6 [ 367.091431] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 367.091433] [drm:drm_mode_debug_printmodeline], Modeline 125:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 367.091435] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 367.109092] [drm:i9xx_update_plane], Writing base 07F4B000 00000000 0 0 3392 [ 367.125091] [drm:g4x_check_srwm], SR watermark: display plane 28, cursor 6 [ 367.125094] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=34, cursor=6, B: plane=2, cursor=2, SR: plane=28, cursor=6 [ 367.125098] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:125:848x480] [ 367.125101] [drm:g4x_check_srwm], SR watermark: display plane 28, cursor 6 [ 367.125104] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=34, cursor=6, B: plane=2, cursor=2, SR: plane=28, cursor=6 [ 367.143129] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 367.144620] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 367.147222] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 367.147224] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 367.148714] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 367.151317] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 367.152804] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 367.155405] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 367.156890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 367.159492] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 367.160976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 367.163578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 367.163580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 367.163581] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 367.163583] [drm:intel_modeset_check_state], [CRTC:3] [ 367.163584] [drm:intel_modeset_check_state], [CRTC:4] [ 372.193569] [drm:drm_mode_addfb], [FB:125] [ 372.193586] [drm:drm_mode_setcrtc], [CRTC:3] [ 372.193589] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 372.193591] [drm:intel_crtc_set_config], [CRTC:3] [FB:125] #connectors=1 (x y) (0 0) [ 372.193593] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 372.193594] [drm:drm_mode_debug_printmodeline], Modeline 125:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 372.193597] [drm:drm_mode_debug_printmodeline], Modeline 126:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 372.193599] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 372.193601] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 372.193603] [drm:drm_mode_debug_printmodeline], Modeline 126:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 372.193605] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 372.193607] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 372.219092] [drm:g4x_check_srwm], SR watermark: display plane 28, cursor 6 [ 372.219095] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=34, cursor=6, B: plane=2, cursor=2, SR: plane=28, cursor=6 [ 372.219432] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 372.219433] [drm:drm_mode_debug_printmodeline], Modeline 126:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 372.219435] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 372.235092] [drm:i9xx_update_plane], Writing base 080D9000 00000000 0 0 2560 [ 372.247091] [drm:g4x_check_srwm], SR watermark: display plane 26, cursor 6 [ 372.247093] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=59, cursor=6, B: plane=2, cursor=2, SR: plane=26, cursor=6 [ 372.247097] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:126:640x480] [ 372.247100] [drm:g4x_check_srwm], SR watermark: display plane 26, cursor 6 [ 372.247103] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=59, cursor=6, B: plane=2, cursor=2, SR: plane=26, cursor=6 [ 372.261127] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 372.262621] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 372.265222] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 372.265224] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 372.266713] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 372.269317] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 372.270805] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 372.273405] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 372.274890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 372.277492] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 372.278976] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 372.281578] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 372.281580] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 372.281581] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 372.281583] [drm:intel_modeset_check_state], [CRTC:3] [ 372.281584] [drm:intel_modeset_check_state], [CRTC:4] [ 375.616086] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 375.617578] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 375.672674] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 375.672676] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 377.311552] [drm:drm_mode_addfb], [FB:126] [ 377.311569] [drm:drm_mode_setcrtc], [CRTC:3] [ 377.311572] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 377.311574] [drm:intel_crtc_set_config], [CRTC:3] [FB:126] #connectors=1 (x y) (0 0) [ 377.311576] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 377.311577] [drm:drm_mode_debug_printmodeline], Modeline 126:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa [ 377.311580] [drm:drm_mode_debug_printmodeline], Modeline 127:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 377.311582] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 377.311584] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 377.311585] [drm:drm_mode_debug_printmodeline], Modeline 127:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 377.311588] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 377.311590] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 377.329092] [drm:g4x_check_srwm], SR watermark: display plane 26, cursor 6 [ 377.329095] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=59, cursor=6, B: plane=2, cursor=2, SR: plane=26, cursor=6 [ 377.329432] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 377.329433] [drm:drm_mode_debug_printmodeline], Modeline 127:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 377.329435] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 377.343092] [drm:i9xx_update_plane], Writing base 08205000 00000000 0 0 2560 [ 377.357091] [drm:g4x_check_srwm], SR watermark: display plane 26, cursor 6 [ 377.357094] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=59, cursor=6, B: plane=2, cursor=2, SR: plane=26, cursor=6 [ 377.357098] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:127:640x480] [ 377.357101] [drm:g4x_check_srwm], SR watermark: display plane 26, cursor 6 [ 377.357103] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=59, cursor=6, B: plane=2, cursor=2, SR: plane=26, cursor=6 [ 377.371127] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 377.372622] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 377.375224] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 377.375225] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 377.376713] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 377.379319] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 377.380805] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 377.383409] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 377.384896] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 377.387499] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 377.388988] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 377.391591] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 377.391592] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 377.391594] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 377.391595] [drm:intel_modeset_check_state], [CRTC:3] [ 377.391597] [drm:intel_modeset_check_state], [CRTC:4] [ 382.421668] [drm:drm_mode_addfb], [FB:127] [ 382.421685] [drm:drm_mode_setcrtc], [CRTC:3] [ 382.421688] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 382.421690] [drm:intel_crtc_set_config], [CRTC:3] [FB:127] #connectors=1 (x y) (0 0) [ 382.421692] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 382.421693] [drm:drm_mode_debug_printmodeline], Modeline 127:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 382.421696] [drm:drm_mode_debug_printmodeline], Modeline 128:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 382.421698] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 382.421700] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 382.421701] [drm:drm_mode_debug_printmodeline], Modeline 128:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 382.421704] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 382.421706] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 382.437092] [drm:g4x_check_srwm], SR watermark: display plane 26, cursor 6 [ 382.437095] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=59, cursor=6, B: plane=2, cursor=2, SR: plane=26, cursor=6 [ 382.437448] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 382.437449] [drm:drm_mode_debug_printmodeline], Modeline 128:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 382.437451] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 382.455091] [drm:i9xx_update_plane], Writing base 08331000 00000000 0 0 2560 [ 382.471092] [drm:g4x_check_srwm], SR watermark: display plane 21, cursor 6 [ 382.471095] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=57, cursor=6, B: plane=2, cursor=2, SR: plane=21, cursor=6 [ 382.471099] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:128:640x480] [ 382.471102] [drm:g4x_check_srwm], SR watermark: display plane 21, cursor 6 [ 382.471104] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=57, cursor=6, B: plane=2, cursor=2, SR: plane=21, cursor=6 [ 382.489129] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 382.490621] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 382.493222] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 382.493223] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 382.494708] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 382.497308] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 382.498793] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 382.501394] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 382.502880] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 382.505481] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 382.506966] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 382.509567] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 382.509569] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 382.509570] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 382.509572] [drm:intel_modeset_check_state], [CRTC:3] [ 382.509573] [drm:intel_modeset_check_state], [CRTC:4] [ 385.696078] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 385.697572] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 385.752680] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 385.752682] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 387.533455] [drm:drm_mode_addfb], [FB:128] [ 387.533476] [drm:drm_mode_setcrtc], [CRTC:3] [ 387.533479] [drm:drm_mode_setcrtc], [CONNECTOR:5:VGA-1] [ 387.533481] [drm:intel_crtc_set_config], [CRTC:3] [FB:128] #connectors=1 (x y) (0 0) [ 387.533484] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 387.533485] [drm:drm_mode_debug_printmodeline], Modeline 128:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 387.533488] [drm:drm_mode_debug_printmodeline], Modeline 129:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 387.533491] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 387.533493] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 387.533494] [drm:drm_mode_debug_printmodeline], Modeline 129:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 387.533497] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 387.533499] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 387.555091] [drm:g4x_check_srwm], SR watermark: display plane 21, cursor 6 [ 387.555094] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=57, cursor=6, B: plane=2, cursor=2, SR: plane=21, cursor=6 [ 387.555448] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 387.555449] [drm:drm_mode_debug_printmodeline], Modeline 129:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 387.555451] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 387.571091] [drm:i9xx_update_plane], Writing base 0845D000 00000000 0 0 2880 [ 387.585089] [drm:g4x_check_srwm], SR watermark: display plane 24, cursor 6 [ 387.585092] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=48, cursor=6, B: plane=2, cursor=2, SR: plane=24, cursor=6 [ 387.585096] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:129:720x400] [ 387.585099] [drm:g4x_check_srwm], SR watermark: display plane 24, cursor 6 [ 387.585102] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=48, cursor=6, B: plane=2, cursor=2, SR: plane=24, cursor=6 [ 387.599126] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 387.600621] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 387.603222] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 387.603224] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 387.604713] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 387.607317] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 387.608804] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 387.611405] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 387.612890] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 387.615495] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 387.616984] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 387.619582] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 387.619584] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 387.619586] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 387.619587] [drm:intel_modeset_check_state], [CRTC:3] [ 387.619589] [drm:intel_modeset_check_state], [CRTC:4] [ 392.619676] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] [ 392.619680] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [NOCRTC] [ 392.619682] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 392.619684] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 392.619687] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 392.637091] [drm:g4x_check_srwm], SR watermark: display plane 24, cursor 6 [ 392.637094] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=48, cursor=6, B: plane=2, cursor=2, SR: plane=24, cursor=6 [ 392.637099] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 392.638592] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 392.641193] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 392.642678] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 392.645276] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 392.646762] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 392.649362] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 392.650848] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 392.653452] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 392.654940] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 392.657540] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 392.657541] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 392.657543] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 392.657544] [drm:intel_modeset_check_state], [CRTC:3] [ 392.657545] [drm:intel_modeset_check_state], [CRTC:4] [ 392.657549] [drm:drm_mode_setcrtc], [CRTC:3] [ 392.657550] [drm:drm_mode_setcrtc], Count connectors is 1 but no mode or fb set [ 392.657558] [drm:drm_mode_getconnector], [CONNECTOR:10:?] [ 392.657560] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] [ 392.657562] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 392.659053] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 392.714676] [drm:intel_sdvo_detect], SDVO response 0 0 [8] [ 392.714678] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected [ 392.714681] [drm:drm_mode_getconnector], [CONNECTOR:10:?] [ 392.714683] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] [ 392.714684] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 392.716176] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 392.771695] [drm:intel_sdvo_detect], SDVO response 0 0 [8] [ 392.771697] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected [ 392.771701] [drm:drm_mode_getconnector], [CONNECTOR:27:?] [ 392.771703] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:27:SVIDEO-2] [ 392.771705] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 392.773194] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 392.828692] [drm:intel_sdvo_detect], SDVO response 0 0 [4] [ 392.828694] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:27:SVIDEO-2] disconnected [ 392.828696] [drm:drm_mode_getconnector], [CONNECTOR:27:?] [ 392.828698] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:27:SVIDEO-2] [ 392.828699] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 392.830187] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 392.885691] [drm:intel_sdvo_detect], SDVO response 0 0 [4] [ 392.885693] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:27:SVIDEO-2] disconnected [ 392.885696] [drm:drm_mode_getconnector], [CONNECTOR:44:?] [ 392.885698] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:44:SVIDEO-3] [ 392.885699] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 392.887187] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 392.942691] [drm:intel_sdvo_detect], SDVO response 0 0 [10] [ 392.942693] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:44:SVIDEO-3] disconnected [ 392.942695] [drm:drm_mode_getconnector], [CONNECTOR:44:?] [ 392.942697] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:44:SVIDEO-3] [ 392.942698] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 392.944187] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 392.999695] [drm:intel_sdvo_detect], SDVO response 0 0 [10] [ 392.999697] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:44:SVIDEO-3] disconnected [ 392.999701] [drm:drm_mode_getconnector], [CONNECTOR:61:?] [ 392.999702] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:61:VGA-2] [ 392.999704] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 393.001197] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 393.056692] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 393.056694] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:61:VGA-2] disconnected [ 393.056697] [drm:drm_mode_getconnector], [CONNECTOR:61:?] [ 393.056698] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:61:VGA-2] [ 393.056700] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 393.058188] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 393.113691] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 393.113693] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:61:VGA-2] disconnected [ 393.153844] [drm:intel_crtc_set_config], [CRTC:3] [FB:96] #connectors=1 (x y) (0 0) [ 393.153848] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 393.153849] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 393.153851] [drm:drm_mode_debug_printmodeline], Modeline 129:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 393.153853] [drm:drm_mode_debug_printmodeline], Modeline 95:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [ 393.153856] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 393.153857] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 393.153859] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 393.153860] [drm:intel_crtc_set_config], attempting to set mode from userspace [ 393.153861] [drm:drm_mode_debug_printmodeline], Modeline 95:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [ 393.153864] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 393.153867] [drm:intel_modeset_adjusted_mode], [CRTC:3] [ 393.154193] [drm:i9xx_crtc_mode_set], Mode for pipe A: [ 393.154194] [drm:drm_mode_debug_printmodeline], Modeline 95:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9 [ 393.154196] [drm:i9xx_crtc_mode_set], disabling CxSR downclocking [ 393.172093] [drm:i9xx_update_plane], Writing base 00046000 00000000 0 0 7680 [ 393.172098] [drm:g4x_check_srwm], SR watermark: display plane 118, cursor 6 [ 393.172100] [drm:g4x_check_srwm], display watermark is too large(118/63), disabling [ 393.172103] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=51, cursor=6, B: plane=2, cursor=2, SR: plane=118, cursor=6 [ 393.172107] [drm:intel_crtc_mode_set], [ENCODER:6:DAC-6] set [MODE:95:1920x1200] [ 393.172110] [drm:g4x_check_srwm], SR watermark: display plane 118, cursor 6 [ 393.172113] [drm:g4x_check_srwm], display watermark is too large(118/63), disabling [ 393.172115] [drm:g4x_update_wm], Setting FIFO watermarks - A: plane=51, cursor=6, B: plane=2, cursor=2, SR: plane=118, cursor=6 [ 393.188129] [drm:intel_sdvo_debug_write], SDVOB: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 393.189621] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 00 00 [ 393.192226] [drm:intel_connector_check_state], [CONNECTOR:5:VGA-1] [ 393.192227] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 393.193714] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 393.196323] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 393.197809] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 393.200410] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 393.201897] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 393.204519] [drm:intel_sdvo_debug_write], SDVOC: W: 04 (SDVO_CMD_GET_ACTIVE_OUTPUTS) [ 393.206007] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 393.208604] [drm:intel_modeset_check_state], [ENCODER:6:DAC-6] [ 393.208606] [drm:intel_modeset_check_state], [ENCODER:7:LVDS-7] [ 393.208608] [drm:intel_modeset_check_state], [ENCODER:9:DAC-9] [ 393.208609] [drm:intel_modeset_check_state], [CRTC:3] [ 393.208610] [drm:intel_modeset_check_state], [CRTC:4] [ 393.208612] [drm:intel_crtc_set_config], [CRTC:4] [NOFB] [ 393.208614] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3] [ 395.776077] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 395.777574] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 395.832684] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 395.832686] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 405.856086] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 405.857578] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 405.912682] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 405.912684] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 415.936086] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 415.937578] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 415.992681] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 415.992683] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 426.016076] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 426.017570] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 426.072681] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 426.072682] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 436.096084] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 436.097578] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 436.152680] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 436.152682] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2 [ 446.176084] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 446.177578] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 446.232676] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 446.232678] [drm:output_poll_execute], [CONNECTOR:61:VGA-2] status updated from 2 to 2