--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -541,10 +541,13 @@
 		}
 	}
 	/* compute number of htile */
-	nbx = nbx >> 3;
-	nby = nby >> 3;
+	/* nbx = nbx >> 3; */
+	/* nby = nby >> 3; */
+	nbx = nbx / 8;
+	nby = nby / 8;
 	/* size must be aligned on npipes * 2K boundary */
-	size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
+	/* size = roundup(nbx * nby * 4, track->npipes * (2 << 10)); */
+	size = nbx * nby * 4;
 	size += track->htile_offset;
 
 	if (size > radeon_bo_size(track->htile_bo)) {
@@ -1802,7 +1805,7 @@
 		/* 8x8 only */
 		track->htile_surface = radeon_get_ib_value(p, idx);
 		/* force 8x8 htile width and height */
-		ib[idx] |= 3;
+		/* ib[idx] |= 3; */
 		track->db_dirty = true;
 		break;
 	case CB_IMMED0_BASE: