From 2d19dd7dd7aa67d336b71451ac2a3295b139beae Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 6 Feb 2013 15:03:17 -0500 Subject: [PATCH] r600g: make sure async blit is done 8 * pitch at a time The blit must be aligned on 8 horizontal block. Signed-off-by: Jerome Glisse --- src/gallium/drivers/r600/r600_state.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index bf194f5..54098de 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -3042,14 +3042,16 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx, return FALSE; } - size = (copy_height * pitch) >> 2; - ncopy = (size / 0x0000ffff) + !!(size % 0x0000ffff); + /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number + * line in the blit. Compute max 8 line we can copy in the size limit + */ + copy_height = align(copy_height, 8); + cheight = ((0x0000ffff << 2) / pitch) & 0xfffffff8; + ncopy = (copy_height / cheight) + !!(copy_height % cheight); r600_need_dma_space(rctx, ncopy * 7); + for (i = 0; i < ncopy; i++) { - cheight = copy_height; - if (((cheight * pitch) >> 2) > 0x0000ffff) { - cheight = (0x0000ffff << 2) / pitch; - } + cheight = cheight > copy_height ? copy_height : cheight; size = (cheight * pitch) >> 2; /* emit reloc before writting cs so that cs is always in consistent state */ r600_context_bo_reloc(rctx, &rctx->rings.dma, &rsrc->resource, RADEON_USAGE_READ); -- 1.7.11.7