#0 0x00007ffff6f08ea8 in ?? () from /lib64/libc.so.6 #1 0x00007ffff186d6e9 in llvm::PassRegistry::removeRegistrationListener(llvm::PassRegistrationListener*) () from /usr/lib64/gbm/gbm_gallium_drm.so #2 0x00007ffff2f1c09c in ?? () from /usr/lib64/egl/egl_gallium.so #3 0x00007ffff6e0aae9 in ?? () from /lib64/libc.so.6 #4 0x00007ffff6e0ab35 in exit () from /lib64/libc.so.6 #5 0x0000000000401ccc in _eglutDefaultKeyboard (key=) at eglut.c:307 #6 0x00000000004024cf in _eglutNativeEventLoop () at eglut_screen.c:165 #7 0x0000000000401bfb in eglutMainLoop () at eglut.c:274 #8 0x0000000000401571 in main (argc=1, argv=0x7fffffffdff8) at egltri.c:138 EGL_VERSION = 1.4 (Gallium) VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 1) %0 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %1 = getelementptr <4 x i32> addrspace(2)* %0, i32 0 %2 = load <4 x i32> addrspace(2)* %1 %3 = call i32 @llvm.SI.vs.load.buffer.index() %4 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %2, i32 0, i32 %3) %5 = extractelement <4 x float> %4, i32 0 %6 = extractelement <4 x float> %4, i32 1 %7 = extractelement <4 x float> %4, i32 2 %8 = extractelement <4 x float> %4, i32 3 %9 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %10 = getelementptr <4 x i32> addrspace(2)* %9, i32 1 %11 = load <4 x i32> addrspace(2)* %10 %12 = call i32 @llvm.SI.vs.load.buffer.index() %13 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %11, i32 0, i32 %12) %14 = extractelement <4 x float> %13, i32 0 %15 = extractelement <4 x float> %13, i32 1 %16 = extractelement <4 x float> %13, i32 2 %17 = extractelement <4 x float> %13, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %14, float %15, float %16, float %17) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %5, float %6, float %7, float %8) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare i32 @llvm.SI.vs.load.buffer.index() #0 declare <4 x float> @llvm.SI.vs.load.input(<4 x i32>, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readnone } ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 1) %0 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %1 = getelementptr <4 x i32> addrspace(2)* %0, i32 0 %2 = load <4 x i32> addrspace(2)* %1 %3 = call i32 @llvm.SI.vs.load.buffer.index() %4 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %2, i32 0, i32 %3) %5 = extractelement <4 x float> %4, i32 0 %6 = extractelement <4 x float> %4, i32 1 %7 = extractelement <4 x float> %4, i32 2 %8 = extractelement <4 x float> %4, i32 3 %9 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %10 = getelementptr <4 x i32> addrspace(2)* %9, i32 1 %11 = load <4 x i32> addrspace(2)* %10 %12 = call i32 @llvm.SI.vs.load.buffer.index() %13 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %11, i32 0, i32 %12) %14 = extractelement <4 x float> %13, i32 0 %15 = extractelement <4 x float> %13, i32 1 %16 = extractelement <4 x float> %13, i32 2 %17 = extractelement <4 x float> %13, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %14, float %15, float %16, float %17) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %5, float %6, float %7, float %8) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare i32 @llvm.SI.vs.load.buffer.index() #0 declare <4 x float> @llvm.SI.vs.load.input(<4 x i32>, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readnone } SI CODE: 00000008 00000009 00000000 c0800700 bf8c007f e00c2000 80000100 c0800704 bf8c0000 e00c2000 80000500 bf8c0700 f800020f 08070605 f80008cf 04030201 bf810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.constant(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.constant(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.constant(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.constant(i32 3, i32 0, i32 %0) call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.constant(i32, i32, i32) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { readonly } ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.constant(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.constant(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.constant(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.constant(i32 3, i32 0, i32 %0) call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.constant(i32, i32, i32) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { readonly } SI CODE: 00000007 00000001 00000001 befe0a7e befc0306 c8020302 c8020202 c8020102 c8020002 7e000280 f8001800 00000000 bf810000 Found 16 modes: 0: 1920 x 1080 1: 1920 x 1080 2: 1920 x 1080 3: 1920 x 1080 4: 1680 x 1050 5: 1680 x 945 6: 1400 x 1050 7: 1600 x 900 8: 1280 x 1024 9: 1440 x 900 10: 1280 x 960 11: 1366 x 768 12: 1360 x 768 13: 1280 x 800 14: 1280 x 768 15: 1280 x 720 Will use screen size: 1920 x 1080 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV_SAT OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.persp.center(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.persp.center(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.persp.center(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.persp.center(i32 3, i32 0, i32 %0) %5 = call float @llvm.AMDIL.clamp.(float %1, float 0.000000e+00, float 1.000000e+00) %6 = call float @llvm.AMDIL.clamp.(float %2, float 0.000000e+00, float 1.000000e+00) %7 = call float @llvm.AMDIL.clamp.(float %3, float 0.000000e+00, float 1.000000e+00) %8 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %5, float %6, float %7, float %8) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.persp.center(i32, i32, i32) #0 declare float @llvm.AMDIL.clamp.(float, float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readonly } attributes #1 = { readnone } ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.persp.center(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.persp.center(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.persp.center(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.persp.center(i32 3, i32 0, i32 %0) %5 = call float @llvm.AMDIL.clamp.(float %1, float 0.000000e+00, float 1.000000e+00) %6 = call float @llvm.AMDIL.clamp.(float %2, float 0.000000e+00, float 1.000000e+00) %7 = call float @llvm.AMDIL.clamp.(float %3, float 0.000000e+00, float 1.000000e+00) %8 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %5, float %6, float %7, float %8) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.persp.center(i32, i32, i32) #0 declare float @llvm.AMDIL.clamp.(float, float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readonly } attributes #1 = { readnone } SI CODE: 00000007 00000005 00000002 befe0a7e befc0306 c8080300 c8090301 d2060802 02010102 c80c0200 c80d0201 d2060803 02010103 c8100100 c8110101 d2060804 02010104 c8000000 c8010001 d2060800 02010100 f800180f 02030400 bf810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV_SAT OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 1) %0 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %1 = getelementptr <4 x i32> addrspace(2)* %0, i32 0 %2 = load <4 x i32> addrspace(2)* %1 %3 = call i32 @llvm.SI.vs.load.buffer.index() %4 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %2, i32 0, i32 %3) %5 = extractelement <4 x float> %4, i32 0 %6 = extractelement <4 x float> %4, i32 1 %7 = extractelement <4 x float> %4, i32 2 %8 = extractelement <4 x float> %4, i32 3 %9 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %10 = getelementptr <4 x i32> addrspace(2)* %9, i32 1 %11 = load <4 x i32> addrspace(2)* %10 %12 = call i32 @llvm.SI.vs.load.buffer.index() %13 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %11, i32 0, i32 %12) %14 = extractelement <4 x float> %13, i32 0 %15 = extractelement <4 x float> %13, i32 1 %16 = extractelement <4 x float> %13, i32 2 %17 = extractelement <4 x float> %13, i32 3 %18 = load float addrspace(2)* addrspace(8)* null %19 = getelementptr float addrspace(2)* %18, i32 0 %20 = load float addrspace(2)* %19 %21 = fmul float %5, %20 %22 = load float addrspace(2)* addrspace(8)* null %23 = getelementptr float addrspace(2)* %22, i32 1 %24 = load float addrspace(2)* %23 %25 = fmul float %5, %24 %26 = load float addrspace(2)* addrspace(8)* null %27 = getelementptr float addrspace(2)* %26, i32 2 %28 = load float addrspace(2)* %27 %29 = fmul float %5, %28 %30 = load float addrspace(2)* addrspace(8)* null %31 = getelementptr float addrspace(2)* %30, i32 3 %32 = load float addrspace(2)* %31 %33 = fmul float %5, %32 %34 = load float addrspace(2)* addrspace(8)* null %35 = getelementptr float addrspace(2)* %34, i32 4 %36 = load float addrspace(2)* %35 %37 = fmul float %6, %36 %38 = fadd float %37, %21 %39 = load float addrspace(2)* addrspace(8)* null %40 = getelementptr float addrspace(2)* %39, i32 5 %41 = load float addrspace(2)* %40 %42 = fmul float %6, %41 %43 = fadd float %42, %25 %44 = load float addrspace(2)* addrspace(8)* null %45 = getelementptr float addrspace(2)* %44, i32 6 %46 = load float addrspace(2)* %45 %47 = fmul float %6, %46 %48 = fadd float %47, %29 %49 = load float addrspace(2)* addrspace(8)* null %50 = getelementptr float addrspace(2)* %49, i32 7 %51 = load float addrspace(2)* %50 %52 = fmul float %6, %51 %53 = fadd float %52, %33 %54 = load float addrspace(2)* addrspace(8)* null %55 = getelementptr float addrspace(2)* %54, i32 8 %56 = load float addrspace(2)* %55 %57 = fmul float %7, %56 %58 = fadd float %57, %38 %59 = load float addrspace(2)* addrspace(8)* null %60 = getelementptr float addrspace(2)* %59, i32 9 %61 = load float addrspace(2)* %60 %62 = fmul float %7, %61 %63 = fadd float %62, %43 %64 = load float addrspace(2)* addrspace(8)* null %65 = getelementptr float addrspace(2)* %64, i32 10 %66 = load float addrspace(2)* %65 %67 = fmul float %7, %66 %68 = fadd float %67, %48 %69 = load float addrspace(2)* addrspace(8)* null %70 = getelementptr float addrspace(2)* %69, i32 11 %71 = load float addrspace(2)* %70 %72 = fmul float %7, %71 %73 = fadd float %72, %53 %74 = load float addrspace(2)* addrspace(8)* null %75 = getelementptr float addrspace(2)* %74, i32 12 %76 = load float addrspace(2)* %75 %77 = fmul float %8, %76 %78 = fadd float %77, %58 %79 = load float addrspace(2)* addrspace(8)* null %80 = getelementptr float addrspace(2)* %79, i32 13 %81 = load float addrspace(2)* %80 %82 = fmul float %8, %81 %83 = fadd float %82, %63 %84 = load float addrspace(2)* addrspace(8)* null %85 = getelementptr float addrspace(2)* %84, i32 14 %86 = load float addrspace(2)* %85 %87 = fmul float %8, %86 %88 = fadd float %87, %68 %89 = load float addrspace(2)* addrspace(8)* null %90 = getelementptr float addrspace(2)* %89, i32 15 %91 = load float addrspace(2)* %90 %92 = fmul float %8, %91 %93 = fadd float %92, %73 %94 = call float @llvm.AMDIL.clamp.(float %14, float 0.000000e+00, float 1.000000e+00) %95 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00) %96 = call float @llvm.AMDIL.clamp.(float %16, float 0.000000e+00, float 1.000000e+00) %97 = call float @llvm.AMDIL.clamp.(float %17, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %94, float %95, float %96, float %97) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %78, float %83, float %88, float %93) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare i32 @llvm.SI.vs.load.buffer.index() #0 declare <4 x float> @llvm.SI.vs.load.input(<4 x i32>, i32, i32) declare float @llvm.AMDIL.clamp.(float, float, float) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readnone } ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 1) %0 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %1 = getelementptr <4 x i32> addrspace(2)* %0, i32 0 %2 = load <4 x i32> addrspace(2)* %1 %3 = call i32 @llvm.SI.vs.load.buffer.index() %4 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %2, i32 0, i32 %3) %5 = extractelement <4 x float> %4, i32 0 %6 = extractelement <4 x float> %4, i32 1 %7 = extractelement <4 x float> %4, i32 2 %8 = extractelement <4 x float> %4, i32 3 %9 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %10 = getelementptr <4 x i32> addrspace(2)* %9, i32 1 %11 = load <4 x i32> addrspace(2)* %10 %12 = call i32 @llvm.SI.vs.load.buffer.index() %13 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %11, i32 0, i32 %12) %14 = extractelement <4 x float> %13, i32 0 %15 = extractelement <4 x float> %13, i32 1 %16 = extractelement <4 x float> %13, i32 2 %17 = extractelement <4 x float> %13, i32 3 %18 = load float addrspace(2)* addrspace(8)* null %19 = getelementptr float addrspace(2)* %18, i32 0 %20 = load float addrspace(2)* %19 %21 = fmul float %5, %20 %22 = load float addrspace(2)* addrspace(8)* null %23 = getelementptr float addrspace(2)* %22, i32 1 %24 = load float addrspace(2)* %23 %25 = fmul float %5, %24 %26 = load float addrspace(2)* addrspace(8)* null %27 = getelementptr float addrspace(2)* %26, i32 2 %28 = load float addrspace(2)* %27 %29 = fmul float %5, %28 %30 = load float addrspace(2)* addrspace(8)* null %31 = getelementptr float addrspace(2)* %30, i32 3 %32 = load float addrspace(2)* %31 %33 = fmul float %5, %32 %34 = load float addrspace(2)* addrspace(8)* null %35 = getelementptr float addrspace(2)* %34, i32 4 %36 = load float addrspace(2)* %35 %37 = fmul float %6, %36 %38 = fadd float %37, %21 %39 = load float addrspace(2)* addrspace(8)* null %40 = getelementptr float addrspace(2)* %39, i32 5 %41 = load float addrspace(2)* %40 %42 = fmul float %6, %41 %43 = fadd float %42, %25 %44 = load float addrspace(2)* addrspace(8)* null %45 = getelementptr float addrspace(2)* %44, i32 6 %46 = load float addrspace(2)* %45 %47 = fmul float %6, %46 %48 = fadd float %47, %29 %49 = load float addrspace(2)* addrspace(8)* null %50 = getelementptr float addrspace(2)* %49, i32 7 %51 = load float addrspace(2)* %50 %52 = fmul float %6, %51 %53 = fadd float %52, %33 %54 = load float addrspace(2)* addrspace(8)* null %55 = getelementptr float addrspace(2)* %54, i32 8 %56 = load float addrspace(2)* %55 %57 = fmul float %7, %56 %58 = fadd float %57, %38 %59 = load float addrspace(2)* addrspace(8)* null %60 = getelementptr float addrspace(2)* %59, i32 9 %61 = load float addrspace(2)* %60 %62 = fmul float %7, %61 %63 = fadd float %62, %43 %64 = load float addrspace(2)* addrspace(8)* null %65 = getelementptr float addrspace(2)* %64, i32 10 %66 = load float addrspace(2)* %65 %67 = fmul float %7, %66 %68 = fadd float %67, %48 %69 = load float addrspace(2)* addrspace(8)* null %70 = getelementptr float addrspace(2)* %69, i32 11 %71 = load float addrspace(2)* %70 %72 = fmul float %7, %71 %73 = fadd float %72, %53 %74 = load float addrspace(2)* addrspace(8)* null %75 = getelementptr float addrspace(2)* %74, i32 12 %76 = load float addrspace(2)* %75 %77 = fmul float %8, %76 %78 = fadd float %77, %58 %79 = load float addrspace(2)* addrspace(8)* null %80 = getelementptr float addrspace(2)* %79, i32 13 %81 = load float addrspace(2)* %80 %82 = fmul float %8, %81 %83 = fadd float %82, %63 %84 = load float addrspace(2)* addrspace(8)* null %85 = getelementptr float addrspace(2)* %84, i32 14 %86 = load float addrspace(2)* %85 %87 = fmul float %8, %86 %88 = fadd float %87, %68 %89 = load float addrspace(2)* addrspace(8)* null %90 = getelementptr float addrspace(2)* %89, i32 15 %91 = load float addrspace(2)* %90 %92 = fmul float %8, %91 %93 = fadd float %92, %73 %94 = call float @llvm.AMDIL.clamp.(float %14, float 0.000000e+00, float 1.000000e+00) %95 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00) %96 = call float @llvm.AMDIL.clamp.(float %16, float 0.000000e+00, float 1.000000e+00) %97 = call float @llvm.AMDIL.clamp.(float %17, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %94, float %95, float %96, float %97) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %78, float %83, float %88, float %93) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare i32 @llvm.SI.vs.load.buffer.index() #0 declare <4 x float> @llvm.SI.vs.load.input(<4 x i32>, i32, i32) declare float @llvm.AMDIL.clamp.(float, float, float) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readnone } SI CODE: 00000011 0000000b 00000000 c0840700 bf8c007f e00c2000 80020100 c0820704 bf8c0000 e00c2000 80010700 bf8c0700 d2060800 0201010a d2060805 02010109 d2060806 02010108 d2060807 02010107 c001010c c0018108 c0020104 c0028100 c003010d c0038109 c0040105 c0048101 c005010e c005810a c0060106 c0068102 c007010f c007810b c0080107 c0000103 f800020f 00050607 bf8c000f 7e000200 10000101 7e0a0210 d2820000 04020b02 7e0a020f d2820000 04020b03 7e0a020e d2820000 04020b04 7e0a020d 100a0b01 7e0c020c d2820005 04160d02 7e0c020b d2820005 04160d03 7e0c020a d2820005 04160d04 7e0c0209 100c0d01 7e0e0208 d2820006 041a0f02 7e0e0207 d2820006 041a0f03 7e0e0206 d2820006 041a0f04 7e0e0205 100e0f01 7e100204 d2820007 041e1102 7e100203 d2820007 041e1103 7e100202 d2820001 041e1104 f80008cf 00050601 bf810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.linear.center(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.linear.center(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.linear.center(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.linear.center(i32 3, i32 0, i32 %0) %5 = call i32 @llvm.SI.packf16(float %1, float %2) %6 = bitcast i32 %5 to float %7 = call i32 @llvm.SI.packf16(float %3, float %4) %8 = bitcast i32 %7 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %6, float %8, float %6, float %8) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.linear.center(i32, i32, i32) #0 declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readonly } attributes #1 = { readnone } ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.linear.center(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.linear.center(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.linear.center(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.linear.center(i32 3, i32 0, i32 %0) %5 = call i32 @llvm.SI.packf16(float %1, float %2) %6 = bitcast i32 %5 to float %7 = call i32 @llvm.SI.packf16(float %3, float %4) %8 = bitcast i32 %7 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %6, float %8, float %6, float %8) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.linear.center(i32, i32, i32) #0 declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readonly } attributes #1 = { readnone } SI CODE: 00000007 00000004 00000020 befe0a7e befc0306 c8080300 c8090301 c80c0200 c80d0201 5e040503 c80c0100 c80d0101 c8000000 c8010001 5e000700 f8001c0f 02000200 bf810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.linear.center(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.linear.center(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.linear.center(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.linear.center(i32 3, i32 0, i32 %0) %5 = call i32 @llvm.SI.packf16(float %1, float %2) %6 = bitcast i32 %5 to float %7 = call i32 @llvm.SI.packf16(float %3, float %4) %8 = bitcast i32 %7 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %6, float %8, float %6, float %8) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.linear.center(i32, i32, i32) #0 declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readonly } attributes #1 = { readnone } ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.linear.center(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.linear.center(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.linear.center(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.linear.center(i32 3, i32 0, i32 %0) %5 = call i32 @llvm.SI.packf16(float %1, float %2) %6 = bitcast i32 %5 to float %7 = call i32 @llvm.SI.packf16(float %3, float %4) %8 = bitcast i32 %7 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %6, float %8, float %6, float %8) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.linear.center(i32, i32, i32) #0 declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readonly } attributes #1 = { readnone } SI CODE: 00000007 00000004 00000020 befe0a7e befc0306 c8080300 c8090301 c80c0200 c80d0201 5e040503 c80c0100 c80d0101 c8000000 c8010001 5e000700 f8001c0f 02000200 bf810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV_SAT OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 1) %0 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %1 = getelementptr <4 x i32> addrspace(2)* %0, i32 0 %2 = load <4 x i32> addrspace(2)* %1 %3 = call i32 @llvm.SI.vs.load.buffer.index() %4 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %2, i32 0, i32 %3) %5 = extractelement <4 x float> %4, i32 0 %6 = extractelement <4 x float> %4, i32 1 %7 = extractelement <4 x float> %4, i32 2 %8 = extractelement <4 x float> %4, i32 3 %9 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %10 = getelementptr <4 x i32> addrspace(2)* %9, i32 1 %11 = load <4 x i32> addrspace(2)* %10 %12 = call i32 @llvm.SI.vs.load.buffer.index() %13 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %11, i32 0, i32 %12) %14 = extractelement <4 x float> %13, i32 0 %15 = extractelement <4 x float> %13, i32 1 %16 = extractelement <4 x float> %13, i32 2 %17 = extractelement <4 x float> %13, i32 3 %18 = load float addrspace(2)* addrspace(8)* null %19 = getelementptr float addrspace(2)* %18, i32 0 %20 = load float addrspace(2)* %19 %21 = fmul float %5, %20 %22 = load float addrspace(2)* addrspace(8)* null %23 = getelementptr float addrspace(2)* %22, i32 1 %24 = load float addrspace(2)* %23 %25 = fmul float %5, %24 %26 = load float addrspace(2)* addrspace(8)* null %27 = getelementptr float addrspace(2)* %26, i32 2 %28 = load float addrspace(2)* %27 %29 = fmul float %5, %28 %30 = load float addrspace(2)* addrspace(8)* null %31 = getelementptr float addrspace(2)* %30, i32 3 %32 = load float addrspace(2)* %31 %33 = fmul float %5, %32 %34 = load float addrspace(2)* addrspace(8)* null %35 = getelementptr float addrspace(2)* %34, i32 4 %36 = load float addrspace(2)* %35 %37 = fmul float %6, %36 %38 = fadd float %37, %21 %39 = load float addrspace(2)* addrspace(8)* null %40 = getelementptr float addrspace(2)* %39, i32 5 %41 = load float addrspace(2)* %40 %42 = fmul float %6, %41 %43 = fadd float %42, %25 %44 = load float addrspace(2)* addrspace(8)* null %45 = getelementptr float addrspace(2)* %44, i32 6 %46 = load float addrspace(2)* %45 %47 = fmul float %6, %46 %48 = fadd float %47, %29 %49 = load float addrspace(2)* addrspace(8)* null %50 = getelementptr float addrspace(2)* %49, i32 7 %51 = load float addrspace(2)* %50 %52 = fmul float %6, %51 %53 = fadd float %52, %33 %54 = load float addrspace(2)* addrspace(8)* null %55 = getelementptr float addrspace(2)* %54, i32 8 %56 = load float addrspace(2)* %55 %57 = fmul float %7, %56 %58 = fadd float %57, %38 %59 = load float addrspace(2)* addrspace(8)* null %60 = getelementptr float addrspace(2)* %59, i32 9 %61 = load float addrspace(2)* %60 %62 = fmul float %7, %61 %63 = fadd float %62, %43 %64 = load float addrspace(2)* addrspace(8)* null %65 = getelementptr float addrspace(2)* %64, i32 10 %66 = load float addrspace(2)* %65 %67 = fmul float %7, %66 %68 = fadd float %67, %48 %69 = load float addrspace(2)* addrspace(8)* null %70 = getelementptr float addrspace(2)* %69, i32 11 %71 = load float addrspace(2)* %70 %72 = fmul float %7, %71 %73 = fadd float %72, %53 %74 = load float addrspace(2)* addrspace(8)* null %75 = getelementptr float addrspace(2)* %74, i32 12 %76 = load float addrspace(2)* %75 %77 = fmul float %8, %76 %78 = fadd float %77, %58 %79 = load float addrspace(2)* addrspace(8)* null %80 = getelementptr float addrspace(2)* %79, i32 13 %81 = load float addrspace(2)* %80 %82 = fmul float %8, %81 %83 = fadd float %82, %63 %84 = load float addrspace(2)* addrspace(8)* null %85 = getelementptr float addrspace(2)* %84, i32 14 %86 = load float addrspace(2)* %85 %87 = fmul float %8, %86 %88 = fadd float %87, %68 %89 = load float addrspace(2)* addrspace(8)* null %90 = getelementptr float addrspace(2)* %89, i32 15 %91 = load float addrspace(2)* %90 %92 = fmul float %8, %91 %93 = fadd float %92, %73 %94 = call float @llvm.AMDIL.clamp.(float %14, float 0.000000e+00, float 1.000000e+00) %95 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00) %96 = call float @llvm.AMDIL.clamp.(float %16, float 0.000000e+00, float 1.000000e+00) %97 = call float @llvm.AMDIL.clamp.(float %17, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %94, float %95, float %96, float %97) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %78, float %83, float %88, float %93) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare i32 @llvm.SI.vs.load.buffer.index() #0 declare <4 x float> @llvm.SI.vs.load.input(<4 x i32>, i32, i32) declare float @llvm.AMDIL.clamp.(float, float, float) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readnone } ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 1) %0 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %1 = getelementptr <4 x i32> addrspace(2)* %0, i32 0 %2 = load <4 x i32> addrspace(2)* %1 %3 = call i32 @llvm.SI.vs.load.buffer.index() %4 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %2, i32 0, i32 %3) %5 = extractelement <4 x float> %4, i32 0 %6 = extractelement <4 x float> %4, i32 1 %7 = extractelement <4 x float> %4, i32 2 %8 = extractelement <4 x float> %4, i32 3 %9 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %10 = getelementptr <4 x i32> addrspace(2)* %9, i32 1 %11 = load <4 x i32> addrspace(2)* %10 %12 = call i32 @llvm.SI.vs.load.buffer.index() %13 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %11, i32 0, i32 %12) %14 = extractelement <4 x float> %13, i32 0 %15 = extractelement <4 x float> %13, i32 1 %16 = extractelement <4 x float> %13, i32 2 %17 = extractelement <4 x float> %13, i32 3 %18 = load float addrspace(2)* addrspace(8)* null %19 = getelementptr float addrspace(2)* %18, i32 0 %20 = load float addrspace(2)* %19 %21 = fmul float %5, %20 %22 = load float addrspace(2)* addrspace(8)* null %23 = getelementptr float addrspace(2)* %22, i32 1 %24 = load float addrspace(2)* %23 %25 = fmul float %5, %24 %26 = load float addrspace(2)* addrspace(8)* null %27 = getelementptr float addrspace(2)* %26, i32 2 %28 = load float addrspace(2)* %27 %29 = fmul float %5, %28 %30 = load float addrspace(2)* addrspace(8)* null %31 = getelementptr float addrspace(2)* %30, i32 3 %32 = load float addrspace(2)* %31 %33 = fmul float %5, %32 %34 = load float addrspace(2)* addrspace(8)* null %35 = getelementptr float addrspace(2)* %34, i32 4 %36 = load float addrspace(2)* %35 %37 = fmul float %6, %36 %38 = fadd float %37, %21 %39 = load float addrspace(2)* addrspace(8)* null %40 = getelementptr float addrspace(2)* %39, i32 5 %41 = load float addrspace(2)* %40 %42 = fmul float %6, %41 %43 = fadd float %42, %25 %44 = load float addrspace(2)* addrspace(8)* null %45 = getelementptr float addrspace(2)* %44, i32 6 %46 = load float addrspace(2)* %45 %47 = fmul float %6, %46 %48 = fadd float %47, %29 %49 = load float addrspace(2)* addrspace(8)* null %50 = getelementptr float addrspace(2)* %49, i32 7 %51 = load float addrspace(2)* %50 %52 = fmul float %6, %51 %53 = fadd float %52, %33 %54 = load float addrspace(2)* addrspace(8)* null %55 = getelementptr float addrspace(2)* %54, i32 8 %56 = load float addrspace(2)* %55 %57 = fmul float %7, %56 %58 = fadd float %57, %38 %59 = load float addrspace(2)* addrspace(8)* null %60 = getelementptr float addrspace(2)* %59, i32 9 %61 = load float addrspace(2)* %60 %62 = fmul float %7, %61 %63 = fadd float %62, %43 %64 = load float addrspace(2)* addrspace(8)* null %65 = getelementptr float addrspace(2)* %64, i32 10 %66 = load float addrspace(2)* %65 %67 = fmul float %7, %66 %68 = fadd float %67, %48 %69 = load float addrspace(2)* addrspace(8)* null %70 = getelementptr float addrspace(2)* %69, i32 11 %71 = load float addrspace(2)* %70 %72 = fmul float %7, %71 %73 = fadd float %72, %53 %74 = load float addrspace(2)* addrspace(8)* null %75 = getelementptr float addrspace(2)* %74, i32 12 %76 = load float addrspace(2)* %75 %77 = fmul float %8, %76 %78 = fadd float %77, %58 %79 = load float addrspace(2)* addrspace(8)* null %80 = getelementptr float addrspace(2)* %79, i32 13 %81 = load float addrspace(2)* %80 %82 = fmul float %8, %81 %83 = fadd float %82, %63 %84 = load float addrspace(2)* addrspace(8)* null %85 = getelementptr float addrspace(2)* %84, i32 14 %86 = load float addrspace(2)* %85 %87 = fmul float %8, %86 %88 = fadd float %87, %68 %89 = load float addrspace(2)* addrspace(8)* null %90 = getelementptr float addrspace(2)* %89, i32 15 %91 = load float addrspace(2)* %90 %92 = fmul float %8, %91 %93 = fadd float %92, %73 %94 = call float @llvm.AMDIL.clamp.(float %14, float 0.000000e+00, float 1.000000e+00) %95 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00) %96 = call float @llvm.AMDIL.clamp.(float %16, float 0.000000e+00, float 1.000000e+00) %97 = call float @llvm.AMDIL.clamp.(float %17, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %94, float %95, float %96, float %97) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %78, float %83, float %88, float %93) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare i32 @llvm.SI.vs.load.buffer.index() #0 declare <4 x float> @llvm.SI.vs.load.input(<4 x i32>, i32, i32) declare float @llvm.AMDIL.clamp.(float, float, float) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readnone } SI CODE: 00000011 0000000b 00000000 c0840700 bf8c007f e00c2000 80020100 c0820704 bf8c0000 e00c2000 80010700 bf8c0700 d2060800 0201010a d2060805 02010109 d2060806 02010108 d2060807 02010107 c001010c c0018108 c0020104 c0028100 c003010d c0038109 c0040105 c0048101 c005010e c005810a c0060106 c0068102 c007010f c007810b c0080107 c0000103 f800020f 00050607 bf8c000f 7e000200 10000101 7e0a0210 d2820000 04020b02 7e0a020f d2820000 04020b03 7e0a020e d2820000 04020b04 7e0a020d 100a0b01 7e0c020c d2820005 04160d02 7e0c020b d2820005 04160d03 7e0c020a d2820005 04160d04 7e0c0209 100c0d01 7e0e0208 d2820006 041a0f02 7e0e0207 d2820006 041a0f03 7e0e0206 d2820006 041a0f04 7e0e0205 100e0f01 7e100204 d2820007 041e1102 7e100203 d2820007 041e1103 7e100202 d2820001 041e1104 f80008cf 00050601 bf810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV_SAT OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.persp.center(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.persp.center(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.persp.center(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.persp.center(i32 3, i32 0, i32 %0) %5 = call float @llvm.AMDIL.clamp.(float %1, float 0.000000e+00, float 1.000000e+00) %6 = call float @llvm.AMDIL.clamp.(float %2, float 0.000000e+00, float 1.000000e+00) %7 = call float @llvm.AMDIL.clamp.(float %3, float 0.000000e+00, float 1.000000e+00) %8 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00) %9 = call i32 @llvm.SI.packf16(float %5, float %6) %10 = bitcast i32 %9 to float %11 = call i32 @llvm.SI.packf16(float %7, float %8) %12 = bitcast i32 %11 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %10, float %12, float %10, float %12) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.persp.center(i32, i32, i32) #0 declare float @llvm.AMDIL.clamp.(float, float, float) #1 declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readonly } attributes #1 = { readnone } ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.persp.center(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.persp.center(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.persp.center(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.persp.center(i32 3, i32 0, i32 %0) %5 = call float @llvm.AMDIL.clamp.(float %1, float 0.000000e+00, float 1.000000e+00) %6 = call float @llvm.AMDIL.clamp.(float %2, float 0.000000e+00, float 1.000000e+00) %7 = call float @llvm.AMDIL.clamp.(float %3, float 0.000000e+00, float 1.000000e+00) %8 = call float @llvm.AMDIL.clamp.(float %4, float 0.000000e+00, float 1.000000e+00) %9 = call i32 @llvm.SI.packf16(float %5, float %6) %10 = bitcast i32 %9 to float %11 = call i32 @llvm.SI.packf16(float %7, float %8) %12 = bitcast i32 %11 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %10, float %12, float %10, float %12) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.persp.center(i32, i32, i32) #0 declare float @llvm.AMDIL.clamp.(float, float, float) #1 declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readonly } attributes #1 = { readnone } SI CODE: 00000007 00000004 00000002 befe0a7e befc0306 c8080300 c8090301 d2060802 02010102 c80c0200 c80d0201 d2060803 02010103 5e040503 c80c0100 c80d0101 d2060803 02010103 c8000000 c8010001 d2060800 02010100 5e000700 f8001c0f 02000200 bf810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 1) %0 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %1 = getelementptr <4 x i32> addrspace(2)* %0, i32 0 %2 = load <4 x i32> addrspace(2)* %1 %3 = call i32 @llvm.SI.vs.load.buffer.index() %4 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %2, i32 0, i32 %3) %5 = extractelement <4 x float> %4, i32 0 %6 = extractelement <4 x float> %4, i32 1 %7 = extractelement <4 x float> %4, i32 2 %8 = extractelement <4 x float> %4, i32 3 %9 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %10 = getelementptr <4 x i32> addrspace(2)* %9, i32 1 %11 = load <4 x i32> addrspace(2)* %10 %12 = call i32 @llvm.SI.vs.load.buffer.index() %13 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %11, i32 0, i32 %12) %14 = extractelement <4 x float> %13, i32 0 %15 = extractelement <4 x float> %13, i32 1 %16 = extractelement <4 x float> %13, i32 2 %17 = extractelement <4 x float> %13, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %14, float %15, float %16, float %17) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %5, float %6, float %7, float %8) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare i32 @llvm.SI.vs.load.buffer.index() #0 declare <4 x float> @llvm.SI.vs.load.input(<4 x i32>, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readnone } ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 1) %0 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %1 = getelementptr <4 x i32> addrspace(2)* %0, i32 0 %2 = load <4 x i32> addrspace(2)* %1 %3 = call i32 @llvm.SI.vs.load.buffer.index() %4 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %2, i32 0, i32 %3) %5 = extractelement <4 x float> %4, i32 0 %6 = extractelement <4 x float> %4, i32 1 %7 = extractelement <4 x float> %4, i32 2 %8 = extractelement <4 x float> %4, i32 3 %9 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 6 to <4 x i32> addrspace(2)* addrspace(8)*) %10 = getelementptr <4 x i32> addrspace(2)* %9, i32 1 %11 = load <4 x i32> addrspace(2)* %10 %12 = call i32 @llvm.SI.vs.load.buffer.index() %13 = call <4 x float> @llvm.SI.vs.load.input(<4 x i32> %11, i32 0, i32 %12) %14 = extractelement <4 x float> %13, i32 0 %15 = extractelement <4 x float> %13, i32 1 %16 = extractelement <4 x float> %13, i32 2 %17 = extractelement <4 x float> %13, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %14, float %15, float %16, float %17) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %5, float %6, float %7, float %8) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare i32 @llvm.SI.vs.load.buffer.index() #0 declare <4 x float> @llvm.SI.vs.load.input(<4 x i32>, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readnone } SI CODE: 00000008 00000009 00000000 c0800700 bf8c007f e00c2000 80000100 c0800704 bf8c0000 e00c2000 80000500 bf8c0700 f800020f 08070605 f80008cf 04030201 bf810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.constant(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.constant(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.constant(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.constant(i32 3, i32 0, i32 %0) call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.constant(i32, i32, i32) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { readonly } ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.constant(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.constant(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.constant(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.constant(i32 3, i32 0, i32 %0) call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.constant(i32, i32, i32) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { readonly } SI CODE: 00000007 00000001 00000001 befe0a7e befc0306 c8020302 c8020202 c8020102 c8020002 7e000280 f8001800 00000000 bf810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.linear.center(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.linear.center(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.linear.center(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.linear.center(i32 3, i32 0, i32 %0) %5 = bitcast float %1 to i32 %6 = bitcast float %2 to i32 %7 = insertelement <2 x i32> undef, i32 %5, i32 0 %8 = insertelement <2 x i32> %7, i32 %6, i32 1 %9 = load <8 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 4 to <8 x i32> addrspace(2)* addrspace(8)*) %10 = getelementptr <8 x i32> addrspace(2)* %9, i32 0 %11 = load <8 x i32> addrspace(2)* %10 %12 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 2 to <4 x i32> addrspace(2)* addrspace(8)*) %13 = getelementptr <4 x i32> addrspace(2)* %12, i32 0 %14 = load <4 x i32> addrspace(2)* %13 %15 = call <4 x float> @llvm.SI.sample.v2i32(i32 15, <2 x i32> %8, <8 x i32> %11, <4 x i32> %14, i32 2) %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %16, float %17, float %18, float %19) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.linear.center(i32, i32, i32) #0 declare <4 x float> @llvm.SI.sample.v2i32(i32, <2 x i32>, <8 x i32>, <4 x i32>, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readonly } ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.linear.center(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.linear.center(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.linear.center(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.linear.center(i32 3, i32 0, i32 %0) %5 = bitcast float %1 to i32 %6 = bitcast float %2 to i32 %7 = insertelement <2 x i32> undef, i32 %5, i32 0 %8 = insertelement <2 x i32> %7, i32 %6, i32 1 %9 = load <8 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 4 to <8 x i32> addrspace(2)* addrspace(8)*) %10 = getelementptr <8 x i32> addrspace(2)* %9, i32 0 %11 = load <8 x i32> addrspace(2)* %10 %12 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 2 to <4 x i32> addrspace(2)* addrspace(8)*) %13 = getelementptr <4 x i32> addrspace(2)* %12, i32 0 %14 = load <4 x i32> addrspace(2)* %13 %15 = call <4 x float> @llvm.SI.sample.v2i32(i32 15, <2 x i32> %8, <8 x i32> %11, <4 x i32> %14, i32 2) %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %16, float %17, float %18, float %19) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.linear.center(i32, i32, i32) #0 declare <4 x float> @llvm.SI.sample.v2i32(i32, <2 x i32>, <8 x i32>, <4 x i32>, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readonly } SI CODE: 00000010 00000005 00000020 befe0a7e befc0306 c8080000 c8090001 c80c0100 c80d0101 c8100300 c8110301 c8000200 c8010201 c0800300 c0c40500 bf8c007f f0800f00 00020002 bf8c0700 f800180f 03020100 bf810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.linear.center(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.linear.center(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.linear.center(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.linear.center(i32 3, i32 0, i32 %0) %5 = bitcast float %1 to i32 %6 = bitcast float %2 to i32 %7 = insertelement <2 x i32> undef, i32 %5, i32 0 %8 = insertelement <2 x i32> %7, i32 %6, i32 1 %9 = load <8 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 4 to <8 x i32> addrspace(2)* addrspace(8)*) %10 = getelementptr <8 x i32> addrspace(2)* %9, i32 0 %11 = load <8 x i32> addrspace(2)* %10 %12 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 2 to <4 x i32> addrspace(2)* addrspace(8)*) %13 = getelementptr <4 x i32> addrspace(2)* %12, i32 0 %14 = load <4 x i32> addrspace(2)* %13 %15 = call <4 x float> @llvm.SI.sample.v2i32(i32 15, <2 x i32> %8, <8 x i32> %11, <4 x i32> %14, i32 2) %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = call i32 @llvm.SI.packf16(float %16, float %17) %21 = bitcast i32 %20 to float %22 = call i32 @llvm.SI.packf16(float %18, float %19) %23 = bitcast i32 %22 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %21, float %23, float %21, float %23) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.linear.center(i32, i32, i32) #0 declare <4 x float> @llvm.SI.sample.v2i32(i32, <2 x i32>, <8 x i32>, <4 x i32>, i32) declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readonly } attributes #1 = { readnone } ; ModuleID = 'tgsi' define void @main() { main_body: call void @llvm.AMDGPU.shader.type(i32 0) %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) call void @llvm.SI.wqm() %1 = call float @llvm.SI.fs.interp.linear.center(i32 0, i32 0, i32 %0) %2 = call float @llvm.SI.fs.interp.linear.center(i32 1, i32 0, i32 %0) %3 = call float @llvm.SI.fs.interp.linear.center(i32 2, i32 0, i32 %0) %4 = call float @llvm.SI.fs.interp.linear.center(i32 3, i32 0, i32 %0) %5 = bitcast float %1 to i32 %6 = bitcast float %2 to i32 %7 = insertelement <2 x i32> undef, i32 %5, i32 0 %8 = insertelement <2 x i32> %7, i32 %6, i32 1 %9 = load <8 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 4 to <8 x i32> addrspace(2)* addrspace(8)*) %10 = getelementptr <8 x i32> addrspace(2)* %9, i32 0 %11 = load <8 x i32> addrspace(2)* %10 %12 = load <4 x i32> addrspace(2)* addrspace(8)* inttoptr (i32 2 to <4 x i32> addrspace(2)* addrspace(8)*) %13 = getelementptr <4 x i32> addrspace(2)* %12, i32 0 %14 = load <4 x i32> addrspace(2)* %13 %15 = call <4 x float> @llvm.SI.sample.v2i32(i32 15, <2 x i32> %8, <8 x i32> %11, <4 x i32> %14, i32 2) %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = call i32 @llvm.SI.packf16(float %16, float %17) %21 = bitcast i32 %20 to float %22 = call i32 @llvm.SI.packf16(float %18, float %19) %23 = bitcast i32 %22 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %21, float %23, float %21, float %23) ret void } declare void @llvm.AMDGPU.shader.type(i32) declare void @llvm.SI.wqm() declare float @llvm.SI.fs.interp.linear.center(i32, i32, i32) #0 declare <4 x float> @llvm.SI.sample.v2i32(i32, <2 x i32>, <8 x i32>, <4 x i32>, i32) declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { readonly } attributes #1 = { readnone } SI CODE: 00000010 00000005 00000020 befe0a7e befc0306 c8080000 c8090001 c80c0100 c80d0101 c8100300 c8110301 c8000200 c8010201 c0800300 c0c40500 bf8c007f f0800f00 00020002 bf8c0700 5e080702 5e000300 f8001c0f 04000400 bf810000 1 frames in 5.0 seconds = 0.200 FPS