diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index a08f657..98e9e1d 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1656,25 +1656,30 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
 /*
  * Registers read & write functions.
  */
-#define RREG8(reg) readb((rdev->rmmio) + (reg))
-#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
-#define RREG16(reg) readw((rdev->rmmio) + (reg))
-#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
-#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
-#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
-#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
-#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
-#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
+
+unsigned char  testb(unsigned char  v);
+unsigned short testw(unsigned short v);
+unsigned long  testd(unsigned long  v);
+
+#define RREG8(reg)  testb(readb((rdev->rmmio) + (reg)))
+#define WREG8(reg, v) do { writeb(v, (rdev->rmmio) + (reg)); RREG8(reg); } while(0)
+#define RREG16(reg) testw(readw((rdev->rmmio) + (reg)))
+#define WREG16(reg, v) do { writew(v, (rdev->rmmio) + (reg)); RREG16(reg); } while (0)
+#define RREG32(reg) testd(r100_mm_rreg(rdev, (reg), false))
+#define RREG32_IDX(reg) testd(r100_mm_rreg(rdev, (reg), true))
+#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", testd(r100_mm_rreg(rdev, (reg), false)))
+#define WREG32(reg, v) do { r100_mm_wreg(rdev, (reg), (v), false); RREG32(v); } while(0)
+#define WREG32_IDX(reg, v) do { r100_mm_wreg(rdev, (reg), (v), true); RREG32(v); } while(0)
 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
-#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
-#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
-#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
-#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
-#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
-#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
-#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
-#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
+#define RREG32_PLL(reg) testd(rdev->pll_rreg(rdev, (reg)))
+#define WREG32_PLL(reg, v) do { rdev->pll_wreg(rdev, (reg), (v)); RREG32_PLL(reg); } while(0)
+#define RREG32_MC(reg) testd(rdev->mc_rreg(rdev, (reg)))
+#define WREG32_MC(reg, v) do { rdev->mc_wreg(rdev, (reg), (v)); RREG32_MC(reg); } while(0)
+#define RREG32_PCIE(reg) testd(rv370_pcie_rreg(rdev, (reg)))
+#define WREG32_PCIE(reg, v) do { rv370_pcie_wreg(rdev, (reg), (v)); RREG32_PCIE(reg); } while(0)
+#define RREG32_PCIE_P(reg) testd(rdev->pciep_rreg(rdev, (reg)))
+#define WREG32_PCIE_P(reg, v) do { rdev->pciep_wreg(rdev, (reg), (v)); RREG32_PCIE_P(reg); } while(0)
 #define WREG32_P(reg, val, mask)				\
 	do {							\
 		uint32_t tmp_ = RREG32(reg);			\
@@ -1689,9 +1694,9 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
 		tmp_ |= ((val) & ~(mask));			\
 		WREG32_PLL(reg, tmp_);				\
 	} while (0)
-#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
-#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
-#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
+#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", testd(r100_mm_rreg((rdev), (reg), false)))
+#define RREG32_IO(reg) testd(r100_io_rreg(rdev, (reg)))
+#define WREG32_IO(reg, v) do { r100_io_wreg(rdev, (reg), (v)); RREG32_IO(reg); } while(0)
 
 /*
  * Indirect registers accessor
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 0d6562b..373c551 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -96,6 +96,21 @@ static const char radeon_family_name[][16] = {
 	"LAST",
 };
 
+#ifndef TESTB
+#define TESTB
+unsigned char  testb(unsigned char  v) { if (v == 0xff) WARN_ON(1); return v; }
+#endif
+
+#ifndef TESTW
+#define TESTW
+unsigned short testw(unsigned short v) { if (v == 0xffff) WARN_ON(1); return v; }
+#endif
+
+#ifndef TESTD
+#define TESTD
+unsigned long testd(unsigned long v) { if (v == 0xffffffff) WARN_ON(1); return v; }
+#endif
+
 /**
  * radeon_surface_init - Clear GPU surface registers.
  *