r300: Initial vertex program VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END Vertex Program: before compilation # Radeon Compiler Program 0: MOV temp[0], input[0]; 1: MOV output[1], input[1]; 2: MOV output[0], temp[0]; 3: MOV output[2], temp[0]; Vertex Program: after 'emulate negative addressing' # Radeon Compiler Program 0: MOV temp[0], input[0]; 1: MOV output[1], input[1]; 2: MOV output[0], temp[0]; 3: MOV output[2], temp[0]; Vertex Program: after 'native rewrite' # Radeon Compiler Program 0: MOV temp[0], input[0]; 1: MOV output[1], input[1]; 2: MOV output[0], temp[0]; 3: MOV output[2], temp[0]; Vertex Program: after 'deadcode' # Radeon Compiler Program 0: MOV temp[0], input[0]; 1: MOV output[1], input[1]; 2: MOV output[0], temp[0]; 3: MOV output[2], temp[0]; Vertex Program: after 'dataflow optimize' # Radeon Compiler Program 0: MOV output[1], input[1]; 1: MOV output[0], input[0]; 2: MOV output[2], input[0]; Vertex Program: after 'source conflict resolve' # Radeon Compiler Program 0: MOV output[1], input[1]; 1: MOV output[0], input[0]; 2: MOV output[2], input[0]; Vertex Program: after 'register allocation' # Radeon Compiler Program 0: MOV output[1], input[1]; 1: MOV output[0], input[0]; 2: MOV output[2], input[0]; Vertex Program: after 'dead constants' # Radeon Compiler Program 0: MOV output[1], input[1]; 1: MOV output[0], input[0]; 2: MOV output[2], input[0]; Vertex Program: after 'lower control flow opcodes' # Radeon Compiler Program 0: MOV output[1], input[1]; 1: MOV output[0], input[0]; 2: MOV output[2], input[0]; Final vertex program code: 0: op: 0x00f02203 dst: 1o op: VE_ADD src0: 0x00d10021 reg: 1i swiz: X/ Y/ Z/ W src1: 0x01248021 reg: 1i swiz: 0/ 0/ 0/ 0 src2: 0x01248021 reg: 1i swiz: 0/ 0/ 0/ 0 1: op: 0x00f00203 dst: 0o op: VE_ADD src0: 0x00d10001 reg: 0i swiz: X/ Y/ Z/ W src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 2: op: 0x00f04203 dst: 2o op: VE_ADD src0: 0x00d10001 reg: 0i swiz: X/ Y/ Z/ W src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 Flow Control Ops: 0x00000000 r300: DRM version: 2.29.0, Name: ATI RV530, ID: 0x71c5, GB: 1, Z: 2 r300: GART size: 509 MB, VRAM size: 256 MB r300: AA compression RAM: YES, Z compression RAM: YES, HiZ RAM: YES r300: Initial vertex program VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[19] DCL CONST[0..10] DCL TEMP[0..3], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MUL TEMP[0], CONST[7], IN[0].xxxx 1: MAD TEMP[0], CONST[8], IN[0].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[9], IN[0].zzzz, TEMP[0] 3: MAD TEMP[0], CONST[10], IN[0].wwww, TEMP[0] 4: ARL ADDR[0].x, CONST[6].xxxx 5: MOV TEMP[1].xy, CONST[ADDR[0].x+2].xyxx 6: SEQ TEMP[2].xy, CONST[5].xxxx, IMM[0].xyyy 7: CMP TEMP[3].x, -TEMP[2].xxxx, TEMP[1].xxxx, TEMP[3].xxxx 8: CMP TEMP[3].x, -TEMP[2].yyyy, TEMP[1].yyyy, TEMP[3].xxxx 9: SEQ TEMP[1].x, TEMP[3].xxxx, CONST[4].xxxx 10: IF TEMP[1].xxxx :0 11: MOV TEMP[1], IMM[0].xyxy 12: ELSE :0 13: MOV TEMP[1], IMM[0].yxxy 14: ENDIF 15: MOV OUT[1], TEMP[1] 16: MOV OUT[0], TEMP[0] 17: END Vertex Program: before compilation # Radeon Compiler Program 0: MUL temp[0], const[7], input[0].xxxx; 1: MAD temp[0], const[8], input[0].yyyy, temp[0]; 2: MAD temp[0], const[9], input[0].zzzz, temp[0]; 3: MAD temp[0], const[10], input[0].wwww, temp[0]; 4: ARL addr[0].x, const[6].xxxx; 5: MOV temp[1].xy, const[2 + addr[0]].xyxx; 6: SEQ temp[2].xy, const[5].xxxx, temp[0].0111; 7: CMP temp[3].x, -temp[2].xxxx, temp[1].xxxx, temp[3].xxxx; 8: CMP temp[3].x, -temp[2].yyyy, temp[1].yyyy, temp[3].xxxx; 9: SEQ temp[1].x, temp[3].xxxx, const[4].xxxx; 10: IF temp[1].xxxx; 11: MOV temp[1], temp[0].0101; 12: ELSE; 13: MOV temp[1], temp[0].1001; 14: ENDIF; 15: MOV output[1], temp[1]; 16: MOV temp[4], temp[0]; 17: MOV output[0], temp[4]; 18: MOV output[2], temp[4]; Vertex Program: after 'emulate negative addressing' # Radeon Compiler Program 0: MUL temp[0], const[7], input[0].xxxx; 1: MAD temp[0], const[8], input[0].yyyy, temp[0]; 2: MAD temp[0], const[9], input[0].zzzz, temp[0]; 3: MAD temp[0], const[10], input[0].wwww, temp[0]; 4: ARL addr[0].x, const[6].xxxx; 5: MOV temp[1].xy, const[2 + addr[0]].xyxx; 6: SEQ temp[2].xy, const[5].xxxx, temp[0].0111; 7: CMP temp[3].x, -temp[2].xxxx, temp[1].xxxx, temp[3].xxxx; 8: CMP temp[3].x, -temp[2].yyyy, temp[1].yyyy, temp[3].xxxx; 9: SEQ temp[1].x, temp[3].xxxx, const[4].xxxx; 10: IF temp[1].xxxx; 11: MOV temp[1], temp[0].0101; 12: ELSE; 13: MOV temp[1], temp[0].1001; 14: ENDIF; 15: MOV output[1], temp[1]; 16: MOV temp[4], temp[0]; 17: MOV output[0], temp[4]; 18: MOV output[2], temp[4]; Vertex Program: after 'native rewrite' # Radeon Compiler Program 0: MUL temp[0], const[7], input[0].xxxx; 1: MAD temp[0], const[8], input[0].yyyy, temp[0]; 2: MAD temp[0], const[9], input[0].zzzz, temp[0]; 3: MAD temp[0], const[10], input[0].wwww, temp[0]; 4: ARL addr[0].x, const[6].xxxx; 5: MOV temp[1].xy, const[2 + addr[0]].xyxx; 6: SEQ temp[2].xy, const[5].xxxx, temp[0].0111; 7: SLT temp[5].x, -temp[2].xxxx, none.0000; 8: ADD temp[6].x, temp[1].xxxx, -temp[3].xxxx; 9: MAD temp[3].x, temp[5], temp[6], temp[3].xxxx; 10: SLT temp[7].x, -temp[2].yyyy, none.0000; 11: ADD temp[8].x, temp[1].yyyy, -temp[3].xxxx; 12: MAD temp[3].x, temp[7], temp[8], temp[3].xxxx; 13: SEQ temp[1].x, temp[3].xxxx, const[4].xxxx; 14: IF temp[1].xxxx; 15: MOV temp[1], temp[0].0101; 16: ELSE; 17: MOV temp[1], temp[0].1001; 18: ENDIF; 19: MOV output[1], temp[1]; 20: MOV temp[4], temp[0]; 21: MOV output[0], temp[4]; 22: MOV output[2], temp[4]; Vertex Program: after 'deadcode' # Radeon Compiler Program 0: MUL temp[0], const[7], input[0].xxxx; 1: MAD temp[0], const[8], input[0].yyyy, temp[0]; 2: MAD temp[0], const[9], input[0].zzzz, temp[0]; 3: MAD temp[0], const[10], input[0].wwww, temp[0]; 4: ARL addr[0].x, const[6].x___; 5: MOV temp[1].xy, const[2 + addr[0]].xy__; 6: SEQ temp[2].xy, const[5].xx__, temp[0].01__; 7: SLT temp[5].x, -temp[2].x___, none.0___; 8: ADD temp[6].x, temp[1].x___, -temp[3].x___; 9: MAD temp[3].x, temp[5].x___, temp[6].x___, temp[3].x___; 10: SLT temp[7].x, -temp[2].y___, none.0___; 11: ADD temp[8].x, temp[1].y___, -temp[3].x___; 12: MAD temp[3].x, temp[7].x___, temp[8].x___, temp[3].x___; 13: SEQ temp[1].x, temp[3].x___, const[4].x___; 14: IF temp[1].x___; 15: MOV temp[1], temp[0].0101; 16: ELSE; 17: MOV temp[1], temp[0].1001; 18: ENDIF; 19: MOV output[1], temp[1]; 20: MOV temp[4], temp[0]; 21: MOV output[0], temp[4]; 22: MOV output[2], temp[4]; Vertex Program: after 'dataflow optimize' # Radeon Compiler Program 0: MUL temp[0], const[7], input[0].xxxx; 1: MAD temp[0], const[8], input[0].yyyy, temp[0]; 2: MAD temp[0], const[9], input[0].zzzz, temp[0]; 3: MAD temp[0], const[10], input[0].wwww, temp[0]; 4: ARL addr[0].x, const[6].x___; 5: SEQ temp[2].xy, const[5].xx__, none.01__; 6: SLT temp[5].x, -temp[2].x___, none.0___; 7: ADD temp[6].x, const[2 + addr[0]].x___, -temp[3].x___; 8: MAD temp[3].x, temp[5].x___, temp[6].x___, temp[3].x___; 9: SLT temp[7].x, -temp[2].y___, none.0___; 10: ADD temp[8].x, const[2 + addr[0]].y___, -temp[3].x___; 11: MAD temp[3].x, temp[7].x___, temp[8].x___, temp[3].x___; 12: SEQ temp[1].x, temp[3].x___, const[4].x___; 13: IF temp[1].x___; 14: MOV temp[1], none.0101; 15: ELSE; 16: MOV temp[1], none.1001; 17: ENDIF; 18: MOV output[1], temp[1]; 19: MOV output[0], temp[0]; 20: MOV output[2], temp[0]; Vertex Program: after 'source conflict resolve' # Radeon Compiler Program 0: MUL temp[0], const[7], input[0].xxxx; 1: MAD temp[0], const[8], input[0].yyyy, temp[0]; 2: MAD temp[0], const[9], input[0].zzzz, temp[0]; 3: MAD temp[0], const[10], input[0].wwww, temp[0]; 4: ARL addr[0].x, const[6].x___; 5: SEQ temp[2].xy, const[5].xx__, none.01__; 6: SLT temp[5].x, -temp[2].x___, none.0___; 7: ADD temp[6].x, const[2 + addr[0]].x___, -temp[3].x___; 8: MAD temp[3].x, temp[5].x___, temp[6].x___, temp[3].x___; 9: SLT temp[7].x, -temp[2].y___, none.0___; 10: ADD temp[8].x, const[2 + addr[0]].y___, -temp[3].x___; 11: MAD temp[3].x, temp[7].x___, temp[8].x___, temp[3].x___; 12: SEQ temp[1].x, temp[3].x___, const[4].x___; 13: IF temp[1].x___; 14: MOV temp[1], none.0101; 15: ELSE; 16: MOV temp[1], none.1001; 17: ENDIF; 18: MOV output[1], temp[1]; 19: MOV output[0], temp[0]; 20: MOV output[2], temp[0]; Vertex Program: after 'register allocation' # Radeon Compiler Program 0: MUL temp[0], const[7], input[0].xxxx; 1: MAD temp[0], const[8], input[0].yyyy, temp[0]; 2: MAD temp[0], const[9], input[0].zzzz, temp[0]; 3: MAD temp[0], const[10], input[0].wwww, temp[0]; 4: ARL addr[0].x, const[6].x___; 5: SEQ temp[1].xy, const[5].xx__, none.01__; 6: SLT temp[2].x, -temp[1].x___, none.0___; 7: ADD temp[3].x, const[2 + addr[0]].x___, -temp[0].x___; 8: MAD temp[2].x, temp[2].x___, temp[3].x___, temp[0].x___; 9: SLT temp[1].x, -temp[1].y___, none.0___; 10: ADD temp[3].x, const[2 + addr[0]].y___, -temp[2].x___; 11: MAD temp[2].x, temp[1].x___, temp[3].x___, temp[2].x___; 12: SEQ temp[1].x, temp[2].x___, const[4].x___; 13: IF temp[1].x___; 14: MOV temp[1], none.0101; 15: ELSE; 16: MOV temp[1], none.1001; 17: ENDIF; 18: MOV output[1], temp[1]; 19: MOV output[0], temp[0]; 20: MOV output[2], temp[0]; Vertex Program: after 'dead constants' # Radeon Compiler Program 0: MUL temp[0], const[7], input[0].xxxx; 1: MAD temp[0], const[8], input[0].yyyy, temp[0]; 2: MAD temp[0], const[9], input[0].zzzz, temp[0]; 3: MAD temp[0], const[10], input[0].wwww, temp[0]; 4: ARL addr[0].x, const[6].x___; 5: SEQ temp[1].xy, const[5].xx__, none.01__; 6: SLT temp[2].x, -temp[1].x___, none.0___; 7: ADD temp[3].x, const[2 + addr[0]].x___, -temp[0].x___; 8: MAD temp[2].x, temp[2].x___, temp[3].x___, temp[0].x___; 9: SLT temp[1].x, -temp[1].y___, none.0___; 10: ADD temp[3].x, const[2 + addr[0]].y___, -temp[2].x___; 11: MAD temp[2].x, temp[1].x___, temp[3].x___, temp[2].x___; 12: SEQ temp[1].x, temp[2].x___, const[4].x___; 13: IF temp[1].x___; 14: MOV temp[1], none.0101; 15: ELSE; 16: MOV temp[1], none.1001; 17: ENDIF; 18: MOV output[1], temp[1]; 19: MOV output[0], temp[0]; 20: MOV output[2], temp[0]; Vertex Program: after 'lower control flow opcodes' # Radeon Compiler Program 0: MUL temp[0], const[7], input[0].xxxx; 1: MAD temp[0], const[8], input[0].yyyy, temp[0]; 2: MAD temp[0], const[9], input[0].zzzz, temp[0]; 3: MAD temp[0], const[10], input[0].wwww, temp[0]; 4: ARL addr[0].x, const[6].x___; 5: SEQ temp[1].xy, const[5].xx__, none.01__; 6: SLT temp[2].x, -temp[1].x___, none.0___; 7: ADD temp[3].x, const[2 + addr[0]].x___, -temp[0].x___; 8: MAD temp[2].x, temp[2].x___, temp[3].x___, temp[0].x___; 9: SLT temp[1].x, -temp[1].y___, none.0___; 10: ADD temp[3].x, const[2 + addr[0]].y___, -temp[2].x___; 11: MAD temp[2].x, temp[1].x___, temp[3].x___, temp[2].x___; 12: SEQ temp[1].x, temp[2].x___, const[4].x___; 13: ME_PRED_SNEQ temp[4].w, temp[1].x___; 14: MOV temp[1], none.0101; PRED_SET 15: ME_PRED_SET_INV temp[4].w, temp[4].___w; 16: MOV temp[1], none.1001; PRED_SET 17: ME_PRED_SET_POP temp[4].w, temp[4].___w; 18: MOV output[1], temp[1]; 19: MOV output[0], temp[0]; 20: MOV output[2], temp[0]; Final vertex program code: 0: op: 0x00f00002 dst: 0t op: VE_MULTIPLY src0: 0x00d100e2 reg: 7c swiz: X/ Y/ Z/ W src1: 0x00000001 reg: 0i swiz: X/ X/ X/ X src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 1: op: 0x00f00004 dst: 0t op: VE_MULTIPLY_ADD src0: 0x00d10102 reg: 8c swiz: X/ Y/ Z/ W src1: 0x00492001 reg: 0i swiz: Y/ Y/ Y/ Y src2: 0x00d10000 reg: 0t swiz: X/ Y/ Z/ W 2: op: 0x00f00004 dst: 0t op: VE_MULTIPLY_ADD src0: 0x00d10122 reg: 9c swiz: X/ Y/ Z/ W src1: 0x00924001 reg: 0i swiz: Z/ Z/ Z/ Z src2: 0x00d10000 reg: 0t swiz: X/ Y/ Z/ W 3: op: 0x00f00004 dst: 0t op: VE_MULTIPLY_ADD src0: 0x00d10142 reg: 10c swiz: X/ Y/ Z/ W src1: 0x00db6001 reg: 0i swiz: W/ W/ W/ W src2: 0x00d10000 reg: 0t swiz: X/ Y/ Z/ W 4: op: 0x0010010d dst: 0a0 op: VE_FLT2FIX_DX src0: 0x01ff00c2 reg: 6c swiz: X/ U/ U/ U src1: 0x012480c2 reg: 6c swiz: 0/ 0/ 0/ 0 src2: 0x012480c2 reg: 6c swiz: 0/ 0/ 0/ 0 5: op: 0x0030201b dst: 1t op: VE_SET_EQUAL src0: 0x01f800a2 reg: 5c swiz: X/ X/ U/ U src1: 0x01fd8000 reg: 0t swiz: 0/ 1/ U/ U src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 6: op: 0x0010400a dst: 2t op: VE_SET_LESS_THAN src0: 0x1fff0020 reg: 1t swiz: -X/-U/-U/-U src1: 0x01ff8000 reg: 0t swiz: 0/ U/ U/ U src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 7: op: 0x00106003 dst: 3t op: VE_ADD src0: 0x01ff0052 reg: 2c swiz: X/ U/ U/ U src1: 0x1fff0000 reg: 0t swiz: -X/-U/-U/-U src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 8: op: 0x00104080 dst: 2t op: PVS_MACRO_OP_2CLK_MADD src0: 0x01ff0040 reg: 2t swiz: X/ U/ U/ U src1: 0x01ff0060 reg: 3t swiz: X/ U/ U/ U src2: 0x01ff0000 reg: 0t swiz: X/ U/ U/ U 9: op: 0x0010200a dst: 1t op: VE_SET_LESS_THAN src0: 0x1fff2020 reg: 1t swiz: -Y/-U/-U/-U src1: 0x01ff8000 reg: 0t swiz: 0/ U/ U/ U src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 10: op: 0x00106003 dst: 3t op: VE_ADD src0: 0x01ff2052 reg: 2c swiz: Y/ U/ U/ U src1: 0x1fff0040 reg: 2t swiz: -X/-U/-U/-U src2: 0x01248040 reg: 2t swiz: 0/ 0/ 0/ 0 11: op: 0x00104080 dst: 2t op: PVS_MACRO_OP_2CLK_MADD src0: 0x01ff0020 reg: 1t swiz: X/ U/ U/ U src1: 0x01ff0060 reg: 3t swiz: X/ U/ U/ U src2: 0x01ff0040 reg: 2t swiz: X/ U/ U/ U 12: op: 0x0010201b dst: 1t op: VE_SET_EQUAL src0: 0x01ff0040 reg: 2t swiz: X/ U/ U/ U src1: 0x01ff0082 reg: 4c swiz: X/ U/ U/ U src2: 0x01248082 reg: 4c swiz: 0/ 0/ 0/ 0 13: op: 0x00808058 dst: 4t op: ME_PRED_SET_NEQ src0: 0x00000020 reg: 1t swiz: X/ X/ X/ X src1: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 src2: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 14: op: 0x0cf02003 dst: 1t op: PRED 1 VE_ADD src0: 0x01658000 reg: 0t swiz: 0/ 1/ 0/ 1 src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 15: op: 0x0080805a dst: 4t op: ME_PRED_SET_INV src0: 0x00db6080 reg: 4t swiz: W/ W/ W/ W src1: 0x01248080 reg: 4t swiz: 0/ 0/ 0/ 0 src2: 0x01248080 reg: 4t swiz: 0/ 0/ 0/ 0 16: op: 0x0cf02003 dst: 1t op: PRED 1 VE_ADD src0: 0x0164a000 reg: 0t swiz: 1/ 0/ 0/ 1 src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 17: op: 0x0080805b dst: 4t op: ME_PRED_SET_POP src0: 0x00db6080 reg: 4t swiz: W/ W/ W/ W src1: 0x01248080 reg: 4t swiz: 0/ 0/ 0/ 0 src2: 0x01248080 reg: 4t swiz: 0/ 0/ 0/ 0 18: op: 0x00f02203 dst: 1o op: VE_ADD src0: 0x00d10020 reg: 1t swiz: X/ Y/ Z/ W src1: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 src2: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 19: op: 0x00f00203 dst: 0o op: VE_ADD src0: 0x00d10000 reg: 0t swiz: X/ Y/ Z/ W src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 20: op: 0x00f04203 dst: 2o op: VE_ADD src0: 0x00d10000 reg: 0t swiz: X/ Y/ Z/ W src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 Flow Control Ops: 0x00000000 r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'transform IF' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'register rename' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'inline literals' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'dead sources' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 r300: Initial fragment program FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[19], PERSPECTIVE DCL OUT[0], COLOR DCL CONST[0..3] 0: MOV_SAT OUT[0], IN[0] 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV_SAT output[0], input[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: MOV_SAT output[0], input[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: MOV_SAT output[0], input[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: MOV_SAT output[0], input[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: MOV_SAT output[0], input[0]; Fragment Program: after 'transform IF' # Radeon Compiler Program 0: MOV_SAT output[0], input[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: MOV_SAT output[0], input[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: MOV_SAT output[0], input[0]; Fragment Program: after 'register rename' # Radeon Compiler Program 0: MOV_SAT output[0], input[0]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: MOV_SAT output[0], input[0]; Fragment Program: after 'inline literals' # Radeon Compiler Program 0: MOV_SAT output[0], input[0]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: MOV_SAT output[0], input[0]; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: MOV_SAT output[0], input[0]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'dead sources' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x001f8005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 r300: Initial fragment program fallback: no matching format for GL_RGB, GL_FLOAT FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END Fragment Program: before compilation # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TEX temp[1], input[0], 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'transform IF' # Radeon Compiler Program 0: TEX temp[1], input[0], 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TEX temp[1], input[0], 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'register rename' # Radeon Compiler Program 0: TEX temp[0], input[0].xy__, 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TEX temp[0], input[0].xy__, 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'inline literals' # Radeon Compiler Program 0: TEX temp[0], input[0].xy__, 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TEX temp[0], input[0].xy__, 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TEX temp[0], input[0].xy__, 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TEX temp[0], input[0].xy__, 2D[0]; 1: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[0], input[0].xy__, 2D[0] SEM_WAIT SEM_ACQUIRE; 2: src0.xyz = temp[0], src0.w = temp[0] SEM_WAIT MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'dead sources' # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[0], input[0].xy__, 2D[0] SEM_WAIT SEM_ACQUIRE; 2: src0.xyz = temp[0], src0.w = temp[0] SEM_WAIT MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[0], input[0].xy__, 2D[0] SEM_WAIT SEM_ACQUIRE; 2: src0.xyz = temp[0], src0.w = temp[0] SEM_WAIT MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x02400000: id: 0 op:LD, ACQ, SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 Probe at (50,10) Expected: 0.000000 1.000000 0.000000 Observed: 1.000000 0.000000 0.000000 fallback: no matching format for GL_RGB, GL_FLOAT Probe at (50,25) Expected: 0.000000 1.000000 0.000000 Observed: 1.000000 0.000000 0.000000 fallback: no matching format for GL_RGB, GL_FLOAT Probe at (65,10) Expected: 0.000000 1.000000 0.000000 Observed: 0.549020 0.450980 0.000000 fallback: no matching format for GL_RGB, GL_FLOAT Probe at (65,25) Expected: 0.000000 1.000000 0.000000 Observed: 1.000000 0.000000 0.000000 PIGLIT: {'result': 'fail' }