From c25683e7feb4cb8517387a55be509ce43c07656b Mon Sep 17 00:00:00 2001 From: Niels Ole Salscheider Date: Fri, 12 Apr 2013 22:50:42 +0200 Subject: [PATCH 1/2] radeon: add r600_dma_fill / evergreen_dma_fill --- src/gallium/drivers/r600/evergreen_hw_context.c | 37 +++++++++++++++++++++++++ src/gallium/drivers/r600/r600_hw_context.c | 37 +++++++++++++++++++++++++ src/gallium/drivers/r600/r600_pipe.h | 10 +++++++ 3 files changed, 84 insertions(+) diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c index d980c18..26962d5 100644 --- a/src/gallium/drivers/r600/evergreen_hw_context.c +++ b/src/gallium/drivers/r600/evergreen_hw_context.c @@ -106,3 +106,40 @@ void evergreen_dma_copy(struct r600_context *rctx, util_range_add(&rdst->valid_buffer_range, dst_offset, dst_offset + size); } + +/* dst has to be DW aligned */ +void evergreen_dma_fill(struct r600_context *rctx, + struct pipe_resource *dst, + uint64_t dst_offset, + uint32_t const_data, + uint64_t size) +{ + struct radeon_winsys_cs *cs = rctx->rings.dma.cs; + unsigned i, nfill, fsize; + struct r600_resource *rdst = (struct r600_resource*)dst; + + /* make sure that the dma ring is only one active */ + rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC); + dst_offset += r600_resource_va(&rctx->screen->screen, dst); + + /* count is in DW */ + size >>= 2; + + nfill = (size / 0x000fffff) + !!(size % 0x000fffff); + + r600_need_dma_space(rctx, nfill * 4); + for (i = 0; i < nfill; i++) { + fsize = size < 0x000fffff ? size : 0x000fffff; + /* emit reloc before writting cs so that cs is always in consistent state */ + r600_context_bo_reloc(rctx, &rctx->rings.dma, rdst, RADEON_USAGE_WRITE); + cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_CONSTANT_FILL, 0x00, fsize); + cs->buf[cs->cdw++] = dst_offset & 0xfffffffc; + cs->buf[cs->cdw++] = const_data; + cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff; + dst_offset += fsize << 2; + size -= fsize; + } + + util_range_add(&rdst->valid_buffer_range, dst_offset, + dst_offset + size); +} diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index b4fb3bf..933b320 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -756,3 +756,40 @@ void r600_dma_copy(struct r600_context *rctx, util_range_add(&rdst->valid_buffer_range, dst_offset, dst_offset + size); } + +/* dst has to be DW aligned */ +void r600_dma_fill(struct r600_context *rctx, + struct pipe_resource *dst, + uint64_t dst_offset, + uint32_t const_data, + uint64_t size) +{ + struct radeon_winsys_cs *cs = rctx->rings.dma.cs; + unsigned i, nfill, fsize; + struct r600_resource *rdst = (struct r600_resource*)dst; + + /* make sure that the dma ring is only one active */ + rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC); + dst_offset += r600_resource_va(&rctx->screen->screen, dst); + + /* count is in DW */ + size >>= 2; + + nfill = (size / 0x0000ffff) + !!(size % 0x0000ffff); + + r600_need_dma_space(rctx, nfill * 4); + for (i = 0; i < nfill; i++) { + fsize = size < 0x0000ffff ? size : 0x0000ffff; + /* emit reloc before writting cs so that cs is always in consistent state */ + r600_context_bo_reloc(rctx, &rctx->rings.dma, rdst, RADEON_USAGE_WRITE); + cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_CONSTANT_FILL, 0, 0, fsize); + cs->buf[cs->cdw++] = dst_offset & 0xfffffffc; + cs->buf[cs->cdw++] = const_data; + cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff; + dst_offset += fsize << 2; + size -= fsize; + } + + util_range_add(&rdst->valid_buffer_range, dst_offset, + dst_offset + size); +} diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index 4a692e7..370585a 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -828,6 +828,11 @@ void r600_dma_copy(struct r600_context *rctx, uint64_t dst_offset, uint64_t src_offset, uint64_t size); +void r600_dma_fill(struct r600_context *rctx, + struct pipe_resource *dst, + uint64_t dst_offset, + uint32_t const_data, + uint64_t size); boolean r600_dma_blit(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dst_level, @@ -849,6 +854,11 @@ void evergreen_dma_copy(struct r600_context *rctx, uint64_t dst_offset, uint64_t src_offset, uint64_t size); +void evergreen_dma_fill(struct r600_context *rctx, + struct pipe_resource *dst, + uint64_t dst_offset, + uint32_t const_data, + uint64_t size); boolean evergreen_dma_blit(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dst_level, -- 1.8.2.1