From 4b4c7b91cb90d9a6b706352e9c6edf21d4720659 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Tue, 14 May 2013 08:02:39 -0700 Subject: [PATCH 2/2] R600: Handle special encoding for R600 chips --- lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp index c5bd01a..cb4cf0c 100644 --- a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp @@ -179,6 +179,13 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, Emit((u_int32_t) 0, OS); } else { uint64_t Inst = getBinaryCodeForInstr(MI, Fixups); + if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) && + ((Desc.TSFlags & R600_InstFlag::OP1) || + Desc.TSFlags & R600_InstFlag::OP2)) { + uint64_t ISAOpCode = Inst & (0x3FFULL << 39); + Inst &= ~(0x3FFULL << 39); + Inst |= ISAOpCode << 1; + } Emit(Inst, OS); } } -- 1.7.11.4