From 0b84c58672696138755e345f79302bde94d268f1 Mon Sep 17 00:00:00 2001 From: Vincent Lejeune Date: Thu, 23 May 2013 17:14:19 +0200 Subject: [PATCH] R600: fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg --- lib/Target/R600/R600ControlFlowFinalizer.cpp | 11 +++++++++-- test/CodeGen/R600/vtx-schedule.ll | 22 ++++++++++++++++++++++ 2 files changed, 31 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/R600/vtx-schedule.ll diff --git a/lib/Target/R600/R600ControlFlowFinalizer.cpp b/lib/Target/R600/R600ControlFlowFinalizer.cpp index 65a4801..c0a9af6 100644 --- a/lib/Target/R600/R600ControlFlowFinalizer.cpp +++ b/lib/Target/R600/R600ControlFlowFinalizer.cpp @@ -116,8 +116,15 @@ private: const MachineOperand &MO = *I; if (!MO.isReg()) continue; - if (MO.isDef()) - DstMI = MO.getReg(); + if (MO.isDef()) { + unsigned Reg = MO.getReg(); + if (AMDGPU::R600_Reg128RegClass.contains(Reg)) + DstMI = Reg; + else + DstMI = TRI.getMatchingSuperReg(Reg, + TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)), + &AMDGPU::R600_Reg128RegClass); + } if (MO.isUse()) { unsigned Reg = MO.getReg(); if (AMDGPU::R600_Reg128RegClass.contains(Reg)) diff --git a/test/CodeGen/R600/vtx-schedule.ll b/test/CodeGen/R600/vtx-schedule.ll new file mode 100644 index 0000000..a0c79e3 --- /dev/null +++ b/test/CodeGen/R600/vtx-schedule.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; This test is for a scheduler bug where VTX_READ instructions that used +; the result of another VTX_READ instruction were being grouped in the +; same fetch clasue. + +; CHECK: @test +; CHECK: Fetch clause +; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 40 +; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 44 +; CHECK: Fetch clause +; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0 +; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0 +define void @test(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in0, i32 addrspace(1)* nocapture %in1) { +entry: + %0 = load i32 addrspace(1)* %in0, align 4 + %1 = load i32 addrspace(1)* %in1, align 4 + %cmp.i = icmp slt i32 %0, %1 + %cond.i = select i1 %cmp.i, i32 %0, i32 %1 + store i32 %cond.i, i32 addrspace(1)* %out, align 4 + ret void +} -- 1.7.11.4