diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
index d0817d9..ad1819b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
@@ -50,11 +50,23 @@ nv50_dac_sense(struct nv50_disp_priv *priv, int or, u32 loadval)
 {
 	const u32 doff = (or * 0x800);
 	int load = -EINVAL;
+	u32 dpms_state;
+
+/*	nv_wr32(priv, NV50_PDISPLAY_DAC_CLK_CTRL1(or), 0x00000001); */
+	dpms_state = nv_rd32(priv, 0x61a004 + doff);
+	nv_info(priv, "[1] 0x%x\n", dpms_state);
+	nv_wr32(priv, 0x61a004 + doff, 0x80000000 | 0x00150000);
+	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
+
 	nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval);
+/*	mdelay(45); */
 	udelay(9500);
 	nv_wr32(priv, 0x61a00c + doff, 0x80000000);
 	load = (nv_rd32(priv, 0x61a00c + doff) & 0x38000000) >> 27;
 	nv_wr32(priv, 0x61a00c + doff, 0x00000000);
+
+	nv_info(priv, "[2] 0x%x\n", nv_rd32(priv, 0x61a004 + doff));
+	nv_wr32(priv, 0x61a004 + doff, 0x80000000 | dpms_state);
 	return load;
 }