[ 30.137695] [drm:i915_driver_open], [ 30.137711] [drm:intel_crtc_set_config], [CRTC:3] [FB:12] #connectors=1 (x y) (0 0) [ 30.137716] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 30.137719] [drm:intel_crtc_set_config], [CRTC:5] [NOFB] [ 30.137721] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 30.137726] [drm:i915_driver_open], [ 30.137844] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[4] ENCODERS[4] [ 30.137850] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[4] ENCODERS[4] [ 30.137858] [drm:drm_mode_getconnector], [CONNECTOR:10:?] [ 30.137860] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] [ 30.137869] [drm:drm_edid_to_eld], ELD: no CEA Extension found [ 30.137872] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes : [ 30.137874] [drm:drm_mode_debug_printmodeline], Modeline 23:"1600x900" 60 97780 1600 1648 1680 1760 900 903 908 926 0x48 0xa [ 30.137878] [drm:drm_mode_getconnector], [CONNECTOR:10:?] [ 30.215739] [drm:drm_mode_addfb], [FB:22] [ 30.215785] [drm:drm_mode_setcrtc], [CRTC:3] [ 30.215796] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 30.215799] [drm:intel_crtc_set_config], [CRTC:3] [FB:22] #connectors=1 (x y) (0 0) [ 30.215802] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 30.215804] [drm:drm_mode_debug_printmodeline], Modeline 11:"1600x900" 60 97780 1600 1648 1680 1760 900 903 908 926 0x48 0xa [ 30.215807] [drm:drm_mode_debug_printmodeline], Modeline 24:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0x0 [ 30.215810] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 30.215812] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 30.215815] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 30.215817] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18 [ 30.215820] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 97780KHz [ 30.215822] [drm:intel_dp_compute_config], DP link bw 0a lane count 1 clock 270000 bpp 18 [ 30.215824] [drm:intel_dp_compute_config], DP link bw required 176004 available 216000 [ 30.215826] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1 [ 30.215828] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A [ 30.215830] [drm:intel_dump_pipe_config], cpu_transcoder: A [ 30.215831] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 30.215833] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 30.215835] [drm:intel_dump_pipe_config], requested mode: [ 30.215836] [drm:drm_mode_debug_printmodeline], Modeline 0:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0x0 [ 30.215839] [drm:intel_dump_pipe_config], adjusted mode: [ 30.215840] [drm:drm_mode_debug_printmodeline], Modeline 0:"800x600" 59 97780 1600 1648 1680 1760 900 903 908 926 0x0 0x0 [ 30.215842] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 30.215844] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00c80000, size: 0x04b00384 [ 30.215846] [drm:intel_dump_pipe_config], ips: 0 [ 30.215848] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 30.215855] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 30.215857] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 30.215862] [drm:ironlake_edp_backlight_off], [ 30.417330] [drm:ironlake_edp_panel_off], Turn eDP power off [ 30.417336] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 30.417341] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 31.262173] [drm:intel_dp_link_down], [ 31.314197] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 31.365853] [drm:intel_update_fbc], no output, disabling [ 31.366444] [drm:ironlake_update_plane], Writing base 005F1000 00000000 0 0 3200 [ 31.366446] [drm:intel_update_fbc], no output, disabling [ 31.366449] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:800x600] [ 31.366451] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 270000 [ 31.366954] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6 [ 31.366956] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6 [ 31.366958] [drm:ironlake_check_srwm], watermark 2: display plane 7, fbc lines 3, cursor 6 [ 31.366960] [drm:ironlake_check_srwm], watermark 3: display plane 29, fbc lines 3, cursor 6 [ 31.366963] [drm:ironlake_edp_pll_on], [ 31.419236] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 31.471251] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 31.471261] [drm:intel_update_fbc], fbc set to per-chip default [ 31.471265] [drm:intel_update_fbc], fbc disabled per module param [ 31.471272] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 31.471278] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 31.471285] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 31.471297] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 31.471303] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 31.673413] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 31.674874] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 31.676337] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000 [ 31.677797] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 31.679256] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 31.680715] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000 [ 31.682170] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 31.683627] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 31.685084] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000 [ 31.686543] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 31.688002] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 31.689459] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000 [ 31.690918] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 31.692377] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 31.693834] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000 [ 31.695292] [drm:intel_dp_start_link_train], too many full retries, give up [ 31.695294] [drm:ironlake_edp_panel_on], Turn eDP power on [ 31.695297] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 31.695301] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 31.695307] [drm:ironlake_wait_panel_on], Wait for panel power on [ 31.695317] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd000b [ 32.102564] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 32.102579] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 32.153590] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000 [ 32.155471] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 32.155917] [drm:ironlake_edp_backlight_on], [ 32.356642] [drm:intel_panel_actually_set_backlight], set backlight PWM = 976 [ 32.372638] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 32.372645] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 32.372648] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 32.372650] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18] [ 32.372653] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 32.372656] [drm:intel_modeset_check_state], [CRTC:3] [ 32.372661] [drm:intel_pipe_config_compare] *ERROR* mismatch in adjusted_mode.flags (expected 0, found 2) [ 32.372719] ------------[ cut here ]------------ [ 32.372760] WARNING: at drivers/gpu/drm/i915/intel_display.c:8190 intel_modeset_check_state+0x904/0x94b [i915]() [ 32.372816] pipe state doesn't match! [ 32.372839] Modules linked in: dm_mod iTCO_wdt iTCO_vendor_support acpi_cpufreq coretemp kvm_intel kvm snd_hda_codec_hdmi microcode pcspkr serio_raw snd_hda_codec_realtek i2c_i801 lpc_ich mfd_core snd_hda_intel snd_hda_codec snd_hwdep snd_pcm snd_page_alloc snd_timer snd soundcore wmi battery ac uvcvideo videobuf2_vmalloc videobuf2_memops videobuf2_core videodev i915 video button drm_kms_helper drm mperf freq_table [ 32.373146] CPU: 0 PID: 3913 Comm: testdisplay Not tainted 3.10.0-rc2_drm-intel-next-queued_ef1b46_20130606_+ #3471 [ 32.373204] Hardware name: ASUSTeK Computer Inc. UX31E/UX31E, BIOS UX31E.211 01/20/2012 [ 32.373249] ffffffff816de142 0000000000000000 ffffffff8102c67d ffff880134e2b920 [ 32.373301] ffff880134e2b928 0000000000000001 ffff88013a3d7000 ffff88013541b800 [ 32.373354] ffff88013a3d76c8 ffff8801357a8000 ffffffff8102c72d ffffffffa00c1d44 [ 32.373406] Call Trace: [ 32.373427] [] ? dump_stack+0xd/0x17 [ 32.373461] [] ? warn_slowpath_common+0x5f/0x77 [ 32.373498] [] ? warn_slowpath_fmt+0x45/0x4a [ 32.373539] [] ? intel_modeset_check_state+0x904/0x94b [i915] [ 32.373587] [] ? intel_set_mode+0x1d/0x27 [i915] [ 32.373635] [] ? intel_crtc_set_config+0x583/0x73b [i915] [ 32.373688] [] ? drm_mode_set_config_internal+0x19/0x40 [drm] [ 32.373751] [] ? drm_mode_setcrtc+0x437/0x4e8 [drm] [ 32.373812] [] ? drm_ioctl+0x290/0x3b5 [drm] [ 32.373862] [] ? drm_mode_setplane+0x30f/0x30f [drm] [ 32.373901] [] ? __schedule+0x60a/0x751 [ 32.373935] [] ? __wake_up+0x35/0x46 [ 32.373968] [] ? vfs_ioctl+0x1e/0x31 [ 32.373999] [] ? do_vfs_ioctl+0x3e9/0x42b [ 32.374033] [] ? SyS_ioctl+0x4e/0x7d [ 32.374065] [] ? system_call_fastpath+0x16/0x1b [ 32.374101] ---[ end trace ee545d65293e034b ]--- [ 32.374129] [drm:intel_dump_pipe_config], [CRTC:3][hw state] config for pipe A [ 32.374131] [drm:intel_dump_pipe_config], cpu_transcoder: A [ 32.374132] [drm:intel_dump_pipe_config], pipe bpp: 0, dithering: 0 [ 32.374134] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 32.374136] [drm:intel_dump_pipe_config], requested mode: [ 32.374137] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 800 0 0 0 600 0 0 0 0x0 0x0 [ 32.374140] [drm:intel_dump_pipe_config], adjusted mode: [ 32.374141] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0xa [ 32.374143] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 32.374145] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00c80000, size: 0x04b00384 [ 32.374147] [drm:intel_dump_pipe_config], ips: 0 [ 32.374148] [drm:intel_dump_pipe_config], [CRTC:3][sw state] config for pipe A [ 32.374150] [drm:intel_dump_pipe_config], cpu_transcoder: A [ 32.374151] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 32.374152] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 32.374154] [drm:intel_dump_pipe_config], requested mode: [ 32.374156] [drm:drm_mode_debug_printmodeline], Modeline 0:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0x0 [ 32.374158] [drm:intel_dump_pipe_config], adjusted mode: [ 32.374159] [drm:drm_mode_debug_printmodeline], Modeline 0:"800x600" 59 97780 1600 1648 1680 1760 900 903 908 926 0x0 0x0 [ 32.374162] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 32.374164] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00c80000, size: 0x04b00384 [ 32.374165] [drm:intel_dump_pipe_config], ips: 0 [ 32.374166] [drm:intel_modeset_check_state], [CRTC:5] [ 32.374178] [drm:drm_mode_getconnector], [CONNECTOR:7:?] [ 32.374180] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1] [ 32.374183] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40000, result 0 [ 32.374185] [drm:intel_crt_detect], CRT not detected via hotplug [ 32.374338] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) [ 32.374340] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga [ 32.374342] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging [ 32.374343] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 [ 32.374701] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga [ 32.374703] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 [ 32.374706] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] [ 32.374709] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1] disconnected [ 32.374714] [drm:drm_mode_getconnector], [CONNECTOR:7:?] [ 32.374717] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1] [ 32.374720] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40000, result 0 [ 32.374722] [drm:intel_crt_detect], CRT not detected via hotplug [ 32.374881] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) [ 32.374884] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga [ 32.374886] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging [ 32.374888] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 [ 32.375240] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga [ 32.375242] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 [ 32.375243] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] [ 32.375245] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1] disconnected [ 32.375251] [drm:drm_mode_getconnector], [CONNECTOR:19:?] [ 32.375253] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:HDMI-A-1] [ 32.375408] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 32.375410] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 32.375411] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:HDMI-A-1] disconnected [ 32.375414] [drm:drm_mode_getconnector], [CONNECTOR:19:?] [ 32.375416] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:HDMI-A-1] [ 32.375565] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 32.375568] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc [ 32.375570] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:HDMI-A-1] disconnected [ 32.375573] [drm:drm_mode_getconnector], [CONNECTOR:21:?] [ 32.375575] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] [ 32.375578] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] disconnected [ 32.375580] [drm:drm_mode_getconnector], [CONNECTOR:21:?] [ 32.375581] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] [ 32.375584] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] disconnected [ 35.103343] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] [ 35.103349] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 35.103351] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 35.103353] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 35.103355] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 35.103358] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 35.103366] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 35.103370] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 35.103373] [drm:ironlake_edp_backlight_off], [ 35.304555] [drm:ironlake_edp_panel_off], Turn eDP power off [ 35.304562] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 35.304567] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 36.175389] [drm:intel_dp_link_down], [ 36.227412] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 36.279065] [drm:intel_update_fbc], no output, disabling [ 36.279074] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 36.279078] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 36.279080] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18] [ 36.279083] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 36.279085] [drm:intel_modeset_check_state], [CRTC:3] [ 36.279086] [drm:intel_modeset_check_state], [CRTC:5] [ 36.279130] [drm:intel_crtc_set_config], [CRTC:3] [FB:12] #connectors=1 (x y) (0 0) [ 36.279133] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 36.279135] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 36.279136] [drm:drm_mode_debug_printmodeline], Modeline 24:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0x0 [ 36.279139] [drm:drm_mode_debug_printmodeline], Modeline 11:"1600x900" 60 97780 1600 1648 1680 1760 900 903 908 926 0x48 0xa [ 36.279142] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 36.279144] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 36.279146] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 36.279148] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 36.279150] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 36.279152] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18 [ 36.279155] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 97780KHz [ 36.279157] [drm:intel_dp_compute_config], DP link bw 0a lane count 1 clock 270000 bpp 18 [ 36.279159] [drm:intel_dp_compute_config], DP link bw required 176004 available 216000 [ 36.279161] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1 [ 36.279163] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A [ 36.279164] [drm:intel_dump_pipe_config], cpu_transcoder: A [ 36.279166] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 36.279167] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 36.279169] [drm:intel_dump_pipe_config], requested mode: [ 36.279171] [drm:drm_mode_debug_printmodeline], Modeline 0:"1600x900" 60 97780 1600 1648 1680 1760 900 903 908 926 0x48 0xa [ 36.279173] [drm:intel_dump_pipe_config], adjusted mode: [ 36.279174] [drm:drm_mode_debug_printmodeline], Modeline 0:"1600x900" 60 97780 1600 1648 1680 1760 900 903 908 926 0x48 0xa [ 36.279177] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 36.279178] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 36.279180] [drm:intel_dump_pipe_config], ips: 0 [ 36.279203] [drm:ironlake_update_plane], Writing base 00072000 00000000 0 0 6400 [ 36.279206] [drm:intel_update_fbc], no output, disabling [ 36.279208] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1600x900] [ 36.279210] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 270000 [ 36.279713] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6 [ 36.279715] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6 [ 36.279718] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6 [ 36.279721] [drm:ironlake_check_srwm], watermark 3: display plane 70, fbc lines 3, cursor 6 [ 36.279728] [drm:ironlake_edp_pll_on], [ 36.331509] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 36.383534] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 36.383545] [drm:intel_update_fbc], fbc set to per-chip default [ 36.383549] [drm:intel_update_fbc], fbc disabled per module param [ 36.383555] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 36.383560] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 36.383566] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 36.383578] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 36.383584] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 36.585660] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 36.587153] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 36.588614] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000 [ 36.590077] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 36.591534] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 36.592989] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000 [ 36.594448] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 36.595906] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 36.597363] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000 [ 36.598824] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 36.600283] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 36.601739] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000 [ 36.603201] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 36.604658] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 36.606141] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000 [ 36.607603] [drm:intel_dp_start_link_train], too many full retries, give up [ 36.607605] [drm:ironlake_edp_panel_on], Turn eDP power on [ 36.607607] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 36.607611] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 36.607618] [drm:ironlake_wait_panel_on], Wait for panel power on [ 36.607621] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd000b [ 37.014825] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 37.014841] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 37.065850] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000 [ 37.067698] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 37.068142] [drm:ironlake_edp_backlight_on], [ 37.268890] [drm:intel_panel_actually_set_backlight], set backlight PWM = 976 [ 37.284893] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 37.284899] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8] [ 37.284902] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9] [ 37.284905] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18] [ 37.284908] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20] [ 37.284911] [drm:intel_modeset_check_state], [CRTC:3] [ 37.284915] [drm:intel_modeset_check_state], [CRTC:5] [ 37.284918] [drm:intel_crtc_set_config], [CRTC:5] [NOFB] [ 37.284921] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]