(process:22407): GLib-CRITICAL **: g_slice_set_config: assertion `sys_page_size == 0' failed -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } ===== SHADER #1 ========================================= FETCH/RS880/R600 ===== ===== 12 dw ===== 3 gprs ===== 0 stack ========================================= 0000 00000002 81000400 VTX 2 @4 0004 7c00a000 88cd1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0008 7c00a000 88cd1002 00080010 VFETCH R2.xyzw, R0.x + 16b , RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_SINT, } ===== SHADER #2 ========================================= FETCH/RS880/R600 ===== ===== 12 dw ===== 3 gprs ===== 0 stack ========================================= 0000 00000002 81000400 VTX 2 @4 0004 7c00a000 88cd1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0008 7c00a000 d88d1002 00080010 VFETCH R2.xyzw, R0.x + 16b , RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:1 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, } ===== SHADER #3 ========================================= FETCH/RS880/R600 ===== ===== 12 dw ===== 3 gprs ===== 0 stack ========================================= 0000 00000002 81000400 VTX 2 @4 0004 7c00a000 88cd1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0008 7c00a000 988d1002 00080010 VFETCH R2.xyzw, R0.x + 16b , RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, } ===== SHADER #4 ========================================= FETCH/RS880/R600 ===== ===== 8 dw ===== 2 gprs ===== 0 stack ========================================== 0000 00000002 81000000 VTX 1 @4 0004 7c00a000 93564001 00080000 VFETCH R1.x001, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:13 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_UINT, } ===== SHADER #5 ========================================= FETCH/RS880/R600 ===== ===== 8 dw ===== 2 gprs ===== 0 stack ========================================== 0000 00000002 81000000 VTX 1 @4 0004 7c00a000 97561001 00080000 VFETCH R1.xy01, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:29 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_UINT, } ===== SHADER #6 ========================================= FETCH/RS880/R600 ===== ===== 8 dw ===== 2 gprs ===== 0 stack ========================================== 0000 00000002 81000000 VTX 1 @4 0004 7c00a000 9bd51001 00080000 VFETCH R1.xyz1, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:47 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, } ===== SHADER #7 ========================================= FETCH/RS880/R600 ===== ===== 8 dw ===== 2 gprs ===== 0 stack ========================================== 0000 00000002 81000000 VTX 1 @4 0004 7c00a000 988d1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) %12 = insertelement <4 x float> undef, float %4, i32 0 %13 = insertelement <4 x float> %12, float %5, i32 1 %14 = insertelement <4 x float> %13, float %6, i32 2 %15 = insertelement <4 x float> %14, float %7, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #8 ============================================ VS/RS880/R600 ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 89800000 CALL_FS @0 0002 c000a03c 94400688 EXPORT_DONE POS 60 R1.xyzw VPM 0004 c0014000 94600688 EXPORT_DONE PARAM 0 R2.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %7, i32 0, i32 0, i32 1) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #9 ============================================ VS/RS880/R600 ===== ===== 12 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 89800000 CALL_FS @0 0002 00008000 90401fff MEM_STREAM0 WRITE 0 R1.x___ ES:0 VPM 0004 c000a03c 94400688 EXPORT_DONE POS 60 R1.xyzw VPM 0006 c0004000 94600fff EXPORT_DONE PARAM 0 R0.____ VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } ===== SHADER #10 =========================================== PS/RS880/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94600fff EXPORT_DONE PIXEL 0 R0.____ VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } ===== SHADER #11 ======================================== FETCH/RS880/R600 ===== ===== 12 dw ===== 3 gprs ===== 0 stack ========================================= 0000 00000002 81000400 VTX 2 @4 0004 7c00a000 88cd1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0008 7c00a000 88cd1002 00080010 VFETCH R2.xyzw, R0.x + 16b , RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_SINT, } ===== SHADER #12 ======================================== FETCH/RS880/R600 ===== ===== 12 dw ===== 3 gprs ===== 0 stack ========================================= 0000 00000002 81000400 VTX 2 @4 0004 7c00a000 88cd1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0008 7c00a000 d88d1002 00080010 VFETCH R2.xyzw, R0.x + 16b , RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:1 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, } ===== SHADER #13 ======================================== FETCH/RS880/R600 ===== ===== 12 dw ===== 3 gprs ===== 0 stack ========================================= 0000 00000002 81000400 VTX 2 @4 0004 7c00a000 88cd1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0008 7c00a000 988d1002 00080010 VFETCH R2.xyzw, R0.x + 16b , RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, } ===== SHADER #14 ======================================== FETCH/RS880/R600 ===== ===== 8 dw ===== 2 gprs ===== 0 stack ========================================== 0000 00000002 81000000 VTX 1 @4 0004 7c00a000 93564001 00080000 VFETCH R1.x001, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:13 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_UINT, } ===== SHADER #15 ======================================== FETCH/RS880/R600 ===== ===== 8 dw ===== 2 gprs ===== 0 stack ========================================== 0000 00000002 81000000 VTX 1 @4 0004 7c00a000 97561001 00080000 VFETCH R1.xy01, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:29 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_UINT, } ===== SHADER #16 ======================================== FETCH/RS880/R600 ===== ===== 8 dw ===== 2 gprs ===== 0 stack ========================================== 0000 00000002 81000000 VTX 1 @4 0004 7c00a000 9bd51001 00080000 VFETCH R1.xyz1, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:47 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, } ===== SHADER #17 ======================================== FETCH/RS880/R600 ===== ===== 8 dw ===== 2 gprs ===== 0 stack ========================================== 0000 00000002 81000000 VTX 1 @4 0004 7c00a000 988d1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) %12 = insertelement <4 x float> undef, float %4, i32 0 %13 = insertelement <4 x float> %12, float %5, i32 1 %14 = insertelement <4 x float> %13, float %6, i32 2 %15 = insertelement <4 x float> %14, float %7, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #18 =========================================== VS/RS880/R600 ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 89800000 CALL_FS @0 0002 c000a03c 94400688 EXPORT_DONE POS 60 R1.xyzw VPM 0004 c0014000 94600688 EXPORT_DONE PARAM 0 R2.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %7, i32 0, i32 0, i32 1) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #19 =========================================== VS/RS880/R600 ===== ===== 12 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 89800000 CALL_FS @0 0002 00008000 90401fff MEM_STREAM0 WRITE 0 R1.x___ ES:0 VPM 0004 c000a03c 94400688 EXPORT_DONE POS 60 R1.xyzw VPM 0006 c0004000 94600fff EXPORT_DONE PARAM 0 R0.____ VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } ===== SHADER #20 =========================================== PS/RS880/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94600fff EXPORT_DONE PIXEL 0 R0.____ VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } ===== SHADER #21 ======================================== FETCH/RS880/R600 ===== ===== 12 dw ===== 3 gprs ===== 0 stack ========================================= 0000 00000002 81000400 VTX 2 @4 0004 7c00a000 88cd1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0008 7c00a000 88cd1002 00080010 VFETCH R2.xyzw, R0.x + 16b , RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_SINT, } ===== SHADER #22 ======================================== FETCH/RS880/R600 ===== ===== 12 dw ===== 3 gprs ===== 0 stack ========================================= 0000 00000002 81000400 VTX 2 @4 0004 7c00a000 88cd1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0008 7c00a000 d88d1002 00080010 VFETCH R2.xyzw, R0.x + 16b , RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:1 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, } ===== SHADER #23 ======================================== FETCH/RS880/R600 ===== ===== 12 dw ===== 3 gprs ===== 0 stack ========================================= 0000 00000002 81000400 VTX 2 @4 0004 7c00a000 88cd1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0008 7c00a000 988d1002 00080010 VFETCH R2.xyzw, R0.x + 16b , RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, } ===== SHADER #24 ======================================== FETCH/RS880/R600 ===== ===== 8 dw ===== 2 gprs ===== 0 stack ========================================== 0000 00000002 81000000 VTX 1 @4 0004 7c00a000 93564001 00080000 VFETCH R1.x001, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:13 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_UINT, } ===== SHADER #25 ======================================== FETCH/RS880/R600 ===== ===== 8 dw ===== 2 gprs ===== 0 stack ========================================== 0000 00000002 81000000 VTX 1 @4 0004 7c00a000 97561001 00080000 VFETCH R1.xy01, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:29 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_UINT, } ===== SHADER #26 ======================================== FETCH/RS880/R600 ===== ===== 8 dw ===== 2 gprs ===== 0 stack ========================================== 0000 00000002 81000000 VTX 1 @4 0004 7c00a000 9bd51001 00080000 VFETCH R1.xyz1, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:47 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, } ===== SHADER #27 ======================================== FETCH/RS880/R600 ===== ===== 8 dw ===== 2 gprs ===== 0 stack ========================================== 0000 00000002 81000000 VTX 1 @4 0004 7c00a000 988d1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) %12 = insertelement <4 x float> undef, float %4, i32 0 %13 = insertelement <4 x float> %12, float %5, i32 1 %14 = insertelement <4 x float> %13, float %6, i32 2 %15 = insertelement <4 x float> %14, float %7, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #28 =========================================== VS/RS880/R600 ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 89800000 CALL_FS @0 0002 c000a03c 94400688 EXPORT_DONE POS 60 R1.xyzw VPM 0004 c0014000 94600688 EXPORT_DONE PARAM 0 R2.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %7, i32 0, i32 0, i32 1) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #29 =========================================== VS/RS880/R600 ===== ===== 12 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 89800000 CALL_FS @0 0002 00008000 90401fff MEM_STREAM0 WRITE 0 R1.x___ ES:0 VPM 0004 c000a03c 94400688 EXPORT_DONE POS 60 R1.xyzw VPM 0006 c0004000 94600fff EXPORT_DONE PARAM 0 R0.____ VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } ===== SHADER #30 =========================================== PS/RS880/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94600fff EXPORT_DONE PIXEL 0 R0.____ VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } ===== SHADER #31 =========================================== PS/RS880/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94600688 EXPORT_DONE PIXEL 0 R0.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV_SAT OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = load <4 x float> addrspace(8)* null %9 = extractelement <4 x float> %8, i32 0 %10 = fmul float %0, %9 %11 = load <4 x float> addrspace(8)* null %12 = extractelement <4 x float> %11, i32 1 %13 = fmul float %0, %12 %14 = load <4 x float> addrspace(8)* null %15 = extractelement <4 x float> %14, i32 2 %16 = fmul float %0, %15 %17 = load <4 x float> addrspace(8)* null %18 = extractelement <4 x float> %17, i32 3 %19 = fmul float %0, %18 %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %21 = extractelement <4 x float> %20, i32 0 %22 = fmul float %1, %21 %23 = fadd float %22, %10 %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %25 = extractelement <4 x float> %24, i32 1 %26 = fmul float %1, %25 %27 = fadd float %26, %13 %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %29 = extractelement <4 x float> %28, i32 2 %30 = fmul float %1, %29 %31 = fadd float %30, %16 %32 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %33 = extractelement <4 x float> %32, i32 3 %34 = fmul float %1, %33 %35 = fadd float %34, %19 %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %37 = extractelement <4 x float> %36, i32 0 %38 = fmul float %2, %37 %39 = fadd float %38, %23 %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %41 = extractelement <4 x float> %40, i32 1 %42 = fmul float %2, %41 %43 = fadd float %42, %27 %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %45 = extractelement <4 x float> %44, i32 2 %46 = fmul float %2, %45 %47 = fadd float %46, %31 %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %49 = extractelement <4 x float> %48, i32 3 %50 = fmul float %2, %49 %51 = fadd float %50, %35 %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %53 = extractelement <4 x float> %52, i32 0 %54 = fmul float %3, %53 %55 = fadd float %54, %39 %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %57 = extractelement <4 x float> %56, i32 1 %58 = fmul float %3, %57 %59 = fadd float %58, %43 %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %61 = extractelement <4 x float> %60, i32 2 %62 = fmul float %3, %61 %63 = fadd float %62, %47 %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %65 = extractelement <4 x float> %64, i32 3 %66 = fmul float %3, %65 %67 = fadd float %66, %51 %68 = call float @llvm.AMDIL.clamp.(float %4, float 0,000000e+00, float 0x3FF0000000000000) %69 = call float @llvm.AMDIL.clamp.(float %5, float 0,000000e+00, float 0x3FF0000000000000) %70 = call float @llvm.AMDIL.clamp.(float %6, float 0,000000e+00, float 0x3FF0000000000000) %71 = call float @llvm.AMDIL.clamp.(float %7, float 0,000000e+00, float 0x3FF0000000000000) %72 = insertelement <4 x float> undef, float %55, i32 0 %73 = insertelement <4 x float> %72, float %59, i32 1 %74 = insertelement <4 x float> %73, float %63, i32 2 %75 = insertelement <4 x float> %74, float %67, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %75, i32 60, i32 1) %76 = insertelement <4 x float> undef, float %68, i32 0 %77 = insertelement <4 x float> %76, float %69, i32 1 %78 = insertelement <4 x float> %77, float %70, i32 2 %79 = insertelement <4 x float> %78, float %71, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %79, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #32 =========================================== VS/RS880/R600 ===== ===== 52 dw ===== 5 gprs ===== 1 stack ========================================= 0000 00000000 89800000 CALL_FS @0 0002 80000006 a04c0000 ALU 20 @12 KC0[CB0:0-31] 0012 81100001 60000210 1 w: MUL_IEEE R0.w, R1.x, KC0[0].z 0014 01102401 40028cfe 2 z: MULADD_IEEE R0.z, R1.y, KC0[1].z, PV.w 0016 80100001 60000210 w: MUL_IEEE R0.w, R1.x, KC0[0].x 0018 00102401 40628cfe 3 z: MULADD_IEEE R3.z, R1.y, KC0[1].x, PV.w 0020 81104801 600288fe w: MULADD_IEEE R0.w, R1.z, KC0[2].z, PV.z 0022 01106c01 40028cfe 4 z: MULADD_IEEE R0.z, R1.w, KC0[3].z, PV.w 0024 80104801 606288fe w: MULADD_IEEE R3.w, R1.z, KC0[2].x, PV.z 0026 00106c01 00028cfe 5 x: MULADD_IEEE R0.x, R1.w, KC0[3].x, PV.w 0028 80900001 60800210 w: MUL_IEEE R4.w, R1.x, KC0[0].y 0030 00000002 80601910 6 x: MOV_sat R3.x, R2.x 0032 00902401 40828cfe z: MULADD_IEEE R4.z, R1.y, KC0[1].y, PV.w 0034 81900001 60880210 w: MUL_IEEE R4.w, R1.x, KC0[0].w VEC_120 0036 01902401 20228cfe 7 y: MULADD_IEEE R1.y, R1.y, KC0[1].w, PV.w 0038 00904801 408288fe z: MULADD_IEEE R4.z, R1.z, KC0[2].y, PV.z 0040 80000c02 e0601910 w: MOV_sat R3.w, R2.w 0042 00906c01 200288fe 8 y: MULADD_IEEE R0.y, R1.w, KC0[3].y, PV.z 0044 00000802 c0601910 z: MOV_sat R3.z, R2.z 0046 81904801 604a84fe w: MULADD_IEEE R2.w, R1.z, KC0[2].w, PV.y VEC_120 0048 00000402 a0601910 9 y: MOV_sat R3.y, R2.y 0050 81906c01 60028cfe w: MULADD_IEEE R0.w, R1.w, KC0[3].w, PV.w 0004 c000203c 94400688 EXPORT_DONE POS 60 R0.xyzw VPM 0006 c001c000 94600688 EXPORT_DONE PARAM 0 R3.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } ===== SHADER #33 =========================================== PS/RS880/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94600688 EXPORT_DONE PIXEL 0 R0.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 %8 = extractelement <4 x float> %7, i32 0 %9 = extractelement <4 x float> %7, i32 1 %10 = insertelement <4 x float> undef, float %8, i32 0 %11 = insertelement <4 x float> %10, float %9, i32 1 %12 = insertelement <4 x float> %11, float undef, i32 2 %13 = insertelement <4 x float> %12, float undef, i32 3 %14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %13, i32 16, i32 0, i32 2) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = insertelement <4 x float> undef, float %15, i32 0 %20 = insertelement <4 x float> %19, float %16, i32 1 %21 = insertelement <4 x float> %20, float %17, i32 2 %22 = insertelement <4 x float> %21, float %18, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %22, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } ===== SHADER #34 =========================================== PS/RS880/R600 ===== ===== 12 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000004 80800000 TEX 1 @8 0008 00001010 f00d1000 68800000 SAMPLE R0.xyzw, R0.xyzw, RID:16, SID:0 CT:NNNN 0002 c0000000 94600688 EXPORT_DONE PIXEL 0 R0.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } ===== SHADER #35 ======================================== FETCH/RS880/R600 ===== ===== 12 dw ===== 3 gprs ===== 0 stack ========================================= 0000 00000002 81000400 VTX 2 @4 0004 7c00a000 88cd1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0008 7c00a000 88cd1002 00080010 VFETCH R2.xyzw, R0.x + 16b , RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } ===== SHADER #36 =========================================== PS/RS880/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94600688 EXPORT_DONE PIXEL 0 R0.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) %12 = insertelement <4 x float> undef, float %4, i32 0 %13 = insertelement <4 x float> %12, float %5, i32 1 %14 = insertelement <4 x float> %13, float %6, i32 2 %15 = insertelement <4 x float> %14, float %7, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #37 =========================================== VS/RS880/R600 ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 89800000 CALL_FS @0 0002 c000a03c 94400688 EXPORT_DONE POS 60 R1.xyzw VPM 0004 c0014000 94600688 EXPORT_DONE PARAM 0 R2.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[19], PERSPECTIVE DCL OUT[0], COLOR DCL CONST[0] DCL TEMP[0..1], LOCAL IMM[0] FLT32 {16777216,0000, 65536,0000, 256,0000, 1,0000} IMM[1] FLT32 { 0,0000, 0,0039, 0,0000, 0,0000} 0: ABS TEMP[0].x, IN[0].yyyy 1: RCP TEMP[1].x, CONST[0].xxxx 2: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx 3: MUL TEMP[0], TEMP[0].xxxx, IMM[0] 4: FRC TEMP[0], TEMP[0] 5: MUL TEMP[1], TEMP[0].xxyz, IMM[1].xyyy 6: ADD TEMP[0], TEMP[0], -TEMP[1] 7: MOV OUT[0], TEMP[0] 8: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = call float @fabs(float %1) %5 = load <4 x float> addrspace(8)* null %6 = extractelement <4 x float> %5, i32 0 %7 = fdiv float 0x3FF0000000000000, %6 %8 = fmul float %4, %7 %9 = fmul float %8, 0x4170000000000000 %10 = fmul float %8, 0x40F0000000000000 %11 = fmul float %8, 0x4070000000000000 %12 = fmul float %8, 0x3FF0000000000000 %13 = call float @llvm.AMDIL.fraction.(float %9) %14 = call float @llvm.AMDIL.fraction.(float %10) %15 = call float @llvm.AMDIL.fraction.(float %11) %16 = call float @llvm.AMDIL.fraction.(float %12) %17 = fmul float %13, 0,000000e+00 %18 = fmul float %13, 0x3F70000000000000 %19 = fmul float %14, 0x3F70000000000000 %20 = fmul float %15, 0x3F70000000000000 %21 = fsub float -0,000000e+00, %17 %22 = fadd float %13, %21 %23 = fsub float -0,000000e+00, %18 %24 = fadd float %14, %23 %25 = fsub float -0,000000e+00, %19 %26 = fadd float %15, %25 %27 = fsub float -0,000000e+00, %20 %28 = fadd float %16, %27 %29 = insertelement <4 x float> undef, float %22, i32 0 %30 = insertelement <4 x float> %29, float %24, i32 1 %31 = insertelement <4 x float> %30, float %26, i32 2 %32 = insertelement <4 x float> %31, float %28, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %32, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } ===== SHADER #38 =========================================== PS/RS880/R600 ===== ===== 44 dw ===== 4 gprs ===== 0 stack ========================================= 0000 80000004 a0440000 ALU 18 @8 KC0[CB0:0-31] 0008 80000080 60006610 1 t: RECIP_IEEE R0.w, KC0[0].x 0010 81800400 60200211 2 w: MUL_IEEE R1.w, |R0.y|, R0.w 0012 001facfe 40000210 3 z: MUL_IEEE R0.z, PV.w, [0x47800000 65536].x 0014 809facfe 60000210 w: MUL_IEEE R0.w, PV.w, [0x4b800000 1,67772e+07].y 0016 47800000 0017 4b800000 0018 001fac01 20200210 4 y: MUL_IEEE R1.y, R1.w, [0x43800000 256].x 0020 00000cfe 40281010 z: FRACT R1.z, PV.w VEC_120 0022 800008fe 60401010 w: FRACT R2.w, PV.z 0024 43800000 0026 001fa8fe 20028cfe 5 y: MULADD_IEEE R0.y, PV.z, [0xbb800000 -0,00390625].x, PV.w 0028 800004fe 60601010 w: FRACT R3.w, PV.y 0030 bb800000 0032 001fac02 40028cfe 6 z: MULADD_IEEE R0.z, R2.w, [0xbb800000 -0,00390625].x, PV.w 0034 80000c01 60281010 w: FRACT R1.w, R1.w VEC_120 0036 bb800000 0038 801fac03 60028cfe 7 w: MULADD_IEEE R0.w, R3.w, [0xbb800000 -0,00390625].x, PV.w 0040 bb800000 0042 801f0801 00028801 8 x: MULADD_IEEE R0.x, R1.z, 0, R1.z 0002 c0000000 94600688 EXPORT_DONE PIXEL 0 R0.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[19] DCL CONST[0..7] DCL TEMP[0..1], LOCAL 0: MUL TEMP[0], CONST[0], IN[0].xxxx 1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0] 3: ADD TEMP[0], TEMP[0], CONST[3] 4: MUL TEMP[1], CONST[4], TEMP[0].xxxx 5: MAD TEMP[1], CONST[5], TEMP[0].yyyy, TEMP[1] 6: MAD TEMP[1], CONST[6], TEMP[0].zzzz, TEMP[1] 7: MAD TEMP[1], CONST[7], TEMP[0].wwww, TEMP[1] 8: MOV OUT[1], TEMP[0] 9: MOV OUT[0], TEMP[1] 10: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = load <4 x float> addrspace(8)* null %5 = extractelement <4 x float> %4, i32 0 %6 = fmul float %5, %0 %7 = load <4 x float> addrspace(8)* null %8 = extractelement <4 x float> %7, i32 1 %9 = fmul float %8, %0 %10 = load <4 x float> addrspace(8)* null %11 = extractelement <4 x float> %10, i32 2 %12 = fmul float %11, %0 %13 = load <4 x float> addrspace(8)* null %14 = extractelement <4 x float> %13, i32 3 %15 = fmul float %14, %0 %16 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %17 = extractelement <4 x float> %16, i32 0 %18 = fmul float %17, %1 %19 = fadd float %18, %6 %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %21 = extractelement <4 x float> %20, i32 1 %22 = fmul float %21, %1 %23 = fadd float %22, %9 %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %25 = extractelement <4 x float> %24, i32 2 %26 = fmul float %25, %1 %27 = fadd float %26, %12 %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %29 = extractelement <4 x float> %28, i32 3 %30 = fmul float %29, %1 %31 = fadd float %30, %15 %32 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %33 = extractelement <4 x float> %32, i32 0 %34 = fmul float %33, %2 %35 = fadd float %34, %19 %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %37 = extractelement <4 x float> %36, i32 1 %38 = fmul float %37, %2 %39 = fadd float %38, %23 %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %41 = extractelement <4 x float> %40, i32 2 %42 = fmul float %41, %2 %43 = fadd float %42, %27 %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %45 = extractelement <4 x float> %44, i32 3 %46 = fmul float %45, %2 %47 = fadd float %46, %31 %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %49 = extractelement <4 x float> %48, i32 0 %50 = fadd float %35, %49 %51 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %52 = extractelement <4 x float> %51, i32 1 %53 = fadd float %39, %52 %54 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %55 = extractelement <4 x float> %54, i32 2 %56 = fadd float %43, %55 %57 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %58 = extractelement <4 x float> %57, i32 3 %59 = fadd float %47, %58 %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %61 = extractelement <4 x float> %60, i32 0 %62 = fmul float %61, %50 %63 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %64 = extractelement <4 x float> %63, i32 1 %65 = fmul float %64, %50 %66 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %67 = extractelement <4 x float> %66, i32 2 %68 = fmul float %67, %50 %69 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %70 = extractelement <4 x float> %69, i32 3 %71 = fmul float %70, %50 %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %73 = extractelement <4 x float> %72, i32 0 %74 = fmul float %73, %53 %75 = fadd float %74, %62 %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %77 = extractelement <4 x float> %76, i32 1 %78 = fmul float %77, %53 %79 = fadd float %78, %65 %80 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %81 = extractelement <4 x float> %80, i32 2 %82 = fmul float %81, %53 %83 = fadd float %82, %68 %84 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %85 = extractelement <4 x float> %84, i32 3 %86 = fmul float %85, %53 %87 = fadd float %86, %71 %88 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %89 = extractelement <4 x float> %88, i32 0 %90 = fmul float %89, %56 %91 = fadd float %90, %75 %92 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %93 = extractelement <4 x float> %92, i32 1 %94 = fmul float %93, %56 %95 = fadd float %94, %79 %96 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %97 = extractelement <4 x float> %96, i32 2 %98 = fmul float %97, %56 %99 = fadd float %98, %83 %100 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %101 = extractelement <4 x float> %100, i32 3 %102 = fmul float %101, %56 %103 = fadd float %102, %87 %104 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %105 = extractelement <4 x float> %104, i32 0 %106 = fmul float %105, %59 %107 = fadd float %106, %91 %108 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %109 = extractelement <4 x float> %108, i32 1 %110 = fmul float %109, %59 %111 = fadd float %110, %95 %112 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %113 = extractelement <4 x float> %112, i32 2 %114 = fmul float %113, %59 %115 = fadd float %114, %99 %116 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %117 = extractelement <4 x float> %116, i32 3 %118 = fmul float %117, %59 %119 = fadd float %118, %103 %120 = insertelement <4 x float> undef, float %107, i32 0 %121 = insertelement <4 x float> %120, float %111, i32 1 %122 = insertelement <4 x float> %121, float %115, i32 2 %123 = insertelement <4 x float> %122, float %119, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %123, i32 60, i32 1) %124 = insertelement <4 x float> undef, float %50, i32 0 %125 = insertelement <4 x float> %124, float %53, i32 1 %126 = insertelement <4 x float> %125, float %56, i32 2 %127 = insertelement <4 x float> %126, float %59, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %127, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #39 =========================================== VS/RS880/R600 ===== ===== 76 dw ===== 5 gprs ===== 1 stack ========================================= 0000 00000000 89800000 CALL_FS @0 0002 80000006 a07c0000 ALU 32 @12 KC0[CB0:0-31] 0012 80002080 60000210 1 w: MUL_IEEE R0.w, KC0[0].x, R1.x 0014 00802081 40028cfe 2 z: MULADD_IEEE R0.z, KC0[1].x, R1.y, PV.w 0016 80002480 60000210 w: MUL_IEEE R0.w, KC0[0].y, R1.x 0018 00802481 40428cfe 3 z: MULADD_IEEE R2.z, KC0[1].y, R1.y, PV.w 0020 81002082 600288fe w: MULADD_IEEE R0.w, KC0[2].x, R1.z, PV.z 0022 00106cfe 00000010 4 x: ADD R0.x, PV.w, KC0[3].x 0024 81002482 602288fe w: MULADD_IEEE R1.w, KC0[2].y, R1.z, PV.z 0026 001fcc84 00400210 5 x: MUL_IEEE R2.x, KC0[4].w, PV.x 0028 001fc084 20400210 y: MUL_IEEE R2.y, KC0[4].x, PV.x 0030 001fc484 40400210 z: MUL_IEEE R2.z, KC0[4].y, PV.x 0032 801fc884 60400210 w: MUL_IEEE R2.w, KC0[4].z, PV.x 0034 00906c01 20000010 6 y: ADD R0.y, R1.w, KC0[3].y 0036 80002880 60200210 w: MUL_IEEE R1.w, KC0[0].z, R1.x 0038 00802881 40828cfe 7 z: MULADD_IEEE R4.z, KC0[1].z, R1.y, PV.w 0040 80002c80 60200210 w: MUL_IEEE R1.w, KC0[0].w, R1.x 0042 00802c81 40628cfe 8 z: MULADD_IEEE R3.z, KC0[1].w, R1.y, PV.w 0044 81002882 606288fe w: MULADD_IEEE R3.w, KC0[2].z, R1.z, PV.z 0046 00800885 00228c02 9 x: MULADD_IEEE R1.x, KC0[5].z, R0.y, R2.w 0048 00800085 20228402 y: MULADD_IEEE R1.y, KC0[5].x, R0.y, R2.y 0050 00800485 40428802 z: MULADD_IEEE R2.z, KC0[5].y, R0.y, R2.z 0052 80800c85 60228002 w: MULADD_IEEE R1.w, KC0[5].w, R0.y, R2.x 0054 01106c03 40000010 10 z: ADD R0.z, R3.w, KC0[3].z 0056 81002c82 60428803 w: MULADD_IEEE R2.w, KC0[2].w, R1.z, R3.z 0058 011fc886 00228001 11 x: MULADD_IEEE R1.x, KC0[6].z, PV.z, R1.x 0060 011fc086 20228401 y: MULADD_IEEE R1.y, KC0[6].x, PV.z, R1.y 0062 011fc486 40228802 z: MULADD_IEEE R1.z, KC0[6].y, PV.z, R2.z 0064 811fcc86 60228c01 w: MULADD_IEEE R1.w, KC0[6].w, PV.z, R1.w 0066 81906c02 60000010 12 w: ADD R0.w, R2.w, KC0[3].w 0068 819fcc87 60428c01 13 w: MULADD_IEEE R2.w, KC0[7].w, PV.w, R1.w 0070 81800487 20428801 14 y: MULADD_IEEE R2.y, KC0[7].y, R0.w, R1.z 0072 01800087 00428401 15 x: MULADD_IEEE R2.x, KC0[7].x, R0.w, R1.y 0074 81800887 40428001 z: MULADD_IEEE R2.z, KC0[7].z, R0.w, R1.x 0004 c001203c 94400688 EXPORT_DONE POS 60 R2.xyzw VPM 0006 c0004000 94600688 EXPORT_DONE PARAM 0 R0.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_FLOAT, } ===== SHADER #40 ======================================== FETCH/RS880/R600 ===== ===== 8 dw ===== 2 gprs ===== 0 stack ========================================== 0000 00000002 81000000 VTX 1 @4 0004 7c00a000 8c151001 00080000 VFETCH R1.xyz1, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:48 NUM:0 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 %8 = extractelement <4 x float> %7, i32 0 %9 = extractelement <4 x float> %7, i32 1 %10 = insertelement <4 x float> undef, float %8, i32 0 %11 = insertelement <4 x float> %10, float %9, i32 1 %12 = insertelement <4 x float> %11, float undef, i32 2 %13 = insertelement <4 x float> %12, float undef, i32 3 %14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %13, i32 16, i32 0, i32 2) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = insertelement <4 x float> undef, float %15, i32 0 %20 = insertelement <4 x float> %19, float %16, i32 1 %21 = insertelement <4 x float> %20, float %17, i32 2 %22 = insertelement <4 x float> %21, float %18, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %22, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } ===== SHADER #41 =========================================== PS/RS880/R600 ===== ===== 12 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000004 80800000 TEX 1 @8 0008 00001010 f00d1000 68800000 SAMPLE R0.xyzw, R0.xyzw, RID:16, SID:0 CT:NNNN 0002 c0000000 94600688 EXPORT_DONE PIXEL 0 R0.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) %12 = insertelement <4 x float> undef, float %4, i32 0 %13 = insertelement <4 x float> %12, float %5, i32 1 %14 = insertelement <4 x float> %13, float %6, i32 2 %15 = insertelement <4 x float> %14, float %7, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #42 =========================================== VS/RS880/R600 ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 89800000 CALL_FS @0 0002 c000a03c 94400688 EXPORT_DONE POS 60 R1.xyzw VPM 0004 c0014000 94600688 EXPORT_DONE PARAM 0 R2.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[19], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float 0,000000e+00, i32 2 %7 = insertelement <4 x float> %6, float 0,000000e+00, i32 3 %8 = extractelement <4 x float> %7, i32 0 %9 = extractelement <4 x float> %7, i32 1 %10 = insertelement <4 x float> undef, float %8, i32 0 %11 = insertelement <4 x float> %10, float %9, i32 1 %12 = insertelement <4 x float> %11, float undef, i32 2 %13 = insertelement <4 x float> %12, float undef, i32 3 %14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %13, i32 16, i32 0, i32 2) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = insertelement <4 x float> undef, float %15, i32 0 %20 = insertelement <4 x float> %19, float %16, i32 1 %21 = insertelement <4 x float> %20, float %17, i32 2 %22 = insertelement <4 x float> %21, float %18, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %22, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } ===== SHADER #43 =========================================== PS/RS880/R600 ===== ===== 12 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000004 80800000 TEX 1 @8 0008 00001010 f00d1000 68800000 SAMPLE R0.xyzw, R0.xyzw, RID:16, SID:0 CT:NNNN 0002 c0000000 94600688 EXPORT_DONE PIXEL 0 R0.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[19] DCL CONST[0..11] DCL TEMP[0..6], LOCAL 0: MUL TEMP[0], CONST[4], CONST[8].xxxx 1: MAD TEMP[0], CONST[5], CONST[8].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[6], CONST[8].zzzz, TEMP[0] 3: MAD TEMP[0], CONST[7], CONST[8].wwww, TEMP[0] 4: MUL TEMP[1], CONST[4], CONST[9].xxxx 5: MAD TEMP[1], CONST[5], CONST[9].yyyy, TEMP[1] 6: MAD TEMP[1], CONST[6], CONST[9].zzzz, TEMP[1] 7: MAD TEMP[1], CONST[7], CONST[9].wwww, TEMP[1] 8: MUL TEMP[2], CONST[4], CONST[10].xxxx 9: MAD TEMP[2], CONST[5], CONST[10].yyyy, TEMP[2] 10: MAD TEMP[2], CONST[6], CONST[10].zzzz, TEMP[2] 11: MAD TEMP[2], CONST[7], CONST[10].wwww, TEMP[2] 12: MUL TEMP[3], CONST[4], CONST[11].xxxx 13: MAD TEMP[3], CONST[5], CONST[11].yyyy, TEMP[3] 14: MAD TEMP[3], CONST[6], CONST[11].zzzz, TEMP[3] 15: MAD TEMP[3], CONST[7], CONST[11].wwww, TEMP[3] 16: MUL TEMP[4], TEMP[0], CONST[2].xxxx 17: MAD TEMP[4], TEMP[1], CONST[2].yyyy, TEMP[4] 18: MAD TEMP[4], TEMP[2], CONST[2].zzzz, TEMP[4] 19: MAD TEMP[4], TEMP[3], CONST[2].wwww, TEMP[4] 20: MUL TEMP[5], TEMP[0], CONST[1].xxxx 21: MAD TEMP[5], TEMP[1], CONST[1].yyyy, TEMP[5] 22: MAD TEMP[5], TEMP[2], CONST[1].zzzz, TEMP[5] 23: MAD TEMP[5], TEMP[3], CONST[1].wwww, TEMP[5] 24: MUL TEMP[6], TEMP[0], CONST[0].xxxx 25: MAD TEMP[6], TEMP[1], CONST[0].yyyy, TEMP[6] 26: MAD TEMP[6], TEMP[2], CONST[0].zzzz, TEMP[6] 27: MAD TEMP[6], TEMP[3], CONST[0].wwww, TEMP[6] 28: MUL TEMP[6], TEMP[6], IN[1].xxxx 29: MAD TEMP[5], TEMP[5], IN[1].yyyy, TEMP[6] 30: MAD TEMP[4], TEMP[4], IN[1].zzzz, TEMP[5] 31: MUL TEMP[0], TEMP[0], CONST[3].xxxx 32: MAD TEMP[0], TEMP[1], CONST[3].yyyy, TEMP[0] 33: MAD TEMP[0], TEMP[2], CONST[3].zzzz, TEMP[0] 34: MAD TEMP[0], TEMP[3], CONST[3].wwww, TEMP[0] 35: ADD TEMP[0], TEMP[4], TEMP[0] 36: MOV TEMP[1].xy, IN[0].xyxx 37: MOV OUT[0], TEMP[0] 38: MOV OUT[1], TEMP[1] 39: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %9 = extractelement <4 x float> %8, i32 0 %10 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %11 = extractelement <4 x float> %10, i32 0 %12 = fmul float %9, %11 %13 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %14 = extractelement <4 x float> %13, i32 1 %15 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %16 = extractelement <4 x float> %15, i32 0 %17 = fmul float %14, %16 %18 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %19 = extractelement <4 x float> %18, i32 2 %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %21 = extractelement <4 x float> %20, i32 0 %22 = fmul float %19, %21 %23 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %24 = extractelement <4 x float> %23, i32 3 %25 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %26 = extractelement <4 x float> %25, i32 0 %27 = fmul float %24, %26 %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %29 = extractelement <4 x float> %28, i32 0 %30 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %31 = extractelement <4 x float> %30, i32 1 %32 = fmul float %29, %31 %33 = fadd float %32, %12 %34 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %35 = extractelement <4 x float> %34, i32 1 %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %37 = extractelement <4 x float> %36, i32 1 %38 = fmul float %35, %37 %39 = fadd float %38, %17 %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %41 = extractelement <4 x float> %40, i32 2 %42 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %43 = extractelement <4 x float> %42, i32 1 %44 = fmul float %41, %43 %45 = fadd float %44, %22 %46 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %47 = extractelement <4 x float> %46, i32 3 %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %49 = extractelement <4 x float> %48, i32 1 %50 = fmul float %47, %49 %51 = fadd float %50, %27 %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %53 = extractelement <4 x float> %52, i32 0 %54 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %55 = extractelement <4 x float> %54, i32 2 %56 = fmul float %53, %55 %57 = fadd float %56, %33 %58 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %59 = extractelement <4 x float> %58, i32 1 %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %61 = extractelement <4 x float> %60, i32 2 %62 = fmul float %59, %61 %63 = fadd float %62, %39 %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %65 = extractelement <4 x float> %64, i32 2 %66 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %67 = extractelement <4 x float> %66, i32 2 %68 = fmul float %65, %67 %69 = fadd float %68, %45 %70 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %71 = extractelement <4 x float> %70, i32 3 %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %73 = extractelement <4 x float> %72, i32 2 %74 = fmul float %71, %73 %75 = fadd float %74, %51 %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %77 = extractelement <4 x float> %76, i32 0 %78 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %79 = extractelement <4 x float> %78, i32 3 %80 = fmul float %77, %79 %81 = fadd float %80, %57 %82 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %83 = extractelement <4 x float> %82, i32 1 %84 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %85 = extractelement <4 x float> %84, i32 3 %86 = fmul float %83, %85 %87 = fadd float %86, %63 %88 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %89 = extractelement <4 x float> %88, i32 2 %90 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %91 = extractelement <4 x float> %90, i32 3 %92 = fmul float %89, %91 %93 = fadd float %92, %69 %94 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %95 = extractelement <4 x float> %94, i32 3 %96 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %97 = extractelement <4 x float> %96, i32 3 %98 = fmul float %95, %97 %99 = fadd float %98, %75 %100 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %101 = extractelement <4 x float> %100, i32 0 %102 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %103 = extractelement <4 x float> %102, i32 0 %104 = fmul float %101, %103 %105 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %106 = extractelement <4 x float> %105, i32 1 %107 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %108 = extractelement <4 x float> %107, i32 0 %109 = fmul float %106, %108 %110 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %111 = extractelement <4 x float> %110, i32 2 %112 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %113 = extractelement <4 x float> %112, i32 0 %114 = fmul float %111, %113 %115 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %116 = extractelement <4 x float> %115, i32 3 %117 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %118 = extractelement <4 x float> %117, i32 0 %119 = fmul float %116, %118 %120 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %121 = extractelement <4 x float> %120, i32 0 %122 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %123 = extractelement <4 x float> %122, i32 1 %124 = fmul float %121, %123 %125 = fadd float %124, %104 %126 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %127 = extractelement <4 x float> %126, i32 1 %128 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %129 = extractelement <4 x float> %128, i32 1 %130 = fmul float %127, %129 %131 = fadd float %130, %109 %132 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %133 = extractelement <4 x float> %132, i32 2 %134 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %135 = extractelement <4 x float> %134, i32 1 %136 = fmul float %133, %135 %137 = fadd float %136, %114 %138 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %139 = extractelement <4 x float> %138, i32 3 %140 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %141 = extractelement <4 x float> %140, i32 1 %142 = fmul float %139, %141 %143 = fadd float %142, %119 %144 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %145 = extractelement <4 x float> %144, i32 0 %146 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %147 = extractelement <4 x float> %146, i32 2 %148 = fmul float %145, %147 %149 = fadd float %148, %125 %150 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %151 = extractelement <4 x float> %150, i32 1 %152 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %153 = extractelement <4 x float> %152, i32 2 %154 = fmul float %151, %153 %155 = fadd float %154, %131 %156 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %157 = extractelement <4 x float> %156, i32 2 %158 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %159 = extractelement <4 x float> %158, i32 2 %160 = fmul float %157, %159 %161 = fadd float %160, %137 %162 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %163 = extractelement <4 x float> %162, i32 3 %164 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %165 = extractelement <4 x float> %164, i32 2 %166 = fmul float %163, %165 %167 = fadd float %166, %143 %168 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %169 = extractelement <4 x float> %168, i32 0 %170 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %171 = extractelement <4 x float> %170, i32 3 %172 = fmul float %169, %171 %173 = fadd float %172, %149 %174 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %175 = extractelement <4 x float> %174, i32 1 %176 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %177 = extractelement <4 x float> %176, i32 3 %178 = fmul float %175, %177 %179 = fadd float %178, %155 %180 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %181 = extractelement <4 x float> %180, i32 2 %182 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %183 = extractelement <4 x float> %182, i32 3 %184 = fmul float %181, %183 %185 = fadd float %184, %161 %186 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %187 = extractelement <4 x float> %186, i32 3 %188 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %189 = extractelement <4 x float> %188, i32 3 %190 = fmul float %187, %189 %191 = fadd float %190, %167 %192 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %193 = extractelement <4 x float> %192, i32 0 %194 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %195 = extractelement <4 x float> %194, i32 0 %196 = fmul float %193, %195 %197 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %198 = extractelement <4 x float> %197, i32 1 %199 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %200 = extractelement <4 x float> %199, i32 0 %201 = fmul float %198, %200 %202 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %203 = extractelement <4 x float> %202, i32 2 %204 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %205 = extractelement <4 x float> %204, i32 0 %206 = fmul float %203, %205 %207 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %208 = extractelement <4 x float> %207, i32 3 %209 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %210 = extractelement <4 x float> %209, i32 0 %211 = fmul float %208, %210 %212 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %213 = extractelement <4 x float> %212, i32 0 %214 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %215 = extractelement <4 x float> %214, i32 1 %216 = fmul float %213, %215 %217 = fadd float %216, %196 %218 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %219 = extractelement <4 x float> %218, i32 1 %220 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %221 = extractelement <4 x float> %220, i32 1 %222 = fmul float %219, %221 %223 = fadd float %222, %201 %224 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %225 = extractelement <4 x float> %224, i32 2 %226 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %227 = extractelement <4 x float> %226, i32 1 %228 = fmul float %225, %227 %229 = fadd float %228, %206 %230 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %231 = extractelement <4 x float> %230, i32 3 %232 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %233 = extractelement <4 x float> %232, i32 1 %234 = fmul float %231, %233 %235 = fadd float %234, %211 %236 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %237 = extractelement <4 x float> %236, i32 0 %238 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %239 = extractelement <4 x float> %238, i32 2 %240 = fmul float %237, %239 %241 = fadd float %240, %217 %242 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %243 = extractelement <4 x float> %242, i32 1 %244 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %245 = extractelement <4 x float> %244, i32 2 %246 = fmul float %243, %245 %247 = fadd float %246, %223 %248 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %249 = extractelement <4 x float> %248, i32 2 %250 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %251 = extractelement <4 x float> %250, i32 2 %252 = fmul float %249, %251 %253 = fadd float %252, %229 %254 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %255 = extractelement <4 x float> %254, i32 3 %256 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %257 = extractelement <4 x float> %256, i32 2 %258 = fmul float %255, %257 %259 = fadd float %258, %235 %260 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %261 = extractelement <4 x float> %260, i32 0 %262 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %263 = extractelement <4 x float> %262, i32 3 %264 = fmul float %261, %263 %265 = fadd float %264, %241 %266 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %267 = extractelement <4 x float> %266, i32 1 %268 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %269 = extractelement <4 x float> %268, i32 3 %270 = fmul float %267, %269 %271 = fadd float %270, %247 %272 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %273 = extractelement <4 x float> %272, i32 2 %274 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %275 = extractelement <4 x float> %274, i32 3 %276 = fmul float %273, %275 %277 = fadd float %276, %253 %278 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %279 = extractelement <4 x float> %278, i32 3 %280 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %281 = extractelement <4 x float> %280, i32 3 %282 = fmul float %279, %281 %283 = fadd float %282, %259 %284 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %285 = extractelement <4 x float> %284, i32 0 %286 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %287 = extractelement <4 x float> %286, i32 0 %288 = fmul float %285, %287 %289 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %290 = extractelement <4 x float> %289, i32 1 %291 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %292 = extractelement <4 x float> %291, i32 0 %293 = fmul float %290, %292 %294 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %295 = extractelement <4 x float> %294, i32 2 %296 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %297 = extractelement <4 x float> %296, i32 0 %298 = fmul float %295, %297 %299 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %300 = extractelement <4 x float> %299, i32 3 %301 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %302 = extractelement <4 x float> %301, i32 0 %303 = fmul float %300, %302 %304 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %305 = extractelement <4 x float> %304, i32 0 %306 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %307 = extractelement <4 x float> %306, i32 1 %308 = fmul float %305, %307 %309 = fadd float %308, %288 %310 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %311 = extractelement <4 x float> %310, i32 1 %312 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %313 = extractelement <4 x float> %312, i32 1 %314 = fmul float %311, %313 %315 = fadd float %314, %293 %316 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %317 = extractelement <4 x float> %316, i32 2 %318 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %319 = extractelement <4 x float> %318, i32 1 %320 = fmul float %317, %319 %321 = fadd float %320, %298 %322 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %323 = extractelement <4 x float> %322, i32 3 %324 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %325 = extractelement <4 x float> %324, i32 1 %326 = fmul float %323, %325 %327 = fadd float %326, %303 %328 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %329 = extractelement <4 x float> %328, i32 0 %330 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %331 = extractelement <4 x float> %330, i32 2 %332 = fmul float %329, %331 %333 = fadd float %332, %309 %334 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %335 = extractelement <4 x float> %334, i32 1 %336 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %337 = extractelement <4 x float> %336, i32 2 %338 = fmul float %335, %337 %339 = fadd float %338, %315 %340 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %341 = extractelement <4 x float> %340, i32 2 %342 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %343 = extractelement <4 x float> %342, i32 2 %344 = fmul float %341, %343 %345 = fadd float %344, %321 %346 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %347 = extractelement <4 x float> %346, i32 3 %348 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %349 = extractelement <4 x float> %348, i32 2 %350 = fmul float %347, %349 %351 = fadd float %350, %327 %352 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %353 = extractelement <4 x float> %352, i32 0 %354 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %355 = extractelement <4 x float> %354, i32 3 %356 = fmul float %353, %355 %357 = fadd float %356, %333 %358 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %359 = extractelement <4 x float> %358, i32 1 %360 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %361 = extractelement <4 x float> %360, i32 3 %362 = fmul float %359, %361 %363 = fadd float %362, %339 %364 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %365 = extractelement <4 x float> %364, i32 2 %366 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %367 = extractelement <4 x float> %366, i32 3 %368 = fmul float %365, %367 %369 = fadd float %368, %345 %370 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %371 = extractelement <4 x float> %370, i32 3 %372 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %373 = extractelement <4 x float> %372, i32 3 %374 = fmul float %371, %373 %375 = fadd float %374, %351 %376 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %377 = extractelement <4 x float> %376, i32 0 %378 = fmul float %81, %377 %379 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %380 = extractelement <4 x float> %379, i32 0 %381 = fmul float %87, %380 %382 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %383 = extractelement <4 x float> %382, i32 0 %384 = fmul float %93, %383 %385 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %386 = extractelement <4 x float> %385, i32 0 %387 = fmul float %99, %386 %388 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %389 = extractelement <4 x float> %388, i32 1 %390 = fmul float %173, %389 %391 = fadd float %390, %378 %392 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %393 = extractelement <4 x float> %392, i32 1 %394 = fmul float %179, %393 %395 = fadd float %394, %381 %396 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %397 = extractelement <4 x float> %396, i32 1 %398 = fmul float %185, %397 %399 = fadd float %398, %384 %400 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %401 = extractelement <4 x float> %400, i32 1 %402 = fmul float %191, %401 %403 = fadd float %402, %387 %404 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %405 = extractelement <4 x float> %404, i32 2 %406 = fmul float %265, %405 %407 = fadd float %406, %391 %408 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %409 = extractelement <4 x float> %408, i32 2 %410 = fmul float %271, %409 %411 = fadd float %410, %395 %412 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %413 = extractelement <4 x float> %412, i32 2 %414 = fmul float %277, %413 %415 = fadd float %414, %399 %416 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %417 = extractelement <4 x float> %416, i32 2 %418 = fmul float %283, %417 %419 = fadd float %418, %403 %420 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %421 = extractelement <4 x float> %420, i32 3 %422 = fmul float %357, %421 %423 = fadd float %422, %407 %424 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %425 = extractelement <4 x float> %424, i32 3 %426 = fmul float %363, %425 %427 = fadd float %426, %411 %428 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %429 = extractelement <4 x float> %428, i32 3 %430 = fmul float %369, %429 %431 = fadd float %430, %415 %432 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %433 = extractelement <4 x float> %432, i32 3 %434 = fmul float %375, %433 %435 = fadd float %434, %419 %436 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %437 = extractelement <4 x float> %436, i32 0 %438 = fmul float %81, %437 %439 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %440 = extractelement <4 x float> %439, i32 0 %441 = fmul float %87, %440 %442 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %443 = extractelement <4 x float> %442, i32 0 %444 = fmul float %93, %443 %445 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %446 = extractelement <4 x float> %445, i32 0 %447 = fmul float %99, %446 %448 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %449 = extractelement <4 x float> %448, i32 1 %450 = fmul float %173, %449 %451 = fadd float %450, %438 %452 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %453 = extractelement <4 x float> %452, i32 1 %454 = fmul float %179, %453 %455 = fadd float %454, %441 %456 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %457 = extractelement <4 x float> %456, i32 1 %458 = fmul float %185, %457 %459 = fadd float %458, %444 %460 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %461 = extractelement <4 x float> %460, i32 1 %462 = fmul float %191, %461 %463 = fadd float %462, %447 %464 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %465 = extractelement <4 x float> %464, i32 2 %466 = fmul float %265, %465 %467 = fadd float %466, %451 %468 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %469 = extractelement <4 x float> %468, i32 2 %470 = fmul float %271, %469 %471 = fadd float %470, %455 %472 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %473 = extractelement <4 x float> %472, i32 2 %474 = fmul float %277, %473 %475 = fadd float %474, %459 %476 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %477 = extractelement <4 x float> %476, i32 2 %478 = fmul float %283, %477 %479 = fadd float %478, %463 %480 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %481 = extractelement <4 x float> %480, i32 3 %482 = fmul float %357, %481 %483 = fadd float %482, %467 %484 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %485 = extractelement <4 x float> %484, i32 3 %486 = fmul float %363, %485 %487 = fadd float %486, %471 %488 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %489 = extractelement <4 x float> %488, i32 3 %490 = fmul float %369, %489 %491 = fadd float %490, %475 %492 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %493 = extractelement <4 x float> %492, i32 3 %494 = fmul float %375, %493 %495 = fadd float %494, %479 %496 = load <4 x float> addrspace(8)* null %497 = extractelement <4 x float> %496, i32 0 %498 = fmul float %81, %497 %499 = load <4 x float> addrspace(8)* null %500 = extractelement <4 x float> %499, i32 0 %501 = fmul float %87, %500 %502 = load <4 x float> addrspace(8)* null %503 = extractelement <4 x float> %502, i32 0 %504 = fmul float %93, %503 %505 = load <4 x float> addrspace(8)* null %506 = extractelement <4 x float> %505, i32 0 %507 = fmul float %99, %506 %508 = load <4 x float> addrspace(8)* null %509 = extractelement <4 x float> %508, i32 1 %510 = fmul float %173, %509 %511 = fadd float %510, %498 %512 = load <4 x float> addrspace(8)* null %513 = extractelement <4 x float> %512, i32 1 %514 = fmul float %179, %513 %515 = fadd float %514, %501 %516 = load <4 x float> addrspace(8)* null %517 = extractelement <4 x float> %516, i32 1 %518 = fmul float %185, %517 %519 = fadd float %518, %504 %520 = load <4 x float> addrspace(8)* null %521 = extractelement <4 x float> %520, i32 1 %522 = fmul float %191, %521 %523 = fadd float %522, %507 %524 = load <4 x float> addrspace(8)* null %525 = extractelement <4 x float> %524, i32 2 %526 = fmul float %265, %525 %527 = fadd float %526, %511 %528 = load <4 x float> addrspace(8)* null %529 = extractelement <4 x float> %528, i32 2 %530 = fmul float %271, %529 %531 = fadd float %530, %515 %532 = load <4 x float> addrspace(8)* null %533 = extractelement <4 x float> %532, i32 2 %534 = fmul float %277, %533 %535 = fadd float %534, %519 %536 = load <4 x float> addrspace(8)* null %537 = extractelement <4 x float> %536, i32 2 %538 = fmul float %283, %537 %539 = fadd float %538, %523 %540 = load <4 x float> addrspace(8)* null %541 = extractelement <4 x float> %540, i32 3 %542 = fmul float %357, %541 %543 = fadd float %542, %527 %544 = load <4 x float> addrspace(8)* null %545 = extractelement <4 x float> %544, i32 3 %546 = fmul float %363, %545 %547 = fadd float %546, %531 %548 = load <4 x float> addrspace(8)* null %549 = extractelement <4 x float> %548, i32 3 %550 = fmul float %369, %549 %551 = fadd float %550, %535 %552 = load <4 x float> addrspace(8)* null %553 = extractelement <4 x float> %552, i32 3 %554 = fmul float %375, %553 %555 = fadd float %554, %539 %556 = fmul float %543, %4 %557 = fmul float %547, %4 %558 = fmul float %551, %4 %559 = fmul float %555, %4 %560 = fmul float %483, %5 %561 = fadd float %560, %556 %562 = fmul float %487, %5 %563 = fadd float %562, %557 %564 = fmul float %491, %5 %565 = fadd float %564, %558 %566 = fmul float %495, %5 %567 = fadd float %566, %559 %568 = fmul float %423, %6 %569 = fadd float %568, %561 %570 = fmul float %427, %6 %571 = fadd float %570, %563 %572 = fmul float %431, %6 %573 = fadd float %572, %565 %574 = fmul float %435, %6 %575 = fadd float %574, %567 %576 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %577 = extractelement <4 x float> %576, i32 0 %578 = fmul float %81, %577 %579 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %580 = extractelement <4 x float> %579, i32 0 %581 = fmul float %87, %580 %582 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %583 = extractelement <4 x float> %582, i32 0 %584 = fmul float %93, %583 %585 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %586 = extractelement <4 x float> %585, i32 0 %587 = fmul float %99, %586 %588 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %589 = extractelement <4 x float> %588, i32 1 %590 = fmul float %173, %589 %591 = fadd float %590, %578 %592 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %593 = extractelement <4 x float> %592, i32 1 %594 = fmul float %179, %593 %595 = fadd float %594, %581 %596 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %597 = extractelement <4 x float> %596, i32 1 %598 = fmul float %185, %597 %599 = fadd float %598, %584 %600 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %601 = extractelement <4 x float> %600, i32 1 %602 = fmul float %191, %601 %603 = fadd float %602, %587 %604 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %605 = extractelement <4 x float> %604, i32 2 %606 = fmul float %265, %605 %607 = fadd float %606, %591 %608 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %609 = extractelement <4 x float> %608, i32 2 %610 = fmul float %271, %609 %611 = fadd float %610, %595 %612 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %613 = extractelement <4 x float> %612, i32 2 %614 = fmul float %277, %613 %615 = fadd float %614, %599 %616 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %617 = extractelement <4 x float> %616, i32 2 %618 = fmul float %283, %617 %619 = fadd float %618, %603 %620 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %621 = extractelement <4 x float> %620, i32 3 %622 = fmul float %357, %621 %623 = fadd float %622, %607 %624 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %625 = extractelement <4 x float> %624, i32 3 %626 = fmul float %363, %625 %627 = fadd float %626, %611 %628 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %629 = extractelement <4 x float> %628, i32 3 %630 = fmul float %369, %629 %631 = fadd float %630, %615 %632 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %633 = extractelement <4 x float> %632, i32 3 %634 = fmul float %375, %633 %635 = fadd float %634, %619 %636 = fadd float %569, %623 %637 = fadd float %571, %627 %638 = fadd float %573, %631 %639 = fadd float %575, %635 %640 = insertelement <4 x float> undef, float %636, i32 0 %641 = insertelement <4 x float> %640, float %637, i32 1 %642 = insertelement <4 x float> %641, float %638, i32 2 %643 = insertelement <4 x float> %642, float %639, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %643, i32 60, i32 1) %644 = insertelement <4 x float> undef, float %0, i32 0 %645 = insertelement <4 x float> %644, float %1, i32 1 %646 = insertelement <4 x float> %645, float %185, i32 2 %647 = insertelement <4 x float> %646, float %191, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %647, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #44 =========================================== VS/RS880/R600 ===== ===== 304 dw ===== 13 gprs ===== 1 stack ======================================= 0000 00000000 89800000 CALL_FS @0 0002 80000006 a1cc0000 ALU 116 @12 KC0[CB0:0-31] 0012 80110c84 60000210 1 w: MUL_IEEE R0.w, KC0[4].w, KC0[8].x 0014 80910c85 60028cfe 2 w: MULADD_IEEE R0.w, KC0[5].w, KC0[8].y, PV.w 0016 81110c86 60028cfe 3 w: MULADD_IEEE R0.w, KC0[6].w, KC0[8].z, PV.w 0018 81910c87 60428cfe 4 w: MULADD_IEEE R2.w, KC0[7].w, KC0[8].w, PV.w 0020 00100cfe 40600210 5 z: MUL_IEEE R3.z, PV.w, KC0[0].x 0022 80102cfe 60200210 w: MUL_IEEE R1.w, PV.w, KC0[1].x 0024 00112884 40200210 6 z: MUL_IEEE R1.z, KC0[4].z, KC0[9].x 0026 80112c84 60000210 w: MUL_IEEE R0.w, KC0[4].w, KC0[9].x 0028 00912c85 40028cfe 7 z: MULADD_IEEE R0.z, KC0[5].w, KC0[9].y, PV.w 0030 80912885 600288fe w: MULADD_IEEE R0.w, KC0[5].z, KC0[9].y, PV.z 0032 01112886 40828cfe 8 z: MULADD_IEEE R4.z, KC0[6].z, KC0[9].z, PV.w 0034 81112c86 600288fe w: MULADD_IEEE R0.w, KC0[6].w, KC0[9].z, PV.z 0036 81912c87 60028cfe 9 w: MULADD_IEEE R0.w, KC0[7].w, KC0[9].w, PV.w 0038 00902cfe 40228c01 10 z: MULADD_IEEE R1.z, PV.w, KC0[1].y, R1.w 0040 80900cfe 60228803 w: MULADD_IEEE R1.w, PV.w, KC0[0].y, R3.z 0042 81912887 40028804 11 z: MULADD_IEEE R0.z, KC0[7].z, KC0[9].w, R4.z 0044 80110884 60600210 12 w: MUL_IEEE R3.w, KC0[4].z, KC0[8].x 0046 80910885 60628cfe 13 w: MULADD_IEEE R3.w, KC0[5].z, KC0[8].y, PV.w 0048 81110886 60628cfe 14 w: MULADD_IEEE R3.w, KC0[6].z, KC0[8].z, PV.w 0050 81910887 60828cfe 15 w: MULADD_IEEE R4.w, KC0[7].z, KC0[8].w, PV.w 0052 00104c02 00800210 16 x: MUL_IEEE R4.x, R2.w, KC0[2].x 0054 00104cfe 20880210 y: MUL_IEEE R4.y, PV.w, KC0[2].x VEC_120 0056 00106c02 40600210 z: MUL_IEEE R3.z, R2.w, KC0[3].x 0058 80106cfe 60480210 w: MUL_IEEE R2.w, PV.w, KC0[3].x VEC_120 0060 00906800 00628cfe 17 x: MULADD_IEEE R3.x, R0.z, KC0[3].y, PV.w 0062 00906c00 206288fe y: MULADD_IEEE R3.y, R0.w, KC0[3].y, PV.z 0064 00904800 406284fe z: MULADD_IEEE R3.z, R0.z, KC0[2].y, PV.y 0066 80904c00 606280fe w: MULADD_IEEE R3.w, R0.w, KC0[2].y, PV.x 0068 00100c04 40a00210 18 z: MUL_IEEE R5.z, R4.w, KC0[0].x 0070 80102c04 60400210 w: MUL_IEEE R2.w, R4.w, KC0[1].x 0072 00902800 40828cfe 19 z: MULADD_IEEE R4.z, R0.z, KC0[1].y, PV.w 0074 80900800 604288fe w: MULADD_IEEE R2.w, R0.z, KC0[0].y, PV.z 0076 00000001 00001910 20 x: MOV R0.x, R1.x 0078 00000401 20001910 y: MOV R0.y, R1.y 0080 00110084 40a00210 z: MUL_IEEE R5.z, KC0[4].x, KC0[8].x 0082 80110484 60800210 w: MUL_IEEE R4.w, KC0[4].y, KC0[8].x 0084 00910485 40c28cfe 21 z: MULADD_IEEE R6.z, KC0[5].y, KC0[8].y, PV.w 0086 80910085 608288fe w: MULADD_IEEE R4.w, KC0[5].x, KC0[8].y, PV.z 0088 01110086 40a28cfe 22 z: MULADD_IEEE R5.z, KC0[6].x, KC0[8].z, PV.w 0090 81110486 608288fe w: MULADD_IEEE R4.w, KC0[6].y, KC0[8].z, PV.z 0092 01910487 41028cfe 23 z: MULADD_IEEE R8.z, KC0[7].y, KC0[8].w, PV.w 0094 81910087 60a288fe w: MULADD_IEEE R5.w, KC0[7].x, KC0[8].w, PV.z 0096 80106cfe 60800210 24 w: MUL_IEEE R4.w, PV.w, KC0[3].x 0098 80112084 60c00210 25 w: MUL_IEEE R6.w, KC0[4].x, KC0[9].x 0100 80912085 60c28cfe 26 w: MULADD_IEEE R6.w, KC0[5].x, KC0[9].y, PV.w 0102 81112086 60c28cfe 27 w: MULADD_IEEE R6.w, KC0[6].x, KC0[9].z, PV.w 0104 81912087 60e28cfe 28 w: MULADD_IEEE R7.w, KC0[7].x, KC0[9].w, PV.w 0106 80906cfe 60c28c04 29 w: MULADD_IEEE R6.w, PV.w, KC0[3].y, R4.w 0108 00114084 40c00210 30 z: MUL_IEEE R6.z, KC0[4].x, KC0[10].x 0110 80114484 60800210 w: MUL_IEEE R4.w, KC0[4].y, KC0[10].x 0112 00914485 40a28cfe 31 z: MULADD_IEEE R5.z, KC0[5].y, KC0[10].y, PV.w 0114 80914085 608288fe w: MULADD_IEEE R4.w, KC0[5].x, KC0[10].y, PV.z 0116 01114086 40c28cfe 32 z: MULADD_IEEE R6.z, KC0[6].x, KC0[10].z, PV.w 0118 81114486 608288fe w: MULADD_IEEE R4.w, KC0[6].y, KC0[10].z, PV.z 0120 01914487 40a28cfe 33 z: MULADD_IEEE R5.z, KC0[7].y, KC0[10].w, PV.w 0122 81914087 614288fe w: MULADD_IEEE R10.w, KC0[7].x, KC0[10].w, PV.z 0124 00114884 40e00210 34 z: MUL_IEEE R7.z, KC0[4].z, KC0[10].x 0126 80114c84 60800210 w: MUL_IEEE R4.w, KC0[4].w, KC0[10].x 0128 00914c85 40c28cfe 35 z: MULADD_IEEE R6.z, KC0[5].w, KC0[10].y, PV.w 0130 80914885 608288fe w: MULADD_IEEE R4.w, KC0[5].z, KC0[10].y, PV.z 0132 01114886 41228cfe 36 z: MULADD_IEEE R9.z, KC0[6].z, KC0[10].z, PV.w 0134 81114c86 608288fe w: MULADD_IEEE R4.w, KC0[6].w, KC0[10].z, PV.z 0136 01914c87 40e28cfe 37 z: MULADD_IEEE R7.z, KC0[7].w, KC0[10].w, PV.w 0138 81914887 608288fe w: MULADD_IEEE R4.w, KC0[7].z, KC0[10].w, PV.z 0140 01106cfe 20228003 38 y: MULADD_IEEE R1.y, PV.w, KC0[3].z, R3.x 0142 01106c0a 40c28c06 z: MULADD_IEEE R6.z, R10.w, KC0[3].z, R6.w 0144 80102808 61000210 w: MUL_IEEE R8.w, R8.z, KC0[1].x 0146 80112484 60c00210 39 w: MUL_IEEE R6.w, KC0[4].y, KC0[9].x 0148 80912485 60c28cfe 40 w: MULADD_IEEE R6.w, KC0[5].y, KC0[9].y, PV.w 0150 81112486 60c28cfe 41 w: MULADD_IEEE R6.w, KC0[6].y, KC0[9].z, PV.w 0152 81912487 60c28cfe 42 w: MULADD_IEEE R6.w, KC0[7].y, KC0[9].w, PV.w 0154 00902cfe 41228c08 43 z: MULADD_IEEE R9.z, PV.w, KC0[1].y, R8.w 0156 80104c05 61000210 w: MUL_IEEE R8.w, R5.w, KC0[2].x 0158 00904c07 41428cfe 44 z: MULADD_IEEE R10.z, R7.w, KC0[2].y, PV.w 0160 81102805 610288fe w: MULADD_IEEE R8.w, R5.z, KC0[1].z, PV.z 0162 80116484 61200210 45 w: MUL_IEEE R9.w, KC0[4].y, KC0[11].x 0164 80916485 61228cfe 46 w: MULADD_IEEE R9.w, KC0[5].y, KC0[11].y, PV.w 0166 81116486 61228cfe 47 w: MULADD_IEEE R9.w, KC0[6].y, KC0[11].z, PV.w 0168 81916487 61228cfe 48 w: MULADD_IEEE R9.w, KC0[7].y, KC0[11].w, PV.w 0170 01902cfe 41228c08 49 z: MULADD_IEEE R9.z, PV.w, KC0[1].w, R8.w 0172 81104c0a 6162880a w: MULADD_IEEE R11.w, R10.w, KC0[2].z, R10.z 0174 80116084 61000210 50 w: MUL_IEEE R8.w, KC0[4].x, KC0[11].x 0176 80916085 61028cfe 51 w: MULADD_IEEE R8.w, KC0[5].x, KC0[11].y, PV.w 0178 81116086 61028cfe 52 w: MULADD_IEEE R8.w, KC0[6].x, KC0[11].z, PV.w 0180 81916087 61028cfe 53 w: MULADD_IEEE R8.w, KC0[7].x, KC0[11].w, PV.w 0182 01904cfe 20828c0b 54 y: MULADD_IEEE R4.y, PV.w, KC0[2].w, R11.w 0184 00106808 41400210 z: MUL_IEEE R10.z, R8.z, KC0[3].x 0186 81104807 616a8c03 w: MULADD_IEEE R11.w, R7.z, KC0[2].z, R3.w VEC_120 0188 00116c84 41600210 55 z: MUL_IEEE R11.z, KC0[4].w, KC0[11].x 0190 80116884 60600210 w: MUL_IEEE R3.w, KC0[4].z, KC0[11].x 0192 00916885 41828cfe 56 z: MULADD_IEEE R12.z, KC0[5].z, KC0[11].y, PV.w 0194 80916c85 606288fe w: MULADD_IEEE R3.w, KC0[5].w, KC0[11].y, PV.z 0196 01116c86 41628cfe 57 z: MULADD_IEEE R11.z, KC0[6].w, KC0[11].z, PV.w 0198 81116886 606288fe w: MULADD_IEEE R3.w, KC0[6].z, KC0[11].z, PV.z 0200 81916887 60628cfe 58 w: MULADD_IEEE R3.w, KC0[7].z, KC0[11].w, PV.w 0202 00104808 20a00210 59 y: MUL_IEEE R5.y, R8.z, KC0[2].x 0204 00100c05 41800210 z: MUL_IEEE R12.z, R5.w, KC0[0].x 0206 80100808 61800210 w: MUL_IEEE R12.w, R8.z, KC0[0].x 0208 00900c06 20c28cfe 60 y: MULADD_IEEE R6.y, R6.w, KC0[0].y, PV.w 0210 00102c05 41080210 z: MUL_IEEE R8.z, R5.w, KC0[1].x VEC_120 0212 80900c07 60b288fe w: MULADD_IEEE R5.w, R7.w, KC0[0].y, PV.z VEC_201 0214 81100c04 21028c02 61 y: MULADD_IEEE R8.y, R4.w, KC0[0].z, R2.w 0216 01100c0a 41828c05 62 z: MULADD_IEEE R12.z, R10.w, KC0[0].z, R5.w 0218 80902c07 604a8808 w: MULADD_IEEE R2.w, R7.w, KC0[1].y, R8.z VEC_120 0220 01102c0a 00228cfe 63 x: MULADD_IEEE R1.x, R10.w, KC0[1].z, PV.w 0222 01900c08 20ea88fe y: MULADD_IEEE R7.y, R8.w, KC0[0].w, PV.z VEC_120 0224 81102c04 40928804 z: MULADD_IEEE R4.z, R4.w, KC0[1].z, R4.z VEC_201 0226 81900c03 60428408 64 w: MULADD_IEEE R2.w, R3.w, KC0[0].w, R8.y 0228 01100807 00628c01 65 x: MULADD_IEEE R3.x, R7.z, KC0[0].z, R1.w 0230 01102807 21028801 y: MULADD_IEEE R8.y, R7.z, KC0[1].z, R1.z 0232 00004cfe 40200210 z: MUL_IEEE R1.z, PV.w, R2.x 0234 81902c03 60268804 w: MULADD_IEEE R1.w, R3.w, KC0[1].w, R4.z VEC_021 0236 00804cfe 402288fe 66 z: MULADD_IEEE R1.z, PV.w, R2.y, PV.z 0238 81916c87 6022880b w: MULADD_IEEE R1.w, KC0[7].w, KC0[11].w, R11.z 0240 01902cfe 00828408 67 x: MULADD_IEEE R4.x, PV.w, KC0[1].w, R8.y 0242 81900cfe 21028003 y: MULADD_IEEE R8.y, PV.w, KC0[0].w, R3.x 0004 8000007a a0740000 ALU 30 @244 KC0[CB0:0-31] 0244 00004407 40800210 68 z: MUL_IEEE R4.z, R7.y, R2.x 0246 81902c08 60428001 w: MULADD_IEEE R2.w, R8.w, KC0[1].w, R1.x 0248 00804cfe 002288fe 69 x: MULADD_IEEE R1.x, PV.w, R2.y, PV.z 0250 00004408 20e00210 y: MUL_IEEE R7.y, R8.y, R2.x 0252 81100805 40828406 z: MULADD_IEEE R4.z, R5.z, KC0[0].z, R6.y 0254 80904c06 60428405 70 w: MULADD_IEEE R2.w, R6.w, KC0[2].y, R5.y 0256 01104805 00628cfe 71 x: MULADD_IEEE R3.x, R5.z, KC0[2].z, PV.w 0258 01900c09 20a28804 y: MULADD_IEEE R5.y, R9.w, KC0[0].w, R4.z 0260 00804004 40828407 z: MULADD_IEEE R4.z, R4.x, R2.y, R7.y 0262 81904c01 604e8c0b w: MULADD_IEEE R2.w, R1.w, KC0[2].w, R11.w VEC_102 0264 01004cfe 008288fe 72 x: MULADD_IEEE R4.x, PV.w, R2.z, PV.z 0266 000044fe 20a00210 y: MUL_IEEE R5.y, PV.y, R2.x 0268 00906c06 4082880a z: MULADD_IEEE R4.z, R6.w, KC0[3].y, R10.z 0270 81106807 60428403 w: MULADD_IEEE R2.w, R7.z, KC0[3].z, R3.y 0272 01906c01 00428cfe 73 x: MULADD_IEEE R2.x, R1.w, KC0[3].w, PV.w 0274 01106805 206288fe y: MULADD_IEEE R3.y, R5.z, KC0[3].z, PV.z 0276 00804809 408a84fe z: MULADD_IEEE R4.z, R9.z, R2.y, PV.y VEC_120 0278 81904c09 602a8003 w: MULADD_IEEE R1.w, R9.w, KC0[2].w, R3.x VEC_120 0280 01004cfe 006288fe 74 x: MULADD_IEEE R3.x, PV.w, R2.z, PV.z 0282 01906c09 204284fe y: MULADD_IEEE R2.y, R9.w, KC0[3].w, PV.y 0284 01104c04 406a8803 z: MULADD_IEEE R3.z, R4.w, KC0[2].z, R3.z VEC_120 0286 801fc004 60a00010 w: ADD R5.w, R4.x, PV.x 0288 01904c03 004288fe 75 x: MULADD_IEEE R2.x, R3.w, KC0[2].w, PV.z 0290 009fc0fe 20a00010 y: ADD R5.y, PV.x, PV.y 0292 01004404 40628001 z: MULADD_IEEE R3.z, R4.y, R2.z, R1.x 0294 81906c08 602a8806 w: MULADD_IEEE R1.w, R8.w, KC0[3].w, R6.z VEC_120 0296 019fc8fe 00a00010 76 x: ADD R5.x, PV.z, PV.w 0298 010040fe 40228801 z: MULADD_IEEE R1.z, PV.x, R2.z, R1.z 0300 81906c03 60228401 w: MULADD_IEEE R1.w, R3.w, KC0[3].w, R1.y 0302 819fc8fe 40a00010 77 z: ADD R5.z, PV.z, PV.w 0006 c002a03c 94400688 EXPORT_DONE POS 60 R5.xyzw VPM 0008 c0004000 94600688 EXPORT_DONE PARAM 0 R0.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_FLOAT, } {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 1, src_format = PIPE_FORMAT_R32G32B32_FLOAT, } ===== SHADER #45 ======================================== FETCH/RS880/R600 ===== ===== 12 dw ===== 3 gprs ===== 0 stack ========================================= 0000 00000002 81000400 VTX 2 @4 0004 7c00a000 87961001 00080000 VFETCH R1.xy01, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:30 NUM:0 COMP:0 MODE:1) 0008 7c00a100 8c151002 00080000 VFETCH R2.xyz1, R0.x, RID:161 VERTEX MFC:31 UCF:0 FMT(DTA:48 NUM:0 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[19], PERSPECTIVE DCL IN[1], GENERIC[20], PERSPECTIVE DCL IN[2], GENERIC[21], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0..3] DCL TEMP[0..6], LOCAL IMM[0] FLT32 { 0,7500, 0,2500, 0,0000, 2,0000} 0: MOV TEMP[0].z, IN[1].xxxx 1: MOV TEMP[0].xy, IN[0].zwzz 2: MOV TEMP[1].xy, IN[0].xyyy 3: TEX TEMP[1], TEMP[1], SAMP[0], 2D 4: MOV TEMP[2], CONST[3] 5: DP3 TEMP[3].x, IN[2].xyzz, IN[2].xyzz 6: RSQ TEMP[3].x, TEMP[3].xxxx 7: MUL TEMP[3].xyz, IN[2].xyzz, TEMP[3].xxxx 8: DP3 TEMP[4].x, IN[1].yzww, IN[1].yzww 9: RSQ TEMP[4].x, TEMP[4].xxxx 10: MUL TEMP[4].xyz, IN[1].yzww, TEMP[4].xxxx 11: DP3 TEMP[5].x, TEMP[3].xyzz, TEMP[4].xyzz 12: MAD TEMP[5].x, TEMP[5].xxxx, IMM[0].xxxx, IMM[0].yyyy 13: SLT TEMP[6].x, IMM[0].zzzz, TEMP[5].xxxx 14: F2I TEMP[6].x, -TEMP[6] 15: UIF TEMP[6].xxxx :0 16: MUL TEMP[5], CONST[2], TEMP[5].xxxx 17: MAD TEMP[2], TEMP[5], IMM[0].wwww, CONST[3] 18: MOV TEMP[4].xyz, -TEMP[4].xyzx 19: DP3 TEMP[5].x, TEMP[3].xyzz, TEMP[4].xyzz 20: MUL TEMP[3].xyz, TEMP[5].xxxx, TEMP[3].xyzz 21: MUL TEMP[3].xyz, IMM[0].wwww, TEMP[3].xyzz 22: ADD TEMP[3].xyz, TEMP[4].xyzz, -TEMP[3].xyzz 23: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz 24: RSQ TEMP[4].x, TEMP[4].xxxx 25: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[4].xxxx 26: DP3_SAT TEMP[0].x, TEMP[3].xyzz, TEMP[0].xyzz 27: POW TEMP[0].x, TEMP[0].xxxx, CONST[0].xxxx 28: MAD TEMP[2].xyz, CONST[1], TEMP[0].xxxx, TEMP[2] 29: ENDIF 30: MUL TEMP[0].xyz, TEMP[1].xyzz, TEMP[2].xyzz 31: MOV TEMP[0].w, TEMP[1].wwww 32: MOV OUT[0], TEMP[0] 33: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = call float @llvm.R600.load.input(i32 4) %5 = call float @llvm.R600.load.input(i32 5) %6 = call float @llvm.R600.load.input(i32 6) %7 = call float @llvm.R600.load.input(i32 7) %8 = call float @llvm.R600.load.input(i32 8) %9 = call float @llvm.R600.load.input(i32 9) %10 = call float @llvm.R600.load.input(i32 10) %11 = call float @llvm.R600.load.input(i32 11) %12 = insertelement <4 x float> undef, float %0, i32 0 %13 = insertelement <4 x float> %12, float %1, i32 1 %14 = insertelement <4 x float> %13, float 0,000000e+00, i32 2 %15 = insertelement <4 x float> %14, float 0,000000e+00, i32 3 %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = insertelement <4 x float> undef, float %16, i32 0 %19 = insertelement <4 x float> %18, float %17, i32 1 %20 = insertelement <4 x float> %19, float undef, i32 2 %21 = insertelement <4 x float> %20, float undef, i32 3 %22 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %21, i32 16, i32 0, i32 2) %23 = extractelement <4 x float> %22, i32 0 %24 = extractelement <4 x float> %22, i32 1 %25 = extractelement <4 x float> %22, i32 2 %26 = extractelement <4 x float> %22, i32 3 %27 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %28 = extractelement <4 x float> %27, i32 0 %29 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %30 = extractelement <4 x float> %29, i32 1 %31 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %32 = extractelement <4 x float> %31, i32 2 %33 = insertelement <4 x float> undef, float %8, i32 0 %34 = insertelement <4 x float> %33, float %9, i32 1 %35 = insertelement <4 x float> %34, float %10, i32 2 %36 = insertelement <4 x float> %35, float 0,000000e+00, i32 3 %37 = insertelement <4 x float> undef, float %8, i32 0 %38 = insertelement <4 x float> %37, float %9, i32 1 %39 = insertelement <4 x float> %38, float %10, i32 2 %40 = insertelement <4 x float> %39, float 0,000000e+00, i32 3 %41 = call float @llvm.AMDGPU.dp4(<4 x float> %36, <4 x float> %40) %42 = call float @fabs(float %41) %43 = call float @llvm.AMDGPU.rsq(float %42) %44 = fmul float %8, %43 %45 = fmul float %9, %43 %46 = fmul float %10, %43 %47 = insertelement <4 x float> undef, float %5, i32 0 %48 = insertelement <4 x float> %47, float %6, i32 1 %49 = insertelement <4 x float> %48, float %7, i32 2 %50 = insertelement <4 x float> %49, float 0,000000e+00, i32 3 %51 = insertelement <4 x float> undef, float %5, i32 0 %52 = insertelement <4 x float> %51, float %6, i32 1 %53 = insertelement <4 x float> %52, float %7, i32 2 %54 = insertelement <4 x float> %53, float 0,000000e+00, i32 3 %55 = call float @llvm.AMDGPU.dp4(<4 x float> %50, <4 x float> %54) %56 = call float @fabs(float %55) %57 = call float @llvm.AMDGPU.rsq(float %56) %58 = fmul float %5, %57 %59 = fmul float %6, %57 %60 = fmul float %7, %57 %61 = insertelement <4 x float> undef, float %44, i32 0 %62 = insertelement <4 x float> %61, float %45, i32 1 %63 = insertelement <4 x float> %62, float %46, i32 2 %64 = insertelement <4 x float> %63, float 0,000000e+00, i32 3 %65 = insertelement <4 x float> undef, float %58, i32 0 %66 = insertelement <4 x float> %65, float %59, i32 1 %67 = insertelement <4 x float> %66, float %60, i32 2 %68 = insertelement <4 x float> %67, float 0,000000e+00, i32 3 %69 = call float @llvm.AMDGPU.dp4(<4 x float> %64, <4 x float> %68) %70 = fmul float %69, 0x3FE8000000000000 %71 = fadd float %70, 0x3FD0000000000000 %72 = fcmp ult float 0,000000e+00, %71 %73 = select i1 %72, float 0x3FF0000000000000, float 0,000000e+00 %74 = fsub float -0,000000e+00, %73 %75 = fptosi float %74 to i32 %76 = bitcast i32 %75 to float %77 = bitcast float %76 to i32 %78 = icmp ne i32 %77, 0 br i1 %78, label %IF, label %ENDIF IF: ; preds = %main_body %79 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %80 = extractelement <4 x float> %79, i32 0 %81 = fmul float %80, %71 %82 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %83 = extractelement <4 x float> %82, i32 1 %84 = fmul float %83, %71 %85 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %86 = extractelement <4 x float> %85, i32 2 %87 = fmul float %86, %71 %88 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %89 = extractelement <4 x float> %88, i32 0 %90 = fmul float %81, 0x4000000000000000 %91 = fadd float %90, %89 %92 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %93 = extractelement <4 x float> %92, i32 1 %94 = fmul float %84, 0x4000000000000000 %95 = fadd float %94, %93 %96 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %97 = extractelement <4 x float> %96, i32 2 %98 = fmul float %87, 0x4000000000000000 %99 = fadd float %98, %97 %100 = fsub float -0,000000e+00, %58 %101 = fsub float -0,000000e+00, %59 %102 = fsub float -0,000000e+00, %60 %103 = insertelement <4 x float> undef, float %44, i32 0 %104 = insertelement <4 x float> %103, float %45, i32 1 %105 = insertelement <4 x float> %104, float %46, i32 2 %106 = insertelement <4 x float> %105, float 0,000000e+00, i32 3 %107 = insertelement <4 x float> undef, float %100, i32 0 %108 = insertelement <4 x float> %107, float %101, i32 1 %109 = insertelement <4 x float> %108, float %102, i32 2 %110 = insertelement <4 x float> %109, float 0,000000e+00, i32 3 %111 = call float @llvm.AMDGPU.dp4(<4 x float> %106, <4 x float> %110) %112 = fmul float %111, %44 %113 = fmul float %111, %45 %114 = fmul float %111, %46 %115 = fmul float 0x4000000000000000, %112 %116 = fmul float 0x4000000000000000, %113 %117 = fmul float 0x4000000000000000, %114 %118 = fsub float -0,000000e+00, %115 %119 = fadd float %100, %118 %120 = fsub float -0,000000e+00, %116 %121 = fadd float %101, %120 %122 = fsub float -0,000000e+00, %117 %123 = fadd float %102, %122 %124 = insertelement <4 x float> undef, float %2, i32 0 %125 = insertelement <4 x float> %124, float %3, i32 1 %126 = insertelement <4 x float> %125, float %4, i32 2 %127 = insertelement <4 x float> %126, float 0,000000e+00, i32 3 %128 = insertelement <4 x float> undef, float %2, i32 0 %129 = insertelement <4 x float> %128, float %3, i32 1 %130 = insertelement <4 x float> %129, float %4, i32 2 %131 = insertelement <4 x float> %130, float 0,000000e+00, i32 3 %132 = call float @llvm.AMDGPU.dp4(<4 x float> %127, <4 x float> %131) %133 = call float @fabs(float %132) %134 = call float @llvm.AMDGPU.rsq(float %133) %135 = fmul float %2, %134 %136 = fmul float %3, %134 %137 = fmul float %4, %134 %138 = insertelement <4 x float> undef, float %119, i32 0 %139 = insertelement <4 x float> %138, float %121, i32 1 %140 = insertelement <4 x float> %139, float %123, i32 2 %141 = insertelement <4 x float> %140, float 0,000000e+00, i32 3 %142 = insertelement <4 x float> undef, float %135, i32 0 %143 = insertelement <4 x float> %142, float %136, i32 1 %144 = insertelement <4 x float> %143, float %137, i32 2 %145 = insertelement <4 x float> %144, float 0,000000e+00, i32 3 %146 = call float @llvm.AMDGPU.dp4(<4 x float> %141, <4 x float> %145) %147 = call float @llvm.AMDIL.clamp.(float %146, float 0,000000e+00, float 0x3FF0000000000000) %148 = load <4 x float> addrspace(8)* null %149 = extractelement <4 x float> %148, i32 0 %150 = call float @llvm.pow.f32(float %147, float %149) %151 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %152 = extractelement <4 x float> %151, i32 0 %153 = fmul float %152, %150 %154 = fadd float %153, %91 %155 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %156 = extractelement <4 x float> %155, i32 1 %157 = fmul float %156, %150 %158 = fadd float %157, %95 %159 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %160 = extractelement <4 x float> %159, i32 2 %161 = fmul float %160, %150 %162 = fadd float %161, %99 br label %ENDIF ENDIF: ; preds = %main_body, %IF %temp8.0 = phi float [ %154, %IF ], [ %28, %main_body ] %temp9.0 = phi float [ %158, %IF ], [ %30, %main_body ] %temp10.0 = phi float [ %162, %IF ], [ %32, %main_body ] %163 = fmul float %23, %temp8.0 %164 = fmul float %24, %temp9.0 %165 = fmul float %25, %temp10.0 %166 = insertelement <4 x float> undef, float %163, i32 0 %167 = insertelement <4 x float> %166, float %164, i32 1 %168 = insertelement <4 x float> %167, float %165, i32 2 %169 = insertelement <4 x float> %168, float %26, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %169, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #1 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #3 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } attributes #3 = { nounwind readonly } ===== SHADER #46 =========================================== PS/RS880/R600 ===== ===== 176 dw ===== 6 gprs ===== 0 stack ======================================== 0000 00000004 80800000 TEX 1 @8 0008 00001010 f00d1003 68800000 SAMPLE R3.xyzw, R0.xyzw, RID:16, SID:0 CT:NNNN 0002 80000006 a1440000 ALU 82 @12 KC0[CB0:0-31] 0012 80000c01 40801910 1 z: MOV R4.z, R1.w 0014 80000801 20801910 2 y: MOV R4.y, R1.z 0016 80000401 00801910 3 x: MOV R4.x, R1.y 0018 00000800 00001910 4 x: MOV R0.x, R0.z 0020 00000c00 20001910 y: MOV R0.y, R0.w 0022 00000001 40001910 z: MOV R0.z, R1.x 0024 800000fd 60201910 w: MOV R1.w, [0x00000000 0].x 0026 00000000 0028 00004002 00005000 5 x: DOT4 __.x, R2.x, R2.x 0030 00804402 20005000 y: DOT4 __.y, R2.y, R2.y 0032 01004802 40005000 z: DOT4 __.z, R2.z, R2.z 0034 81802c01 60005010 w: DOT4 R0.w, R1.w, R1.w 0036 80000c00 60406711 6 t: RECIPSQRT_CLAMPED R2.w, |R0.w| 0038 00008004 00005000 7 x: DOT4 __.x, R4.x, R4.x 0040 00808404 20005000 y: DOT4 __.y, R4.y, R4.y 0042 01008804 40005000 z: DOT4 __.z, R4.z, R4.z 0044 81802c01 60005010 w: DOT4 R0.w, R1.w, R1.w 0046 01804002 00400210 8 x: MUL_IEEE R2.x, R2.x, R2.w 0048 01804402 20400210 y: MUL_IEEE R2.y, R2.y, R2.w 0050 81804802 40400210 z: MUL_IEEE R2.z, R2.z, R2.w 0052 80000c00 60006711 9 t: RECIPSQRT_CLAMPED R0.w, |R0.w| 0054 01800004 00200210 10 x: MUL_IEEE R1.x, R4.x, R0.w 0056 01800404 20200210 y: MUL_IEEE R1.y, R4.y, R0.w 0058 01800804 40200210 z: MUL_IEEE R1.z, R4.z, R0.w 0060 800000fd 60001910 w: MOV R0.w, [0x3f400000 0,75].x 0062 3f400000 0064 00002002 00405000 11 x: DOT4 __.x, R2.x, R1.x 0066 00802402 20405000 y: DOT4 __.y, R2.y, R1.y 0068 01002802 40405000 z: DOT4 __.z, R2.z, R1.z 0070 81802c01 60405010 w: DOT4 R2.w, R1.w, R1.w 0072 818000fe 600280fd 12 w: MULADD_IEEE R0.w, PV.x, R0.w, [0x3e800000 0,25].x 0074 3e800000 0076 819fc0f8 60400e10 13 w: SETGE_DX10 R2.w, 0, PV.w 0078 801f0cfe 00004208 14 P x: PRED_SETE_INT __.x, PV.w, 0 0080 40000083 20001910 15 0 y: MOV R0.y, KC0[3].x 0082 40000483 40001910 0 z: MOV R0.z, KC0[3].y 0084 c0000883 60001910 0 w: MOV R0.w, KC0[3].z 0086 02002002 00405000 16 x: DOT4 __.x, R2.x, -R1.x 0088 02802402 20405000 y: DOT4 __.y, R2.y, -R1.y 0090 03002802 40405000 z: DOT4 __.z, R2.z, -R1.z 0092 81802c01 60405010 w: DOT4 R2.w, R1.w, R1.w 0094 600040fe 20a00210 17 1 y: MUL_IEEE R5.y, PV.x, R2.x 0096 608040fe 40800210 1 z: MUL_IEEE R4.z, PV.x, R2.y 0098 e10040fe 60800210 1 w: MUL_IEEE R4.w, PV.x, R2.z 0100 61004c02 20828c04 18 1 y: MULADD_IEEE R4.y, R2.w, R2.z, R4.w 0102 60804c02 40428804 1 z: MULADD_IEEE R2.z, R2.w, R2.y, R4.z 0104 e0004c02 60428405 1 w: MULADD_IEEE R2.w, R2.w, R2.x, R5.y 0106 00000000 00405010 19 x: DOT4 R2.x, R0.x, R0.x 0108 00800400 20405000 y: DOT4 __.y, R0.y, R0.y 0110 01000800 40405000 z: DOT4 __.z, R0.z, R0.z 0112 81802c01 60405000 w: DOT4 __.w, R1.w, R1.w 0114 63805001 00200010 20 1 x: ADD R1.x, -R1.x, -R2.w 0116 63005401 20200010 1 y: ADD R1.y, -R1.y, -R2.z 0118 e2809801 40200010 1 z: ADD R1.z, -R1.z, -R4.y 0120 e0000002 60406711 21 1 t: RECIPSQRT_CLAMPED R2.w, |R2.x| 0122 61804000 00000210 22 1 x: MUL_IEEE R0.x, R0.x, R2.w 0124 61804400 20000210 1 y: MUL_IEEE R0.y, R0.y, R2.w 0126 e1804800 40000210 1 z: MUL_IEEE R0.z, R0.z, R2.w 0128 00000001 00005010 23 x: DOT4 R0.x, R1.x, R0.x 0130 00800401 20005000 y: DOT4 __.y, R1.y, R0.y 0132 01000801 40005000 z: DOT4 __.z, R1.z, R0.z 0134 81802c01 60005000 w: DOT4 __.w, R1.w, R1.w 0136 61800882 40000210 24 1 z: MUL_IEEE R0.z, KC0[2].z, R0.w 0138 e00000fe e0201910 1 w: MOV_sat R1.w, PV.x 0140 e1800482 00200210 25 1 x: MUL_IEEE R1.x, KC0[2].y, R0.w 0142 e0000c01 20006310 26 1 t: LOG_IEEE R0.y, R1.w 0144 60000080 40201910 27 1 z: MOV R1.z, KC0[0].x 0146 e1800082 60200210 1 w: MUL_IEEE R1.w, KC0[2].x, R0.w 0148 61800082 00028c01 28 1 x: MULADD_IEEE R0.x, KC0[2].x, R0.w, R1.w 0150 60800801 20000110 1 y: MUL R0.y, R1.z, R0.y 0152 61800482 40228001 1 z: MULADD_IEEE R1.z, KC0[2].y, R0.w, R1.x 0154 e1800882 60028800 1 w: MULADD_IEEE R0.w, KC0[2].z, R0.w, R0.z 0156 61106c00 00200010 29 1 x: ADD R1.x, R0.w, KC0[3].z 0158 e0906801 20200010 1 y: ADD R1.y, R1.z, KC0[3].y 0160 e0000400 40206110 30 1 t: EXP_IEEE R1.z, R0.y 0162 e0106000 60000010 31 1 w: ADD R0.w, R0.x, KC0[3].x 0164 61002081 20028c00 32 1 y: MULADD_IEEE R0.y, KC0[1].x, R1.z, R0.w 0166 61002481 40028401 1 z: MULADD_IEEE R0.z, KC0[1].y, R1.z, R1.y 0168 e1002881 60028001 1 w: MULADD_IEEE R0.w, KC0[1].z, R1.z, R1.x 0170 81800803 40600210 33 z: MUL_IEEE R3.z, R3.z, R0.w 0172 80800003 00600210 34 x: MUL_IEEE R3.x, R3.x, R0.y 0174 81000403 20600210 35 y: MUL_IEEE R3.y, R3.y, R0.z 0004 c0018000 94600688 EXPORT_DONE PIXEL 0 R3.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], GENERIC[19] DCL OUT[2], GENERIC[20] DCL OUT[3], GENERIC[21] DCL CONST[0..13] DCL TEMP[0..4], LOCAL 0: MUL TEMP[0], CONST[2], IN[2].xxxx 1: MAD TEMP[0], CONST[3], IN[2].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[4], IN[2].zzzz, TEMP[0] 3: ADD TEMP[0], TEMP[0], CONST[5] 4: MUL TEMP[1], CONST[6], CONST[13].xxxx 5: MAD TEMP[1], CONST[7], CONST[13].yyyy, TEMP[1] 6: MAD TEMP[1], CONST[8], CONST[13].zzzz, TEMP[1] 7: MAD TEMP[1], CONST[9], CONST[13].wwww, TEMP[1] 8: MUL TEMP[2], CONST[6], CONST[12].xxxx 9: MAD TEMP[2], CONST[7], CONST[12].yyyy, TEMP[2] 10: MAD TEMP[2], CONST[8], CONST[12].zzzz, TEMP[2] 11: MAD TEMP[2], CONST[9], CONST[12].wwww, TEMP[2] 12: MUL TEMP[3], CONST[6], CONST[11].xxxx 13: MAD TEMP[3], CONST[7], CONST[11].yyyy, TEMP[3] 14: MAD TEMP[3], CONST[8], CONST[11].zzzz, TEMP[3] 15: MAD TEMP[3], CONST[9], CONST[11].wwww, TEMP[3] 16: MUL TEMP[4], CONST[6], CONST[10].xxxx 17: MAD TEMP[4], CONST[7], CONST[10].yyyy, TEMP[4] 18: MAD TEMP[4], CONST[8], CONST[10].zzzz, TEMP[4] 19: MAD TEMP[4], CONST[9], CONST[10].wwww, TEMP[4] 20: MUL TEMP[4], TEMP[4], TEMP[0].xxxx 21: MAD TEMP[3], TEMP[3], TEMP[0].yyyy, TEMP[4] 22: MAD TEMP[2], TEMP[2], TEMP[0].zzzz, TEMP[3] 23: MAD TEMP[1], TEMP[1], TEMP[0].wwww, TEMP[2] 24: ADD TEMP[0].xyz, CONST[1].xyzz, -TEMP[0].xyzz 25: MOV TEMP[2].xy, IN[0].xyxx 26: MOV TEMP[2].zw, TEMP[0].yyxy 27: MOV TEMP[0].x, TEMP[0].zzzz 28: MOV TEMP[0].yzw, CONST[0].yxyz 29: MUL TEMP[3], CONST[2], IN[1].xxxx 30: MAD TEMP[3], CONST[3], IN[1].yyyy, TEMP[3] 31: MAD TEMP[3].xyz, CONST[4], IN[1].zzzz, TEMP[3] 32: MOV TEMP[3].xyz, TEMP[3].xyzx 33: MOV OUT[3], TEMP[3] 34: MOV OUT[2], TEMP[0] 35: MOV OUT[1], TEMP[2] 36: MOV OUT[0], TEMP[1] 37: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = call float @llvm.R600.load.input(i32 12) %9 = call float @llvm.R600.load.input(i32 13) %10 = call float @llvm.R600.load.input(i32 14) %11 = call float @llvm.R600.load.input(i32 15) %12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %13 = extractelement <4 x float> %12, i32 0 %14 = fmul float %13, %8 %15 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %16 = extractelement <4 x float> %15, i32 1 %17 = fmul float %16, %8 %18 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %19 = extractelement <4 x float> %18, i32 2 %20 = fmul float %19, %8 %21 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %22 = extractelement <4 x float> %21, i32 3 %23 = fmul float %22, %8 %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %25 = extractelement <4 x float> %24, i32 0 %26 = fmul float %25, %9 %27 = fadd float %26, %14 %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %29 = extractelement <4 x float> %28, i32 1 %30 = fmul float %29, %9 %31 = fadd float %30, %17 %32 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %33 = extractelement <4 x float> %32, i32 2 %34 = fmul float %33, %9 %35 = fadd float %34, %20 %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %37 = extractelement <4 x float> %36, i32 3 %38 = fmul float %37, %9 %39 = fadd float %38, %23 %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %41 = extractelement <4 x float> %40, i32 0 %42 = fmul float %41, %10 %43 = fadd float %42, %27 %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %45 = extractelement <4 x float> %44, i32 1 %46 = fmul float %45, %10 %47 = fadd float %46, %31 %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %49 = extractelement <4 x float> %48, i32 2 %50 = fmul float %49, %10 %51 = fadd float %50, %35 %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %53 = extractelement <4 x float> %52, i32 3 %54 = fmul float %53, %10 %55 = fadd float %54, %39 %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %57 = extractelement <4 x float> %56, i32 0 %58 = fadd float %43, %57 %59 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %60 = extractelement <4 x float> %59, i32 1 %61 = fadd float %47, %60 %62 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %63 = extractelement <4 x float> %62, i32 2 %64 = fadd float %51, %63 %65 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %66 = extractelement <4 x float> %65, i32 3 %67 = fadd float %55, %66 %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %69 = extractelement <4 x float> %68, i32 0 %70 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %71 = extractelement <4 x float> %70, i32 0 %72 = fmul float %69, %71 %73 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %74 = extractelement <4 x float> %73, i32 1 %75 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %76 = extractelement <4 x float> %75, i32 0 %77 = fmul float %74, %76 %78 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %79 = extractelement <4 x float> %78, i32 2 %80 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %81 = extractelement <4 x float> %80, i32 0 %82 = fmul float %79, %81 %83 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %84 = extractelement <4 x float> %83, i32 3 %85 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %86 = extractelement <4 x float> %85, i32 0 %87 = fmul float %84, %86 %88 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %89 = extractelement <4 x float> %88, i32 0 %90 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %91 = extractelement <4 x float> %90, i32 1 %92 = fmul float %89, %91 %93 = fadd float %92, %72 %94 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %95 = extractelement <4 x float> %94, i32 1 %96 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %97 = extractelement <4 x float> %96, i32 1 %98 = fmul float %95, %97 %99 = fadd float %98, %77 %100 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %101 = extractelement <4 x float> %100, i32 2 %102 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %103 = extractelement <4 x float> %102, i32 1 %104 = fmul float %101, %103 %105 = fadd float %104, %82 %106 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %107 = extractelement <4 x float> %106, i32 3 %108 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %109 = extractelement <4 x float> %108, i32 1 %110 = fmul float %107, %109 %111 = fadd float %110, %87 %112 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %113 = extractelement <4 x float> %112, i32 0 %114 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %115 = extractelement <4 x float> %114, i32 2 %116 = fmul float %113, %115 %117 = fadd float %116, %93 %118 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %119 = extractelement <4 x float> %118, i32 1 %120 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %121 = extractelement <4 x float> %120, i32 2 %122 = fmul float %119, %121 %123 = fadd float %122, %99 %124 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %125 = extractelement <4 x float> %124, i32 2 %126 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %127 = extractelement <4 x float> %126, i32 2 %128 = fmul float %125, %127 %129 = fadd float %128, %105 %130 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %131 = extractelement <4 x float> %130, i32 3 %132 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %133 = extractelement <4 x float> %132, i32 2 %134 = fmul float %131, %133 %135 = fadd float %134, %111 %136 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %137 = extractelement <4 x float> %136, i32 0 %138 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %139 = extractelement <4 x float> %138, i32 3 %140 = fmul float %137, %139 %141 = fadd float %140, %117 %142 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %143 = extractelement <4 x float> %142, i32 1 %144 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %145 = extractelement <4 x float> %144, i32 3 %146 = fmul float %143, %145 %147 = fadd float %146, %123 %148 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %149 = extractelement <4 x float> %148, i32 2 %150 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %151 = extractelement <4 x float> %150, i32 3 %152 = fmul float %149, %151 %153 = fadd float %152, %129 %154 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %155 = extractelement <4 x float> %154, i32 3 %156 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %157 = extractelement <4 x float> %156, i32 3 %158 = fmul float %155, %157 %159 = fadd float %158, %135 %160 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %161 = extractelement <4 x float> %160, i32 0 %162 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %163 = extractelement <4 x float> %162, i32 0 %164 = fmul float %161, %163 %165 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %166 = extractelement <4 x float> %165, i32 1 %167 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %168 = extractelement <4 x float> %167, i32 0 %169 = fmul float %166, %168 %170 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %171 = extractelement <4 x float> %170, i32 2 %172 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %173 = extractelement <4 x float> %172, i32 0 %174 = fmul float %171, %173 %175 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %176 = extractelement <4 x float> %175, i32 3 %177 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %178 = extractelement <4 x float> %177, i32 0 %179 = fmul float %176, %178 %180 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %181 = extractelement <4 x float> %180, i32 0 %182 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %183 = extractelement <4 x float> %182, i32 1 %184 = fmul float %181, %183 %185 = fadd float %184, %164 %186 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %187 = extractelement <4 x float> %186, i32 1 %188 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %189 = extractelement <4 x float> %188, i32 1 %190 = fmul float %187, %189 %191 = fadd float %190, %169 %192 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %193 = extractelement <4 x float> %192, i32 2 %194 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %195 = extractelement <4 x float> %194, i32 1 %196 = fmul float %193, %195 %197 = fadd float %196, %174 %198 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %199 = extractelement <4 x float> %198, i32 3 %200 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %201 = extractelement <4 x float> %200, i32 1 %202 = fmul float %199, %201 %203 = fadd float %202, %179 %204 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %205 = extractelement <4 x float> %204, i32 0 %206 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %207 = extractelement <4 x float> %206, i32 2 %208 = fmul float %205, %207 %209 = fadd float %208, %185 %210 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %211 = extractelement <4 x float> %210, i32 1 %212 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %213 = extractelement <4 x float> %212, i32 2 %214 = fmul float %211, %213 %215 = fadd float %214, %191 %216 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %217 = extractelement <4 x float> %216, i32 2 %218 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %219 = extractelement <4 x float> %218, i32 2 %220 = fmul float %217, %219 %221 = fadd float %220, %197 %222 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %223 = extractelement <4 x float> %222, i32 3 %224 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %225 = extractelement <4 x float> %224, i32 2 %226 = fmul float %223, %225 %227 = fadd float %226, %203 %228 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %229 = extractelement <4 x float> %228, i32 0 %230 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %231 = extractelement <4 x float> %230, i32 3 %232 = fmul float %229, %231 %233 = fadd float %232, %209 %234 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %235 = extractelement <4 x float> %234, i32 1 %236 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %237 = extractelement <4 x float> %236, i32 3 %238 = fmul float %235, %237 %239 = fadd float %238, %215 %240 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %241 = extractelement <4 x float> %240, i32 2 %242 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %243 = extractelement <4 x float> %242, i32 3 %244 = fmul float %241, %243 %245 = fadd float %244, %221 %246 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %247 = extractelement <4 x float> %246, i32 3 %248 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %249 = extractelement <4 x float> %248, i32 3 %250 = fmul float %247, %249 %251 = fadd float %250, %227 %252 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %253 = extractelement <4 x float> %252, i32 0 %254 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %255 = extractelement <4 x float> %254, i32 0 %256 = fmul float %253, %255 %257 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %258 = extractelement <4 x float> %257, i32 1 %259 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %260 = extractelement <4 x float> %259, i32 0 %261 = fmul float %258, %260 %262 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %263 = extractelement <4 x float> %262, i32 2 %264 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %265 = extractelement <4 x float> %264, i32 0 %266 = fmul float %263, %265 %267 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %268 = extractelement <4 x float> %267, i32 3 %269 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %270 = extractelement <4 x float> %269, i32 0 %271 = fmul float %268, %270 %272 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %273 = extractelement <4 x float> %272, i32 0 %274 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %275 = extractelement <4 x float> %274, i32 1 %276 = fmul float %273, %275 %277 = fadd float %276, %256 %278 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %279 = extractelement <4 x float> %278, i32 1 %280 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %281 = extractelement <4 x float> %280, i32 1 %282 = fmul float %279, %281 %283 = fadd float %282, %261 %284 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %285 = extractelement <4 x float> %284, i32 2 %286 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %287 = extractelement <4 x float> %286, i32 1 %288 = fmul float %285, %287 %289 = fadd float %288, %266 %290 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %291 = extractelement <4 x float> %290, i32 3 %292 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %293 = extractelement <4 x float> %292, i32 1 %294 = fmul float %291, %293 %295 = fadd float %294, %271 %296 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %297 = extractelement <4 x float> %296, i32 0 %298 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %299 = extractelement <4 x float> %298, i32 2 %300 = fmul float %297, %299 %301 = fadd float %300, %277 %302 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %303 = extractelement <4 x float> %302, i32 1 %304 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %305 = extractelement <4 x float> %304, i32 2 %306 = fmul float %303, %305 %307 = fadd float %306, %283 %308 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %309 = extractelement <4 x float> %308, i32 2 %310 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %311 = extractelement <4 x float> %310, i32 2 %312 = fmul float %309, %311 %313 = fadd float %312, %289 %314 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %315 = extractelement <4 x float> %314, i32 3 %316 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %317 = extractelement <4 x float> %316, i32 2 %318 = fmul float %315, %317 %319 = fadd float %318, %295 %320 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %321 = extractelement <4 x float> %320, i32 0 %322 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %323 = extractelement <4 x float> %322, i32 3 %324 = fmul float %321, %323 %325 = fadd float %324, %301 %326 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %327 = extractelement <4 x float> %326, i32 1 %328 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %329 = extractelement <4 x float> %328, i32 3 %330 = fmul float %327, %329 %331 = fadd float %330, %307 %332 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %333 = extractelement <4 x float> %332, i32 2 %334 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %335 = extractelement <4 x float> %334, i32 3 %336 = fmul float %333, %335 %337 = fadd float %336, %313 %338 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %339 = extractelement <4 x float> %338, i32 3 %340 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %341 = extractelement <4 x float> %340, i32 3 %342 = fmul float %339, %341 %343 = fadd float %342, %319 %344 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %345 = extractelement <4 x float> %344, i32 0 %346 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %347 = extractelement <4 x float> %346, i32 0 %348 = fmul float %345, %347 %349 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %350 = extractelement <4 x float> %349, i32 1 %351 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %352 = extractelement <4 x float> %351, i32 0 %353 = fmul float %350, %352 %354 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %355 = extractelement <4 x float> %354, i32 2 %356 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %357 = extractelement <4 x float> %356, i32 0 %358 = fmul float %355, %357 %359 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %360 = extractelement <4 x float> %359, i32 3 %361 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %362 = extractelement <4 x float> %361, i32 0 %363 = fmul float %360, %362 %364 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %365 = extractelement <4 x float> %364, i32 0 %366 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %367 = extractelement <4 x float> %366, i32 1 %368 = fmul float %365, %367 %369 = fadd float %368, %348 %370 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %371 = extractelement <4 x float> %370, i32 1 %372 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %373 = extractelement <4 x float> %372, i32 1 %374 = fmul float %371, %373 %375 = fadd float %374, %353 %376 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %377 = extractelement <4 x float> %376, i32 2 %378 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %379 = extractelement <4 x float> %378, i32 1 %380 = fmul float %377, %379 %381 = fadd float %380, %358 %382 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %383 = extractelement <4 x float> %382, i32 3 %384 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %385 = extractelement <4 x float> %384, i32 1 %386 = fmul float %383, %385 %387 = fadd float %386, %363 %388 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %389 = extractelement <4 x float> %388, i32 0 %390 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %391 = extractelement <4 x float> %390, i32 2 %392 = fmul float %389, %391 %393 = fadd float %392, %369 %394 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %395 = extractelement <4 x float> %394, i32 1 %396 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %397 = extractelement <4 x float> %396, i32 2 %398 = fmul float %395, %397 %399 = fadd float %398, %375 %400 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %401 = extractelement <4 x float> %400, i32 2 %402 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %403 = extractelement <4 x float> %402, i32 2 %404 = fmul float %401, %403 %405 = fadd float %404, %381 %406 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %407 = extractelement <4 x float> %406, i32 3 %408 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %409 = extractelement <4 x float> %408, i32 2 %410 = fmul float %407, %409 %411 = fadd float %410, %387 %412 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %413 = extractelement <4 x float> %412, i32 0 %414 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %415 = extractelement <4 x float> %414, i32 3 %416 = fmul float %413, %415 %417 = fadd float %416, %393 %418 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %419 = extractelement <4 x float> %418, i32 1 %420 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %421 = extractelement <4 x float> %420, i32 3 %422 = fmul float %419, %421 %423 = fadd float %422, %399 %424 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %425 = extractelement <4 x float> %424, i32 2 %426 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %427 = extractelement <4 x float> %426, i32 3 %428 = fmul float %425, %427 %429 = fadd float %428, %405 %430 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %431 = extractelement <4 x float> %430, i32 3 %432 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %433 = extractelement <4 x float> %432, i32 3 %434 = fmul float %431, %433 %435 = fadd float %434, %411 %436 = fmul float %417, %58 %437 = fmul float %423, %58 %438 = fmul float %429, %58 %439 = fmul float %435, %58 %440 = fmul float %325, %61 %441 = fadd float %440, %436 %442 = fmul float %331, %61 %443 = fadd float %442, %437 %444 = fmul float %337, %61 %445 = fadd float %444, %438 %446 = fmul float %343, %61 %447 = fadd float %446, %439 %448 = fmul float %233, %64 %449 = fadd float %448, %441 %450 = fmul float %239, %64 %451 = fadd float %450, %443 %452 = fmul float %245, %64 %453 = fadd float %452, %445 %454 = fmul float %251, %64 %455 = fadd float %454, %447 %456 = fmul float %141, %67 %457 = fadd float %456, %449 %458 = fmul float %147, %67 %459 = fadd float %458, %451 %460 = fmul float %153, %67 %461 = fadd float %460, %453 %462 = fmul float %159, %67 %463 = fadd float %462, %455 %464 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %465 = extractelement <4 x float> %464, i32 0 %466 = fsub float -0,000000e+00, %58 %467 = fadd float %465, %466 %468 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %469 = extractelement <4 x float> %468, i32 1 %470 = fsub float -0,000000e+00, %61 %471 = fadd float %469, %470 %472 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %473 = extractelement <4 x float> %472, i32 2 %474 = fsub float -0,000000e+00, %64 %475 = fadd float %473, %474 %476 = load <4 x float> addrspace(8)* null %477 = extractelement <4 x float> %476, i32 0 %478 = load <4 x float> addrspace(8)* null %479 = extractelement <4 x float> %478, i32 1 %480 = load <4 x float> addrspace(8)* null %481 = extractelement <4 x float> %480, i32 2 %482 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %483 = extractelement <4 x float> %482, i32 0 %484 = fmul float %483, %4 %485 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %486 = extractelement <4 x float> %485, i32 1 %487 = fmul float %486, %4 %488 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %489 = extractelement <4 x float> %488, i32 2 %490 = fmul float %489, %4 %491 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %492 = extractelement <4 x float> %491, i32 3 %493 = fmul float %492, %4 %494 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %495 = extractelement <4 x float> %494, i32 0 %496 = fmul float %495, %5 %497 = fadd float %496, %484 %498 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %499 = extractelement <4 x float> %498, i32 1 %500 = fmul float %499, %5 %501 = fadd float %500, %487 %502 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %503 = extractelement <4 x float> %502, i32 2 %504 = fmul float %503, %5 %505 = fadd float %504, %490 %506 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %507 = extractelement <4 x float> %506, i32 3 %508 = fmul float %507, %5 %509 = fadd float %508, %493 %510 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %511 = extractelement <4 x float> %510, i32 0 %512 = fmul float %511, %6 %513 = fadd float %512, %497 %514 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %515 = extractelement <4 x float> %514, i32 1 %516 = fmul float %515, %6 %517 = fadd float %516, %501 %518 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %519 = extractelement <4 x float> %518, i32 2 %520 = fmul float %519, %6 %521 = fadd float %520, %505 %522 = insertelement <4 x float> undef, float %457, i32 0 %523 = insertelement <4 x float> %522, float %459, i32 1 %524 = insertelement <4 x float> %523, float %461, i32 2 %525 = insertelement <4 x float> %524, float %463, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %525, i32 60, i32 1) %526 = insertelement <4 x float> undef, float %0, i32 0 %527 = insertelement <4 x float> %526, float %1, i32 1 %528 = insertelement <4 x float> %527, float %467, i32 2 %529 = insertelement <4 x float> %528, float %471, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %529, i32 0, i32 2) %530 = insertelement <4 x float> undef, float %475, i32 0 %531 = insertelement <4 x float> %530, float %477, i32 1 %532 = insertelement <4 x float> %531, float %479, i32 2 %533 = insertelement <4 x float> %532, float %481, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %533, i32 1, i32 2) %534 = insertelement <4 x float> undef, float %513, i32 0 %535 = insertelement <4 x float> %534, float %517, i32 1 %536 = insertelement <4 x float> %535, float %521, i32 2 %537 = insertelement <4 x float> %536, float %509, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %537, i32 2, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #47 =========================================== VS/RS880/R600 ===== ===== 246 dw ===== 16 gprs ===== 1 stack ======================================= 0000 00000000 89800000 CALL_FS @0 0002 80000008 a1c80000 ALU 115 @16 KC0[CB0:0-31] 0016 80006482 60000210 1 w: MUL_IEEE R0.w, KC0[2].y, R3.x 0018 00806483 40228cfe 2 z: MULADD_IEEE R1.z, KC0[3].y, R3.y, PV.w 0020 80006082 60000210 w: MUL_IEEE R0.w, KC0[2].x, R3.x 0022 00806083 40028cfe 3 z: MULADD_IEEE R0.z, KC0[3].x, R3.y, PV.w 0024 81006484 600288fe w: MULADD_IEEE R0.w, KC0[4].y, R3.z, PV.z 0026 0090acfe 40200010 4 z: ADD R1.z, PV.w, KC0[5].y 0028 81006084 600288fe w: MULADD_IEEE R0.w, KC0[4].x, R3.z, PV.z 0030 0010acfe 40800010 5 z: ADD R4.z, PV.w, KC0[5].x 0032 831fc481 60000010 w: ADD R0.w, KC0[1].y, -PV.z 0034 831fc081 40000010 6 z: ADD R0.z, KC0[1].x, -PV.z 0036 80000401 20001910 7 y: MOV R0.y, R1.y 0038 00000001 00001910 8 x: MOV R0.x, R1.x 0040 00004c82 40a00210 z: MUL_IEEE R5.z, KC0[2].w, R2.x 0042 80004882 60200210 w: MUL_IEEE R1.w, KC0[2].z, R2.x 0044 00004482 20200210 9 y: MUL_IEEE R1.y, KC0[2].y, R2.x 0046 00804883 40c28cfe z: MULADD_IEEE R6.z, KC0[3].z, R2.y, PV.w 0048 80804c83 60a288fe w: MULADD_IEEE R5.w, KC0[3].w, R2.y, PV.z 0050 01004884 40a288fe 10 z: MULADD_IEEE R5.z, KC0[4].z, R2.z, PV.z 0052 80804483 602284fe w: MULADD_IEEE R1.w, KC0[3].y, R2.y, PV.y 0054 81004484 20a28cfe 11 y: MULADD_IEEE R5.y, KC0[4].y, R2.z, PV.w 0056 0011a086 40c00210 12 z: MUL_IEEE R6.z, KC0[6].x, KC0[13].x 0058 8011a486 60200210 w: MUL_IEEE R1.w, KC0[6].y, KC0[13].x 0060 0091a487 40e28cfe 13 z: MULADD_IEEE R7.z, KC0[7].y, KC0[13].y, PV.w 0062 8091a087 602288fe w: MULADD_IEEE R1.w, KC0[7].x, KC0[13].y, PV.z 0064 0111a088 40c28cfe 14 z: MULADD_IEEE R6.z, KC0[8].x, KC0[13].z, PV.w 0066 8111a488 602288fe w: MULADD_IEEE R1.w, KC0[8].y, KC0[13].z, PV.z 0068 00118486 40e00210 15 z: MUL_IEEE R7.z, KC0[6].y, KC0[12].x 0070 80118086 60400210 w: MUL_IEEE R2.w, KC0[6].x, KC0[12].x 0072 00918087 41228cfe 16 z: MULADD_IEEE R9.z, KC0[7].x, KC0[12].y, PV.w 0074 80918487 604288fe w: MULADD_IEEE R2.w, KC0[7].y, KC0[12].y, PV.z 0076 01118488 41028cfe 17 z: MULADD_IEEE R8.z, KC0[8].y, KC0[12].z, PV.w 0078 81118088 604288fe w: MULADD_IEEE R2.w, KC0[8].x, KC0[12].z, PV.z 0080 01918089 40e28cfe 18 z: MULADD_IEEE R7.z, KC0[9].x, KC0[12].w, PV.w 0082 81918489 606288fe w: MULADD_IEEE R3.w, KC0[9].y, KC0[12].w, PV.z 0084 00004082 41200210 19 z: MUL_IEEE R9.z, KC0[2].x, R2.x 0086 80006882 60440210 w: MUL_IEEE R2.w, KC0[2].z, R3.x VEC_021 0088 00806883 41028cfe 20 z: MULADD_IEEE R8.z, KC0[3].z, R3.y, PV.w 0090 80804083 604688fe w: MULADD_IEEE R2.w, KC0[3].x, R2.y, PV.z VEC_021 0092 01004084 00a28cfe 21 x: MULADD_IEEE R5.x, KC0[4].x, R2.z, PV.w 0094 81006884 604a88fe w: MULADD_IEEE R2.w, KC0[4].z, R3.z, PV.z VEC_120 0096 0110acfe 41000010 22 z: ADD R8.z, PV.w, KC0[5].z 0098 80006c82 60400210 w: MUL_IEEE R2.w, KC0[2].w, R3.x 0100 00806c83 41228cfe 23 z: MULADD_IEEE R9.z, KC0[3].w, R3.y, PV.w 0102 831fc881 60400010 w: ADD R2.w, KC0[1].z, -PV.z 0104 00000480 20401910 24 y: MOV R2.y, KC0[0].y 0106 81006c84 608288fe w: MULADD_IEEE R4.w, KC0[4].w, R3.z, PV.z 0108 00000080 00401910 25 x: MOV R2.x, KC0[0].x 0110 8190acfe 60800010 w: ADD R4.w, PV.w, KC0[5].w 0112 0011ac86 40600210 26 z: MUL_IEEE R3.z, KC0[6].w, KC0[13].x 0114 8011a886 60c00210 w: MUL_IEEE R6.w, KC0[6].z, KC0[13].x 0116 0091a887 41428cfe 27 z: MULADD_IEEE R10.z, KC0[7].z, KC0[13].y, PV.w 0118 8091ac87 60c288fe w: MULADD_IEEE R6.w, KC0[7].w, KC0[13].y, PV.z 0120 0111ac88 41228cfe 28 z: MULADD_IEEE R9.z, KC0[8].w, KC0[13].z, PV.w 0122 8111a888 60c288fe w: MULADD_IEEE R6.w, KC0[8].z, KC0[13].z, PV.z 0124 0191a889 40628cfe 29 z: MULADD_IEEE R3.z, KC0[9].z, KC0[13].w, PV.w 0126 8191ac89 60c288fe w: MULADD_IEEE R6.w, KC0[9].w, KC0[13].w, PV.z 0128 00116086 41200210 30 z: MUL_IEEE R9.z, KC0[6].x, KC0[11].x 0130 80116486 60e00210 w: MUL_IEEE R7.w, KC0[6].y, KC0[11].x 0132 00916487 41428cfe 31 z: MULADD_IEEE R10.z, KC0[7].y, KC0[11].y, PV.w 0134 80916087 60e288fe w: MULADD_IEEE R7.w, KC0[7].x, KC0[11].y, PV.z 0136 01116088 41228cfe 32 z: MULADD_IEEE R9.z, KC0[8].x, KC0[11].z, PV.w 0138 81116488 60e288fe w: MULADD_IEEE R7.w, KC0[8].y, KC0[11].z, PV.z 0140 00114486 41400210 33 z: MUL_IEEE R10.z, KC0[6].y, KC0[10].x 0142 80114086 61000210 w: MUL_IEEE R8.w, KC0[6].x, KC0[10].x 0144 00914087 41628cfe 34 z: MULADD_IEEE R11.z, KC0[7].x, KC0[10].y, PV.w 0146 80914487 610288fe w: MULADD_IEEE R8.w, KC0[7].y, KC0[10].y, PV.z 0148 01114488 41828cfe 35 z: MULADD_IEEE R12.z, KC0[8].y, KC0[10].z, PV.w 0150 81114088 610288fe w: MULADD_IEEE R8.w, KC0[8].x, KC0[10].z, PV.z 0152 01914089 41428cfe 36 z: MULADD_IEEE R10.z, KC0[9].x, KC0[10].w, PV.w 0154 81914489 610288fe w: MULADD_IEEE R8.w, KC0[9].y, KC0[10].w, PV.z 0156 00118886 41600210 37 z: MUL_IEEE R11.z, KC0[6].z, KC0[12].x 0158 80118c86 61200210 w: MUL_IEEE R9.w, KC0[6].w, KC0[12].x 0160 00918c87 41828cfe 38 z: MULADD_IEEE R12.z, KC0[7].w, KC0[12].y, PV.w 0162 80918887 612288fe w: MULADD_IEEE R9.w, KC0[7].z, KC0[12].y, PV.z 0164 01118888 41628cfe 39 z: MULADD_IEEE R11.z, KC0[8].z, KC0[12].z, PV.w 0166 81118c88 612288fe w: MULADD_IEEE R9.w, KC0[8].w, KC0[12].z, PV.z 0168 00116c86 41800210 40 z: MUL_IEEE R12.z, KC0[6].w, KC0[11].x 0170 80116886 61400210 w: MUL_IEEE R10.w, KC0[6].z, KC0[11].x 0172 00916887 41a28cfe 41 z: MULADD_IEEE R13.z, KC0[7].z, KC0[11].y, PV.w 0174 80916c87 614288fe w: MULADD_IEEE R10.w, KC0[7].w, KC0[11].y, PV.z 0176 01116c88 41828cfe 42 z: MULADD_IEEE R12.z, KC0[8].w, KC0[11].z, PV.w 0178 81116888 614288fe w: MULADD_IEEE R10.w, KC0[8].z, KC0[11].z, PV.z 0180 00114886 41a00210 43 z: MUL_IEEE R13.z, KC0[6].z, KC0[10].x 0182 80114c86 61600210 w: MUL_IEEE R11.w, KC0[6].w, KC0[10].x 0184 00914c87 41c28cfe 44 z: MULADD_IEEE R14.z, KC0[7].w, KC0[10].y, PV.w 0186 80914887 616288fe w: MULADD_IEEE R11.w, KC0[7].z, KC0[10].y, PV.z 0188 01114888 41e28cfe 45 z: MULADD_IEEE R15.z, KC0[8].z, KC0[10].z, PV.w 0190 81114c88 616288fe w: MULADD_IEEE R11.w, KC0[8].w, KC0[10].z, PV.z 0192 01914c89 41a28cfe 46 z: MULADD_IEEE R13.z, KC0[9].w, KC0[10].w, PV.w 0194 81914889 616288fe w: MULADD_IEEE R11.w, KC0[9].z, KC0[10].w, PV.z 0196 01008cfe 00200210 47 x: MUL_IEEE R1.x, PV.w, R4.z 0198 01916889 20228c0a y: MULADD_IEEE R1.y, KC0[9].z, KC0[11].w, R10.w 0200 010088fe 41a00210 z: MUL_IEEE R13.z, PV.z, R4.z 0202 81916c89 6142880c w: MULADD_IEEE R10.w, KC0[9].w, KC0[11].w, R12.z 0204 01002cfe 006288fe 48 x: MULADD_IEEE R3.x, PV.w, R1.z, PV.z 0206 01918c89 20628c09 y: MULADD_IEEE R3.y, KC0[9].w, KC0[12].w, R9.w 0208 010024fe 418280fe z: MULADD_IEEE R12.z, PV.y, R1.z, PV.x 0210 81918889 6122880b w: MULADD_IEEE R9.w, KC0[9].z, KC0[12].w, R11.z 0212 01010cfe 002288fe 49 x: MULADD_IEEE R1.x, PV.w, R8.z, PV.z 0214 010104fe 202280fe y: MULADD_IEEE R1.y, PV.y, R8.z, PV.x 0216 01008c08 41640210 z: MUL_IEEE R11.z, R8.w, R4.z VEC_021 0218 81916489 60e28c07 w: MULADD_IEEE R7.w, KC0[9].y, KC0[11].w, R7.w 0220 01002cfe 006288fe 50 x: MULADD_IEEE R3.x, PV.w, R1.z, PV.z 0222 8100880a 20640210 y: MUL_IEEE R3.y, R10.z, R4.z VEC_021 0224 01916089 40828809 51 z: MULADD_IEEE R4.z, KC0[9].x, KC0[11].w, R9.z 0226 81808c06 61228401 w: MULADD_IEEE R9.w, R6.w, R4.w, R1.y 0228 010028fe 00828403 52 x: MULADD_IEEE R4.x, PV.z, R1.z, R3.y 0230 01010c03 20268003 y: MULADD_IEEE R1.y, R3.w, R8.z, R3.x VEC_021 0232 01808803 41228001 z: MULADD_IEEE R9.z, R3.z, R4.w, R1.x 0234 8191a489 60228c01 w: MULADD_IEEE R1.w, KC0[9].y, KC0[13].w, R1.w 0236 01808cfe 212284fe 53 y: MULADD_IEEE R9.y, PV.w, R4.w, PV.y 0238 01010807 402280fe z: MULADD_IEEE R1.z, R7.z, R8.z, PV.x 0240 8191a089 60228806 w: MULADD_IEEE R1.w, KC0[9].x, KC0[13].w, R6.z 0242 01808cfe 012288fe 54 x: MULADD_IEEE R9.x, PV.w, R4.w, PV.z 0244 80000880 40401910 z: MOV R2.z, KC0[0].z 0004 c004a03c 94400688 EXPORT_DONE POS 60 R9.xyzw VPM 0006 c0004000 93c00688 EXPORT PARAM 0 R0.xyzw VPM 0008 c0014001 93c004d1 EXPORT PARAM 1 R2.yzwz VPM 0010 c002c002 94600688 EXPORT_DONE PARAM 2 R5.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_FLOAT, } {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 1, src_format = PIPE_FORMAT_R32G32B32_FLOAT, } {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 2, src_format = PIPE_FORMAT_R32G32B32_FLOAT, } ===== SHADER #48 ======================================== FETCH/RS880/R600 ===== ===== 16 dw ===== 4 gprs ===== 0 stack ========================================= 0000 00000002 81000800 VTX 3 @4 0004 7c00a000 87961001 00080000 VFETCH R1.xy01, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:30 NUM:0 COMP:0 MODE:1) 0008 7c00a100 8c151002 00080000 VFETCH R2.xyz1, R0.x, RID:161 VERTEX MFC:31 UCF:0 FMT(DTA:48 NUM:0 COMP:0 MODE:1) 0012 7c00a200 8c151003 00080000 VFETCH R3.xyz1, R0.x, RID:162 VERTEX MFC:31 UCF:0 FMT(DTA:48 NUM:0 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[19], PERSPECTIVE DCL IN[1], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0..1] DCL TEMP[0..4], LOCAL IMM[0] FLT32 { 0,7500, 0,2500, 0,0000, 2,0000} 0: MOV TEMP[0].z, IN[1].xxxx 1: MOV TEMP[0].xy, IN[0].zwzz 2: MOV TEMP[1].xy, IN[0].xyyy 3: TEX TEMP[1], TEMP[1], SAMP[0], 2D 4: MOV TEMP[2].xyz, CONST[1] 5: DP3 TEMP[3].x, IN[1].yzww, IN[1].yzww 6: RSQ TEMP[3].x, TEMP[3].xxxx 7: MUL TEMP[3].xyz, IN[1].yzww, TEMP[3].xxxx 8: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz 9: RSQ TEMP[4].x, TEMP[4].xxxx 10: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[4].xxxx 11: DP3 TEMP[0].x, TEMP[3].xyzz, TEMP[0].xyzz 12: MAD TEMP[0].x, TEMP[0].xxxx, IMM[0].xxxx, IMM[0].yyyy 13: SLT TEMP[3].x, IMM[0].zzzz, TEMP[0].xxxx 14: F2I TEMP[3].x, -TEMP[3] 15: UIF TEMP[3].xxxx :0 16: MUL TEMP[0], CONST[0], TEMP[0].xxxx 17: MAD TEMP[2].xyz, TEMP[0], IMM[0].wwww, CONST[1] 18: ENDIF 19: MUL TEMP[0].xyz, TEMP[1].xyzz, TEMP[2].xyzz 20: MOV TEMP[0].w, TEMP[1].wwww 21: MOV OUT[0], TEMP[0] 22: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = call float @llvm.R600.load.input(i32 4) %5 = call float @llvm.R600.load.input(i32 5) %6 = call float @llvm.R600.load.input(i32 6) %7 = call float @llvm.R600.load.input(i32 7) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float 0,000000e+00, i32 2 %11 = insertelement <4 x float> %10, float 0,000000e+00, i32 3 %12 = extractelement <4 x float> %11, i32 0 %13 = extractelement <4 x float> %11, i32 1 %14 = insertelement <4 x float> undef, float %12, i32 0 %15 = insertelement <4 x float> %14, float %13, i32 1 %16 = insertelement <4 x float> %15, float undef, i32 2 %17 = insertelement <4 x float> %16, float undef, i32 3 %18 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %17, i32 16, i32 0, i32 2) %19 = extractelement <4 x float> %18, i32 0 %20 = extractelement <4 x float> %18, i32 1 %21 = extractelement <4 x float> %18, i32 2 %22 = extractelement <4 x float> %18, i32 3 %23 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %24 = extractelement <4 x float> %23, i32 0 %25 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %26 = extractelement <4 x float> %25, i32 1 %27 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %28 = extractelement <4 x float> %27, i32 2 %29 = insertelement <4 x float> undef, float %5, i32 0 %30 = insertelement <4 x float> %29, float %6, i32 1 %31 = insertelement <4 x float> %30, float %7, i32 2 %32 = insertelement <4 x float> %31, float 0,000000e+00, i32 3 %33 = insertelement <4 x float> undef, float %5, i32 0 %34 = insertelement <4 x float> %33, float %6, i32 1 %35 = insertelement <4 x float> %34, float %7, i32 2 %36 = insertelement <4 x float> %35, float 0,000000e+00, i32 3 %37 = call float @llvm.AMDGPU.dp4(<4 x float> %32, <4 x float> %36) %38 = call float @fabs(float %37) %39 = call float @llvm.AMDGPU.rsq(float %38) %40 = fmul float %5, %39 %41 = fmul float %6, %39 %42 = fmul float %7, %39 %43 = insertelement <4 x float> undef, float %2, i32 0 %44 = insertelement <4 x float> %43, float %3, i32 1 %45 = insertelement <4 x float> %44, float %4, i32 2 %46 = insertelement <4 x float> %45, float 0,000000e+00, i32 3 %47 = insertelement <4 x float> undef, float %2, i32 0 %48 = insertelement <4 x float> %47, float %3, i32 1 %49 = insertelement <4 x float> %48, float %4, i32 2 %50 = insertelement <4 x float> %49, float 0,000000e+00, i32 3 %51 = call float @llvm.AMDGPU.dp4(<4 x float> %46, <4 x float> %50) %52 = call float @fabs(float %51) %53 = call float @llvm.AMDGPU.rsq(float %52) %54 = fmul float %2, %53 %55 = fmul float %3, %53 %56 = fmul float %4, %53 %57 = insertelement <4 x float> undef, float %40, i32 0 %58 = insertelement <4 x float> %57, float %41, i32 1 %59 = insertelement <4 x float> %58, float %42, i32 2 %60 = insertelement <4 x float> %59, float 0,000000e+00, i32 3 %61 = insertelement <4 x float> undef, float %54, i32 0 %62 = insertelement <4 x float> %61, float %55, i32 1 %63 = insertelement <4 x float> %62, float %56, i32 2 %64 = insertelement <4 x float> %63, float 0,000000e+00, i32 3 %65 = call float @llvm.AMDGPU.dp4(<4 x float> %60, <4 x float> %64) %66 = fmul float %65, 0x3FE8000000000000 %67 = fadd float %66, 0x3FD0000000000000 %68 = fcmp ult float 0,000000e+00, %67 %69 = select i1 %68, float 0x3FF0000000000000, float 0,000000e+00 %70 = fsub float -0,000000e+00, %69 %71 = fptosi float %70 to i32 %72 = bitcast i32 %71 to float %73 = bitcast float %72 to i32 %74 = icmp ne i32 %73, 0 br i1 %74, label %IF, label %ENDIF IF: ; preds = %main_body %75 = load <4 x float> addrspace(8)* null %76 = extractelement <4 x float> %75, i32 0 %77 = fmul float %76, %67 %78 = load <4 x float> addrspace(8)* null %79 = extractelement <4 x float> %78, i32 1 %80 = fmul float %79, %67 %81 = load <4 x float> addrspace(8)* null %82 = extractelement <4 x float> %81, i32 2 %83 = fmul float %82, %67 %84 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %85 = extractelement <4 x float> %84, i32 0 %86 = fmul float %77, 0x4000000000000000 %87 = fadd float %86, %85 %88 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %89 = extractelement <4 x float> %88, i32 1 %90 = fmul float %80, 0x4000000000000000 %91 = fadd float %90, %89 %92 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %93 = extractelement <4 x float> %92, i32 2 %94 = fmul float %83, 0x4000000000000000 %95 = fadd float %94, %93 br label %ENDIF ENDIF: ; preds = %main_body, %IF %temp8.0 = phi float [ %87, %IF ], [ %24, %main_body ] %temp9.0 = phi float [ %91, %IF ], [ %26, %main_body ] %temp10.0 = phi float [ %95, %IF ], [ %28, %main_body ] %96 = fmul float %19, %temp8.0 %97 = fmul float %20, %temp9.0 %98 = fmul float %21, %temp10.0 %99 = insertelement <4 x float> undef, float %96, i32 0 %100 = insertelement <4 x float> %99, float %97, i32 1 %101 = insertelement <4 x float> %100, float %98, i32 2 %102 = insertelement <4 x float> %101, float %22, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %102, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } ===== SHADER #49 =========================================== PS/RS880/R600 ===== ===== 110 dw ===== 4 gprs ===== 0 stack ======================================== 0000 00000004 80800000 TEX 1 @8 0008 00001010 f00d1002 68800000 SAMPLE R2.xyzw, R0.xyzw, RID:16, SID:0 CT:NNNN 0002 80000006 a0c00000 ALU 49 @12 KC0[CB0:0-31] 0012 80000c01 40601910 1 z: MOV R3.z, R1.w 0014 80000801 20601910 2 y: MOV R3.y, R1.z 0016 00000401 00601910 3 x: MOV R3.x, R1.y 0018 80000001 40201910 z: MOV R1.z, R1.x 0020 80000c00 20001910 4 y: MOV R0.y, R0.w 0022 00000800 00001910 5 x: MOV R0.x, R0.z 0024 800000fd 60001910 w: MOV R0.w, [0x00000000 0].x 0026 00000000 0028 00006003 00005000 6 x: DOT4 __.x, R3.x, R3.x 0030 00806403 20005000 y: DOT4 __.y, R3.y, R3.y 0032 01006803 40005010 z: DOT4 R0.z, R3.z, R3.z 0034 81800c00 60005000 w: DOT4 __.w, R0.w, R0.w 0036 80000800 60606711 7 t: RECIPSQRT_CLAMPED R3.w, |R0.z| 0038 00000000 00205000 8 x: DOT4 __.x, R0.x, R0.x 0040 00800400 20205000 y: DOT4 __.y, R0.y, R0.y 0042 01002801 40205000 z: DOT4 __.z, R1.z, R1.z 0044 81800c00 60205010 w: DOT4 R1.w, R0.w, R0.w 0046 01806003 00200210 9 x: MUL_IEEE R1.x, R3.x, R3.w 0048 01806403 20200210 y: MUL_IEEE R1.y, R3.y, R3.w 0050 81806803 40000210 z: MUL_IEEE R0.z, R3.z, R3.w 0052 80000c01 60206711 10 t: RECIPSQRT_CLAMPED R1.w, |R1.w| 0054 01802000 00000210 11 x: MUL_IEEE R0.x, R0.x, R1.w 0056 01802400 20000210 y: MUL_IEEE R0.y, R0.y, R1.w 0058 01802801 40200210 z: MUL_IEEE R1.z, R1.z, R1.w 0060 800000fd 60201910 w: MOV R1.w, [0x3f400000 0,75].x 0062 3f400000 0064 00000001 00005010 12 x: DOT4 R0.x, R1.x, R0.x 0066 00800401 20005000 y: DOT4 __.y, R1.y, R0.y 0068 01002800 40005000 z: DOT4 __.z, R0.z, R1.z 0070 81800c00 60005000 w: DOT4 __.w, R0.w, R0.w 0072 818020fe 600280fd 13 w: MULADD_IEEE R0.w, PV.x, R1.w, [0x3e800000 0,25].x 0074 3e800000 0076 819fc0f8 60200e10 14 w: SETGE_DX10 R1.w, 0, PV.w 0078 801f0cfe 00004208 15 P x: PRED_SETE_INT __.x, PV.w, 0 0080 40000881 20001910 16 0 y: MOV R0.y, KC0[1].z 0082 40000081 40001910 0 z: MOV R0.z, KC0[1].x 0084 c0000481 60001910 0 w: MOV R0.w, KC0[1].y 0086 61800880 20000210 17 1 y: MUL_IEEE R0.y, KC0[0].z, R0.w 0088 61800080 40000210 1 z: MUL_IEEE R0.z, KC0[0].x, R0.w 0090 e1800480 60200210 1 w: MUL_IEEE R1.w, KC0[0].y, R0.w 0092 61800480 20228c01 18 1 y: MULADD_IEEE R1.y, KC0[0].y, R0.w, R1.w 0094 61800080 40028800 1 z: MULADD_IEEE R0.z, KC0[0].x, R0.w, R0.z 0096 e1800880 60028400 1 w: MULADD_IEEE R0.w, KC0[0].z, R0.w, R0.y 0098 61102c00 20000010 19 1 y: ADD R0.y, R0.w, KC0[1].z 0100 60102800 40000010 1 z: ADD R0.z, R0.z, KC0[1].x 0102 e0902401 60000010 1 w: ADD R0.w, R1.y, KC0[1].y 0104 80800802 40400210 20 z: MUL_IEEE R2.z, R2.z, R0.y 0106 81000002 00400210 21 x: MUL_IEEE R2.x, R2.x, R0.z 0108 81800402 20400210 22 y: MUL_IEEE R2.y, R2.y, R0.w 0004 c0010000 94600688 EXPORT_DONE PIXEL 0 R2.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL OUT[0], POSITION DCL OUT[1], GENERIC[19] DCL OUT[2], GENERIC[20] DCL CONST[0..192] DCL TEMP[0..3], ARRAY(1), LOCAL DCL TEMP[4..7], ARRAY(2), LOCAL DCL TEMP[8..10], LOCAL DCL TEMP[11..14], ARRAY(3), LOCAL DCL TEMP[15..18], ARRAY(4), LOCAL DCL TEMP[19..22], ARRAY(5), LOCAL DCL TEMP[23..26], ARRAY(6), LOCAL DCL TEMP[27..29], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0,0000, 0,0000, 0,0000, 0,0000} IMM[1] INT32 {0, 44, 4, 0} 0: MOV TEMP[0], IMM[0].xxxx 1: MOV TEMP[1], IMM[0].xxxx 2: MOV TEMP[2], IMM[0].xxxx 3: MOV TEMP[3], IMM[0].xxxx 4: MOV TEMP[4], TEMP[0] 5: MOV TEMP[5], TEMP[1] 6: MOV TEMP[6], TEMP[2] 7: MOV TEMP[7], TEMP[3] 8: F2I TEMP[8].x, IN[0].xxxx 9: ISLT TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx 10: UIF TEMP[9].xxxx :0 11: MOV TEMP[9].x, IMM[1].xxxx 12: ELSE :0 13: ISLT TEMP[10].x, IMM[1].yyyy, TEMP[8].xxxx 14: UIF TEMP[10].xxxx :0 15: MOV TEMP[10].x, IMM[1].yyyy 16: ELSE :0 17: MOV TEMP[10].x, TEMP[8].xxxx 18: ENDIF 19: MOV TEMP[9].x, TEMP[10].xxxx 20: ENDIF 21: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 22: UARL ADDR[0].x, TEMP[8].xxxx 23: UARL ADDR[0].x, TEMP[8].xxxx 24: MAD TEMP[11], CONST[ADDR[0].x+1], IN[1].xxxx, TEMP[4] 25: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 26: UARL ADDR[0].x, TEMP[8].xxxx 27: UARL ADDR[0].x, TEMP[8].xxxx 28: MAD TEMP[12], CONST[ADDR[0].x+2], IN[1].xxxx, TEMP[5] 29: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 30: UARL ADDR[0].x, TEMP[8].xxxx 31: UARL ADDR[0].x, TEMP[8].xxxx 32: MAD TEMP[13], CONST[ADDR[0].x+3], IN[1].xxxx, TEMP[6] 33: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 34: UARL ADDR[0].x, TEMP[8].xxxx 35: UARL ADDR[0].x, TEMP[8].xxxx 36: MAD TEMP[14], CONST[ADDR[0].x+4], IN[1].xxxx, TEMP[7] 37: MOV TEMP[4], TEMP[11] 38: MOV TEMP[5], TEMP[12] 39: MOV TEMP[6], TEMP[13] 40: MOV TEMP[7], TEMP[14] 41: F2I TEMP[8].x, IN[0].yyyy 42: ISLT TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx 43: UIF TEMP[9].xxxx :0 44: MOV TEMP[9].x, IMM[1].xxxx 45: ELSE :0 46: ISLT TEMP[10].x, IMM[1].yyyy, TEMP[8].xxxx 47: UIF TEMP[10].xxxx :0 48: MOV TEMP[10].x, IMM[1].yyyy 49: ELSE :0 50: MOV TEMP[10].x, TEMP[8].xxxx 51: ENDIF 52: MOV TEMP[9].x, TEMP[10].xxxx 53: ENDIF 54: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 55: UARL ADDR[0].x, TEMP[8].xxxx 56: UARL ADDR[0].x, TEMP[8].xxxx 57: MAD TEMP[15], CONST[ADDR[0].x+1], IN[1].yyyy, TEMP[11] 58: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 59: UARL ADDR[0].x, TEMP[8].xxxx 60: UARL ADDR[0].x, TEMP[8].xxxx 61: MAD TEMP[16], CONST[ADDR[0].x+2], IN[1].yyyy, TEMP[12] 62: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 63: UARL ADDR[0].x, TEMP[8].xxxx 64: UARL ADDR[0].x, TEMP[8].xxxx 65: MAD TEMP[17], CONST[ADDR[0].x+3], IN[1].yyyy, TEMP[13] 66: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 67: UARL ADDR[0].x, TEMP[8].xxxx 68: UARL ADDR[0].x, TEMP[8].xxxx 69: MAD TEMP[18], CONST[ADDR[0].x+4], IN[1].yyyy, TEMP[14] 70: MOV TEMP[4], TEMP[15] 71: MOV TEMP[5], TEMP[16] 72: MOV TEMP[6], TEMP[17] 73: MOV TEMP[7], TEMP[18] 74: F2I TEMP[8].x, IN[0].zzzz 75: ISLT TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx 76: UIF TEMP[9].xxxx :0 77: MOV TEMP[9].x, IMM[1].xxxx 78: ELSE :0 79: ISLT TEMP[10].x, IMM[1].yyyy, TEMP[8].xxxx 80: UIF TEMP[10].xxxx :0 81: MOV TEMP[10].x, IMM[1].yyyy 82: ELSE :0 83: MOV TEMP[10].x, TEMP[8].xxxx 84: ENDIF 85: MOV TEMP[9].x, TEMP[10].xxxx 86: ENDIF 87: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 88: UARL ADDR[0].x, TEMP[8].xxxx 89: UARL ADDR[0].x, TEMP[8].xxxx 90: MAD TEMP[19], CONST[ADDR[0].x+1], IN[1].zzzz, TEMP[15] 91: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 92: UARL ADDR[0].x, TEMP[8].xxxx 93: UARL ADDR[0].x, TEMP[8].xxxx 94: MAD TEMP[20], CONST[ADDR[0].x+2], IN[1].zzzz, TEMP[16] 95: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 96: UARL ADDR[0].x, TEMP[8].xxxx 97: UARL ADDR[0].x, TEMP[8].xxxx 98: MAD TEMP[21], CONST[ADDR[0].x+3], IN[1].zzzz, TEMP[17] 99: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 100: UARL ADDR[0].x, TEMP[8].xxxx 101: UARL ADDR[0].x, TEMP[8].xxxx 102: MAD TEMP[22], CONST[ADDR[0].x+4], IN[1].zzzz, TEMP[18] 103: MOV TEMP[4], TEMP[19] 104: MOV TEMP[5], TEMP[20] 105: MOV TEMP[6], TEMP[21] 106: MOV TEMP[7], TEMP[22] 107: F2I TEMP[8].x, IN[0].wwww 108: ISLT TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx 109: UIF TEMP[9].xxxx :0 110: MOV TEMP[9].x, IMM[1].xxxx 111: ELSE :0 112: ISLT TEMP[10].x, IMM[1].yyyy, TEMP[8].xxxx 113: UIF TEMP[10].xxxx :0 114: MOV TEMP[10].x, IMM[1].yyyy 115: ELSE :0 116: MOV TEMP[10].x, TEMP[8].xxxx 117: ENDIF 118: MOV TEMP[9].x, TEMP[10].xxxx 119: ENDIF 120: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 121: UARL ADDR[0].x, TEMP[8].xxxx 122: UARL ADDR[0].x, TEMP[8].xxxx 123: MAD TEMP[23], CONST[ADDR[0].x+1], IN[1].wwww, TEMP[19] 124: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 125: UARL ADDR[0].x, TEMP[8].xxxx 126: UARL ADDR[0].x, TEMP[8].xxxx 127: MAD TEMP[24], CONST[ADDR[0].x+2], IN[1].wwww, TEMP[20] 128: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 129: UARL ADDR[0].x, TEMP[8].xxxx 130: UARL ADDR[0].x, TEMP[8].xxxx 131: MAD TEMP[25], CONST[ADDR[0].x+3], IN[1].wwww, TEMP[21] 132: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 133: UARL ADDR[0].x, TEMP[8].xxxx 134: UARL ADDR[0].x, TEMP[8].xxxx 135: MAD TEMP[26], CONST[ADDR[0].x+4], IN[1].wwww, TEMP[22] 136: MOV TEMP[4], TEMP[23] 137: MOV TEMP[5], TEMP[24] 138: MOV TEMP[6], TEMP[25] 139: MOV TEMP[7], TEMP[26] 140: MUL TEMP[8], CONST[181], TEMP[25].xxxx 141: MAD TEMP[8], CONST[182], TEMP[25].yyyy, TEMP[8] 142: MAD TEMP[8], CONST[183], TEMP[25].zzzz, TEMP[8] 143: MAD TEMP[8], CONST[184], TEMP[25].wwww, TEMP[8] 144: MUL TEMP[9], CONST[181], TEMP[24].xxxx 145: MAD TEMP[9], CONST[182], TEMP[24].yyyy, TEMP[9] 146: MAD TEMP[9], CONST[183], TEMP[24].zzzz, TEMP[9] 147: MAD TEMP[9], CONST[184], TEMP[24].wwww, TEMP[9] 148: MUL TEMP[10], CONST[181], TEMP[23].xxxx 149: MAD TEMP[10], CONST[182], TEMP[23].yyyy, TEMP[10] 150: MAD TEMP[10], CONST[183], TEMP[23].zzzz, TEMP[10] 151: MAD TEMP[10], CONST[184], TEMP[23].wwww, TEMP[10] 152: MUL TEMP[10], TEMP[10], IN[4].xxxx 153: MAD TEMP[9], TEMP[9], IN[4].yyyy, TEMP[10] 154: MAD TEMP[8], TEMP[8], IN[4].zzzz, TEMP[9] 155: MUL TEMP[9], CONST[181], TEMP[26].xxxx 156: MAD TEMP[9], CONST[182], TEMP[26].yyyy, TEMP[9] 157: MAD TEMP[9], CONST[183], TEMP[26].zzzz, TEMP[9] 158: MAD TEMP[9], CONST[184], TEMP[26].wwww, TEMP[9] 159: ADD TEMP[8], TEMP[8], TEMP[9] 160: MUL TEMP[9], CONST[185], CONST[192].xxxx 161: MAD TEMP[9], CONST[186], CONST[192].yyyy, TEMP[9] 162: MAD TEMP[9], CONST[187], CONST[192].zzzz, TEMP[9] 163: MAD TEMP[9], CONST[188], CONST[192].wwww, TEMP[9] 164: MUL TEMP[10], CONST[185], CONST[191].xxxx 165: MAD TEMP[10], CONST[186], CONST[191].yyyy, TEMP[10] 166: MAD TEMP[10], CONST[187], CONST[191].zzzz, TEMP[10] 167: MAD TEMP[10], CONST[188], CONST[191].wwww, TEMP[10] 168: MUL TEMP[27], CONST[185], CONST[190].xxxx 169: MAD TEMP[27], CONST[186], CONST[190].yyyy, TEMP[27] 170: MAD TEMP[27], CONST[187], CONST[190].zzzz, TEMP[27] 171: MAD TEMP[27], CONST[188], CONST[190].wwww, TEMP[27] 172: MUL TEMP[28], CONST[185], CONST[189].xxxx 173: MAD TEMP[28], CONST[186], CONST[189].yyyy, TEMP[28] 174: MAD TEMP[28], CONST[187], CONST[189].zzzz, TEMP[28] 175: MAD TEMP[28], CONST[188], CONST[189].wwww, TEMP[28] 176: MUL TEMP[28], TEMP[28], TEMP[8].xxxx 177: MAD TEMP[27], TEMP[27], TEMP[8].yyyy, TEMP[28] 178: MAD TEMP[10], TEMP[10], TEMP[8].zzzz, TEMP[27] 179: MAD TEMP[8], TEMP[9], TEMP[8].wwww, TEMP[10] 180: MOV TEMP[9].xy, IN[2].xyxx 181: MOV TEMP[9].zw, CONST[0].yyxy 182: MOV TEMP[10].x, CONST[0].zzzz 183: MUL TEMP[27], CONST[181], TEMP[25].xxxx 184: MAD TEMP[27], CONST[182], TEMP[25].yyyy, TEMP[27] 185: MAD TEMP[27], CONST[183], TEMP[25].zzzz, TEMP[27] 186: MAD TEMP[27], CONST[184], TEMP[25].wwww, TEMP[27] 187: MUL TEMP[28], CONST[181], TEMP[24].xxxx 188: MAD TEMP[28], CONST[182], TEMP[24].yyyy, TEMP[28] 189: MAD TEMP[28], CONST[183], TEMP[24].zzzz, TEMP[28] 190: MAD TEMP[28], CONST[184], TEMP[24].wwww, TEMP[28] 191: MUL TEMP[29], CONST[181], TEMP[23].xxxx 192: MAD TEMP[29], CONST[182], TEMP[23].yyyy, TEMP[29] 193: MAD TEMP[29], CONST[183], TEMP[23].zzzz, TEMP[29] 194: MAD TEMP[29], CONST[184], TEMP[23].wwww, TEMP[29] 195: MUL TEMP[29], TEMP[29], IN[3].xxxx 196: MAD TEMP[28], TEMP[28], IN[3].yyyy, TEMP[29] 197: MAD TEMP[27].xyz, TEMP[27], IN[3].zzzz, TEMP[28] 198: MOV TEMP[10].yzw, TEMP[27].yxyz 199: MOV OUT[1], TEMP[9] 200: MOV OUT[2], TEMP[10] 201: MOV OUT[0], TEMP[8] 202: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = call float @llvm.R600.load.input(i32 12) %9 = call float @llvm.R600.load.input(i32 13) %10 = call float @llvm.R600.load.input(i32 14) %11 = call float @llvm.R600.load.input(i32 15) %12 = call float @llvm.R600.load.input(i32 16) %13 = call float @llvm.R600.load.input(i32 17) %14 = call float @llvm.R600.load.input(i32 18) %15 = call float @llvm.R600.load.input(i32 19) %16 = call float @llvm.R600.load.input(i32 20) %17 = call float @llvm.R600.load.input(i32 21) %18 = call float @llvm.R600.load.input(i32 22) %19 = call float @llvm.R600.load.input(i32 23) %20 = fptosi float %0 to i32 %21 = bitcast i32 %20 to float %22 = bitcast float %21 to i32 %23 = icmp slt i32 %22, 0 %24 = sext i1 %23 to i32 %25 = bitcast i32 %24 to float %26 = bitcast float %25 to i32 %27 = icmp ne i32 %26, 0 br i1 %27, label %ENDIF, label %ELSE ELSE: ; preds = %main_body %28 = bitcast float %21 to i32 %29 = icmp slt i32 44, %28 %30 = sext i1 %29 to i32 %31 = bitcast i32 %30 to float %32 = bitcast float %31 to i32 %33 = icmp ne i32 %32, 0 %. = select i1 %33, float 0,000000e+00, float %21 br label %ENDIF ENDIF: ; preds = %main_body, %ELSE %temp36.0 = phi float [ %., %ELSE ], [ 0,000000e+00, %main_body ] %34 = bitcast float %temp36.0 to i32 %35 = mul i32 %34, 4 %36 = bitcast i32 %35 to float %37 = bitcast float %36 to i32 %38 = add i32 1, %37 %39 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %38 %40 = load <4 x float> addrspace(8)* %39 %41 = extractelement <4 x float> %40, i32 0 %42 = fmul float %41, %4 %43 = fadd float %42, 0,000000e+00 %44 = add i32 1, %37 %45 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %44 %46 = load <4 x float> addrspace(8)* %45 %47 = extractelement <4 x float> %46, i32 1 %48 = fmul float %47, %4 %49 = fadd float %48, 0,000000e+00 %50 = add i32 1, %37 %51 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %50 %52 = load <4 x float> addrspace(8)* %51 %53 = extractelement <4 x float> %52, i32 2 %54 = fmul float %53, %4 %55 = fadd float %54, 0,000000e+00 %56 = add i32 1, %37 %57 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %56 %58 = load <4 x float> addrspace(8)* %57 %59 = extractelement <4 x float> %58, i32 3 %60 = fmul float %59, %4 %61 = fadd float %60, 0,000000e+00 %62 = bitcast float %temp36.0 to i32 %63 = mul i32 %62, 4 %64 = bitcast i32 %63 to float %65 = bitcast float %64 to i32 %66 = add i32 2, %65 %67 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %66 %68 = load <4 x float> addrspace(8)* %67 %69 = extractelement <4 x float> %68, i32 0 %70 = fmul float %69, %4 %71 = fadd float %70, 0,000000e+00 %72 = add i32 2, %65 %73 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %72 %74 = load <4 x float> addrspace(8)* %73 %75 = extractelement <4 x float> %74, i32 1 %76 = fmul float %75, %4 %77 = fadd float %76, 0,000000e+00 %78 = add i32 2, %65 %79 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %78 %80 = load <4 x float> addrspace(8)* %79 %81 = extractelement <4 x float> %80, i32 2 %82 = fmul float %81, %4 %83 = fadd float %82, 0,000000e+00 %84 = add i32 2, %65 %85 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %84 %86 = load <4 x float> addrspace(8)* %85 %87 = extractelement <4 x float> %86, i32 3 %88 = fmul float %87, %4 %89 = fadd float %88, 0,000000e+00 %90 = bitcast float %temp36.0 to i32 %91 = mul i32 %90, 4 %92 = bitcast i32 %91 to float %93 = bitcast float %92 to i32 %94 = add i32 3, %93 %95 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %94 %96 = load <4 x float> addrspace(8)* %95 %97 = extractelement <4 x float> %96, i32 0 %98 = fmul float %97, %4 %99 = fadd float %98, 0,000000e+00 %100 = add i32 3, %93 %101 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %100 %102 = load <4 x float> addrspace(8)* %101 %103 = extractelement <4 x float> %102, i32 1 %104 = fmul float %103, %4 %105 = fadd float %104, 0,000000e+00 %106 = add i32 3, %93 %107 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %106 %108 = load <4 x float> addrspace(8)* %107 %109 = extractelement <4 x float> %108, i32 2 %110 = fmul float %109, %4 %111 = fadd float %110, 0,000000e+00 %112 = add i32 3, %93 %113 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %112 %114 = load <4 x float> addrspace(8)* %113 %115 = extractelement <4 x float> %114, i32 3 %116 = fmul float %115, %4 %117 = fadd float %116, 0,000000e+00 %118 = bitcast float %temp36.0 to i32 %119 = mul i32 %118, 4 %120 = bitcast i32 %119 to float %121 = bitcast float %120 to i32 %122 = add i32 4, %121 %123 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %122 %124 = load <4 x float> addrspace(8)* %123 %125 = extractelement <4 x float> %124, i32 0 %126 = fmul float %125, %4 %127 = fadd float %126, 0,000000e+00 %128 = add i32 4, %121 %129 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %128 %130 = load <4 x float> addrspace(8)* %129 %131 = extractelement <4 x float> %130, i32 1 %132 = fmul float %131, %4 %133 = fadd float %132, 0,000000e+00 %134 = add i32 4, %121 %135 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %134 %136 = load <4 x float> addrspace(8)* %135 %137 = extractelement <4 x float> %136, i32 2 %138 = fmul float %137, %4 %139 = fadd float %138, 0,000000e+00 %140 = add i32 4, %121 %141 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %140 %142 = load <4 x float> addrspace(8)* %141 %143 = extractelement <4 x float> %142, i32 3 %144 = fmul float %143, %4 %145 = fadd float %144, 0,000000e+00 %146 = fptosi float %1 to i32 %147 = bitcast i32 %146 to float %148 = bitcast float %147 to i32 %149 = icmp slt i32 %148, 0 %150 = sext i1 %149 to i32 %151 = bitcast i32 %150 to float %152 = bitcast float %151 to i32 %153 = icmp ne i32 %152, 0 br i1 %153, label %ENDIF123, label %ELSE125 ELSE125: ; preds = %ENDIF %154 = bitcast float %147 to i32 %155 = icmp slt i32 44, %154 %156 = sext i1 %155 to i32 %157 = bitcast i32 %156 to float %158 = bitcast float %157 to i32 %159 = icmp ne i32 %158, 0 %.141 = select i1 %159, float 0,000000e+00, float %147 br label %ENDIF123 ENDIF123: ; preds = %ENDIF, %ELSE125 %temp36.1 = phi float [ %.141, %ELSE125 ], [ 0,000000e+00, %ENDIF ] %160 = bitcast float %temp36.1 to i32 %161 = mul i32 %160, 4 %162 = bitcast i32 %161 to float %163 = bitcast float %162 to i32 %164 = add i32 1, %163 %165 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %164 %166 = load <4 x float> addrspace(8)* %165 %167 = extractelement <4 x float> %166, i32 0 %168 = fmul float %167, %5 %169 = fadd float %168, %43 %170 = add i32 1, %163 %171 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %170 %172 = load <4 x float> addrspace(8)* %171 %173 = extractelement <4 x float> %172, i32 1 %174 = fmul float %173, %5 %175 = fadd float %174, %49 %176 = add i32 1, %163 %177 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %176 %178 = load <4 x float> addrspace(8)* %177 %179 = extractelement <4 x float> %178, i32 2 %180 = fmul float %179, %5 %181 = fadd float %180, %55 %182 = add i32 1, %163 %183 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %182 %184 = load <4 x float> addrspace(8)* %183 %185 = extractelement <4 x float> %184, i32 3 %186 = fmul float %185, %5 %187 = fadd float %186, %61 %188 = bitcast float %temp36.1 to i32 %189 = mul i32 %188, 4 %190 = bitcast i32 %189 to float %191 = bitcast float %190 to i32 %192 = add i32 2, %191 %193 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %192 %194 = load <4 x float> addrspace(8)* %193 %195 = extractelement <4 x float> %194, i32 0 %196 = fmul float %195, %5 %197 = fadd float %196, %71 %198 = add i32 2, %191 %199 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %198 %200 = load <4 x float> addrspace(8)* %199 %201 = extractelement <4 x float> %200, i32 1 %202 = fmul float %201, %5 %203 = fadd float %202, %77 %204 = add i32 2, %191 %205 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %204 %206 = load <4 x float> addrspace(8)* %205 %207 = extractelement <4 x float> %206, i32 2 %208 = fmul float %207, %5 %209 = fadd float %208, %83 %210 = add i32 2, %191 %211 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %210 %212 = load <4 x float> addrspace(8)* %211 %213 = extractelement <4 x float> %212, i32 3 %214 = fmul float %213, %5 %215 = fadd float %214, %89 %216 = bitcast float %temp36.1 to i32 %217 = mul i32 %216, 4 %218 = bitcast i32 %217 to float %219 = bitcast float %218 to i32 %220 = add i32 3, %219 %221 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %220 %222 = load <4 x float> addrspace(8)* %221 %223 = extractelement <4 x float> %222, i32 0 %224 = fmul float %223, %5 %225 = fadd float %224, %99 %226 = add i32 3, %219 %227 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %226 %228 = load <4 x float> addrspace(8)* %227 %229 = extractelement <4 x float> %228, i32 1 %230 = fmul float %229, %5 %231 = fadd float %230, %105 %232 = add i32 3, %219 %233 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %232 %234 = load <4 x float> addrspace(8)* %233 %235 = extractelement <4 x float> %234, i32 2 %236 = fmul float %235, %5 %237 = fadd float %236, %111 %238 = add i32 3, %219 %239 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %238 %240 = load <4 x float> addrspace(8)* %239 %241 = extractelement <4 x float> %240, i32 3 %242 = fmul float %241, %5 %243 = fadd float %242, %117 %244 = bitcast float %temp36.1 to i32 %245 = mul i32 %244, 4 %246 = bitcast i32 %245 to float %247 = bitcast float %246 to i32 %248 = add i32 4, %247 %249 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %248 %250 = load <4 x float> addrspace(8)* %249 %251 = extractelement <4 x float> %250, i32 0 %252 = fmul float %251, %5 %253 = fadd float %252, %127 %254 = add i32 4, %247 %255 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %254 %256 = load <4 x float> addrspace(8)* %255 %257 = extractelement <4 x float> %256, i32 1 %258 = fmul float %257, %5 %259 = fadd float %258, %133 %260 = add i32 4, %247 %261 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %260 %262 = load <4 x float> addrspace(8)* %261 %263 = extractelement <4 x float> %262, i32 2 %264 = fmul float %263, %5 %265 = fadd float %264, %139 %266 = add i32 4, %247 %267 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %266 %268 = load <4 x float> addrspace(8)* %267 %269 = extractelement <4 x float> %268, i32 3 %270 = fmul float %269, %5 %271 = fadd float %270, %145 %272 = fptosi float %2 to i32 %273 = bitcast i32 %272 to float %274 = bitcast float %273 to i32 %275 = icmp slt i32 %274, 0 %276 = sext i1 %275 to i32 %277 = bitcast i32 %276 to float %278 = bitcast float %277 to i32 %279 = icmp ne i32 %278, 0 br i1 %279, label %ENDIF129, label %ELSE131 ELSE131: ; preds = %ENDIF123 %280 = bitcast float %273 to i32 %281 = icmp slt i32 44, %280 %282 = sext i1 %281 to i32 %283 = bitcast i32 %282 to float %284 = bitcast float %283 to i32 %285 = icmp ne i32 %284, 0 %.142 = select i1 %285, float 0,000000e+00, float %273 br label %ENDIF129 ENDIF129: ; preds = %ENDIF123, %ELSE131 %temp36.2 = phi float [ %.142, %ELSE131 ], [ 0,000000e+00, %ENDIF123 ] %286 = bitcast float %temp36.2 to i32 %287 = mul i32 %286, 4 %288 = bitcast i32 %287 to float %289 = bitcast float %288 to i32 %290 = add i32 1, %289 %291 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %290 %292 = load <4 x float> addrspace(8)* %291 %293 = extractelement <4 x float> %292, i32 0 %294 = fmul float %293, %6 %295 = fadd float %294, %169 %296 = add i32 1, %289 %297 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %296 %298 = load <4 x float> addrspace(8)* %297 %299 = extractelement <4 x float> %298, i32 1 %300 = fmul float %299, %6 %301 = fadd float %300, %175 %302 = add i32 1, %289 %303 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %302 %304 = load <4 x float> addrspace(8)* %303 %305 = extractelement <4 x float> %304, i32 2 %306 = fmul float %305, %6 %307 = fadd float %306, %181 %308 = add i32 1, %289 %309 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %308 %310 = load <4 x float> addrspace(8)* %309 %311 = extractelement <4 x float> %310, i32 3 %312 = fmul float %311, %6 %313 = fadd float %312, %187 %314 = bitcast float %temp36.2 to i32 %315 = mul i32 %314, 4 %316 = bitcast i32 %315 to float %317 = bitcast float %316 to i32 %318 = add i32 2, %317 %319 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %318 %320 = load <4 x float> addrspace(8)* %319 %321 = extractelement <4 x float> %320, i32 0 %322 = fmul float %321, %6 %323 = fadd float %322, %197 %324 = add i32 2, %317 %325 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %324 %326 = load <4 x float> addrspace(8)* %325 %327 = extractelement <4 x float> %326, i32 1 %328 = fmul float %327, %6 %329 = fadd float %328, %203 %330 = add i32 2, %317 %331 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %330 %332 = load <4 x float> addrspace(8)* %331 %333 = extractelement <4 x float> %332, i32 2 %334 = fmul float %333, %6 %335 = fadd float %334, %209 %336 = add i32 2, %317 %337 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %336 %338 = load <4 x float> addrspace(8)* %337 %339 = extractelement <4 x float> %338, i32 3 %340 = fmul float %339, %6 %341 = fadd float %340, %215 %342 = bitcast float %temp36.2 to i32 %343 = mul i32 %342, 4 %344 = bitcast i32 %343 to float %345 = bitcast float %344 to i32 %346 = add i32 3, %345 %347 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %346 %348 = load <4 x float> addrspace(8)* %347 %349 = extractelement <4 x float> %348, i32 0 %350 = fmul float %349, %6 %351 = fadd float %350, %225 %352 = add i32 3, %345 %353 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %352 %354 = load <4 x float> addrspace(8)* %353 %355 = extractelement <4 x float> %354, i32 1 %356 = fmul float %355, %6 %357 = fadd float %356, %231 %358 = add i32 3, %345 %359 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %358 %360 = load <4 x float> addrspace(8)* %359 %361 = extractelement <4 x float> %360, i32 2 %362 = fmul float %361, %6 %363 = fadd float %362, %237 %364 = add i32 3, %345 %365 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %364 %366 = load <4 x float> addrspace(8)* %365 %367 = extractelement <4 x float> %366, i32 3 %368 = fmul float %367, %6 %369 = fadd float %368, %243 %370 = bitcast float %temp36.2 to i32 %371 = mul i32 %370, 4 %372 = bitcast i32 %371 to float %373 = bitcast float %372 to i32 %374 = add i32 4, %373 %375 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %374 %376 = load <4 x float> addrspace(8)* %375 %377 = extractelement <4 x float> %376, i32 0 %378 = fmul float %377, %6 %379 = fadd float %378, %253 %380 = add i32 4, %373 %381 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %380 %382 = load <4 x float> addrspace(8)* %381 %383 = extractelement <4 x float> %382, i32 1 %384 = fmul float %383, %6 %385 = fadd float %384, %259 %386 = add i32 4, %373 %387 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %386 %388 = load <4 x float> addrspace(8)* %387 %389 = extractelement <4 x float> %388, i32 2 %390 = fmul float %389, %6 %391 = fadd float %390, %265 %392 = add i32 4, %373 %393 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %392 %394 = load <4 x float> addrspace(8)* %393 %395 = extractelement <4 x float> %394, i32 3 %396 = fmul float %395, %6 %397 = fadd float %396, %271 %398 = fptosi float %3 to i32 %399 = bitcast i32 %398 to float %400 = bitcast float %399 to i32 %401 = icmp slt i32 %400, 0 %402 = sext i1 %401 to i32 %403 = bitcast i32 %402 to float %404 = bitcast float %403 to i32 %405 = icmp ne i32 %404, 0 br i1 %405, label %ENDIF135, label %ELSE137 ELSE137: ; preds = %ENDIF129 %406 = bitcast float %399 to i32 %407 = icmp slt i32 44, %406 %408 = sext i1 %407 to i32 %409 = bitcast i32 %408 to float %410 = bitcast float %409 to i32 %411 = icmp ne i32 %410, 0 %.143 = select i1 %411, float 0,000000e+00, float %399 br label %ENDIF135 ENDIF135: ; preds = %ENDIF129, %ELSE137 %temp36.3 = phi float [ %.143, %ELSE137 ], [ 0,000000e+00, %ENDIF129 ] %412 = bitcast float %temp36.3 to i32 %413 = mul i32 %412, 4 %414 = bitcast i32 %413 to float %415 = bitcast float %414 to i32 %416 = add i32 1, %415 %417 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %416 %418 = load <4 x float> addrspace(8)* %417 %419 = extractelement <4 x float> %418, i32 0 %420 = fmul float %419, %7 %421 = fadd float %420, %295 %422 = add i32 1, %415 %423 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %422 %424 = load <4 x float> addrspace(8)* %423 %425 = extractelement <4 x float> %424, i32 1 %426 = fmul float %425, %7 %427 = fadd float %426, %301 %428 = add i32 1, %415 %429 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %428 %430 = load <4 x float> addrspace(8)* %429 %431 = extractelement <4 x float> %430, i32 2 %432 = fmul float %431, %7 %433 = fadd float %432, %307 %434 = add i32 1, %415 %435 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %434 %436 = load <4 x float> addrspace(8)* %435 %437 = extractelement <4 x float> %436, i32 3 %438 = fmul float %437, %7 %439 = fadd float %438, %313 %440 = bitcast float %temp36.3 to i32 %441 = mul i32 %440, 4 %442 = bitcast i32 %441 to float %443 = bitcast float %442 to i32 %444 = add i32 2, %443 %445 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %444 %446 = load <4 x float> addrspace(8)* %445 %447 = extractelement <4 x float> %446, i32 0 %448 = fmul float %447, %7 %449 = fadd float %448, %323 %450 = add i32 2, %443 %451 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %450 %452 = load <4 x float> addrspace(8)* %451 %453 = extractelement <4 x float> %452, i32 1 %454 = fmul float %453, %7 %455 = fadd float %454, %329 %456 = add i32 2, %443 %457 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %456 %458 = load <4 x float> addrspace(8)* %457 %459 = extractelement <4 x float> %458, i32 2 %460 = fmul float %459, %7 %461 = fadd float %460, %335 %462 = add i32 2, %443 %463 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %462 %464 = load <4 x float> addrspace(8)* %463 %465 = extractelement <4 x float> %464, i32 3 %466 = fmul float %465, %7 %467 = fadd float %466, %341 %468 = bitcast float %temp36.3 to i32 %469 = mul i32 %468, 4 %470 = bitcast i32 %469 to float %471 = bitcast float %470 to i32 %472 = add i32 3, %471 %473 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %472 %474 = load <4 x float> addrspace(8)* %473 %475 = extractelement <4 x float> %474, i32 0 %476 = fmul float %475, %7 %477 = fadd float %476, %351 %478 = add i32 3, %471 %479 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %478 %480 = load <4 x float> addrspace(8)* %479 %481 = extractelement <4 x float> %480, i32 1 %482 = fmul float %481, %7 %483 = fadd float %482, %357 %484 = add i32 3, %471 %485 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %484 %486 = load <4 x float> addrspace(8)* %485 %487 = extractelement <4 x float> %486, i32 2 %488 = fmul float %487, %7 %489 = fadd float %488, %363 %490 = add i32 3, %471 %491 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %490 %492 = load <4 x float> addrspace(8)* %491 %493 = extractelement <4 x float> %492, i32 3 %494 = fmul float %493, %7 %495 = fadd float %494, %369 %496 = bitcast float %temp36.3 to i32 %497 = mul i32 %496, 4 %498 = bitcast i32 %497 to float %499 = bitcast float %498 to i32 %500 = add i32 4, %499 %501 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %500 %502 = load <4 x float> addrspace(8)* %501 %503 = extractelement <4 x float> %502, i32 0 %504 = fmul float %503, %7 %505 = fadd float %504, %379 %506 = add i32 4, %499 %507 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %506 %508 = load <4 x float> addrspace(8)* %507 %509 = extractelement <4 x float> %508, i32 1 %510 = fmul float %509, %7 %511 = fadd float %510, %385 %512 = add i32 4, %499 %513 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %512 %514 = load <4 x float> addrspace(8)* %513 %515 = extractelement <4 x float> %514, i32 2 %516 = fmul float %515, %7 %517 = fadd float %516, %391 %518 = add i32 4, %499 %519 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %518 %520 = load <4 x float> addrspace(8)* %519 %521 = extractelement <4 x float> %520, i32 3 %522 = fmul float %521, %7 %523 = fadd float %522, %397 %524 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %525 = extractelement <4 x float> %524, i32 0 %526 = fmul float %525, %477 %527 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %528 = extractelement <4 x float> %527, i32 1 %529 = fmul float %528, %477 %530 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %531 = extractelement <4 x float> %530, i32 2 %532 = fmul float %531, %477 %533 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %534 = extractelement <4 x float> %533, i32 3 %535 = fmul float %534, %477 %536 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %537 = extractelement <4 x float> %536, i32 0 %538 = fmul float %537, %483 %539 = fadd float %538, %526 %540 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %541 = extractelement <4 x float> %540, i32 1 %542 = fmul float %541, %483 %543 = fadd float %542, %529 %544 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %545 = extractelement <4 x float> %544, i32 2 %546 = fmul float %545, %483 %547 = fadd float %546, %532 %548 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %549 = extractelement <4 x float> %548, i32 3 %550 = fmul float %549, %483 %551 = fadd float %550, %535 %552 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %553 = extractelement <4 x float> %552, i32 0 %554 = fmul float %553, %489 %555 = fadd float %554, %539 %556 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %557 = extractelement <4 x float> %556, i32 1 %558 = fmul float %557, %489 %559 = fadd float %558, %543 %560 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %561 = extractelement <4 x float> %560, i32 2 %562 = fmul float %561, %489 %563 = fadd float %562, %547 %564 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %565 = extractelement <4 x float> %564, i32 3 %566 = fmul float %565, %489 %567 = fadd float %566, %551 %568 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %569 = extractelement <4 x float> %568, i32 0 %570 = fmul float %569, %495 %571 = fadd float %570, %555 %572 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %573 = extractelement <4 x float> %572, i32 1 %574 = fmul float %573, %495 %575 = fadd float %574, %559 %576 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %577 = extractelement <4 x float> %576, i32 2 %578 = fmul float %577, %495 %579 = fadd float %578, %563 %580 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %581 = extractelement <4 x float> %580, i32 3 %582 = fmul float %581, %495 %583 = fadd float %582, %567 %584 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %585 = extractelement <4 x float> %584, i32 0 %586 = fmul float %585, %449 %587 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %588 = extractelement <4 x float> %587, i32 1 %589 = fmul float %588, %449 %590 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %591 = extractelement <4 x float> %590, i32 2 %592 = fmul float %591, %449 %593 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %594 = extractelement <4 x float> %593, i32 3 %595 = fmul float %594, %449 %596 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %597 = extractelement <4 x float> %596, i32 0 %598 = fmul float %597, %455 %599 = fadd float %598, %586 %600 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %601 = extractelement <4 x float> %600, i32 1 %602 = fmul float %601, %455 %603 = fadd float %602, %589 %604 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %605 = extractelement <4 x float> %604, i32 2 %606 = fmul float %605, %455 %607 = fadd float %606, %592 %608 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %609 = extractelement <4 x float> %608, i32 3 %610 = fmul float %609, %455 %611 = fadd float %610, %595 %612 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %613 = extractelement <4 x float> %612, i32 0 %614 = fmul float %613, %461 %615 = fadd float %614, %599 %616 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %617 = extractelement <4 x float> %616, i32 1 %618 = fmul float %617, %461 %619 = fadd float %618, %603 %620 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %621 = extractelement <4 x float> %620, i32 2 %622 = fmul float %621, %461 %623 = fadd float %622, %607 %624 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %625 = extractelement <4 x float> %624, i32 3 %626 = fmul float %625, %461 %627 = fadd float %626, %611 %628 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %629 = extractelement <4 x float> %628, i32 0 %630 = fmul float %629, %467 %631 = fadd float %630, %615 %632 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %633 = extractelement <4 x float> %632, i32 1 %634 = fmul float %633, %467 %635 = fadd float %634, %619 %636 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %637 = extractelement <4 x float> %636, i32 2 %638 = fmul float %637, %467 %639 = fadd float %638, %623 %640 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %641 = extractelement <4 x float> %640, i32 3 %642 = fmul float %641, %467 %643 = fadd float %642, %627 %644 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %645 = extractelement <4 x float> %644, i32 0 %646 = fmul float %645, %421 %647 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %648 = extractelement <4 x float> %647, i32 1 %649 = fmul float %648, %421 %650 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %651 = extractelement <4 x float> %650, i32 2 %652 = fmul float %651, %421 %653 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %654 = extractelement <4 x float> %653, i32 3 %655 = fmul float %654, %421 %656 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %657 = extractelement <4 x float> %656, i32 0 %658 = fmul float %657, %427 %659 = fadd float %658, %646 %660 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %661 = extractelement <4 x float> %660, i32 1 %662 = fmul float %661, %427 %663 = fadd float %662, %649 %664 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %665 = extractelement <4 x float> %664, i32 2 %666 = fmul float %665, %427 %667 = fadd float %666, %652 %668 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %669 = extractelement <4 x float> %668, i32 3 %670 = fmul float %669, %427 %671 = fadd float %670, %655 %672 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %673 = extractelement <4 x float> %672, i32 0 %674 = fmul float %673, %433 %675 = fadd float %674, %659 %676 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %677 = extractelement <4 x float> %676, i32 1 %678 = fmul float %677, %433 %679 = fadd float %678, %663 %680 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %681 = extractelement <4 x float> %680, i32 2 %682 = fmul float %681, %433 %683 = fadd float %682, %667 %684 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %685 = extractelement <4 x float> %684, i32 3 %686 = fmul float %685, %433 %687 = fadd float %686, %671 %688 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %689 = extractelement <4 x float> %688, i32 0 %690 = fmul float %689, %439 %691 = fadd float %690, %675 %692 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %693 = extractelement <4 x float> %692, i32 1 %694 = fmul float %693, %439 %695 = fadd float %694, %679 %696 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %697 = extractelement <4 x float> %696, i32 2 %698 = fmul float %697, %439 %699 = fadd float %698, %683 %700 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %701 = extractelement <4 x float> %700, i32 3 %702 = fmul float %701, %439 %703 = fadd float %702, %687 %704 = fmul float %691, %16 %705 = fmul float %695, %16 %706 = fmul float %699, %16 %707 = fmul float %703, %16 %708 = fmul float %631, %17 %709 = fadd float %708, %704 %710 = fmul float %635, %17 %711 = fadd float %710, %705 %712 = fmul float %639, %17 %713 = fadd float %712, %706 %714 = fmul float %643, %17 %715 = fadd float %714, %707 %716 = fmul float %571, %18 %717 = fadd float %716, %709 %718 = fmul float %575, %18 %719 = fadd float %718, %711 %720 = fmul float %579, %18 %721 = fadd float %720, %713 %722 = fmul float %583, %18 %723 = fadd float %722, %715 %724 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %725 = extractelement <4 x float> %724, i32 0 %726 = fmul float %725, %505 %727 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %728 = extractelement <4 x float> %727, i32 1 %729 = fmul float %728, %505 %730 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %731 = extractelement <4 x float> %730, i32 2 %732 = fmul float %731, %505 %733 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %734 = extractelement <4 x float> %733, i32 3 %735 = fmul float %734, %505 %736 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %737 = extractelement <4 x float> %736, i32 0 %738 = fmul float %737, %511 %739 = fadd float %738, %726 %740 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %741 = extractelement <4 x float> %740, i32 1 %742 = fmul float %741, %511 %743 = fadd float %742, %729 %744 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %745 = extractelement <4 x float> %744, i32 2 %746 = fmul float %745, %511 %747 = fadd float %746, %732 %748 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %749 = extractelement <4 x float> %748, i32 3 %750 = fmul float %749, %511 %751 = fadd float %750, %735 %752 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %753 = extractelement <4 x float> %752, i32 0 %754 = fmul float %753, %517 %755 = fadd float %754, %739 %756 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %757 = extractelement <4 x float> %756, i32 1 %758 = fmul float %757, %517 %759 = fadd float %758, %743 %760 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %761 = extractelement <4 x float> %760, i32 2 %762 = fmul float %761, %517 %763 = fadd float %762, %747 %764 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %765 = extractelement <4 x float> %764, i32 3 %766 = fmul float %765, %517 %767 = fadd float %766, %751 %768 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %769 = extractelement <4 x float> %768, i32 0 %770 = fmul float %769, %523 %771 = fadd float %770, %755 %772 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %773 = extractelement <4 x float> %772, i32 1 %774 = fmul float %773, %523 %775 = fadd float %774, %759 %776 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %777 = extractelement <4 x float> %776, i32 2 %778 = fmul float %777, %523 %779 = fadd float %778, %763 %780 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %781 = extractelement <4 x float> %780, i32 3 %782 = fmul float %781, %523 %783 = fadd float %782, %767 %784 = fadd float %717, %771 %785 = fadd float %719, %775 %786 = fadd float %721, %779 %787 = fadd float %723, %783 %788 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %789 = extractelement <4 x float> %788, i32 0 %790 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %791 = extractelement <4 x float> %790, i32 0 %792 = fmul float %789, %791 %793 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %794 = extractelement <4 x float> %793, i32 1 %795 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %796 = extractelement <4 x float> %795, i32 0 %797 = fmul float %794, %796 %798 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %799 = extractelement <4 x float> %798, i32 2 %800 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %801 = extractelement <4 x float> %800, i32 0 %802 = fmul float %799, %801 %803 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %804 = extractelement <4 x float> %803, i32 3 %805 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %806 = extractelement <4 x float> %805, i32 0 %807 = fmul float %804, %806 %808 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %809 = extractelement <4 x float> %808, i32 0 %810 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %811 = extractelement <4 x float> %810, i32 1 %812 = fmul float %809, %811 %813 = fadd float %812, %792 %814 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %815 = extractelement <4 x float> %814, i32 1 %816 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %817 = extractelement <4 x float> %816, i32 1 %818 = fmul float %815, %817 %819 = fadd float %818, %797 %820 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %821 = extractelement <4 x float> %820, i32 2 %822 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %823 = extractelement <4 x float> %822, i32 1 %824 = fmul float %821, %823 %825 = fadd float %824, %802 %826 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %827 = extractelement <4 x float> %826, i32 3 %828 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %829 = extractelement <4 x float> %828, i32 1 %830 = fmul float %827, %829 %831 = fadd float %830, %807 %832 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %833 = extractelement <4 x float> %832, i32 0 %834 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %835 = extractelement <4 x float> %834, i32 2 %836 = fmul float %833, %835 %837 = fadd float %836, %813 %838 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %839 = extractelement <4 x float> %838, i32 1 %840 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %841 = extractelement <4 x float> %840, i32 2 %842 = fmul float %839, %841 %843 = fadd float %842, %819 %844 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %845 = extractelement <4 x float> %844, i32 2 %846 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %847 = extractelement <4 x float> %846, i32 2 %848 = fmul float %845, %847 %849 = fadd float %848, %825 %850 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %851 = extractelement <4 x float> %850, i32 3 %852 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %853 = extractelement <4 x float> %852, i32 2 %854 = fmul float %851, %853 %855 = fadd float %854, %831 %856 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %857 = extractelement <4 x float> %856, i32 0 %858 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %859 = extractelement <4 x float> %858, i32 3 %860 = fmul float %857, %859 %861 = fadd float %860, %837 %862 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %863 = extractelement <4 x float> %862, i32 1 %864 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %865 = extractelement <4 x float> %864, i32 3 %866 = fmul float %863, %865 %867 = fadd float %866, %843 %868 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %869 = extractelement <4 x float> %868, i32 2 %870 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %871 = extractelement <4 x float> %870, i32 3 %872 = fmul float %869, %871 %873 = fadd float %872, %849 %874 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %875 = extractelement <4 x float> %874, i32 3 %876 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 192) %877 = extractelement <4 x float> %876, i32 3 %878 = fmul float %875, %877 %879 = fadd float %878, %855 %880 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %881 = extractelement <4 x float> %880, i32 0 %882 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %883 = extractelement <4 x float> %882, i32 0 %884 = fmul float %881, %883 %885 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %886 = extractelement <4 x float> %885, i32 1 %887 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %888 = extractelement <4 x float> %887, i32 0 %889 = fmul float %886, %888 %890 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %891 = extractelement <4 x float> %890, i32 2 %892 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %893 = extractelement <4 x float> %892, i32 0 %894 = fmul float %891, %893 %895 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %896 = extractelement <4 x float> %895, i32 3 %897 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %898 = extractelement <4 x float> %897, i32 0 %899 = fmul float %896, %898 %900 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %901 = extractelement <4 x float> %900, i32 0 %902 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %903 = extractelement <4 x float> %902, i32 1 %904 = fmul float %901, %903 %905 = fadd float %904, %884 %906 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %907 = extractelement <4 x float> %906, i32 1 %908 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %909 = extractelement <4 x float> %908, i32 1 %910 = fmul float %907, %909 %911 = fadd float %910, %889 %912 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %913 = extractelement <4 x float> %912, i32 2 %914 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %915 = extractelement <4 x float> %914, i32 1 %916 = fmul float %913, %915 %917 = fadd float %916, %894 %918 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %919 = extractelement <4 x float> %918, i32 3 %920 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %921 = extractelement <4 x float> %920, i32 1 %922 = fmul float %919, %921 %923 = fadd float %922, %899 %924 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %925 = extractelement <4 x float> %924, i32 0 %926 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %927 = extractelement <4 x float> %926, i32 2 %928 = fmul float %925, %927 %929 = fadd float %928, %905 %930 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %931 = extractelement <4 x float> %930, i32 1 %932 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %933 = extractelement <4 x float> %932, i32 2 %934 = fmul float %931, %933 %935 = fadd float %934, %911 %936 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %937 = extractelement <4 x float> %936, i32 2 %938 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %939 = extractelement <4 x float> %938, i32 2 %940 = fmul float %937, %939 %941 = fadd float %940, %917 %942 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %943 = extractelement <4 x float> %942, i32 3 %944 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %945 = extractelement <4 x float> %944, i32 2 %946 = fmul float %943, %945 %947 = fadd float %946, %923 %948 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %949 = extractelement <4 x float> %948, i32 0 %950 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %951 = extractelement <4 x float> %950, i32 3 %952 = fmul float %949, %951 %953 = fadd float %952, %929 %954 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %955 = extractelement <4 x float> %954, i32 1 %956 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %957 = extractelement <4 x float> %956, i32 3 %958 = fmul float %955, %957 %959 = fadd float %958, %935 %960 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %961 = extractelement <4 x float> %960, i32 2 %962 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %963 = extractelement <4 x float> %962, i32 3 %964 = fmul float %961, %963 %965 = fadd float %964, %941 %966 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %967 = extractelement <4 x float> %966, i32 3 %968 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 191) %969 = extractelement <4 x float> %968, i32 3 %970 = fmul float %967, %969 %971 = fadd float %970, %947 %972 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %973 = extractelement <4 x float> %972, i32 0 %974 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %975 = extractelement <4 x float> %974, i32 0 %976 = fmul float %973, %975 %977 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %978 = extractelement <4 x float> %977, i32 1 %979 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %980 = extractelement <4 x float> %979, i32 0 %981 = fmul float %978, %980 %982 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %983 = extractelement <4 x float> %982, i32 2 %984 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %985 = extractelement <4 x float> %984, i32 0 %986 = fmul float %983, %985 %987 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %988 = extractelement <4 x float> %987, i32 3 %989 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %990 = extractelement <4 x float> %989, i32 0 %991 = fmul float %988, %990 %992 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %993 = extractelement <4 x float> %992, i32 0 %994 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %995 = extractelement <4 x float> %994, i32 1 %996 = fmul float %993, %995 %997 = fadd float %996, %976 %998 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %999 = extractelement <4 x float> %998, i32 1 %1000 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %1001 = extractelement <4 x float> %1000, i32 1 %1002 = fmul float %999, %1001 %1003 = fadd float %1002, %981 %1004 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %1005 = extractelement <4 x float> %1004, i32 2 %1006 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %1007 = extractelement <4 x float> %1006, i32 1 %1008 = fmul float %1005, %1007 %1009 = fadd float %1008, %986 %1010 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %1011 = extractelement <4 x float> %1010, i32 3 %1012 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %1013 = extractelement <4 x float> %1012, i32 1 %1014 = fmul float %1011, %1013 %1015 = fadd float %1014, %991 %1016 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %1017 = extractelement <4 x float> %1016, i32 0 %1018 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %1019 = extractelement <4 x float> %1018, i32 2 %1020 = fmul float %1017, %1019 %1021 = fadd float %1020, %997 %1022 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %1023 = extractelement <4 x float> %1022, i32 1 %1024 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %1025 = extractelement <4 x float> %1024, i32 2 %1026 = fmul float %1023, %1025 %1027 = fadd float %1026, %1003 %1028 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %1029 = extractelement <4 x float> %1028, i32 2 %1030 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %1031 = extractelement <4 x float> %1030, i32 2 %1032 = fmul float %1029, %1031 %1033 = fadd float %1032, %1009 %1034 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %1035 = extractelement <4 x float> %1034, i32 3 %1036 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %1037 = extractelement <4 x float> %1036, i32 2 %1038 = fmul float %1035, %1037 %1039 = fadd float %1038, %1015 %1040 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %1041 = extractelement <4 x float> %1040, i32 0 %1042 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %1043 = extractelement <4 x float> %1042, i32 3 %1044 = fmul float %1041, %1043 %1045 = fadd float %1044, %1021 %1046 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %1047 = extractelement <4 x float> %1046, i32 1 %1048 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %1049 = extractelement <4 x float> %1048, i32 3 %1050 = fmul float %1047, %1049 %1051 = fadd float %1050, %1027 %1052 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %1053 = extractelement <4 x float> %1052, i32 2 %1054 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %1055 = extractelement <4 x float> %1054, i32 3 %1056 = fmul float %1053, %1055 %1057 = fadd float %1056, %1033 %1058 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %1059 = extractelement <4 x float> %1058, i32 3 %1060 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 190) %1061 = extractelement <4 x float> %1060, i32 3 %1062 = fmul float %1059, %1061 %1063 = fadd float %1062, %1039 %1064 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %1065 = extractelement <4 x float> %1064, i32 0 %1066 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1067 = extractelement <4 x float> %1066, i32 0 %1068 = fmul float %1065, %1067 %1069 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %1070 = extractelement <4 x float> %1069, i32 1 %1071 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1072 = extractelement <4 x float> %1071, i32 0 %1073 = fmul float %1070, %1072 %1074 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %1075 = extractelement <4 x float> %1074, i32 2 %1076 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1077 = extractelement <4 x float> %1076, i32 0 %1078 = fmul float %1075, %1077 %1079 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 185) %1080 = extractelement <4 x float> %1079, i32 3 %1081 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1082 = extractelement <4 x float> %1081, i32 0 %1083 = fmul float %1080, %1082 %1084 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %1085 = extractelement <4 x float> %1084, i32 0 %1086 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1087 = extractelement <4 x float> %1086, i32 1 %1088 = fmul float %1085, %1087 %1089 = fadd float %1088, %1068 %1090 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %1091 = extractelement <4 x float> %1090, i32 1 %1092 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1093 = extractelement <4 x float> %1092, i32 1 %1094 = fmul float %1091, %1093 %1095 = fadd float %1094, %1073 %1096 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %1097 = extractelement <4 x float> %1096, i32 2 %1098 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1099 = extractelement <4 x float> %1098, i32 1 %1100 = fmul float %1097, %1099 %1101 = fadd float %1100, %1078 %1102 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 186) %1103 = extractelement <4 x float> %1102, i32 3 %1104 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1105 = extractelement <4 x float> %1104, i32 1 %1106 = fmul float %1103, %1105 %1107 = fadd float %1106, %1083 %1108 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %1109 = extractelement <4 x float> %1108, i32 0 %1110 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1111 = extractelement <4 x float> %1110, i32 2 %1112 = fmul float %1109, %1111 %1113 = fadd float %1112, %1089 %1114 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %1115 = extractelement <4 x float> %1114, i32 1 %1116 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1117 = extractelement <4 x float> %1116, i32 2 %1118 = fmul float %1115, %1117 %1119 = fadd float %1118, %1095 %1120 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %1121 = extractelement <4 x float> %1120, i32 2 %1122 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1123 = extractelement <4 x float> %1122, i32 2 %1124 = fmul float %1121, %1123 %1125 = fadd float %1124, %1101 %1126 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 187) %1127 = extractelement <4 x float> %1126, i32 3 %1128 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1129 = extractelement <4 x float> %1128, i32 2 %1130 = fmul float %1127, %1129 %1131 = fadd float %1130, %1107 %1132 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %1133 = extractelement <4 x float> %1132, i32 0 %1134 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1135 = extractelement <4 x float> %1134, i32 3 %1136 = fmul float %1133, %1135 %1137 = fadd float %1136, %1113 %1138 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %1139 = extractelement <4 x float> %1138, i32 1 %1140 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1141 = extractelement <4 x float> %1140, i32 3 %1142 = fmul float %1139, %1141 %1143 = fadd float %1142, %1119 %1144 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %1145 = extractelement <4 x float> %1144, i32 2 %1146 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1147 = extractelement <4 x float> %1146, i32 3 %1148 = fmul float %1145, %1147 %1149 = fadd float %1148, %1125 %1150 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 188) %1151 = extractelement <4 x float> %1150, i32 3 %1152 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 189) %1153 = extractelement <4 x float> %1152, i32 3 %1154 = fmul float %1151, %1153 %1155 = fadd float %1154, %1131 %1156 = fmul float %1137, %784 %1157 = fmul float %1143, %784 %1158 = fmul float %1149, %784 %1159 = fmul float %1155, %784 %1160 = fmul float %1045, %785 %1161 = fadd float %1160, %1156 %1162 = fmul float %1051, %785 %1163 = fadd float %1162, %1157 %1164 = fmul float %1057, %785 %1165 = fadd float %1164, %1158 %1166 = fmul float %1063, %785 %1167 = fadd float %1166, %1159 %1168 = fmul float %953, %786 %1169 = fadd float %1168, %1161 %1170 = fmul float %959, %786 %1171 = fadd float %1170, %1163 %1172 = fmul float %965, %786 %1173 = fadd float %1172, %1165 %1174 = fmul float %971, %786 %1175 = fadd float %1174, %1167 %1176 = fmul float %861, %787 %1177 = fadd float %1176, %1169 %1178 = fmul float %867, %787 %1179 = fadd float %1178, %1171 %1180 = fmul float %873, %787 %1181 = fadd float %1180, %1173 %1182 = fmul float %879, %787 %1183 = fadd float %1182, %1175 %1184 = load <4 x float> addrspace(8)* null %1185 = extractelement <4 x float> %1184, i32 0 %1186 = load <4 x float> addrspace(8)* null %1187 = extractelement <4 x float> %1186, i32 1 %1188 = load <4 x float> addrspace(8)* null %1189 = extractelement <4 x float> %1188, i32 2 %1190 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %1191 = extractelement <4 x float> %1190, i32 0 %1192 = fmul float %1191, %477 %1193 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %1194 = extractelement <4 x float> %1193, i32 1 %1195 = fmul float %1194, %477 %1196 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %1197 = extractelement <4 x float> %1196, i32 2 %1198 = fmul float %1197, %477 %1199 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %1200 = extractelement <4 x float> %1199, i32 0 %1201 = fmul float %1200, %483 %1202 = fadd float %1201, %1192 %1203 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %1204 = extractelement <4 x float> %1203, i32 1 %1205 = fmul float %1204, %483 %1206 = fadd float %1205, %1195 %1207 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %1208 = extractelement <4 x float> %1207, i32 2 %1209 = fmul float %1208, %483 %1210 = fadd float %1209, %1198 %1211 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %1212 = extractelement <4 x float> %1211, i32 0 %1213 = fmul float %1212, %489 %1214 = fadd float %1213, %1202 %1215 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %1216 = extractelement <4 x float> %1215, i32 1 %1217 = fmul float %1216, %489 %1218 = fadd float %1217, %1206 %1219 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %1220 = extractelement <4 x float> %1219, i32 2 %1221 = fmul float %1220, %489 %1222 = fadd float %1221, %1210 %1223 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %1224 = extractelement <4 x float> %1223, i32 0 %1225 = fmul float %1224, %495 %1226 = fadd float %1225, %1214 %1227 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %1228 = extractelement <4 x float> %1227, i32 1 %1229 = fmul float %1228, %495 %1230 = fadd float %1229, %1218 %1231 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %1232 = extractelement <4 x float> %1231, i32 2 %1233 = fmul float %1232, %495 %1234 = fadd float %1233, %1222 %1235 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %1236 = extractelement <4 x float> %1235, i32 0 %1237 = fmul float %1236, %449 %1238 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %1239 = extractelement <4 x float> %1238, i32 1 %1240 = fmul float %1239, %449 %1241 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %1242 = extractelement <4 x float> %1241, i32 2 %1243 = fmul float %1242, %449 %1244 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %1245 = extractelement <4 x float> %1244, i32 0 %1246 = fmul float %1245, %455 %1247 = fadd float %1246, %1237 %1248 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %1249 = extractelement <4 x float> %1248, i32 1 %1250 = fmul float %1249, %455 %1251 = fadd float %1250, %1240 %1252 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %1253 = extractelement <4 x float> %1252, i32 2 %1254 = fmul float %1253, %455 %1255 = fadd float %1254, %1243 %1256 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %1257 = extractelement <4 x float> %1256, i32 0 %1258 = fmul float %1257, %461 %1259 = fadd float %1258, %1247 %1260 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %1261 = extractelement <4 x float> %1260, i32 1 %1262 = fmul float %1261, %461 %1263 = fadd float %1262, %1251 %1264 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %1265 = extractelement <4 x float> %1264, i32 2 %1266 = fmul float %1265, %461 %1267 = fadd float %1266, %1255 %1268 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %1269 = extractelement <4 x float> %1268, i32 0 %1270 = fmul float %1269, %467 %1271 = fadd float %1270, %1259 %1272 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %1273 = extractelement <4 x float> %1272, i32 1 %1274 = fmul float %1273, %467 %1275 = fadd float %1274, %1263 %1276 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %1277 = extractelement <4 x float> %1276, i32 2 %1278 = fmul float %1277, %467 %1279 = fadd float %1278, %1267 %1280 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %1281 = extractelement <4 x float> %1280, i32 0 %1282 = fmul float %1281, %421 %1283 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %1284 = extractelement <4 x float> %1283, i32 1 %1285 = fmul float %1284, %421 %1286 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 181) %1287 = extractelement <4 x float> %1286, i32 2 %1288 = fmul float %1287, %421 %1289 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %1290 = extractelement <4 x float> %1289, i32 0 %1291 = fmul float %1290, %427 %1292 = fadd float %1291, %1282 %1293 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %1294 = extractelement <4 x float> %1293, i32 1 %1295 = fmul float %1294, %427 %1296 = fadd float %1295, %1285 %1297 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 182) %1298 = extractelement <4 x float> %1297, i32 2 %1299 = fmul float %1298, %427 %1300 = fadd float %1299, %1288 %1301 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %1302 = extractelement <4 x float> %1301, i32 0 %1303 = fmul float %1302, %433 %1304 = fadd float %1303, %1292 %1305 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %1306 = extractelement <4 x float> %1305, i32 1 %1307 = fmul float %1306, %433 %1308 = fadd float %1307, %1296 %1309 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 183) %1310 = extractelement <4 x float> %1309, i32 2 %1311 = fmul float %1310, %433 %1312 = fadd float %1311, %1300 %1313 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %1314 = extractelement <4 x float> %1313, i32 0 %1315 = fmul float %1314, %439 %1316 = fadd float %1315, %1304 %1317 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %1318 = extractelement <4 x float> %1317, i32 1 %1319 = fmul float %1318, %439 %1320 = fadd float %1319, %1308 %1321 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 184) %1322 = extractelement <4 x float> %1321, i32 2 %1323 = fmul float %1322, %439 %1324 = fadd float %1323, %1312 %1325 = fmul float %1316, %12 %1326 = fmul float %1320, %12 %1327 = fmul float %1324, %12 %1328 = fmul float %1271, %13 %1329 = fadd float %1328, %1325 %1330 = fmul float %1275, %13 %1331 = fadd float %1330, %1326 %1332 = fmul float %1279, %13 %1333 = fadd float %1332, %1327 %1334 = fmul float %1226, %14 %1335 = fadd float %1334, %1329 %1336 = fmul float %1230, %14 %1337 = fadd float %1336, %1331 %1338 = fmul float %1234, %14 %1339 = fadd float %1338, %1333 %1340 = insertelement <4 x float> undef, float %1177, i32 0 %1341 = insertelement <4 x float> %1340, float %1179, i32 1 %1342 = insertelement <4 x float> %1341, float %1181, i32 2 %1343 = insertelement <4 x float> %1342, float %1183, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %1343, i32 60, i32 1) %1344 = insertelement <4 x float> undef, float %8, i32 0 %1345 = insertelement <4 x float> %1344, float %9, i32 1 %1346 = insertelement <4 x float> %1345, float %1185, i32 2 %1347 = insertelement <4 x float> %1346, float %1187, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %1347, i32 0, i32 2) %1348 = insertelement <4 x float> undef, float %1189, i32 0 %1349 = insertelement <4 x float> %1348, float %1335, i32 1 %1350 = insertelement <4 x float> %1349, float %1337, i32 2 %1351 = insertelement <4 x float> %1350, float %1339, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %1351, i32 1, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #50 =========================================== VS/RS880/R600 ===== ===== 754 dw ===== 22 gprs ===== 1 stack ======================================= 0000 00000000 89800000 CALL_FS @0 0002 00000032 a05c0000 ALU 24 @100 0100 00000003 40001910 1 z: MOV R0.z, R3.x 0102 80000403 60001910 w: MOV R0.w, R3.y 0104 800000f8 60601910 2 w: MOV R3.w, 0 0106 80000001 60806b10 3 t: FLT_TO_INT R4.w, R1.x 0108 801fac04 60a07010 4 t: ASHR_INT R5.w, R4.w, [0x0000001f 0].x 0110 0000001f 0112 801f0cfe 60a03d10 5 w: SETNE_INT R5.w, PV.w, 0 0114 801f0cfe 00004508 6 P x: PRED_SETNE_INT __.x, PV.w, 0 0116 c01fac04 60603b10 7 0 w: SETGT_INT R3.w, R4.w, [0x0000002c 0].x 0118 0000002c 0120 c1808c03 606380fd 8 0 w: CNDE_INT R3.w, R3.w, R4.w, [0x0000002c 0].x 0122 0000002c 0124 801fac03 60607210 9 t: LSHL_INT R3.w, R3.w, [0x00000006 0].x 0126 00000006 0128 801facfe 60803410 10 w: ADD_INT R4.w, PV.w, [0x00000040 0].x 0130 00000040 0132 001facfe 00207110 11 x: ADD __.x, R4.x, R0.x 0134 801fac03 60607110 t: OR_INT R3.x, PV.w, [0x00000003 0].x 0136 00000004 0138 801facfe 00603110 12 x: OR_INT R6.x, R3.w, [0x00000002 0].x 0140 00000003 0142 801fac03 00c03110 13 x: OR_INT R7.x, R3.w, 1 0144 00000002 00000000 14 w: MOV R5.w, 0 0004 00000012 80800c00 TEX 4 @36 0036 40070040 e8cd1009 00080000 VFETCH R9.xyzw, R7.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0040 40060040 e8cd100a 00080000 VFETCH R10.xyzw, R6.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0044 40030040 e8cd1007 00080000 VFETCH R7.xyzw, R3.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0048 40010040 e8cd100b 00080000 VFETCH R11.xyzw, R1.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0006 0000004a a0940000 ALU 38 @148 0148 800000f8 60a01910 15 w: MOV R5.w, 0 0150 0000440b 206280f8 16 y: MULADD_IEEE R3.y, R11.y, R2.x, 0 0152 0000400b 40c280f8 z: MULADD_IEEE R6.z, R11.x, R2.x, 0 0154 80004c07 606280f8 w: MULADD_IEEE R3.w, R7.w, R2.x, 0 0156 00004807 002280f8 17 x: MULADD_IEEE R1.x, R7.z, R2.x, 0 0158 00004407 210280f8 y: MULADD_IEEE R8.y, R7.y, R2.x, 0 0160 00004007 410280f8 z: MULADD_IEEE R8.z, R7.x, R2.x, 0 0162 80004c0a 608280f8 w: MULADD_IEEE R4.w, R10.w, R2.x, 0 0164 0000480a 00e280f8 18 x: MULADD_IEEE R7.x, R10.z, R2.x, 0 0166 0000440a 20e280f8 y: MULADD_IEEE R7.y, R10.y, R2.x, 0 0168 8000400a 406280f8 z: MULADD_IEEE R3.z, R10.x, R2.x, 0 0170 80000401 60c06b10 19 t: FLT_TO_INT R6.w, R1.y 0172 00004c09 006280f8 20 x: MULADD_IEEE R3.x, R9.w, R2.x, 0 0174 00004809 20c280f8 y: MULADD_IEEE R6.y, R9.z, R2.x, 0 0176 00004409 40e280f8 z: MULADD_IEEE R7.z, R9.y, R2.x, 0 0178 801fac06 60e87010 t: ASHR_INT R7.w, R6.w, [0x0000001f 0].x SCL_212 0180 0000001f 0182 00004009 00c280f8 21 x: MULADD_IEEE R6.x, R9.x, R2.x, 0 0184 0000480b 212280f8 y: MULADD_IEEE R9.y, R11.z, R2.x, 0 0186 00004c0b 412280f8 z: MULADD_IEEE R9.z, R11.w, R2.x, 0 0188 801f0cfe 60e83d10 w: SETNE_INT R7.w, PV.w, 0 VEC_120 0190 801f0cfe 00004508 22 P x: PRED_SETNE_INT __.x, PV.w, 0 0192 c01fac06 60a03b10 23 0 w: SETGT_INT R5.w, R6.w, [0x0000002c 0].x 0194 0000002c 0196 c180cc05 60a380fd 24 0 w: CNDE_INT R5.w, R5.w, R6.w, [0x0000002c 0].x 0198 0000002c 0200 801fac05 60a07210 25 t: LSHL_INT R5.w, R5.w, [0x00000006 0].x 0202 00000006 0204 801facfe 60c03410 26 w: ADD_INT R6.w, PV.w, [0x00000040 0].x 0206 00000040 0208 001facfe 00407110 27 x: ADD __.x, R4.x, R0.x 0210 801fac05 60a07110 t: OR_INT R8.x, PV.w, [0x00000003 0].x 0212 00000004 0214 801facfe 01003110 28 x: OR_INT R9.x, R5.w, [0x00000002 0].x 0216 00000003 0218 801fac05 01203110 29 x: OR_INT R10.x, R5.w, 1 0220 00000002 00000000 30 w: MOV R5.w, 0 0008 0000001a 80800c00 TEX 4 @52 0052 400a0040 e8cd100a 00080000 VFETCH R10.xyzw, R10.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0056 40090040 e8cd100b 00080000 VFETCH R11.xyzw, R9.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0060 40080040 e8cd100d 00080000 VFETCH R13.xyzw, R8.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0064 40020040 e8cd100c 00080000 VFETCH R12.xyzw, R2.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0010 00000070 a0940000 ALU 38 @224 0224 800000f8 60a01910 31 w: MOV R5.w, 0 0226 0080440c 20628403 32 y: MULADD_IEEE R3.y, R12.y, R2.y, R3.y 0228 0080400c 40c28806 z: MULADD_IEEE R6.z, R12.x, R2.y, R6.z 0230 80804c0d 60628c03 w: MULADD_IEEE R3.w, R13.w, R2.y, R3.w 0232 0080480d 00228001 33 x: MULADD_IEEE R1.x, R13.z, R2.y, R1.x 0234 0080440d 20228408 y: MULADD_IEEE R1.y, R13.y, R2.y, R8.y 0236 0080400d 41028808 z: MULADD_IEEE R8.z, R13.x, R2.y, R8.z 0238 80804c0b 60828c04 w: MULADD_IEEE R4.w, R11.w, R2.y, R4.w 0240 0080480b 00428007 34 x: MULADD_IEEE R2.x, R11.z, R2.y, R7.x 0242 0080440b 20e28407 y: MULADD_IEEE R7.y, R11.y, R2.y, R7.y 0244 8080400b 40628803 z: MULADD_IEEE R3.z, R11.x, R2.y, R3.z 0246 80000801 60c06b10 35 t: FLT_TO_INT R6.w, R1.z 0248 00804c0a 00628003 36 x: MULADD_IEEE R3.x, R10.w, R2.y, R3.x 0250 0080480a 20c28406 y: MULADD_IEEE R6.y, R10.z, R2.y, R6.y 0252 0080440a 40e28807 z: MULADD_IEEE R7.z, R10.y, R2.y, R7.z 0254 801fac06 60e87010 t: ASHR_INT R7.w, R6.w, [0x0000001f 0].x SCL_212 0256 0000001f 0258 0080400a 00c28006 37 x: MULADD_IEEE R6.x, R10.x, R2.y, R6.x 0260 0080480c 21028409 y: MULADD_IEEE R8.y, R12.z, R2.y, R9.y 0262 00804c0c 41228809 z: MULADD_IEEE R9.z, R12.w, R2.y, R9.z 0264 801f0cfe 60e83d10 w: SETNE_INT R7.w, PV.w, 0 VEC_120 0266 801f0cfe 00004508 38 P x: PRED_SETNE_INT __.x, PV.w, 0 0268 c01fac06 60a03b10 39 0 w: SETGT_INT R5.w, R6.w, [0x0000002c 0].x 0270 0000002c 0272 c180cc05 60a380fd 40 0 w: CNDE_INT R5.w, R5.w, R6.w, [0x0000002c 0].x 0274 0000002c 0276 801fac05 60a07210 41 t: LSHL_INT R5.w, R5.w, [0x00000006 0].x 0278 00000006 0280 801facfe 60c03410 42 w: ADD_INT R6.w, PV.w, [0x00000040 0].x 0282 00000040 0284 001facfe 00e07110 43 x: ADD __.x, R4.x, R0.x 0286 801fac05 60a07110 t: OR_INT R8.x, PV.w, [0x00000003 0].x 0288 00000004 0290 801facfe 01003110 44 x: OR_INT R9.x, R5.w, [0x00000002 0].x 0292 00000003 0294 801fac05 01203110 45 x: OR_INT R10.x, R5.w, 1 0296 00000002 00000000 46 w: MOV R5.w, 0 0012 00000022 80800c00 TEX 4 @68 0068 400a0040 e8cd100a 00080000 VFETCH R10.xyzw, R10.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0072 40090040 e8cd100b 00080000 VFETCH R11.xyzw, R9.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0076 40080040 e8cd100d 00080000 VFETCH R13.xyzw, R8.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0080 40070040 e8cd100c 00080000 VFETCH R12.xyzw, R7.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0014 00000096 a0900000 ALU 37 @300 0300 800000f8 60a01910 47 w: MOV R5.w, 0 0302 0100440c 20628403 48 y: MULADD_IEEE R3.y, R12.y, R2.z, R3.y 0304 0100400c 40c28806 z: MULADD_IEEE R6.z, R12.x, R2.z, R6.z 0306 81004c0d 60628c03 w: MULADD_IEEE R3.w, R13.w, R2.z, R3.w 0308 0100480d 00228001 49 x: MULADD_IEEE R1.x, R13.z, R2.z, R1.x 0310 0100440d 20228401 y: MULADD_IEEE R1.y, R13.y, R2.z, R1.y 0312 0100400d 40228808 z: MULADD_IEEE R1.z, R13.x, R2.z, R8.z 0314 81004c0b 60828c04 w: MULADD_IEEE R4.w, R11.w, R2.z, R4.w 0316 0100480b 00428002 50 x: MULADD_IEEE R2.x, R11.z, R2.z, R2.x 0318 0100440b 20428407 y: MULADD_IEEE R2.y, R11.y, R2.z, R7.y 0320 8100400b 40628803 z: MULADD_IEEE R3.z, R11.x, R2.z, R3.z 0322 80000c01 60206b10 51 t: FLT_TO_INT R1.w, R1.w 0324 01004c0a 00628003 52 x: MULADD_IEEE R3.x, R10.w, R2.z, R3.x 0326 0100480a 20c28406 y: MULADD_IEEE R6.y, R10.z, R2.z, R6.y 0328 0100440a 40e28807 z: MULADD_IEEE R7.z, R10.y, R2.z, R7.z 0330 801fac01 60c87010 t: ASHR_INT R6.w, R1.w, [0x0000001f 0].x SCL_212 0332 0000001f 0334 0100400a 00c28006 53 x: MULADD_IEEE R6.x, R10.x, R2.z, R6.x 0336 0100480c 20e28408 y: MULADD_IEEE R7.y, R12.z, R2.z, R8.y 0338 01004c0c 40428809 z: MULADD_IEEE R2.z, R12.w, R2.z, R9.z 0340 801f0cfe 60c83d10 w: SETNE_INT R6.w, PV.w, 0 VEC_120 0342 801f0cfe 00004508 54 P x: PRED_SETNE_INT __.x, PV.w, 0 0344 c01fac01 60a03b10 55 0 w: SETGT_INT R5.w, R1.w, [0x0000002c 0].x 0346 0000002c 0348 c1802c05 60a380fd 56 0 w: CNDE_INT R5.w, R5.w, R1.w, [0x0000002c 0].x 0350 0000002c 0352 801fac05 60207210 57 t: LSHL_INT R1.w, R5.w, [0x00000002 0].x 0354 00000002 0356 001fac05 41007210 58 t: LSHL_INT R8.z, R5.w, [0x00000006 0].x 0358 809facfe 60283410 w: ADD_INT R1.w, PV.w, [0x00000004 0].y VEC_120 0360 00000006 0361 00000004 0362 001facfe 00e03010 59 x: AND_INT R7.x, PV.w, [0x0ffffffc 2,52435e-29].x 0364 809fa8fe 60207110 t: LSHR_INT R1.w, PV.z, [0x00000004 0].y 0366 0ffffffc 0367 00000004 0368 801f4cfe 01203110 60 x: OR_INT R9.x, PV.w, 1 0370 801fac01 01003110 61 x: OR_INT R8.x, R1.w, [0x00000002 0].x 0372 00000002 0016 0000002a 80800800 TEX 3 @84 0084 40080040 e8cd1008 00080000 VFETCH R8.xyzw, R8.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0088 40090040 e8cd1009 00080000 VFETCH R9.xyzw, R9.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0092 40070040 e8cd100a 00080000 VFETCH R10.xyzw, R7.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0018 800000bb a128302a ALU 75 @374 KC0[CB0:160-191] KC1[CB0:192-223] 0374 00140099 41600210 62 z: MUL_IEEE R11.z, KC0[25].x, KC1[0].x 0376 80140499 60a00210 w: MUL_IEEE R5.w, KC0[25].y, KC1[0].x 0378 0094049a 41828cfe 63 z: MULADD_IEEE R12.z, KC0[26].y, KC1[0].y, PV.w 0380 8094009a 60a288fe w: MULADD_IEEE R5.w, KC0[26].x, KC1[0].y, PV.z 0382 0114009b 41628cfe 64 z: MULADD_IEEE R11.z, KC0[27].x, KC1[0].z, PV.w 0384 8114049b 60a288fe w: MULADD_IEEE R5.w, KC0[27].y, KC1[0].z, PV.z 0386 8194049c 60a28cfe 65 w: MULADD_IEEE R5.w, KC0[28].y, KC1[0].w, PV.w 0388 00140c99 41800210 66 z: MUL_IEEE R12.z, KC0[25].w, KC1[0].x 0390 80140899 60c00210 w: MUL_IEEE R6.w, KC0[25].z, KC1[0].x 0392 0094089a 41c28cfe 67 z: MULADD_IEEE R14.z, KC0[26].z, KC1[0].y, PV.w 0394 80940c9a 60c288fe w: MULADD_IEEE R6.w, KC0[26].w, KC1[0].y, PV.z 0396 01140c9b 41a28cfe 68 z: MULADD_IEEE R13.z, KC0[27].w, KC1[0].z, PV.w 0398 8114089b 60c288fe w: MULADD_IEEE R6.w, KC0[27].z, KC1[0].z, PV.z 0400 0194089c 41828cfe 69 z: MULADD_IEEE R12.z, KC0[28].z, KC1[0].w, PV.w 0402 81940c9c 60c288fe w: MULADD_IEEE R6.w, KC0[28].w, KC1[0].w, PV.z 0404 0013e899 41a00210 70 z: MUL_IEEE R13.z, KC0[25].z, KC0[31].x 0406 8013ec99 60e00210 w: MUL_IEEE R7.w, KC0[25].w, KC0[31].x 0408 0093ec9a 41c28cfe 71 z: MULADD_IEEE R14.z, KC0[26].w, KC0[31].y, PV.w 0410 8093e89a 60e288fe w: MULADD_IEEE R7.w, KC0[26].z, KC0[31].y, PV.z 0412 0113e89b 41a28cfe 72 z: MULADD_IEEE R13.z, KC0[27].z, KC0[31].z, PV.w 0414 8113ec9b 60e288fe w: MULADD_IEEE R7.w, KC0[27].w, KC0[31].z, PV.z 0416 0013c899 41e00210 73 z: MUL_IEEE R15.z, KC0[25].z, KC0[30].x 0418 8013cc99 61600210 w: MUL_IEEE R11.w, KC0[25].w, KC0[30].x 0420 0093cc9a 41c28cfe 74 z: MULADD_IEEE R14.z, KC0[26].w, KC0[30].y, PV.w 0422 8093c89a 616288fe w: MULADD_IEEE R11.w, KC0[26].z, KC0[30].y, PV.z 0424 0113c89b 41e28cfe 75 z: MULADD_IEEE R15.z, KC0[27].z, KC0[30].z, PV.w 0426 8113cc9b 616288fe w: MULADD_IEEE R11.w, KC0[27].w, KC0[30].z, PV.z 0428 8193cc9c 61628cfe 76 w: MULADD_IEEE R11.w, KC0[28].w, KC0[30].w, PV.w 0430 0013ac99 41c00210 77 z: MUL_IEEE R14.z, KC0[25].w, KC0[29].x 0432 8013a899 61800210 w: MUL_IEEE R12.w, KC0[25].z, KC0[29].x 0434 0093a89a 42028cfe 78 z: MULADD_IEEE R16.z, KC0[26].z, KC0[29].y, PV.w 0436 8093ac9a 618288fe w: MULADD_IEEE R12.w, KC0[26].w, KC0[29].y, PV.z 0438 0013e499 41c00210 79 z: MUL_IEEE R14.z, KC0[25].y, KC0[31].x 0440 8013e099 61a00210 w: MUL_IEEE R13.w, KC0[25].x, KC0[31].x 0442 0093e09a 42428cfe 80 z: MULADD_IEEE R18.z, KC0[26].x, KC0[31].y, PV.w 0444 8093e49a 61a288fe w: MULADD_IEEE R13.w, KC0[26].y, KC0[31].y, PV.z 0446 0113e49b 42228cfe 81 z: MULADD_IEEE R17.z, KC0[27].y, KC0[31].z, PV.w 0448 8113e09b 61a288fe w: MULADD_IEEE R13.w, KC0[27].x, KC0[31].z, PV.z 0450 0193e09c 41c28cfe 82 z: MULADD_IEEE R14.z, KC0[28].x, KC0[31].w, PV.w 0452 8193e49c 61a288fe w: MULADD_IEEE R13.w, KC0[28].y, KC0[31].w, PV.z 0454 8013c099 61c00210 83 w: MUL_IEEE R14.w, KC0[25].x, KC0[30].x 0456 8093c09a 61c28cfe 84 w: MULADD_IEEE R14.w, KC0[26].x, KC0[30].y, PV.w 0458 0113c09b 42228cfe 85 z: MULADD_IEEE R17.z, KC0[27].x, KC0[30].z, PV.w 0460 8180400a 62228806 w: MULADD_IEEE R17.w, R10.x, R2.w, R6.z 0462 019fc895 21600210 86 y: MUL_IEEE R11.y, KC0[21].z, PV.w 0464 0180440a 40c28403 z: MULADD_IEEE R6.z, R10.y, R2.w, R3.y 0466 81804009 61e28006 w: MULADD_IEEE R15.w, R9.x, R2.w, R6.x 0468 019fcc95 00e00210 87 x: MUL_IEEE R7.x, KC0[21].w, PV.w 0470 01804409 20628807 y: MULADD_IEEE R3.y, R9.y, R2.w, R7.z 0472 011fc896 40e284fe z: MULADD_IEEE R7.z, KC0[22].z, PV.z, PV.y 0474 8180480a 61c28407 w: MULADD_IEEE R14.w, R10.z, R2.w, R7.y 0476 019fc897 00c288fe 88 x: MULADD_IEEE R6.x, KC0[23].z, PV.w, PV.z 0478 01804008 20e28803 y: MULADD_IEEE R7.y, R8.x, R2.w, R3.z 0480 009fcc96 406280fe z: MULADD_IEEE R3.z, KC0[22].w, PV.y, PV.x 0482 81804809 62028406 w: MULADD_IEEE R16.w, R9.z, R2.w, R6.y 0484 019fcc97 00e288fe 89 x: MULADD_IEEE R7.x, KC0[23].w, PV.w, PV.z 0486 009fcc95 20c00210 y: MUL_IEEE R6.y, KC0[21].w, PV.y 0488 01804408 40628402 z: MULADD_IEEE R3.z, R8.y, R2.w, R2.y 0490 81822c95 62440210 w: MUL_IEEE R18.w, KC0[21].w, R17.w VEC_021 0492 01804c09 00628003 90 x: MULADD_IEEE R3.x, R9.w, R2.w, R3.x 0494 0100cc96 20428cfe y: MULADD_IEEE R2.y, KC0[22].w, R6.z, PV.w 0496 011fcc96 40e684fe z: MULADD_IEEE R7.z, KC0[22].w, PV.z, PV.y VEC_021 0498 81804808 62468002 w: MULADD_IEEE R18.w, R8.z, R2.w, R2.x VEC_021 0500 019fcc97 012288fe 91 x: MULADD_IEEE R9.x, KC0[23].w, PV.w, PV.z 0502 81804c08 20c28c04 y: MULADD_IEEE R6.y, R8.w, R2.w, R4.w 0504 0181cc97 40e28402 92 z: MULADD_IEEE R7.z, KC0[23].w, R14.w, R2.y 0506 81804c0a 61068802 w: MULADD_IEEE R8.w, R10.w, R2.w, R2.z VEC_021 0508 019fcc98 004288fe 93 x: MULADD_IEEE R2.x, KC0[24].w, PV.w, PV.z 0510 0080cc98 20428009 y: MULADD_IEEE R2.y, KC0[24].w, R6.y, R9.x 0512 80006c98 40528007 z: MULADD_IEEE R2.z, KC0[24].w, R3.x, R7.x VEC_201 0514 81810898 60828006 94 w: MULADD_IEEE R4.w, KC0[24].z, R8.w, R6.x 0516 8013c499 61200210 95 w: MUL_IEEE R9.w, KC0[25].y, KC0[30].x 0518 001fac01 00c03110 96 x: OR_INT R6.x, R1.w, [0x00000003 0].x 0520 8093c49a 60228cfe w: MULADD_IEEE R1.w, KC0[26].y, KC0[30].y, PV.w 0522 00000003 0020 00000030 80800000 TEX 1 @96 0096 40060040 e8cd100a 00080000 VFETCH R10.xyzw, R6.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0022 80000106 a1bc002a ALU 112 @524 KC0[CB0:160-191] KC1[CB0:0-31] 0524 8113c49b 61228c01 97 w: MULADD_IEEE R9.w, KC0[27].y, KC0[30].z, R1.w 0526 0013a499 41000210 98 z: MUL_IEEE R8.z, KC0[25].y, KC0[29].x 0528 8013a099 60200210 w: MUL_IEEE R1.w, KC0[25].x, KC0[29].x 0530 0093a09a 40e28cfe 99 z: MULADD_IEEE R7.z, KC0[26].x, KC0[29].y, PV.w 0532 8093a49a 602288fe w: MULADD_IEEE R1.w, KC0[26].y, KC0[29].y, PV.z 0534 0113a49b 41028cfe 100 z: MULADD_IEEE R8.z, KC0[27].y, KC0[29].z, PV.w 0536 8113a09b 602288fe w: MULADD_IEEE R1.w, KC0[27].x, KC0[29].z, PV.z 0538 0193a09c 21028cfe 101 y: MULADD_IEEE R8.y, KC0[28].x, KC0[29].w, PV.w 0540 0193a49c 40e288fe z: MULADD_IEEE R7.z, KC0[28].y, KC0[29].w, PV.z 0542 8180400a 62628801 w: MULADD_IEEE R19.w, R10.x, R2.w, R1.z 0544 01822095 00c00210 102 x: MUL_IEEE R6.x, KC0[21].x, R17.w 0546 019fcc95 21240210 y: MUL_IEEE R9.y, KC0[21].w, PV.w VEC_021 0548 019fc895 40240210 z: MUL_IEEE R1.z, KC0[21].z, PV.w VEC_021 0550 8180440a 60268401 w: MULADD_IEEE R1.w, R10.y, R2.w, R1.y VEC_021 0552 01826095 00e00210 103 x: MUL_IEEE R7.x, KC0[21].x, R19.w 0554 019fc896 202688fe y: MULADD_IEEE R1.y, KC0[22].z, PV.w, PV.z VEC_021 0556 019fcc96 402684fe z: MULADD_IEEE R1.z, KC0[22].w, PV.w, PV.y VEC_021 0558 8180480a 62868001 w: MULADD_IEEE R20.w, R10.z, R2.w, R1.x VEC_021 0560 019fcc97 002288fe 104 x: MULADD_IEEE R1.x, KC0[23].w, PV.w, PV.z 0562 019fc897 212284fe y: MULADD_IEEE R9.y, KC0[23].z, PV.w, PV.y 0564 01802096 402280fe z: MULADD_IEEE R1.z, KC0[22].x, R1.w, PV.x 0566 8100c096 62a28006 w: MULADD_IEEE R21.w, KC0[22].x, R6.z, R6.x 0568 0181c097 00e28cfe 105 x: MULADD_IEEE R7.x, KC0[23].x, R14.w, PV.w 0570 01828097 216688fe y: MULADD_IEEE R11.y, KC0[23].x, R20.w, PV.z VEC_021 0572 0080e095 40200210 z: MUL_IEEE R1.z, KC0[21].x, R7.y 0574 8181e095 62ac0210 w: MUL_IEEE R21.w, KC0[21].x, R15.w VEC_102 0576 0080e495 01000210 106 x: MUL_IEEE R8.x, KC0[21].y, R7.y 0578 0181e495 20200210 y: MUL_IEEE R1.y, KC0[21].y, R15.w 0580 00806096 410a8cfe z: MULADD_IEEE R8.z, KC0[22].x, R3.y, PV.w VEC_120 0582 81006096 62a288fe w: MULADD_IEEE R21.w, KC0[22].x, R3.z, PV.z 0584 01824097 00c28cfe 107 x: MULADD_IEEE R6.x, KC0[23].x, R18.w, PV.w 0586 01820097 21a688fe y: MULADD_IEEE R13.y, KC0[23].x, R16.w, PV.z VEC_021 0588 00806496 402284fe z: MULADD_IEEE R1.z, KC0[22].y, R3.y, PV.y 0590 81006496 62a280fe w: MULADD_IEEE R21.w, KC0[22].y, R3.z, PV.x 0592 01824497 01028cfe 108 x: MULADD_IEEE R8.x, KC0[23].y, R18.w, PV.w 0594 01826495 20240210 y: MUL_IEEE R1.y, KC0[21].y, R19.w VEC_021 0596 81820497 402e88fe z: MULADD_IEEE R1.z, KC0[23].y, R16.w, PV.z VEC_102 0598 81822495 62200210 109 w: MUL_IEEE R17.w, KC0[21].y, R17.w 0600 0100c496 21828cfe 110 y: MULADD_IEEE R12.y, KC0[22].y, R6.z, PV.w 0602 00006498 41028801 z: MULADD_IEEE R8.z, KC0[24].y, R3.x, R1.z 0604 81802496 60228401 w: MULADD_IEEE R1.w, KC0[22].y, R1.w, R1.y 0606 81828497 01628cfe 111 x: MULADD_IEEE R11.x, KC0[23].y, R20.w, PV.w 0608 01804c0a 20228c03 112 y: MULADD_IEEE R1.y, R10.w, R2.w, R3.w 0610 0000a808 40200210 z: MUL_IEEE R1.z, R8.z, R5.x 0612 8080c498 60228008 w: MULADD_IEEE R1.w, KC0[24].y, R6.y, R8.x 0614 0181e895 01200210 113 x: MUL_IEEE R9.x, KC0[21].z, R15.w 0616 0080e895 20e00210 y: MUL_IEEE R7.y, KC0[21].z, R7.y 0618 0080acfe 402688fe z: MULADD_IEEE R1.z, PV.w, R5.y, PV.z VEC_021 0620 809fc498 604e800b w: MULADD_IEEE R2.w, KC0[24].y, PV.y, R11.x VEC_102 0622 0100acfe 010288fe 114 x: MULADD_IEEE R8.x, PV.w, R5.z, PV.z 0624 01006896 20e684fe y: MULADD_IEEE R7.y, KC0[22].z, R3.z, PV.y VEC_021 0626 00006098 40c2840d z: MULADD_IEEE R6.z, KC0[24].x, R3.x, R13.y 0628 80806896 606280fe w: MULADD_IEEE R3.w, KC0[22].z, R3.y, PV.x 0630 01820897 01228cfe 115 x: MULADD_IEEE R9.x, KC0[23].z, R16.w, PV.w 0632 0000a8fe 20600210 y: MUL_IEEE R3.y, PV.z, R5.x 0634 0080c098 40628006 z: MULADD_IEEE R3.z, KC0[24].x, R6.y, R6.x 0636 81824897 606a84fe w: MULADD_IEEE R3.w, KC0[23].z, R18.w, PV.y VEC_120 0638 0080c898 00c28cfe 116 x: MULADD_IEEE R6.x, KC0[24].z, R6.y, PV.w 0640 8080a8fe 206a84fe y: MULADD_IEEE R3.y, PV.z, R5.y, PV.y VEC_120 0642 00802098 4022840b 117 z: MULADD_IEEE R1.z, KC0[24].x, R1.y, R11.y 0644 80006898 61428009 w: MULADD_IEEE R10.w, KC0[24].z, R3.x, R9.x 0646 0000acfe 00600210 118 x: MUL_IEEE R3.x, PV.w, R5.x 0648 0100a8fe 20628403 y: MULADD_IEEE R3.y, PV.z, R5.z, R3.y 0650 01810098 41228007 z: MULADD_IEEE R9.z, KC0[24].x, R8.w, R7.x 0652 8181c497 6066840c w: MULADD_IEEE R3.w, KC0[23].y, R14.w, R12.y VEC_021 0654 01810498 00e28cfe 119 x: MULADD_IEEE R7.x, KC0[24].y, R8.w, PV.w 0656 011fc4fe 20e00010 y: ADD R7.y, PV.y, PV.z 0658 0080a006 412280fe z: MULADD_IEEE R9.z, R6.x, R5.y, PV.x 0660 80802898 606a8409 w: MULADD_IEEE R3.w, KC0[24].z, R1.y, R9.y VEC_120 0662 0100acfe 006288fe 120 x: MULADD_IEEE R3.x, PV.w, R5.z, PV.z 0664 009fc807 20600210 y: MUL_IEEE R3.y, R7.z, PV.y 0666 001fc008 40e00010 z: ADD R7.z, R8.x, PV.x 0668 8193c49c 61028c09 w: MULADD_IEEE R8.w, KC0[28].y, KC0[30].w, R9.w 0670 011fccfe 00e284fe 121 x: MULADD_IEEE R7.x, PV.w, PV.z, PV.y 0672 018080fe 20600010 y: ADD R3.y, PV.x, R4.w 0674 0080e408 41200210 z: MUL_IEEE R9.z, R8.y, R7.y 0676 8193c09c 60828811 w: MULADD_IEEE R4.w, KC0[28].x, KC0[30].w, R17.z 0678 0100ecfe 006288fe 122 x: MULADD_IEEE R3.x, PV.w, R7.z, PV.z 0680 009fcc0d 20c280fe y: MULADD_IEEE R6.y, R13.w, PV.y, PV.x 0682 0113ac9b 41228c0c z: MULADD_IEEE R9.z, KC0[27].w, KC0[29].z, R12.w 0684 8113a89b 60828810 w: MULADD_IEEE R4.w, KC0[27].z, KC0[29].z, R16.z 0686 00008808 00e00210 123 x: MUL_IEEE R7.x, R8.z, R4.x 0688 0193a89c 21028cfe y: MULADD_IEEE R8.y, KC0[28].z, KC0[29].w, PV.w 0690 0000a802 40480210 z: MUL_IEEE R2.z, R2.z, R5.x VEC_120 0692 8193ac9c 608288fe w: MULADD_IEEE R4.w, KC0[28].w, KC0[29].w, PV.z 0694 0080ecfe 00a00210 124 x: MUL_IEEE R5.x, PV.w, R7.y 0696 8080a402 204688fe y: MULADD_IEEE R2.y, R2.y, R5.y, PV.z VEC_021 0698 00802c98 40428001 125 z: MULADD_IEEE R2.z, KC0[24].w, R1.y, R1.x 0700 80008c0a 60800210 w: MUL_IEEE R4.w, R10.w, R4.x 0702 00808006 00228cfe 126 x: MULADD_IEEE R1.x, R6.x, R4.y, PV.w 0704 0100a8fe 20228402 y: MULADD_IEEE R1.y, PV.z, R5.z, R2.y 0706 0100ec0b 40468005 z: MULADD_IEEE R2.z, R11.w, R7.z, R5.x VEC_021 0708 8193ec9c 60828c07 w: MULADD_IEEE R4.w, KC0[28].w, KC0[31].w, R7.w 0710 00806cfe 00a288fe 127 x: MULADD_IEEE R5.x, PV.w, R3.y, PV.z 0712 000044fe 20200010 y: ADD R1.y, PV.y, R2.x 0714 0080e408 40440210 z: MUL_IEEE R2.z, R8.y, R7.y VEC_021 0716 8193c89c 6082880f w: MULADD_IEEE R4.w, KC0[28].z, KC0[30].w, R15.z 0718 00008806 00800210 128 x: MUL_IEEE R4.x, R6.z, R4.x 0720 0100ecfe 204288fe y: MULADD_IEEE R2.y, PV.w, R7.z, PV.z 0722 0193e89c 4042880d z: MULADD_IEEE R2.z, KC0[28].z, KC0[31].w, R13.z 0724 809fcc06 612280fe w: MULADD_IEEE R9.w, R6.w, PV.y, PV.x 0726 008068fe 004284fe 129 x: MULADD_IEEE R2.x, PV.z, R3.y, PV.y 0728 000004a0 20001910 y: MOV R0.y, KC1[0].y 0730 00808803 404680fe z: MULADD_IEEE R2.z, R3.z, R4.y, PV.x VEC_021 0732 81008c03 61028001 w: MULADD_IEEE R8.w, R3.w, R4.z, R1.x 0734 000000a0 00001910 130 x: MOV R0.x, KC1[0].x 0736 01008801 210288fe y: MULADD_IEEE R8.y, R1.z, R4.z, PV.z 0738 0080280c 413280fe z: MULADD_IEEE R9.z, R12.z, R1.y, PV.x VEC_201 0740 80808c01 60228007 w: MULADD_IEEE R1.w, R1.w, R4.y, R7.x 0742 01008c02 01028cfe 131 x: MULADD_IEEE R8.x, R2.w, R4.z, PV.w 0744 00802c05 212a8406 y: MULADD_IEEE R9.y, R5.w, R1.y, R6.y VEC_120 0746 8080680e 40228003 z: MULADD_IEEE R1.z, R14.z, R3.y, R3.x 0024 80000176 a004302a ALU 2 @748 KC0[CB0:160-191] KC1[CB0:192-223] 0748 8194009c 6022880b 132 w: MULADD_IEEE R1.w, KC0[28].x, KC1[0].w, R11.z 0750 80802cfe 01228801 133 x: MULADD_IEEE R9.x, PV.w, R1.y, R1.z 0026 80000178 a0000000 ALU 1 @752 KC0[CB0:0-31] 0752 80000880 41001910 134 z: MOV R8.z, KC0[0].z 0028 c004a03c 94400688 EXPORT_DONE POS 60 R9.xyzw VPM 0030 c0004000 93c0021a EXPORT PARAM 0 R0.zwxy VPM 0032 c0044001 9460060a EXPORT_DONE PARAM 1 R8.zyxw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R16G16B16A16_SSCALED, } {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 1, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 2, src_format = PIPE_FORMAT_R32G32_FLOAT, } {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 3, src_format = PIPE_FORMAT_R32G32B32_FLOAT, } {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 4, src_format = PIPE_FORMAT_R32G32B32_FLOAT, } ===== SHADER #51 ======================================== FETCH/RS880/R600 ===== ===== 24 dw ===== 6 gprs ===== 0 stack ========================================= 0000 00000002 81001000 VTX 5 @4 0004 7c00a000 e7cd1001 00080000 VFETCH R1.xyzw, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:31 NUM:2 COMP:1 MODE:1) 0008 7c00a100 88cd1002 00080000 VFETCH R2.xyzw, R0.x, RID:161 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0012 7c00a200 87961003 00080000 VFETCH R3.xy01, R0.x, RID:162 VERTEX MFC:31 UCF:0 FMT(DTA:30 NUM:0 COMP:0 MODE:1) 0016 7c00a300 8c151004 00080000 VFETCH R4.xyz1, R0.x, RID:163 VERTEX MFC:31 UCF:0 FMT(DTA:48 NUM:0 COMP:0 MODE:1) 0020 7c00a400 8c151005 00080000 VFETCH R5.xyz1, R0.x, RID:164 VERTEX MFC:31 UCF:0 FMT(DTA:48 NUM:0 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[19], PERSPECTIVE DCL IN[1], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0..1] DCL TEMP[0..4], LOCAL IMM[0] FLT32 { 0,7500, 0,2500, 0,0000, 2,0000} 0: MOV TEMP[0].z, IN[1].xxxx 1: MOV TEMP[0].xy, IN[0].zwzz 2: MOV TEMP[1].xy, IN[0].xyyy 3: TEX TEMP[1], TEMP[1], SAMP[0], 2D 4: MOV TEMP[2].xyz, CONST[1] 5: DP3 TEMP[3].x, IN[1].yzww, IN[1].yzww 6: RSQ TEMP[3].x, TEMP[3].xxxx 7: MUL TEMP[3].xyz, IN[1].yzww, TEMP[3].xxxx 8: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz 9: RSQ TEMP[4].x, TEMP[4].xxxx 10: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[4].xxxx 11: DP3 TEMP[0].x, TEMP[3].xyzz, TEMP[0].xyzz 12: MAD TEMP[0].x, TEMP[0].xxxx, IMM[0].xxxx, IMM[0].yyyy 13: SLT TEMP[3].x, IMM[0].zzzz, TEMP[0].xxxx 14: F2I TEMP[3].x, -TEMP[3] 15: UIF TEMP[3].xxxx :0 16: MUL TEMP[0], CONST[0], TEMP[0].xxxx 17: MAD TEMP[2].xyz, TEMP[0], IMM[0].wwww, CONST[1] 18: ENDIF 19: MUL TEMP[0].xyz, TEMP[1].xyzz, TEMP[2].xyzz 20: MOV TEMP[0].w, TEMP[1].wwww 21: MOV OUT[0], TEMP[0] 22: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = call float @llvm.R600.load.input(i32 4) %5 = call float @llvm.R600.load.input(i32 5) %6 = call float @llvm.R600.load.input(i32 6) %7 = call float @llvm.R600.load.input(i32 7) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float 0,000000e+00, i32 2 %11 = insertelement <4 x float> %10, float 0,000000e+00, i32 3 %12 = extractelement <4 x float> %11, i32 0 %13 = extractelement <4 x float> %11, i32 1 %14 = insertelement <4 x float> undef, float %12, i32 0 %15 = insertelement <4 x float> %14, float %13, i32 1 %16 = insertelement <4 x float> %15, float undef, i32 2 %17 = insertelement <4 x float> %16, float undef, i32 3 %18 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %17, i32 16, i32 0, i32 2) %19 = extractelement <4 x float> %18, i32 0 %20 = extractelement <4 x float> %18, i32 1 %21 = extractelement <4 x float> %18, i32 2 %22 = extractelement <4 x float> %18, i32 3 %23 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %24 = extractelement <4 x float> %23, i32 0 %25 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %26 = extractelement <4 x float> %25, i32 1 %27 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %28 = extractelement <4 x float> %27, i32 2 %29 = insertelement <4 x float> undef, float %5, i32 0 %30 = insertelement <4 x float> %29, float %6, i32 1 %31 = insertelement <4 x float> %30, float %7, i32 2 %32 = insertelement <4 x float> %31, float 0,000000e+00, i32 3 %33 = insertelement <4 x float> undef, float %5, i32 0 %34 = insertelement <4 x float> %33, float %6, i32 1 %35 = insertelement <4 x float> %34, float %7, i32 2 %36 = insertelement <4 x float> %35, float 0,000000e+00, i32 3 %37 = call float @llvm.AMDGPU.dp4(<4 x float> %32, <4 x float> %36) %38 = call float @fabs(float %37) %39 = call float @llvm.AMDGPU.rsq(float %38) %40 = fmul float %5, %39 %41 = fmul float %6, %39 %42 = fmul float %7, %39 %43 = insertelement <4 x float> undef, float %2, i32 0 %44 = insertelement <4 x float> %43, float %3, i32 1 %45 = insertelement <4 x float> %44, float %4, i32 2 %46 = insertelement <4 x float> %45, float 0,000000e+00, i32 3 %47 = insertelement <4 x float> undef, float %2, i32 0 %48 = insertelement <4 x float> %47, float %3, i32 1 %49 = insertelement <4 x float> %48, float %4, i32 2 %50 = insertelement <4 x float> %49, float 0,000000e+00, i32 3 %51 = call float @llvm.AMDGPU.dp4(<4 x float> %46, <4 x float> %50) %52 = call float @fabs(float %51) %53 = call float @llvm.AMDGPU.rsq(float %52) %54 = fmul float %2, %53 %55 = fmul float %3, %53 %56 = fmul float %4, %53 %57 = insertelement <4 x float> undef, float %40, i32 0 %58 = insertelement <4 x float> %57, float %41, i32 1 %59 = insertelement <4 x float> %58, float %42, i32 2 %60 = insertelement <4 x float> %59, float 0,000000e+00, i32 3 %61 = insertelement <4 x float> undef, float %54, i32 0 %62 = insertelement <4 x float> %61, float %55, i32 1 %63 = insertelement <4 x float> %62, float %56, i32 2 %64 = insertelement <4 x float> %63, float 0,000000e+00, i32 3 %65 = call float @llvm.AMDGPU.dp4(<4 x float> %60, <4 x float> %64) %66 = fmul float %65, 0x3FE8000000000000 %67 = fadd float %66, 0x3FD0000000000000 %68 = fcmp ult float 0,000000e+00, %67 %69 = select i1 %68, float 0x3FF0000000000000, float 0,000000e+00 %70 = fsub float -0,000000e+00, %69 %71 = fptosi float %70 to i32 %72 = bitcast i32 %71 to float %73 = bitcast float %72 to i32 %74 = icmp ne i32 %73, 0 br i1 %74, label %IF, label %ENDIF IF: ; preds = %main_body %75 = load <4 x float> addrspace(8)* null %76 = extractelement <4 x float> %75, i32 0 %77 = fmul float %76, %67 %78 = load <4 x float> addrspace(8)* null %79 = extractelement <4 x float> %78, i32 1 %80 = fmul float %79, %67 %81 = load <4 x float> addrspace(8)* null %82 = extractelement <4 x float> %81, i32 2 %83 = fmul float %82, %67 %84 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %85 = extractelement <4 x float> %84, i32 0 %86 = fmul float %77, 0x4000000000000000 %87 = fadd float %86, %85 %88 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %89 = extractelement <4 x float> %88, i32 1 %90 = fmul float %80, 0x4000000000000000 %91 = fadd float %90, %89 %92 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %93 = extractelement <4 x float> %92, i32 2 %94 = fmul float %83, 0x4000000000000000 %95 = fadd float %94, %93 br label %ENDIF ENDIF: ; preds = %main_body, %IF %temp8.0 = phi float [ %87, %IF ], [ %24, %main_body ] %temp9.0 = phi float [ %91, %IF ], [ %26, %main_body ] %temp10.0 = phi float [ %95, %IF ], [ %28, %main_body ] %96 = fmul float %19, %temp8.0 %97 = fmul float %20, %temp9.0 %98 = fmul float %21, %temp10.0 %99 = insertelement <4 x float> undef, float %96, i32 0 %100 = insertelement <4 x float> %99, float %97, i32 1 %101 = insertelement <4 x float> %100, float %98, i32 2 %102 = insertelement <4 x float> %101, float %22, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %102, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } ===== SHADER #52 =========================================== PS/RS880/R600 ===== ===== 110 dw ===== 4 gprs ===== 0 stack ======================================== 0000 00000004 80800000 TEX 1 @8 0008 00001010 f00d1002 68800000 SAMPLE R2.xyzw, R0.xyzw, RID:16, SID:0 CT:NNNN 0002 80000006 a0c00000 ALU 49 @12 KC0[CB0:0-31] 0012 80000c01 40601910 1 z: MOV R3.z, R1.w 0014 80000801 20601910 2 y: MOV R3.y, R1.z 0016 00000401 00601910 3 x: MOV R3.x, R1.y 0018 80000001 40201910 z: MOV R1.z, R1.x 0020 80000c00 20001910 4 y: MOV R0.y, R0.w 0022 00000800 00001910 5 x: MOV R0.x, R0.z 0024 800000fd 60001910 w: MOV R0.w, [0x00000000 0].x 0026 00000000 0028 00006003 00005000 6 x: DOT4 __.x, R3.x, R3.x 0030 00806403 20005000 y: DOT4 __.y, R3.y, R3.y 0032 01006803 40005010 z: DOT4 R0.z, R3.z, R3.z 0034 81800c00 60005000 w: DOT4 __.w, R0.w, R0.w 0036 80000800 60606711 7 t: RECIPSQRT_CLAMPED R3.w, |R0.z| 0038 00000000 00205000 8 x: DOT4 __.x, R0.x, R0.x 0040 00800400 20205000 y: DOT4 __.y, R0.y, R0.y 0042 01002801 40205000 z: DOT4 __.z, R1.z, R1.z 0044 81800c00 60205010 w: DOT4 R1.w, R0.w, R0.w 0046 01806003 00200210 9 x: MUL_IEEE R1.x, R3.x, R3.w 0048 01806403 20200210 y: MUL_IEEE R1.y, R3.y, R3.w 0050 81806803 40000210 z: MUL_IEEE R0.z, R3.z, R3.w 0052 80000c01 60206711 10 t: RECIPSQRT_CLAMPED R1.w, |R1.w| 0054 01802000 00000210 11 x: MUL_IEEE R0.x, R0.x, R1.w 0056 01802400 20000210 y: MUL_IEEE R0.y, R0.y, R1.w 0058 01802801 40200210 z: MUL_IEEE R1.z, R1.z, R1.w 0060 800000fd 60201910 w: MOV R1.w, [0x3f400000 0,75].x 0062 3f400000 0064 00000001 00005010 12 x: DOT4 R0.x, R1.x, R0.x 0066 00800401 20005000 y: DOT4 __.y, R1.y, R0.y 0068 01002800 40005000 z: DOT4 __.z, R0.z, R1.z 0070 81800c00 60005000 w: DOT4 __.w, R0.w, R0.w 0072 818020fe 600280fd 13 w: MULADD_IEEE R0.w, PV.x, R1.w, [0x3e800000 0,25].x 0074 3e800000 0076 819fc0f8 60200e10 14 w: SETGE_DX10 R1.w, 0, PV.w 0078 801f0cfe 00004208 15 P x: PRED_SETE_INT __.x, PV.w, 0 0080 40000881 20001910 16 0 y: MOV R0.y, KC0[1].z 0082 40000081 40001910 0 z: MOV R0.z, KC0[1].x 0084 c0000481 60001910 0 w: MOV R0.w, KC0[1].y 0086 61800880 20000210 17 1 y: MUL_IEEE R0.y, KC0[0].z, R0.w 0088 61800080 40000210 1 z: MUL_IEEE R0.z, KC0[0].x, R0.w 0090 e1800480 60200210 1 w: MUL_IEEE R1.w, KC0[0].y, R0.w 0092 61800480 20228c01 18 1 y: MULADD_IEEE R1.y, KC0[0].y, R0.w, R1.w 0094 61800080 40028800 1 z: MULADD_IEEE R0.z, KC0[0].x, R0.w, R0.z 0096 e1800880 60028400 1 w: MULADD_IEEE R0.w, KC0[0].z, R0.w, R0.y 0098 61102c00 20000010 19 1 y: ADD R0.y, R0.w, KC0[1].z 0100 60102800 40000010 1 z: ADD R0.z, R0.z, KC0[1].x 0102 e0902401 60000010 1 w: ADD R0.w, R1.y, KC0[1].y 0104 80800802 40400210 20 z: MUL_IEEE R2.z, R2.z, R0.y 0106 81000002 00400210 21 x: MUL_IEEE R2.x, R2.x, R0.z 0108 81800402 20400210 22 y: MUL_IEEE R2.y, R2.y, R0.w 0004 c0010000 94600688 EXPORT_DONE PIXEL 0 R2.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL OUT[0], POSITION DCL OUT[1], GENERIC[19] DCL OUT[2], GENERIC[20] DCL CONST[0..60] DCL TEMP[0..3], ARRAY(1), LOCAL DCL TEMP[4..7], ARRAY(2), LOCAL DCL TEMP[8..10], LOCAL DCL TEMP[11..14], ARRAY(3), LOCAL DCL TEMP[15..18], ARRAY(4), LOCAL DCL TEMP[19..22], ARRAY(5), LOCAL DCL TEMP[23..26], ARRAY(6), LOCAL DCL TEMP[27..29], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0,0000, 0,0000, 0,0000, 0,0000} IMM[1] INT32 {0, 11, 4, 0} 0: MOV TEMP[0], IMM[0].xxxx 1: MOV TEMP[1], IMM[0].xxxx 2: MOV TEMP[2], IMM[0].xxxx 3: MOV TEMP[3], IMM[0].xxxx 4: MOV TEMP[4], TEMP[0] 5: MOV TEMP[5], TEMP[1] 6: MOV TEMP[6], TEMP[2] 7: MOV TEMP[7], TEMP[3] 8: F2I TEMP[8].x, IN[0].xxxx 9: ISLT TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx 10: UIF TEMP[9].xxxx :0 11: MOV TEMP[9].x, IMM[1].xxxx 12: ELSE :0 13: ISLT TEMP[10].x, IMM[1].yyyy, TEMP[8].xxxx 14: UIF TEMP[10].xxxx :0 15: MOV TEMP[10].x, IMM[1].yyyy 16: ELSE :0 17: MOV TEMP[10].x, TEMP[8].xxxx 18: ENDIF 19: MOV TEMP[9].x, TEMP[10].xxxx 20: ENDIF 21: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 22: UARL ADDR[0].x, TEMP[8].xxxx 23: UARL ADDR[0].x, TEMP[8].xxxx 24: MAD TEMP[11], CONST[ADDR[0].x+1], IN[1].xxxx, TEMP[4] 25: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 26: UARL ADDR[0].x, TEMP[8].xxxx 27: UARL ADDR[0].x, TEMP[8].xxxx 28: MAD TEMP[12], CONST[ADDR[0].x+2], IN[1].xxxx, TEMP[5] 29: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 30: UARL ADDR[0].x, TEMP[8].xxxx 31: UARL ADDR[0].x, TEMP[8].xxxx 32: MAD TEMP[13], CONST[ADDR[0].x+3], IN[1].xxxx, TEMP[6] 33: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 34: UARL ADDR[0].x, TEMP[8].xxxx 35: UARL ADDR[0].x, TEMP[8].xxxx 36: MAD TEMP[14], CONST[ADDR[0].x+4], IN[1].xxxx, TEMP[7] 37: MOV TEMP[4], TEMP[11] 38: MOV TEMP[5], TEMP[12] 39: MOV TEMP[6], TEMP[13] 40: MOV TEMP[7], TEMP[14] 41: F2I TEMP[8].x, IN[0].yyyy 42: ISLT TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx 43: UIF TEMP[9].xxxx :0 44: MOV TEMP[9].x, IMM[1].xxxx 45: ELSE :0 46: ISLT TEMP[10].x, IMM[1].yyyy, TEMP[8].xxxx 47: UIF TEMP[10].xxxx :0 48: MOV TEMP[10].x, IMM[1].yyyy 49: ELSE :0 50: MOV TEMP[10].x, TEMP[8].xxxx 51: ENDIF 52: MOV TEMP[9].x, TEMP[10].xxxx 53: ENDIF 54: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 55: UARL ADDR[0].x, TEMP[8].xxxx 56: UARL ADDR[0].x, TEMP[8].xxxx 57: MAD TEMP[15], CONST[ADDR[0].x+1], IN[1].yyyy, TEMP[11] 58: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 59: UARL ADDR[0].x, TEMP[8].xxxx 60: UARL ADDR[0].x, TEMP[8].xxxx 61: MAD TEMP[16], CONST[ADDR[0].x+2], IN[1].yyyy, TEMP[12] 62: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 63: UARL ADDR[0].x, TEMP[8].xxxx 64: UARL ADDR[0].x, TEMP[8].xxxx 65: MAD TEMP[17], CONST[ADDR[0].x+3], IN[1].yyyy, TEMP[13] 66: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 67: UARL ADDR[0].x, TEMP[8].xxxx 68: UARL ADDR[0].x, TEMP[8].xxxx 69: MAD TEMP[18], CONST[ADDR[0].x+4], IN[1].yyyy, TEMP[14] 70: MOV TEMP[4], TEMP[15] 71: MOV TEMP[5], TEMP[16] 72: MOV TEMP[6], TEMP[17] 73: MOV TEMP[7], TEMP[18] 74: F2I TEMP[8].x, IN[0].zzzz 75: ISLT TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx 76: UIF TEMP[9].xxxx :0 77: MOV TEMP[9].x, IMM[1].xxxx 78: ELSE :0 79: ISLT TEMP[10].x, IMM[1].yyyy, TEMP[8].xxxx 80: UIF TEMP[10].xxxx :0 81: MOV TEMP[10].x, IMM[1].yyyy 82: ELSE :0 83: MOV TEMP[10].x, TEMP[8].xxxx 84: ENDIF 85: MOV TEMP[9].x, TEMP[10].xxxx 86: ENDIF 87: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 88: UARL ADDR[0].x, TEMP[8].xxxx 89: UARL ADDR[0].x, TEMP[8].xxxx 90: MAD TEMP[19], CONST[ADDR[0].x+1], IN[1].zzzz, TEMP[15] 91: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 92: UARL ADDR[0].x, TEMP[8].xxxx 93: UARL ADDR[0].x, TEMP[8].xxxx 94: MAD TEMP[20], CONST[ADDR[0].x+2], IN[1].zzzz, TEMP[16] 95: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 96: UARL ADDR[0].x, TEMP[8].xxxx 97: UARL ADDR[0].x, TEMP[8].xxxx 98: MAD TEMP[21], CONST[ADDR[0].x+3], IN[1].zzzz, TEMP[17] 99: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 100: UARL ADDR[0].x, TEMP[8].xxxx 101: UARL ADDR[0].x, TEMP[8].xxxx 102: MAD TEMP[22], CONST[ADDR[0].x+4], IN[1].zzzz, TEMP[18] 103: MOV TEMP[4], TEMP[19] 104: MOV TEMP[5], TEMP[20] 105: MOV TEMP[6], TEMP[21] 106: MOV TEMP[7], TEMP[22] 107: F2I TEMP[8].x, IN[0].wwww 108: ISLT TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx 109: UIF TEMP[9].xxxx :0 110: MOV TEMP[9].x, IMM[1].xxxx 111: ELSE :0 112: ISLT TEMP[10].x, IMM[1].yyyy, TEMP[8].xxxx 113: UIF TEMP[10].xxxx :0 114: MOV TEMP[10].x, IMM[1].yyyy 115: ELSE :0 116: MOV TEMP[10].x, TEMP[8].xxxx 117: ENDIF 118: MOV TEMP[9].x, TEMP[10].xxxx 119: ENDIF 120: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 121: UARL ADDR[0].x, TEMP[8].xxxx 122: UARL ADDR[0].x, TEMP[8].xxxx 123: MAD TEMP[23], CONST[ADDR[0].x+1], IN[1].wwww, TEMP[19] 124: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 125: UARL ADDR[0].x, TEMP[8].xxxx 126: UARL ADDR[0].x, TEMP[8].xxxx 127: MAD TEMP[24], CONST[ADDR[0].x+2], IN[1].wwww, TEMP[20] 128: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 129: UARL ADDR[0].x, TEMP[8].xxxx 130: UARL ADDR[0].x, TEMP[8].xxxx 131: MAD TEMP[25], CONST[ADDR[0].x+3], IN[1].wwww, TEMP[21] 132: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 133: UARL ADDR[0].x, TEMP[8].xxxx 134: UARL ADDR[0].x, TEMP[8].xxxx 135: MAD TEMP[26], CONST[ADDR[0].x+4], IN[1].wwww, TEMP[22] 136: MOV TEMP[4], TEMP[23] 137: MOV TEMP[5], TEMP[24] 138: MOV TEMP[6], TEMP[25] 139: MOV TEMP[7], TEMP[26] 140: MUL TEMP[8], CONST[49], TEMP[25].xxxx 141: MAD TEMP[8], CONST[50], TEMP[25].yyyy, TEMP[8] 142: MAD TEMP[8], CONST[51], TEMP[25].zzzz, TEMP[8] 143: MAD TEMP[8], CONST[52], TEMP[25].wwww, TEMP[8] 144: MUL TEMP[9], CONST[49], TEMP[24].xxxx 145: MAD TEMP[9], CONST[50], TEMP[24].yyyy, TEMP[9] 146: MAD TEMP[9], CONST[51], TEMP[24].zzzz, TEMP[9] 147: MAD TEMP[9], CONST[52], TEMP[24].wwww, TEMP[9] 148: MUL TEMP[10], CONST[49], TEMP[23].xxxx 149: MAD TEMP[10], CONST[50], TEMP[23].yyyy, TEMP[10] 150: MAD TEMP[10], CONST[51], TEMP[23].zzzz, TEMP[10] 151: MAD TEMP[10], CONST[52], TEMP[23].wwww, TEMP[10] 152: MUL TEMP[10], TEMP[10], IN[4].xxxx 153: MAD TEMP[9], TEMP[9], IN[4].yyyy, TEMP[10] 154: MAD TEMP[8], TEMP[8], IN[4].zzzz, TEMP[9] 155: MUL TEMP[9], CONST[49], TEMP[26].xxxx 156: MAD TEMP[9], CONST[50], TEMP[26].yyyy, TEMP[9] 157: MAD TEMP[9], CONST[51], TEMP[26].zzzz, TEMP[9] 158: MAD TEMP[9], CONST[52], TEMP[26].wwww, TEMP[9] 159: ADD TEMP[8], TEMP[8], TEMP[9] 160: MUL TEMP[9], CONST[53], CONST[60].xxxx 161: MAD TEMP[9], CONST[54], CONST[60].yyyy, TEMP[9] 162: MAD TEMP[9], CONST[55], CONST[60].zzzz, TEMP[9] 163: MAD TEMP[9], CONST[56], CONST[60].wwww, TEMP[9] 164: MUL TEMP[10], CONST[53], CONST[59].xxxx 165: MAD TEMP[10], CONST[54], CONST[59].yyyy, TEMP[10] 166: MAD TEMP[10], CONST[55], CONST[59].zzzz, TEMP[10] 167: MAD TEMP[10], CONST[56], CONST[59].wwww, TEMP[10] 168: MUL TEMP[27], CONST[53], CONST[58].xxxx 169: MAD TEMP[27], CONST[54], CONST[58].yyyy, TEMP[27] 170: MAD TEMP[27], CONST[55], CONST[58].zzzz, TEMP[27] 171: MAD TEMP[27], CONST[56], CONST[58].wwww, TEMP[27] 172: MUL TEMP[28], CONST[53], CONST[57].xxxx 173: MAD TEMP[28], CONST[54], CONST[57].yyyy, TEMP[28] 174: MAD TEMP[28], CONST[55], CONST[57].zzzz, TEMP[28] 175: MAD TEMP[28], CONST[56], CONST[57].wwww, TEMP[28] 176: MUL TEMP[28], TEMP[28], TEMP[8].xxxx 177: MAD TEMP[27], TEMP[27], TEMP[8].yyyy, TEMP[28] 178: MAD TEMP[10], TEMP[10], TEMP[8].zzzz, TEMP[27] 179: MAD TEMP[8], TEMP[9], TEMP[8].wwww, TEMP[10] 180: MOV TEMP[9].xy, IN[2].xyxx 181: MOV TEMP[9].zw, CONST[0].yyxy 182: MOV TEMP[10].x, CONST[0].zzzz 183: MUL TEMP[27], CONST[49], TEMP[25].xxxx 184: MAD TEMP[27], CONST[50], TEMP[25].yyyy, TEMP[27] 185: MAD TEMP[27], CONST[51], TEMP[25].zzzz, TEMP[27] 186: MAD TEMP[27], CONST[52], TEMP[25].wwww, TEMP[27] 187: MUL TEMP[28], CONST[49], TEMP[24].xxxx 188: MAD TEMP[28], CONST[50], TEMP[24].yyyy, TEMP[28] 189: MAD TEMP[28], CONST[51], TEMP[24].zzzz, TEMP[28] 190: MAD TEMP[28], CONST[52], TEMP[24].wwww, TEMP[28] 191: MUL TEMP[29], CONST[49], TEMP[23].xxxx 192: MAD TEMP[29], CONST[50], TEMP[23].yyyy, TEMP[29] 193: MAD TEMP[29], CONST[51], TEMP[23].zzzz, TEMP[29] 194: MAD TEMP[29], CONST[52], TEMP[23].wwww, TEMP[29] 195: MUL TEMP[29], TEMP[29], IN[3].xxxx 196: MAD TEMP[28], TEMP[28], IN[3].yyyy, TEMP[29] 197: MAD TEMP[27].xyz, TEMP[27], IN[3].zzzz, TEMP[28] 198: MOV TEMP[10].yzw, TEMP[27].yxyz 199: MOV OUT[1], TEMP[9] 200: MOV OUT[2], TEMP[10] 201: MOV OUT[0], TEMP[8] 202: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = call float @llvm.R600.load.input(i32 12) %9 = call float @llvm.R600.load.input(i32 13) %10 = call float @llvm.R600.load.input(i32 14) %11 = call float @llvm.R600.load.input(i32 15) %12 = call float @llvm.R600.load.input(i32 16) %13 = call float @llvm.R600.load.input(i32 17) %14 = call float @llvm.R600.load.input(i32 18) %15 = call float @llvm.R600.load.input(i32 19) %16 = call float @llvm.R600.load.input(i32 20) %17 = call float @llvm.R600.load.input(i32 21) %18 = call float @llvm.R600.load.input(i32 22) %19 = call float @llvm.R600.load.input(i32 23) %20 = fptosi float %0 to i32 %21 = bitcast i32 %20 to float %22 = bitcast float %21 to i32 %23 = icmp slt i32 %22, 0 %24 = sext i1 %23 to i32 %25 = bitcast i32 %24 to float %26 = bitcast float %25 to i32 %27 = icmp ne i32 %26, 0 br i1 %27, label %ENDIF, label %ELSE ELSE: ; preds = %main_body %28 = bitcast float %21 to i32 %29 = icmp slt i32 11, %28 %30 = sext i1 %29 to i32 %31 = bitcast i32 %30 to float %32 = bitcast float %31 to i32 %33 = icmp ne i32 %32, 0 %. = select i1 %33, float 0,000000e+00, float %21 br label %ENDIF ENDIF: ; preds = %main_body, %ELSE %temp36.0 = phi float [ %., %ELSE ], [ 0,000000e+00, %main_body ] %34 = bitcast float %temp36.0 to i32 %35 = mul i32 %34, 4 %36 = bitcast i32 %35 to float %37 = bitcast float %36 to i32 %38 = add i32 1, %37 %39 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %38 %40 = load <4 x float> addrspace(8)* %39 %41 = extractelement <4 x float> %40, i32 0 %42 = fmul float %41, %4 %43 = fadd float %42, 0,000000e+00 %44 = add i32 1, %37 %45 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %44 %46 = load <4 x float> addrspace(8)* %45 %47 = extractelement <4 x float> %46, i32 1 %48 = fmul float %47, %4 %49 = fadd float %48, 0,000000e+00 %50 = add i32 1, %37 %51 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %50 %52 = load <4 x float> addrspace(8)* %51 %53 = extractelement <4 x float> %52, i32 2 %54 = fmul float %53, %4 %55 = fadd float %54, 0,000000e+00 %56 = add i32 1, %37 %57 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %56 %58 = load <4 x float> addrspace(8)* %57 %59 = extractelement <4 x float> %58, i32 3 %60 = fmul float %59, %4 %61 = fadd float %60, 0,000000e+00 %62 = bitcast float %temp36.0 to i32 %63 = mul i32 %62, 4 %64 = bitcast i32 %63 to float %65 = bitcast float %64 to i32 %66 = add i32 2, %65 %67 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %66 %68 = load <4 x float> addrspace(8)* %67 %69 = extractelement <4 x float> %68, i32 0 %70 = fmul float %69, %4 %71 = fadd float %70, 0,000000e+00 %72 = add i32 2, %65 %73 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %72 %74 = load <4 x float> addrspace(8)* %73 %75 = extractelement <4 x float> %74, i32 1 %76 = fmul float %75, %4 %77 = fadd float %76, 0,000000e+00 %78 = add i32 2, %65 %79 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %78 %80 = load <4 x float> addrspace(8)* %79 %81 = extractelement <4 x float> %80, i32 2 %82 = fmul float %81, %4 %83 = fadd float %82, 0,000000e+00 %84 = add i32 2, %65 %85 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %84 %86 = load <4 x float> addrspace(8)* %85 %87 = extractelement <4 x float> %86, i32 3 %88 = fmul float %87, %4 %89 = fadd float %88, 0,000000e+00 %90 = bitcast float %temp36.0 to i32 %91 = mul i32 %90, 4 %92 = bitcast i32 %91 to float %93 = bitcast float %92 to i32 %94 = add i32 3, %93 %95 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %94 %96 = load <4 x float> addrspace(8)* %95 %97 = extractelement <4 x float> %96, i32 0 %98 = fmul float %97, %4 %99 = fadd float %98, 0,000000e+00 %100 = add i32 3, %93 %101 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %100 %102 = load <4 x float> addrspace(8)* %101 %103 = extractelement <4 x float> %102, i32 1 %104 = fmul float %103, %4 %105 = fadd float %104, 0,000000e+00 %106 = add i32 3, %93 %107 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %106 %108 = load <4 x float> addrspace(8)* %107 %109 = extractelement <4 x float> %108, i32 2 %110 = fmul float %109, %4 %111 = fadd float %110, 0,000000e+00 %112 = add i32 3, %93 %113 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %112 %114 = load <4 x float> addrspace(8)* %113 %115 = extractelement <4 x float> %114, i32 3 %116 = fmul float %115, %4 %117 = fadd float %116, 0,000000e+00 %118 = bitcast float %temp36.0 to i32 %119 = mul i32 %118, 4 %120 = bitcast i32 %119 to float %121 = bitcast float %120 to i32 %122 = add i32 4, %121 %123 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %122 %124 = load <4 x float> addrspace(8)* %123 %125 = extractelement <4 x float> %124, i32 0 %126 = fmul float %125, %4 %127 = fadd float %126, 0,000000e+00 %128 = add i32 4, %121 %129 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %128 %130 = load <4 x float> addrspace(8)* %129 %131 = extractelement <4 x float> %130, i32 1 %132 = fmul float %131, %4 %133 = fadd float %132, 0,000000e+00 %134 = add i32 4, %121 %135 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %134 %136 = load <4 x float> addrspace(8)* %135 %137 = extractelement <4 x float> %136, i32 2 %138 = fmul float %137, %4 %139 = fadd float %138, 0,000000e+00 %140 = add i32 4, %121 %141 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %140 %142 = load <4 x float> addrspace(8)* %141 %143 = extractelement <4 x float> %142, i32 3 %144 = fmul float %143, %4 %145 = fadd float %144, 0,000000e+00 %146 = fptosi float %1 to i32 %147 = bitcast i32 %146 to float %148 = bitcast float %147 to i32 %149 = icmp slt i32 %148, 0 %150 = sext i1 %149 to i32 %151 = bitcast i32 %150 to float %152 = bitcast float %151 to i32 %153 = icmp ne i32 %152, 0 br i1 %153, label %ENDIF123, label %ELSE125 ELSE125: ; preds = %ENDIF %154 = bitcast float %147 to i32 %155 = icmp slt i32 11, %154 %156 = sext i1 %155 to i32 %157 = bitcast i32 %156 to float %158 = bitcast float %157 to i32 %159 = icmp ne i32 %158, 0 %.141 = select i1 %159, float 0,000000e+00, float %147 br label %ENDIF123 ENDIF123: ; preds = %ENDIF, %ELSE125 %temp36.1 = phi float [ %.141, %ELSE125 ], [ 0,000000e+00, %ENDIF ] %160 = bitcast float %temp36.1 to i32 %161 = mul i32 %160, 4 %162 = bitcast i32 %161 to float %163 = bitcast float %162 to i32 %164 = add i32 1, %163 %165 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %164 %166 = load <4 x float> addrspace(8)* %165 %167 = extractelement <4 x float> %166, i32 0 %168 = fmul float %167, %5 %169 = fadd float %168, %43 %170 = add i32 1, %163 %171 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %170 %172 = load <4 x float> addrspace(8)* %171 %173 = extractelement <4 x float> %172, i32 1 %174 = fmul float %173, %5 %175 = fadd float %174, %49 %176 = add i32 1, %163 %177 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %176 %178 = load <4 x float> addrspace(8)* %177 %179 = extractelement <4 x float> %178, i32 2 %180 = fmul float %179, %5 %181 = fadd float %180, %55 %182 = add i32 1, %163 %183 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %182 %184 = load <4 x float> addrspace(8)* %183 %185 = extractelement <4 x float> %184, i32 3 %186 = fmul float %185, %5 %187 = fadd float %186, %61 %188 = bitcast float %temp36.1 to i32 %189 = mul i32 %188, 4 %190 = bitcast i32 %189 to float %191 = bitcast float %190 to i32 %192 = add i32 2, %191 %193 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %192 %194 = load <4 x float> addrspace(8)* %193 %195 = extractelement <4 x float> %194, i32 0 %196 = fmul float %195, %5 %197 = fadd float %196, %71 %198 = add i32 2, %191 %199 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %198 %200 = load <4 x float> addrspace(8)* %199 %201 = extractelement <4 x float> %200, i32 1 %202 = fmul float %201, %5 %203 = fadd float %202, %77 %204 = add i32 2, %191 %205 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %204 %206 = load <4 x float> addrspace(8)* %205 %207 = extractelement <4 x float> %206, i32 2 %208 = fmul float %207, %5 %209 = fadd float %208, %83 %210 = add i32 2, %191 %211 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %210 %212 = load <4 x float> addrspace(8)* %211 %213 = extractelement <4 x float> %212, i32 3 %214 = fmul float %213, %5 %215 = fadd float %214, %89 %216 = bitcast float %temp36.1 to i32 %217 = mul i32 %216, 4 %218 = bitcast i32 %217 to float %219 = bitcast float %218 to i32 %220 = add i32 3, %219 %221 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %220 %222 = load <4 x float> addrspace(8)* %221 %223 = extractelement <4 x float> %222, i32 0 %224 = fmul float %223, %5 %225 = fadd float %224, %99 %226 = add i32 3, %219 %227 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %226 %228 = load <4 x float> addrspace(8)* %227 %229 = extractelement <4 x float> %228, i32 1 %230 = fmul float %229, %5 %231 = fadd float %230, %105 %232 = add i32 3, %219 %233 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %232 %234 = load <4 x float> addrspace(8)* %233 %235 = extractelement <4 x float> %234, i32 2 %236 = fmul float %235, %5 %237 = fadd float %236, %111 %238 = add i32 3, %219 %239 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %238 %240 = load <4 x float> addrspace(8)* %239 %241 = extractelement <4 x float> %240, i32 3 %242 = fmul float %241, %5 %243 = fadd float %242, %117 %244 = bitcast float %temp36.1 to i32 %245 = mul i32 %244, 4 %246 = bitcast i32 %245 to float %247 = bitcast float %246 to i32 %248 = add i32 4, %247 %249 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %248 %250 = load <4 x float> addrspace(8)* %249 %251 = extractelement <4 x float> %250, i32 0 %252 = fmul float %251, %5 %253 = fadd float %252, %127 %254 = add i32 4, %247 %255 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %254 %256 = load <4 x float> addrspace(8)* %255 %257 = extractelement <4 x float> %256, i32 1 %258 = fmul float %257, %5 %259 = fadd float %258, %133 %260 = add i32 4, %247 %261 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %260 %262 = load <4 x float> addrspace(8)* %261 %263 = extractelement <4 x float> %262, i32 2 %264 = fmul float %263, %5 %265 = fadd float %264, %139 %266 = add i32 4, %247 %267 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %266 %268 = load <4 x float> addrspace(8)* %267 %269 = extractelement <4 x float> %268, i32 3 %270 = fmul float %269, %5 %271 = fadd float %270, %145 %272 = fptosi float %2 to i32 %273 = bitcast i32 %272 to float %274 = bitcast float %273 to i32 %275 = icmp slt i32 %274, 0 %276 = sext i1 %275 to i32 %277 = bitcast i32 %276 to float %278 = bitcast float %277 to i32 %279 = icmp ne i32 %278, 0 br i1 %279, label %ENDIF129, label %ELSE131 ELSE131: ; preds = %ENDIF123 %280 = bitcast float %273 to i32 %281 = icmp slt i32 11, %280 %282 = sext i1 %281 to i32 %283 = bitcast i32 %282 to float %284 = bitcast float %283 to i32 %285 = icmp ne i32 %284, 0 %.142 = select i1 %285, float 0,000000e+00, float %273 br label %ENDIF129 ENDIF129: ; preds = %ENDIF123, %ELSE131 %temp36.2 = phi float [ %.142, %ELSE131 ], [ 0,000000e+00, %ENDIF123 ] %286 = bitcast float %temp36.2 to i32 %287 = mul i32 %286, 4 %288 = bitcast i32 %287 to float %289 = bitcast float %288 to i32 %290 = add i32 1, %289 %291 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %290 %292 = load <4 x float> addrspace(8)* %291 %293 = extractelement <4 x float> %292, i32 0 %294 = fmul float %293, %6 %295 = fadd float %294, %169 %296 = add i32 1, %289 %297 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %296 %298 = load <4 x float> addrspace(8)* %297 %299 = extractelement <4 x float> %298, i32 1 %300 = fmul float %299, %6 %301 = fadd float %300, %175 %302 = add i32 1, %289 %303 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %302 %304 = load <4 x float> addrspace(8)* %303 %305 = extractelement <4 x float> %304, i32 2 %306 = fmul float %305, %6 %307 = fadd float %306, %181 %308 = add i32 1, %289 %309 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %308 %310 = load <4 x float> addrspace(8)* %309 %311 = extractelement <4 x float> %310, i32 3 %312 = fmul float %311, %6 %313 = fadd float %312, %187 %314 = bitcast float %temp36.2 to i32 %315 = mul i32 %314, 4 %316 = bitcast i32 %315 to float %317 = bitcast float %316 to i32 %318 = add i32 2, %317 %319 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %318 %320 = load <4 x float> addrspace(8)* %319 %321 = extractelement <4 x float> %320, i32 0 %322 = fmul float %321, %6 %323 = fadd float %322, %197 %324 = add i32 2, %317 %325 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %324 %326 = load <4 x float> addrspace(8)* %325 %327 = extractelement <4 x float> %326, i32 1 %328 = fmul float %327, %6 %329 = fadd float %328, %203 %330 = add i32 2, %317 %331 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %330 %332 = load <4 x float> addrspace(8)* %331 %333 = extractelement <4 x float> %332, i32 2 %334 = fmul float %333, %6 %335 = fadd float %334, %209 %336 = add i32 2, %317 %337 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %336 %338 = load <4 x float> addrspace(8)* %337 %339 = extractelement <4 x float> %338, i32 3 %340 = fmul float %339, %6 %341 = fadd float %340, %215 %342 = bitcast float %temp36.2 to i32 %343 = mul i32 %342, 4 %344 = bitcast i32 %343 to float %345 = bitcast float %344 to i32 %346 = add i32 3, %345 %347 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %346 %348 = load <4 x float> addrspace(8)* %347 %349 = extractelement <4 x float> %348, i32 0 %350 = fmul float %349, %6 %351 = fadd float %350, %225 %352 = add i32 3, %345 %353 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %352 %354 = load <4 x float> addrspace(8)* %353 %355 = extractelement <4 x float> %354, i32 1 %356 = fmul float %355, %6 %357 = fadd float %356, %231 %358 = add i32 3, %345 %359 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %358 %360 = load <4 x float> addrspace(8)* %359 %361 = extractelement <4 x float> %360, i32 2 %362 = fmul float %361, %6 %363 = fadd float %362, %237 %364 = add i32 3, %345 %365 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %364 %366 = load <4 x float> addrspace(8)* %365 %367 = extractelement <4 x float> %366, i32 3 %368 = fmul float %367, %6 %369 = fadd float %368, %243 %370 = bitcast float %temp36.2 to i32 %371 = mul i32 %370, 4 %372 = bitcast i32 %371 to float %373 = bitcast float %372 to i32 %374 = add i32 4, %373 %375 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %374 %376 = load <4 x float> addrspace(8)* %375 %377 = extractelement <4 x float> %376, i32 0 %378 = fmul float %377, %6 %379 = fadd float %378, %253 %380 = add i32 4, %373 %381 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %380 %382 = load <4 x float> addrspace(8)* %381 %383 = extractelement <4 x float> %382, i32 1 %384 = fmul float %383, %6 %385 = fadd float %384, %259 %386 = add i32 4, %373 %387 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %386 %388 = load <4 x float> addrspace(8)* %387 %389 = extractelement <4 x float> %388, i32 2 %390 = fmul float %389, %6 %391 = fadd float %390, %265 %392 = add i32 4, %373 %393 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %392 %394 = load <4 x float> addrspace(8)* %393 %395 = extractelement <4 x float> %394, i32 3 %396 = fmul float %395, %6 %397 = fadd float %396, %271 %398 = fptosi float %3 to i32 %399 = bitcast i32 %398 to float %400 = bitcast float %399 to i32 %401 = icmp slt i32 %400, 0 %402 = sext i1 %401 to i32 %403 = bitcast i32 %402 to float %404 = bitcast float %403 to i32 %405 = icmp ne i32 %404, 0 br i1 %405, label %ENDIF135, label %ELSE137 ELSE137: ; preds = %ENDIF129 %406 = bitcast float %399 to i32 %407 = icmp slt i32 11, %406 %408 = sext i1 %407 to i32 %409 = bitcast i32 %408 to float %410 = bitcast float %409 to i32 %411 = icmp ne i32 %410, 0 %.143 = select i1 %411, float 0,000000e+00, float %399 br label %ENDIF135 ENDIF135: ; preds = %ENDIF129, %ELSE137 %temp36.3 = phi float [ %.143, %ELSE137 ], [ 0,000000e+00, %ENDIF129 ] %412 = bitcast float %temp36.3 to i32 %413 = mul i32 %412, 4 %414 = bitcast i32 %413 to float %415 = bitcast float %414 to i32 %416 = add i32 1, %415 %417 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %416 %418 = load <4 x float> addrspace(8)* %417 %419 = extractelement <4 x float> %418, i32 0 %420 = fmul float %419, %7 %421 = fadd float %420, %295 %422 = add i32 1, %415 %423 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %422 %424 = load <4 x float> addrspace(8)* %423 %425 = extractelement <4 x float> %424, i32 1 %426 = fmul float %425, %7 %427 = fadd float %426, %301 %428 = add i32 1, %415 %429 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %428 %430 = load <4 x float> addrspace(8)* %429 %431 = extractelement <4 x float> %430, i32 2 %432 = fmul float %431, %7 %433 = fadd float %432, %307 %434 = add i32 1, %415 %435 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %434 %436 = load <4 x float> addrspace(8)* %435 %437 = extractelement <4 x float> %436, i32 3 %438 = fmul float %437, %7 %439 = fadd float %438, %313 %440 = bitcast float %temp36.3 to i32 %441 = mul i32 %440, 4 %442 = bitcast i32 %441 to float %443 = bitcast float %442 to i32 %444 = add i32 2, %443 %445 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %444 %446 = load <4 x float> addrspace(8)* %445 %447 = extractelement <4 x float> %446, i32 0 %448 = fmul float %447, %7 %449 = fadd float %448, %323 %450 = add i32 2, %443 %451 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %450 %452 = load <4 x float> addrspace(8)* %451 %453 = extractelement <4 x float> %452, i32 1 %454 = fmul float %453, %7 %455 = fadd float %454, %329 %456 = add i32 2, %443 %457 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %456 %458 = load <4 x float> addrspace(8)* %457 %459 = extractelement <4 x float> %458, i32 2 %460 = fmul float %459, %7 %461 = fadd float %460, %335 %462 = add i32 2, %443 %463 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %462 %464 = load <4 x float> addrspace(8)* %463 %465 = extractelement <4 x float> %464, i32 3 %466 = fmul float %465, %7 %467 = fadd float %466, %341 %468 = bitcast float %temp36.3 to i32 %469 = mul i32 %468, 4 %470 = bitcast i32 %469 to float %471 = bitcast float %470 to i32 %472 = add i32 3, %471 %473 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %472 %474 = load <4 x float> addrspace(8)* %473 %475 = extractelement <4 x float> %474, i32 0 %476 = fmul float %475, %7 %477 = fadd float %476, %351 %478 = add i32 3, %471 %479 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %478 %480 = load <4 x float> addrspace(8)* %479 %481 = extractelement <4 x float> %480, i32 1 %482 = fmul float %481, %7 %483 = fadd float %482, %357 %484 = add i32 3, %471 %485 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %484 %486 = load <4 x float> addrspace(8)* %485 %487 = extractelement <4 x float> %486, i32 2 %488 = fmul float %487, %7 %489 = fadd float %488, %363 %490 = add i32 3, %471 %491 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %490 %492 = load <4 x float> addrspace(8)* %491 %493 = extractelement <4 x float> %492, i32 3 %494 = fmul float %493, %7 %495 = fadd float %494, %369 %496 = bitcast float %temp36.3 to i32 %497 = mul i32 %496, 4 %498 = bitcast i32 %497 to float %499 = bitcast float %498 to i32 %500 = add i32 4, %499 %501 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %500 %502 = load <4 x float> addrspace(8)* %501 %503 = extractelement <4 x float> %502, i32 0 %504 = fmul float %503, %7 %505 = fadd float %504, %379 %506 = add i32 4, %499 %507 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %506 %508 = load <4 x float> addrspace(8)* %507 %509 = extractelement <4 x float> %508, i32 1 %510 = fmul float %509, %7 %511 = fadd float %510, %385 %512 = add i32 4, %499 %513 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %512 %514 = load <4 x float> addrspace(8)* %513 %515 = extractelement <4 x float> %514, i32 2 %516 = fmul float %515, %7 %517 = fadd float %516, %391 %518 = add i32 4, %499 %519 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %518 %520 = load <4 x float> addrspace(8)* %519 %521 = extractelement <4 x float> %520, i32 3 %522 = fmul float %521, %7 %523 = fadd float %522, %397 %524 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %525 = extractelement <4 x float> %524, i32 0 %526 = fmul float %525, %477 %527 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %528 = extractelement <4 x float> %527, i32 1 %529 = fmul float %528, %477 %530 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %531 = extractelement <4 x float> %530, i32 2 %532 = fmul float %531, %477 %533 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %534 = extractelement <4 x float> %533, i32 3 %535 = fmul float %534, %477 %536 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %537 = extractelement <4 x float> %536, i32 0 %538 = fmul float %537, %483 %539 = fadd float %538, %526 %540 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %541 = extractelement <4 x float> %540, i32 1 %542 = fmul float %541, %483 %543 = fadd float %542, %529 %544 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %545 = extractelement <4 x float> %544, i32 2 %546 = fmul float %545, %483 %547 = fadd float %546, %532 %548 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %549 = extractelement <4 x float> %548, i32 3 %550 = fmul float %549, %483 %551 = fadd float %550, %535 %552 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %553 = extractelement <4 x float> %552, i32 0 %554 = fmul float %553, %489 %555 = fadd float %554, %539 %556 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %557 = extractelement <4 x float> %556, i32 1 %558 = fmul float %557, %489 %559 = fadd float %558, %543 %560 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %561 = extractelement <4 x float> %560, i32 2 %562 = fmul float %561, %489 %563 = fadd float %562, %547 %564 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %565 = extractelement <4 x float> %564, i32 3 %566 = fmul float %565, %489 %567 = fadd float %566, %551 %568 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %569 = extractelement <4 x float> %568, i32 0 %570 = fmul float %569, %495 %571 = fadd float %570, %555 %572 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %573 = extractelement <4 x float> %572, i32 1 %574 = fmul float %573, %495 %575 = fadd float %574, %559 %576 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %577 = extractelement <4 x float> %576, i32 2 %578 = fmul float %577, %495 %579 = fadd float %578, %563 %580 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %581 = extractelement <4 x float> %580, i32 3 %582 = fmul float %581, %495 %583 = fadd float %582, %567 %584 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %585 = extractelement <4 x float> %584, i32 0 %586 = fmul float %585, %449 %587 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %588 = extractelement <4 x float> %587, i32 1 %589 = fmul float %588, %449 %590 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %591 = extractelement <4 x float> %590, i32 2 %592 = fmul float %591, %449 %593 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %594 = extractelement <4 x float> %593, i32 3 %595 = fmul float %594, %449 %596 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %597 = extractelement <4 x float> %596, i32 0 %598 = fmul float %597, %455 %599 = fadd float %598, %586 %600 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %601 = extractelement <4 x float> %600, i32 1 %602 = fmul float %601, %455 %603 = fadd float %602, %589 %604 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %605 = extractelement <4 x float> %604, i32 2 %606 = fmul float %605, %455 %607 = fadd float %606, %592 %608 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %609 = extractelement <4 x float> %608, i32 3 %610 = fmul float %609, %455 %611 = fadd float %610, %595 %612 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %613 = extractelement <4 x float> %612, i32 0 %614 = fmul float %613, %461 %615 = fadd float %614, %599 %616 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %617 = extractelement <4 x float> %616, i32 1 %618 = fmul float %617, %461 %619 = fadd float %618, %603 %620 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %621 = extractelement <4 x float> %620, i32 2 %622 = fmul float %621, %461 %623 = fadd float %622, %607 %624 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %625 = extractelement <4 x float> %624, i32 3 %626 = fmul float %625, %461 %627 = fadd float %626, %611 %628 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %629 = extractelement <4 x float> %628, i32 0 %630 = fmul float %629, %467 %631 = fadd float %630, %615 %632 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %633 = extractelement <4 x float> %632, i32 1 %634 = fmul float %633, %467 %635 = fadd float %634, %619 %636 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %637 = extractelement <4 x float> %636, i32 2 %638 = fmul float %637, %467 %639 = fadd float %638, %623 %640 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %641 = extractelement <4 x float> %640, i32 3 %642 = fmul float %641, %467 %643 = fadd float %642, %627 %644 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %645 = extractelement <4 x float> %644, i32 0 %646 = fmul float %645, %421 %647 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %648 = extractelement <4 x float> %647, i32 1 %649 = fmul float %648, %421 %650 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %651 = extractelement <4 x float> %650, i32 2 %652 = fmul float %651, %421 %653 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %654 = extractelement <4 x float> %653, i32 3 %655 = fmul float %654, %421 %656 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %657 = extractelement <4 x float> %656, i32 0 %658 = fmul float %657, %427 %659 = fadd float %658, %646 %660 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %661 = extractelement <4 x float> %660, i32 1 %662 = fmul float %661, %427 %663 = fadd float %662, %649 %664 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %665 = extractelement <4 x float> %664, i32 2 %666 = fmul float %665, %427 %667 = fadd float %666, %652 %668 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %669 = extractelement <4 x float> %668, i32 3 %670 = fmul float %669, %427 %671 = fadd float %670, %655 %672 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %673 = extractelement <4 x float> %672, i32 0 %674 = fmul float %673, %433 %675 = fadd float %674, %659 %676 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %677 = extractelement <4 x float> %676, i32 1 %678 = fmul float %677, %433 %679 = fadd float %678, %663 %680 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %681 = extractelement <4 x float> %680, i32 2 %682 = fmul float %681, %433 %683 = fadd float %682, %667 %684 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %685 = extractelement <4 x float> %684, i32 3 %686 = fmul float %685, %433 %687 = fadd float %686, %671 %688 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %689 = extractelement <4 x float> %688, i32 0 %690 = fmul float %689, %439 %691 = fadd float %690, %675 %692 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %693 = extractelement <4 x float> %692, i32 1 %694 = fmul float %693, %439 %695 = fadd float %694, %679 %696 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %697 = extractelement <4 x float> %696, i32 2 %698 = fmul float %697, %439 %699 = fadd float %698, %683 %700 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %701 = extractelement <4 x float> %700, i32 3 %702 = fmul float %701, %439 %703 = fadd float %702, %687 %704 = fmul float %691, %16 %705 = fmul float %695, %16 %706 = fmul float %699, %16 %707 = fmul float %703, %16 %708 = fmul float %631, %17 %709 = fadd float %708, %704 %710 = fmul float %635, %17 %711 = fadd float %710, %705 %712 = fmul float %639, %17 %713 = fadd float %712, %706 %714 = fmul float %643, %17 %715 = fadd float %714, %707 %716 = fmul float %571, %18 %717 = fadd float %716, %709 %718 = fmul float %575, %18 %719 = fadd float %718, %711 %720 = fmul float %579, %18 %721 = fadd float %720, %713 %722 = fmul float %583, %18 %723 = fadd float %722, %715 %724 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %725 = extractelement <4 x float> %724, i32 0 %726 = fmul float %725, %505 %727 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %728 = extractelement <4 x float> %727, i32 1 %729 = fmul float %728, %505 %730 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %731 = extractelement <4 x float> %730, i32 2 %732 = fmul float %731, %505 %733 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %734 = extractelement <4 x float> %733, i32 3 %735 = fmul float %734, %505 %736 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %737 = extractelement <4 x float> %736, i32 0 %738 = fmul float %737, %511 %739 = fadd float %738, %726 %740 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %741 = extractelement <4 x float> %740, i32 1 %742 = fmul float %741, %511 %743 = fadd float %742, %729 %744 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %745 = extractelement <4 x float> %744, i32 2 %746 = fmul float %745, %511 %747 = fadd float %746, %732 %748 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %749 = extractelement <4 x float> %748, i32 3 %750 = fmul float %749, %511 %751 = fadd float %750, %735 %752 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %753 = extractelement <4 x float> %752, i32 0 %754 = fmul float %753, %517 %755 = fadd float %754, %739 %756 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %757 = extractelement <4 x float> %756, i32 1 %758 = fmul float %757, %517 %759 = fadd float %758, %743 %760 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %761 = extractelement <4 x float> %760, i32 2 %762 = fmul float %761, %517 %763 = fadd float %762, %747 %764 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %765 = extractelement <4 x float> %764, i32 3 %766 = fmul float %765, %517 %767 = fadd float %766, %751 %768 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %769 = extractelement <4 x float> %768, i32 0 %770 = fmul float %769, %523 %771 = fadd float %770, %755 %772 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %773 = extractelement <4 x float> %772, i32 1 %774 = fmul float %773, %523 %775 = fadd float %774, %759 %776 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %777 = extractelement <4 x float> %776, i32 2 %778 = fmul float %777, %523 %779 = fadd float %778, %763 %780 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %781 = extractelement <4 x float> %780, i32 3 %782 = fmul float %781, %523 %783 = fadd float %782, %767 %784 = fadd float %717, %771 %785 = fadd float %719, %775 %786 = fadd float %721, %779 %787 = fadd float %723, %783 %788 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %789 = extractelement <4 x float> %788, i32 0 %790 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %791 = extractelement <4 x float> %790, i32 0 %792 = fmul float %789, %791 %793 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %794 = extractelement <4 x float> %793, i32 1 %795 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %796 = extractelement <4 x float> %795, i32 0 %797 = fmul float %794, %796 %798 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %799 = extractelement <4 x float> %798, i32 2 %800 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %801 = extractelement <4 x float> %800, i32 0 %802 = fmul float %799, %801 %803 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %804 = extractelement <4 x float> %803, i32 3 %805 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %806 = extractelement <4 x float> %805, i32 0 %807 = fmul float %804, %806 %808 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %809 = extractelement <4 x float> %808, i32 0 %810 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %811 = extractelement <4 x float> %810, i32 1 %812 = fmul float %809, %811 %813 = fadd float %812, %792 %814 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %815 = extractelement <4 x float> %814, i32 1 %816 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %817 = extractelement <4 x float> %816, i32 1 %818 = fmul float %815, %817 %819 = fadd float %818, %797 %820 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %821 = extractelement <4 x float> %820, i32 2 %822 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %823 = extractelement <4 x float> %822, i32 1 %824 = fmul float %821, %823 %825 = fadd float %824, %802 %826 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %827 = extractelement <4 x float> %826, i32 3 %828 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %829 = extractelement <4 x float> %828, i32 1 %830 = fmul float %827, %829 %831 = fadd float %830, %807 %832 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %833 = extractelement <4 x float> %832, i32 0 %834 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %835 = extractelement <4 x float> %834, i32 2 %836 = fmul float %833, %835 %837 = fadd float %836, %813 %838 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %839 = extractelement <4 x float> %838, i32 1 %840 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %841 = extractelement <4 x float> %840, i32 2 %842 = fmul float %839, %841 %843 = fadd float %842, %819 %844 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %845 = extractelement <4 x float> %844, i32 2 %846 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %847 = extractelement <4 x float> %846, i32 2 %848 = fmul float %845, %847 %849 = fadd float %848, %825 %850 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %851 = extractelement <4 x float> %850, i32 3 %852 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %853 = extractelement <4 x float> %852, i32 2 %854 = fmul float %851, %853 %855 = fadd float %854, %831 %856 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %857 = extractelement <4 x float> %856, i32 0 %858 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %859 = extractelement <4 x float> %858, i32 3 %860 = fmul float %857, %859 %861 = fadd float %860, %837 %862 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %863 = extractelement <4 x float> %862, i32 1 %864 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %865 = extractelement <4 x float> %864, i32 3 %866 = fmul float %863, %865 %867 = fadd float %866, %843 %868 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %869 = extractelement <4 x float> %868, i32 2 %870 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %871 = extractelement <4 x float> %870, i32 3 %872 = fmul float %869, %871 %873 = fadd float %872, %849 %874 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %875 = extractelement <4 x float> %874, i32 3 %876 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 60) %877 = extractelement <4 x float> %876, i32 3 %878 = fmul float %875, %877 %879 = fadd float %878, %855 %880 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %881 = extractelement <4 x float> %880, i32 0 %882 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %883 = extractelement <4 x float> %882, i32 0 %884 = fmul float %881, %883 %885 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %886 = extractelement <4 x float> %885, i32 1 %887 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %888 = extractelement <4 x float> %887, i32 0 %889 = fmul float %886, %888 %890 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %891 = extractelement <4 x float> %890, i32 2 %892 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %893 = extractelement <4 x float> %892, i32 0 %894 = fmul float %891, %893 %895 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %896 = extractelement <4 x float> %895, i32 3 %897 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %898 = extractelement <4 x float> %897, i32 0 %899 = fmul float %896, %898 %900 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %901 = extractelement <4 x float> %900, i32 0 %902 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %903 = extractelement <4 x float> %902, i32 1 %904 = fmul float %901, %903 %905 = fadd float %904, %884 %906 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %907 = extractelement <4 x float> %906, i32 1 %908 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %909 = extractelement <4 x float> %908, i32 1 %910 = fmul float %907, %909 %911 = fadd float %910, %889 %912 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %913 = extractelement <4 x float> %912, i32 2 %914 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %915 = extractelement <4 x float> %914, i32 1 %916 = fmul float %913, %915 %917 = fadd float %916, %894 %918 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %919 = extractelement <4 x float> %918, i32 3 %920 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %921 = extractelement <4 x float> %920, i32 1 %922 = fmul float %919, %921 %923 = fadd float %922, %899 %924 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %925 = extractelement <4 x float> %924, i32 0 %926 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %927 = extractelement <4 x float> %926, i32 2 %928 = fmul float %925, %927 %929 = fadd float %928, %905 %930 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %931 = extractelement <4 x float> %930, i32 1 %932 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %933 = extractelement <4 x float> %932, i32 2 %934 = fmul float %931, %933 %935 = fadd float %934, %911 %936 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %937 = extractelement <4 x float> %936, i32 2 %938 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %939 = extractelement <4 x float> %938, i32 2 %940 = fmul float %937, %939 %941 = fadd float %940, %917 %942 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %943 = extractelement <4 x float> %942, i32 3 %944 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %945 = extractelement <4 x float> %944, i32 2 %946 = fmul float %943, %945 %947 = fadd float %946, %923 %948 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %949 = extractelement <4 x float> %948, i32 0 %950 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %951 = extractelement <4 x float> %950, i32 3 %952 = fmul float %949, %951 %953 = fadd float %952, %929 %954 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %955 = extractelement <4 x float> %954, i32 1 %956 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %957 = extractelement <4 x float> %956, i32 3 %958 = fmul float %955, %957 %959 = fadd float %958, %935 %960 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %961 = extractelement <4 x float> %960, i32 2 %962 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %963 = extractelement <4 x float> %962, i32 3 %964 = fmul float %961, %963 %965 = fadd float %964, %941 %966 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %967 = extractelement <4 x float> %966, i32 3 %968 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 59) %969 = extractelement <4 x float> %968, i32 3 %970 = fmul float %967, %969 %971 = fadd float %970, %947 %972 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %973 = extractelement <4 x float> %972, i32 0 %974 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %975 = extractelement <4 x float> %974, i32 0 %976 = fmul float %973, %975 %977 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %978 = extractelement <4 x float> %977, i32 1 %979 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %980 = extractelement <4 x float> %979, i32 0 %981 = fmul float %978, %980 %982 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %983 = extractelement <4 x float> %982, i32 2 %984 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %985 = extractelement <4 x float> %984, i32 0 %986 = fmul float %983, %985 %987 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %988 = extractelement <4 x float> %987, i32 3 %989 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %990 = extractelement <4 x float> %989, i32 0 %991 = fmul float %988, %990 %992 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %993 = extractelement <4 x float> %992, i32 0 %994 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %995 = extractelement <4 x float> %994, i32 1 %996 = fmul float %993, %995 %997 = fadd float %996, %976 %998 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %999 = extractelement <4 x float> %998, i32 1 %1000 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %1001 = extractelement <4 x float> %1000, i32 1 %1002 = fmul float %999, %1001 %1003 = fadd float %1002, %981 %1004 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %1005 = extractelement <4 x float> %1004, i32 2 %1006 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %1007 = extractelement <4 x float> %1006, i32 1 %1008 = fmul float %1005, %1007 %1009 = fadd float %1008, %986 %1010 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %1011 = extractelement <4 x float> %1010, i32 3 %1012 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %1013 = extractelement <4 x float> %1012, i32 1 %1014 = fmul float %1011, %1013 %1015 = fadd float %1014, %991 %1016 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %1017 = extractelement <4 x float> %1016, i32 0 %1018 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %1019 = extractelement <4 x float> %1018, i32 2 %1020 = fmul float %1017, %1019 %1021 = fadd float %1020, %997 %1022 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %1023 = extractelement <4 x float> %1022, i32 1 %1024 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %1025 = extractelement <4 x float> %1024, i32 2 %1026 = fmul float %1023, %1025 %1027 = fadd float %1026, %1003 %1028 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %1029 = extractelement <4 x float> %1028, i32 2 %1030 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %1031 = extractelement <4 x float> %1030, i32 2 %1032 = fmul float %1029, %1031 %1033 = fadd float %1032, %1009 %1034 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %1035 = extractelement <4 x float> %1034, i32 3 %1036 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %1037 = extractelement <4 x float> %1036, i32 2 %1038 = fmul float %1035, %1037 %1039 = fadd float %1038, %1015 %1040 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %1041 = extractelement <4 x float> %1040, i32 0 %1042 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %1043 = extractelement <4 x float> %1042, i32 3 %1044 = fmul float %1041, %1043 %1045 = fadd float %1044, %1021 %1046 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %1047 = extractelement <4 x float> %1046, i32 1 %1048 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %1049 = extractelement <4 x float> %1048, i32 3 %1050 = fmul float %1047, %1049 %1051 = fadd float %1050, %1027 %1052 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %1053 = extractelement <4 x float> %1052, i32 2 %1054 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %1055 = extractelement <4 x float> %1054, i32 3 %1056 = fmul float %1053, %1055 %1057 = fadd float %1056, %1033 %1058 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %1059 = extractelement <4 x float> %1058, i32 3 %1060 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 58) %1061 = extractelement <4 x float> %1060, i32 3 %1062 = fmul float %1059, %1061 %1063 = fadd float %1062, %1039 %1064 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %1065 = extractelement <4 x float> %1064, i32 0 %1066 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1067 = extractelement <4 x float> %1066, i32 0 %1068 = fmul float %1065, %1067 %1069 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %1070 = extractelement <4 x float> %1069, i32 1 %1071 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1072 = extractelement <4 x float> %1071, i32 0 %1073 = fmul float %1070, %1072 %1074 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %1075 = extractelement <4 x float> %1074, i32 2 %1076 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1077 = extractelement <4 x float> %1076, i32 0 %1078 = fmul float %1075, %1077 %1079 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 53) %1080 = extractelement <4 x float> %1079, i32 3 %1081 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1082 = extractelement <4 x float> %1081, i32 0 %1083 = fmul float %1080, %1082 %1084 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %1085 = extractelement <4 x float> %1084, i32 0 %1086 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1087 = extractelement <4 x float> %1086, i32 1 %1088 = fmul float %1085, %1087 %1089 = fadd float %1088, %1068 %1090 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %1091 = extractelement <4 x float> %1090, i32 1 %1092 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1093 = extractelement <4 x float> %1092, i32 1 %1094 = fmul float %1091, %1093 %1095 = fadd float %1094, %1073 %1096 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %1097 = extractelement <4 x float> %1096, i32 2 %1098 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1099 = extractelement <4 x float> %1098, i32 1 %1100 = fmul float %1097, %1099 %1101 = fadd float %1100, %1078 %1102 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 54) %1103 = extractelement <4 x float> %1102, i32 3 %1104 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1105 = extractelement <4 x float> %1104, i32 1 %1106 = fmul float %1103, %1105 %1107 = fadd float %1106, %1083 %1108 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %1109 = extractelement <4 x float> %1108, i32 0 %1110 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1111 = extractelement <4 x float> %1110, i32 2 %1112 = fmul float %1109, %1111 %1113 = fadd float %1112, %1089 %1114 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %1115 = extractelement <4 x float> %1114, i32 1 %1116 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1117 = extractelement <4 x float> %1116, i32 2 %1118 = fmul float %1115, %1117 %1119 = fadd float %1118, %1095 %1120 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %1121 = extractelement <4 x float> %1120, i32 2 %1122 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1123 = extractelement <4 x float> %1122, i32 2 %1124 = fmul float %1121, %1123 %1125 = fadd float %1124, %1101 %1126 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 55) %1127 = extractelement <4 x float> %1126, i32 3 %1128 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1129 = extractelement <4 x float> %1128, i32 2 %1130 = fmul float %1127, %1129 %1131 = fadd float %1130, %1107 %1132 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %1133 = extractelement <4 x float> %1132, i32 0 %1134 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1135 = extractelement <4 x float> %1134, i32 3 %1136 = fmul float %1133, %1135 %1137 = fadd float %1136, %1113 %1138 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %1139 = extractelement <4 x float> %1138, i32 1 %1140 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1141 = extractelement <4 x float> %1140, i32 3 %1142 = fmul float %1139, %1141 %1143 = fadd float %1142, %1119 %1144 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %1145 = extractelement <4 x float> %1144, i32 2 %1146 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1147 = extractelement <4 x float> %1146, i32 3 %1148 = fmul float %1145, %1147 %1149 = fadd float %1148, %1125 %1150 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 56) %1151 = extractelement <4 x float> %1150, i32 3 %1152 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 57) %1153 = extractelement <4 x float> %1152, i32 3 %1154 = fmul float %1151, %1153 %1155 = fadd float %1154, %1131 %1156 = fmul float %1137, %784 %1157 = fmul float %1143, %784 %1158 = fmul float %1149, %784 %1159 = fmul float %1155, %784 %1160 = fmul float %1045, %785 %1161 = fadd float %1160, %1156 %1162 = fmul float %1051, %785 %1163 = fadd float %1162, %1157 %1164 = fmul float %1057, %785 %1165 = fadd float %1164, %1158 %1166 = fmul float %1063, %785 %1167 = fadd float %1166, %1159 %1168 = fmul float %953, %786 %1169 = fadd float %1168, %1161 %1170 = fmul float %959, %786 %1171 = fadd float %1170, %1163 %1172 = fmul float %965, %786 %1173 = fadd float %1172, %1165 %1174 = fmul float %971, %786 %1175 = fadd float %1174, %1167 %1176 = fmul float %861, %787 %1177 = fadd float %1176, %1169 %1178 = fmul float %867, %787 %1179 = fadd float %1178, %1171 %1180 = fmul float %873, %787 %1181 = fadd float %1180, %1173 %1182 = fmul float %879, %787 %1183 = fadd float %1182, %1175 %1184 = load <4 x float> addrspace(8)* null %1185 = extractelement <4 x float> %1184, i32 0 %1186 = load <4 x float> addrspace(8)* null %1187 = extractelement <4 x float> %1186, i32 1 %1188 = load <4 x float> addrspace(8)* null %1189 = extractelement <4 x float> %1188, i32 2 %1190 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %1191 = extractelement <4 x float> %1190, i32 0 %1192 = fmul float %1191, %477 %1193 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %1194 = extractelement <4 x float> %1193, i32 1 %1195 = fmul float %1194, %477 %1196 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %1197 = extractelement <4 x float> %1196, i32 2 %1198 = fmul float %1197, %477 %1199 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %1200 = extractelement <4 x float> %1199, i32 0 %1201 = fmul float %1200, %483 %1202 = fadd float %1201, %1192 %1203 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %1204 = extractelement <4 x float> %1203, i32 1 %1205 = fmul float %1204, %483 %1206 = fadd float %1205, %1195 %1207 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %1208 = extractelement <4 x float> %1207, i32 2 %1209 = fmul float %1208, %483 %1210 = fadd float %1209, %1198 %1211 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %1212 = extractelement <4 x float> %1211, i32 0 %1213 = fmul float %1212, %489 %1214 = fadd float %1213, %1202 %1215 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %1216 = extractelement <4 x float> %1215, i32 1 %1217 = fmul float %1216, %489 %1218 = fadd float %1217, %1206 %1219 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %1220 = extractelement <4 x float> %1219, i32 2 %1221 = fmul float %1220, %489 %1222 = fadd float %1221, %1210 %1223 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %1224 = extractelement <4 x float> %1223, i32 0 %1225 = fmul float %1224, %495 %1226 = fadd float %1225, %1214 %1227 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %1228 = extractelement <4 x float> %1227, i32 1 %1229 = fmul float %1228, %495 %1230 = fadd float %1229, %1218 %1231 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %1232 = extractelement <4 x float> %1231, i32 2 %1233 = fmul float %1232, %495 %1234 = fadd float %1233, %1222 %1235 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %1236 = extractelement <4 x float> %1235, i32 0 %1237 = fmul float %1236, %449 %1238 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %1239 = extractelement <4 x float> %1238, i32 1 %1240 = fmul float %1239, %449 %1241 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %1242 = extractelement <4 x float> %1241, i32 2 %1243 = fmul float %1242, %449 %1244 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %1245 = extractelement <4 x float> %1244, i32 0 %1246 = fmul float %1245, %455 %1247 = fadd float %1246, %1237 %1248 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %1249 = extractelement <4 x float> %1248, i32 1 %1250 = fmul float %1249, %455 %1251 = fadd float %1250, %1240 %1252 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %1253 = extractelement <4 x float> %1252, i32 2 %1254 = fmul float %1253, %455 %1255 = fadd float %1254, %1243 %1256 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %1257 = extractelement <4 x float> %1256, i32 0 %1258 = fmul float %1257, %461 %1259 = fadd float %1258, %1247 %1260 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %1261 = extractelement <4 x float> %1260, i32 1 %1262 = fmul float %1261, %461 %1263 = fadd float %1262, %1251 %1264 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %1265 = extractelement <4 x float> %1264, i32 2 %1266 = fmul float %1265, %461 %1267 = fadd float %1266, %1255 %1268 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %1269 = extractelement <4 x float> %1268, i32 0 %1270 = fmul float %1269, %467 %1271 = fadd float %1270, %1259 %1272 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %1273 = extractelement <4 x float> %1272, i32 1 %1274 = fmul float %1273, %467 %1275 = fadd float %1274, %1263 %1276 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %1277 = extractelement <4 x float> %1276, i32 2 %1278 = fmul float %1277, %467 %1279 = fadd float %1278, %1267 %1280 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %1281 = extractelement <4 x float> %1280, i32 0 %1282 = fmul float %1281, %421 %1283 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %1284 = extractelement <4 x float> %1283, i32 1 %1285 = fmul float %1284, %421 %1286 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 49) %1287 = extractelement <4 x float> %1286, i32 2 %1288 = fmul float %1287, %421 %1289 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %1290 = extractelement <4 x float> %1289, i32 0 %1291 = fmul float %1290, %427 %1292 = fadd float %1291, %1282 %1293 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %1294 = extractelement <4 x float> %1293, i32 1 %1295 = fmul float %1294, %427 %1296 = fadd float %1295, %1285 %1297 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 50) %1298 = extractelement <4 x float> %1297, i32 2 %1299 = fmul float %1298, %427 %1300 = fadd float %1299, %1288 %1301 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %1302 = extractelement <4 x float> %1301, i32 0 %1303 = fmul float %1302, %433 %1304 = fadd float %1303, %1292 %1305 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %1306 = extractelement <4 x float> %1305, i32 1 %1307 = fmul float %1306, %433 %1308 = fadd float %1307, %1296 %1309 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 51) %1310 = extractelement <4 x float> %1309, i32 2 %1311 = fmul float %1310, %433 %1312 = fadd float %1311, %1300 %1313 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %1314 = extractelement <4 x float> %1313, i32 0 %1315 = fmul float %1314, %439 %1316 = fadd float %1315, %1304 %1317 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %1318 = extractelement <4 x float> %1317, i32 1 %1319 = fmul float %1318, %439 %1320 = fadd float %1319, %1308 %1321 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 52) %1322 = extractelement <4 x float> %1321, i32 2 %1323 = fmul float %1322, %439 %1324 = fadd float %1323, %1312 %1325 = fmul float %1316, %12 %1326 = fmul float %1320, %12 %1327 = fmul float %1324, %12 %1328 = fmul float %1271, %13 %1329 = fadd float %1328, %1325 %1330 = fmul float %1275, %13 %1331 = fadd float %1330, %1326 %1332 = fmul float %1279, %13 %1333 = fadd float %1332, %1327 %1334 = fmul float %1226, %14 %1335 = fadd float %1334, %1329 %1336 = fmul float %1230, %14 %1337 = fadd float %1336, %1331 %1338 = fmul float %1234, %14 %1339 = fadd float %1338, %1333 %1340 = insertelement <4 x float> undef, float %1177, i32 0 %1341 = insertelement <4 x float> %1340, float %1179, i32 1 %1342 = insertelement <4 x float> %1341, float %1181, i32 2 %1343 = insertelement <4 x float> %1342, float %1183, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %1343, i32 60, i32 1) %1344 = insertelement <4 x float> undef, float %8, i32 0 %1345 = insertelement <4 x float> %1344, float %9, i32 1 %1346 = insertelement <4 x float> %1345, float %1185, i32 2 %1347 = insertelement <4 x float> %1346, float %1187, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %1347, i32 0, i32 2) %1348 = insertelement <4 x float> undef, float %1189, i32 0 %1349 = insertelement <4 x float> %1348, float %1335, i32 1 %1350 = insertelement <4 x float> %1349, float %1337, i32 2 %1351 = insertelement <4 x float> %1350, float %1339, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %1351, i32 1, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #53 =========================================== VS/RS880/R600 ===== ===== 750 dw ===== 22 gprs ===== 1 stack ======================================= 0000 00000000 89800000 CALL_FS @0 0002 00000030 a05c0000 ALU 24 @96 0096 00000003 40001910 1 z: MOV R0.z, R3.x 0098 80000403 60001910 w: MOV R0.w, R3.y 0100 800000f8 60601910 2 w: MOV R3.w, 0 0102 80000001 60806b10 3 t: FLT_TO_INT R4.w, R1.x 0104 801fac04 60a07010 4 t: ASHR_INT R5.w, R4.w, [0x0000001f 0].x 0106 0000001f 0108 801f0cfe 60a03d10 5 w: SETNE_INT R5.w, PV.w, 0 0110 801f0cfe 00004508 6 P x: PRED_SETNE_INT __.x, PV.w, 0 0112 c01fac04 60603b10 7 0 w: SETGT_INT R3.w, R4.w, [0x0000000b 0].x 0114 0000000b 0116 c1808c03 606380fd 8 0 w: CNDE_INT R3.w, R3.w, R4.w, [0x0000000b 0].x 0118 0000000b 0120 801fac03 60607210 9 t: LSHL_INT R3.w, R3.w, [0x00000006 0].x 0122 00000006 0124 801facfe 60803410 10 w: ADD_INT R4.w, PV.w, [0x00000040 0].x 0126 00000040 0128 001facfe 00207110 11 x: ADD __.x, R4.x, R0.x 0130 801fac03 60607110 t: OR_INT R3.x, PV.w, [0x00000003 0].x 0132 00000004 0134 801facfe 00603110 12 x: OR_INT R6.x, R3.w, [0x00000002 0].x 0136 00000003 0138 801fac03 00c03110 13 x: OR_INT R7.x, R3.w, 1 0140 00000002 00000000 14 w: MOV R5.w, 0 0004 00000010 80800c00 TEX 4 @32 0032 40070040 e8cd1009 00080000 VFETCH R9.xyzw, R7.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0036 40060040 e8cd100a 00080000 VFETCH R10.xyzw, R6.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0040 40030040 e8cd1007 00080000 VFETCH R7.xyzw, R3.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0044 40010040 e8cd100b 00080000 VFETCH R11.xyzw, R1.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0006 00000048 a0940000 ALU 38 @144 0144 800000f8 60a01910 15 w: MOV R5.w, 0 0146 0000440b 206280f8 16 y: MULADD_IEEE R3.y, R11.y, R2.x, 0 0148 0000400b 40c280f8 z: MULADD_IEEE R6.z, R11.x, R2.x, 0 0150 80004c07 606280f8 w: MULADD_IEEE R3.w, R7.w, R2.x, 0 0152 00004807 002280f8 17 x: MULADD_IEEE R1.x, R7.z, R2.x, 0 0154 00004407 210280f8 y: MULADD_IEEE R8.y, R7.y, R2.x, 0 0156 00004007 410280f8 z: MULADD_IEEE R8.z, R7.x, R2.x, 0 0158 80004c0a 608280f8 w: MULADD_IEEE R4.w, R10.w, R2.x, 0 0160 0000480a 00e280f8 18 x: MULADD_IEEE R7.x, R10.z, R2.x, 0 0162 0000440a 20e280f8 y: MULADD_IEEE R7.y, R10.y, R2.x, 0 0164 8000400a 406280f8 z: MULADD_IEEE R3.z, R10.x, R2.x, 0 0166 80000401 60c06b10 19 t: FLT_TO_INT R6.w, R1.y 0168 00004c09 006280f8 20 x: MULADD_IEEE R3.x, R9.w, R2.x, 0 0170 00004809 20c280f8 y: MULADD_IEEE R6.y, R9.z, R2.x, 0 0172 00004409 40e280f8 z: MULADD_IEEE R7.z, R9.y, R2.x, 0 0174 801fac06 60e87010 t: ASHR_INT R7.w, R6.w, [0x0000001f 0].x SCL_212 0176 0000001f 0178 00004009 00c280f8 21 x: MULADD_IEEE R6.x, R9.x, R2.x, 0 0180 0000480b 212280f8 y: MULADD_IEEE R9.y, R11.z, R2.x, 0 0182 00004c0b 412280f8 z: MULADD_IEEE R9.z, R11.w, R2.x, 0 0184 801f0cfe 60e83d10 w: SETNE_INT R7.w, PV.w, 0 VEC_120 0186 801f0cfe 00004508 22 P x: PRED_SETNE_INT __.x, PV.w, 0 0188 c01fac06 60a03b10 23 0 w: SETGT_INT R5.w, R6.w, [0x0000000b 0].x 0190 0000000b 0192 c180cc05 60a380fd 24 0 w: CNDE_INT R5.w, R5.w, R6.w, [0x0000000b 0].x 0194 0000000b 0196 801fac05 60a07210 25 t: LSHL_INT R5.w, R5.w, [0x00000006 0].x 0198 00000006 0200 801facfe 60c03410 26 w: ADD_INT R6.w, PV.w, [0x00000040 0].x 0202 00000040 0204 001facfe 00407110 27 x: ADD __.x, R4.x, R0.x 0206 801fac05 60a07110 t: OR_INT R8.x, PV.w, [0x00000003 0].x 0208 00000004 0210 801facfe 01003110 28 x: OR_INT R9.x, R5.w, [0x00000002 0].x 0212 00000003 0214 801fac05 01203110 29 x: OR_INT R10.x, R5.w, 1 0216 00000002 00000000 30 w: MOV R5.w, 0 0008 00000018 80800c00 TEX 4 @48 0048 400a0040 e8cd100a 00080000 VFETCH R10.xyzw, R10.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0052 40090040 e8cd100b 00080000 VFETCH R11.xyzw, R9.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0056 40080040 e8cd100d 00080000 VFETCH R13.xyzw, R8.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0060 40020040 e8cd100c 00080000 VFETCH R12.xyzw, R2.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0010 0000006e a0940000 ALU 38 @220 0220 800000f8 60a01910 31 w: MOV R5.w, 0 0222 0080440c 20628403 32 y: MULADD_IEEE R3.y, R12.y, R2.y, R3.y 0224 0080400c 40c28806 z: MULADD_IEEE R6.z, R12.x, R2.y, R6.z 0226 80804c0d 60628c03 w: MULADD_IEEE R3.w, R13.w, R2.y, R3.w 0228 0080480d 00228001 33 x: MULADD_IEEE R1.x, R13.z, R2.y, R1.x 0230 0080440d 20228408 y: MULADD_IEEE R1.y, R13.y, R2.y, R8.y 0232 0080400d 41028808 z: MULADD_IEEE R8.z, R13.x, R2.y, R8.z 0234 80804c0b 60828c04 w: MULADD_IEEE R4.w, R11.w, R2.y, R4.w 0236 0080480b 00428007 34 x: MULADD_IEEE R2.x, R11.z, R2.y, R7.x 0238 0080440b 20e28407 y: MULADD_IEEE R7.y, R11.y, R2.y, R7.y 0240 8080400b 40628803 z: MULADD_IEEE R3.z, R11.x, R2.y, R3.z 0242 80000801 60c06b10 35 t: FLT_TO_INT R6.w, R1.z 0244 00804c0a 00628003 36 x: MULADD_IEEE R3.x, R10.w, R2.y, R3.x 0246 0080480a 20c28406 y: MULADD_IEEE R6.y, R10.z, R2.y, R6.y 0248 0080440a 40e28807 z: MULADD_IEEE R7.z, R10.y, R2.y, R7.z 0250 801fac06 60e87010 t: ASHR_INT R7.w, R6.w, [0x0000001f 0].x SCL_212 0252 0000001f 0254 0080400a 00c28006 37 x: MULADD_IEEE R6.x, R10.x, R2.y, R6.x 0256 0080480c 21028409 y: MULADD_IEEE R8.y, R12.z, R2.y, R9.y 0258 00804c0c 41228809 z: MULADD_IEEE R9.z, R12.w, R2.y, R9.z 0260 801f0cfe 60e83d10 w: SETNE_INT R7.w, PV.w, 0 VEC_120 0262 801f0cfe 00004508 38 P x: PRED_SETNE_INT __.x, PV.w, 0 0264 c01fac06 60a03b10 39 0 w: SETGT_INT R5.w, R6.w, [0x0000000b 0].x 0266 0000000b 0268 c180cc05 60a380fd 40 0 w: CNDE_INT R5.w, R5.w, R6.w, [0x0000000b 0].x 0270 0000000b 0272 801fac05 60a07210 41 t: LSHL_INT R5.w, R5.w, [0x00000006 0].x 0274 00000006 0276 801facfe 60c03410 42 w: ADD_INT R6.w, PV.w, [0x00000040 0].x 0278 00000040 0280 001facfe 00e07110 43 x: ADD __.x, R4.x, R0.x 0282 801fac05 60a07110 t: OR_INT R8.x, PV.w, [0x00000003 0].x 0284 00000004 0286 801facfe 01003110 44 x: OR_INT R9.x, R5.w, [0x00000002 0].x 0288 00000003 0290 801fac05 01203110 45 x: OR_INT R10.x, R5.w, 1 0292 00000002 00000000 46 w: MOV R5.w, 0 0012 00000020 80800c00 TEX 4 @64 0064 400a0040 e8cd100a 00080000 VFETCH R10.xyzw, R10.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0068 40090040 e8cd100b 00080000 VFETCH R11.xyzw, R9.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0072 40080040 e8cd100d 00080000 VFETCH R13.xyzw, R8.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0076 40070040 e8cd100c 00080000 VFETCH R12.xyzw, R7.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0014 00000094 a0900000 ALU 37 @296 0296 800000f8 60a01910 47 w: MOV R5.w, 0 0298 0100440c 20628403 48 y: MULADD_IEEE R3.y, R12.y, R2.z, R3.y 0300 0100400c 40c28806 z: MULADD_IEEE R6.z, R12.x, R2.z, R6.z 0302 81004c0d 60628c03 w: MULADD_IEEE R3.w, R13.w, R2.z, R3.w 0304 0100480d 00228001 49 x: MULADD_IEEE R1.x, R13.z, R2.z, R1.x 0306 0100440d 20228401 y: MULADD_IEEE R1.y, R13.y, R2.z, R1.y 0308 0100400d 40228808 z: MULADD_IEEE R1.z, R13.x, R2.z, R8.z 0310 81004c0b 60828c04 w: MULADD_IEEE R4.w, R11.w, R2.z, R4.w 0312 0100480b 00428002 50 x: MULADD_IEEE R2.x, R11.z, R2.z, R2.x 0314 0100440b 20428407 y: MULADD_IEEE R2.y, R11.y, R2.z, R7.y 0316 8100400b 40628803 z: MULADD_IEEE R3.z, R11.x, R2.z, R3.z 0318 80000c01 60206b10 51 t: FLT_TO_INT R1.w, R1.w 0320 01004c0a 00628003 52 x: MULADD_IEEE R3.x, R10.w, R2.z, R3.x 0322 0100480a 20c28406 y: MULADD_IEEE R6.y, R10.z, R2.z, R6.y 0324 0100440a 40e28807 z: MULADD_IEEE R7.z, R10.y, R2.z, R7.z 0326 801fac01 60c87010 t: ASHR_INT R6.w, R1.w, [0x0000001f 0].x SCL_212 0328 0000001f 0330 0100400a 00c28006 53 x: MULADD_IEEE R6.x, R10.x, R2.z, R6.x 0332 0100480c 20e28408 y: MULADD_IEEE R7.y, R12.z, R2.z, R8.y 0334 01004c0c 40428809 z: MULADD_IEEE R2.z, R12.w, R2.z, R9.z 0336 801f0cfe 60c83d10 w: SETNE_INT R6.w, PV.w, 0 VEC_120 0338 801f0cfe 00004508 54 P x: PRED_SETNE_INT __.x, PV.w, 0 0340 c01fac01 60a03b10 55 0 w: SETGT_INT R5.w, R1.w, [0x0000000b 0].x 0342 0000000b 0344 c1802c05 60a380fd 56 0 w: CNDE_INT R5.w, R5.w, R1.w, [0x0000000b 0].x 0346 0000000b 0348 801fac05 60207210 57 t: LSHL_INT R1.w, R5.w, [0x00000002 0].x 0350 00000002 0352 001fac05 41007210 58 t: LSHL_INT R8.z, R5.w, [0x00000006 0].x 0354 809facfe 60283410 w: ADD_INT R1.w, PV.w, [0x00000004 0].y VEC_120 0356 00000006 0357 00000004 0358 001facfe 00e03010 59 x: AND_INT R7.x, PV.w, [0x0ffffffc 2,52435e-29].x 0360 809fa8fe 60207110 t: LSHR_INT R1.w, PV.z, [0x00000004 0].y 0362 0ffffffc 0363 00000004 0364 801f4cfe 01203110 60 x: OR_INT R9.x, PV.w, 1 0366 801fac01 01003110 61 x: OR_INT R8.x, R1.w, [0x00000002 0].x 0368 00000002 0016 00000028 80800800 TEX 3 @80 0080 40080040 e8cd1008 00080000 VFETCH R8.xyzw, R8.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0084 40090040 e8cd1009 00080000 VFETCH R9.xyzw, R9.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0088 40070040 e8cd100a 00080000 VFETCH R10.xyzw, R7.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0018 800000b9 a1280008 ALU 75 @370 KC0[CB0:32-63] 0370 00138095 41600210 62 z: MUL_IEEE R11.z, KC0[21].x, KC0[28].x 0372 80138495 60a00210 w: MUL_IEEE R5.w, KC0[21].y, KC0[28].x 0374 00938496 41828cfe 63 z: MULADD_IEEE R12.z, KC0[22].y, KC0[28].y, PV.w 0376 80938096 60a288fe w: MULADD_IEEE R5.w, KC0[22].x, KC0[28].y, PV.z 0378 01138097 41628cfe 64 z: MULADD_IEEE R11.z, KC0[23].x, KC0[28].z, PV.w 0380 81138497 60a288fe w: MULADD_IEEE R5.w, KC0[23].y, KC0[28].z, PV.z 0382 81938498 60a28cfe 65 w: MULADD_IEEE R5.w, KC0[24].y, KC0[28].w, PV.w 0384 00138c95 41800210 66 z: MUL_IEEE R12.z, KC0[21].w, KC0[28].x 0386 80138895 60c00210 w: MUL_IEEE R6.w, KC0[21].z, KC0[28].x 0388 00938896 41c28cfe 67 z: MULADD_IEEE R14.z, KC0[22].z, KC0[28].y, PV.w 0390 80938c96 60c288fe w: MULADD_IEEE R6.w, KC0[22].w, KC0[28].y, PV.z 0392 01138c97 41a28cfe 68 z: MULADD_IEEE R13.z, KC0[23].w, KC0[28].z, PV.w 0394 81138897 60c288fe w: MULADD_IEEE R6.w, KC0[23].z, KC0[28].z, PV.z 0396 01938898 41828cfe 69 z: MULADD_IEEE R12.z, KC0[24].z, KC0[28].w, PV.w 0398 81938c98 60c288fe w: MULADD_IEEE R6.w, KC0[24].w, KC0[28].w, PV.z 0400 00136895 41a00210 70 z: MUL_IEEE R13.z, KC0[21].z, KC0[27].x 0402 80136c95 60e00210 w: MUL_IEEE R7.w, KC0[21].w, KC0[27].x 0404 00936c96 41c28cfe 71 z: MULADD_IEEE R14.z, KC0[22].w, KC0[27].y, PV.w 0406 80936896 60e288fe w: MULADD_IEEE R7.w, KC0[22].z, KC0[27].y, PV.z 0408 01136897 41a28cfe 72 z: MULADD_IEEE R13.z, KC0[23].z, KC0[27].z, PV.w 0410 81136c97 60e288fe w: MULADD_IEEE R7.w, KC0[23].w, KC0[27].z, PV.z 0412 00134895 41e00210 73 z: MUL_IEEE R15.z, KC0[21].z, KC0[26].x 0414 80134c95 61600210 w: MUL_IEEE R11.w, KC0[21].w, KC0[26].x 0416 00934c96 41c28cfe 74 z: MULADD_IEEE R14.z, KC0[22].w, KC0[26].y, PV.w 0418 80934896 616288fe w: MULADD_IEEE R11.w, KC0[22].z, KC0[26].y, PV.z 0420 01134897 41e28cfe 75 z: MULADD_IEEE R15.z, KC0[23].z, KC0[26].z, PV.w 0422 81134c97 616288fe w: MULADD_IEEE R11.w, KC0[23].w, KC0[26].z, PV.z 0424 81934c98 61628cfe 76 w: MULADD_IEEE R11.w, KC0[24].w, KC0[26].w, PV.w 0426 00132c95 41c00210 77 z: MUL_IEEE R14.z, KC0[21].w, KC0[25].x 0428 80132895 61800210 w: MUL_IEEE R12.w, KC0[21].z, KC0[25].x 0430 00932896 42028cfe 78 z: MULADD_IEEE R16.z, KC0[22].z, KC0[25].y, PV.w 0432 80932c96 618288fe w: MULADD_IEEE R12.w, KC0[22].w, KC0[25].y, PV.z 0434 00136495 41c00210 79 z: MUL_IEEE R14.z, KC0[21].y, KC0[27].x 0436 80136095 61a00210 w: MUL_IEEE R13.w, KC0[21].x, KC0[27].x 0438 00936096 42428cfe 80 z: MULADD_IEEE R18.z, KC0[22].x, KC0[27].y, PV.w 0440 80936496 61a288fe w: MULADD_IEEE R13.w, KC0[22].y, KC0[27].y, PV.z 0442 01136497 42228cfe 81 z: MULADD_IEEE R17.z, KC0[23].y, KC0[27].z, PV.w 0444 81136097 61a288fe w: MULADD_IEEE R13.w, KC0[23].x, KC0[27].z, PV.z 0446 01936098 41c28cfe 82 z: MULADD_IEEE R14.z, KC0[24].x, KC0[27].w, PV.w 0448 81936498 61a288fe w: MULADD_IEEE R13.w, KC0[24].y, KC0[27].w, PV.z 0450 80134095 61c00210 83 w: MUL_IEEE R14.w, KC0[21].x, KC0[26].x 0452 80934096 61c28cfe 84 w: MULADD_IEEE R14.w, KC0[22].x, KC0[26].y, PV.w 0454 01134097 42228cfe 85 z: MULADD_IEEE R17.z, KC0[23].x, KC0[26].z, PV.w 0456 8180400a 62228806 w: MULADD_IEEE R17.w, R10.x, R2.w, R6.z 0458 019fc891 21600210 86 y: MUL_IEEE R11.y, KC0[17].z, PV.w 0460 0180440a 40c28403 z: MULADD_IEEE R6.z, R10.y, R2.w, R3.y 0462 81804009 61e28006 w: MULADD_IEEE R15.w, R9.x, R2.w, R6.x 0464 019fcc91 00e00210 87 x: MUL_IEEE R7.x, KC0[17].w, PV.w 0466 01804409 20628807 y: MULADD_IEEE R3.y, R9.y, R2.w, R7.z 0468 011fc892 40e284fe z: MULADD_IEEE R7.z, KC0[18].z, PV.z, PV.y 0470 8180480a 61c28407 w: MULADD_IEEE R14.w, R10.z, R2.w, R7.y 0472 019fc893 00c288fe 88 x: MULADD_IEEE R6.x, KC0[19].z, PV.w, PV.z 0474 01804008 20e28803 y: MULADD_IEEE R7.y, R8.x, R2.w, R3.z 0476 009fcc92 406280fe z: MULADD_IEEE R3.z, KC0[18].w, PV.y, PV.x 0478 81804809 62028406 w: MULADD_IEEE R16.w, R9.z, R2.w, R6.y 0480 019fcc93 00e288fe 89 x: MULADD_IEEE R7.x, KC0[19].w, PV.w, PV.z 0482 009fcc91 20c00210 y: MUL_IEEE R6.y, KC0[17].w, PV.y 0484 01804408 40628402 z: MULADD_IEEE R3.z, R8.y, R2.w, R2.y 0486 81822c91 62440210 w: MUL_IEEE R18.w, KC0[17].w, R17.w VEC_021 0488 01804c09 00628003 90 x: MULADD_IEEE R3.x, R9.w, R2.w, R3.x 0490 0100cc92 20428cfe y: MULADD_IEEE R2.y, KC0[18].w, R6.z, PV.w 0492 011fcc92 40e684fe z: MULADD_IEEE R7.z, KC0[18].w, PV.z, PV.y VEC_021 0494 81804808 62468002 w: MULADD_IEEE R18.w, R8.z, R2.w, R2.x VEC_021 0496 019fcc93 012288fe 91 x: MULADD_IEEE R9.x, KC0[19].w, PV.w, PV.z 0498 81804c08 20c28c04 y: MULADD_IEEE R6.y, R8.w, R2.w, R4.w 0500 0181cc93 40e28402 92 z: MULADD_IEEE R7.z, KC0[19].w, R14.w, R2.y 0502 81804c0a 61068802 w: MULADD_IEEE R8.w, R10.w, R2.w, R2.z VEC_021 0504 019fcc94 004288fe 93 x: MULADD_IEEE R2.x, KC0[20].w, PV.w, PV.z 0506 0080cc94 20428009 y: MULADD_IEEE R2.y, KC0[20].w, R6.y, R9.x 0508 80006c94 40528007 z: MULADD_IEEE R2.z, KC0[20].w, R3.x, R7.x VEC_201 0510 81810894 60828006 94 w: MULADD_IEEE R4.w, KC0[20].z, R8.w, R6.x 0512 80134495 61200210 95 w: MUL_IEEE R9.w, KC0[21].y, KC0[26].x 0514 001fac01 00c03110 96 x: OR_INT R6.x, R1.w, [0x00000003 0].x 0516 80934496 60228cfe w: MULADD_IEEE R1.w, KC0[22].y, KC0[26].y, PV.w 0518 00000003 0020 0000002e 80800000 TEX 1 @92 0092 40060040 e8cd100a 00080000 VFETCH R10.xyzw, R6.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0022 80000104 a1c8000a ALU 115 @520 KC0[CB0:32-63] KC1[CB0:0-31] 0520 81134497 61228c01 97 w: MULADD_IEEE R9.w, KC0[23].y, KC0[26].z, R1.w 0522 00132495 41000210 98 z: MUL_IEEE R8.z, KC0[21].y, KC0[25].x 0524 80132095 60200210 w: MUL_IEEE R1.w, KC0[21].x, KC0[25].x 0526 00932096 40e28cfe 99 z: MULADD_IEEE R7.z, KC0[22].x, KC0[25].y, PV.w 0528 80932496 602288fe w: MULADD_IEEE R1.w, KC0[22].y, KC0[25].y, PV.z 0530 01132497 41028cfe 100 z: MULADD_IEEE R8.z, KC0[23].y, KC0[25].z, PV.w 0532 81132097 602288fe w: MULADD_IEEE R1.w, KC0[23].x, KC0[25].z, PV.z 0534 01932098 21028cfe 101 y: MULADD_IEEE R8.y, KC0[24].x, KC0[25].w, PV.w 0536 01932498 40e288fe z: MULADD_IEEE R7.z, KC0[24].y, KC0[25].w, PV.z 0538 8180400a 62628801 w: MULADD_IEEE R19.w, R10.x, R2.w, R1.z 0540 01822091 00c00210 102 x: MUL_IEEE R6.x, KC0[17].x, R17.w 0542 019fcc91 21240210 y: MUL_IEEE R9.y, KC0[17].w, PV.w VEC_021 0544 019fc891 40240210 z: MUL_IEEE R1.z, KC0[17].z, PV.w VEC_021 0546 8180440a 60268401 w: MULADD_IEEE R1.w, R10.y, R2.w, R1.y VEC_021 0548 01826091 00e00210 103 x: MUL_IEEE R7.x, KC0[17].x, R19.w 0550 019fc892 202688fe y: MULADD_IEEE R1.y, KC0[18].z, PV.w, PV.z VEC_021 0552 019fcc92 402684fe z: MULADD_IEEE R1.z, KC0[18].w, PV.w, PV.y VEC_021 0554 8180480a 62868001 w: MULADD_IEEE R20.w, R10.z, R2.w, R1.x VEC_021 0556 019fcc93 002288fe 104 x: MULADD_IEEE R1.x, KC0[19].w, PV.w, PV.z 0558 019fc893 212284fe y: MULADD_IEEE R9.y, KC0[19].z, PV.w, PV.y 0560 01802092 402280fe z: MULADD_IEEE R1.z, KC0[18].x, R1.w, PV.x 0562 8100c092 62a28006 w: MULADD_IEEE R21.w, KC0[18].x, R6.z, R6.x 0564 0181c093 00e28cfe 105 x: MULADD_IEEE R7.x, KC0[19].x, R14.w, PV.w 0566 01828093 216688fe y: MULADD_IEEE R11.y, KC0[19].x, R20.w, PV.z VEC_021 0568 0080e091 40200210 z: MUL_IEEE R1.z, KC0[17].x, R7.y 0570 8181e091 62ac0210 w: MUL_IEEE R21.w, KC0[17].x, R15.w VEC_102 0572 0080e491 01000210 106 x: MUL_IEEE R8.x, KC0[17].y, R7.y 0574 0181e491 20200210 y: MUL_IEEE R1.y, KC0[17].y, R15.w 0576 00806092 410a8cfe z: MULADD_IEEE R8.z, KC0[18].x, R3.y, PV.w VEC_120 0578 81006092 62a288fe w: MULADD_IEEE R21.w, KC0[18].x, R3.z, PV.z 0580 01824093 00c28cfe 107 x: MULADD_IEEE R6.x, KC0[19].x, R18.w, PV.w 0582 01820093 21a688fe y: MULADD_IEEE R13.y, KC0[19].x, R16.w, PV.z VEC_021 0584 00806492 402284fe z: MULADD_IEEE R1.z, KC0[18].y, R3.y, PV.y 0586 81006492 62a280fe w: MULADD_IEEE R21.w, KC0[18].y, R3.z, PV.x 0588 01824493 01028cfe 108 x: MULADD_IEEE R8.x, KC0[19].y, R18.w, PV.w 0590 01826491 20240210 y: MUL_IEEE R1.y, KC0[17].y, R19.w VEC_021 0592 81820493 402e88fe z: MULADD_IEEE R1.z, KC0[19].y, R16.w, PV.z VEC_102 0594 81822491 62200210 109 w: MUL_IEEE R17.w, KC0[17].y, R17.w 0596 0100c492 21828cfe 110 y: MULADD_IEEE R12.y, KC0[18].y, R6.z, PV.w 0598 00006494 41028801 z: MULADD_IEEE R8.z, KC0[20].y, R3.x, R1.z 0600 81802492 60228401 w: MULADD_IEEE R1.w, KC0[18].y, R1.w, R1.y 0602 81828493 01628cfe 111 x: MULADD_IEEE R11.x, KC0[19].y, R20.w, PV.w 0604 01804c0a 20228c03 112 y: MULADD_IEEE R1.y, R10.w, R2.w, R3.w 0606 0000a808 40200210 z: MUL_IEEE R1.z, R8.z, R5.x 0608 8080c494 60228008 w: MULADD_IEEE R1.w, KC0[20].y, R6.y, R8.x 0610 0181e891 01200210 113 x: MUL_IEEE R9.x, KC0[17].z, R15.w 0612 0080e891 20e00210 y: MUL_IEEE R7.y, KC0[17].z, R7.y 0614 0080acfe 402688fe z: MULADD_IEEE R1.z, PV.w, R5.y, PV.z VEC_021 0616 809fc494 604e800b w: MULADD_IEEE R2.w, KC0[20].y, PV.y, R11.x VEC_102 0618 0100acfe 010288fe 114 x: MULADD_IEEE R8.x, PV.w, R5.z, PV.z 0620 01006892 20e684fe y: MULADD_IEEE R7.y, KC0[18].z, R3.z, PV.y VEC_021 0622 00006094 40c2840d z: MULADD_IEEE R6.z, KC0[20].x, R3.x, R13.y 0624 80806892 606280fe w: MULADD_IEEE R3.w, KC0[18].z, R3.y, PV.x 0626 01820893 01228cfe 115 x: MULADD_IEEE R9.x, KC0[19].z, R16.w, PV.w 0628 0000a8fe 20600210 y: MUL_IEEE R3.y, PV.z, R5.x 0630 0080c094 40628006 z: MULADD_IEEE R3.z, KC0[20].x, R6.y, R6.x 0632 81824893 606a84fe w: MULADD_IEEE R3.w, KC0[19].z, R18.w, PV.y VEC_120 0634 0080c894 00c28cfe 116 x: MULADD_IEEE R6.x, KC0[20].z, R6.y, PV.w 0636 8080a8fe 206a84fe y: MULADD_IEEE R3.y, PV.z, R5.y, PV.y VEC_120 0638 00802094 4022840b 117 z: MULADD_IEEE R1.z, KC0[20].x, R1.y, R11.y 0640 80006894 61428009 w: MULADD_IEEE R10.w, KC0[20].z, R3.x, R9.x 0642 0000acfe 00600210 118 x: MUL_IEEE R3.x, PV.w, R5.x 0644 0100a8fe 20628403 y: MULADD_IEEE R3.y, PV.z, R5.z, R3.y 0646 01810094 41228007 z: MULADD_IEEE R9.z, KC0[20].x, R8.w, R7.x 0648 8181c493 6066840c w: MULADD_IEEE R3.w, KC0[19].y, R14.w, R12.y VEC_021 0650 01810494 00e28cfe 119 x: MULADD_IEEE R7.x, KC0[20].y, R8.w, PV.w 0652 011fc4fe 20e00010 y: ADD R7.y, PV.y, PV.z 0654 0080a006 412280fe z: MULADD_IEEE R9.z, R6.x, R5.y, PV.x 0656 80802894 606a8409 w: MULADD_IEEE R3.w, KC0[20].z, R1.y, R9.y VEC_120 0658 0100acfe 006288fe 120 x: MULADD_IEEE R3.x, PV.w, R5.z, PV.z 0660 009fc807 20600210 y: MUL_IEEE R3.y, R7.z, PV.y 0662 001fc008 40e00010 z: ADD R7.z, R8.x, PV.x 0664 81934498 61028c09 w: MULADD_IEEE R8.w, KC0[24].y, KC0[26].w, R9.w 0666 011fccfe 00e284fe 121 x: MULADD_IEEE R7.x, PV.w, PV.z, PV.y 0668 018080fe 20600010 y: ADD R3.y, PV.x, R4.w 0670 0080e408 41200210 z: MUL_IEEE R9.z, R8.y, R7.y 0672 81934098 60828811 w: MULADD_IEEE R4.w, KC0[24].x, KC0[26].w, R17.z 0674 0100ecfe 006288fe 122 x: MULADD_IEEE R3.x, PV.w, R7.z, PV.z 0676 009fcc0d 20c280fe y: MULADD_IEEE R6.y, R13.w, PV.y, PV.x 0678 01132c97 41228c0c z: MULADD_IEEE R9.z, KC0[23].w, KC0[25].z, R12.w 0680 81132897 60828810 w: MULADD_IEEE R4.w, KC0[23].z, KC0[25].z, R16.z 0682 00008808 00e00210 123 x: MUL_IEEE R7.x, R8.z, R4.x 0684 01932898 21028cfe y: MULADD_IEEE R8.y, KC0[24].z, KC0[25].w, PV.w 0686 0000a802 40480210 z: MUL_IEEE R2.z, R2.z, R5.x VEC_120 0688 81932c98 608288fe w: MULADD_IEEE R4.w, KC0[24].w, KC0[25].w, PV.z 0690 0080ecfe 00a00210 124 x: MUL_IEEE R5.x, PV.w, R7.y 0692 8080a402 204688fe y: MULADD_IEEE R2.y, R2.y, R5.y, PV.z VEC_021 0694 00802c94 40428001 125 z: MULADD_IEEE R2.z, KC0[20].w, R1.y, R1.x 0696 80008c0a 60800210 w: MUL_IEEE R4.w, R10.w, R4.x 0698 00808006 00228cfe 126 x: MULADD_IEEE R1.x, R6.x, R4.y, PV.w 0700 0100a8fe 20228402 y: MULADD_IEEE R1.y, PV.z, R5.z, R2.y 0702 0100ec0b 40468005 z: MULADD_IEEE R2.z, R11.w, R7.z, R5.x VEC_021 0704 81936c98 60828c07 w: MULADD_IEEE R4.w, KC0[24].w, KC0[27].w, R7.w 0706 00806cfe 00a288fe 127 x: MULADD_IEEE R5.x, PV.w, R3.y, PV.z 0708 000044fe 20200010 y: ADD R1.y, PV.y, R2.x 0710 0080e408 40440210 z: MUL_IEEE R2.z, R8.y, R7.y VEC_021 0712 81934898 6082880f w: MULADD_IEEE R4.w, KC0[24].z, KC0[26].w, R15.z 0714 00008806 00800210 128 x: MUL_IEEE R4.x, R6.z, R4.x 0716 0100ecfe 204288fe y: MULADD_IEEE R2.y, PV.w, R7.z, PV.z 0718 01936898 4042880d z: MULADD_IEEE R2.z, KC0[24].z, KC0[27].w, R13.z 0720 809fcc06 612280fe w: MULADD_IEEE R9.w, R6.w, PV.y, PV.x 0722 008068fe 004284fe 129 x: MULADD_IEEE R2.x, PV.z, R3.y, PV.y 0724 000004a0 20001910 y: MOV R0.y, KC1[0].y 0726 00808803 404680fe z: MULADD_IEEE R2.z, R3.z, R4.y, PV.x VEC_021 0728 81008c03 61028001 w: MULADD_IEEE R8.w, R3.w, R4.z, R1.x 0730 000000a0 00001910 130 x: MOV R0.x, KC1[0].x 0732 01008801 210288fe y: MULADD_IEEE R8.y, R1.z, R4.z, PV.z 0734 0080280c 413280fe z: MULADD_IEEE R9.z, R12.z, R1.y, PV.x VEC_201 0736 80808c01 60228007 w: MULADD_IEEE R1.w, R1.w, R4.y, R7.x 0738 01008c02 01028cfe 131 x: MULADD_IEEE R8.x, R2.w, R4.z, PV.w 0740 00802c05 212a8406 y: MULADD_IEEE R9.y, R5.w, R1.y, R6.y VEC_120 0742 0080680e 40228003 z: MULADD_IEEE R1.z, R14.z, R3.y, R3.x 0744 81938098 6022880b w: MULADD_IEEE R1.w, KC0[24].x, KC0[28].w, R11.z 0746 00802cfe 012288fe 132 x: MULADD_IEEE R9.x, PV.w, R1.y, PV.z 0748 800008a0 41001910 z: MOV R8.z, KC1[0].z 0024 c004a03c 94400688 EXPORT_DONE POS 60 R9.xyzw VPM 0026 c0004000 93c0021a EXPORT PARAM 0 R0.zwxy VPM 0028 c0044001 9460060a EXPORT_DONE PARAM 1 R8.zyxw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[19], PERSPECTIVE DCL IN[1], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0..1] DCL TEMP[0..4], LOCAL IMM[0] FLT32 { 0,7500, 0,2500, 0,0000, 2,0000} 0: MOV TEMP[0].z, IN[1].xxxx 1: MOV TEMP[0].xy, IN[0].zwzz 2: MOV TEMP[1].xy, IN[0].xyyy 3: TEX TEMP[1], TEMP[1], SAMP[0], 2D 4: MOV TEMP[2].xyz, CONST[1] 5: DP3 TEMP[3].x, IN[1].yzww, IN[1].yzww 6: RSQ TEMP[3].x, TEMP[3].xxxx 7: MUL TEMP[3].xyz, IN[1].yzww, TEMP[3].xxxx 8: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz 9: RSQ TEMP[4].x, TEMP[4].xxxx 10: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[4].xxxx 11: DP3 TEMP[0].x, TEMP[3].xyzz, TEMP[0].xyzz 12: MAD TEMP[0].x, TEMP[0].xxxx, IMM[0].xxxx, IMM[0].yyyy 13: SLT TEMP[3].x, IMM[0].zzzz, TEMP[0].xxxx 14: F2I TEMP[3].x, -TEMP[3] 15: UIF TEMP[3].xxxx :0 16: MUL TEMP[0], CONST[0], TEMP[0].xxxx 17: MAD TEMP[2].xyz, TEMP[0], IMM[0].wwww, CONST[1] 18: ENDIF 19: MUL TEMP[0].xyz, TEMP[1].xyzz, TEMP[2].xyzz 20: MOV TEMP[0].w, TEMP[1].wwww 21: MOV OUT[0], TEMP[0] 22: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = call float @llvm.R600.load.input(i32 4) %5 = call float @llvm.R600.load.input(i32 5) %6 = call float @llvm.R600.load.input(i32 6) %7 = call float @llvm.R600.load.input(i32 7) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float 0,000000e+00, i32 2 %11 = insertelement <4 x float> %10, float 0,000000e+00, i32 3 %12 = extractelement <4 x float> %11, i32 0 %13 = extractelement <4 x float> %11, i32 1 %14 = insertelement <4 x float> undef, float %12, i32 0 %15 = insertelement <4 x float> %14, float %13, i32 1 %16 = insertelement <4 x float> %15, float undef, i32 2 %17 = insertelement <4 x float> %16, float undef, i32 3 %18 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %17, i32 16, i32 0, i32 2) %19 = extractelement <4 x float> %18, i32 0 %20 = extractelement <4 x float> %18, i32 1 %21 = extractelement <4 x float> %18, i32 2 %22 = extractelement <4 x float> %18, i32 3 %23 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %24 = extractelement <4 x float> %23, i32 0 %25 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %26 = extractelement <4 x float> %25, i32 1 %27 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %28 = extractelement <4 x float> %27, i32 2 %29 = insertelement <4 x float> undef, float %5, i32 0 %30 = insertelement <4 x float> %29, float %6, i32 1 %31 = insertelement <4 x float> %30, float %7, i32 2 %32 = insertelement <4 x float> %31, float 0,000000e+00, i32 3 %33 = insertelement <4 x float> undef, float %5, i32 0 %34 = insertelement <4 x float> %33, float %6, i32 1 %35 = insertelement <4 x float> %34, float %7, i32 2 %36 = insertelement <4 x float> %35, float 0,000000e+00, i32 3 %37 = call float @llvm.AMDGPU.dp4(<4 x float> %32, <4 x float> %36) %38 = call float @fabs(float %37) %39 = call float @llvm.AMDGPU.rsq(float %38) %40 = fmul float %5, %39 %41 = fmul float %6, %39 %42 = fmul float %7, %39 %43 = insertelement <4 x float> undef, float %2, i32 0 %44 = insertelement <4 x float> %43, float %3, i32 1 %45 = insertelement <4 x float> %44, float %4, i32 2 %46 = insertelement <4 x float> %45, float 0,000000e+00, i32 3 %47 = insertelement <4 x float> undef, float %2, i32 0 %48 = insertelement <4 x float> %47, float %3, i32 1 %49 = insertelement <4 x float> %48, float %4, i32 2 %50 = insertelement <4 x float> %49, float 0,000000e+00, i32 3 %51 = call float @llvm.AMDGPU.dp4(<4 x float> %46, <4 x float> %50) %52 = call float @fabs(float %51) %53 = call float @llvm.AMDGPU.rsq(float %52) %54 = fmul float %2, %53 %55 = fmul float %3, %53 %56 = fmul float %4, %53 %57 = insertelement <4 x float> undef, float %40, i32 0 %58 = insertelement <4 x float> %57, float %41, i32 1 %59 = insertelement <4 x float> %58, float %42, i32 2 %60 = insertelement <4 x float> %59, float 0,000000e+00, i32 3 %61 = insertelement <4 x float> undef, float %54, i32 0 %62 = insertelement <4 x float> %61, float %55, i32 1 %63 = insertelement <4 x float> %62, float %56, i32 2 %64 = insertelement <4 x float> %63, float 0,000000e+00, i32 3 %65 = call float @llvm.AMDGPU.dp4(<4 x float> %60, <4 x float> %64) %66 = fmul float %65, 0x3FE8000000000000 %67 = fadd float %66, 0x3FD0000000000000 %68 = fcmp ult float 0,000000e+00, %67 %69 = select i1 %68, float 0x3FF0000000000000, float 0,000000e+00 %70 = fsub float -0,000000e+00, %69 %71 = fptosi float %70 to i32 %72 = bitcast i32 %71 to float %73 = bitcast float %72 to i32 %74 = icmp ne i32 %73, 0 br i1 %74, label %IF, label %ENDIF IF: ; preds = %main_body %75 = load <4 x float> addrspace(8)* null %76 = extractelement <4 x float> %75, i32 0 %77 = fmul float %76, %67 %78 = load <4 x float> addrspace(8)* null %79 = extractelement <4 x float> %78, i32 1 %80 = fmul float %79, %67 %81 = load <4 x float> addrspace(8)* null %82 = extractelement <4 x float> %81, i32 2 %83 = fmul float %82, %67 %84 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %85 = extractelement <4 x float> %84, i32 0 %86 = fmul float %77, 0x4000000000000000 %87 = fadd float %86, %85 %88 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %89 = extractelement <4 x float> %88, i32 1 %90 = fmul float %80, 0x4000000000000000 %91 = fadd float %90, %89 %92 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %93 = extractelement <4 x float> %92, i32 2 %94 = fmul float %83, 0x4000000000000000 %95 = fadd float %94, %93 br label %ENDIF ENDIF: ; preds = %main_body, %IF %temp8.0 = phi float [ %87, %IF ], [ %24, %main_body ] %temp9.0 = phi float [ %91, %IF ], [ %26, %main_body ] %temp10.0 = phi float [ %95, %IF ], [ %28, %main_body ] %96 = fmul float %19, %temp8.0 %97 = fmul float %20, %temp9.0 %98 = fmul float %21, %temp10.0 %99 = insertelement <4 x float> undef, float %96, i32 0 %100 = insertelement <4 x float> %99, float %97, i32 1 %101 = insertelement <4 x float> %100, float %98, i32 2 %102 = insertelement <4 x float> %101, float %22, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %102, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } ===== SHADER #54 =========================================== PS/RS880/R600 ===== ===== 110 dw ===== 4 gprs ===== 0 stack ======================================== 0000 00000004 80800000 TEX 1 @8 0008 00001010 f00d1002 68800000 SAMPLE R2.xyzw, R0.xyzw, RID:16, SID:0 CT:NNNN 0002 80000006 a0c00000 ALU 49 @12 KC0[CB0:0-31] 0012 80000c01 40601910 1 z: MOV R3.z, R1.w 0014 80000801 20601910 2 y: MOV R3.y, R1.z 0016 00000401 00601910 3 x: MOV R3.x, R1.y 0018 80000001 40201910 z: MOV R1.z, R1.x 0020 80000c00 20001910 4 y: MOV R0.y, R0.w 0022 00000800 00001910 5 x: MOV R0.x, R0.z 0024 800000fd 60001910 w: MOV R0.w, [0x00000000 0].x 0026 00000000 0028 00006003 00005000 6 x: DOT4 __.x, R3.x, R3.x 0030 00806403 20005000 y: DOT4 __.y, R3.y, R3.y 0032 01006803 40005010 z: DOT4 R0.z, R3.z, R3.z 0034 81800c00 60005000 w: DOT4 __.w, R0.w, R0.w 0036 80000800 60606711 7 t: RECIPSQRT_CLAMPED R3.w, |R0.z| 0038 00000000 00205000 8 x: DOT4 __.x, R0.x, R0.x 0040 00800400 20205000 y: DOT4 __.y, R0.y, R0.y 0042 01002801 40205000 z: DOT4 __.z, R1.z, R1.z 0044 81800c00 60205010 w: DOT4 R1.w, R0.w, R0.w 0046 01806003 00200210 9 x: MUL_IEEE R1.x, R3.x, R3.w 0048 01806403 20200210 y: MUL_IEEE R1.y, R3.y, R3.w 0050 81806803 40000210 z: MUL_IEEE R0.z, R3.z, R3.w 0052 80000c01 60206711 10 t: RECIPSQRT_CLAMPED R1.w, |R1.w| 0054 01802000 00000210 11 x: MUL_IEEE R0.x, R0.x, R1.w 0056 01802400 20000210 y: MUL_IEEE R0.y, R0.y, R1.w 0058 01802801 40200210 z: MUL_IEEE R1.z, R1.z, R1.w 0060 800000fd 60201910 w: MOV R1.w, [0x3f400000 0,75].x 0062 3f400000 0064 00000001 00005010 12 x: DOT4 R0.x, R1.x, R0.x 0066 00800401 20005000 y: DOT4 __.y, R1.y, R0.y 0068 01002800 40005000 z: DOT4 __.z, R0.z, R1.z 0070 81800c00 60005000 w: DOT4 __.w, R0.w, R0.w 0072 818020fe 600280fd 13 w: MULADD_IEEE R0.w, PV.x, R1.w, [0x3e800000 0,25].x 0074 3e800000 0076 819fc0f8 60200e10 14 w: SETGE_DX10 R1.w, 0, PV.w 0078 801f0cfe 00004208 15 P x: PRED_SETE_INT __.x, PV.w, 0 0080 40000881 20001910 16 0 y: MOV R0.y, KC0[1].z 0082 40000081 40001910 0 z: MOV R0.z, KC0[1].x 0084 c0000481 60001910 0 w: MOV R0.w, KC0[1].y 0086 61800880 20000210 17 1 y: MUL_IEEE R0.y, KC0[0].z, R0.w 0088 61800080 40000210 1 z: MUL_IEEE R0.z, KC0[0].x, R0.w 0090 e1800480 60200210 1 w: MUL_IEEE R1.w, KC0[0].y, R0.w 0092 61800480 20228c01 18 1 y: MULADD_IEEE R1.y, KC0[0].y, R0.w, R1.w 0094 61800080 40028800 1 z: MULADD_IEEE R0.z, KC0[0].x, R0.w, R0.z 0096 e1800880 60028400 1 w: MULADD_IEEE R0.w, KC0[0].z, R0.w, R0.y 0098 61102c00 20000010 19 1 y: ADD R0.y, R0.w, KC0[1].z 0100 60102800 40000010 1 z: ADD R0.z, R0.z, KC0[1].x 0102 e0902401 60000010 1 w: ADD R0.w, R1.y, KC0[1].y 0104 80800802 40400210 20 z: MUL_IEEE R2.z, R2.z, R0.y 0106 81000002 00400210 21 x: MUL_IEEE R2.x, R2.x, R0.z 0108 81800402 20400210 22 y: MUL_IEEE R2.y, R2.y, R0.w 0004 c0010000 94600688 EXPORT_DONE PIXEL 0 R2.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL OUT[0], POSITION DCL OUT[1], GENERIC[19] DCL OUT[2], GENERIC[20] DCL CONST[0..24] DCL TEMP[0..3], ARRAY(1), LOCAL DCL TEMP[4..7], ARRAY(2), LOCAL DCL TEMP[8..10], LOCAL DCL TEMP[11..14], ARRAY(3), LOCAL DCL TEMP[15..18], ARRAY(4), LOCAL DCL TEMP[19..22], ARRAY(5), LOCAL DCL TEMP[23..26], ARRAY(6), LOCAL DCL TEMP[27..29], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0,0000, 0,0000, 0,0000, 0,0000} IMM[1] INT32 {0, 2, 4, 0} 0: MOV TEMP[0], IMM[0].xxxx 1: MOV TEMP[1], IMM[0].xxxx 2: MOV TEMP[2], IMM[0].xxxx 3: MOV TEMP[3], IMM[0].xxxx 4: MOV TEMP[4], TEMP[0] 5: MOV TEMP[5], TEMP[1] 6: MOV TEMP[6], TEMP[2] 7: MOV TEMP[7], TEMP[3] 8: F2I TEMP[8].x, IN[0].xxxx 9: ISLT TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx 10: UIF TEMP[9].xxxx :0 11: MOV TEMP[9].x, IMM[1].xxxx 12: ELSE :0 13: ISLT TEMP[10].x, IMM[1].yyyy, TEMP[8].xxxx 14: UIF TEMP[10].xxxx :0 15: MOV TEMP[10].x, IMM[1].yyyy 16: ELSE :0 17: MOV TEMP[10].x, TEMP[8].xxxx 18: ENDIF 19: MOV TEMP[9].x, TEMP[10].xxxx 20: ENDIF 21: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 22: UARL ADDR[0].x, TEMP[8].xxxx 23: UARL ADDR[0].x, TEMP[8].xxxx 24: MAD TEMP[11], CONST[ADDR[0].x+1], IN[1].xxxx, TEMP[4] 25: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 26: UARL ADDR[0].x, TEMP[8].xxxx 27: UARL ADDR[0].x, TEMP[8].xxxx 28: MAD TEMP[12], CONST[ADDR[0].x+2], IN[1].xxxx, TEMP[5] 29: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 30: UARL ADDR[0].x, TEMP[8].xxxx 31: UARL ADDR[0].x, TEMP[8].xxxx 32: MAD TEMP[13], CONST[ADDR[0].x+3], IN[1].xxxx, TEMP[6] 33: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 34: UARL ADDR[0].x, TEMP[8].xxxx 35: UARL ADDR[0].x, TEMP[8].xxxx 36: MAD TEMP[14], CONST[ADDR[0].x+4], IN[1].xxxx, TEMP[7] 37: MOV TEMP[4], TEMP[11] 38: MOV TEMP[5], TEMP[12] 39: MOV TEMP[6], TEMP[13] 40: MOV TEMP[7], TEMP[14] 41: F2I TEMP[8].x, IN[0].yyyy 42: ISLT TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx 43: UIF TEMP[9].xxxx :0 44: MOV TEMP[9].x, IMM[1].xxxx 45: ELSE :0 46: ISLT TEMP[10].x, IMM[1].yyyy, TEMP[8].xxxx 47: UIF TEMP[10].xxxx :0 48: MOV TEMP[10].x, IMM[1].yyyy 49: ELSE :0 50: MOV TEMP[10].x, TEMP[8].xxxx 51: ENDIF 52: MOV TEMP[9].x, TEMP[10].xxxx 53: ENDIF 54: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 55: UARL ADDR[0].x, TEMP[8].xxxx 56: UARL ADDR[0].x, TEMP[8].xxxx 57: MAD TEMP[15], CONST[ADDR[0].x+1], IN[1].yyyy, TEMP[11] 58: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 59: UARL ADDR[0].x, TEMP[8].xxxx 60: UARL ADDR[0].x, TEMP[8].xxxx 61: MAD TEMP[16], CONST[ADDR[0].x+2], IN[1].yyyy, TEMP[12] 62: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 63: UARL ADDR[0].x, TEMP[8].xxxx 64: UARL ADDR[0].x, TEMP[8].xxxx 65: MAD TEMP[17], CONST[ADDR[0].x+3], IN[1].yyyy, TEMP[13] 66: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 67: UARL ADDR[0].x, TEMP[8].xxxx 68: UARL ADDR[0].x, TEMP[8].xxxx 69: MAD TEMP[18], CONST[ADDR[0].x+4], IN[1].yyyy, TEMP[14] 70: MOV TEMP[4], TEMP[15] 71: MOV TEMP[5], TEMP[16] 72: MOV TEMP[6], TEMP[17] 73: MOV TEMP[7], TEMP[18] 74: F2I TEMP[8].x, IN[0].zzzz 75: ISLT TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx 76: UIF TEMP[9].xxxx :0 77: MOV TEMP[9].x, IMM[1].xxxx 78: ELSE :0 79: ISLT TEMP[10].x, IMM[1].yyyy, TEMP[8].xxxx 80: UIF TEMP[10].xxxx :0 81: MOV TEMP[10].x, IMM[1].yyyy 82: ELSE :0 83: MOV TEMP[10].x, TEMP[8].xxxx 84: ENDIF 85: MOV TEMP[9].x, TEMP[10].xxxx 86: ENDIF 87: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 88: UARL ADDR[0].x, TEMP[8].xxxx 89: UARL ADDR[0].x, TEMP[8].xxxx 90: MAD TEMP[19], CONST[ADDR[0].x+1], IN[1].zzzz, TEMP[15] 91: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 92: UARL ADDR[0].x, TEMP[8].xxxx 93: UARL ADDR[0].x, TEMP[8].xxxx 94: MAD TEMP[20], CONST[ADDR[0].x+2], IN[1].zzzz, TEMP[16] 95: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 96: UARL ADDR[0].x, TEMP[8].xxxx 97: UARL ADDR[0].x, TEMP[8].xxxx 98: MAD TEMP[21], CONST[ADDR[0].x+3], IN[1].zzzz, TEMP[17] 99: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 100: UARL ADDR[0].x, TEMP[8].xxxx 101: UARL ADDR[0].x, TEMP[8].xxxx 102: MAD TEMP[22], CONST[ADDR[0].x+4], IN[1].zzzz, TEMP[18] 103: MOV TEMP[4], TEMP[19] 104: MOV TEMP[5], TEMP[20] 105: MOV TEMP[6], TEMP[21] 106: MOV TEMP[7], TEMP[22] 107: F2I TEMP[8].x, IN[0].wwww 108: ISLT TEMP[9].x, TEMP[8].xxxx, IMM[1].xxxx 109: UIF TEMP[9].xxxx :0 110: MOV TEMP[9].x, IMM[1].xxxx 111: ELSE :0 112: ISLT TEMP[10].x, IMM[1].yyyy, TEMP[8].xxxx 113: UIF TEMP[10].xxxx :0 114: MOV TEMP[10].x, IMM[1].yyyy 115: ELSE :0 116: MOV TEMP[10].x, TEMP[8].xxxx 117: ENDIF 118: MOV TEMP[9].x, TEMP[10].xxxx 119: ENDIF 120: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 121: UARL ADDR[0].x, TEMP[8].xxxx 122: UARL ADDR[0].x, TEMP[8].xxxx 123: MAD TEMP[23], CONST[ADDR[0].x+1], IN[1].wwww, TEMP[19] 124: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 125: UARL ADDR[0].x, TEMP[8].xxxx 126: UARL ADDR[0].x, TEMP[8].xxxx 127: MAD TEMP[24], CONST[ADDR[0].x+2], IN[1].wwww, TEMP[20] 128: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 129: UARL ADDR[0].x, TEMP[8].xxxx 130: UARL ADDR[0].x, TEMP[8].xxxx 131: MAD TEMP[25], CONST[ADDR[0].x+3], IN[1].wwww, TEMP[21] 132: UMUL TEMP[8].x, TEMP[9].xxxx, IMM[1].zzzz 133: UARL ADDR[0].x, TEMP[8].xxxx 134: UARL ADDR[0].x, TEMP[8].xxxx 135: MAD TEMP[26], CONST[ADDR[0].x+4], IN[1].wwww, TEMP[22] 136: MOV TEMP[4], TEMP[23] 137: MOV TEMP[5], TEMP[24] 138: MOV TEMP[6], TEMP[25] 139: MOV TEMP[7], TEMP[26] 140: MUL TEMP[8], CONST[13], TEMP[25].xxxx 141: MAD TEMP[8], CONST[14], TEMP[25].yyyy, TEMP[8] 142: MAD TEMP[8], CONST[15], TEMP[25].zzzz, TEMP[8] 143: MAD TEMP[8], CONST[16], TEMP[25].wwww, TEMP[8] 144: MUL TEMP[9], CONST[13], TEMP[24].xxxx 145: MAD TEMP[9], CONST[14], TEMP[24].yyyy, TEMP[9] 146: MAD TEMP[9], CONST[15], TEMP[24].zzzz, TEMP[9] 147: MAD TEMP[9], CONST[16], TEMP[24].wwww, TEMP[9] 148: MUL TEMP[10], CONST[13], TEMP[23].xxxx 149: MAD TEMP[10], CONST[14], TEMP[23].yyyy, TEMP[10] 150: MAD TEMP[10], CONST[15], TEMP[23].zzzz, TEMP[10] 151: MAD TEMP[10], CONST[16], TEMP[23].wwww, TEMP[10] 152: MUL TEMP[10], TEMP[10], IN[4].xxxx 153: MAD TEMP[9], TEMP[9], IN[4].yyyy, TEMP[10] 154: MAD TEMP[8], TEMP[8], IN[4].zzzz, TEMP[9] 155: MUL TEMP[9], CONST[13], TEMP[26].xxxx 156: MAD TEMP[9], CONST[14], TEMP[26].yyyy, TEMP[9] 157: MAD TEMP[9], CONST[15], TEMP[26].zzzz, TEMP[9] 158: MAD TEMP[9], CONST[16], TEMP[26].wwww, TEMP[9] 159: ADD TEMP[8], TEMP[8], TEMP[9] 160: MUL TEMP[9], CONST[17], CONST[24].xxxx 161: MAD TEMP[9], CONST[18], CONST[24].yyyy, TEMP[9] 162: MAD TEMP[9], CONST[19], CONST[24].zzzz, TEMP[9] 163: MAD TEMP[9], CONST[20], CONST[24].wwww, TEMP[9] 164: MUL TEMP[10], CONST[17], CONST[23].xxxx 165: MAD TEMP[10], CONST[18], CONST[23].yyyy, TEMP[10] 166: MAD TEMP[10], CONST[19], CONST[23].zzzz, TEMP[10] 167: MAD TEMP[10], CONST[20], CONST[23].wwww, TEMP[10] 168: MUL TEMP[27], CONST[17], CONST[22].xxxx 169: MAD TEMP[27], CONST[18], CONST[22].yyyy, TEMP[27] 170: MAD TEMP[27], CONST[19], CONST[22].zzzz, TEMP[27] 171: MAD TEMP[27], CONST[20], CONST[22].wwww, TEMP[27] 172: MUL TEMP[28], CONST[17], CONST[21].xxxx 173: MAD TEMP[28], CONST[18], CONST[21].yyyy, TEMP[28] 174: MAD TEMP[28], CONST[19], CONST[21].zzzz, TEMP[28] 175: MAD TEMP[28], CONST[20], CONST[21].wwww, TEMP[28] 176: MUL TEMP[28], TEMP[28], TEMP[8].xxxx 177: MAD TEMP[27], TEMP[27], TEMP[8].yyyy, TEMP[28] 178: MAD TEMP[10], TEMP[10], TEMP[8].zzzz, TEMP[27] 179: MAD TEMP[8], TEMP[9], TEMP[8].wwww, TEMP[10] 180: MOV TEMP[9].xy, IN[2].xyxx 181: MOV TEMP[9].zw, CONST[0].yyxy 182: MOV TEMP[10].x, CONST[0].zzzz 183: MUL TEMP[27], CONST[13], TEMP[25].xxxx 184: MAD TEMP[27], CONST[14], TEMP[25].yyyy, TEMP[27] 185: MAD TEMP[27], CONST[15], TEMP[25].zzzz, TEMP[27] 186: MAD TEMP[27], CONST[16], TEMP[25].wwww, TEMP[27] 187: MUL TEMP[28], CONST[13], TEMP[24].xxxx 188: MAD TEMP[28], CONST[14], TEMP[24].yyyy, TEMP[28] 189: MAD TEMP[28], CONST[15], TEMP[24].zzzz, TEMP[28] 190: MAD TEMP[28], CONST[16], TEMP[24].wwww, TEMP[28] 191: MUL TEMP[29], CONST[13], TEMP[23].xxxx 192: MAD TEMP[29], CONST[14], TEMP[23].yyyy, TEMP[29] 193: MAD TEMP[29], CONST[15], TEMP[23].zzzz, TEMP[29] 194: MAD TEMP[29], CONST[16], TEMP[23].wwww, TEMP[29] 195: MUL TEMP[29], TEMP[29], IN[3].xxxx 196: MAD TEMP[28], TEMP[28], IN[3].yyyy, TEMP[29] 197: MAD TEMP[27].xyz, TEMP[27], IN[3].zzzz, TEMP[28] 198: MOV TEMP[10].yzw, TEMP[27].yxyz 199: MOV OUT[1], TEMP[9] 200: MOV OUT[2], TEMP[10] 201: MOV OUT[0], TEMP[8] 202: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = call float @llvm.R600.load.input(i32 12) %9 = call float @llvm.R600.load.input(i32 13) %10 = call float @llvm.R600.load.input(i32 14) %11 = call float @llvm.R600.load.input(i32 15) %12 = call float @llvm.R600.load.input(i32 16) %13 = call float @llvm.R600.load.input(i32 17) %14 = call float @llvm.R600.load.input(i32 18) %15 = call float @llvm.R600.load.input(i32 19) %16 = call float @llvm.R600.load.input(i32 20) %17 = call float @llvm.R600.load.input(i32 21) %18 = call float @llvm.R600.load.input(i32 22) %19 = call float @llvm.R600.load.input(i32 23) %20 = fptosi float %0 to i32 %21 = bitcast i32 %20 to float %22 = bitcast float %21 to i32 %23 = icmp slt i32 %22, 0 %24 = sext i1 %23 to i32 %25 = bitcast i32 %24 to float %26 = bitcast float %25 to i32 %27 = icmp ne i32 %26, 0 br i1 %27, label %ENDIF, label %ELSE ELSE: ; preds = %main_body %28 = bitcast float %21 to i32 %29 = icmp slt i32 2, %28 %30 = sext i1 %29 to i32 %31 = bitcast i32 %30 to float %32 = bitcast float %31 to i32 %33 = icmp ne i32 %32, 0 %. = select i1 %33, float 0,000000e+00, float %21 br label %ENDIF ENDIF: ; preds = %main_body, %ELSE %temp36.0 = phi float [ %., %ELSE ], [ 0,000000e+00, %main_body ] %34 = bitcast float %temp36.0 to i32 %35 = mul i32 %34, 4 %36 = bitcast i32 %35 to float %37 = bitcast float %36 to i32 %38 = add i32 1, %37 %39 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %38 %40 = load <4 x float> addrspace(8)* %39 %41 = extractelement <4 x float> %40, i32 0 %42 = fmul float %41, %4 %43 = fadd float %42, 0,000000e+00 %44 = add i32 1, %37 %45 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %44 %46 = load <4 x float> addrspace(8)* %45 %47 = extractelement <4 x float> %46, i32 1 %48 = fmul float %47, %4 %49 = fadd float %48, 0,000000e+00 %50 = add i32 1, %37 %51 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %50 %52 = load <4 x float> addrspace(8)* %51 %53 = extractelement <4 x float> %52, i32 2 %54 = fmul float %53, %4 %55 = fadd float %54, 0,000000e+00 %56 = add i32 1, %37 %57 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %56 %58 = load <4 x float> addrspace(8)* %57 %59 = extractelement <4 x float> %58, i32 3 %60 = fmul float %59, %4 %61 = fadd float %60, 0,000000e+00 %62 = bitcast float %temp36.0 to i32 %63 = mul i32 %62, 4 %64 = bitcast i32 %63 to float %65 = bitcast float %64 to i32 %66 = add i32 2, %65 %67 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %66 %68 = load <4 x float> addrspace(8)* %67 %69 = extractelement <4 x float> %68, i32 0 %70 = fmul float %69, %4 %71 = fadd float %70, 0,000000e+00 %72 = add i32 2, %65 %73 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %72 %74 = load <4 x float> addrspace(8)* %73 %75 = extractelement <4 x float> %74, i32 1 %76 = fmul float %75, %4 %77 = fadd float %76, 0,000000e+00 %78 = add i32 2, %65 %79 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %78 %80 = load <4 x float> addrspace(8)* %79 %81 = extractelement <4 x float> %80, i32 2 %82 = fmul float %81, %4 %83 = fadd float %82, 0,000000e+00 %84 = add i32 2, %65 %85 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %84 %86 = load <4 x float> addrspace(8)* %85 %87 = extractelement <4 x float> %86, i32 3 %88 = fmul float %87, %4 %89 = fadd float %88, 0,000000e+00 %90 = bitcast float %temp36.0 to i32 %91 = mul i32 %90, 4 %92 = bitcast i32 %91 to float %93 = bitcast float %92 to i32 %94 = add i32 3, %93 %95 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %94 %96 = load <4 x float> addrspace(8)* %95 %97 = extractelement <4 x float> %96, i32 0 %98 = fmul float %97, %4 %99 = fadd float %98, 0,000000e+00 %100 = add i32 3, %93 %101 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %100 %102 = load <4 x float> addrspace(8)* %101 %103 = extractelement <4 x float> %102, i32 1 %104 = fmul float %103, %4 %105 = fadd float %104, 0,000000e+00 %106 = add i32 3, %93 %107 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %106 %108 = load <4 x float> addrspace(8)* %107 %109 = extractelement <4 x float> %108, i32 2 %110 = fmul float %109, %4 %111 = fadd float %110, 0,000000e+00 %112 = add i32 3, %93 %113 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %112 %114 = load <4 x float> addrspace(8)* %113 %115 = extractelement <4 x float> %114, i32 3 %116 = fmul float %115, %4 %117 = fadd float %116, 0,000000e+00 %118 = bitcast float %temp36.0 to i32 %119 = mul i32 %118, 4 %120 = bitcast i32 %119 to float %121 = bitcast float %120 to i32 %122 = add i32 4, %121 %123 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %122 %124 = load <4 x float> addrspace(8)* %123 %125 = extractelement <4 x float> %124, i32 0 %126 = fmul float %125, %4 %127 = fadd float %126, 0,000000e+00 %128 = add i32 4, %121 %129 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %128 %130 = load <4 x float> addrspace(8)* %129 %131 = extractelement <4 x float> %130, i32 1 %132 = fmul float %131, %4 %133 = fadd float %132, 0,000000e+00 %134 = add i32 4, %121 %135 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %134 %136 = load <4 x float> addrspace(8)* %135 %137 = extractelement <4 x float> %136, i32 2 %138 = fmul float %137, %4 %139 = fadd float %138, 0,000000e+00 %140 = add i32 4, %121 %141 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %140 %142 = load <4 x float> addrspace(8)* %141 %143 = extractelement <4 x float> %142, i32 3 %144 = fmul float %143, %4 %145 = fadd float %144, 0,000000e+00 %146 = fptosi float %1 to i32 %147 = bitcast i32 %146 to float %148 = bitcast float %147 to i32 %149 = icmp slt i32 %148, 0 %150 = sext i1 %149 to i32 %151 = bitcast i32 %150 to float %152 = bitcast float %151 to i32 %153 = icmp ne i32 %152, 0 br i1 %153, label %ENDIF123, label %ELSE125 ELSE125: ; preds = %ENDIF %154 = bitcast float %147 to i32 %155 = icmp slt i32 2, %154 %156 = sext i1 %155 to i32 %157 = bitcast i32 %156 to float %158 = bitcast float %157 to i32 %159 = icmp ne i32 %158, 0 %.141 = select i1 %159, float 0,000000e+00, float %147 br label %ENDIF123 ENDIF123: ; preds = %ENDIF, %ELSE125 %temp36.1 = phi float [ %.141, %ELSE125 ], [ 0,000000e+00, %ENDIF ] %160 = bitcast float %temp36.1 to i32 %161 = mul i32 %160, 4 %162 = bitcast i32 %161 to float %163 = bitcast float %162 to i32 %164 = add i32 1, %163 %165 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %164 %166 = load <4 x float> addrspace(8)* %165 %167 = extractelement <4 x float> %166, i32 0 %168 = fmul float %167, %5 %169 = fadd float %168, %43 %170 = add i32 1, %163 %171 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %170 %172 = load <4 x float> addrspace(8)* %171 %173 = extractelement <4 x float> %172, i32 1 %174 = fmul float %173, %5 %175 = fadd float %174, %49 %176 = add i32 1, %163 %177 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %176 %178 = load <4 x float> addrspace(8)* %177 %179 = extractelement <4 x float> %178, i32 2 %180 = fmul float %179, %5 %181 = fadd float %180, %55 %182 = add i32 1, %163 %183 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %182 %184 = load <4 x float> addrspace(8)* %183 %185 = extractelement <4 x float> %184, i32 3 %186 = fmul float %185, %5 %187 = fadd float %186, %61 %188 = bitcast float %temp36.1 to i32 %189 = mul i32 %188, 4 %190 = bitcast i32 %189 to float %191 = bitcast float %190 to i32 %192 = add i32 2, %191 %193 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %192 %194 = load <4 x float> addrspace(8)* %193 %195 = extractelement <4 x float> %194, i32 0 %196 = fmul float %195, %5 %197 = fadd float %196, %71 %198 = add i32 2, %191 %199 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %198 %200 = load <4 x float> addrspace(8)* %199 %201 = extractelement <4 x float> %200, i32 1 %202 = fmul float %201, %5 %203 = fadd float %202, %77 %204 = add i32 2, %191 %205 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %204 %206 = load <4 x float> addrspace(8)* %205 %207 = extractelement <4 x float> %206, i32 2 %208 = fmul float %207, %5 %209 = fadd float %208, %83 %210 = add i32 2, %191 %211 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %210 %212 = load <4 x float> addrspace(8)* %211 %213 = extractelement <4 x float> %212, i32 3 %214 = fmul float %213, %5 %215 = fadd float %214, %89 %216 = bitcast float %temp36.1 to i32 %217 = mul i32 %216, 4 %218 = bitcast i32 %217 to float %219 = bitcast float %218 to i32 %220 = add i32 3, %219 %221 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %220 %222 = load <4 x float> addrspace(8)* %221 %223 = extractelement <4 x float> %222, i32 0 %224 = fmul float %223, %5 %225 = fadd float %224, %99 %226 = add i32 3, %219 %227 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %226 %228 = load <4 x float> addrspace(8)* %227 %229 = extractelement <4 x float> %228, i32 1 %230 = fmul float %229, %5 %231 = fadd float %230, %105 %232 = add i32 3, %219 %233 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %232 %234 = load <4 x float> addrspace(8)* %233 %235 = extractelement <4 x float> %234, i32 2 %236 = fmul float %235, %5 %237 = fadd float %236, %111 %238 = add i32 3, %219 %239 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %238 %240 = load <4 x float> addrspace(8)* %239 %241 = extractelement <4 x float> %240, i32 3 %242 = fmul float %241, %5 %243 = fadd float %242, %117 %244 = bitcast float %temp36.1 to i32 %245 = mul i32 %244, 4 %246 = bitcast i32 %245 to float %247 = bitcast float %246 to i32 %248 = add i32 4, %247 %249 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %248 %250 = load <4 x float> addrspace(8)* %249 %251 = extractelement <4 x float> %250, i32 0 %252 = fmul float %251, %5 %253 = fadd float %252, %127 %254 = add i32 4, %247 %255 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %254 %256 = load <4 x float> addrspace(8)* %255 %257 = extractelement <4 x float> %256, i32 1 %258 = fmul float %257, %5 %259 = fadd float %258, %133 %260 = add i32 4, %247 %261 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %260 %262 = load <4 x float> addrspace(8)* %261 %263 = extractelement <4 x float> %262, i32 2 %264 = fmul float %263, %5 %265 = fadd float %264, %139 %266 = add i32 4, %247 %267 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %266 %268 = load <4 x float> addrspace(8)* %267 %269 = extractelement <4 x float> %268, i32 3 %270 = fmul float %269, %5 %271 = fadd float %270, %145 %272 = fptosi float %2 to i32 %273 = bitcast i32 %272 to float %274 = bitcast float %273 to i32 %275 = icmp slt i32 %274, 0 %276 = sext i1 %275 to i32 %277 = bitcast i32 %276 to float %278 = bitcast float %277 to i32 %279 = icmp ne i32 %278, 0 br i1 %279, label %ENDIF129, label %ELSE131 ELSE131: ; preds = %ENDIF123 %280 = bitcast float %273 to i32 %281 = icmp slt i32 2, %280 %282 = sext i1 %281 to i32 %283 = bitcast i32 %282 to float %284 = bitcast float %283 to i32 %285 = icmp ne i32 %284, 0 %.142 = select i1 %285, float 0,000000e+00, float %273 br label %ENDIF129 ENDIF129: ; preds = %ENDIF123, %ELSE131 %temp36.2 = phi float [ %.142, %ELSE131 ], [ 0,000000e+00, %ENDIF123 ] %286 = bitcast float %temp36.2 to i32 %287 = mul i32 %286, 4 %288 = bitcast i32 %287 to float %289 = bitcast float %288 to i32 %290 = add i32 1, %289 %291 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %290 %292 = load <4 x float> addrspace(8)* %291 %293 = extractelement <4 x float> %292, i32 0 %294 = fmul float %293, %6 %295 = fadd float %294, %169 %296 = add i32 1, %289 %297 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %296 %298 = load <4 x float> addrspace(8)* %297 %299 = extractelement <4 x float> %298, i32 1 %300 = fmul float %299, %6 %301 = fadd float %300, %175 %302 = add i32 1, %289 %303 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %302 %304 = load <4 x float> addrspace(8)* %303 %305 = extractelement <4 x float> %304, i32 2 %306 = fmul float %305, %6 %307 = fadd float %306, %181 %308 = add i32 1, %289 %309 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %308 %310 = load <4 x float> addrspace(8)* %309 %311 = extractelement <4 x float> %310, i32 3 %312 = fmul float %311, %6 %313 = fadd float %312, %187 %314 = bitcast float %temp36.2 to i32 %315 = mul i32 %314, 4 %316 = bitcast i32 %315 to float %317 = bitcast float %316 to i32 %318 = add i32 2, %317 %319 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %318 %320 = load <4 x float> addrspace(8)* %319 %321 = extractelement <4 x float> %320, i32 0 %322 = fmul float %321, %6 %323 = fadd float %322, %197 %324 = add i32 2, %317 %325 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %324 %326 = load <4 x float> addrspace(8)* %325 %327 = extractelement <4 x float> %326, i32 1 %328 = fmul float %327, %6 %329 = fadd float %328, %203 %330 = add i32 2, %317 %331 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %330 %332 = load <4 x float> addrspace(8)* %331 %333 = extractelement <4 x float> %332, i32 2 %334 = fmul float %333, %6 %335 = fadd float %334, %209 %336 = add i32 2, %317 %337 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %336 %338 = load <4 x float> addrspace(8)* %337 %339 = extractelement <4 x float> %338, i32 3 %340 = fmul float %339, %6 %341 = fadd float %340, %215 %342 = bitcast float %temp36.2 to i32 %343 = mul i32 %342, 4 %344 = bitcast i32 %343 to float %345 = bitcast float %344 to i32 %346 = add i32 3, %345 %347 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %346 %348 = load <4 x float> addrspace(8)* %347 %349 = extractelement <4 x float> %348, i32 0 %350 = fmul float %349, %6 %351 = fadd float %350, %225 %352 = add i32 3, %345 %353 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %352 %354 = load <4 x float> addrspace(8)* %353 %355 = extractelement <4 x float> %354, i32 1 %356 = fmul float %355, %6 %357 = fadd float %356, %231 %358 = add i32 3, %345 %359 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %358 %360 = load <4 x float> addrspace(8)* %359 %361 = extractelement <4 x float> %360, i32 2 %362 = fmul float %361, %6 %363 = fadd float %362, %237 %364 = add i32 3, %345 %365 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %364 %366 = load <4 x float> addrspace(8)* %365 %367 = extractelement <4 x float> %366, i32 3 %368 = fmul float %367, %6 %369 = fadd float %368, %243 %370 = bitcast float %temp36.2 to i32 %371 = mul i32 %370, 4 %372 = bitcast i32 %371 to float %373 = bitcast float %372 to i32 %374 = add i32 4, %373 %375 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %374 %376 = load <4 x float> addrspace(8)* %375 %377 = extractelement <4 x float> %376, i32 0 %378 = fmul float %377, %6 %379 = fadd float %378, %253 %380 = add i32 4, %373 %381 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %380 %382 = load <4 x float> addrspace(8)* %381 %383 = extractelement <4 x float> %382, i32 1 %384 = fmul float %383, %6 %385 = fadd float %384, %259 %386 = add i32 4, %373 %387 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %386 %388 = load <4 x float> addrspace(8)* %387 %389 = extractelement <4 x float> %388, i32 2 %390 = fmul float %389, %6 %391 = fadd float %390, %265 %392 = add i32 4, %373 %393 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %392 %394 = load <4 x float> addrspace(8)* %393 %395 = extractelement <4 x float> %394, i32 3 %396 = fmul float %395, %6 %397 = fadd float %396, %271 %398 = fptosi float %3 to i32 %399 = bitcast i32 %398 to float %400 = bitcast float %399 to i32 %401 = icmp slt i32 %400, 0 %402 = sext i1 %401 to i32 %403 = bitcast i32 %402 to float %404 = bitcast float %403 to i32 %405 = icmp ne i32 %404, 0 br i1 %405, label %ENDIF135, label %ELSE137 ELSE137: ; preds = %ENDIF129 %406 = bitcast float %399 to i32 %407 = icmp slt i32 2, %406 %408 = sext i1 %407 to i32 %409 = bitcast i32 %408 to float %410 = bitcast float %409 to i32 %411 = icmp ne i32 %410, 0 %.143 = select i1 %411, float 0,000000e+00, float %399 br label %ENDIF135 ENDIF135: ; preds = %ENDIF129, %ELSE137 %temp36.3 = phi float [ %.143, %ELSE137 ], [ 0,000000e+00, %ENDIF129 ] %412 = bitcast float %temp36.3 to i32 %413 = mul i32 %412, 4 %414 = bitcast i32 %413 to float %415 = bitcast float %414 to i32 %416 = add i32 1, %415 %417 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %416 %418 = load <4 x float> addrspace(8)* %417 %419 = extractelement <4 x float> %418, i32 0 %420 = fmul float %419, %7 %421 = fadd float %420, %295 %422 = add i32 1, %415 %423 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %422 %424 = load <4 x float> addrspace(8)* %423 %425 = extractelement <4 x float> %424, i32 1 %426 = fmul float %425, %7 %427 = fadd float %426, %301 %428 = add i32 1, %415 %429 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %428 %430 = load <4 x float> addrspace(8)* %429 %431 = extractelement <4 x float> %430, i32 2 %432 = fmul float %431, %7 %433 = fadd float %432, %307 %434 = add i32 1, %415 %435 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %434 %436 = load <4 x float> addrspace(8)* %435 %437 = extractelement <4 x float> %436, i32 3 %438 = fmul float %437, %7 %439 = fadd float %438, %313 %440 = bitcast float %temp36.3 to i32 %441 = mul i32 %440, 4 %442 = bitcast i32 %441 to float %443 = bitcast float %442 to i32 %444 = add i32 2, %443 %445 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %444 %446 = load <4 x float> addrspace(8)* %445 %447 = extractelement <4 x float> %446, i32 0 %448 = fmul float %447, %7 %449 = fadd float %448, %323 %450 = add i32 2, %443 %451 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %450 %452 = load <4 x float> addrspace(8)* %451 %453 = extractelement <4 x float> %452, i32 1 %454 = fmul float %453, %7 %455 = fadd float %454, %329 %456 = add i32 2, %443 %457 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %456 %458 = load <4 x float> addrspace(8)* %457 %459 = extractelement <4 x float> %458, i32 2 %460 = fmul float %459, %7 %461 = fadd float %460, %335 %462 = add i32 2, %443 %463 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %462 %464 = load <4 x float> addrspace(8)* %463 %465 = extractelement <4 x float> %464, i32 3 %466 = fmul float %465, %7 %467 = fadd float %466, %341 %468 = bitcast float %temp36.3 to i32 %469 = mul i32 %468, 4 %470 = bitcast i32 %469 to float %471 = bitcast float %470 to i32 %472 = add i32 3, %471 %473 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %472 %474 = load <4 x float> addrspace(8)* %473 %475 = extractelement <4 x float> %474, i32 0 %476 = fmul float %475, %7 %477 = fadd float %476, %351 %478 = add i32 3, %471 %479 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %478 %480 = load <4 x float> addrspace(8)* %479 %481 = extractelement <4 x float> %480, i32 1 %482 = fmul float %481, %7 %483 = fadd float %482, %357 %484 = add i32 3, %471 %485 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %484 %486 = load <4 x float> addrspace(8)* %485 %487 = extractelement <4 x float> %486, i32 2 %488 = fmul float %487, %7 %489 = fadd float %488, %363 %490 = add i32 3, %471 %491 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %490 %492 = load <4 x float> addrspace(8)* %491 %493 = extractelement <4 x float> %492, i32 3 %494 = fmul float %493, %7 %495 = fadd float %494, %369 %496 = bitcast float %temp36.3 to i32 %497 = mul i32 %496, 4 %498 = bitcast i32 %497 to float %499 = bitcast float %498 to i32 %500 = add i32 4, %499 %501 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %500 %502 = load <4 x float> addrspace(8)* %501 %503 = extractelement <4 x float> %502, i32 0 %504 = fmul float %503, %7 %505 = fadd float %504, %379 %506 = add i32 4, %499 %507 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %506 %508 = load <4 x float> addrspace(8)* %507 %509 = extractelement <4 x float> %508, i32 1 %510 = fmul float %509, %7 %511 = fadd float %510, %385 %512 = add i32 4, %499 %513 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %512 %514 = load <4 x float> addrspace(8)* %513 %515 = extractelement <4 x float> %514, i32 2 %516 = fmul float %515, %7 %517 = fadd float %516, %391 %518 = add i32 4, %499 %519 = getelementptr [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 %518 %520 = load <4 x float> addrspace(8)* %519 %521 = extractelement <4 x float> %520, i32 3 %522 = fmul float %521, %7 %523 = fadd float %522, %397 %524 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %525 = extractelement <4 x float> %524, i32 0 %526 = fmul float %525, %477 %527 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %528 = extractelement <4 x float> %527, i32 1 %529 = fmul float %528, %477 %530 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %531 = extractelement <4 x float> %530, i32 2 %532 = fmul float %531, %477 %533 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %534 = extractelement <4 x float> %533, i32 3 %535 = fmul float %534, %477 %536 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %537 = extractelement <4 x float> %536, i32 0 %538 = fmul float %537, %483 %539 = fadd float %538, %526 %540 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %541 = extractelement <4 x float> %540, i32 1 %542 = fmul float %541, %483 %543 = fadd float %542, %529 %544 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %545 = extractelement <4 x float> %544, i32 2 %546 = fmul float %545, %483 %547 = fadd float %546, %532 %548 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %549 = extractelement <4 x float> %548, i32 3 %550 = fmul float %549, %483 %551 = fadd float %550, %535 %552 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %553 = extractelement <4 x float> %552, i32 0 %554 = fmul float %553, %489 %555 = fadd float %554, %539 %556 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %557 = extractelement <4 x float> %556, i32 1 %558 = fmul float %557, %489 %559 = fadd float %558, %543 %560 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %561 = extractelement <4 x float> %560, i32 2 %562 = fmul float %561, %489 %563 = fadd float %562, %547 %564 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %565 = extractelement <4 x float> %564, i32 3 %566 = fmul float %565, %489 %567 = fadd float %566, %551 %568 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %569 = extractelement <4 x float> %568, i32 0 %570 = fmul float %569, %495 %571 = fadd float %570, %555 %572 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %573 = extractelement <4 x float> %572, i32 1 %574 = fmul float %573, %495 %575 = fadd float %574, %559 %576 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %577 = extractelement <4 x float> %576, i32 2 %578 = fmul float %577, %495 %579 = fadd float %578, %563 %580 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %581 = extractelement <4 x float> %580, i32 3 %582 = fmul float %581, %495 %583 = fadd float %582, %567 %584 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %585 = extractelement <4 x float> %584, i32 0 %586 = fmul float %585, %449 %587 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %588 = extractelement <4 x float> %587, i32 1 %589 = fmul float %588, %449 %590 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %591 = extractelement <4 x float> %590, i32 2 %592 = fmul float %591, %449 %593 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %594 = extractelement <4 x float> %593, i32 3 %595 = fmul float %594, %449 %596 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %597 = extractelement <4 x float> %596, i32 0 %598 = fmul float %597, %455 %599 = fadd float %598, %586 %600 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %601 = extractelement <4 x float> %600, i32 1 %602 = fmul float %601, %455 %603 = fadd float %602, %589 %604 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %605 = extractelement <4 x float> %604, i32 2 %606 = fmul float %605, %455 %607 = fadd float %606, %592 %608 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %609 = extractelement <4 x float> %608, i32 3 %610 = fmul float %609, %455 %611 = fadd float %610, %595 %612 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %613 = extractelement <4 x float> %612, i32 0 %614 = fmul float %613, %461 %615 = fadd float %614, %599 %616 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %617 = extractelement <4 x float> %616, i32 1 %618 = fmul float %617, %461 %619 = fadd float %618, %603 %620 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %621 = extractelement <4 x float> %620, i32 2 %622 = fmul float %621, %461 %623 = fadd float %622, %607 %624 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %625 = extractelement <4 x float> %624, i32 3 %626 = fmul float %625, %461 %627 = fadd float %626, %611 %628 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %629 = extractelement <4 x float> %628, i32 0 %630 = fmul float %629, %467 %631 = fadd float %630, %615 %632 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %633 = extractelement <4 x float> %632, i32 1 %634 = fmul float %633, %467 %635 = fadd float %634, %619 %636 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %637 = extractelement <4 x float> %636, i32 2 %638 = fmul float %637, %467 %639 = fadd float %638, %623 %640 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %641 = extractelement <4 x float> %640, i32 3 %642 = fmul float %641, %467 %643 = fadd float %642, %627 %644 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %645 = extractelement <4 x float> %644, i32 0 %646 = fmul float %645, %421 %647 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %648 = extractelement <4 x float> %647, i32 1 %649 = fmul float %648, %421 %650 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %651 = extractelement <4 x float> %650, i32 2 %652 = fmul float %651, %421 %653 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %654 = extractelement <4 x float> %653, i32 3 %655 = fmul float %654, %421 %656 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %657 = extractelement <4 x float> %656, i32 0 %658 = fmul float %657, %427 %659 = fadd float %658, %646 %660 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %661 = extractelement <4 x float> %660, i32 1 %662 = fmul float %661, %427 %663 = fadd float %662, %649 %664 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %665 = extractelement <4 x float> %664, i32 2 %666 = fmul float %665, %427 %667 = fadd float %666, %652 %668 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %669 = extractelement <4 x float> %668, i32 3 %670 = fmul float %669, %427 %671 = fadd float %670, %655 %672 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %673 = extractelement <4 x float> %672, i32 0 %674 = fmul float %673, %433 %675 = fadd float %674, %659 %676 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %677 = extractelement <4 x float> %676, i32 1 %678 = fmul float %677, %433 %679 = fadd float %678, %663 %680 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %681 = extractelement <4 x float> %680, i32 2 %682 = fmul float %681, %433 %683 = fadd float %682, %667 %684 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %685 = extractelement <4 x float> %684, i32 3 %686 = fmul float %685, %433 %687 = fadd float %686, %671 %688 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %689 = extractelement <4 x float> %688, i32 0 %690 = fmul float %689, %439 %691 = fadd float %690, %675 %692 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %693 = extractelement <4 x float> %692, i32 1 %694 = fmul float %693, %439 %695 = fadd float %694, %679 %696 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %697 = extractelement <4 x float> %696, i32 2 %698 = fmul float %697, %439 %699 = fadd float %698, %683 %700 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %701 = extractelement <4 x float> %700, i32 3 %702 = fmul float %701, %439 %703 = fadd float %702, %687 %704 = fmul float %691, %16 %705 = fmul float %695, %16 %706 = fmul float %699, %16 %707 = fmul float %703, %16 %708 = fmul float %631, %17 %709 = fadd float %708, %704 %710 = fmul float %635, %17 %711 = fadd float %710, %705 %712 = fmul float %639, %17 %713 = fadd float %712, %706 %714 = fmul float %643, %17 %715 = fadd float %714, %707 %716 = fmul float %571, %18 %717 = fadd float %716, %709 %718 = fmul float %575, %18 %719 = fadd float %718, %711 %720 = fmul float %579, %18 %721 = fadd float %720, %713 %722 = fmul float %583, %18 %723 = fadd float %722, %715 %724 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %725 = extractelement <4 x float> %724, i32 0 %726 = fmul float %725, %505 %727 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %728 = extractelement <4 x float> %727, i32 1 %729 = fmul float %728, %505 %730 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %731 = extractelement <4 x float> %730, i32 2 %732 = fmul float %731, %505 %733 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %734 = extractelement <4 x float> %733, i32 3 %735 = fmul float %734, %505 %736 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %737 = extractelement <4 x float> %736, i32 0 %738 = fmul float %737, %511 %739 = fadd float %738, %726 %740 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %741 = extractelement <4 x float> %740, i32 1 %742 = fmul float %741, %511 %743 = fadd float %742, %729 %744 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %745 = extractelement <4 x float> %744, i32 2 %746 = fmul float %745, %511 %747 = fadd float %746, %732 %748 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %749 = extractelement <4 x float> %748, i32 3 %750 = fmul float %749, %511 %751 = fadd float %750, %735 %752 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %753 = extractelement <4 x float> %752, i32 0 %754 = fmul float %753, %517 %755 = fadd float %754, %739 %756 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %757 = extractelement <4 x float> %756, i32 1 %758 = fmul float %757, %517 %759 = fadd float %758, %743 %760 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %761 = extractelement <4 x float> %760, i32 2 %762 = fmul float %761, %517 %763 = fadd float %762, %747 %764 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %765 = extractelement <4 x float> %764, i32 3 %766 = fmul float %765, %517 %767 = fadd float %766, %751 %768 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %769 = extractelement <4 x float> %768, i32 0 %770 = fmul float %769, %523 %771 = fadd float %770, %755 %772 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %773 = extractelement <4 x float> %772, i32 1 %774 = fmul float %773, %523 %775 = fadd float %774, %759 %776 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %777 = extractelement <4 x float> %776, i32 2 %778 = fmul float %777, %523 %779 = fadd float %778, %763 %780 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %781 = extractelement <4 x float> %780, i32 3 %782 = fmul float %781, %523 %783 = fadd float %782, %767 %784 = fadd float %717, %771 %785 = fadd float %719, %775 %786 = fadd float %721, %779 %787 = fadd float %723, %783 %788 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %789 = extractelement <4 x float> %788, i32 0 %790 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %791 = extractelement <4 x float> %790, i32 0 %792 = fmul float %789, %791 %793 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %794 = extractelement <4 x float> %793, i32 1 %795 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %796 = extractelement <4 x float> %795, i32 0 %797 = fmul float %794, %796 %798 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %799 = extractelement <4 x float> %798, i32 2 %800 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %801 = extractelement <4 x float> %800, i32 0 %802 = fmul float %799, %801 %803 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %804 = extractelement <4 x float> %803, i32 3 %805 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %806 = extractelement <4 x float> %805, i32 0 %807 = fmul float %804, %806 %808 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %809 = extractelement <4 x float> %808, i32 0 %810 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %811 = extractelement <4 x float> %810, i32 1 %812 = fmul float %809, %811 %813 = fadd float %812, %792 %814 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %815 = extractelement <4 x float> %814, i32 1 %816 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %817 = extractelement <4 x float> %816, i32 1 %818 = fmul float %815, %817 %819 = fadd float %818, %797 %820 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %821 = extractelement <4 x float> %820, i32 2 %822 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %823 = extractelement <4 x float> %822, i32 1 %824 = fmul float %821, %823 %825 = fadd float %824, %802 %826 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %827 = extractelement <4 x float> %826, i32 3 %828 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %829 = extractelement <4 x float> %828, i32 1 %830 = fmul float %827, %829 %831 = fadd float %830, %807 %832 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %833 = extractelement <4 x float> %832, i32 0 %834 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %835 = extractelement <4 x float> %834, i32 2 %836 = fmul float %833, %835 %837 = fadd float %836, %813 %838 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %839 = extractelement <4 x float> %838, i32 1 %840 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %841 = extractelement <4 x float> %840, i32 2 %842 = fmul float %839, %841 %843 = fadd float %842, %819 %844 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %845 = extractelement <4 x float> %844, i32 2 %846 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %847 = extractelement <4 x float> %846, i32 2 %848 = fmul float %845, %847 %849 = fadd float %848, %825 %850 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %851 = extractelement <4 x float> %850, i32 3 %852 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %853 = extractelement <4 x float> %852, i32 2 %854 = fmul float %851, %853 %855 = fadd float %854, %831 %856 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %857 = extractelement <4 x float> %856, i32 0 %858 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %859 = extractelement <4 x float> %858, i32 3 %860 = fmul float %857, %859 %861 = fadd float %860, %837 %862 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %863 = extractelement <4 x float> %862, i32 1 %864 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %865 = extractelement <4 x float> %864, i32 3 %866 = fmul float %863, %865 %867 = fadd float %866, %843 %868 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %869 = extractelement <4 x float> %868, i32 2 %870 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %871 = extractelement <4 x float> %870, i32 3 %872 = fmul float %869, %871 %873 = fadd float %872, %849 %874 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %875 = extractelement <4 x float> %874, i32 3 %876 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) %877 = extractelement <4 x float> %876, i32 3 %878 = fmul float %875, %877 %879 = fadd float %878, %855 %880 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %881 = extractelement <4 x float> %880, i32 0 %882 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %883 = extractelement <4 x float> %882, i32 0 %884 = fmul float %881, %883 %885 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %886 = extractelement <4 x float> %885, i32 1 %887 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %888 = extractelement <4 x float> %887, i32 0 %889 = fmul float %886, %888 %890 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %891 = extractelement <4 x float> %890, i32 2 %892 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %893 = extractelement <4 x float> %892, i32 0 %894 = fmul float %891, %893 %895 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %896 = extractelement <4 x float> %895, i32 3 %897 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %898 = extractelement <4 x float> %897, i32 0 %899 = fmul float %896, %898 %900 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %901 = extractelement <4 x float> %900, i32 0 %902 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %903 = extractelement <4 x float> %902, i32 1 %904 = fmul float %901, %903 %905 = fadd float %904, %884 %906 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %907 = extractelement <4 x float> %906, i32 1 %908 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %909 = extractelement <4 x float> %908, i32 1 %910 = fmul float %907, %909 %911 = fadd float %910, %889 %912 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %913 = extractelement <4 x float> %912, i32 2 %914 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %915 = extractelement <4 x float> %914, i32 1 %916 = fmul float %913, %915 %917 = fadd float %916, %894 %918 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %919 = extractelement <4 x float> %918, i32 3 %920 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %921 = extractelement <4 x float> %920, i32 1 %922 = fmul float %919, %921 %923 = fadd float %922, %899 %924 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %925 = extractelement <4 x float> %924, i32 0 %926 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %927 = extractelement <4 x float> %926, i32 2 %928 = fmul float %925, %927 %929 = fadd float %928, %905 %930 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %931 = extractelement <4 x float> %930, i32 1 %932 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %933 = extractelement <4 x float> %932, i32 2 %934 = fmul float %931, %933 %935 = fadd float %934, %911 %936 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %937 = extractelement <4 x float> %936, i32 2 %938 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %939 = extractelement <4 x float> %938, i32 2 %940 = fmul float %937, %939 %941 = fadd float %940, %917 %942 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %943 = extractelement <4 x float> %942, i32 3 %944 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %945 = extractelement <4 x float> %944, i32 2 %946 = fmul float %943, %945 %947 = fadd float %946, %923 %948 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %949 = extractelement <4 x float> %948, i32 0 %950 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %951 = extractelement <4 x float> %950, i32 3 %952 = fmul float %949, %951 %953 = fadd float %952, %929 %954 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %955 = extractelement <4 x float> %954, i32 1 %956 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %957 = extractelement <4 x float> %956, i32 3 %958 = fmul float %955, %957 %959 = fadd float %958, %935 %960 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %961 = extractelement <4 x float> %960, i32 2 %962 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %963 = extractelement <4 x float> %962, i32 3 %964 = fmul float %961, %963 %965 = fadd float %964, %941 %966 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %967 = extractelement <4 x float> %966, i32 3 %968 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) %969 = extractelement <4 x float> %968, i32 3 %970 = fmul float %967, %969 %971 = fadd float %970, %947 %972 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %973 = extractelement <4 x float> %972, i32 0 %974 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %975 = extractelement <4 x float> %974, i32 0 %976 = fmul float %973, %975 %977 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %978 = extractelement <4 x float> %977, i32 1 %979 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %980 = extractelement <4 x float> %979, i32 0 %981 = fmul float %978, %980 %982 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %983 = extractelement <4 x float> %982, i32 2 %984 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %985 = extractelement <4 x float> %984, i32 0 %986 = fmul float %983, %985 %987 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %988 = extractelement <4 x float> %987, i32 3 %989 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %990 = extractelement <4 x float> %989, i32 0 %991 = fmul float %988, %990 %992 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %993 = extractelement <4 x float> %992, i32 0 %994 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %995 = extractelement <4 x float> %994, i32 1 %996 = fmul float %993, %995 %997 = fadd float %996, %976 %998 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %999 = extractelement <4 x float> %998, i32 1 %1000 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %1001 = extractelement <4 x float> %1000, i32 1 %1002 = fmul float %999, %1001 %1003 = fadd float %1002, %981 %1004 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %1005 = extractelement <4 x float> %1004, i32 2 %1006 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %1007 = extractelement <4 x float> %1006, i32 1 %1008 = fmul float %1005, %1007 %1009 = fadd float %1008, %986 %1010 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %1011 = extractelement <4 x float> %1010, i32 3 %1012 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %1013 = extractelement <4 x float> %1012, i32 1 %1014 = fmul float %1011, %1013 %1015 = fadd float %1014, %991 %1016 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %1017 = extractelement <4 x float> %1016, i32 0 %1018 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %1019 = extractelement <4 x float> %1018, i32 2 %1020 = fmul float %1017, %1019 %1021 = fadd float %1020, %997 %1022 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %1023 = extractelement <4 x float> %1022, i32 1 %1024 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %1025 = extractelement <4 x float> %1024, i32 2 %1026 = fmul float %1023, %1025 %1027 = fadd float %1026, %1003 %1028 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %1029 = extractelement <4 x float> %1028, i32 2 %1030 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %1031 = extractelement <4 x float> %1030, i32 2 %1032 = fmul float %1029, %1031 %1033 = fadd float %1032, %1009 %1034 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %1035 = extractelement <4 x float> %1034, i32 3 %1036 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %1037 = extractelement <4 x float> %1036, i32 2 %1038 = fmul float %1035, %1037 %1039 = fadd float %1038, %1015 %1040 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %1041 = extractelement <4 x float> %1040, i32 0 %1042 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %1043 = extractelement <4 x float> %1042, i32 3 %1044 = fmul float %1041, %1043 %1045 = fadd float %1044, %1021 %1046 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %1047 = extractelement <4 x float> %1046, i32 1 %1048 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %1049 = extractelement <4 x float> %1048, i32 3 %1050 = fmul float %1047, %1049 %1051 = fadd float %1050, %1027 %1052 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %1053 = extractelement <4 x float> %1052, i32 2 %1054 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %1055 = extractelement <4 x float> %1054, i32 3 %1056 = fmul float %1053, %1055 %1057 = fadd float %1056, %1033 %1058 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %1059 = extractelement <4 x float> %1058, i32 3 %1060 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) %1061 = extractelement <4 x float> %1060, i32 3 %1062 = fmul float %1059, %1061 %1063 = fadd float %1062, %1039 %1064 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %1065 = extractelement <4 x float> %1064, i32 0 %1066 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1067 = extractelement <4 x float> %1066, i32 0 %1068 = fmul float %1065, %1067 %1069 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %1070 = extractelement <4 x float> %1069, i32 1 %1071 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1072 = extractelement <4 x float> %1071, i32 0 %1073 = fmul float %1070, %1072 %1074 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %1075 = extractelement <4 x float> %1074, i32 2 %1076 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1077 = extractelement <4 x float> %1076, i32 0 %1078 = fmul float %1075, %1077 %1079 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) %1080 = extractelement <4 x float> %1079, i32 3 %1081 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1082 = extractelement <4 x float> %1081, i32 0 %1083 = fmul float %1080, %1082 %1084 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %1085 = extractelement <4 x float> %1084, i32 0 %1086 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1087 = extractelement <4 x float> %1086, i32 1 %1088 = fmul float %1085, %1087 %1089 = fadd float %1088, %1068 %1090 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %1091 = extractelement <4 x float> %1090, i32 1 %1092 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1093 = extractelement <4 x float> %1092, i32 1 %1094 = fmul float %1091, %1093 %1095 = fadd float %1094, %1073 %1096 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %1097 = extractelement <4 x float> %1096, i32 2 %1098 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1099 = extractelement <4 x float> %1098, i32 1 %1100 = fmul float %1097, %1099 %1101 = fadd float %1100, %1078 %1102 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) %1103 = extractelement <4 x float> %1102, i32 3 %1104 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1105 = extractelement <4 x float> %1104, i32 1 %1106 = fmul float %1103, %1105 %1107 = fadd float %1106, %1083 %1108 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %1109 = extractelement <4 x float> %1108, i32 0 %1110 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1111 = extractelement <4 x float> %1110, i32 2 %1112 = fmul float %1109, %1111 %1113 = fadd float %1112, %1089 %1114 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %1115 = extractelement <4 x float> %1114, i32 1 %1116 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1117 = extractelement <4 x float> %1116, i32 2 %1118 = fmul float %1115, %1117 %1119 = fadd float %1118, %1095 %1120 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %1121 = extractelement <4 x float> %1120, i32 2 %1122 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1123 = extractelement <4 x float> %1122, i32 2 %1124 = fmul float %1121, %1123 %1125 = fadd float %1124, %1101 %1126 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) %1127 = extractelement <4 x float> %1126, i32 3 %1128 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1129 = extractelement <4 x float> %1128, i32 2 %1130 = fmul float %1127, %1129 %1131 = fadd float %1130, %1107 %1132 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %1133 = extractelement <4 x float> %1132, i32 0 %1134 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1135 = extractelement <4 x float> %1134, i32 3 %1136 = fmul float %1133, %1135 %1137 = fadd float %1136, %1113 %1138 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %1139 = extractelement <4 x float> %1138, i32 1 %1140 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1141 = extractelement <4 x float> %1140, i32 3 %1142 = fmul float %1139, %1141 %1143 = fadd float %1142, %1119 %1144 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %1145 = extractelement <4 x float> %1144, i32 2 %1146 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1147 = extractelement <4 x float> %1146, i32 3 %1148 = fmul float %1145, %1147 %1149 = fadd float %1148, %1125 %1150 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) %1151 = extractelement <4 x float> %1150, i32 3 %1152 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) %1153 = extractelement <4 x float> %1152, i32 3 %1154 = fmul float %1151, %1153 %1155 = fadd float %1154, %1131 %1156 = fmul float %1137, %784 %1157 = fmul float %1143, %784 %1158 = fmul float %1149, %784 %1159 = fmul float %1155, %784 %1160 = fmul float %1045, %785 %1161 = fadd float %1160, %1156 %1162 = fmul float %1051, %785 %1163 = fadd float %1162, %1157 %1164 = fmul float %1057, %785 %1165 = fadd float %1164, %1158 %1166 = fmul float %1063, %785 %1167 = fadd float %1166, %1159 %1168 = fmul float %953, %786 %1169 = fadd float %1168, %1161 %1170 = fmul float %959, %786 %1171 = fadd float %1170, %1163 %1172 = fmul float %965, %786 %1173 = fadd float %1172, %1165 %1174 = fmul float %971, %786 %1175 = fadd float %1174, %1167 %1176 = fmul float %861, %787 %1177 = fadd float %1176, %1169 %1178 = fmul float %867, %787 %1179 = fadd float %1178, %1171 %1180 = fmul float %873, %787 %1181 = fadd float %1180, %1173 %1182 = fmul float %879, %787 %1183 = fadd float %1182, %1175 %1184 = load <4 x float> addrspace(8)* null %1185 = extractelement <4 x float> %1184, i32 0 %1186 = load <4 x float> addrspace(8)* null %1187 = extractelement <4 x float> %1186, i32 1 %1188 = load <4 x float> addrspace(8)* null %1189 = extractelement <4 x float> %1188, i32 2 %1190 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %1191 = extractelement <4 x float> %1190, i32 0 %1192 = fmul float %1191, %477 %1193 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %1194 = extractelement <4 x float> %1193, i32 1 %1195 = fmul float %1194, %477 %1196 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %1197 = extractelement <4 x float> %1196, i32 2 %1198 = fmul float %1197, %477 %1199 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %1200 = extractelement <4 x float> %1199, i32 0 %1201 = fmul float %1200, %483 %1202 = fadd float %1201, %1192 %1203 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %1204 = extractelement <4 x float> %1203, i32 1 %1205 = fmul float %1204, %483 %1206 = fadd float %1205, %1195 %1207 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %1208 = extractelement <4 x float> %1207, i32 2 %1209 = fmul float %1208, %483 %1210 = fadd float %1209, %1198 %1211 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %1212 = extractelement <4 x float> %1211, i32 0 %1213 = fmul float %1212, %489 %1214 = fadd float %1213, %1202 %1215 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %1216 = extractelement <4 x float> %1215, i32 1 %1217 = fmul float %1216, %489 %1218 = fadd float %1217, %1206 %1219 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %1220 = extractelement <4 x float> %1219, i32 2 %1221 = fmul float %1220, %489 %1222 = fadd float %1221, %1210 %1223 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %1224 = extractelement <4 x float> %1223, i32 0 %1225 = fmul float %1224, %495 %1226 = fadd float %1225, %1214 %1227 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %1228 = extractelement <4 x float> %1227, i32 1 %1229 = fmul float %1228, %495 %1230 = fadd float %1229, %1218 %1231 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %1232 = extractelement <4 x float> %1231, i32 2 %1233 = fmul float %1232, %495 %1234 = fadd float %1233, %1222 %1235 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %1236 = extractelement <4 x float> %1235, i32 0 %1237 = fmul float %1236, %449 %1238 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %1239 = extractelement <4 x float> %1238, i32 1 %1240 = fmul float %1239, %449 %1241 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %1242 = extractelement <4 x float> %1241, i32 2 %1243 = fmul float %1242, %449 %1244 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %1245 = extractelement <4 x float> %1244, i32 0 %1246 = fmul float %1245, %455 %1247 = fadd float %1246, %1237 %1248 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %1249 = extractelement <4 x float> %1248, i32 1 %1250 = fmul float %1249, %455 %1251 = fadd float %1250, %1240 %1252 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %1253 = extractelement <4 x float> %1252, i32 2 %1254 = fmul float %1253, %455 %1255 = fadd float %1254, %1243 %1256 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %1257 = extractelement <4 x float> %1256, i32 0 %1258 = fmul float %1257, %461 %1259 = fadd float %1258, %1247 %1260 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %1261 = extractelement <4 x float> %1260, i32 1 %1262 = fmul float %1261, %461 %1263 = fadd float %1262, %1251 %1264 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %1265 = extractelement <4 x float> %1264, i32 2 %1266 = fmul float %1265, %461 %1267 = fadd float %1266, %1255 %1268 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %1269 = extractelement <4 x float> %1268, i32 0 %1270 = fmul float %1269, %467 %1271 = fadd float %1270, %1259 %1272 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %1273 = extractelement <4 x float> %1272, i32 1 %1274 = fmul float %1273, %467 %1275 = fadd float %1274, %1263 %1276 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %1277 = extractelement <4 x float> %1276, i32 2 %1278 = fmul float %1277, %467 %1279 = fadd float %1278, %1267 %1280 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %1281 = extractelement <4 x float> %1280, i32 0 %1282 = fmul float %1281, %421 %1283 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %1284 = extractelement <4 x float> %1283, i32 1 %1285 = fmul float %1284, %421 %1286 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %1287 = extractelement <4 x float> %1286, i32 2 %1288 = fmul float %1287, %421 %1289 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %1290 = extractelement <4 x float> %1289, i32 0 %1291 = fmul float %1290, %427 %1292 = fadd float %1291, %1282 %1293 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %1294 = extractelement <4 x float> %1293, i32 1 %1295 = fmul float %1294, %427 %1296 = fadd float %1295, %1285 %1297 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %1298 = extractelement <4 x float> %1297, i32 2 %1299 = fmul float %1298, %427 %1300 = fadd float %1299, %1288 %1301 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %1302 = extractelement <4 x float> %1301, i32 0 %1303 = fmul float %1302, %433 %1304 = fadd float %1303, %1292 %1305 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %1306 = extractelement <4 x float> %1305, i32 1 %1307 = fmul float %1306, %433 %1308 = fadd float %1307, %1296 %1309 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %1310 = extractelement <4 x float> %1309, i32 2 %1311 = fmul float %1310, %433 %1312 = fadd float %1311, %1300 %1313 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %1314 = extractelement <4 x float> %1313, i32 0 %1315 = fmul float %1314, %439 %1316 = fadd float %1315, %1304 %1317 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %1318 = extractelement <4 x float> %1317, i32 1 %1319 = fmul float %1318, %439 %1320 = fadd float %1319, %1308 %1321 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %1322 = extractelement <4 x float> %1321, i32 2 %1323 = fmul float %1322, %439 %1324 = fadd float %1323, %1312 %1325 = fmul float %1316, %12 %1326 = fmul float %1320, %12 %1327 = fmul float %1324, %12 %1328 = fmul float %1271, %13 %1329 = fadd float %1328, %1325 %1330 = fmul float %1275, %13 %1331 = fadd float %1330, %1326 %1332 = fmul float %1279, %13 %1333 = fadd float %1332, %1327 %1334 = fmul float %1226, %14 %1335 = fadd float %1334, %1329 %1336 = fmul float %1230, %14 %1337 = fadd float %1336, %1331 %1338 = fmul float %1234, %14 %1339 = fadd float %1338, %1333 %1340 = insertelement <4 x float> undef, float %1177, i32 0 %1341 = insertelement <4 x float> %1340, float %1179, i32 1 %1342 = insertelement <4 x float> %1341, float %1181, i32 2 %1343 = insertelement <4 x float> %1342, float %1183, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %1343, i32 60, i32 1) %1344 = insertelement <4 x float> undef, float %8, i32 0 %1345 = insertelement <4 x float> %1344, float %9, i32 1 %1346 = insertelement <4 x float> %1345, float %1185, i32 2 %1347 = insertelement <4 x float> %1346, float %1187, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %1347, i32 0, i32 2) %1348 = insertelement <4 x float> undef, float %1189, i32 0 %1349 = insertelement <4 x float> %1348, float %1335, i32 1 %1350 = insertelement <4 x float> %1349, float %1337, i32 2 %1351 = insertelement <4 x float> %1350, float %1339, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %1351, i32 1, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } ===== SHADER #55 =========================================== VS/RS880/R600 ===== ===== 750 dw ===== 22 gprs ===== 1 stack ======================================= 0000 00000000 89800000 CALL_FS @0 0002 00000030 a05c0000 ALU 24 @96 0096 00000003 40001910 1 z: MOV R0.z, R3.x 0098 80000403 60001910 w: MOV R0.w, R3.y 0100 800000f8 60601910 2 w: MOV R3.w, 0 0102 80000001 60806b10 3 t: FLT_TO_INT R4.w, R1.x 0104 801fac04 60a07010 4 t: ASHR_INT R5.w, R4.w, [0x0000001f 0].x 0106 0000001f 0108 801f0cfe 60a03d10 5 w: SETNE_INT R5.w, PV.w, 0 0110 801f0cfe 00004508 6 P x: PRED_SETNE_INT __.x, PV.w, 0 0112 c01fac04 60603b10 7 0 w: SETGT_INT R3.w, R4.w, [0x00000002 0].x 0114 00000002 0116 c1808c03 606380fd 8 0 w: CNDE_INT R3.w, R3.w, R4.w, [0x00000002 0].x 0118 00000002 0120 801fac03 60607210 9 t: LSHL_INT R3.w, R3.w, [0x00000006 0].x 0122 00000006 0124 801facfe 60803410 10 w: ADD_INT R4.w, PV.w, [0x00000040 0].x 0126 00000040 0128 001facfe 00207110 11 x: ADD __.x, R4.x, R0.x 0130 801fac03 60607110 t: OR_INT R3.x, PV.w, [0x00000003 0].x 0132 00000004 0134 801facfe 00603110 12 x: OR_INT R6.x, R3.w, [0x00000002 0].x 0136 00000003 0138 801fac03 00c03110 13 x: OR_INT R7.x, R3.w, 1 0140 00000002 00000000 14 w: MOV R5.w, 0 0004 00000010 80800c00 TEX 4 @32 0032 40070040 e8cd1009 00080000 VFETCH R9.xyzw, R7.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0036 40060040 e8cd100a 00080000 VFETCH R10.xyzw, R6.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0040 40030040 e8cd1007 00080000 VFETCH R7.xyzw, R3.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0044 40010040 e8cd100b 00080000 VFETCH R11.xyzw, R1.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0006 00000048 a0940000 ALU 38 @144 0144 800000f8 60a01910 15 w: MOV R5.w, 0 0146 0000440b 206280f8 16 y: MULADD_IEEE R3.y, R11.y, R2.x, 0 0148 0000400b 40c280f8 z: MULADD_IEEE R6.z, R11.x, R2.x, 0 0150 80004c07 606280f8 w: MULADD_IEEE R3.w, R7.w, R2.x, 0 0152 00004807 002280f8 17 x: MULADD_IEEE R1.x, R7.z, R2.x, 0 0154 00004407 210280f8 y: MULADD_IEEE R8.y, R7.y, R2.x, 0 0156 00004007 410280f8 z: MULADD_IEEE R8.z, R7.x, R2.x, 0 0158 80004c0a 608280f8 w: MULADD_IEEE R4.w, R10.w, R2.x, 0 0160 0000480a 00e280f8 18 x: MULADD_IEEE R7.x, R10.z, R2.x, 0 0162 0000440a 20e280f8 y: MULADD_IEEE R7.y, R10.y, R2.x, 0 0164 8000400a 406280f8 z: MULADD_IEEE R3.z, R10.x, R2.x, 0 0166 80000401 60c06b10 19 t: FLT_TO_INT R6.w, R1.y 0168 00004c09 006280f8 20 x: MULADD_IEEE R3.x, R9.w, R2.x, 0 0170 00004809 20c280f8 y: MULADD_IEEE R6.y, R9.z, R2.x, 0 0172 00004409 40e280f8 z: MULADD_IEEE R7.z, R9.y, R2.x, 0 0174 801fac06 60e87010 t: ASHR_INT R7.w, R6.w, [0x0000001f 0].x SCL_212 0176 0000001f 0178 00004009 00c280f8 21 x: MULADD_IEEE R6.x, R9.x, R2.x, 0 0180 0000480b 212280f8 y: MULADD_IEEE R9.y, R11.z, R2.x, 0 0182 00004c0b 412280f8 z: MULADD_IEEE R9.z, R11.w, R2.x, 0 0184 801f0cfe 60e83d10 w: SETNE_INT R7.w, PV.w, 0 VEC_120 0186 801f0cfe 00004508 22 P x: PRED_SETNE_INT __.x, PV.w, 0 0188 c01fac06 60a03b10 23 0 w: SETGT_INT R5.w, R6.w, [0x00000002 0].x 0190 00000002 0192 c180cc05 60a380fd 24 0 w: CNDE_INT R5.w, R5.w, R6.w, [0x00000002 0].x 0194 00000002 0196 801fac05 60a07210 25 t: LSHL_INT R5.w, R5.w, [0x00000006 0].x 0198 00000006 0200 801facfe 60c03410 26 w: ADD_INT R6.w, PV.w, [0x00000040 0].x 0202 00000040 0204 001facfe 00407110 27 x: ADD __.x, R4.x, R0.x 0206 801fac05 60a07110 t: OR_INT R8.x, PV.w, [0x00000003 0].x 0208 00000004 0210 801facfe 01003110 28 x: OR_INT R9.x, R5.w, [0x00000002 0].x 0212 00000003 0214 801fac05 01203110 29 x: OR_INT R10.x, R5.w, 1 0216 00000002 00000000 30 w: MOV R5.w, 0 0008 00000018 80800c00 TEX 4 @48 0048 400a0040 e8cd100a 00080000 VFETCH R10.xyzw, R10.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0052 40090040 e8cd100b 00080000 VFETCH R11.xyzw, R9.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0056 40080040 e8cd100d 00080000 VFETCH R13.xyzw, R8.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0060 40020040 e8cd100c 00080000 VFETCH R12.xyzw, R2.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0010 0000006e a0940000 ALU 38 @220 0220 800000f8 60a01910 31 w: MOV R5.w, 0 0222 0080440c 20628403 32 y: MULADD_IEEE R3.y, R12.y, R2.y, R3.y 0224 0080400c 40c28806 z: MULADD_IEEE R6.z, R12.x, R2.y, R6.z 0226 80804c0d 60628c03 w: MULADD_IEEE R3.w, R13.w, R2.y, R3.w 0228 0080480d 00228001 33 x: MULADD_IEEE R1.x, R13.z, R2.y, R1.x 0230 0080440d 20228408 y: MULADD_IEEE R1.y, R13.y, R2.y, R8.y 0232 0080400d 41028808 z: MULADD_IEEE R8.z, R13.x, R2.y, R8.z 0234 80804c0b 60828c04 w: MULADD_IEEE R4.w, R11.w, R2.y, R4.w 0236 0080480b 00428007 34 x: MULADD_IEEE R2.x, R11.z, R2.y, R7.x 0238 0080440b 20e28407 y: MULADD_IEEE R7.y, R11.y, R2.y, R7.y 0240 8080400b 40628803 z: MULADD_IEEE R3.z, R11.x, R2.y, R3.z 0242 80000801 60c06b10 35 t: FLT_TO_INT R6.w, R1.z 0244 00804c0a 00628003 36 x: MULADD_IEEE R3.x, R10.w, R2.y, R3.x 0246 0080480a 20c28406 y: MULADD_IEEE R6.y, R10.z, R2.y, R6.y 0248 0080440a 40e28807 z: MULADD_IEEE R7.z, R10.y, R2.y, R7.z 0250 801fac06 60e87010 t: ASHR_INT R7.w, R6.w, [0x0000001f 0].x SCL_212 0252 0000001f 0254 0080400a 00c28006 37 x: MULADD_IEEE R6.x, R10.x, R2.y, R6.x 0256 0080480c 21028409 y: MULADD_IEEE R8.y, R12.z, R2.y, R9.y 0258 00804c0c 41228809 z: MULADD_IEEE R9.z, R12.w, R2.y, R9.z 0260 801f0cfe 60e83d10 w: SETNE_INT R7.w, PV.w, 0 VEC_120 0262 801f0cfe 00004508 38 P x: PRED_SETNE_INT __.x, PV.w, 0 0264 c01fac06 60a03b10 39 0 w: SETGT_INT R5.w, R6.w, [0x00000002 0].x 0266 00000002 0268 c180cc05 60a380fd 40 0 w: CNDE_INT R5.w, R5.w, R6.w, [0x00000002 0].x 0270 00000002 0272 801fac05 60a07210 41 t: LSHL_INT R5.w, R5.w, [0x00000006 0].x 0274 00000006 0276 801facfe 60c03410 42 w: ADD_INT R6.w, PV.w, [0x00000040 0].x 0278 00000040 0280 001facfe 00e07110 43 x: ADD __.x, R4.x, R0.x 0282 801fac05 60a07110 t: OR_INT R8.x, PV.w, [0x00000003 0].x 0284 00000004 0286 801facfe 01003110 44 x: OR_INT R9.x, R5.w, [0x00000002 0].x 0288 00000003 0290 801fac05 01203110 45 x: OR_INT R10.x, R5.w, 1 0292 00000002 00000000 46 w: MOV R5.w, 0 0012 00000020 80800c00 TEX 4 @64 0064 400a0040 e8cd100a 00080000 VFETCH R10.xyzw, R10.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0068 40090040 e8cd100b 00080000 VFETCH R11.xyzw, R9.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0072 40080040 e8cd100d 00080000 VFETCH R13.xyzw, R8.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0076 40070040 e8cd100c 00080000 VFETCH R12.xyzw, R7.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0014 00000094 a0900000 ALU 37 @296 0296 800000f8 60a01910 47 w: MOV R5.w, 0 0298 0100440c 20628403 48 y: MULADD_IEEE R3.y, R12.y, R2.z, R3.y 0300 0100400c 40c28806 z: MULADD_IEEE R6.z, R12.x, R2.z, R6.z 0302 81004c0d 60628c03 w: MULADD_IEEE R3.w, R13.w, R2.z, R3.w 0304 0100480d 00228001 49 x: MULADD_IEEE R1.x, R13.z, R2.z, R1.x 0306 0100440d 20228401 y: MULADD_IEEE R1.y, R13.y, R2.z, R1.y 0308 0100400d 40228808 z: MULADD_IEEE R1.z, R13.x, R2.z, R8.z 0310 81004c0b 60828c04 w: MULADD_IEEE R4.w, R11.w, R2.z, R4.w 0312 0100480b 00428002 50 x: MULADD_IEEE R2.x, R11.z, R2.z, R2.x 0314 0100440b 20428407 y: MULADD_IEEE R2.y, R11.y, R2.z, R7.y 0316 8100400b 40628803 z: MULADD_IEEE R3.z, R11.x, R2.z, R3.z 0318 80000c01 60206b10 51 t: FLT_TO_INT R1.w, R1.w 0320 01004c0a 00628003 52 x: MULADD_IEEE R3.x, R10.w, R2.z, R3.x 0322 0100480a 20c28406 y: MULADD_IEEE R6.y, R10.z, R2.z, R6.y 0324 0100440a 40e28807 z: MULADD_IEEE R7.z, R10.y, R2.z, R7.z 0326 801fac01 60c87010 t: ASHR_INT R6.w, R1.w, [0x0000001f 0].x SCL_212 0328 0000001f 0330 0100400a 00c28006 53 x: MULADD_IEEE R6.x, R10.x, R2.z, R6.x 0332 0100480c 20e28408 y: MULADD_IEEE R7.y, R12.z, R2.z, R8.y 0334 01004c0c 40428809 z: MULADD_IEEE R2.z, R12.w, R2.z, R9.z 0336 801f0cfe 60c83d10 w: SETNE_INT R6.w, PV.w, 0 VEC_120 0338 801f0cfe 00004508 54 P x: PRED_SETNE_INT __.x, PV.w, 0 0340 c01fac01 60a03b10 55 0 w: SETGT_INT R5.w, R1.w, [0x00000002 0].x 0342 00000002 0344 c1802c05 60a380fd 56 0 w: CNDE_INT R5.w, R5.w, R1.w, [0x00000002 0].x 0346 00000002 0348 801fac05 60207210 57 t: LSHL_INT R1.w, R5.w, [0x00000002 0].x 0350 00000002 0352 001fac05 41007210 58 t: LSHL_INT R8.z, R5.w, [0x00000006 0].x 0354 809facfe 60283410 w: ADD_INT R1.w, PV.w, [0x00000004 0].y VEC_120 0356 00000006 0357 00000004 0358 001facfe 00e03010 59 x: AND_INT R7.x, PV.w, [0x0ffffffc 2,52435e-29].x 0360 809fa8fe 60207110 t: LSHR_INT R1.w, PV.z, [0x00000004 0].y 0362 0ffffffc 0363 00000004 0364 801f4cfe 01203110 60 x: OR_INT R9.x, PV.w, 1 0366 801fac01 01003110 61 x: OR_INT R8.x, R1.w, [0x00000002 0].x 0368 00000002 0016 00000028 80800800 TEX 3 @80 0080 40080040 e8cd1008 00080000 VFETCH R8.xyzw, R8.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0084 40090040 e8cd1009 00080000 VFETCH R9.xyzw, R9.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0088 40070040 e8cd100a 00080000 VFETCH R10.xyzw, R7.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0018 800000b9 a1280000 ALU 75 @370 KC0[CB0:0-31] 0370 00130091 41600210 62 z: MUL_IEEE R11.z, KC0[17].x, KC0[24].x 0372 80130491 60a00210 w: MUL_IEEE R5.w, KC0[17].y, KC0[24].x 0374 00930492 41828cfe 63 z: MULADD_IEEE R12.z, KC0[18].y, KC0[24].y, PV.w 0376 80930092 60a288fe w: MULADD_IEEE R5.w, KC0[18].x, KC0[24].y, PV.z 0378 01130093 41628cfe 64 z: MULADD_IEEE R11.z, KC0[19].x, KC0[24].z, PV.w 0380 81130493 60a288fe w: MULADD_IEEE R5.w, KC0[19].y, KC0[24].z, PV.z 0382 81930494 60a28cfe 65 w: MULADD_IEEE R5.w, KC0[20].y, KC0[24].w, PV.w 0384 00130c91 41800210 66 z: MUL_IEEE R12.z, KC0[17].w, KC0[24].x 0386 80130891 60c00210 w: MUL_IEEE R6.w, KC0[17].z, KC0[24].x 0388 00930892 41c28cfe 67 z: MULADD_IEEE R14.z, KC0[18].z, KC0[24].y, PV.w 0390 80930c92 60c288fe w: MULADD_IEEE R6.w, KC0[18].w, KC0[24].y, PV.z 0392 01130c93 41a28cfe 68 z: MULADD_IEEE R13.z, KC0[19].w, KC0[24].z, PV.w 0394 81130893 60c288fe w: MULADD_IEEE R6.w, KC0[19].z, KC0[24].z, PV.z 0396 01930894 41828cfe 69 z: MULADD_IEEE R12.z, KC0[20].z, KC0[24].w, PV.w 0398 81930c94 60c288fe w: MULADD_IEEE R6.w, KC0[20].w, KC0[24].w, PV.z 0400 0012e891 41a00210 70 z: MUL_IEEE R13.z, KC0[17].z, KC0[23].x 0402 8012ec91 60e00210 w: MUL_IEEE R7.w, KC0[17].w, KC0[23].x 0404 0092ec92 41c28cfe 71 z: MULADD_IEEE R14.z, KC0[18].w, KC0[23].y, PV.w 0406 8092e892 60e288fe w: MULADD_IEEE R7.w, KC0[18].z, KC0[23].y, PV.z 0408 0112e893 41a28cfe 72 z: MULADD_IEEE R13.z, KC0[19].z, KC0[23].z, PV.w 0410 8112ec93 60e288fe w: MULADD_IEEE R7.w, KC0[19].w, KC0[23].z, PV.z 0412 0012c891 41e00210 73 z: MUL_IEEE R15.z, KC0[17].z, KC0[22].x 0414 8012cc91 61600210 w: MUL_IEEE R11.w, KC0[17].w, KC0[22].x 0416 0092cc92 41c28cfe 74 z: MULADD_IEEE R14.z, KC0[18].w, KC0[22].y, PV.w 0418 8092c892 616288fe w: MULADD_IEEE R11.w, KC0[18].z, KC0[22].y, PV.z 0420 0112c893 41e28cfe 75 z: MULADD_IEEE R15.z, KC0[19].z, KC0[22].z, PV.w 0422 8112cc93 616288fe w: MULADD_IEEE R11.w, KC0[19].w, KC0[22].z, PV.z 0424 8192cc94 61628cfe 76 w: MULADD_IEEE R11.w, KC0[20].w, KC0[22].w, PV.w 0426 0012ac91 41c00210 77 z: MUL_IEEE R14.z, KC0[17].w, KC0[21].x 0428 8012a891 61800210 w: MUL_IEEE R12.w, KC0[17].z, KC0[21].x 0430 0092a892 42028cfe 78 z: MULADD_IEEE R16.z, KC0[18].z, KC0[21].y, PV.w 0432 8092ac92 618288fe w: MULADD_IEEE R12.w, KC0[18].w, KC0[21].y, PV.z 0434 0012e491 41c00210 79 z: MUL_IEEE R14.z, KC0[17].y, KC0[23].x 0436 8012e091 61a00210 w: MUL_IEEE R13.w, KC0[17].x, KC0[23].x 0438 0092e092 42428cfe 80 z: MULADD_IEEE R18.z, KC0[18].x, KC0[23].y, PV.w 0440 8092e492 61a288fe w: MULADD_IEEE R13.w, KC0[18].y, KC0[23].y, PV.z 0442 0112e493 42228cfe 81 z: MULADD_IEEE R17.z, KC0[19].y, KC0[23].z, PV.w 0444 8112e093 61a288fe w: MULADD_IEEE R13.w, KC0[19].x, KC0[23].z, PV.z 0446 0192e094 41c28cfe 82 z: MULADD_IEEE R14.z, KC0[20].x, KC0[23].w, PV.w 0448 8192e494 61a288fe w: MULADD_IEEE R13.w, KC0[20].y, KC0[23].w, PV.z 0450 8012c091 61c00210 83 w: MUL_IEEE R14.w, KC0[17].x, KC0[22].x 0452 8092c092 61c28cfe 84 w: MULADD_IEEE R14.w, KC0[18].x, KC0[22].y, PV.w 0454 0112c093 42228cfe 85 z: MULADD_IEEE R17.z, KC0[19].x, KC0[22].z, PV.w 0456 8180400a 62228806 w: MULADD_IEEE R17.w, R10.x, R2.w, R6.z 0458 019fc88d 21600210 86 y: MUL_IEEE R11.y, KC0[13].z, PV.w 0460 0180440a 40c28403 z: MULADD_IEEE R6.z, R10.y, R2.w, R3.y 0462 81804009 61e28006 w: MULADD_IEEE R15.w, R9.x, R2.w, R6.x 0464 019fcc8d 00e00210 87 x: MUL_IEEE R7.x, KC0[13].w, PV.w 0466 01804409 20628807 y: MULADD_IEEE R3.y, R9.y, R2.w, R7.z 0468 011fc88e 40e284fe z: MULADD_IEEE R7.z, KC0[14].z, PV.z, PV.y 0470 8180480a 61c28407 w: MULADD_IEEE R14.w, R10.z, R2.w, R7.y 0472 019fc88f 00c288fe 88 x: MULADD_IEEE R6.x, KC0[15].z, PV.w, PV.z 0474 01804008 20e28803 y: MULADD_IEEE R7.y, R8.x, R2.w, R3.z 0476 009fcc8e 406280fe z: MULADD_IEEE R3.z, KC0[14].w, PV.y, PV.x 0478 81804809 62028406 w: MULADD_IEEE R16.w, R9.z, R2.w, R6.y 0480 019fcc8f 00e288fe 89 x: MULADD_IEEE R7.x, KC0[15].w, PV.w, PV.z 0482 009fcc8d 20c00210 y: MUL_IEEE R6.y, KC0[13].w, PV.y 0484 01804408 40628402 z: MULADD_IEEE R3.z, R8.y, R2.w, R2.y 0486 81822c8d 62440210 w: MUL_IEEE R18.w, KC0[13].w, R17.w VEC_021 0488 01804c09 00628003 90 x: MULADD_IEEE R3.x, R9.w, R2.w, R3.x 0490 0100cc8e 20428cfe y: MULADD_IEEE R2.y, KC0[14].w, R6.z, PV.w 0492 011fcc8e 40e684fe z: MULADD_IEEE R7.z, KC0[14].w, PV.z, PV.y VEC_021 0494 81804808 62468002 w: MULADD_IEEE R18.w, R8.z, R2.w, R2.x VEC_021 0496 019fcc8f 012288fe 91 x: MULADD_IEEE R9.x, KC0[15].w, PV.w, PV.z 0498 81804c08 20c28c04 y: MULADD_IEEE R6.y, R8.w, R2.w, R4.w 0500 0181cc8f 40e28402 92 z: MULADD_IEEE R7.z, KC0[15].w, R14.w, R2.y 0502 81804c0a 61068802 w: MULADD_IEEE R8.w, R10.w, R2.w, R2.z VEC_021 0504 019fcc90 004288fe 93 x: MULADD_IEEE R2.x, KC0[16].w, PV.w, PV.z 0506 0080cc90 20428009 y: MULADD_IEEE R2.y, KC0[16].w, R6.y, R9.x 0508 80006c90 40528007 z: MULADD_IEEE R2.z, KC0[16].w, R3.x, R7.x VEC_201 0510 81810890 60828006 94 w: MULADD_IEEE R4.w, KC0[16].z, R8.w, R6.x 0512 8012c491 61200210 95 w: MUL_IEEE R9.w, KC0[17].y, KC0[22].x 0514 001fac01 00c03110 96 x: OR_INT R6.x, R1.w, [0x00000003 0].x 0516 8092c492 60228cfe w: MULADD_IEEE R1.w, KC0[18].y, KC0[22].y, PV.w 0518 00000003 0020 0000002e 80800000 TEX 1 @92 0092 40060040 e8cd100a 00080000 VFETCH R10.xyzw, R6.x, RID:0 MFC:16 UCF:0 FMT(DTA:35 NUM:2 COMP:1 MODE:1) 0022 80000104 a1c80000 ALU 115 @520 KC0[CB0:0-31] 0520 8112c493 61228c01 97 w: MULADD_IEEE R9.w, KC0[19].y, KC0[22].z, R1.w 0522 0012a491 41000210 98 z: MUL_IEEE R8.z, KC0[17].y, KC0[21].x 0524 8012a091 60200210 w: MUL_IEEE R1.w, KC0[17].x, KC0[21].x 0526 0092a092 40e28cfe 99 z: MULADD_IEEE R7.z, KC0[18].x, KC0[21].y, PV.w 0528 8092a492 602288fe w: MULADD_IEEE R1.w, KC0[18].y, KC0[21].y, PV.z 0530 0112a493 41028cfe 100 z: MULADD_IEEE R8.z, KC0[19].y, KC0[21].z, PV.w 0532 8112a093 602288fe w: MULADD_IEEE R1.w, KC0[19].x, KC0[21].z, PV.z 0534 0192a094 21028cfe 101 y: MULADD_IEEE R8.y, KC0[20].x, KC0[21].w, PV.w 0536 0192a494 40e288fe z: MULADD_IEEE R7.z, KC0[20].y, KC0[21].w, PV.z 0538 8180400a 62628801 w: MULADD_IEEE R19.w, R10.x, R2.w, R1.z 0540 0182208d 00c00210 102 x: MUL_IEEE R6.x, KC0[13].x, R17.w 0542 019fcc8d 21240210 y: MUL_IEEE R9.y, KC0[13].w, PV.w VEC_021 0544 019fc88d 40240210 z: MUL_IEEE R1.z, KC0[13].z, PV.w VEC_021 0546 8180440a 60268401 w: MULADD_IEEE R1.w, R10.y, R2.w, R1.y VEC_021 0548 0182608d 00e00210 103 x: MUL_IEEE R7.x, KC0[13].x, R19.w 0550 019fc88e 202688fe y: MULADD_IEEE R1.y, KC0[14].z, PV.w, PV.z VEC_021 0552 019fcc8e 402684fe z: MULADD_IEEE R1.z, KC0[14].w, PV.w, PV.y VEC_021 0554 8180480a 62868001 w: MULADD_IEEE R20.w, R10.z, R2.w, R1.x VEC_021 0556 019fcc8f 002288fe 104 x: MULADD_IEEE R1.x, KC0[15].w, PV.w, PV.z 0558 019fc88f 212284fe y: MULADD_IEEE R9.y, KC0[15].z, PV.w, PV.y 0560 0180208e 402280fe z: MULADD_IEEE R1.z, KC0[14].x, R1.w, PV.x 0562 8100c08e 62a28006 w: MULADD_IEEE R21.w, KC0[14].x, R6.z, R6.x 0564 0181c08f 00e28cfe 105 x: MULADD_IEEE R7.x, KC0[15].x, R14.w, PV.w 0566 0182808f 216688fe y: MULADD_IEEE R11.y, KC0[15].x, R20.w, PV.z VEC_021 0568 0080e08d 40200210 z: MUL_IEEE R1.z, KC0[13].x, R7.y 0570 8181e08d 62ac0210 w: MUL_IEEE R21.w, KC0[13].x, R15.w VEC_102 0572 0080e48d 01000210 106 x: MUL_IEEE R8.x, KC0[13].y, R7.y 0574 0181e48d 20200210 y: MUL_IEEE R1.y, KC0[13].y, R15.w 0576 0080608e 410a8cfe z: MULADD_IEEE R8.z, KC0[14].x, R3.y, PV.w VEC_120 0578 8100608e 62a288fe w: MULADD_IEEE R21.w, KC0[14].x, R3.z, PV.z 0580 0182408f 00c28cfe 107 x: MULADD_IEEE R6.x, KC0[15].x, R18.w, PV.w 0582 0182008f 21a688fe y: MULADD_IEEE R13.y, KC0[15].x, R16.w, PV.z VEC_021 0584 0080648e 402284fe z: MULADD_IEEE R1.z, KC0[14].y, R3.y, PV.y 0586 8100648e 62a280fe w: MULADD_IEEE R21.w, KC0[14].y, R3.z, PV.x 0588 0182448f 01028cfe 108 x: MULADD_IEEE R8.x, KC0[15].y, R18.w, PV.w 0590 0182648d 20240210 y: MUL_IEEE R1.y, KC0[13].y, R19.w VEC_021 0592 8182048f 402e88fe z: MULADD_IEEE R1.z, KC0[15].y, R16.w, PV.z VEC_102 0594 8182248d 62200210 109 w: MUL_IEEE R17.w, KC0[13].y, R17.w 0596 0100c48e 21828cfe 110 y: MULADD_IEEE R12.y, KC0[14].y, R6.z, PV.w 0598 00006490 41028801 z: MULADD_IEEE R8.z, KC0[16].y, R3.x, R1.z 0600 8180248e 60228401 w: MULADD_IEEE R1.w, KC0[14].y, R1.w, R1.y 0602 8182848f 01628cfe 111 x: MULADD_IEEE R11.x, KC0[15].y, R20.w, PV.w 0604 01804c0a 20228c03 112 y: MULADD_IEEE R1.y, R10.w, R2.w, R3.w 0606 0000a808 40200210 z: MUL_IEEE R1.z, R8.z, R5.x 0608 8080c490 60228008 w: MULADD_IEEE R1.w, KC0[16].y, R6.y, R8.x 0610 0181e88d 01200210 113 x: MUL_IEEE R9.x, KC0[13].z, R15.w 0612 0080e88d 20e00210 y: MUL_IEEE R7.y, KC0[13].z, R7.y 0614 0080acfe 402688fe z: MULADD_IEEE R1.z, PV.w, R5.y, PV.z VEC_021 0616 809fc490 604e800b w: MULADD_IEEE R2.w, KC0[16].y, PV.y, R11.x VEC_102 0618 0100acfe 010288fe 114 x: MULADD_IEEE R8.x, PV.w, R5.z, PV.z 0620 0100688e 20e684fe y: MULADD_IEEE R7.y, KC0[14].z, R3.z, PV.y VEC_021 0622 00006090 40c2840d z: MULADD_IEEE R6.z, KC0[16].x, R3.x, R13.y 0624 8080688e 606280fe w: MULADD_IEEE R3.w, KC0[14].z, R3.y, PV.x 0626 0182088f 01228cfe 115 x: MULADD_IEEE R9.x, KC0[15].z, R16.w, PV.w 0628 0000a8fe 20600210 y: MUL_IEEE R3.y, PV.z, R5.x 0630 0080c090 40628006 z: MULADD_IEEE R3.z, KC0[16].x, R6.y, R6.x 0632 8182488f 606a84fe w: MULADD_IEEE R3.w, KC0[15].z, R18.w, PV.y VEC_120 0634 0080c890 00c28cfe 116 x: MULADD_IEEE R6.x, KC0[16].z, R6.y, PV.w 0636 8080a8fe 206a84fe y: MULADD_IEEE R3.y, PV.z, R5.y, PV.y VEC_120 0638 00802090 4022840b 117 z: MULADD_IEEE R1.z, KC0[16].x, R1.y, R11.y 0640 80006890 61428009 w: MULADD_IEEE R10.w, KC0[16].z, R3.x, R9.x 0642 0000acfe 00600210 118 x: MUL_IEEE R3.x, PV.w, R5.x 0644 0100a8fe 20628403 y: MULADD_IEEE R3.y, PV.z, R5.z, R3.y 0646 01810090 41228007 z: MULADD_IEEE R9.z, KC0[16].x, R8.w, R7.x 0648 8181c48f 6066840c w: MULADD_IEEE R3.w, KC0[15].y, R14.w, R12.y VEC_021 0650 01810490 00e28cfe 119 x: MULADD_IEEE R7.x, KC0[16].y, R8.w, PV.w 0652 011fc4fe 20e00010 y: ADD R7.y, PV.y, PV.z 0654 0080a006 412280fe z: MULADD_IEEE R9.z, R6.x, R5.y, PV.x 0656 80802890 606a8409 w: MULADD_IEEE R3.w, KC0[16].z, R1.y, R9.y VEC_120 0658 0100acfe 006288fe 120 x: MULADD_IEEE R3.x, PV.w, R5.z, PV.z 0660 009fc807 20600210 y: MUL_IEEE R3.y, R7.z, PV.y 0662 001fc008 40e00010 z: ADD R7.z, R8.x, PV.x 0664 8192c494 61028c09 w: MULADD_IEEE R8.w, KC0[20].y, KC0[22].w, R9.w 0666 011fccfe 00e284fe 121 x: MULADD_IEEE R7.x, PV.w, PV.z, PV.y 0668 018080fe 20600010 y: ADD R3.y, PV.x, R4.w 0670 0080e408 41200210 z: MUL_IEEE R9.z, R8.y, R7.y 0672 8192c094 60828811 w: MULADD_IEEE R4.w, KC0[20].x, KC0[22].w, R17.z 0674 0100ecfe 006288fe 122 x: MULADD_IEEE R3.x, PV.w, R7.z, PV.z 0676 009fcc0d 20c280fe y: MULADD_IEEE R6.y, R13.w, PV.y, PV.x 0678 0112ac93 41228c0c z: MULADD_IEEE R9.z, KC0[19].w, KC0[21].z, R12.w 0680 8112a893 60828810 w: MULADD_IEEE R4.w, KC0[19].z, KC0[21].z, R16.z 0682 00008808 00e00210 123 x: MUL_IEEE R7.x, R8.z, R4.x 0684 0192a894 21028cfe y: MULADD_IEEE R8.y, KC0[20].z, KC0[21].w, PV.w 0686 0000a802 40480210 z: MUL_IEEE R2.z, R2.z, R5.x VEC_120 0688 8192ac94 608288fe w: MULADD_IEEE R4.w, KC0[20].w, KC0[21].w, PV.z 0690 0080ecfe 00a00210 124 x: MUL_IEEE R5.x, PV.w, R7.y 0692 8080a402 204688fe y: MULADD_IEEE R2.y, R2.y, R5.y, PV.z VEC_021 0694 00802c90 40428001 125 z: MULADD_IEEE R2.z, KC0[16].w, R1.y, R1.x 0696 80008c0a 60800210 w: MUL_IEEE R4.w, R10.w, R4.x 0698 00808006 00228cfe 126 x: MULADD_IEEE R1.x, R6.x, R4.y, PV.w 0700 0100a8fe 20228402 y: MULADD_IEEE R1.y, PV.z, R5.z, R2.y 0702 0100ec0b 40468005 z: MULADD_IEEE R2.z, R11.w, R7.z, R5.x VEC_021 0704 8192ec94 60828c07 w: MULADD_IEEE R4.w, KC0[20].w, KC0[23].w, R7.w 0706 00806cfe 00a288fe 127 x: MULADD_IEEE R5.x, PV.w, R3.y, PV.z 0708 000044fe 20200010 y: ADD R1.y, PV.y, R2.x 0710 0080e408 40440210 z: MUL_IEEE R2.z, R8.y, R7.y VEC_021 0712 8192c894 6082880f w: MULADD_IEEE R4.w, KC0[20].z, KC0[22].w, R15.z 0714 00008806 00800210 128 x: MUL_IEEE R4.x, R6.z, R4.x 0716 0100ecfe 204288fe y: MULADD_IEEE R2.y, PV.w, R7.z, PV.z 0718 0192e894 4042880d z: MULADD_IEEE R2.z, KC0[20].z, KC0[23].w, R13.z 0720 809fcc06 612280fe w: MULADD_IEEE R9.w, R6.w, PV.y, PV.x 0722 008068fe 004284fe 129 x: MULADD_IEEE R2.x, PV.z, R3.y, PV.y 0724 00000480 20001910 y: MOV R0.y, KC0[0].y 0726 00808803 404680fe z: MULADD_IEEE R2.z, R3.z, R4.y, PV.x VEC_021 0728 81008c03 61028001 w: MULADD_IEEE R8.w, R3.w, R4.z, R1.x 0730 00000080 00001910 130 x: MOV R0.x, KC0[0].x 0732 01008801 210288fe y: MULADD_IEEE R8.y, R1.z, R4.z, PV.z 0734 0080280c 413280fe z: MULADD_IEEE R9.z, R12.z, R1.y, PV.x VEC_201 0736 80808c01 60228007 w: MULADD_IEEE R1.w, R1.w, R4.y, R7.x 0738 01008c02 01028cfe 131 x: MULADD_IEEE R8.x, R2.w, R4.z, PV.w 0740 00802c05 212a8406 y: MULADD_IEEE R9.y, R5.w, R1.y, R6.y VEC_120 0742 0080680e 40228003 z: MULADD_IEEE R1.z, R14.z, R3.y, R3.x 0744 81930094 6022880b w: MULADD_IEEE R1.w, KC0[20].x, KC0[24].w, R11.z 0746 00802cfe 012288fe 132 x: MULADD_IEEE R9.x, PV.w, R1.y, PV.z 0748 80000880 41001910 z: MOV R8.z, KC0[0].z 0024 c004a03c 94400688 EXPORT_DONE POS 60 R9.xyzw VPM 0026 c0004000 93c0021a EXPORT PARAM 0 R0.zwxy VPM 0028 c0044001 9460060a EXPORT_DONE PARAM 1 R8.zyxw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[19], PERSPECTIVE DCL IN[1], GENERIC[20], PERSPECTIVE DCL IN[2], GENERIC[21], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL CONST[0..16] DCL TEMP[0..10], LOCAL IMM[0] FLT32 { 0,0190, 0,0210, -0,0170, 0,0160} IMM[1] FLT32 { 0,0600, 0,0300, 0,0500, -0,0400} IMM[2] FLT32 { 1,0000, 0,0012, 0,0010, 0,7500} IMM[3] FLT32 { 0,0060, 0,2500, 0,0080, 0,4444} IMM[4] FLT32 { 0,0010, 0,0011, -0,4800, 0,9500} IMM[5] UINT32 {0, 4294967295, 0, 0} IMM[6] FLT32 { 0,5000, 0,0000, 400,0000, 0,9990} IMM[7] FLT32 { 0,0000, 0,0000, 0,0039, 1,0000} IMM[8] FLT32 { 40,0000, 0,8000, 0,9000, 1,0000} IMM[9] FLT32 { 2,0000, 0,6000, 0,0000, 0,0000} 0: MOV TEMP[0].z, IN[2].xxxx 1: MOV TEMP[0].xy, IN[1].zwzz 2: ADD TEMP[1].x, IN[0].zzzz, -CONST[13].xxxx 3: RCP TEMP[2].x, CONST[12].xxxx 4: MUL_SAT TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx 5: MUL TEMP[2].x, CONST[11].xxxx, CONST[10].xxxx 6: MUL TEMP[3].x, IMM[0].xxxx, TEMP[2].xxxx 7: MUL TEMP[4].x, IMM[0].yyyy, TEMP[2].xxxx 8: MOV TEMP[3].y, TEMP[4].xxxx 9: MUL TEMP[4].x, IMM[0].zzzz, TEMP[2].xxxx 10: MUL TEMP[5].x, IMM[0].wwww, TEMP[2].xxxx 11: MOV TEMP[4].y, TEMP[5].xxxx 12: MUL TEMP[5].x, IMM[1].xxxx, TEMP[2].xxxx 13: MUL TEMP[6].x, IMM[1].yyyy, TEMP[2].xxxx 14: MOV TEMP[5].y, TEMP[6].xxxx 15: MUL TEMP[6].x, IMM[1].zzzz, TEMP[2].xxxx 16: MUL TEMP[2].x, IMM[1].wwww, TEMP[2].xxxx 17: MOV TEMP[6].y, TEMP[2].xxxx 18: MOV TEMP[2].z, IMM[2].xxxx 19: MOV TEMP[2].x, CONST[3].xxxx 20: MOV TEMP[2].y, CONST[3].xxxx 21: MAD TEMP[3].xy, IN[1].xyyy, IMM[2].yzzz, TEMP[3].xyyy 22: MOV TEMP[3].xy, TEMP[3].xyyy 23: TEX TEMP[3], TEMP[3], SAMP[3], 2D 24: MAD TEMP[6].xy, IN[1].xyyy, IMM[3].xxxx, TEMP[6].xyyy 25: MOV TEMP[6].xy, TEMP[6].xyyy 26: TEX TEMP[6], TEMP[6], SAMP[3], 2D 27: MAD TEMP[5].xy, IN[1].xyyy, IMM[3].zzzz, TEMP[5].xyyy 28: MOV TEMP[5].xy, TEMP[5].xyyy 29: TEX TEMP[5], TEMP[5], SAMP[3], 2D 30: MUL TEMP[5], TEMP[5], IMM[3].yyyy 31: MAD TEMP[5], TEMP[6], IMM[3].yyyy, TEMP[5] 32: MAD TEMP[3], TEMP[3], IMM[2].wwww, TEMP[5] 33: MAD TEMP[4].xy, IN[1].xyyy, IMM[4].xyyy, TEMP[4].xyyy 34: MOV TEMP[4].xy, TEMP[4].xyyy 35: TEX TEMP[4], TEMP[4], SAMP[3], 2D 36: ADD TEMP[3], TEMP[3], TEMP[4] 37: MAD TEMP[3].xyz, TEMP[3], IMM[3].wwww, IMM[4].zzzz 38: MUL TEMP[2].xyz, TEMP[3].xyzz, TEMP[2].xyzz 39: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz 40: RSQ TEMP[3].x, TEMP[3].xxxx 41: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx 42: DP3 TEMP[3].x, TEMP[0].xyzz, TEMP[0].xyzz 43: RSQ TEMP[3].x, TEMP[3].xxxx 44: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[3].xxxx 45: MOV TEMP[3].z, IMM[2].xxxx 46: MOV TEMP[3].x, CONST[2].xxxx 47: MOV TEMP[3].y, CONST[2].xxxx 48: MUL TEMP[3].xyz, TEMP[2].xyzz, TEMP[3].xyzz 49: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[3].xyzz 50: RSQ TEMP[4].x, TEMP[4].xxxx 51: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx 52: DP3 TEMP[3].x, TEMP[3].xyzz, TEMP[0].xyzz 53: MOV TEMP[4].x, TEMP[3].xxxx 54: USEQ TEMP[5].x, CONST[15].xxxx, IMM[5].xxxx 55: UIF TEMP[5].xxxx :0 56: MOV TEMP[4].x, -TEMP[3].xxxx 57: ENDIF 58: ADD TEMP[3].x, IMM[2].xxxx, -TEMP[1].xxxx 59: MUL TEMP[3].x, TEMP[4].xxxx, TEMP[3].xxxx 60: ADD TEMP[3].x, IMM[2].xxxx, -TEMP[3].xxxx 61: POW TEMP[3].x, TEMP[3].xxxx, CONST[8].xxxx 62: MOV_SAT TEMP[3].x, TEMP[3].xxxx 63: MAD TEMP[3].x, TEMP[3].xxxx, IMM[4].wwww, IMM[1].zzzz 64: RCP TEMP[4].x, IN[0].wwww 65: MAD TEMP[4].xy, IN[0].xyyy, TEMP[4].xxxx, IMM[2].xxxx 66: MUL TEMP[4].xy, TEMP[4].xyyy, IMM[6].xxxx 67: MOV TEMP[5].x, TEMP[4].xxxx 68: RCP TEMP[6].x, CONST[0].yyyy 69: ADD TEMP[4].x, TEMP[4].yyyy, -TEMP[6].xxxx 70: MOV TEMP[5].y, TEMP[4].xxxx 71: MOV TEMP[4].xy, TEMP[5].xyyy 72: TEX TEMP[4], TEMP[4], SAMP[0], 2D 73: DP4 TEMP[4].x, TEMP[4], IMM[7] 74: MOV TEMP[6].x, TEMP[4].xxxx 75: SLT TEMP[4].x, IMM[6].xxxx, TEMP[4].xxxx 76: F2I TEMP[4].x, -TEMP[4] 77: UIF TEMP[4].xxxx :0 78: MOV TEMP[6].x, IMM[6].yyyy 79: ENDIF 80: MUL TEMP[4].xy, TEMP[2].xyyy, CONST[9].xxxx 81: MUL_SAT TEMP[6].x, TEMP[6].xxxx, IMM[6].zzzz 82: MAD TEMP[4].xy, TEMP[4].xyyy, TEMP[6].xxxx, TEMP[5].xyyy 83: MIN TEMP[4].xy, TEMP[4].xyyy, IMM[6].wwww 84: MAX TEMP[4].xy, TEMP[4].xyyy, IMM[2].zzzz 85: MOV TEMP[6].xy, TEMP[4].xyyy 86: TEX TEMP[6], TEMP[6], SAMP[0], 2D 87: DP4 TEMP[6].x, TEMP[6], IMM[7] 88: MUL TEMP[6].x, TEMP[6].xxxx, IMM[8].xxxx 89: MIN TEMP[6].x, TEMP[6].xxxx, IMM[2].xxxx 90: MAX TEMP[6].x, TEMP[6].xxxx, IMM[8].yyyy 91: MAD TEMP[7].xy, TEMP[2].xyyy, CONST[9].xxxx, TEMP[5].xyyy 92: MIN TEMP[7].xy, TEMP[7].xyyy, IMM[6].wwww 93: MAX TEMP[7].xy, TEMP[7].xyyy, IMM[2].zzzz 94: MOV TEMP[5].xy, TEMP[7].xyxx 95: USEQ TEMP[8].x, CONST[15].xxxx, IMM[5].yyyy 96: UIF TEMP[8].xxxx :0 97: ADD TEMP[5].x, IMM[2].xxxx, -TEMP[7].xxxx 98: ENDIF 99: MOV TEMP[7].w, IMM[2].xxxx 100: MOV TEMP[7].xyz, CONST[16].xyzx 101: MOV TEMP[5].xy, TEMP[5].xyyy 102: TEX TEMP[5], TEMP[5], SAMP[2], 2D 103: MOV TEMP[8], TEMP[5] 104: USEQ TEMP[9].x, CONST[15].xxxx, IMM[5].xxxx 105: UIF TEMP[9].xxxx :0 106: MUL TEMP[5], TEMP[5], IMM[8].yzww 107: MOV TEMP[8], TEMP[5] 108: LRP TEMP[5], TEMP[3].xxxx, TEMP[7], TEMP[5] 109: LRP TEMP[5], TEMP[1].xxxx, TEMP[7], TEMP[5] 110: ELSE :0 111: MOV TEMP[9].xyz, -CONST[7].xyzx 112: DP3 TEMP[10].x, TEMP[2].xyzz, TEMP[9].xyzz 113: MUL TEMP[2].xyz, TEMP[10].xxxx, TEMP[2].xyzz 114: MUL TEMP[2].xyz, IMM[9].xxxx, TEMP[2].xyzz 115: ADD TEMP[2].xyz, TEMP[9].xyzz, -TEMP[2].xyzz 116: DP3 TEMP[9].x, TEMP[2].xyzz, TEMP[2].xyzz 117: RSQ TEMP[9].x, TEMP[9].xxxx 118: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[9].xxxx 119: DP3 TEMP[0].x, TEMP[0].xyzz, TEMP[2].xyzz 120: MAX TEMP[0].x, IMM[6].yyyy, TEMP[0].xxxx 121: POW TEMP[0].x, TEMP[0].xxxx, CONST[5].xxxx 122: MUL TEMP[0].x, TEMP[0].xxxx, CONST[4].xxxx 123: MUL TEMP[0].xyz, TEMP[0].xxxx, CONST[6].xyzz 124: MOV TEMP[2].xy, TEMP[4].xyyy 125: TEX TEMP[2], TEMP[2], SAMP[1], 2D 126: MUL TEMP[2], TEMP[2], IMM[9].yyyy 127: LRP TEMP[2], TEMP[6].xxxx, TEMP[7], TEMP[2] 128: LRP TEMP[2], TEMP[3].xxxx, TEMP[8], TEMP[2] 129: UIF CONST[1].xxxx :0 130: MOV TEMP[3].w, IMM[2].xxxx 131: MOV TEMP[3].xyz, TEMP[0].xyzx 132: MOV TEMP[4].w, IMM[2].xxxx 133: MOV TEMP[4].xyz, CONST[14].xyzx 134: LRP TEMP[6], TEMP[1].xxxx, TEMP[8], TEMP[2] 135: ADD TEMP[3], TEMP[3], TEMP[6] 136: ADD TEMP[6].x, IMM[2].xxxx, -TEMP[1].xxxx 137: MUL TEMP[3], TEMP[3], TEMP[6].xxxx 138: MAD TEMP[5], TEMP[4], TEMP[1].xxxx, TEMP[3] 139: ELSE :0 140: MOV TEMP[3].w, IMM[2].xxxx 141: MOV TEMP[3].xyz, TEMP[0].xyzx 142: LRP TEMP[0], TEMP[1].xxxx, TEMP[8], TEMP[2] 143: ADD TEMP[5], TEMP[3], TEMP[0] 144: ENDIF 145: ENDIF 146: MOV OUT[0], TEMP[5] 147: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = call float @llvm.R600.load.input(i32 4) %5 = call float @llvm.R600.load.input(i32 5) %6 = call float @llvm.R600.load.input(i32 6) %7 = call float @llvm.R600.load.input(i32 7) %8 = call float @llvm.R600.load.input(i32 8) %9 = call float @llvm.R600.load.input(i32 9) %10 = call float @llvm.R600.load.input(i32 10) %11 = call float @llvm.R600.load.input(i32 11) %12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %13 = extractelement <4 x float> %12, i32 0 %14 = fsub float -0,000000e+00, %13 %15 = fadd float %2, %14 %16 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %17 = extractelement <4 x float> %16, i32 0 %18 = fdiv float 0x3FF0000000000000, %17 %19 = fmul float %15, %18 %20 = call float @llvm.AMDIL.clamp.(float %19, float 0,000000e+00, float 0x3FF0000000000000) %21 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %22 = extractelement <4 x float> %21, i32 0 %23 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %24 = extractelement <4 x float> %23, i32 0 %25 = fmul float %22, %24 %26 = fmul float 0x3F9374BC60000000, %25 %27 = fmul float 0x3F95810620000000, %25 %28 = fmul float 0xBF916872C0000000, %25 %29 = fmul float 0x3F90624DE0000000, %25 %30 = fmul float 0x3FAEB851E0000000, %25 %31 = fmul float 0x3F9EB851E0000000, %25 %32 = fmul float 0x3FA99999A0000000, %25 %33 = fmul float 0xBFA47AE140000000, %25 %34 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %35 = extractelement <4 x float> %34, i32 0 %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %37 = extractelement <4 x float> %36, i32 0 %38 = fmul float %4, 0x3F53A92A40000000 %39 = fadd float %38, %26 %40 = fmul float %5, 0x3F50624DE0000000 %41 = fadd float %40, %27 %42 = insertelement <4 x float> undef, float %39, i32 0 %43 = insertelement <4 x float> %42, float %41, i32 1 %44 = insertelement <4 x float> %43, float 0,000000e+00, i32 2 %45 = insertelement <4 x float> %44, float 0,000000e+00, i32 3 %46 = extractelement <4 x float> %45, i32 0 %47 = extractelement <4 x float> %45, i32 1 %48 = insertelement <4 x float> undef, float %46, i32 0 %49 = insertelement <4 x float> %48, float %47, i32 1 %50 = insertelement <4 x float> %49, float undef, i32 2 %51 = insertelement <4 x float> %50, float undef, i32 3 %52 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %51, i32 19, i32 3, i32 2) %53 = extractelement <4 x float> %52, i32 0 %54 = extractelement <4 x float> %52, i32 1 %55 = extractelement <4 x float> %52, i32 2 %56 = fmul float %4, 0x3F789374C0000000 %57 = fadd float %56, %32 %58 = fmul float %5, 0x3F789374C0000000 %59 = fadd float %58, %33 %60 = insertelement <4 x float> undef, float %57, i32 0 %61 = insertelement <4 x float> %60, float %59, i32 1 %62 = insertelement <4 x float> %61, float 0,000000e+00, i32 2 %63 = insertelement <4 x float> %62, float 0,000000e+00, i32 3 %64 = extractelement <4 x float> %63, i32 0 %65 = extractelement <4 x float> %63, i32 1 %66 = insertelement <4 x float> undef, float %64, i32 0 %67 = insertelement <4 x float> %66, float %65, i32 1 %68 = insertelement <4 x float> %67, float undef, i32 2 %69 = insertelement <4 x float> %68, float undef, i32 3 %70 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %69, i32 19, i32 3, i32 2) %71 = extractelement <4 x float> %70, i32 0 %72 = extractelement <4 x float> %70, i32 1 %73 = extractelement <4 x float> %70, i32 2 %74 = extractelement <4 x float> %70, i32 3 %75 = fmul float %4, 0x3F80624DE0000000 %76 = fadd float %75, %30 %77 = fmul float %5, 0x3F80624DE0000000 %78 = fadd float %77, %31 %79 = insertelement <4 x float> undef, float %76, i32 0 %80 = insertelement <4 x float> %79, float %78, i32 1 %81 = insertelement <4 x float> %80, float 0,000000e+00, i32 2 %82 = insertelement <4 x float> %81, float 0,000000e+00, i32 3 %83 = extractelement <4 x float> %82, i32 0 %84 = extractelement <4 x float> %82, i32 1 %85 = insertelement <4 x float> undef, float %83, i32 0 %86 = insertelement <4 x float> %85, float %84, i32 1 %87 = insertelement <4 x float> %86, float undef, i32 2 %88 = insertelement <4 x float> %87, float undef, i32 3 %89 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %88, i32 19, i32 3, i32 2) %90 = extractelement <4 x float> %89, i32 0 %91 = extractelement <4 x float> %89, i32 1 %92 = extractelement <4 x float> %89, i32 2 %93 = extractelement <4 x float> %89, i32 3 %94 = fmul float %90, 0x3FD0000000000000 %95 = fmul float %91, 0x3FD0000000000000 %96 = fmul float %92, 0x3FD0000000000000 %97 = fmul float %93, 0x3FD0000000000000 %98 = fmul float %71, 0x3FD0000000000000 %99 = fadd float %98, %94 %100 = fmul float %72, 0x3FD0000000000000 %101 = fadd float %100, %95 %102 = fmul float %73, 0x3FD0000000000000 %103 = fadd float %102, %96 %104 = fmul float %74, 0x3FD0000000000000 %105 = fadd float %104, %97 %106 = fmul float %53, 0x3FE8000000000000 %107 = fadd float %106, %99 %108 = fmul float %54, 0x3FE8000000000000 %109 = fadd float %108, %101 %110 = fmul float %55, 0x3FE8000000000000 %111 = fadd float %110, %103 %112 = fmul float %4, 0x3F50624DE0000000 %113 = fadd float %112, %28 %114 = fmul float %5, 0x3F5205BC00000000 %115 = fadd float %114, %29 %116 = insertelement <4 x float> undef, float %113, i32 0 %117 = insertelement <4 x float> %116, float %115, i32 1 %118 = insertelement <4 x float> %117, float 0,000000e+00, i32 2 %119 = insertelement <4 x float> %118, float 0,000000e+00, i32 3 %120 = extractelement <4 x float> %119, i32 0 %121 = extractelement <4 x float> %119, i32 1 %122 = insertelement <4 x float> undef, float %120, i32 0 %123 = insertelement <4 x float> %122, float %121, i32 1 %124 = insertelement <4 x float> %123, float undef, i32 2 %125 = insertelement <4 x float> %124, float undef, i32 3 %126 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %125, i32 19, i32 3, i32 2) %127 = extractelement <4 x float> %126, i32 0 %128 = extractelement <4 x float> %126, i32 1 %129 = extractelement <4 x float> %126, i32 2 %130 = extractelement <4 x float> %126, i32 3 %131 = fadd float %107, %127 %132 = fadd float %109, %128 %133 = fadd float %111, %129 %134 = fmul float %131, 0x3FDC71C720000000 %135 = fadd float %134, 0xBFDEB851E0000000 %136 = fmul float %132, 0x3FDC71C720000000 %137 = fadd float %136, 0xBFDEB851E0000000 %138 = fmul float %133, 0x3FDC71C720000000 %139 = fadd float %138, 0xBFDEB851E0000000 %140 = fmul float %135, %35 %141 = fmul float %137, %37 %142 = fmul float %139, 0x3FF0000000000000 %143 = insertelement <4 x float> undef, float %140, i32 0 %144 = insertelement <4 x float> %143, float %141, i32 1 %145 = insertelement <4 x float> %144, float %142, i32 2 %146 = insertelement <4 x float> %145, float 0,000000e+00, i32 3 %147 = insertelement <4 x float> undef, float %140, i32 0 %148 = insertelement <4 x float> %147, float %141, i32 1 %149 = insertelement <4 x float> %148, float %142, i32 2 %150 = insertelement <4 x float> %149, float 0,000000e+00, i32 3 %151 = call float @llvm.AMDGPU.dp4(<4 x float> %146, <4 x float> %150) %152 = call float @fabs(float %151) %153 = call float @llvm.AMDGPU.rsq(float %152) %154 = fmul float %140, %153 %155 = fmul float %141, %153 %156 = fmul float %142, %153 %157 = insertelement <4 x float> undef, float %6, i32 0 %158 = insertelement <4 x float> %157, float %7, i32 1 %159 = insertelement <4 x float> %158, float %8, i32 2 %160 = insertelement <4 x float> %159, float 0,000000e+00, i32 3 %161 = insertelement <4 x float> undef, float %6, i32 0 %162 = insertelement <4 x float> %161, float %7, i32 1 %163 = insertelement <4 x float> %162, float %8, i32 2 %164 = insertelement <4 x float> %163, float 0,000000e+00, i32 3 %165 = call float @llvm.AMDGPU.dp4(<4 x float> %160, <4 x float> %164) %166 = call float @fabs(float %165) %167 = call float @llvm.AMDGPU.rsq(float %166) %168 = fmul float %6, %167 %169 = fmul float %7, %167 %170 = fmul float %8, %167 %171 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %172 = extractelement <4 x float> %171, i32 0 %173 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %174 = extractelement <4 x float> %173, i32 0 %175 = fmul float %154, %172 %176 = fmul float %155, %174 %177 = fmul float %156, 0x3FF0000000000000 %178 = insertelement <4 x float> undef, float %175, i32 0 %179 = insertelement <4 x float> %178, float %176, i32 1 %180 = insertelement <4 x float> %179, float %177, i32 2 %181 = insertelement <4 x float> %180, float 0,000000e+00, i32 3 %182 = insertelement <4 x float> undef, float %175, i32 0 %183 = insertelement <4 x float> %182, float %176, i32 1 %184 = insertelement <4 x float> %183, float %177, i32 2 %185 = insertelement <4 x float> %184, float 0,000000e+00, i32 3 %186 = call float @llvm.AMDGPU.dp4(<4 x float> %181, <4 x float> %185) %187 = call float @fabs(float %186) %188 = call float @llvm.AMDGPU.rsq(float %187) %189 = fmul float %175, %188 %190 = fmul float %176, %188 %191 = fmul float %177, %188 %192 = insertelement <4 x float> undef, float %189, i32 0 %193 = insertelement <4 x float> %192, float %190, i32 1 %194 = insertelement <4 x float> %193, float %191, i32 2 %195 = insertelement <4 x float> %194, float 0,000000e+00, i32 3 %196 = insertelement <4 x float> undef, float %168, i32 0 %197 = insertelement <4 x float> %196, float %169, i32 1 %198 = insertelement <4 x float> %197, float %170, i32 2 %199 = insertelement <4 x float> %198, float 0,000000e+00, i32 3 %200 = call float @llvm.AMDGPU.dp4(<4 x float> %195, <4 x float> %199) %201 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %202 = extractelement <4 x float> %201, i32 0 %203 = bitcast float %202 to i32 %204 = icmp eq i32 %203, 0 %205 = sext i1 %204 to i32 %206 = bitcast i32 %205 to float %207 = bitcast float %206 to i32 %208 = icmp ne i32 %207, 0 br i1 %208, label %IF, label %ENDIF IF: ; preds = %main_body %209 = fsub float -0,000000e+00, %200 br label %ENDIF ENDIF: ; preds = %main_body, %IF %temp16.0 = phi float [ %209, %IF ], [ %200, %main_body ] %210 = fsub float -0,000000e+00, %20 %211 = fadd float 0x3FF0000000000000, %210 %212 = fmul float %temp16.0, %211 %213 = fsub float -0,000000e+00, %212 %214 = fadd float 0x3FF0000000000000, %213 %215 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %216 = extractelement <4 x float> %215, i32 0 %217 = call float @llvm.pow.f32(float %214, float %216) %218 = call float @llvm.AMDIL.clamp.(float %217, float 0,000000e+00, float 0x3FF0000000000000) %219 = fmul float %218, 0x3FEE666660000000 %220 = fadd float %219, 0x3FA99999A0000000 %221 = fdiv float 0x3FF0000000000000, %3 %222 = fmul float %0, %221 %223 = fadd float %222, 0x3FF0000000000000 %224 = fmul float %1, %221 %225 = fadd float %224, 0x3FF0000000000000 %226 = fmul float %223, 0x3FE0000000000000 %227 = fmul float %225, 0x3FE0000000000000 %228 = load <4 x float> addrspace(8)* null %229 = extractelement <4 x float> %228, i32 1 %230 = fdiv float 0x3FF0000000000000, %229 %231 = fsub float -0,000000e+00, %230 %232 = fadd float %227, %231 %233 = insertelement <4 x float> undef, float %226, i32 0 %234 = insertelement <4 x float> %233, float %232, i32 1 %235 = insertelement <4 x float> %234, float %129, i32 2 %236 = insertelement <4 x float> %235, float %130, i32 3 %237 = extractelement <4 x float> %236, i32 0 %238 = extractelement <4 x float> %236, i32 1 %239 = insertelement <4 x float> undef, float %237, i32 0 %240 = insertelement <4 x float> %239, float %238, i32 1 %241 = insertelement <4 x float> %240, float undef, i32 2 %242 = insertelement <4 x float> %241, float undef, i32 3 %243 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %242, i32 16, i32 0, i32 2) %244 = extractelement <4 x float> %243, i32 0 %245 = extractelement <4 x float> %243, i32 1 %246 = extractelement <4 x float> %243, i32 2 %247 = extractelement <4 x float> %243, i32 3 %248 = insertelement <4 x float> undef, float %244, i32 0 %249 = insertelement <4 x float> %248, float %245, i32 1 %250 = insertelement <4 x float> %249, float %246, i32 2 %251 = insertelement <4 x float> %250, float %247, i32 3 %252 = call float @llvm.AMDGPU.dp4(<4 x float> %251, <4 x float> ) %253 = fcmp ult float 0x3FE0000000000000, %252 %254 = select i1 %253, float 0x3FF0000000000000, float 0,000000e+00 %255 = fsub float -0,000000e+00, %254 %256 = fptosi float %255 to i32 %257 = bitcast i32 %256 to float %258 = bitcast float %257 to i32 %259 = icmp ne i32 %258, 0 %. = select i1 %259, float 0,000000e+00, float %252 %260 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %261 = extractelement <4 x float> %260, i32 0 %262 = fmul float %154, %261 %263 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %264 = extractelement <4 x float> %263, i32 0 %265 = fmul float %155, %264 %266 = fmul float %., 0x4079000000000000 %267 = call float @llvm.AMDIL.clamp.(float %266, float 0,000000e+00, float 0x3FF0000000000000) %268 = fmul float %262, %267 %269 = fadd float %268, %226 %270 = fmul float %265, %267 %271 = fadd float %270, %232 %272 = fcmp uge float %269, 0x3FEFF7CEE0000000 %273 = select i1 %272, float 0x3FEFF7CEE0000000, float %269 %274 = fcmp uge float %271, 0x3FEFF7CEE0000000 %275 = select i1 %274, float 0x3FEFF7CEE0000000, float %271 %276 = fcmp uge float %273, 0x3F50624DE0000000 %277 = select i1 %276, float %273, float 0x3F50624DE0000000 %278 = fcmp uge float %275, 0x3F50624DE0000000 %279 = select i1 %278, float %275, float 0x3F50624DE0000000 %280 = insertelement <4 x float> undef, float %277, i32 0 %281 = insertelement <4 x float> %280, float %279, i32 1 %282 = insertelement <4 x float> %281, float %73, i32 2 %283 = insertelement <4 x float> %282, float %74, i32 3 %284 = extractelement <4 x float> %283, i32 0 %285 = extractelement <4 x float> %283, i32 1 %286 = insertelement <4 x float> undef, float %284, i32 0 %287 = insertelement <4 x float> %286, float %285, i32 1 %288 = insertelement <4 x float> %287, float undef, i32 2 %289 = insertelement <4 x float> %288, float undef, i32 3 %290 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %289, i32 16, i32 0, i32 2) %291 = extractelement <4 x float> %290, i32 0 %292 = extractelement <4 x float> %290, i32 1 %293 = extractelement <4 x float> %290, i32 2 %294 = extractelement <4 x float> %290, i32 3 %295 = insertelement <4 x float> undef, float %291, i32 0 %296 = insertelement <4 x float> %295, float %292, i32 1 %297 = insertelement <4 x float> %296, float %293, i32 2 %298 = insertelement <4 x float> %297, float %294, i32 3 %299 = call float @llvm.AMDGPU.dp4(<4 x float> %298, <4 x float> ) %300 = fmul float %299, 0x4044000000000000 %301 = fcmp uge float %300, 0x3FF0000000000000 %302 = select i1 %301, float 0x3FF0000000000000, float %300 %303 = fcmp uge float %302, 0x3FE99999A0000000 %304 = select i1 %303, float %302, float 0x3FE99999A0000000 %305 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %306 = extractelement <4 x float> %305, i32 0 %307 = fmul float %154, %306 %308 = fadd float %307, %226 %309 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %310 = extractelement <4 x float> %309, i32 0 %311 = fmul float %155, %310 %312 = fadd float %311, %232 %313 = fcmp uge float %308, 0x3FEFF7CEE0000000 %314 = select i1 %313, float 0x3FEFF7CEE0000000, float %308 %315 = fcmp uge float %312, 0x3FEFF7CEE0000000 %316 = select i1 %315, float 0x3FEFF7CEE0000000, float %312 %317 = fcmp uge float %314, 0x3F50624DE0000000 %318 = select i1 %317, float %314, float 0x3F50624DE0000000 %319 = fcmp uge float %316, 0x3F50624DE0000000 %320 = select i1 %319, float %316, float 0x3F50624DE0000000 %321 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %322 = extractelement <4 x float> %321, i32 0 %323 = bitcast float %322 to i32 %324 = icmp eq i32 %323, -1 %325 = sext i1 %324 to i32 %326 = bitcast i32 %325 to float %327 = bitcast float %326 to i32 %328 = icmp ne i32 %327, 0 br i1 %328, label %IF48, label %ENDIF47 IF48: ; preds = %ENDIF %329 = fsub float -0,000000e+00, %318 %330 = fadd float 0x3FF0000000000000, %329 br label %ENDIF47 ENDIF47: ; preds = %ENDIF, %IF48 %temp20.0 = phi float [ %330, %IF48 ], [ %318, %ENDIF ] %331 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %332 = extractelement <4 x float> %331, i32 0 %333 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %334 = extractelement <4 x float> %333, i32 1 %335 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) %336 = extractelement <4 x float> %335, i32 2 %337 = insertelement <4 x float> undef, float %temp20.0, i32 0 %338 = insertelement <4 x float> %337, float %320, i32 1 %339 = insertelement <4 x float> %338, float %103, i32 2 %340 = insertelement <4 x float> %339, float %105, i32 3 %341 = extractelement <4 x float> %340, i32 0 %342 = extractelement <4 x float> %340, i32 1 %343 = insertelement <4 x float> undef, float %341, i32 0 %344 = insertelement <4 x float> %343, float %342, i32 1 %345 = insertelement <4 x float> %344, float undef, i32 2 %346 = insertelement <4 x float> %345, float undef, i32 3 %347 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %346, i32 18, i32 2, i32 2) %348 = extractelement <4 x float> %347, i32 0 %349 = extractelement <4 x float> %347, i32 1 %350 = extractelement <4 x float> %347, i32 2 %351 = extractelement <4 x float> %347, i32 3 %352 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %353 = extractelement <4 x float> %352, i32 0 %354 = bitcast float %353 to i32 %355 = icmp eq i32 %354, 0 %356 = sext i1 %355 to i32 %357 = bitcast i32 %356 to float %358 = bitcast float %357 to i32 %359 = icmp ne i32 %358, 0 br i1 %359, label %IF51, label %ELSE52 IF51: ; preds = %ENDIF47 %360 = fmul float %348, 0x3FE99999A0000000 %361 = fmul float %349, 0x3FECCCCCC0000000 %362 = fmul float %350, 0x3FF0000000000000 %363 = fmul float %351, 0x3FF0000000000000 %364 = call float @llvm.AMDGPU.lrp(float %220, float %332, float %360) %365 = call float @llvm.AMDGPU.lrp(float %220, float %334, float %361) %366 = call float @llvm.AMDGPU.lrp(float %220, float %336, float %362) %367 = call float @llvm.AMDGPU.lrp(float %220, float 0x3FF0000000000000, float %363) %368 = call float @llvm.AMDGPU.lrp(float %20, float %332, float %364) %369 = call float @llvm.AMDGPU.lrp(float %20, float %334, float %365) %370 = call float @llvm.AMDGPU.lrp(float %20, float %336, float %366) %371 = call float @llvm.AMDGPU.lrp(float %20, float 0x3FF0000000000000, float %367) br label %ENDIF50 ELSE52: ; preds = %ENDIF47 %372 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %373 = extractelement <4 x float> %372, i32 0 %374 = fsub float -0,000000e+00, %373 %375 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %376 = extractelement <4 x float> %375, i32 1 %377 = fsub float -0,000000e+00, %376 %378 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %379 = extractelement <4 x float> %378, i32 2 %380 = fsub float -0,000000e+00, %379 %381 = insertelement <4 x float> undef, float %154, i32 0 %382 = insertelement <4 x float> %381, float %155, i32 1 %383 = insertelement <4 x float> %382, float %156, i32 2 %384 = insertelement <4 x float> %383, float 0,000000e+00, i32 3 %385 = insertelement <4 x float> undef, float %374, i32 0 %386 = insertelement <4 x float> %385, float %377, i32 1 %387 = insertelement <4 x float> %386, float %380, i32 2 %388 = insertelement <4 x float> %387, float 0,000000e+00, i32 3 %389 = call float @llvm.AMDGPU.dp4(<4 x float> %384, <4 x float> %388) %390 = fmul float %389, %154 %391 = fmul float %389, %155 %392 = fmul float %389, %156 %393 = fmul float 0x4000000000000000, %390 %394 = fmul float 0x4000000000000000, %391 %395 = fmul float 0x4000000000000000, %392 %396 = fsub float -0,000000e+00, %393 %397 = fadd float %374, %396 %398 = fsub float -0,000000e+00, %394 %399 = fadd float %377, %398 %400 = fsub float -0,000000e+00, %395 %401 = fadd float %380, %400 %402 = insertelement <4 x float> undef, float %397, i32 0 %403 = insertelement <4 x float> %402, float %399, i32 1 %404 = insertelement <4 x float> %403, float %401, i32 2 %405 = insertelement <4 x float> %404, float 0,000000e+00, i32 3 %406 = insertelement <4 x float> undef, float %397, i32 0 %407 = insertelement <4 x float> %406, float %399, i32 1 %408 = insertelement <4 x float> %407, float %401, i32 2 %409 = insertelement <4 x float> %408, float 0,000000e+00, i32 3 %410 = call float @llvm.AMDGPU.dp4(<4 x float> %405, <4 x float> %409) %411 = call float @fabs(float %410) %412 = call float @llvm.AMDGPU.rsq(float %411) %413 = fmul float %397, %412 %414 = fmul float %399, %412 %415 = fmul float %401, %412 %416 = insertelement <4 x float> undef, float %168, i32 0 %417 = insertelement <4 x float> %416, float %169, i32 1 %418 = insertelement <4 x float> %417, float %170, i32 2 %419 = insertelement <4 x float> %418, float 0,000000e+00, i32 3 %420 = insertelement <4 x float> undef, float %413, i32 0 %421 = insertelement <4 x float> %420, float %414, i32 1 %422 = insertelement <4 x float> %421, float %415, i32 2 %423 = insertelement <4 x float> %422, float 0,000000e+00, i32 3 %424 = call float @llvm.AMDGPU.dp4(<4 x float> %419, <4 x float> %423) %425 = fcmp uge float 0,000000e+00, %424 %426 = select i1 %425, float 0,000000e+00, float %424 %427 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %428 = extractelement <4 x float> %427, i32 0 %429 = call float @llvm.pow.f32(float %426, float %428) %430 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %431 = extractelement <4 x float> %430, i32 0 %432 = fmul float %429, %431 %433 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %434 = extractelement <4 x float> %433, i32 0 %435 = fmul float %432, %434 %436 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %437 = extractelement <4 x float> %436, i32 1 %438 = fmul float %432, %437 %439 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %440 = extractelement <4 x float> %439, i32 2 %441 = fmul float %432, %440 %442 = insertelement <4 x float> undef, float %277, i32 0 %443 = insertelement <4 x float> %442, float %279, i32 1 %444 = insertelement <4 x float> %443, float %415, i32 2 %445 = insertelement <4 x float> %444, float 0,000000e+00, i32 3 %446 = extractelement <4 x float> %445, i32 0 %447 = extractelement <4 x float> %445, i32 1 %448 = insertelement <4 x float> undef, float %446, i32 0 %449 = insertelement <4 x float> %448, float %447, i32 1 %450 = insertelement <4 x float> %449, float undef, i32 2 %451 = insertelement <4 x float> %450, float undef, i32 3 %452 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %451, i32 17, i32 1, i32 2) %453 = extractelement <4 x float> %452, i32 0 %454 = extractelement <4 x float> %452, i32 1 %455 = extractelement <4 x float> %452, i32 2 %456 = extractelement <4 x float> %452, i32 3 %457 = fmul float %453, 0x3FE3333340000000 %458 = fmul float %454, 0x3FE3333340000000 %459 = fmul float %455, 0x3FE3333340000000 %460 = fmul float %456, 0x3FE3333340000000 %461 = call float @llvm.AMDGPU.lrp(float %304, float %332, float %457) %462 = call float @llvm.AMDGPU.lrp(float %304, float %334, float %458) %463 = call float @llvm.AMDGPU.lrp(float %304, float %336, float %459) %464 = call float @llvm.AMDGPU.lrp(float %304, float 0x3FF0000000000000, float %460) %465 = call float @llvm.AMDGPU.lrp(float %220, float %348, float %461) %466 = call float @llvm.AMDGPU.lrp(float %220, float %349, float %462) %467 = call float @llvm.AMDGPU.lrp(float %220, float %350, float %463) %468 = call float @llvm.AMDGPU.lrp(float %220, float %351, float %464) %469 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %470 = extractelement <4 x float> %469, i32 0 %471 = bitcast float %470 to i32 %472 = icmp ne i32 %471, 0 br i1 %472, label %IF54, label %ELSE55 ENDIF50: ; preds = %IF54, %ELSE55, %IF51 %temp20.1 = phi float [ %368, %IF51 ], [ %498, %IF54 ], [ %509, %ELSE55 ] %temp21.0 = phi float [ %369, %IF51 ], [ %500, %IF54 ], [ %510, %ELSE55 ] %temp22.0 = phi float [ %370, %IF51 ], [ %502, %IF54 ], [ %511, %ELSE55 ] %temp23.0 = phi float [ %371, %IF51 ], [ %504, %IF54 ], [ %512, %ELSE55 ] %473 = insertelement <4 x float> undef, float %temp20.1, i32 0 %474 = insertelement <4 x float> %473, float %temp21.0, i32 1 %475 = insertelement <4 x float> %474, float %temp22.0, i32 2 %476 = insertelement <4 x float> %475, float %temp23.0, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %476, i32 0, i32 0) ret void IF54: ; preds = %ELSE52 %477 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %478 = extractelement <4 x float> %477, i32 0 %479 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %480 = extractelement <4 x float> %479, i32 1 %481 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %482 = extractelement <4 x float> %481, i32 2 %483 = call float @llvm.AMDGPU.lrp(float %20, float %348, float %465) %484 = call float @llvm.AMDGPU.lrp(float %20, float %349, float %466) %485 = call float @llvm.AMDGPU.lrp(float %20, float %350, float %467) %486 = call float @llvm.AMDGPU.lrp(float %20, float %351, float %468) %487 = fadd float %435, %483 %488 = fadd float %438, %484 %489 = fadd float %441, %485 %490 = fadd float 0x3FF0000000000000, %486 %491 = fsub float -0,000000e+00, %20 %492 = fadd float 0x3FF0000000000000, %491 %493 = fmul float %487, %492 %494 = fmul float %488, %492 %495 = fmul float %489, %492 %496 = fmul float %490, %492 %497 = fmul float %478, %20 %498 = fadd float %497, %493 %499 = fmul float %480, %20 %500 = fadd float %499, %494 %501 = fmul float %482, %20 %502 = fadd float %501, %495 %503 = fmul float 0x3FF0000000000000, %20 %504 = fadd float %503, %496 br label %ENDIF50 ELSE55: ; preds = %ELSE52 %505 = call float @llvm.AMDGPU.lrp(float %20, float %348, float %465) %506 = call float @llvm.AMDGPU.lrp(float %20, float %349, float %466) %507 = call float @llvm.AMDGPU.lrp(float %20, float %350, float %467) %508 = call float @llvm.AMDGPU.lrp(float %20, float %351, float %468) %509 = fadd float %435, %505 %510 = fadd float %438, %506 %511 = fadd float %441, %507 %512 = fadd float 0x3FF0000000000000, %508 br label %ENDIF50 } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #1 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #3 ; Function Attrs: readnone declare float @llvm.AMDGPU.lrp(float, float, float) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } attributes #3 = { nounwind readonly } ===== SHADER #56 =========================================== PS/RS880/R600 ===== ===== 618 dw ===== 9 gprs ===== 1 stack ======================================== 0000 80000020 a0680000 ALU 27 @64 KC0[CB0:0-31] 0064 8011408b 60400210 1 w: MUL_IEEE R2.w, KC0[11].x, KC0[10].x 0066 801facfe 60600210 2 w: MUL_IEEE R3.w, PV.w, [0x3d75c28f 0,06].x 0068 3d75c28f 0070 001fa001 00a28cfe 3 x: MULADD_IEEE R5.x, R1.x, [0x3c03126f 0,008].x, PV.w 0072 009fac02 40400210 z: MUL_IEEE R2.z, R2.w, [0x3d4ccccd 0,05].y 0074 811fac02 60600210 w: MUL_IEEE R3.w, R2.w, [0x3cac0831 0,021].z 0076 3c03126f 0077 3d4ccccd 0078 3cac0831 0080 001fac02 00600210 4 x: MUL_IEEE R3.x, R2.w, [0x3cf5c28f 0,03].x 0082 009fa401 20828cfe y: MULADD_IEEE R4.y, R1.y, [0x3a83126f 0,001].y, PV.w 0084 011fa001 40a288fe z: MULADD_IEEE R5.z, R1.x, [0x3bc49ba6 0,006].z, PV.z 0086 819fac02 60600210 w: MUL_IEEE R3.w, R2.w, [0x3c9ba5e3 0,019].w 0088 3cf5c28f 0089 3a83126f 0090 3bc49ba6 0091 3c9ba5e3 0092 001fa001 00828cfe 5 x: MULADD_IEEE R4.x, R1.x, [0x3a9d4952 0,0012].x, PV.w 0094 009fa401 20a280fe y: MULADD_IEEE R5.y, R1.y, [0x3c03126f 0,008].y, PV.x 0096 011fac02 40400210 z: MUL_IEEE R2.z, R2.w, [0xbd23d70a -0,04].z 0098 819fac02 60600210 w: MUL_IEEE R3.w, R2.w, [0x3c83126f 0,016].w 0100 3a9d4952 0101 3c03126f 0102 bd23d70a 0103 3c83126f 0104 001fac02 20400210 6 y: MUL_IEEE R2.y, R2.w, [0xbc8b4396 -0,017].x 0106 009fa401 40828cfe z: MULADD_IEEE R4.z, R1.y, [0x3a902de0 0,0011].y, PV.w 0108 811fa401 60a288fe w: MULADD_IEEE R5.w, R1.y, [0x3bc49ba6 0,006].z, PV.z 0110 bc8b4396 0111 3a902de0 0112 3bc49ba6 0114 801fa001 608284fe 7 w: MULADD_IEEE R4.w, R1.x, [0x3a83126f 0,001].x, PV.y 0116 3a83126f 0002 00000010 80800c00 TEX 4 @32 0032 00041310 f00d1003 69318000 SAMPLE R3.xyzw, R4.wzzw, RID:19, SID:3 CT:NNNN 0036 00041310 f00d1004 68818000 SAMPLE R4.xyzw, R4.xyzw, RID:19, SID:3 CT:NNNN 0040 00051310 f00d1006 69a18000 SAMPLE R6.xyzw, R5.zwzw, RID:19, SID:3 CT:NNNN 0044 00051310 f00d1005 68818000 SAMPLE R5.xyzw, R5.xyzw, RID:19, SID:3 CT:NNNN 0004 8000003b a11c0000 ALU 72 @118 KC0[CB0:0-31] 0118 80000002 40401910 8 z: MOV R2.z, R2.x 0120 80000c01 20201910 9 y: MOV R1.y, R1.w 0122 00000801 00201910 10 x: MOV R1.x, R1.z 0124 001fa405 40200210 z: MUL_IEEE R1.z, R5.y, [0x3e800000 0,25].x 0126 801fa005 60200210 w: MUL_IEEE R1.w, R5.x, [0x3e800000 0,25].x 0128 3e800000 0130 001fa006 20e28cfe 11 y: MULADD_IEEE R7.y, R6.x, [0x3e800000 0,25].x, PV.w 0132 001fa406 402288fe z: MULADD_IEEE R1.z, R6.y, [0x3e800000 0,25].x, PV.z 0134 801fa805 60200210 w: MUL_IEEE R1.w, R5.z, [0x3e800000 0,25].x 0136 3e800000 0138 001fa806 20428cfe 12 y: MULADD_IEEE R2.y, R6.z, [0x3e800000 0,25].x, PV.w 0140 009fa404 402288fe z: MULADD_IEEE R1.z, R4.y, [0x3f400000 0,75].y, PV.z 0142 809fa004 602284fe w: MULADD_IEEE R1.w, R4.x, [0x3f400000 0,75].y, PV.y 0144 3e800000 0145 3f400000 0146 00006cfe 00400010 13 x: ADD R2.x, PV.w, R3.x 0148 008068fe 20a00010 y: ADD R5.y, PV.z, R3.y 0150 000000fd 40201910 z: MOV R1.z, [0x3ee38e39 0,444444].x 0152 809fa804 602284fe w: MULADD_IEEE R1.w, R4.z, [0x3f400000 0,75].y, PV.y 0154 3ee38e39 0155 3f400000 0156 01006cfe 20600010 14 y: ADD R3.y, PV.w, R3.z 0158 011fc4fe 406680fd z: MULADD_IEEE R3.z, PV.y, PV.z, [0xbef5c28f -0,48].x VEC_021 0160 811fc0fe 602680fd w: MULADD_IEEE R1.w, PV.x, PV.z, [0xbef5c28f -0,48].x VEC_021 0162 bef5c28f 0164 00106cfe 00400210 15 x: MUL_IEEE R2.x, PV.w, KC0[3].x 0166 001068fe 20400210 y: MUL_IEEE R2.y, PV.z, KC0[3].x 0168 010024fe 402280fd z: MULADD_IEEE R1.z, PV.y, R1.z, [0xbef5c28f -0,48].x 0170 800004fd 60201910 w: MOV R1.w, [0x00000000 0].y 0172 bef5c28f 0173 00000000 0174 00004002 00405000 16 x: DOT4 __.x, R2.x, R2.x 0176 00804402 20405000 y: DOT4 __.y, R2.y, R2.y 0178 01002801 40405000 z: DOT4 __.z, R1.z, R1.z 0180 81802c01 60405010 w: DOT4 R2.w, R1.w, R1.w 0182 801fa08d 40603210 17 z: XOR_INT R3.z, KC0[13].x, [0x80000000 -0].x 0184 80000000 0186 80000c02 60406711 18 t: RECIPSQRT_CLAMPED R2.w, |R2.w| 0188 01804002 00600210 19 x: MUL_IEEE R3.x, R2.x, R2.w 0190 01804402 20600210 y: MUL_IEEE R3.y, R2.y, R2.w 0192 81006800 60600010 w: ADD R3.w, R0.z, R3.z 0194 001040fe 00400210 20 x: MUL_IEEE R2.x, PV.x, KC0[2].x 0196 001044fe 20400210 y: MUL_IEEE R2.y, PV.y, KC0[2].x 0198 81804801 40600210 z: MUL_IEEE R3.z, R1.z, R2.w 0200 8000008c 60406610 21 t: RECIP_IEEE R2.w, KC0[12].x 0202 00004002 00205000 22 x: DOT4 __.x, R2.x, R2.x 0204 00804402 20205000 y: DOT4 __.y, R2.y, R2.y 0206 01006803 40205010 z: DOT4 R1.z, R3.z, R3.z 0208 81802c01 60205000 w: DOT4 __.w, R1.w, R1.w 0210 81804c03 c0000210 23 z: MUL_IEEE_sat R0.z, R3.w, R2.w 0212 80000801 60406711 24 t: RECIPSQRT_CLAMPED R2.w, |R1.z| 0214 00002001 00205000 25 x: DOT4 __.x, R1.x, R1.x 0216 00802401 20205000 y: DOT4 __.y, R1.y, R1.y 0218 01004802 40205010 z: DOT4 R1.z, R2.z, R2.z 0220 81802c01 60205000 w: DOT4 __.w, R1.w, R1.w 0222 01804002 00400210 26 x: MUL_IEEE R2.x, R2.x, R2.w 0224 01804402 20400210 y: MUL_IEEE R2.y, R2.y, R2.w 0226 81804803 40800210 z: MUL_IEEE R4.z, R3.z, R2.w 0228 80000801 60406711 27 t: RECIPSQRT_CLAMPED R2.w, |R1.z| 0230 01804001 00200210 28 x: MUL_IEEE R1.x, R1.x, R2.w 0232 01804401 20200210 y: MUL_IEEE R1.y, R1.y, R2.w 0234 01804802 40200210 z: MUL_IEEE R1.z, R2.z, R2.w 0236 801f008f 60403d10 w: SETNE_INT R2.w, KC0[15].x, 0 0238 00002002 00405010 29 x: DOT4 R2.x, R2.x, R1.x 0240 00802402 20405000 y: DOT4 __.y, R2.y, R1.y 0242 01002804 40405000 z: DOT4 __.z, R4.z, R1.z 0244 81802c01 60405000 w: DOT4 __.w, R1.w, R1.w 0246 801f0c02 00004508 30 P x: PRED_SETNE_INT __.x, R2.w, 0 0248 c0001002 00401910 31 0 x: MOV R2.x, -R2.x 0250 80000c00 60006610 32 t: RECIP_IEEE R0.w, R0.w 0252 81800400 404280f9 33 z: MULADD_IEEE R2.z, R0.y, R0.w, 1.0 0254 80000480 60406610 34 t: RECIP_IEEE R2.w, KC0[0].y 0256 001f8802 20a29c02 35 y: MULADD_IEEE R5.y, R2.z, 0.5, -R2.w 0258 81800000 600280f9 w: MULADD_IEEE R0.w, R0.x, R0.w, 1.0 0260 801f8cfe 00a00210 36 x: MUL_IEEE R5.x, PV.w, 0.5 0006 00000018 80800000 TEX 1 @48 0048 00051010 f00d1007 68800000 SAMPLE R7.xyzw, R5.xyzw, RID:16, SID:0 CT:NNNN 0008 80000083 a0b40000 ALU 46 @262 KC0[CB0:0-31] 0262 000000fd 00001910 37 x: MOV R0.x, [0x33800000 5,96046e-08].x 0264 000004fd 20801910 y: MOV R4.y, [0x37800000 1,52588e-05].y 0266 000008fd 40c01910 z: MOV R6.z, [0x3b800000 0,00390625].z 0268 80000cfd 60801910 w: MOV R4.w, [0x3f800000 1].w 0270 33800000 0271 37800000 0272 3b800000 0273 3f800000 0274 00000007 00005000 38 x: DOT4 __.x, R7.x, R0.x 0276 00808407 20005010 y: DOT4 R0.y, R7.y, R4.y 0278 0100c807 40005000 z: DOT4 __.z, R7.z, R6.z 0280 81808c07 60005000 w: DOT4 __.w, R7.w, R4.w 0282 801f80fe 60000d10 39 w: SETGT_DX10 R0.w, PV.x, 0.5 0284 80800cfe 600380f8 40 w: CNDE_INT R0.w, PV.w, R0.y, 0 0286 001facfe c0400210 41 z: MUL_IEEE_sat R2.z, PV.w, [0x43c80000 400].x 0288 80112403 60000210 w: MUL_IEEE R0.w, R3.y, KC0[9].x 0290 43c80000 0292 00112003 40800210 42 z: MUL_IEEE R4.z, R3.x, KC0[9].x 0294 811fccfe 60028405 w: MULADD_IEEE R0.w, PV.w, PV.z, R5.y 0296 001facfe 40e00410 43 z: MIN R7.z, PV.w, [0x3f7fbe77 0,999].x 0298 810048fe 60028005 w: MULADD_IEEE R0.w, PV.z, R2.z, R5.x 0300 3f7fbe77 0302 001facfe 20000410 44 y: MIN R0.y, PV.w, [0x3f7fbe77 0,999].x 0304 009fa8fe 40a00310 z: MAX R5.z, PV.z, [0x3a83126f 0,001].y 0306 801f3800 60000010 w: ADD R0.w, -R0.z, 1.0 0308 3f7fbe77 0309 3a83126f 0310 019fc002 40800210 45 z: MUL_IEEE R4.z, R2.x, PV.w 0312 801fa4fe 60a00310 w: MAX R5.w, PV.y, [0x3a83126f 0,001].x 0314 3a83126f 0316 00112003 40428005 46 z: MULADD_IEEE R2.z, R3.x, KC0[9].x, R5.x 0318 801f38fe 60400010 w: ADD R2.w, -PV.z, 1.0 0320 80112403 00828405 47 x: MULADD_IEEE R4.x, R3.y, KC0[9].x, R5.y 0322 80000c02 20006310 48 t: LOG_IEEE R0.y, R2.w 0324 00000088 40801910 49 z: MOV R4.z, KC0[8].x 0326 801fa802 60400410 w: MIN R2.w, R2.z, [0x3f7fbe77 0,999].x 0328 3f7fbe77 0330 001facfe 00400310 50 x: MAX R2.x, PV.w, [0x3a83126f 0,001].x 0332 008008fe 40800110 z: MUL R4.z, PV.z, R0.y 0334 809fa004 60600410 w: MIN R3.w, R4.x, [0x3f7fbe77 0,999].y 0336 3a83126f 0337 3f7fbe77 0338 000000fd 00c01910 51 x: MOV R6.x, [0x3f733333 0,95].x 0340 809facfe 20400310 y: MAX R2.y, PV.w, [0x3a83126f 0,001].y 0342 3f733333 0343 3a83126f 0344 80000804 c0806110 52 t: EXP_IEEE_sat R4.z, R4.z 0346 801fa08f 60603d10 53 w: SETNE_INT R3.w, KC0[15].x, [0xffffffff -nan].x 0348 ffffffff 0350 801f0cfe 00004508 54 P x: PRED_SETNE_INT __.x, PV.w, 0 0352 c01f3002 00400010 55 0 x: ADD R2.x, -R2.x, 1.0 0010 0000001a 80800000 TEX 1 @52 0052 00021210 f00d1002 68810000 SAMPLE R2.xyzw, R2.xyzw, RID:18, SID:2 CT:NNNN 0012 800000b1 a4180000 ALU_PUSH_BEFORE 7 @354 KC0[CB0:0-31] 0354 80000890 60601910 56 w: MOV R3.w, KC0[16].z 0356 00000490 00801910 57 x: MOV R4.x, KC0[16].y 0358 00000090 20001910 y: MOV R0.y, KC0[16].x 0360 0000c804 408280fd z: MULADD_IEEE R4.z, R4.z, R6.x, [0x3d4ccccd 0,05].x 0362 801f008f 60c03d10 w: SETNE_INT R6.w, KC0[15].x, 0 0364 3d4ccccd 0366 801f0cfe 00004504 58 M x: PRED_SETNE_INT __.x, PV.w, 0 0014 0000000b 85000000 JUMP @22 0016 000000b8 a0040000 ALU 2 @368 0368 00000c05 00e01910 59 x: MOV R7.x, R5.w 0370 80000805 20e01910 y: MOV R7.y, R5.z 0018 0000001c 80800400 TEX 2 @56 0056 00071110 f00d1007 68808000 SAMPLE R7.xyzw, R7.xyzw, RID:17, SID:1 CT:NNNN 0060 00051010 f00d1005 69300000 SAMPLE R5.xyzw, R5.wzzw, RID:16, SID:0 CT:NNNN 0020 800000ba a19c0000 ALU 104 @372 KC0[CB0:0-31] 0372 00000005 00005010 60 x: DOT4 R0.x, R5.x, R0.x 0374 00808405 20005000 y: DOT4 __.y, R5.y, R4.y 0376 0100c805 40005000 z: DOT4 __.z, R5.z, R6.z 0378 81808c05 60005000 w: DOT4 __.w, R5.w, R4.w 0380 801fa0fe 60800210 61 w: MUL_IEEE R4.w, PV.x, [0x42200000 40].x 0382 42200000 0384 001fa087 00003210 62 x: XOR_INT R0.x, KC0[7].x, [0x80000000 -0].x 0386 001fa487 20803210 y: XOR_INT R4.y, KC0[7].y, [0x80000000 -0].x 0388 001fa887 40a03210 z: XOR_INT R5.z, KC0[7].z, [0x80000000 -0].x 0390 801f2cfe 60800410 w: MIN R4.w, PV.w, 1.0 0392 80000000 0394 00000003 00a05000 63 x: DOT4 __.x, R3.x, R0.x 0396 00808403 20a05010 y: DOT4 R5.y, R3.y, R4.y 0398 0100a803 40a05000 z: DOT4 __.z, R3.z, R5.z 0400 81802c01 60a05000 w: DOT4 __.w, R1.w, R1.w 0402 000060fe 00c00210 64 x: MUL_IEEE R6.x, PV.x, R3.x 0404 008060fe 20c00210 y: MUL_IEEE R6.y, PV.x, R3.y 0406 010060fe 40c00210 z: MUL_IEEE R6.z, PV.x, R3.z 0408 801fac04 60800310 w: MAX R4.w, R4.w, [0x3f4ccccd 0,8].x 0410 3f4ccccd 0412 001f3cfe 00a00010 65 x: ADD R5.x, -PV.w, 1.0 0414 01006405 210288fe y: MULADD_IEEE R8.y, R5.y, R3.z, PV.z 0416 00806405 406284fe z: MULADD_IEEE R3.z, R5.y, R3.y, PV.y 0418 80006405 60a280fe w: MULADD_IEEE R5.w, R5.y, R3.x, PV.x 0420 039fc000 00000010 66 x: ADD R0.x, R0.x, -PV.w 0422 031fc404 20600010 y: ADD R3.y, R4.y, -PV.z 0424 029fc805 40a00010 z: ADD R5.z, R5.z, -PV.y 0426 801fac07 60a00210 w: MUL_IEEE R5.w, R7.w, [0x3f19999a 0,6].x 0428 3f19999a 0430 00000000 00605010 67 x: DOT4 R3.x, R0.x, R0.x 0432 00806403 20605000 y: DOT4 __.y, R3.y, R3.y 0434 0100a805 40605000 z: DOT4 __.z, R5.z, R5.z 0436 81802c01 60605000 w: DOT4 __.w, R1.w, R1.w 0438 8180a005 40628c04 68 z: MULADD_IEEE R3.z, R5.x, R5.w, R4.w 0440 80000003 60a06711 69 t: RECIPSQRT_CLAMPED R5.w, |R3.x| 0442 0180a000 00000210 70 x: MUL_IEEE R0.x, R0.x, R5.w 0444 0180a403 20600210 y: MUL_IEEE R3.y, R3.y, R5.w 0446 0180a805 40a00210 z: MUL_IEEE R5.z, R5.z, R5.w 0448 801f3804 60a80010 w: ADD R5.w, -R4.z, 1.0 VEC_120 0450 00000001 00005010 71 x: DOT4 R0.x, R1.x, R0.x 0452 00806401 20005000 y: DOT4 __.y, R1.y, R3.y 0454 0100a801 40005000 z: DOT4 __.z, R1.z, R5.z 0456 81802c01 60005000 w: DOT4 __.w, R1.w, R1.w 0458 001fa407 20200210 72 y: MUL_IEEE R1.y, R7.y, [0x3f19999a 0,6].x 0460 001fc0fe 402320f8 z: CNDGT R1.z, PV.x, PV.x, 0 0462 81006c05 60200210 w: MUL_IEEE R1.w, R5.w, R3.z 0464 3f19999a 0466 81804804 00028cfe 73 x: MULADD_IEEE R0.x, R4.z, R2.w, PV.w 0468 80000801 20606310 74 t: LOG_IEEE R3.y, R1.z 0470 00000085 40201910 75 z: MOV R1.z, KC0[5].x 0472 80802005 60200210 w: MUL_IEEE R1.w, R5.x, R1.y 0474 00008c04 00228cfe 76 x: MULADD_IEEE R1.x, R4.w, R4.x, PV.w 0476 001fa007 20200210 y: MUL_IEEE R1.y, R7.x, [0x3f19999a 0,6].x 0478 001fa807 40600210 z: MUL_IEEE R3.z, R7.z, [0x3f19999a 0,6].x 0480 808068fe 60280110 w: MUL R1.w, PV.z, R3.y VEC_120 0482 3f19999a 0484 80000c01 00606110 77 t: EXP_IEEE R3.x, R1.w 0486 01006005 20600210 78 y: MUL_IEEE R3.y, R5.x, R3.z 0488 00802005 40200210 z: MUL_IEEE R1.z, R5.x, R1.y 0490 80002c05 60200210 w: MUL_IEEE R1.w, R5.w, R1.x 0492 00804804 00228cfe 79 x: MULADD_IEEE R1.x, R4.z, R2.y, PV.w 0494 00800c04 202688fe y: MULADD_IEEE R1.y, R4.w, R0.y, PV.z VEC_021 0496 01806c04 402a84fe z: MULADD_IEEE R1.z, R4.w, R3.w, PV.y VEC_120 0498 80108003 60200210 w: MUL_IEEE R1.w, R3.x, KC0[4].x 0500 0010ccfe 00600210 80 x: MUL_IEEE R3.x, PV.w, KC0[6].x 0502 0090ccfe 20000210 y: MUL_IEEE R0.y, PV.w, KC0[6].y 0504 011fcc05 40200210 z: MUL_IEEE R1.z, R5.w, PV.z 0506 809fcc05 60600210 w: MUL_IEEE R3.w, R5.w, PV.y 0508 00004804 00828cfe 81 x: MULADD_IEEE R4.x, R4.z, R2.x, PV.w 0510 01004804 206288fe y: MULADD_IEEE R3.y, R4.z, R2.z, PV.z 0512 0110cc01 40600210 z: MUL_IEEE R3.z, R1.w, KC0[6].z 0514 801f0081 60203d10 w: SETNE_INT R1.w, KC0[1].x, 0 0516 801f0cfe 00004208 82 P x: PRED_SETE_INT __.x, PV.w, 0 0518 e0000c00 60200210 83 1 w: MUL_IEEE R1.w, R0.w, R0.x 0520 61804800 40228c01 84 1 z: MULADD_IEEE R1.z, R0.z, R2.w, R1.w 0522 e0002c00 60200210 1 w: MUL_IEEE R1.w, R0.w, R1.x 0524 60008c00 20800210 85 1 y: MUL_IEEE R4.y, R0.w, R4.x 0526 60804800 40828c01 1 z: MULADD_IEEE R4.z, R0.z, R2.y, R1.w 0528 e01f2801 60280010 1 w: ADD R1.w, R1.z, 1.0 VEC_120 0530 61008400 20200010 86 1 y: ADD R1.y, R0.y, R4.z 0532 60806c00 40800210 1 z: MUL_IEEE R4.z, R0.w, R3.y 0534 e0004800 60028404 1 w: MULADD_IEEE R0.w, R0.z, R2.x, R4.y 0536 61800003 00200010 87 1 x: ADD R1.x, R3.x, R0.w 0538 e1004800 60028804 1 w: MULADD_IEEE R0.w, R0.z, R2.z, R4.z 0540 e1800803 40200010 88 1 z: ADD R1.z, R3.z, R0.w 0542 c0008c00 60200210 89 0 w: MUL_IEEE R1.w, R0.w, R4.x 0544 40806c00 40800210 90 0 z: MUL_IEEE R4.z, R0.w, R3.y 0546 c0004800 60228c01 0 w: MULADD_IEEE R1.w, R0.z, R2.x, R1.w 0548 41802003 20200010 91 0 y: ADD R1.y, R3.x, R1.w 0550 40002c00 40200210 0 z: MUL_IEEE R1.z, R0.w, R1.x 0552 c1004800 60228804 0 w: MULADD_IEEE R1.w, R0.z, R2.z, R4.z 0554 41802803 20600010 92 0 y: ADD R3.y, R3.z, R1.w 0556 40804800 406e8801 0 z: MULADD_IEEE R3.z, R0.z, R2.y, R1.z VEC_102 0558 c1800401 60280210 0 w: MUL_IEEE R1.w, R1.y, R0.w VEC_120 0560 4100008e 00228c01 93 0 x: MULADD_IEEE R1.x, KC0[14].x, R0.z, R1.w 0562 41006400 20840010 0 y: ADD R4.y, R0.y, R3.z VEC_021 0564 41800403 406c0210 0 z: MUL_IEEE R3.z, R3.y, R0.w VEC_102 0566 c0000c00 60600210 0 w: MUL_IEEE R3.w, R0.w, R0.x 0568 41804800 20028c03 94 0 y: MULADD_IEEE R0.y, R0.z, R2.w, R3.w 0570 4100088e 40228803 0 z: MULADD_IEEE R1.z, KC0[14].z, R0.z, R3.z 0572 c1800404 604c0210 0 w: MUL_IEEE R2.w, R4.y, R0.w VEC_102 0574 4100048e 20228c02 95 0 y: MULADD_IEEE R1.y, KC0[14].y, R0.z, R2.w 0576 c01f2400 60400010 0 w: ADD R2.w, R0.y, 1.0 0578 c1800c02 60228800 96 0 w: MULADD_IEEE R1.w, R2.w, R0.w, R0.z 0022 0000000e 86800001 ELSE @28 POP:1 0024 00000122 a0480000 ALU 19 @580 0580 801f3804 60800010 97 w: ADD R4.w, -R4.z, 1.0 0582 001fa402 40200210 98 z: MUL_IEEE R1.z, R2.y, [0x3f666666 0,9].x 0584 81004cfe 60200210 w: MUL_IEEE R1.w, PV.w, R2.z 0586 3f666666 0588 001fa002 20200210 99 y: MUL_IEEE R1.y, R2.x, [0x3f4ccccd 0,8].x 0590 01806804 40628cfe z: MULADD_IEEE R3.z, R4.z, R3.w, PV.w 0592 811fcc04 60200210 w: MUL_IEEE R1.w, R4.w, PV.z 0594 3f4ccccd 0596 00008804 20828cfe 100 y: MULADD_IEEE R4.y, R4.z, R4.x, PV.w 0598 011fcc00 40200210 z: MUL_IEEE R1.z, R0.w, PV.z 0600 809fcc04 60280210 w: MUL_IEEE R1.w, R4.w, PV.y VEC_120 0602 00800804 20628cfe 101 y: MULADD_IEEE R3.y, R4.z, R0.y, PV.w 0604 01806800 402e88fe z: MULADD_IEEE R1.z, R0.z, R3.w, PV.z VEC_102 0606 809fcc00 60680210 w: MUL_IEEE R3.w, R0.w, PV.y VEC_120 0608 00008800 20228cfe 102 y: MULADD_IEEE R1.y, R0.z, R4.x, PV.w 0610 809fcc00 60600210 w: MUL_IEEE R3.w, R0.w, PV.y 0612 00800800 00228cfe 103 x: MULADD_IEEE R1.x, R0.z, R0.y, PV.w 0614 81804c04 60428804 w: MULADD_IEEE R2.w, R4.w, R2.w, R4.z 0616 819fcc00 60228800 104 w: MULADD_IEEE R1.w, R0.w, PV.w, R0.z 0026 0000000e 87000001 POP @28 POP:1 0028 c0008000 94600688 EXPORT_DONE PIXEL 0 R1.xyzw VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[19] DCL OUT[2], GENERIC[20] DCL OUT[3], GENERIC[21] DCL CONST[0..14] DCL TEMP[0..9], LOCAL 0: MUL TEMP[0], CONST[2], IN[1].xxxx 1: MAD TEMP[0], CONST[3], IN[1].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[4], IN[1].zzzz, TEMP[0] 3: ADD TEMP[0].xyz, TEMP[0], CONST[5] 4: MOV TEMP[1].z, -IN[0].zzzz 5: MUL TEMP[2].xyz, CONST[2].xyzz, IN[0].xxxx 6: MAD TEMP[2].xyz, CONST[3].xyzz, IN[0].yyyy, TEMP[2].xyzz 7: MAD TEMP[1].xyz, CONST[4].xyzz, TEMP[1].zzzz, TEMP[2].xyzz 8: DP3 TEMP[2].x, TEMP[1].xyzz, TEMP[1].xyzz 9: RSQ TEMP[2].x, TEMP[2].xxxx 10: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xxxx 11: MUL TEMP[2].xyz, CONST[2].xyzz, CONST[14].xxxx 12: MAD TEMP[2].xyz, CONST[3].xyzz, CONST[14].yyyy, TEMP[2].xyzz 13: MAD TEMP[2].xyz, CONST[4].xyzz, CONST[14].zzzz, TEMP[2].xyzz 14: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz 15: RSQ TEMP[3].x, TEMP[3].xxxx 16: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx 17: ADD TEMP[3].xyz, TEMP[0].xyzz, -CONST[1].xyzz 18: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[2].xyzz 19: MUL TEMP[5].xyz, TEMP[1].zxyy, TEMP[2].yzxx 20: MAD TEMP[2].xyz, TEMP[1].yzxx, TEMP[2].zxyy, -TEMP[5].xyzz 21: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[14].wwww 22: DP3 TEMP[2].x, TEMP[3].xyzz, TEMP[2].xyzz 23: MOV TEMP[4].y, TEMP[2].xxxx 24: DP3 TEMP[1].x, TEMP[3].xyzz, TEMP[1].xyzz 25: MUL TEMP[2], CONST[6], CONST[10].xxxx 26: MAD TEMP[2], CONST[7], CONST[10].yyyy, TEMP[2] 27: MAD TEMP[2], CONST[8], CONST[10].zzzz, TEMP[2] 28: MAD TEMP[2], CONST[9], CONST[10].wwww, TEMP[2] 29: MUL TEMP[3], CONST[6], CONST[11].xxxx 30: MAD TEMP[3], CONST[7], CONST[11].yyyy, TEMP[3] 31: MAD TEMP[3], CONST[8], CONST[11].zzzz, TEMP[3] 32: MAD TEMP[3], CONST[9], CONST[11].wwww, TEMP[3] 33: MUL TEMP[5], CONST[6], CONST[12].xxxx 34: MAD TEMP[5], CONST[7], CONST[12].yyyy, TEMP[5] 35: MAD TEMP[5], CONST[8], CONST[12].zzzz, TEMP[5] 36: MAD TEMP[5], CONST[9], CONST[12].wwww, TEMP[5] 37: MUL TEMP[6], CONST[6], CONST[13].xxxx 38: MAD TEMP[6], CONST[7], CONST[13].yyyy, TEMP[6] 39: MAD TEMP[6], CONST[8], CONST[13].zzzz, TEMP[6] 40: MAD TEMP[6], CONST[9], CONST[13].wwww, TEMP[6] 41: MUL TEMP[7], TEMP[2], CONST[4].xxxx 42: MAD TEMP[7], TEMP[3], CONST[4].yyyy, TEMP[7] 43: MAD TEMP[7], TEMP[5], CONST[4].zzzz, TEMP[7] 44: MAD TEMP[7], TEMP[6], CONST[4].wwww, TEMP[7] 45: MUL TEMP[8], TEMP[2], CONST[3].xxxx 46: MAD TEMP[8], TEMP[3], CONST[3].yyyy, TEMP[8] 47: MAD TEMP[8], TEMP[5], CONST[3].zzzz, TEMP[8] 48: MAD TEMP[8], TEMP[6], CONST[3].wwww, TEMP[8] 49: MUL TEMP[9], TEMP[2], CONST[2].xxxx 50: MAD TEMP[9], TEMP[3], CONST[2].yyyy, TEMP[9] 51: MAD TEMP[9], TEMP[5], CONST[2].zzzz, TEMP[9] 52: MAD TEMP[9], TEMP[6], CONST[2].wwww, TEMP[9] 53: MUL TEMP[9], TEMP[9], IN[1].xxxx 54: MAD TEMP[8], TEMP[8], IN[1].yyyy, TEMP[9] 55: MAD TEMP[7], TEMP[7], IN[1].zzzz, TEMP[8] 56: MUL TEMP[2], TEMP[2], CONST[5].xxxx 57: MAD TEMP[2], TEMP[3], CONST[5].yyyy, TEMP[2] 58: MAD TEMP[2], TEMP[5], CONST[5].zzzz, TEMP[2] 59: MAD TEMP[2], TEMP[6], CONST[5].wwww, TEMP[2] 60: ADD TEMP[2], TEMP[7], TEMP[2] 61: MOV TEMP[3].zw, TEMP[4].yyxy 62: MOV TEMP[1].x, TEMP[1].xxxx 63: MUL TEMP[3].xy, TEMP[0].xzzz, CONST[0].xxxx 64: MOV OUT[3], TEMP[1] 65: MOV OUT[1], TEMP[2] 66: MOV OUT[2], TEMP[3] 67: MOV OUT[0], TEMP[2] 68: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %9 = extractelement <4 x float> %8, i32 0 %10 = fmul float %9, %4 %11 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %12 = extractelement <4 x float> %11, i32 1 %13 = fmul float %12, %4 %14 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %15 = extractelement <4 x float> %14, i32 2 %16 = fmul float %15, %4 %17 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %18 = extractelement <4 x float> %17, i32 0 %19 = fmul float %18, %5 %20 = fadd float %19, %10 %21 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %22 = extractelement <4 x float> %21, i32 1 %23 = fmul float %22, %5 %24 = fadd float %23, %13 %25 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %26 = extractelement <4 x float> %25, i32 2 %27 = fmul float %26, %5 %28 = fadd float %27, %16 %29 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %30 = extractelement <4 x float> %29, i32 0 %31 = fmul float %30, %6 %32 = fadd float %31, %20 %33 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %34 = extractelement <4 x float> %33, i32 1 %35 = fmul float %34, %6 %36 = fadd float %35, %24 %37 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %38 = extractelement <4 x float> %37, i32 2 %39 = fmul float %38, %6 %40 = fadd float %39, %28 %41 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %42 = extractelement <4 x float> %41, i32 0 %43 = fadd float %32, %42 %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %45 = extractelement <4 x float> %44, i32 1 %46 = fadd float %36, %45 %47 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %48 = extractelement <4 x float> %47, i32 2 %49 = fadd float %40, %48 %50 = fsub float -0,000000e+00, %2 %51 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %52 = extractelement <4 x float> %51, i32 0 %53 = fmul float %52, %0 %54 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %55 = extractelement <4 x float> %54, i32 1 %56 = fmul float %55, %0 %57 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %58 = extractelement <4 x float> %57, i32 2 %59 = fmul float %58, %0 %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %61 = extractelement <4 x float> %60, i32 0 %62 = fmul float %61, %1 %63 = fadd float %62, %53 %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %65 = extractelement <4 x float> %64, i32 1 %66 = fmul float %65, %1 %67 = fadd float %66, %56 %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %69 = extractelement <4 x float> %68, i32 2 %70 = fmul float %69, %1 %71 = fadd float %70, %59 %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %73 = extractelement <4 x float> %72, i32 0 %74 = fmul float %73, %50 %75 = fadd float %74, %63 %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %77 = extractelement <4 x float> %76, i32 1 %78 = fmul float %77, %50 %79 = fadd float %78, %67 %80 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %81 = extractelement <4 x float> %80, i32 2 %82 = fmul float %81, %50 %83 = fadd float %82, %71 %84 = insertelement <4 x float> undef, float %75, i32 0 %85 = insertelement <4 x float> %84, float %79, i32 1 %86 = insertelement <4 x float> %85, float %83, i32 2 %87 = insertelement <4 x float> %86, float 0,000000e+00, i32 3 %88 = insertelement <4 x float> undef, float %75, i32 0 %89 = insertelement <4 x float> %88, float %79, i32 1 %90 = insertelement <4 x float> %89, float %83, i32 2 %91 = insertelement <4 x float> %90, float 0,000000e+00, i32 3 %92 = call float @llvm.AMDGPU.dp4(<4 x float> %87, <4 x float> %91) %93 = call float @fabs(float %92) %94 = call float @llvm.AMDGPU.rsq(float %93) %95 = fmul float %75, %94 %96 = fmul float %79, %94 %97 = fmul float %83, %94 %98 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %99 = extractelement <4 x float> %98, i32 0 %100 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %101 = extractelement <4 x float> %100, i32 0 %102 = fmul float %99, %101 %103 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %104 = extractelement <4 x float> %103, i32 1 %105 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %106 = extractelement <4 x float> %105, i32 0 %107 = fmul float %104, %106 %108 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %109 = extractelement <4 x float> %108, i32 2 %110 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %111 = extractelement <4 x float> %110, i32 0 %112 = fmul float %109, %111 %113 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %114 = extractelement <4 x float> %113, i32 0 %115 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %116 = extractelement <4 x float> %115, i32 1 %117 = fmul float %114, %116 %118 = fadd float %117, %102 %119 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %120 = extractelement <4 x float> %119, i32 1 %121 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %122 = extractelement <4 x float> %121, i32 1 %123 = fmul float %120, %122 %124 = fadd float %123, %107 %125 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %126 = extractelement <4 x float> %125, i32 2 %127 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %128 = extractelement <4 x float> %127, i32 1 %129 = fmul float %126, %128 %130 = fadd float %129, %112 %131 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %132 = extractelement <4 x float> %131, i32 0 %133 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %134 = extractelement <4 x float> %133, i32 2 %135 = fmul float %132, %134 %136 = fadd float %135, %118 %137 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %138 = extractelement <4 x float> %137, i32 1 %139 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %140 = extractelement <4 x float> %139, i32 2 %141 = fmul float %138, %140 %142 = fadd float %141, %124 %143 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %144 = extractelement <4 x float> %143, i32 2 %145 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %146 = extractelement <4 x float> %145, i32 2 %147 = fmul float %144, %146 %148 = fadd float %147, %130 %149 = insertelement <4 x float> undef, float %136, i32 0 %150 = insertelement <4 x float> %149, float %142, i32 1 %151 = insertelement <4 x float> %150, float %148, i32 2 %152 = insertelement <4 x float> %151, float 0,000000e+00, i32 3 %153 = insertelement <4 x float> undef, float %136, i32 0 %154 = insertelement <4 x float> %153, float %142, i32 1 %155 = insertelement <4 x float> %154, float %148, i32 2 %156 = insertelement <4 x float> %155, float 0,000000e+00, i32 3 %157 = call float @llvm.AMDGPU.dp4(<4 x float> %152, <4 x float> %156) %158 = call float @fabs(float %157) %159 = call float @llvm.AMDGPU.rsq(float %158) %160 = fmul float %136, %159 %161 = fmul float %142, %159 %162 = fmul float %148, %159 %163 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %164 = extractelement <4 x float> %163, i32 0 %165 = fsub float -0,000000e+00, %164 %166 = fadd float %43, %165 %167 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %168 = extractelement <4 x float> %167, i32 1 %169 = fsub float -0,000000e+00, %168 %170 = fadd float %46, %169 %171 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %172 = extractelement <4 x float> %171, i32 2 %173 = fsub float -0,000000e+00, %172 %174 = fadd float %49, %173 %175 = insertelement <4 x float> undef, float %166, i32 0 %176 = insertelement <4 x float> %175, float %170, i32 1 %177 = insertelement <4 x float> %176, float %174, i32 2 %178 = insertelement <4 x float> %177, float 0,000000e+00, i32 3 %179 = insertelement <4 x float> undef, float %160, i32 0 %180 = insertelement <4 x float> %179, float %161, i32 1 %181 = insertelement <4 x float> %180, float %162, i32 2 %182 = insertelement <4 x float> %181, float 0,000000e+00, i32 3 %183 = call float @llvm.AMDGPU.dp4(<4 x float> %178, <4 x float> %182) %184 = fmul float %97, %161 %185 = fmul float %95, %162 %186 = fmul float %96, %160 %187 = fsub float -0,000000e+00, %184 %188 = fmul float %96, %162 %189 = fadd float %188, %187 %190 = fsub float -0,000000e+00, %185 %191 = fmul float %97, %160 %192 = fadd float %191, %190 %193 = fsub float -0,000000e+00, %186 %194 = fmul float %95, %161 %195 = fadd float %194, %193 %196 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %197 = extractelement <4 x float> %196, i32 3 %198 = fmul float %189, %197 %199 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %200 = extractelement <4 x float> %199, i32 3 %201 = fmul float %192, %200 %202 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %203 = extractelement <4 x float> %202, i32 3 %204 = fmul float %195, %203 %205 = insertelement <4 x float> undef, float %166, i32 0 %206 = insertelement <4 x float> %205, float %170, i32 1 %207 = insertelement <4 x float> %206, float %174, i32 2 %208 = insertelement <4 x float> %207, float 0,000000e+00, i32 3 %209 = insertelement <4 x float> undef, float %198, i32 0 %210 = insertelement <4 x float> %209, float %201, i32 1 %211 = insertelement <4 x float> %210, float %204, i32 2 %212 = insertelement <4 x float> %211, float 0,000000e+00, i32 3 %213 = call float @llvm.AMDGPU.dp4(<4 x float> %208, <4 x float> %212) %214 = insertelement <4 x float> undef, float %166, i32 0 %215 = insertelement <4 x float> %214, float %170, i32 1 %216 = insertelement <4 x float> %215, float %174, i32 2 %217 = insertelement <4 x float> %216, float 0,000000e+00, i32 3 %218 = insertelement <4 x float> undef, float %95, i32 0 %219 = insertelement <4 x float> %218, float %96, i32 1 %220 = insertelement <4 x float> %219, float %97, i32 2 %221 = insertelement <4 x float> %220, float 0,000000e+00, i32 3 %222 = call float @llvm.AMDGPU.dp4(<4 x float> %217, <4 x float> %221) %223 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %224 = extractelement <4 x float> %223, i32 0 %225 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %226 = extractelement <4 x float> %225, i32 0 %227 = fmul float %224, %226 %228 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %229 = extractelement <4 x float> %228, i32 1 %230 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %231 = extractelement <4 x float> %230, i32 0 %232 = fmul float %229, %231 %233 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %234 = extractelement <4 x float> %233, i32 2 %235 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %236 = extractelement <4 x float> %235, i32 0 %237 = fmul float %234, %236 %238 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %239 = extractelement <4 x float> %238, i32 3 %240 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %241 = extractelement <4 x float> %240, i32 0 %242 = fmul float %239, %241 %243 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %244 = extractelement <4 x float> %243, i32 0 %245 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %246 = extractelement <4 x float> %245, i32 1 %247 = fmul float %244, %246 %248 = fadd float %247, %227 %249 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %250 = extractelement <4 x float> %249, i32 1 %251 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %252 = extractelement <4 x float> %251, i32 1 %253 = fmul float %250, %252 %254 = fadd float %253, %232 %255 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %256 = extractelement <4 x float> %255, i32 2 %257 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %258 = extractelement <4 x float> %257, i32 1 %259 = fmul float %256, %258 %260 = fadd float %259, %237 %261 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %262 = extractelement <4 x float> %261, i32 3 %263 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %264 = extractelement <4 x float> %263, i32 1 %265 = fmul float %262, %264 %266 = fadd float %265, %242 %267 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %268 = extractelement <4 x float> %267, i32 0 %269 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %270 = extractelement <4 x float> %269, i32 2 %271 = fmul float %268, %270 %272 = fadd float %271, %248 %273 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %274 = extractelement <4 x float> %273, i32 1 %275 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %276 = extractelement <4 x float> %275, i32 2 %277 = fmul float %274, %276 %278 = fadd float %277, %254 %279 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %280 = extractelement <4 x float> %279, i32 2 %281 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %282 = extractelement <4 x float> %281, i32 2 %283 = fmul float %280, %282 %284 = fadd float %283, %260 %285 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %286 = extractelement <4 x float> %285, i32 3 %287 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %288 = extractelement <4 x float> %287, i32 2 %289 = fmul float %286, %288 %290 = fadd float %289, %266 %291 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %292 = extractelement <4 x float> %291, i32 0 %293 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %294 = extractelement <4 x float> %293, i32 3 %295 = fmul float %292, %294 %296 = fadd float %295, %272 %297 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %298 = extractelement <4 x float> %297, i32 1 %299 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %300 = extractelement <4 x float> %299, i32 3 %301 = fmul float %298, %300 %302 = fadd float %301, %278 %303 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %304 = extractelement <4 x float> %303, i32 2 %305 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %306 = extractelement <4 x float> %305, i32 3 %307 = fmul float %304, %306 %308 = fadd float %307, %284 %309 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %310 = extractelement <4 x float> %309, i32 3 %311 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) %312 = extractelement <4 x float> %311, i32 3 %313 = fmul float %310, %312 %314 = fadd float %313, %290 %315 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %316 = extractelement <4 x float> %315, i32 0 %317 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %318 = extractelement <4 x float> %317, i32 0 %319 = fmul float %316, %318 %320 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %321 = extractelement <4 x float> %320, i32 1 %322 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %323 = extractelement <4 x float> %322, i32 0 %324 = fmul float %321, %323 %325 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %326 = extractelement <4 x float> %325, i32 2 %327 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %328 = extractelement <4 x float> %327, i32 0 %329 = fmul float %326, %328 %330 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %331 = extractelement <4 x float> %330, i32 3 %332 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %333 = extractelement <4 x float> %332, i32 0 %334 = fmul float %331, %333 %335 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %336 = extractelement <4 x float> %335, i32 0 %337 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %338 = extractelement <4 x float> %337, i32 1 %339 = fmul float %336, %338 %340 = fadd float %339, %319 %341 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %342 = extractelement <4 x float> %341, i32 1 %343 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %344 = extractelement <4 x float> %343, i32 1 %345 = fmul float %342, %344 %346 = fadd float %345, %324 %347 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %348 = extractelement <4 x float> %347, i32 2 %349 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %350 = extractelement <4 x float> %349, i32 1 %351 = fmul float %348, %350 %352 = fadd float %351, %329 %353 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %354 = extractelement <4 x float> %353, i32 3 %355 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %356 = extractelement <4 x float> %355, i32 1 %357 = fmul float %354, %356 %358 = fadd float %357, %334 %359 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %360 = extractelement <4 x float> %359, i32 0 %361 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %362 = extractelement <4 x float> %361, i32 2 %363 = fmul float %360, %362 %364 = fadd float %363, %340 %365 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %366 = extractelement <4 x float> %365, i32 1 %367 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %368 = extractelement <4 x float> %367, i32 2 %369 = fmul float %366, %368 %370 = fadd float %369, %346 %371 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %372 = extractelement <4 x float> %371, i32 2 %373 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %374 = extractelement <4 x float> %373, i32 2 %375 = fmul float %372, %374 %376 = fadd float %375, %352 %377 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %378 = extractelement <4 x float> %377, i32 3 %379 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %380 = extractelement <4 x float> %379, i32 2 %381 = fmul float %378, %380 %382 = fadd float %381, %358 %383 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %384 = extractelement <4 x float> %383, i32 0 %385 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %386 = extractelement <4 x float> %385, i32 3 %387 = fmul float %384, %386 %388 = fadd float %387, %364 %389 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %390 = extractelement <4 x float> %389, i32 1 %391 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %392 = extractelement <4 x float> %391, i32 3 %393 = fmul float %390, %392 %394 = fadd float %393, %370 %395 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %396 = extractelement <4 x float> %395, i32 2 %397 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %398 = extractelement <4 x float> %397, i32 3 %399 = fmul float %396, %398 %400 = fadd float %399, %376 %401 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %402 = extractelement <4 x float> %401, i32 3 %403 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) %404 = extractelement <4 x float> %403, i32 3 %405 = fmul float %402, %404 %406 = fadd float %405, %382 %407 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %408 = extractelement <4 x float> %407, i32 0 %409 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %410 = extractelement <4 x float> %409, i32 0 %411 = fmul float %408, %410 %412 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %413 = extractelement <4 x float> %412, i32 1 %414 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %415 = extractelement <4 x float> %414, i32 0 %416 = fmul float %413, %415 %417 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %418 = extractelement <4 x float> %417, i32 2 %419 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %420 = extractelement <4 x float> %419, i32 0 %421 = fmul float %418, %420 %422 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %423 = extractelement <4 x float> %422, i32 3 %424 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %425 = extractelement <4 x float> %424, i32 0 %426 = fmul float %423, %425 %427 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %428 = extractelement <4 x float> %427, i32 0 %429 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %430 = extractelement <4 x float> %429, i32 1 %431 = fmul float %428, %430 %432 = fadd float %431, %411 %433 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %434 = extractelement <4 x float> %433, i32 1 %435 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %436 = extractelement <4 x float> %435, i32 1 %437 = fmul float %434, %436 %438 = fadd float %437, %416 %439 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %440 = extractelement <4 x float> %439, i32 2 %441 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %442 = extractelement <4 x float> %441, i32 1 %443 = fmul float %440, %442 %444 = fadd float %443, %421 %445 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %446 = extractelement <4 x float> %445, i32 3 %447 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %448 = extractelement <4 x float> %447, i32 1 %449 = fmul float %446, %448 %450 = fadd float %449, %426 %451 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %452 = extractelement <4 x float> %451, i32 0 %453 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %454 = extractelement <4 x float> %453, i32 2 %455 = fmul float %452, %454 %456 = fadd float %455, %432 %457 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %458 = extractelement <4 x float> %457, i32 1 %459 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %460 = extractelement <4 x float> %459, i32 2 %461 = fmul float %458, %460 %462 = fadd float %461, %438 %463 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %464 = extractelement <4 x float> %463, i32 2 %465 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %466 = extractelement <4 x float> %465, i32 2 %467 = fmul float %464, %466 %468 = fadd float %467, %444 %469 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %470 = extractelement <4 x float> %469, i32 3 %471 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %472 = extractelement <4 x float> %471, i32 2 %473 = fmul float %470, %472 %474 = fadd float %473, %450 %475 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %476 = extractelement <4 x float> %475, i32 0 %477 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %478 = extractelement <4 x float> %477, i32 3 %479 = fmul float %476, %478 %480 = fadd float %479, %456 %481 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %482 = extractelement <4 x float> %481, i32 1 %483 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %484 = extractelement <4 x float> %483, i32 3 %485 = fmul float %482, %484 %486 = fadd float %485, %462 %487 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %488 = extractelement <4 x float> %487, i32 2 %489 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %490 = extractelement <4 x float> %489, i32 3 %491 = fmul float %488, %490 %492 = fadd float %491, %468 %493 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %494 = extractelement <4 x float> %493, i32 3 %495 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) %496 = extractelement <4 x float> %495, i32 3 %497 = fmul float %494, %496 %498 = fadd float %497, %474 %499 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %500 = extractelement <4 x float> %499, i32 0 %501 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %502 = extractelement <4 x float> %501, i32 0 %503 = fmul float %500, %502 %504 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %505 = extractelement <4 x float> %504, i32 1 %506 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %507 = extractelement <4 x float> %506, i32 0 %508 = fmul float %505, %507 %509 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %510 = extractelement <4 x float> %509, i32 2 %511 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %512 = extractelement <4 x float> %511, i32 0 %513 = fmul float %510, %512 %514 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %515 = extractelement <4 x float> %514, i32 3 %516 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %517 = extractelement <4 x float> %516, i32 0 %518 = fmul float %515, %517 %519 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %520 = extractelement <4 x float> %519, i32 0 %521 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %522 = extractelement <4 x float> %521, i32 1 %523 = fmul float %520, %522 %524 = fadd float %523, %503 %525 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %526 = extractelement <4 x float> %525, i32 1 %527 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %528 = extractelement <4 x float> %527, i32 1 %529 = fmul float %526, %528 %530 = fadd float %529, %508 %531 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %532 = extractelement <4 x float> %531, i32 2 %533 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %534 = extractelement <4 x float> %533, i32 1 %535 = fmul float %532, %534 %536 = fadd float %535, %513 %537 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %538 = extractelement <4 x float> %537, i32 3 %539 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %540 = extractelement <4 x float> %539, i32 1 %541 = fmul float %538, %540 %542 = fadd float %541, %518 %543 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %544 = extractelement <4 x float> %543, i32 0 %545 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %546 = extractelement <4 x float> %545, i32 2 %547 = fmul float %544, %546 %548 = fadd float %547, %524 %549 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %550 = extractelement <4 x float> %549, i32 1 %551 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %552 = extractelement <4 x float> %551, i32 2 %553 = fmul float %550, %552 %554 = fadd float %553, %530 %555 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %556 = extractelement <4 x float> %555, i32 2 %557 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %558 = extractelement <4 x float> %557, i32 2 %559 = fmul float %556, %558 %560 = fadd float %559, %536 %561 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %562 = extractelement <4 x float> %561, i32 3 %563 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %564 = extractelement <4 x float> %563, i32 2 %565 = fmul float %562, %564 %566 = fadd float %565, %542 %567 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %568 = extractelement <4 x float> %567, i32 0 %569 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %570 = extractelement <4 x float> %569, i32 3 %571 = fmul float %568, %570 %572 = fadd float %571, %548 %573 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %574 = extractelement <4 x float> %573, i32 1 %575 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %576 = extractelement <4 x float> %575, i32 3 %577 = fmul float %574, %576 %578 = fadd float %577, %554 %579 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %580 = extractelement <4 x float> %579, i32 2 %581 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %582 = extractelement <4 x float> %581, i32 3 %583 = fmul float %580, %582 %584 = fadd float %583, %560 %585 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) %586 = extractelement <4 x float> %585, i32 3 %587 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) %588 = extractelement <4 x float> %587, i32 3 %589 = fmul float %586, %588 %590 = fadd float %589, %566 %591 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %592 = extractelement <4 x float> %591, i32 0 %593 = fmul float %296, %592 %594 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %595 = extractelement <4 x float> %594, i32 0 %596 = fmul float %302, %595 %597 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %598 = extractelement <4 x float> %597, i32 0 %599 = fmul float %308, %598 %600 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %601 = extractelement <4 x float> %600, i32 0 %602 = fmul float %314, %601 %603 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %604 = extractelement <4 x float> %603, i32 1 %605 = fmul float %388, %604 %606 = fadd float %605, %593 %607 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %608 = extractelement <4 x float> %607, i32 1 %609 = fmul float %394, %608 %610 = fadd float %609, %596 %611 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %612 = extractelement <4 x float> %611, i32 1 %613 = fmul float %400, %612 %614 = fadd float %613, %599 %615 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %616 = extractelement <4 x float> %615, i32 1 %617 = fmul float %406, %616 %618 = fadd float %617, %602 %619 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %620 = extractelement <4 x float> %619, i32 2 %621 = fmul float %480, %620 %622 = fadd float %621, %606 %623 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %624 = extractelement <4 x float> %623, i32 2 %625 = fmul float %486, %624 %626 = fadd float %625, %610 %627 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %628 = extractelement <4 x float> %627, i32 2 %629 = fmul float %492, %628 %630 = fadd float %629, %614 %631 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %632 = extractelement <4 x float> %631, i32 2 %633 = fmul float %498, %632 %634 = fadd float %633, %618 %635 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %636 = extractelement <4 x float> %635, i32 3 %637 = fmul float %572, %636 %638 = fadd float %637, %622 %639 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %640 = extractelement <4 x float> %639, i32 3 %641 = fmul float %578, %640 %642 = fadd float %641, %626 %643 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %644 = extractelement <4 x float> %643, i32 3 %645 = fmul float %584, %644 %646 = fadd float %645, %630 %647 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %648 = extractelement <4 x float> %647, i32 3 %649 = fmul float %590, %648 %650 = fadd float %649, %634 %651 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %652 = extractelement <4 x float> %651, i32 0 %653 = fmul float %296, %652 %654 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %655 = extractelement <4 x float> %654, i32 0 %656 = fmul float %302, %655 %657 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %658 = extractelement <4 x float> %657, i32 0 %659 = fmul float %308, %658 %660 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %661 = extractelement <4 x float> %660, i32 0 %662 = fmul float %314, %661 %663 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %664 = extractelement <4 x float> %663, i32 1 %665 = fmul float %388, %664 %666 = fadd float %665, %653 %667 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %668 = extractelement <4 x float> %667, i32 1 %669 = fmul float %394, %668 %670 = fadd float %669, %656 %671 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %672 = extractelement <4 x float> %671, i32 1 %673 = fmul float %400, %672 %674 = fadd float %673, %659 %675 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %676 = extractelement <4 x float> %675, i32 1 %677 = fmul float %406, %676 %678 = fadd float %677, %662 %679 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %680 = extractelement <4 x float> %679, i32 2 %681 = fmul float %480, %680 %682 = fadd float %681, %666 %683 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %684 = extractelement <4 x float> %683, i32 2 %685 = fmul float %486, %684 %686 = fadd float %685, %670 %687 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %688 = extractelement <4 x float> %687, i32 2 %689 = fmul float %492, %688 %690 = fadd float %689, %674 %691 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %692 = extractelement <4 x float> %691, i32 2 %693 = fmul float %498, %692 %694 = fadd float %693, %678 %695 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %696 = extractelement <4 x float> %695, i32 3 %697 = fmul float %572, %696 %698 = fadd float %697, %682 %699 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %700 = extractelement <4 x float> %699, i32 3 %701 = fmul float %578, %700 %702 = fadd float %701, %686 %703 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %704 = extractelement <4 x float> %703, i32 3 %705 = fmul float %584, %704 %706 = fadd float %705, %690 %707 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %708 = extractelement <4 x float> %707, i32 3 %709 = fmul float %590, %708 %710 = fadd float %709, %694 %711 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %712 = extractelement <4 x float> %711, i32 0 %713 = fmul float %296, %712 %714 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %715 = extractelement <4 x float> %714, i32 0 %716 = fmul float %302, %715 %717 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %718 = extractelement <4 x float> %717, i32 0 %719 = fmul float %308, %718 %720 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %721 = extractelement <4 x float> %720, i32 0 %722 = fmul float %314, %721 %723 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %724 = extractelement <4 x float> %723, i32 1 %725 = fmul float %388, %724 %726 = fadd float %725, %713 %727 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %728 = extractelement <4 x float> %727, i32 1 %729 = fmul float %394, %728 %730 = fadd float %729, %716 %731 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %732 = extractelement <4 x float> %731, i32 1 %733 = fmul float %400, %732 %734 = fadd float %733, %719 %735 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %736 = extractelement <4 x float> %735, i32 1 %737 = fmul float %406, %736 %738 = fadd float %737, %722 %739 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %740 = extractelement <4 x float> %739, i32 2 %741 = fmul float %480, %740 %742 = fadd float %741, %726 %743 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %744 = extractelement <4 x float> %743, i32 2 %745 = fmul float %486, %744 %746 = fadd float %745, %730 %747 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %748 = extractelement <4 x float> %747, i32 2 %749 = fmul float %492, %748 %750 = fadd float %749, %734 %751 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %752 = extractelement <4 x float> %751, i32 2 %753 = fmul float %498, %752 %754 = fadd float %753, %738 %755 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %756 = extractelement <4 x float> %755, i32 3 %757 = fmul float %572, %756 %758 = fadd float %757, %742 %759 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %760 = extractelement <4 x float> %759, i32 3 %761 = fmul float %578, %760 %762 = fadd float %761, %746 %763 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %764 = extractelement <4 x float> %763, i32 3 %765 = fmul float %584, %764 %766 = fadd float %765, %750 %767 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %768 = extractelement <4 x float> %767, i32 3 %769 = fmul float %590, %768 %770 = fadd float %769, %754 %771 = fmul float %758, %4 %772 = fmul float %762, %4 %773 = fmul float %766, %4 %774 = fmul float %770, %4 %775 = fmul float %698, %5 %776 = fadd float %775, %771 %777 = fmul float %702, %5 %778 = fadd float %777, %772 %779 = fmul float %706, %5 %780 = fadd float %779, %773 %781 = fmul float %710, %5 %782 = fadd float %781, %774 %783 = fmul float %638, %6 %784 = fadd float %783, %776 %785 = fmul float %642, %6 %786 = fadd float %785, %778 %787 = fmul float %646, %6 %788 = fadd float %787, %780 %789 = fmul float %650, %6 %790 = fadd float %789, %782 %791 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %792 = extractelement <4 x float> %791, i32 0 %793 = fmul float %296, %792 %794 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %795 = extractelement <4 x float> %794, i32 0 %796 = fmul float %302, %795 %797 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %798 = extractelement <4 x float> %797, i32 0 %799 = fmul float %308, %798 %800 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %801 = extractelement <4 x float> %800, i32 0 %802 = fmul float %314, %801 %803 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %804 = extractelement <4 x float> %803, i32 1 %805 = fmul float %388, %804 %806 = fadd float %805, %793 %807 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %808 = extractelement <4 x float> %807, i32 1 %809 = fmul float %394, %808 %810 = fadd float %809, %796 %811 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %812 = extractelement <4 x float> %811, i32 1 %813 = fmul float %400, %812 %814 = fadd float %813, %799 %815 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %816 = extractelement <4 x float> %815, i32 1 %817 = fmul float %406, %816 %818 = fadd float %817, %802 %819 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %820 = extractelement <4 x float> %819, i32 2 %821 = fmul float %480, %820 %822 = fadd float %821, %806 %823 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %824 = extractelement <4 x float> %823, i32 2 %825 = fmul float %486, %824 %826 = fadd float %825, %810 %827 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %828 = extractelement <4 x float> %827, i32 2 %829 = fmul float %492, %828 %830 = fadd float %829, %814 %831 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %832 = extractelement <4 x float> %831, i32 2 %833 = fmul float %498, %832 %834 = fadd float %833, %818 %835 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %836 = extractelement <4 x float> %835, i32 3 %837 = fmul float %572, %836 %838 = fadd float %837, %822 %839 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %840 = extractelement <4 x float> %839, i32 3 %841 = fmul float %578, %840 %842 = fadd float %841, %826 %843 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %844 = extractelement <4 x float> %843, i32 3 %845 = fmul float %584, %844 %846 = fadd float %845, %830 %847 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %848 = extractelement <4 x float> %847, i32 3 %849 = fmul float %590, %848 %850 = fadd float %849, %834 %851 = fadd float %784, %838 %852 = fadd float %786, %842 %853 = fadd float %788, %846 %854 = fadd float %790, %850 %855 = load <4 x float> addrspace(8)* null %856 = extractelement <4 x float> %855, i32 0 %857 = fmul float %43, %856 %858 = load <4 x float> addrspace(8)* null %859 = extractelement <4 x float> %858, i32 0 %860 = fmul float %49, %859 %861 = insertelement <4 x float> undef, float %851, i32 0 %862 = insertelement <4 x float> %861, float %852, i32 1 %863 = insertelement <4 x float> %862, float %853, i32 2 %864 = insertelement <4 x float> %863, float %854, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %864, i32 60, i32 1) %865 = insertelement <4 x float> undef, float %851, i32 0 %866 = insertelement <4 x float> %865, float %852, i32 1 %867 = insertelement <4 x float> %866, float %853, i32 2 %868 = insertelement <4 x float> %867, float %854, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %868, i32 0, i32 2) %869 = insertelement <4 x float> undef, float %857, i32 0 %870 = insertelement <4 x float> %869, float %860, i32 1 %871 = insertelement <4 x float> %870, float %183, i32 2 %872 = insertelement <4 x float> %871, float %213, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %872, i32 1, i32 2) %873 = insertelement <4 x float> undef, float %222, i32 0 %874 = insertelement <4 x float> %873, float %96, i32 1 %875 = insertelement <4 x float> %874, float %97, i32 2 %876 = insertelement <4 x float> %875, float 0,000000e+00, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %876, i32 2, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } attributes #2 = { readonly } ===== SHADER #57 =========================================== VS/RS880/R600 ===== ===== 470 dw ===== 19 gprs ===== 1 stack ======================================= 0000 00000000 89800000 CALL_FS @0 0002 80000008 a1cc0000 ALU 116 @16 KC0[CB0:0-31] 0016 80118086 60000210 1 w: MUL_IEEE R0.w, KC0[6].x, KC0[12].x 0018 80918087 60028cfe 2 w: MULADD_IEEE R0.w, KC0[7].x, KC0[12].y, PV.w 0020 81118088 60028cfe 3 w: MULADD_IEEE R0.w, KC0[8].x, KC0[12].z, PV.w 0022 81918089 60828cfe 4 w: MULADD_IEEE R4.w, KC0[9].x, KC0[12].w, PV.w 0024 8011a886 60000210 5 w: MUL_IEEE R0.w, KC0[6].z, KC0[13].x 0026 8091a887 60028cfe 6 w: MULADD_IEEE R0.w, KC0[7].z, KC0[13].y, PV.w 0028 8111a888 60028cfe 7 w: MULADD_IEEE R0.w, KC0[8].z, KC0[13].z, PV.w 0030 8191a889 60028cfe 8 w: MULADD_IEEE R0.w, KC0[9].z, KC0[13].w, PV.w 0032 80118886 60200210 9 w: MUL_IEEE R1.w, KC0[6].z, KC0[12].x 0034 80918887 60228cfe 10 w: MULADD_IEEE R1.w, KC0[7].z, KC0[12].y, PV.w 0036 81118888 60228cfe 11 w: MULADD_IEEE R1.w, KC0[8].z, KC0[12].z, PV.w 0038 81918889 60a28cfe 12 w: MULADD_IEEE R5.w, KC0[9].z, KC0[12].w, PV.w 0040 80116086 60200210 13 w: MUL_IEEE R1.w, KC0[6].x, KC0[11].x 0042 80916087 60228cfe 14 w: MULADD_IEEE R1.w, KC0[7].x, KC0[11].y, PV.w 0044 81116088 60228cfe 15 w: MULADD_IEEE R1.w, KC0[8].x, KC0[11].z, PV.w 0046 81916089 60c28cfe 16 w: MULADD_IEEE R6.w, KC0[9].x, KC0[11].w, PV.w 0048 80114886 60200210 17 w: MUL_IEEE R1.w, KC0[6].z, KC0[10].x 0050 80914887 60228cfe 18 w: MULADD_IEEE R1.w, KC0[7].z, KC0[10].y, PV.w 0052 81114888 60228cfe 19 w: MULADD_IEEE R1.w, KC0[8].z, KC0[10].z, PV.w 0054 81914889 61228cfe 20 w: MULADD_IEEE R9.w, KC0[9].z, KC0[10].w, PV.w 0056 80108cfe 60200210 21 w: MUL_IEEE R1.w, PV.w, KC0[4].x 0058 80116886 60400210 22 w: MUL_IEEE R2.w, KC0[6].z, KC0[11].x 0060 80916887 60428cfe 23 w: MULADD_IEEE R2.w, KC0[7].z, KC0[11].y, PV.w 0062 81116888 60428cfe 24 w: MULADD_IEEE R2.w, KC0[8].z, KC0[11].z, PV.w 0064 81916889 61028cfe 25 w: MULADD_IEEE R8.w, KC0[9].z, KC0[11].w, PV.w 0066 00908cfe 40028c01 26 z: MULADD_IEEE R0.z, PV.w, KC0[4].y, R1.w 0068 80004882 60200210 w: MUL_IEEE R1.w, KC0[2].z, R2.x 0070 80114086 60400210 27 w: MUL_IEEE R2.w, KC0[6].x, KC0[10].x 0072 80914087 60428cfe 28 w: MULADD_IEEE R2.w, KC0[7].x, KC0[10].y, PV.w 0074 81114088 60428cfe 29 w: MULADD_IEEE R2.w, KC0[8].x, KC0[10].z, PV.w 0076 81914089 61c28cfe 30 w: MULADD_IEEE R14.w, KC0[9].x, KC0[10].w, PV.w 0078 0010ac09 20000210 31 y: MUL_IEEE R0.y, R9.w, KC0[5].x 0080 0010acfe 40680210 z: MUL_IEEE R3.z, PV.w, KC0[5].x VEC_120 0082 80804883 60228c01 w: MULADD_IEEE R1.w, KC0[3].z, R2.y, R1.w 0084 01004884 00628cfe 32 x: MULADD_IEEE R3.x, KC0[4].z, R2.z, PV.w 0086 0090ac06 206288fe y: MULADD_IEEE R3.y, R6.w, KC0[5].y, PV.z 0088 01108c05 400a8800 z: MULADD_IEEE R0.z, R5.w, KC0[4].z, R0.z VEC_120 0090 8090ac08 603284fe w: MULADD_IEEE R1.w, R8.w, KC0[5].y, PV.y VEC_201 0092 0110ac05 00028cfe 33 x: MULADD_IEEE R0.x, R5.w, KC0[5].z, PV.w 0094 01908c00 200a88fe y: MULADD_IEEE R0.y, R0.w, KC0[4].w, PV.z VEC_120 0096 0110ac04 401284fe z: MULADD_IEEE R0.z, R4.w, KC0[5].z, PV.y VEC_201 0098 8110a0fe 60200010 w: ADD R1.w, PV.x, KC0[5].z 0100 8011ac86 60400210 34 w: MUL_IEEE R2.w, KC0[6].w, KC0[13].x 0102 8091ac87 60428cfe 35 w: MULADD_IEEE R2.w, KC0[7].w, KC0[13].y, PV.w 0104 8111ac88 60428cfe 36 w: MULADD_IEEE R2.w, KC0[8].w, KC0[13].z, PV.w 0106 8191ac89 60428cfe 37 w: MULADD_IEEE R2.w, KC0[9].w, KC0[13].w, PV.w 0108 8011c882 61600210 38 w: MUL_IEEE R11.w, KC0[2].z, KC0[14].x 0110 80118486 60600210 39 w: MUL_IEEE R3.w, KC0[6].y, KC0[12].x 0112 80918487 60628cfe 40 w: MULADD_IEEE R3.w, KC0[7].y, KC0[12].y, PV.w 0114 81118488 60628cfe 41 w: MULADD_IEEE R3.w, KC0[8].y, KC0[12].z, PV.w 0116 81918489 60628cfe 42 w: MULADD_IEEE R3.w, KC0[9].y, KC0[12].w, PV.w 0118 80116c86 60e00210 43 w: MUL_IEEE R7.w, KC0[6].w, KC0[11].x 0120 80916c87 60e28cfe 44 w: MULADD_IEEE R7.w, KC0[7].w, KC0[11].y, PV.w 0122 81116c88 60e28cfe 45 w: MULADD_IEEE R7.w, KC0[8].w, KC0[11].z, PV.w 0124 81916c89 61828cfe 46 w: MULADD_IEEE R12.w, KC0[9].w, KC0[11].w, PV.w 0126 80114486 60e00210 47 w: MUL_IEEE R7.w, KC0[6].y, KC0[10].x 0128 80914487 60e28cfe 48 w: MULADD_IEEE R7.w, KC0[7].y, KC0[10].y, PV.w 0130 81114488 60e28cfe 49 w: MULADD_IEEE R7.w, KC0[8].y, KC0[10].z, PV.w 0132 81914489 61428cfe 50 w: MULADD_IEEE R10.w, KC0[9].y, KC0[10].w, PV.w 0134 00004082 40600210 51 z: MUL_IEEE R3.z, KC0[2].x, R2.x 0136 80106cfe 61a00210 w: MUL_IEEE R13.w, PV.w, KC0[3].x 0138 80116486 60e00210 52 w: MUL_IEEE R7.w, KC0[6].y, KC0[11].x 0140 80916487 60e28cfe 53 w: MULADD_IEEE R7.w, KC0[7].y, KC0[11].y, PV.w 0142 81116488 60e28cfe 54 w: MULADD_IEEE R7.w, KC0[8].y, KC0[11].z, PV.w 0144 81916489 60e28cfe 55 w: MULADD_IEEE R7.w, KC0[9].y, KC0[11].w, PV.w 0146 001fa881 20603210 56 y: XOR_INT R3.y, KC0[1].z, [0x80000000 -0].x 0148 00906cfe 40828c0d z: MULADD_IEEE R4.z, PV.w, KC0[3].y, R13.w 0150 80804083 61a28803 w: MULADD_IEEE R13.w, KC0[3].x, R2.y, R3.z 0152 80000000 0154 80114c86 61e00210 57 w: MUL_IEEE R15.w, KC0[6].w, KC0[10].x 0156 80914c87 61e28cfe 58 w: MULADD_IEEE R15.w, KC0[7].w, KC0[10].y, PV.w 0158 81114c88 61e28cfe 59 w: MULADD_IEEE R15.w, KC0[8].w, KC0[10].z, PV.w 0160 81914c89 61e28cfe 60 w: MULADD_IEEE R15.w, KC0[9].w, KC0[10].w, PV.w 0162 0010acfe 40600210 61 z: MUL_IEEE R3.z, PV.w, KC0[5].x 0164 81004084 61a28c0d w: MULADD_IEEE R13.w, KC0[4].x, R2.z, R13.w 0166 0010acfe 00600010 62 x: ADD R3.x, PV.w, KC0[5].x 0168 0090ac0c 208288fe y: MULADD_IEEE R4.y, R12.w, KC0[5].y, PV.z 0170 0010ac0a 40680210 z: MUL_IEEE R3.z, R10.w, KC0[5].x VEC_120 0172 81106c03 62128804 w: MULADD_IEEE R16.w, R3.w, KC0[3].z, R4.z VEC_201 0174 8011a486 61a00210 63 w: MUL_IEEE R13.w, KC0[6].y, KC0[13].x 0176 8091a487 61a28cfe 64 w: MULADD_IEEE R13.w, KC0[7].y, KC0[13].y, PV.w 0178 8111a488 61a28cfe 65 w: MULADD_IEEE R13.w, KC0[8].y, KC0[13].z, PV.w 0180 8191a489 61a28cfe 66 w: MULADD_IEEE R13.w, KC0[9].y, KC0[13].w, PV.w 0182 01906cfe 40828c10 67 z: MULADD_IEEE R4.z, PV.w, KC0[3].w, R16.w 0184 8091c883 62068c0b w: MULADD_IEEE R16.w, KC0[3].z, KC0[14].y, R11.w VEC_021 0186 80118c86 61600210 68 w: MUL_IEEE R11.w, KC0[6].w, KC0[12].x 0188 80918c87 61628cfe 69 w: MULADD_IEEE R11.w, KC0[7].w, KC0[12].y, PV.w 0190 81118c88 62228cfe 70 w: MULADD_IEEE R17.w, KC0[8].w, KC0[12].z, PV.w 0192 8011a086 61600210 71 w: MUL_IEEE R11.w, KC0[6].x, KC0[13].x 0194 8091a087 61628cfe 72 w: MULADD_IEEE R11.w, KC0[7].x, KC0[13].y, PV.w 0196 8111a088 61628cfe 73 w: MULADD_IEEE R11.w, KC0[8].x, KC0[13].z, PV.w 0198 8191a089 61628cfe 74 w: MULADD_IEEE R11.w, KC0[9].x, KC0[13].w, PV.w 0200 01002484 20c00210 75 y: MUL_IEEE R6.y, KC0[4].y, R1.z 0202 00104c0e 40a00210 z: MUL_IEEE R5.z, R14.w, KC0[2].x 0204 80104c09 62480210 w: MUL_IEEE R18.w, R9.w, KC0[2].x VEC_120 0206 00904c08 00a28cfe 76 x: MULADD_IEEE R5.x, R8.w, KC0[2].y, PV.w 0208 00106c0e 20a80210 y: MUL_IEEE R5.y, R14.w, KC0[3].x VEC_120 0210 00904c06 40b288fe z: MULADD_IEEE R5.z, R6.w, KC0[2].y, PV.z VEC_201 0212 80004482 62400210 w: MUL_IEEE R18.w, KC0[2].y, R2.x 0214 00804483 00828cfe 77 x: MULADD_IEEE R4.x, KC0[3].y, R2.y, PV.w 0216 01104c04 20e288fe y: MULADD_IEEE R7.y, R4.w, KC0[2].z, PV.z 0218 00906c06 40aa84fe z: MULADD_IEEE R5.z, R6.w, KC0[3].y, PV.y VEC_120 0220 81104c05 625280fe w: MULADD_IEEE R18.w, R5.w, KC0[2].z, PV.x VEC_201 0222 00002882 00c00210 78 x: MUL_IEEE R6.x, KC0[2].z, R1.x 0224 01904c00 20a28cfe y: MULADD_IEEE R5.y, R0.w, KC0[2].w, PV.w 0226 01106c04 40aa88fe z: MULADD_IEEE R5.z, R4.w, KC0[3].z, PV.z VEC_120 0228 81904c0b 625284fe w: MULADD_IEEE R18.w, R11.w, KC0[2].w, PV.y VEC_201 0230 00106c09 00a00210 79 x: MUL_IEEE R5.x, R9.w, KC0[3].x 0232 00108c0e 21080210 y: MUL_IEEE R8.y, R14.w, KC0[4].x VEC_120 0234 00108c0f 40d00210 z: MUL_IEEE R6.z, R15.w, KC0[4].x VEC_201 0236 80106c0f 61300210 w: MUL_IEEE R9.w, R15.w, KC0[3].x VEC_201 0238 00906c0c 00e28cfe 80 x: MULADD_IEEE R7.x, R12.w, KC0[3].y, PV.w 0240 00908c0c 20e288fe y: MULADD_IEEE R7.y, R12.w, KC0[4].y, PV.z 0242 00908c06 40ca84fe z: MULADD_IEEE R6.z, R6.w, KC0[4].y, PV.y VEC_120 0244 80906c08 60d280fe w: MULADD_IEEE R6.w, R8.w, KC0[3].y, PV.x VEC_201 0246 81106c05 00a28cfe 81 x: MULADD_IEEE R5.x, R5.w, KC0[3].z, PV.w 0004 8000007c a1b80000 ALU 111 @248 KC0[CB0:0-31] 0248 01108c04 21028806 82 y: MULADD_IEEE R8.y, R4.w, KC0[4].z, R6.z 0250 00004c12 40c80210 z: MUL_IEEE R6.z, R18.w, R2.x VEC_120 0252 81906c0b 60928805 w: MULADD_IEEE R4.w, R11.w, KC0[3].w, R5.z VEC_201 0254 00804cfe 010288fe 83 x: MULADD_IEEE R8.x, PV.w, R2.y, PV.z 0256 01908c0b 210284fe y: MULADD_IEEE R8.y, R11.w, KC0[4].w, PV.y 0258 00004405 40a00210 z: MUL_IEEE R5.z, R5.y, R2.x 0260 81906c00 608a8005 w: MULADD_IEEE R4.w, R0.w, KC0[3].w, R5.x VEC_120 0262 00804cfe 20a288fe 84 y: MULADD_IEEE R5.y, PV.w, R2.y, PV.z 0264 010044fe 40a280fe z: MULADD_IEEE R5.z, PV.y, R2.z, PV.x 0266 81918c89 60a28c11 w: MULADD_IEEE R5.w, KC0[9].w, KC0[12].w, R17.w 0268 01108cfe 00a28407 85 x: MULADD_IEEE R5.x, PV.w, KC0[4].z, R7.y 0270 01106cfe 20e28007 y: MULADD_IEEE R7.y, PV.w, KC0[3].z, R7.x 0272 00802883 40d28006 z: MULADD_IEEE R6.z, KC0[3].z, R1.y, R6.x VEC_201 0274 81002884 60800210 w: MUL_IEEE R4.w, KC0[4].z, R1.z 0276 0011c082 00c00210 86 x: MUL_IEEE R6.x, KC0[2].x, KC0[14].x 0278 0011c482 21200210 y: MUL_IEEE R9.y, KC0[2].y, KC0[14].x 0280 00002082 40e00210 z: MUL_IEEE R7.z, KC0[2].x, R1.x 0282 80002482 60c00210 w: MUL_IEEE R6.w, KC0[2].y, R1.x 0284 00802483 00e28cfe 87 x: MULADD_IEEE R7.x, KC0[3].y, R1.y, PV.w 0286 00802083 210288fe y: MULADD_IEEE R8.y, KC0[3].x, R1.y, PV.z 0288 0091c483 40e284fe z: MULADD_IEEE R7.z, KC0[3].y, KC0[14].y, PV.y 0290 8091c083 60c280fe w: MULADD_IEEE R6.w, KC0[3].x, KC0[14].y, PV.x 0292 0111c084 00c28cfe 88 x: MULADD_IEEE R6.x, KC0[4].x, KC0[14].z, PV.w 0294 0111c484 202288fe y: MULADD_IEEE R1.y, KC0[4].y, KC0[14].z, PV.z 0296 03808806 40e00010 z: ADD R7.z, R6.z, -R4.w 0298 81002084 60800210 w: MUL_IEEE R4.w, KC0[4].x, R1.z 0300 039fc408 00200010 89 x: ADD R1.x, R8.y, -PV.w 0302 0280c007 20c00010 y: ADD R6.y, R7.x, -R6.y 0304 0111c884 40228c10 z: MULADD_IEEE R1.z, KC0[4].z, KC0[14].z, R16.w 0306 800000fd 60801910 w: MOV R4.w, [0x00000000 0].x 0308 00000000 0310 0000c006 00c05000 90 x: DOT4 __.x, R6.x, R6.x 0312 00802401 20c05000 y: DOT4 __.y, R1.y, R1.y 0314 01002801 40c05010 z: DOT4 R6.z, R1.z, R1.z 0316 81808c04 60c05000 w: DOT4 __.w, R4.w, R4.w 0318 00002001 00c05000 91 x: DOT4 __.x, R1.x, R1.x 0320 0080c406 20c05000 y: DOT4 __.y, R6.y, R6.y 0322 0100e807 40c05000 z: DOT4 __.z, R7.z, R7.z 0324 81808c04 60c05010 w: DOT4 R6.w, R4.w, R4.w 0326 01906c02 01228407 92 x: MULADD_IEEE R9.x, R2.w, KC0[3].w, R7.y 0328 80104c0f 20e80210 y: MUL_IEEE R7.y, R15.w, KC0[2].x VEC_120 0330 80000c06 41206711 93 t: RECIPSQRT_CLAMPED R9.z, |R6.w| 0332 80000806 61006711 94 t: RECIPSQRT_CLAMPED R8.w, |R6.z| 0334 01810006 00e00210 95 x: MUL_IEEE R7.x, R6.x, R8.w 0336 01012406 20c00210 y: MUL_IEEE R6.y, R6.y, R9.z 0338 00108c0a 41000210 z: MUL_IEEE R8.z, R10.w, KC0[4].x 0340 80904c0c 61328407 w: MULADD_IEEE R9.w, R12.w, KC0[2].y, R7.y VEC_201 0342 01012001 00200210 96 x: MUL_IEEE R1.x, R1.x, R9.z 0344 01104c05 21028cfe y: MULADD_IEEE R8.y, R5.w, KC0[2].z, PV.w 0346 01810801 40200210 z: MUL_IEEE R1.z, R1.z, R8.w 0348 801fc4fe 61200210 w: MUL_IEEE R9.w, PV.y, PV.x 0350 00104c0a 01400210 97 x: MUL_IEEE R10.x, R10.w, KC0[2].x 0352 01810401 20200210 y: MUL_IEEE R1.y, R1.y, R8.w 0354 01012807 40c00210 z: MUL_IEEE R6.z, R7.z, R9.z 0356 811fc0fe 61040210 w: MUL_IEEE R8.w, PV.x, PV.z VEC_021 0358 0000e8fe 01029cfe 98 x: MULADD_IEEE R8.x, PV.z, R7.x, -PV.w 0360 009fc001 20e29c09 y: MULADD_IEEE R7.y, R1.x, PV.y, -R9.w 0362 00904c07 40e280fe z: MULADD_IEEE R7.z, R7.w, KC0[2].y, PV.x 0364 81904c02 610a8408 w: MULADD_IEEE R8.w, R2.w, KC0[2].w, R8.y VEC_120 0366 00802806 01400210 99 x: MUL_IEEE R10.x, R6.z, R1.y 0368 00004cfe 21000210 y: MUL_IEEE R8.y, PV.w, R2.x 0370 01104c03 40e288fe z: MULADD_IEEE R7.z, R3.w, KC0[2].z, PV.z 0372 80908c07 610e8808 w: MULADD_IEEE R8.w, R7.w, KC0[4].y, R8.z VEC_102 0374 01108c03 01628cfe 100 x: MULADD_IEEE R11.x, R3.w, KC0[4].z, PV.w 0376 01904c0d 212a88fe y: MULADD_IEEE R9.y, R13.w, KC0[2].w, PV.z VEC_120 0378 00804009 40e284fe z: MULADD_IEEE R7.z, R9.x, R2.y, PV.y 0380 81908c02 61128005 w: MULADD_IEEE R8.w, R2.w, KC0[4].w, R5.x VEC_201 0382 01004cfe 00a288fe 101 x: MULADD_IEEE R5.x, PV.w, R2.z, PV.z 0384 000044fe 21000210 y: MUL_IEEE R8.y, PV.y, R2.x 0386 0090ac07 40628803 z: MULADD_IEEE R3.z, R7.w, KC0[5].y, R3.z 0388 8110ac05 60aa8404 w: MULADD_IEEE R5.w, R5.w, KC0[5].z, R4.y VEC_120 0390 0190ac02 00428cfe 102 x: MULADD_IEEE R2.x, R2.w, KC0[5].w, PV.w 0392 0110ac03 208a88fe y: MULADD_IEEE R4.y, R3.w, KC0[5].z, PV.z VEC_120 0394 00804804 406284fe z: MULADD_IEEE R3.z, R4.z, R2.y, PV.y 0396 81908c0d 6052800b w: MULADD_IEEE R2.w, R13.w, KC0[4].w, R11.x VEC_201 0398 01004cfe 016288fe 103 x: MULADD_IEEE R11.x, PV.w, R2.z, PV.z 0400 0190ac0d 204284fe y: MULADD_IEEE R2.y, R13.w, KC0[5].w, PV.y 0402 01004484 40628004 z: MULADD_IEEE R3.z, KC0[4].y, R2.z, R4.x 0404 801fc005 61200010 w: ADD R9.w, R5.x, PV.x 0406 0090a8fe 00400010 104 x: ADD R2.x, PV.z, KC0[5].y 0408 009fc0fe 21200010 y: ADD R9.y, PV.x, PV.y 0410 001fa481 40603210 z: XOR_INT R3.z, KC0[1].y, [0x80000000 -0].x 0412 81002406 6042900a w: MULADD_IEEE R2.w, R6.y, R1.z, -R10.x 0414 80000000 0416 0191ccfe 00800210 105 x: MUL_IEEE R4.x, PV.w, KC0[14].w 0418 011fc0fe 20400010 y: ADD R2.y, PV.x, PV.z 0420 0191c407 40800210 z: MUL_IEEE R4.z, R7.y, KC0[14].w 0422 801fa081 60403210 w: XOR_INT R2.w, KC0[1].x, [0x80000000 -0].x 0424 80000000 0426 019fc003 00400010 106 x: ADD R2.x, R3.x, PV.w 0428 0191c008 20880210 y: MUL_IEEE R4.y, R8.x, KC0[14].w VEC_120 0430 00806c01 40600010 z: ADD R3.z, R1.w, R3.y 0432 8190ac0b 604a8800 w: MULADD_IEEE R2.w, R11.w, KC0[5].w, R0.z VEC_120 0434 00008002 01005000 107 x: DOT4 __.x, R2.x, R4.x 0436 00808402 21005000 y: DOT4 __.y, R2.y, R4.y 0438 01008803 41005000 z: DOT4 __.z, R3.z, R4.z 0440 81808c04 61005010 w: DOT4 R8.w, R4.w, R4.w 0442 0000e002 01005000 108 x: DOT4 __.x, R2.x, R7.x 0444 00802402 21005000 y: DOT4 __.y, R2.y, R1.y 0446 01002803 41005010 z: DOT4 R8.z, R3.z, R1.z 0448 81808c04 61005000 w: DOT4 __.w, R4.w, R4.w 0450 01804805 01200010 109 x: ADD R9.x, R5.z, R2.w 0452 00100c01 21000210 y: MUL_IEEE R8.y, R1.w, KC0[0].x 0454 01004400 40028405 z: MULADD_IEEE R0.z, R0.y, R2.z, R5.y 0456 8190ac00 60128000 w: MULADD_IEEE R0.w, R0.w, KC0[5].w, R0.x VEC_201 0458 00100003 01000210 110 x: MUL_IEEE R8.x, R3.x, KC0[0].x 0460 819fc8fe 41200010 z: ADD R9.z, PV.z, PV.w 0462 00002002 00c05010 111 x: DOT4 R6.x, R2.x, R1.x 0464 0080c402 20c05000 y: DOT4 __.y, R2.y, R6.y 0466 0100c803 40c05000 z: DOT4 __.z, R3.z, R6.z 0468 81808c04 60c05000 w: DOT4 __.w, R4.w, R4.w 0006 c004a03c 94400688 EXPORT_DONE POS 60 R9.xyzw VPM 0008 c004c000 93c00688 EXPORT PARAM 0 R9.xyzw VPM 0010 c0044001 93c00688 EXPORT PARAM 1 R8.xyzw VPM 0012 c0034002 94600888 EXPORT_DONE PARAM 2 R6.xyz0 VPM EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_FLOAT, } {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 1, src_format = PIPE_FORMAT_R32G32B32_FLOAT, } ===== SHADER #58 ======================================== FETCH/RS880/R600 ===== ===== 12 dw ===== 3 gprs ===== 0 stack ========================================= 0000 00000002 81000400 VTX 2 @4 0004 7c00a000 8c151001 00080000 VFETCH R1.xyz1, R0.x, RID:160 VERTEX MFC:31 UCF:0 FMT(DTA:48 NUM:0 COMP:0 MODE:1) 0008 7c00a100 8c151002 00080000 VFETCH R2.xyz1, R0.x, RID:161 VERTEX MFC:31 UCF:0 FMT(DTA:48 NUM:0 COMP:0 MODE:1) 0002 00000000 8a000000 RET @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } ===== SHADER #59 =========================================== PS/RS880/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94600688 EXPORT_DONE PIXEL 0 R0.xyzw VPM EOP ===== SHADER_END =============================================================== RemoveFilesRecursively: unlink dir: Ist kein Verzeichnis shm_unlink(/pulse-shm-1380777508) failed: Datei oder Verzeichnis nicht gefunden