diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 1298153..127c605 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -780,6 +780,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl,
 	struct nouveau_bios *bios = nouveau_bios(priv);
 	u16 mask, type, data;
 
+	nv_info(priv, "%s:%d outp %s\n", __func__, __LINE__, outp);
 	if (outp < 4) {
 		type = DCB_OUTPUT_ANALOG;
 		mask = 0;
@@ -802,6 +803,8 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl,
 	mask |= 0x0001 << outp;
 	mask |= 0x0100 << head;
 
+	nv_info(priv, "%s:%d dcb_outp_match(t %u, m %u)\n", __func__,
+		__LINE__, type, mask);
 	data = dcb_outp_match(bios, type, mask, ver, hdr, dcb);
 	if (!data)
 		return 0x0000;
@@ -837,12 +840,18 @@ exec_script(struct nv50_disp_priv *priv, int head, int id)
 		}
 	}
 
+	nv_info(priv, "%s:%d ctrl %u, head %d\n", __func__, __LINE__,
+		ctrl, head);
+
 	if (!(ctrl & (1 << head)))
 		return false;
 	i--;
 
 	data = exec_lookup(priv, head, i, ctrl, &dcb, &ver, &hdr, &cnt, &len, &info);
 	if (data) {
+		nv_info(priv, "%s:%d ctrl %u, head %d\n", __func__, __LINE__,
+			ctrl, head);
+
 		struct nvbios_init init = {
 			.subdev = nv_subdev(priv),
 			.bios = bios,
@@ -887,6 +896,8 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk,
 		}
 	}
 
+	nv_info(priv, "%s:%d ctrl %u, head %d\n", __func__, __LINE__,
+		ctrl, head);
 	if (!(ctrl & (1 << head)))
 		return conf;
 	i--;
@@ -1067,6 +1078,7 @@ nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super)
 
 	/* check whether a vpll change is required */
 	head = ffs((super & 0x00000600) >> 9) - 1;
+	nv_info(priv, "%s:%d head %d\n", __func__, __LINE__, head);
 	if (head >= 0) {
 		u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
 		if (pclk) {
@@ -1074,11 +1086,15 @@ nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super)
 			clk->pll_set(clk, PLL_VPLL0 + head, pclk);
 		}
 
+		nv_info(priv, "%s:%d r[0x%x] 0x%x%d\n", __func__, __LINE__,
+				0x614200 + head * 0x800,
+				nv_rd32(priv, 0x614200 + head * 0x800));
 		nv_mask(priv, 0x614200 + head * 0x800, 0x0000000f, 0x00000000);
 	}
 
 	/* (re)attach the relevant OR to the head */
 	head = ffs((super & 0x00000180) >> 7) - 1;
+	nv_info(priv, "%s:%d head %d\n", __func__, __LINE__, head);
 	if (head >= 0) {
 		u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
 		u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
@@ -1115,6 +1131,9 @@ nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super)
 				data = (conf & 0x0100) ? 0x0101 : 0x0000;
 			}
 
+			nv_info(priv, "%s:%d r[0x%x] 0x%x%d\n", __func__,
+				__LINE__, addr, nv_rd32(priv, data));
+
 			nv_mask(priv, addr, mask, data);
 		}
 	}