-------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } bytecode 12 dw -- 3 gprs -- 0 nstack ------------- shader 0 -- E 0000 00000002 80800400 VTX 2 @4 0004 7C000000 88CD1001 00080000 VFETCH R1.xyzw, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0008 7C000000 88CD1002 00080010 VFETCH R2.xyzw, R0.x +16b, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, } bytecode 8 dw -- 2 gprs -- 0 nstack ------------- shader 1 -- E 0000 00000002 80800000 VTX 1 @4 0004 7C000000 93564001 00080000 VFETCH R1.x001, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:13 NUM:1 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_UINT, } bytecode 8 dw -- 2 gprs -- 0 nstack ------------- shader 2 -- E 0000 00000002 80800000 VTX 1 @4 0004 7C000000 97561001 00080000 VFETCH R1.xy01, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:29 NUM:1 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_UINT, } bytecode 8 dw -- 2 gprs -- 0 nstack ------------- shader 3 -- E 0000 00000002 80800000 VTX 1 @4 0004 7C000000 9BD51001 00080000 VFETCH R1.xyz1, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:47 NUM:1 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, } bytecode 8 dw -- 2 gprs -- 0 nstack ------------- shader 4 -- E 0000 00000002 80800000 VTX 1 @4 0004 7C000000 988D1001 00080000 VFETCH R1.xyzw, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG 0: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: call void @llvm.R600.store.dummy(i32 0) ret void } declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body EG_ExportSwz %T0_XYZW, 0, 0, 7, 7, 7, 7, 84, 1 CF_END_EG # End machine code for function main. -------------------------------------------------------------- bytecode 4 dw -- 1 gprs -- 1 nstack ------------- shader 5 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.interp.input(i32 0, i32 -1) %1 = call float @llvm.R600.interp.input(i32 1, i32 -1) %2 = call float @llvm.R600.interp.input(i32 2, i32 -1) %3 = call float @llvm.R600.interp.input(i32 3, i32 -1) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.interp.input(i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body CF_ALU 4, 0, 0, 0, 0, 0, 0, 3 EG_ExportSwz %T0_XYZW, 0, 0, 0, 1, 2, 3, 84, 1 CF_END_EG PAD ALU_CLAUSE 4 %T0_X = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Y = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_W = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 # End machine code for function main. -------------------------------------------------------------- bytecode 16 dw -- 1 gprs -- 1 nstack ------------- shader 6 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.interp.input(i32 0, i32 -1) %1 = call float @llvm.R600.interp.input(i32 1, i32 -1) %2 = call float @llvm.R600.interp.input(i32 2, i32 -1) %3 = call float @llvm.R600.interp.input(i32 3, i32 -1) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.interp.input(i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body CF_ALU 4, 0, 0, 0, 0, 0, 0, 3 EG_ExportSwz %T0_XYZW, 0, 0, 0, 1, 2, 3, 84, 1 CF_END_EG PAD ALU_CLAUSE 4 %T0_X = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Y = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_W = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 # End machine code for function main. -------------------------------------------------------------- bytecode 16 dw -- 1 gprs -- 1 nstack ------------- shader 7 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) %12 = insertelement <4 x float> undef, float %4, i32 0 %13 = insertelement <4 x float> %12, float %5, i32 1 %14 = insertelement <4 x float> %13, float %6, i32 2 %15 = insertelement <4 x float> %14, float %7, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7 BB#0: derived from LLVM BB %main_body Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X CF_CALL_FS_EG EG_ExportSwz %T1_XYZW, 1, 60, 0, 1, 2, 3, 84, 0 EG_ExportSwz %T2_XYZW, 2, 0, 0, 1, 2, 3, 84, 1 CF_END_EG # End machine code for function main. -------------------------------------------------------------- bytecode 8 dw -- 3 gprs -- 1 nstack ------------- shader 8 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %7, i32 0, i32 0, i32 1) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3 BB#0: derived from LLVM BB %main_body Live Ins: %T1_W %T1_Z %T1_Y %T1_X CF_CALL_FS_EG EG_ExportBuf %T1_XYZW, 0, 0, 4095, 1, 64, 0 EG_ExportSwz %T1_XYZW, 1, 60, 0, 1, 2, 3, 84, 0 EG_ExportSwz %T0_XYZW, 2, 0, 7, 7, 7, 7, 84, 1 CF_END_EG PAD # End machine code for function main. -------------------------------------------------------------- bytecode 12 dw -- 2 gprs -- 1 nstack ------------- shader 9 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.interp.input(i32 0, i32 -1) %1 = call float @llvm.R600.interp.input(i32 1, i32 -1) %2 = call float @llvm.R600.interp.input(i32 2, i32 -1) %3 = call float @llvm.R600.interp.input(i32 3, i32 -1) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.interp.input(i32, i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body EG_ExportSwz %T0_XYZW, 0, 0, 7, 7, 7, 7, 84, 1 CF_END_EG # End machine code for function main. -------------------------------------------------------------- bytecode 4 dw -- 1 gprs -- 1 nstack ------------- shader 10 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } bytecode 12 dw -- 3 gprs -- 0 nstack ------------- shader 11 -- E 0000 00000002 80800400 VTX 2 @4 0004 7C000000 88CD1001 00080000 VFETCH R1.xyzw, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0008 7C000000 88CD1002 00080010 VFETCH R2.xyzw, R0.x +16b, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, } bytecode 8 dw -- 2 gprs -- 0 nstack ------------- shader 12 -- E 0000 00000002 80800000 VTX 1 @4 0004 7C000000 93564001 00080000 VFETCH R1.x001, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:13 NUM:1 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_UINT, } bytecode 8 dw -- 2 gprs -- 0 nstack ------------- shader 13 -- E 0000 00000002 80800000 VTX 1 @4 0004 7C000000 97561001 00080000 VFETCH R1.xy01, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:29 NUM:1 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_UINT, } bytecode 8 dw -- 2 gprs -- 0 nstack ------------- shader 14 -- E 0000 00000002 80800000 VTX 1 @4 0004 7C000000 9BD51001 00080000 VFETCH R1.xyz1, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:47 NUM:1 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, } bytecode 8 dw -- 2 gprs -- 0 nstack ------------- shader 15 -- E 0000 00000002 80800000 VTX 1 @4 0004 7C000000 988D1001 00080000 VFETCH R1.xyzw, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG 0: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: call void @llvm.R600.store.dummy(i32 0) ret void } declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body EG_ExportSwz %T0_XYZW, 0, 0, 7, 7, 7, 7, 84, 1 CF_END_EG # End machine code for function main. -------------------------------------------------------------- bytecode 4 dw -- 1 gprs -- 1 nstack ------------- shader 16 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.interp.input(i32 0, i32 -1) %1 = call float @llvm.R600.interp.input(i32 1, i32 -1) %2 = call float @llvm.R600.interp.input(i32 2, i32 -1) %3 = call float @llvm.R600.interp.input(i32 3, i32 -1) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.interp.input(i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body CF_ALU 4, 0, 0, 0, 0, 0, 0, 3 EG_ExportSwz %T0_XYZW, 0, 0, 0, 1, 2, 3, 84, 1 CF_END_EG PAD ALU_CLAUSE 4 %T0_X = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Y = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_W = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 # End machine code for function main. -------------------------------------------------------------- bytecode 16 dw -- 1 gprs -- 1 nstack ------------- shader 17 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.interp.input(i32 0, i32 -1) %1 = call float @llvm.R600.interp.input(i32 1, i32 -1) %2 = call float @llvm.R600.interp.input(i32 2, i32 -1) %3 = call float @llvm.R600.interp.input(i32 3, i32 -1) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.interp.input(i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body CF_ALU 4, 0, 0, 0, 0, 0, 0, 3 EG_ExportSwz %T0_XYZW, 0, 0, 0, 1, 2, 3, 84, 1 CF_END_EG PAD ALU_CLAUSE 4 %T0_X = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Y = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_W = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 # End machine code for function main. -------------------------------------------------------------- bytecode 16 dw -- 1 gprs -- 1 nstack ------------- shader 18 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) %12 = insertelement <4 x float> undef, float %4, i32 0 %13 = insertelement <4 x float> %12, float %5, i32 1 %14 = insertelement <4 x float> %13, float %6, i32 2 %15 = insertelement <4 x float> %14, float %7, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7 BB#0: derived from LLVM BB %main_body Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X CF_CALL_FS_EG EG_ExportSwz %T1_XYZW, 1, 60, 0, 1, 2, 3, 84, 0 EG_ExportSwz %T2_XYZW, 2, 0, 0, 1, 2, 3, 84, 1 CF_END_EG # End machine code for function main. -------------------------------------------------------------- bytecode 8 dw -- 3 gprs -- 1 nstack ------------- shader 19 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %7, i32 0, i32 0, i32 1) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3 BB#0: derived from LLVM BB %main_body Live Ins: %T1_W %T1_Z %T1_Y %T1_X CF_CALL_FS_EG EG_ExportBuf %T1_XYZW, 0, 0, 4095, 1, 64, 0 EG_ExportSwz %T1_XYZW, 1, 60, 0, 1, 2, 3, 84, 0 EG_ExportSwz %T0_XYZW, 2, 0, 7, 7, 7, 7, 84, 1 CF_END_EG PAD # End machine code for function main. -------------------------------------------------------------- bytecode 12 dw -- 2 gprs -- 1 nstack ------------- shader 20 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.interp.input(i32 0, i32 -1) %1 = call float @llvm.R600.interp.input(i32 1, i32 -1) %2 = call float @llvm.R600.interp.input(i32 2, i32 -1) %3 = call float @llvm.R600.interp.input(i32 3, i32 -1) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.interp.input(i32, i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body EG_ExportSwz %T0_XYZW, 0, 0, 7, 7, 7, 7, 84, 1 CF_END_EG # End machine code for function main. -------------------------------------------------------------- bytecode 4 dw -- 1 gprs -- 1 nstack ------------- shader 21 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, } bytecode 12 dw -- 3 gprs -- 0 nstack ------------- shader 22 -- E 0000 00000002 80800400 VTX 2 @4 0004 7C000000 88CD1001 00080000 VFETCH R1.xyzw, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0008 7C000000 88CD1002 00080010 VFETCH R2.xyzw, R0.x +16b, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, } bytecode 8 dw -- 2 gprs -- 0 nstack ------------- shader 23 -- E 0000 00000002 80800000 VTX 1 @4 0004 7C000000 93564001 00080000 VFETCH R1.x001, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:13 NUM:1 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_UINT, } bytecode 8 dw -- 2 gprs -- 0 nstack ------------- shader 24 -- E 0000 00000002 80800000 VTX 1 @4 0004 7C000000 97561001 00080000 VFETCH R1.xy01, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:29 NUM:1 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_UINT, } bytecode 8 dw -- 2 gprs -- 0 nstack ------------- shader 25 -- E 0000 00000002 80800000 VTX 1 @4 0004 7C000000 9BD51001 00080000 VFETCH R1.xyz1, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:47 NUM:1 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- Vertex elements state: {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, } bytecode 8 dw -- 2 gprs -- 0 nstack ------------- shader 26 -- E 0000 00000002 80800000 VTX 1 @4 0004 7C000000 988D1001 00080000 VFETCH R1.xyzw, R0.x, RID:0 VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1) 0002 00000000 85000000 RET @0 -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG 0: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: call void @llvm.R600.store.dummy(i32 0) ret void } declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body EG_ExportSwz %T0_XYZW, 0, 0, 7, 7, 7, 7, 84, 1 CF_END_EG # End machine code for function main. -------------------------------------------------------------- bytecode 4 dw -- 1 gprs -- 1 nstack ------------- shader 27 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.interp.input(i32 0, i32 -1) %1 = call float @llvm.R600.interp.input(i32 1, i32 -1) %2 = call float @llvm.R600.interp.input(i32 2, i32 -1) %3 = call float @llvm.R600.interp.input(i32 3, i32 -1) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.interp.input(i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body CF_ALU 4, 0, 0, 0, 0, 0, 0, 3 EG_ExportSwz %T0_XYZW, 0, 0, 0, 1, 2, 3, 84, 1 CF_END_EG PAD ALU_CLAUSE 4 %T0_X = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Y = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_W = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 # End machine code for function main. -------------------------------------------------------------- bytecode 16 dw -- 1 gprs -- 1 nstack ------------- shader 28 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.interp.input(i32 0, i32 -1) %1 = call float @llvm.R600.interp.input(i32 1, i32 -1) %2 = call float @llvm.R600.interp.input(i32 2, i32 -1) %3 = call float @llvm.R600.interp.input(i32 3, i32 -1) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.interp.input(i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body CF_ALU 4, 0, 0, 0, 0, 0, 0, 3 EG_ExportSwz %T0_XYZW, 0, 0, 0, 1, 2, 3, 84, 1 CF_END_EG PAD ALU_CLAUSE 4 %T0_X = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Y = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_W = INTERP_LOAD_P0 1, 0, 0, 0, %ArrayBase448, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 # End machine code for function main. -------------------------------------------------------------- bytecode 16 dw -- 1 gprs -- 1 nstack ------------- shader 29 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) %12 = insertelement <4 x float> undef, float %4, i32 0 %13 = insertelement <4 x float> %12, float %5, i32 1 %14 = insertelement <4 x float> %13, float %6, i32 2 %15 = insertelement <4 x float> %14, float %7, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T2_W in %vreg0, %T2_Z in %vreg1, %T2_Y in %vreg2, %T2_X in %vreg3, %T1_W in %vreg4, %T1_Z in %vreg5, %T1_Y in %vreg6, %T1_X in %vreg7 BB#0: derived from LLVM BB %main_body Live Ins: %T2_W %T2_Z %T2_Y %T2_X %T1_W %T1_Z %T1_Y %T1_X CF_CALL_FS_EG EG_ExportSwz %T1_XYZW, 1, 60, 0, 1, 2, 3, 84, 0 EG_ExportSwz %T2_XYZW, 2, 0, 0, 1, 2, 3, 84, 1 CF_END_EG # End machine code for function main. -------------------------------------------------------------- bytecode 8 dw -- 3 gprs -- 1 nstack ------------- shader 30 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %7, i32 0, i32 0, i32 1) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3 BB#0: derived from LLVM BB %main_body Live Ins: %T1_W %T1_Z %T1_Y %T1_X CF_CALL_FS_EG EG_ExportBuf %T1_XYZW, 0, 0, 4095, 1, 64, 0 EG_ExportSwz %T1_XYZW, 1, 60, 0, 1, 2, 3, 84, 0 EG_ExportSwz %T0_XYZW, 2, 0, 7, 7, 7, 7, 84, 1 CF_END_EG PAD # End machine code for function main. -------------------------------------------------------------- bytecode 12 dw -- 2 gprs -- 1 nstack ------------- shader 31 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.interp.input(i32 0, i32 -1) %1 = call float @llvm.R600.interp.input(i32 1, i32 -1) %2 = call float @llvm.R600.interp.input(i32 2, i32 -1) %3 = call float @llvm.R600.interp.input(i32 3, i32 -1) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.interp.input(i32, i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body EG_ExportSwz %T0_XYZW, 0, 0, 7, 7, 7, 7, 84, 1 CF_END_EG # End machine code for function main. -------------------------------------------------------------- bytecode 4 dw -- 1 gprs -- 1 nstack ------------- shader 32 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.interp.input(i32 0, i32 0) %1 = call float @llvm.R600.interp.input(i32 1, i32 0) %2 = call float @llvm.R600.interp.input(i32 2, i32 0) %3 = call float @llvm.R600.interp.input(i32 3, i32 0) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.interp.input(i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T0_X in %vreg0, %T0_Y in %vreg1 BB#0: derived from LLVM BB %main_body Live Ins: %T0_X %T0_Y CF_ALU 4, 0, 0, 0, 0, 0, 0, 7 EG_ExportSwz %T1_XYZW, 0, 0, 0, 1, 2, 3, 84, 1 CF_END_EG PAD ALU_CLAUSE 4 %T0_X = INTERP_ZW 0, 0, 0, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Y = INTERP_ZW 0, 0, 0, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T1_Z = INTERP_ZW 0, 0, 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T1_W = INTERP_ZW 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T1_X = INTERP_XY 0, 0, 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T1_Y = INTERP_XY 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = INTERP_XY 0, 0, 0, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_W = INTERP_XY 0, 0, 0, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 # End machine code for function main. -------------------------------------------------------------- bytecode 24 dw -- 2 gprs -- 1 nstack ------------- shader 33 -- E -------------------------------------- ______________________________________________________________ -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV_SAT OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = load <4 x float> addrspace(8)* null %9 = extractelement <4 x float> %8, i32 0 %10 = fmul float %0, %9 %11 = load <4 x float> addrspace(8)* null %12 = extractelement <4 x float> %11, i32 1 %13 = fmul float %0, %12 %14 = load <4 x float> addrspace(8)* null %15 = extractelement <4 x float> %14, i32 2 %16 = fmul float %0, %15 %17 = load <4 x float> addrspace(8)* null %18 = extractelement <4 x float> %17, i32 3 %19 = fmul float %0, %18 %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %21 = extractelement <4 x float> %20, i32 0 %22 = fmul float %1, %21 %23 = fadd float %22, %10 %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %25 = extractelement <4 x float> %24, i32 1 %26 = fmul float %1, %25 %27 = fadd float %26, %13 %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %29 = extractelement <4 x float> %28, i32 2 %30 = fmul float %1, %29 %31 = fadd float %30, %16 %32 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %33 = extractelement <4 x float> %32, i32 3 %34 = fmul float %1, %33 %35 = fadd float %34, %19 %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %37 = extractelement <4 x float> %36, i32 0 %38 = fmul float %2, %37 %39 = fadd float %38, %23 %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %41 = extractelement <4 x float> %40, i32 1 %42 = fmul float %2, %41 %43 = fadd float %42, %27 %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %45 = extractelement <4 x float> %44, i32 2 %46 = fmul float %2, %45 %47 = fadd float %46, %31 %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %49 = extractelement <4 x float> %48, i32 3 %50 = fmul float %2, %49 %51 = fadd float %50, %35 %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %53 = extractelement <4 x float> %52, i32 0 %54 = fmul float %3, %53 %55 = fadd float %54, %39 %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %57 = extractelement <4 x float> %56, i32 1 %58 = fmul float %3, %57 %59 = fadd float %58, %43 %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %61 = extractelement <4 x float> %60, i32 2 %62 = fmul float %3, %61 %63 = fadd float %62, %47 %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %65 = extractelement <4 x float> %64, i32 3 %66 = fmul float %3, %65 %67 = fadd float %66, %51 %68 = call float @llvm.AMDIL.clamp.(float %4, float firefox: /home/greg/build/llvm-3.3.src/lib/Support/APFloat.cpp:267: void interpretDecimal(llvm::StringRef::iterator, llvm::StringRef::iterator, decimalInfo*): Assertion `(*p == 'e' || *p == 'E') && "Invalid character in significand"' failed.