diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 314dda6..d150bd3 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -1106,18 +1106,28 @@ nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super)
 	head = ffs((super & 0x00000600) >> 9) - 1;
 	if (head >= 0) {
 		u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
+		u32 hval, hreg = 0x614200 + (head * 0x800);
 		if (pclk) {
 			struct nouveau_clock *clk = nouveau_clock(priv);
 			clk->pll_set(clk, PLL_VPLL0 + head, pclk);
 		}
+		exec_clkcmp(priv, head, 0, pclk, &outp);
+
+		if (!outp.location) {
+			hval = 0x00000000;
+		} else {
+			hval = 0x00000001;
+		}
+
+		nv_mask(priv, hreg, 0x0000000f, hval);
 	}
 
 	/* (re)attach the relevant OR to the head */
 	head = ffs((super & 0x00000180) >> 7) - 1;
 	if (head >= 0) {
 		u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
-		u32 hval, hreg = 0x614200 + (head * 0x800);
 		u32 oval, oreg;
+		u32 mask;
 		u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
 		if (conf != ~0) {
 			if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
@@ -1143,22 +1153,21 @@ nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super)
 			if (!outp.location && outp.type == DCB_OUTPUT_ANALOG) {
 				oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800;
 				oval = 0x00000000;
-				hval = 0x00000000;
+				mask = 0xffffffff;
 			} else
 			if (!outp.location) {
 				if (outp.type == DCB_OUTPUT_DP)
 					nv50_disp_intr_unk20_dp(priv, &outp, pclk);
 				oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800;
 				oval = (conf & 0x0100) ? 0x0101 : 0x0000;
-				hval = 0x00000000;
+				mask = 0x00000707;
 			} else {
 				oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800;
 				oval = 0x00000001;
-				hval = 0x00000001;
+				mask = 0x00000707;
 			}
 
-			nv_mask(priv, hreg, 0x0000000f, hval);
-			nv_mask(priv, oreg, 0x00000707, oval);
+			nv_mask(priv, oreg, mask, oval);
 		}
 	}