From b00885376b81057bcbbcc24cd9c206ab92095cb5 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 3 Jul 2013 17:40:53 +0100 Subject: [PATCH] drm/i915: Print out extra information for DRAM channels on gen3/gen4 Useful for tracking down the residual swizzling bugs with L shaped memory. References: https://bugs.freedesktop.org/show_bug.cgi?id=28813 Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c | 17 +++++++++++------ drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index fa1e4ac..c87118a 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1839,12 +1839,17 @@ static int i915_swizzle_info(struct seq_file *m, void *data) swizzle_string(dev_priv->mm.bit_6_swizzle_y)); if (IS_GEN3(dev) || IS_GEN4(dev)) { - seq_printf(m, "DDC = 0x%08x\n", - I915_READ(DCC)); - seq_printf(m, "C0DRB3 = 0x%04x\n", - I915_READ16(C0DRB3)); - seq_printf(m, "C1DRB3 = 0x%04x\n", - I915_READ16(C1DRB3)); + seq_printf(m, "DDC = 0x%08x\n", I915_READ(DCC)); + seq_printf(m, "CHDECMISC = 0x%02x\n", I915_READ8(CHDECMISC)); + seq_printf(m, "C0DRB0 = 0x%04x\n", I915_READ16(C0DRB0)); + seq_printf(m, "C0DRB1 = 0x%04x\n", I915_READ16(C0DRB1)); + seq_printf(m, "C0DRB2 = 0x%04x\n", I915_READ16(C0DRB2)); + seq_printf(m, "C0DRB3 = 0x%04x\n", I915_READ16(C0DRB3)); + seq_printf(m, "C1DRB0 = 0x%04x\n", I915_READ16(C1DRB0)); + seq_printf(m, "C1DRB1 = 0x%04x\n", I915_READ16(C1DRB1)); + seq_printf(m, "C1DRB2 = 0x%04x\n", I915_READ16(C1DRB2)); + seq_printf(m, "C1DRB3 = 0x%04x\n", I915_READ16(C1DRB3)); + seq_printf(m, "C1DRB3 = 0x%04x\n", I915_READ16(C1DRB3)); } else if (IS_GEN6(dev) || IS_GEN7(dev)) { seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", I915_READ(MAD_DIMM_C0)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f2326fc..55706ff 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1408,7 +1408,14 @@ #define CSHRDDR3CTL_DDR3 (1 << 2) /** 965 MCH register controlling DRAM channel configuration */ +#define CHDECMISC 0x10111 +#define C0DRB0 0x10200 +#define C0DRB1 0x10202 +#define C0DRB2 0x10204 #define C0DRB3 0x10206 +#define C1DRB0 0x10600 +#define C1DRB1 0x10602 +#define C1DRB2 0x10604 #define C1DRB3 0x10606 /** snb MCH registers for reading the DRAM channel configuration */ -- 1.8.3.2