From 0a7e39ef695eabfeded59c0d1333929aa276d634 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 3 Jul 2013 17:40:53 +0100 Subject: [PATCH 1/2] drm/i915: Print out extra information for DRAM channels on gen3/gen4 mobiles Useful for tracking down the residual swizzling bugs with L shaped memory. References: https://bugs.freedesktop.org/show_bug.cgi?id=28813 Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index c87118a..932e7c7 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1839,17 +1839,29 @@ static int i915_swizzle_info(struct seq_file *m, void *data) swizzle_string(dev_priv->mm.bit_6_swizzle_y)); if (IS_GEN3(dev) || IS_GEN4(dev)) { - seq_printf(m, "DDC = 0x%08x\n", I915_READ(DCC)); - seq_printf(m, "CHDECMISC = 0x%02x\n", I915_READ8(CHDECMISC)); - seq_printf(m, "C0DRB0 = 0x%04x\n", I915_READ16(C0DRB0)); - seq_printf(m, "C0DRB1 = 0x%04x\n", I915_READ16(C0DRB1)); - seq_printf(m, "C0DRB2 = 0x%04x\n", I915_READ16(C0DRB2)); - seq_printf(m, "C0DRB3 = 0x%04x\n", I915_READ16(C0DRB3)); - seq_printf(m, "C1DRB0 = 0x%04x\n", I915_READ16(C1DRB0)); - seq_printf(m, "C1DRB1 = 0x%04x\n", I915_READ16(C1DRB1)); - seq_printf(m, "C1DRB2 = 0x%04x\n", I915_READ16(C1DRB2)); - seq_printf(m, "C1DRB3 = 0x%04x\n", I915_READ16(C1DRB3)); - seq_printf(m, "C1DRB3 = 0x%04x\n", I915_READ16(C1DRB3)); + if (IS_MOBILE(dev)) { + seq_printf(m, "C0DRB0 = 0x%04x\n", I915_READ16(C0DRB0+0x1000)); + seq_printf(m, "C0DRB1 = 0x%04x\n", I915_READ16(C0DRB1+0x1000)); + seq_printf(m, "C0DRB2 = 0x%04x\n", I915_READ16(C0DRB2+0x1000)); + seq_printf(m, "C0DRB3 = 0x%04x\n", I915_READ16(C0DRB3+0x1000)); + seq_printf(m, "C1DRB0 = 0x%04x\n", I915_READ16(C1DRB0+0x1000)); + seq_printf(m, "C1DRB1 = 0x%04x\n", I915_READ16(C1DRB1+0x1000)); + seq_printf(m, "C1DRB2 = 0x%04x\n", I915_READ16(C1DRB2+0x1000)); + seq_printf(m, "C1DRB3 = 0x%04x\n", I915_READ16(C1DRB3+0x1000)); + seq_printf(m, "C1DRB3 = 0x%04x\n", I915_READ16(C1DRB3+0x1000)); + } else { + seq_printf(m, "DDC = 0x%08x\n", I915_READ(DCC)); + seq_printf(m, "CHDECMISC = 0x%02x\n", I915_READ8(CHDECMISC)); + seq_printf(m, "C0DRB0 = 0x%04x\n", I915_READ16(C0DRB0)); + seq_printf(m, "C0DRB1 = 0x%04x\n", I915_READ16(C0DRB1)); + seq_printf(m, "C0DRB2 = 0x%04x\n", I915_READ16(C0DRB2)); + seq_printf(m, "C0DRB3 = 0x%04x\n", I915_READ16(C0DRB3)); + seq_printf(m, "C1DRB0 = 0x%04x\n", I915_READ16(C1DRB0)); + seq_printf(m, "C1DRB1 = 0x%04x\n", I915_READ16(C1DRB1)); + seq_printf(m, "C1DRB2 = 0x%04x\n", I915_READ16(C1DRB2)); + seq_printf(m, "C1DRB3 = 0x%04x\n", I915_READ16(C1DRB3)); + seq_printf(m, "C1DRB3 = 0x%04x\n", I915_READ16(C1DRB3)); + } } else if (IS_GEN6(dev) || IS_GEN7(dev)) { seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", I915_READ(MAD_DIMM_C0)); -- 1.8.3.2