-------------------------------------------------------------- FRAG DCL IN[0], GENERIC[19], PERSPECTIVE DCL IN[1], GENERIC[20], PERSPECTIVE DCL IN[2], GENERIC[21], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL CONST[2..8] DCL TEMP[0..12], LOCAL IMM[0] FLT32 { 1.0000, -1.0000, 0.0000, 0.0000} 0: DDX TEMP[0].xy, IN[1].xyyy 1: MUL TEMP[1], CONST[8].xxxx, IN[1].xyyy 2: DDY TEMP[1].xy, TEMP[1] 3: MOV TEMP[2].xy, IN[1].xyxx 4: MOV TEMP[3].xy, TEMP[0].xyxx 5: MOV TEMP[4].xy, TEMP[1].xyxx 6: RCP TEMP[5].x, IN[2].zzzz 7: MUL TEMP[5].x, CONST[4].xxxx, TEMP[5].xxxx 8: MIN TEMP[5].x, IMM[0].xxxx, TEMP[5].xxxx 9: MUL TEMP[5].x, TEMP[5].xxxx, CONST[2].yyyy 10: CEIL TEMP[5].x, TEMP[5].xxxx 11: MOV TEMP[6].x, CONST[2].xxxx 12: MOV TEMP[6].y, TEMP[5].xxxx 13: RCP TEMP[7].x, TEMP[5].xxxx 14: MOV TEMP[6].z, TEMP[7].xxxx 15: RCP TEMP[8].x, CONST[2].yyyy 16: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[8].xxxx 17: MUL TEMP[5].x, CONST[2].wwww, TEMP[5].xxxx 18: MOV TEMP[6].w, TEMP[5].xxxx 19: MOV TEMP[5], TEMP[6] 20: DP3 TEMP[6].x, IN[2].xyzz, IN[2].xyzz 21: RSQ TEMP[6].x, TEMP[6].xxxx 22: MUL TEMP[6].xyz, IN[2].xyzz, TEMP[6].xxxx 23: MUL TEMP[6].xy, TEMP[6].xyyy, CONST[2].xxxx 24: MUL TEMP[6].xy, TEMP[6].xyyy, IMM[0].yxxx 25: MUL TEMP[6].xy, TEMP[6].xyyy, TEMP[7].xxxx 26: MOV TEMP[7].x, IMM[0].zzzz 27: BGNLOOP :0 28: SGE TEMP[8].x, TEMP[7].xxxx, TEMP[5].yyyy 29: F2I TEMP[8].x, -TEMP[8] 30: UIF TEMP[8].xxxx :0 31: BRK 32: ENDIF 33: ADD TEMP[9].x, IMM[0].xxxx, -CONST[3].xxxx 34: MOV TEMP[10].xy, TEMP[2].xyyy 35: TXD TEMP[11], TEMP[10], TEMP[3].xyyy, TEMP[4].xyyy, SAMP[0], 2D 36: ADD TEMP[12].x, TEMP[9].xxxx, -TEMP[11].wwww 37: MAD TEMP[2].xy, TEMP[6].xyyy, TEMP[12].xxxx, TEMP[2].xyyy 38: ADD TEMP[7].x, TEMP[7].xxxx, IMM[0].xxxx 39: ENDLOOP :0 40: MOV TEMP[2].xy, TEMP[2].xyyy 41: TXD TEMP[0], TEMP[2], TEMP[0].xyyy, TEMP[1].xyyy, SAMP[1], 2D 42: MUL TEMP[1].x, TEMP[0].wwww, CONST[7].xxxx 43: MOV TEMP[1].w, TEMP[1].xxxx 44: MAD TEMP[2].xyz, IN[0].xyzz, CONST[6].xyzz, CONST[5].xyzz 45: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xyzz 46: MOV OUT[0], TEMP[1] 47: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.interp.input(i32 0, i32 0) %1 = call float @llvm.R600.interp.input(i32 1, i32 0) %2 = call float @llvm.R600.interp.input(i32 2, i32 0) %3 = call float @llvm.R600.interp.input(i32 3, i32 0) %4 = call float @llvm.R600.interp.input(i32 4, i32 0) %5 = call float @llvm.R600.interp.input(i32 5, i32 0) %6 = call float @llvm.R600.interp.input(i32 6, i32 0) %7 = call float @llvm.R600.interp.input(i32 7, i32 0) %8 = call float @llvm.R600.interp.input(i32 8, i32 0) %9 = call float @llvm.R600.interp.input(i32 9, i32 0) %10 = call float @llvm.R600.interp.input(i32 10, i32 0) %11 = call float @llvm.R600.interp.input(i32 11, i32 0) %12 = insertelement <4 x float> undef, float %4, i32 0 %13 = insertelement <4 x float> %12, float %5, i32 1 %14 = insertelement <4 x float> %13, float %5, i32 2 %15 = insertelement <4 x float> %14, float %5, i32 3 %16 = call <4 x float> @llvm.AMDGPU.ddx(<4 x float> %15, i32 17, i32 1, i32 0) %17 = insertelement <4 x float> undef, float %4, i32 0 %18 = insertelement <4 x float> %17, float %5, i32 1 %19 = insertelement <4 x float> %18, float %5, i32 2 %20 = insertelement <4 x float> %19, float %5, i32 3 %21 = call <4 x float> @llvm.AMDGPU.ddx(<4 x float> %20, i32 17, i32 1, i32 0) %22 = extractelement <4 x float> %21, i32 0 %23 = extractelement <4 x float> %21, i32 1 %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %25 = extractelement <4 x float> %24, i32 0 %26 = fmul float %25, %4 %27 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %28 = extractelement <4 x float> %27, i32 0 %29 = fmul float %28, %5 %30 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %31 = extractelement <4 x float> %30, i32 0 %32 = fmul float %31, %5 %33 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %34 = extractelement <4 x float> %33, i32 0 %35 = fmul float %34, %5 %36 = insertelement <4 x float> undef, float %26, i32 0 %37 = insertelement <4 x float> %36, float %29, i32 1 %38 = insertelement <4 x float> %37, float %32, i32 2 %39 = insertelement <4 x float> %38, float %35, i32 3 %40 = call <4 x float> @llvm.AMDGPU.ddy(<4 x float> %39, i32 17, i32 1, i32 0) %41 = insertelement <4 x float> undef, float %26, i32 0 %42 = insertelement <4 x float> %41, float %29, i32 1 %43 = insertelement <4 x float> %42, float %32, i32 2 %44 = insertelement <4 x float> %43, float %35, i32 3 %45 = call <4 x float> @llvm.AMDGPU.ddy(<4 x float> %44, i32 17, i32 1, i32 0) %46 = extractelement <4 x float> %45, i32 0 %47 = extractelement <4 x float> %45, i32 1 %48 = fdiv float 1.000000e+00, %10 %49 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %50 = extractelement <4 x float> %49, i32 0 %51 = fmul float %50, %48 %52 = fcmp uge float 1.000000e+00, %51 %53 = select i1 %52, float %51, float 1.000000e+00 %54 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %55 = extractelement <4 x float> %54, i32 1 %56 = fmul float %53, %55 %57 = call float @ceil(float %56) %58 = fdiv float 1.000000e+00, %57 %59 = insertelement <4 x float> undef, float %8, i32 0 %60 = insertelement <4 x float> %59, float %9, i32 1 %61 = insertelement <4 x float> %60, float %10, i32 2 %62 = insertelement <4 x float> %61, float 0.000000e+00, i32 3 %63 = insertelement <4 x float> undef, float %8, i32 0 %64 = insertelement <4 x float> %63, float %9, i32 1 %65 = insertelement <4 x float> %64, float %10, i32 2 %66 = insertelement <4 x float> %65, float 0.000000e+00, i32 3 %67 = call float @llvm.AMDGPU.dp4(<4 x float> %62, <4 x float> %66) %68 = call float @fabs(float %67) %69 = call float @llvm.AMDGPU.rsq(float %68) %70 = fmul float %8, %69 %71 = fmul float %9, %69 %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %73 = extractelement <4 x float> %72, i32 0 %74 = fmul float %70, %73 %75 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %76 = extractelement <4 x float> %75, i32 0 %77 = fmul float %71, %76 %78 = fmul float %74, -1.000000e+00 %79 = fmul float %77, 1.000000e+00 %80 = fmul float %78, %58 %81 = fmul float %79, %58 %82 = insertelement <4 x float> undef, float %22, i32 0 %83 = insertelement <4 x float> %82, float %23, i32 1 %84 = insertelement <4 x float> %83, float %23, i32 2 %85 = insertelement <4 x float> %84, float %23, i32 3 %86 = insertelement <4 x float> undef, float %46, i32 0 %87 = insertelement <4 x float> %86, float %47, i32 1 %88 = insertelement <4 x float> %87, float %47, i32 2 %89 = insertelement <4 x float> %88, float %47, i32 3 br label %LOOP LOOP: ; preds = %ENDIF, %main_body %temp28.0 = phi float [ 0.000000e+00, %main_body ], [ %158, %ENDIF ] %temp9.0 = phi float [ %5, %main_body ], [ %157, %ENDIF ] %temp8.0 = phi float [ %4, %main_body ], [ %155, %ENDIF ] %90 = fcmp uge float %temp28.0, %57 %91 = select i1 %90, float 1.000000e+00, float 0.000000e+00 %92 = fsub float -0.000000e+00, %91 %93 = fptosi float %92 to i32 %94 = bitcast i32 %93 to float %95 = bitcast float %94 to i32 %96 = icmp ne i32 %95, 0 br i1 %96, label %IF, label %ENDIF IF: ; preds = %LOOP %97 = insertelement <4 x float> undef, float %temp8.0, i32 0 %98 = insertelement <4 x float> %97, float %temp9.0, i32 1 %99 = insertelement <4 x float> %98, float 0.000000e+00, i32 2 %100 = insertelement <4 x float> %99, float 0.000000e+00, i32 3 %101 = insertelement <4 x float> undef, float %22, i32 0 %102 = insertelement <4 x float> %101, float %23, i32 1 %103 = insertelement <4 x float> %102, float %23, i32 2 %104 = insertelement <4 x float> %103, float %23, i32 3 %105 = insertelement <4 x float> undef, float %46, i32 0 %106 = insertelement <4 x float> %105, float %47, i32 1 %107 = insertelement <4 x float> %106, float %47, i32 2 %108 = insertelement <4 x float> %107, float %47, i32 3 %109 = call <4 x float> @llvm.AMDGPU.txd(<4 x float> %100, <4 x float> %104, <4 x float> %108, i32 17, i32 1, i32 2) %110 = extractelement <4 x float> %109, i32 0 %111 = extractelement <4 x float> %109, i32 1 %112 = extractelement <4 x float> %109, i32 2 %113 = extractelement <4 x float> %109, i32 3 %114 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %115 = extractelement <4 x float> %114, i32 0 %116 = fmul float %113, %115 %117 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %118 = extractelement <4 x float> %117, i32 0 %119 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %120 = extractelement <4 x float> %119, i32 0 %121 = fmul float %0, %118 %122 = fadd float %121, %120 %123 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %124 = extractelement <4 x float> %123, i32 1 %125 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %126 = extractelement <4 x float> %125, i32 1 %127 = fmul float %1, %124 %128 = fadd float %127, %126 %129 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %130 = extractelement <4 x float> %129, i32 2 %131 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %132 = extractelement <4 x float> %131, i32 2 %133 = fmul float %2, %130 %134 = fadd float %133, %132 %135 = fmul float %110, %122 %136 = fmul float %111, %128 %137 = fmul float %112, %134 %138 = insertelement <4 x float> undef, float %135, i32 0 %139 = insertelement <4 x float> %138, float %136, i32 1 %140 = insertelement <4 x float> %139, float %137, i32 2 %141 = insertelement <4 x float> %140, float %116, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %141, i32 0, i32 0) ret void ENDIF: ; preds = %LOOP %142 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %143 = extractelement <4 x float> %142, i32 0 %144 = fsub float -0.000000e+00, %143 %145 = fadd float 1.000000e+00, %144 %146 = insertelement <4 x float> undef, float %temp8.0, i32 0 %147 = insertelement <4 x float> %146, float %temp9.0, i32 1 %148 = insertelement <4 x float> %147, float 0.000000e+00, i32 2 %149 = insertelement <4 x float> %148, float 0.000000e+00, i32 3 %150 = call <4 x float> @llvm.AMDGPU.txd(<4 x float> %149, <4 x float> %85, <4 x float> %89, i32 16, i32 0, i32 2) %151 = extractelement <4 x float> %150, i32 3 %152 = fsub float -0.000000e+00, %151 %153 = fadd float %145, %152 %154 = fmul float %80, %153 %155 = fadd float %154, %temp8.0 %156 = fmul float %81, %153 %157 = fadd float %156, %temp9.0 %158 = fadd float %temp28.0, 1.000000e+00 br label %LOOP } ; Function Attrs: readnone declare float @llvm.R600.interp.input(i32, i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.ddx(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.ddy(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readonly declare float @ceil(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.txd(<4 x float>, <4 x float>, <4 x float>, i32, i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %T0_X, %T0_Y, %T0_X, %T0_Y, %T0_X, %T0_Y, %T0_X, %T0_Y, %T0_X, %T0_Y, %T0_X, %T0_Y, %T0_X, %T0_Y, %T0_X, %T0_Y BB#0: derived from LLVM BB %main_body Live Ins: %T0_X %T0_Y %T0_X %T0_Y %T0_X %T0_Y %T0_X %T0_Y %T0_X %T0_Y %T0_X %T0_Y %T0_X %T0_Y %T0_X %T0_Y CF_ALU 38, 0, 0, 2, 0, 0, 0, 13 CF_TC_EG 22, 1 CF_ALU 52, 0, 0, 0, 0, 0, 0, 7 CF_TC_EG 26, 1 CF_ALU 60, 0, 0, 2, 0, 0, 0, 26 WHILE_LOOP_EG 14 CF_ALU_PUSH_BEFORE 87, 0, 0, 0, 0, 0, 0, 1 CF_JUMP_EG 10, 1 LOOP_BREAK_EG 13 POP_EG 10, 1 CF_ALU 89, 0, 0, 0, 0, 0, 0, 2 CF_TC_EG 30, 0 CF_ALU 92, 0, 0, 2, 0, 0, 0, 6 END_LOOP_EG 6 CF_ALU 99, 0, 0, 0, 0, 0, 0, 3 CF_TC_EG 32, 1 CF_ALU 103, 0, 0, 0, 0, 0, 0, 2 CF_TC_EG 36, 0 CF_ALU 106, 0, 0, 2, 0, 0, 0, 6 EG_ExportSwz %T2_XYZW, 0, 0, 0, 1, 2, 3, 84, 1 CF_END_EG PAD FETCH_CLAUSE 22 %T2_XYZW = TEX_GET_GRADIENTS_H %T1_XYZW, 0, 1, 1, 1, 0, 0, 0, 0, 1, 2, 3, 17, 1, 1, 1, 1, 1 %T3_XYZW = TEX_GET_GRADIENTS_V %T1_XYZW, 3, 2, 2, 2, 0, 0, 0, 0, 1, 2, 3, 17, 1, 1, 1, 1, 1 FETCH_CLAUSE 26 %T5_XYZW = TEX_SET_GRADIENTS_V %T5_XYZW, 0, 1, 2, 3, 0, 0, 0, 0, 1, 2, 3, 16, 0, 1, 1, 1, 1 %T6_XYZW = TEX_SET_GRADIENTS_H %T6_XYZW, 0, 1, 2, 3, 0, 0, 0, 0, 1, 2, 3, 16, 0, 1, 1, 1, 1 FETCH_CLAUSE 30 %T8_XYZW = TEX_SAMPLE_G %T1_XYZW, 0, 1, 2, 3, 0, 0, 0, 0, 1, 2, 3, 16, 0, 1, 1, 1, 1, %T6_XYZW, %T5_XYZW FETCH_CLAUSE 32 %T2_XYZW = TEX_SET_GRADIENTS_V %T2_XYZW, 0, 1, 2, 3, 0, 0, 0, 0, 1, 2, 3, 17, 1, 1, 1, 1, 1 %T3_XYZW = TEX_SET_GRADIENTS_H %T3_XYZW, 0, 1, 2, 3, 0, 0, 0, 0, 1, 2, 3, 17, 1, 1, 1, 1, 1 FETCH_CLAUSE 36 %T1_XYZW = TEX_SAMPLE_G %T1_XYZW, 0, 1, 2, 3, 0, 0, 0, 0, 1, 2, 3, 17, 1, 1, 1, 1, 1, %T3_XYZW, %T2_XYZW ALU_CLAUSE 38 %T0_X = INTERP_ZW 0, 0, 0, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase450, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Y = INTERP_ZW 0, 0, 0, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase450, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = INTERP_ZW 0, 0, 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase450, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_W = INTERP_ZW 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase450, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T4_X = INTERP_XY 0, 0, 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase450, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T4_Y = INTERP_XY 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase450, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = INTERP_XY 0, 0, 0, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase450, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_W = INTERP_XY 0, 0, 0, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase450, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T1_X = INTERP_XY 0, 0, 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase449, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T1_Y = INTERP_XY 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase449, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = INTERP_XY 0, 0, 0, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase449, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_W = INTERP_XY 0, 0, 0, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase449, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T1_Z = MUL_IEEE 0, 0, 1, 0, 0, 0, %KC0_136_X, 0, 0, 0, 2080, %PV_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW, %T1_XYZW %T1_W = MUL_IEEE 0, 0, 1, 0, 0, 0, %KC0_136_X, 0, 0, 0, 2080, %T1_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW, %T1_XYZW ALU_CLAUSE 52 %T6_X = MOV 1, 0, 0, 0, %T3_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T6_XYZW %T5_X = MOV 1, 0, 0, 0, %T2_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0, %T5_XYZW %T6_Y = MOV 1, 0, 0, 0, %T3_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T6_XYZW %T5_Y = MOV 1, 0, 0, 0, %T2_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0, %T5_XYZW %T6_Z = MOV 1, 0, 0, 0, %T3_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 2, %T6_XYZW %T5_Z = MOV 1, 0, 0, 0, %T2_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0, %T5_XYZW %T6_W = MOV 1, 0, 0, 0, %T3_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 2, %T6_XYZW %T5_W = MOV 1, 0, 0, 0, %T2_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T5_XYZW ALU_CLAUSE 60 %T0_W = RECIP_IEEE_eg 1, 0, 0, 0, %T0_Z, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T0_W = MUL_IEEE 0, 0, 1, 0, 0, 0, %KC0_132_X, 0, 0, 0, 2064, %PS, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T4_Z = MIN 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ONE, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_W = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 LITERALS 0, 0 %T0_X = DOT4_eg 0, 0, 0, 0, 0, 0, %T4_X, 0, 0, 0, -1, %T4_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Y = DOT4_eg 0, 0, 0, 0, 0, 0, %T4_Y, 0, 0, 0, -1, %T4_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = DOT4_eg 0, 0, 1, 0, 0, 0, %T0_Z, 0, 0, 0, -1, %T0_Z, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_W = DOT4_eg 0, 0, 0, 0, 0, 0, %T0_W, 0, 0, 0, -1, %T0_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T4_W = MUL_IEEE 0, 0, 1, 0, 0, 0, %T4_Z, 0, 0, 0, -1, %KC0_130_Y, 0, 0, 0, 2057, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = RECIPSQRT_CLAMPED_eg 1, 0, 0, 0, %PV_X, 0, 0, 1, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T7_Y = CEIL 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T4_Z = MUL_IEEE 0, 0, 1, 0, 0, 0, %T4_X, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T4_W = MUL_IEEE 0, 0, 1, 0, 0, 0, %T4_Y, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = MUL_IEEE 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %KC0_130_X, 0, 0, 0, 2056, 0, pred:%PRED_SEL_OFF, 0, 0 %T4_W = MUL_IEEE 0, 0, 1, 0, 0, 0, %PV_Z, 0, 0, 0, -1, %KC0_130_X, 0, 0, 0, 2056, 0, pred:%PRED_SEL_OFF, 0, 0 %T4_X = RECIP_IEEE_eg 1, 0, 0, 0, %PV_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T4_Z = MUL_IEEE 0, 0, 1, 0, 0, 0, %PV_W, 1, 0, 0, -1, %PS, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T4_W = MUL_IEEE 0, 0, 1, 0, 0, 0, %PV_Z, 0, 0, 0, -1, %PS, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T0_X = INTERP_ZW 0, 0, 0, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Y = INTERP_ZW 0, 0, 0, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = INTERP_ZW 0, 0, 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T7_W = INTERP_ZW 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T0_X = INTERP_XY 0, 0, 1, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Y = INTERP_XY 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_Z = INTERP_XY 0, 0, 0, 0, 0, 0, %T0_Y, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T0_W = INTERP_XY 0, 0, 0, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ArrayBase448, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 ALU_CLAUSE 87 %T7_W = SETGT_DX10 0, 0, 1, 0, 0, 0, %T7_Y, 0, 0, 0, -1, %T0_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %PREDICATE_BIT = PRED_SETE_INT 1, 0, 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ZERO, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 ALU_CLAUSE 89 %T1_Z = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW, %T1_XYZW LITERALS 0, 0 %T1_W = MOV 1, 0, 0, 0, %PV_Z, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW ALU_CLAUSE 92 %T7_W = XOR_INT 0, 0, 1, 0, 0, 0, %KC0_131_X, 0, 0, 0, 2060, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, -2147483648, 0 LITERALS 2147483648, 0 %T7_W = ADD 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %ONE, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T7_W = ADD 0, 0, 1, 0, 0, 0, %PV_W, 0, 0, 0, -1, %T8_W, 1, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T8_XYZW %T1_X = MULADD_IEEE_eg 0, 0, %T4_Z, 0, 0, -1, %PV_W, 0, 0, -1, %T1_X, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW, %T1_XYZW %T1_Y = MULADD_IEEE_eg 0, 0, %T4_W, 0, 0, -1, %T7_W, 0, 0, -1, %T1_Y, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW, %T1_XYZW %T0_W = ADD 0, 0, 1, 0, 0, 0, %T0_W, 0, 0, 0, -1, %ONE, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 4 ALU_CLAUSE 99 %T3_Z = MOV 1, 0, 0, 0, %T3_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T3_XYZW %T2_Z = MOV 1, 0, 0, 0, %T2_Y, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0, %T2_XYZW %T3_W = MOV 1, 0, 0, 0, %T3_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 2, %T3_XYZW %T2_W = MOV 1, 0, 0, 0, %T2_Y, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T2_XYZW ALU_CLAUSE 103 %T1_Z = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW, %T1_XYZW LITERALS 0, 0 %T1_W = MOV 1, 0, 0, 0, %PV_Z, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW ALU_CLAUSE 106 %T0_W = MULADD_IEEE_eg 0, 0, %T0_X, 0, 0, -1, %KC0_134_X, 0, 0, 2072, %KC0_133_X, 0, 0, 2068, 1, pred:%PRED_SEL_OFF, 0, 0 %T2_X = MUL_IEEE 0, 0, 1, 0, 0, 0, %T1_X, 0, 0, 0, -1, %PV_W, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0, %T2_XYZW %T0_W = MULADD_IEEE_eg 0, 0, %T0_Z, 0, 0, -1, %KC0_134_Z, 0, 0, 2074, %KC0_133_Z, 0, 0, 2070, 1, pred:%PRED_SEL_OFF, 0, 0 %T2_W = MUL_IEEE 0, 0, 1, 0, 0, 0, %T1_W, 0, 0, 0, -1, %KC0_135_X, 0, 0, 0, 2076, 1, pred:%PRED_SEL_OFF, 0, 0, %T2_XYZW, %T2_XYZW %T2_Z = MUL_IEEE 0, 0, 1, 0, 0, 0, %T1_Z, 0, 0, 0, -1, %T0_W, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0, %T2_XYZW, %T2_XYZW %T0_W = MULADD_IEEE_eg 0, 0, %T0_Y, 0, 0, -1, %KC0_134_Y, 0, 0, 2073, %KC0_133_Y, 0, 0, 2069, 1, pred:%PRED_SEL_OFF, 0, 0 %T2_Y = MUL_IEEE 0, 0, 1, 0, 0, 0, %T1_Y, 0, 0, 0, -1, %PV_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW, %T2_XYZW, %T2_XYZW # End machine code for function main. ===== SHADER #35 ==================================== PS/JUNIPER/EVERGREEN ===== ===== 226 dw ===== 9 gprs ===== 2 stack ======================================== 0000 80000026 a0340000 ALU 14 @76 KC0[CB0:0-31] 0076 00384400 00146b80 1 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0078 00384000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.x VEC_210 0080 00384400 40146b90 z: INTERP_ZW R0.z, R0.y, Param2.x VEC_210 0082 80384000 60146b90 w: INTERP_ZW R0.w, R0.x, Param2.x VEC_210 0084 00384400 00946b10 2 x: INTERP_XY R4.x, R0.y, Param2.x VEC_210 0086 00384000 20946b10 y: INTERP_XY R4.y, R0.x, Param2.x VEC_210 0088 00384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.x VEC_210 0090 80384000 60146b00 w: INTERP_XY __.w, R0.x, Param2.x VEC_210 0092 00382400 00346b10 3 x: INTERP_XY R1.x, R0.y, Param1.x VEC_210 0094 00382000 20346b10 y: INTERP_XY R1.y, R0.x, Param1.x VEC_210 0096 00382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.x VEC_210 0098 80382000 60146b00 w: INTERP_XY __.w, R0.x, Param1.x VEC_210 0100 809fc088 40200110 4 z: MUL_IEEE R1.z, KC0[8].x, PV.y 0102 80002088 60200110 5 w: MUL_IEEE R1.w, KC0[8].x, R1.x 0002 00000016 80400400 TEX 2 @44 0044 00011107 f00d1002 24808000 GET_GRADIENTS_H R2.xyzw, R1.xyyy, RID:17, SID:1 CT:NNNN 0048 00011108 f00d1003 49308000 GET_GRADIENTS_V R3.xyzw, R1.wzzz, RID:17, SID:1 CT:NNNN 0004 00000034 a01c0000 ALU 8 @104 0104 80000003 00c00c90 6 x: MOV R6.x, R3.x 0106 00000002 00a00c90 7 x: MOV R5.x, R2.x 0108 80000403 20c00c90 y: MOV R6.y, R3.y 0110 00000402 20a00c90 8 y: MOV R5.y, R2.y 0112 80000403 40c80c90 z: MOV R6.z, R3.y VEC_120 0114 00000402 40a00c90 9 z: MOV R5.z, R2.y 0116 80000403 60c80c90 w: MOV R6.w, R3.y VEC_120 0118 80000402 60a00c90 10 w: MOV R5.w, R2.y 0006 0000001a 80400400 TEX 2 @52 0052 0005100c f00d1005 68800000 SET_GRADIENTS_V R5.xyzw, R5.xyzw, RID:16, SID:0 CT:NNNN 0056 0006100b f00d1006 68800000 SET_GRADIENTS_H R6.xyzw, R6.xyzw, RID:16, SID:0 CT:NNNN 0008 8000003c a0680000 ALU 27 @120 KC0[CB0:0-31] 0120 80000800 60004310 11 t: RECIP_IEEE R0.w, R0.z 0122 801fe084 60000110 12 w: MUL_IEEE R0.w, KC0[4].x, PS 0124 001f2cfe 40800210 13 z: MIN R4.z, PV.w, 1.0 0126 800000fd 60000c90 w: MOV R0.w, [0x00000000 0].x 0128 00000000 0130 00008004 00005f00 14 x: DOT4 __.x, R4.x, R4.x 0132 00808404 20005f00 y: DOT4 __.y, R4.y, R4.y 0134 01000800 40005f10 z: DOT4 R0.z, R0.z, R0.z 0136 81800c00 60005f00 w: DOT4 __.w, R0.w, R0.w 0138 00904804 60800110 15 w: MUL_IEEE R4.w, R4.z, KC0[2].y 0140 800000fe 40004391 t: RECIPSQRT_CLAMPED R0.z, |PV.x| 0142 00000cfe 20e00910 16 y: CEIL R7.y, PV.w 0144 001fe004 40800110 z: MUL_IEEE R4.z, R4.x, PS 0146 801fe404 60800110 w: MUL_IEEE R4.w, R4.y, PS 0148 00104cfe 40000110 17 z: MUL_IEEE R0.z, PV.w, KC0[2].x 0150 001048fe 60800110 w: MUL_IEEE R4.w, PV.z, KC0[2].x 0152 800004fe 00804310 t: RECIP_IEEE R4.x, PV.y 0154 001ffcfe 40800110 18 z: MUL_IEEE R4.z, -PV.w, PS 0156 801fe8fe 60800110 w: MUL_IEEE R4.w, PV.z, PS 0158 00380400 00146b80 19 x: INTERP_ZW __.x, R0.y, Param0.x VEC_210 0160 00380000 20146b80 y: INTERP_ZW __.y, R0.x, Param0.x VEC_210 0162 00380400 40146b90 z: INTERP_ZW R0.z, R0.y, Param0.x VEC_210 0164 80380000 60f46b90 w: INTERP_ZW R7.w, R0.x, Param0.x VEC_210 0166 00380400 00146b10 20 x: INTERP_XY R0.x, R0.y, Param0.x VEC_210 0168 00380000 20146b10 y: INTERP_XY R0.y, R0.x, Param0.x VEC_210 0170 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0172 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0010 0000000e 81800000 LOOP_START_DX10 @28 0012 00000057 a4040000 ALU_PUSH_BEFORE 2 @174 0174 81800407 60e00690 21 w: SETGT_DX10 R7.w, R7.y, R0.w 0176 801f0cfe 00002104 22 M x: PRED_SETE_INT __.x, PV.w, 0 0014 0000000a 82800001 JUMP @20 POP:1 0016 0000000d 82400000 LOOP_BREAK @26 0018 0000000a 83800001 POP @20 POP:1 0020 00000059 a0080000 ALU 3 @178 0178 800000fd 40200c90 23 z: MOV R1.z, [0x00000000 0].x 0180 00000000 0182 800008fe 60200c90 24 w: MOV R1.w, PV.z 0022 0000001e 80400000 TEX 1 @60 0060 00011014 f00d1008 68800000 SAMPLE_G R8.xyzw, R1.xyzw, RID:16, SID:0 CT:NNNN 0024 8000005c a0180000 ALU 7 @184 KC0[CB0:0-31] 0184 801fa083 60e01910 25 w: XOR_INT R7.w, KC0[3].x, [0x80000000 -0].x 0186 80000000 0188 801f2cfe 60e00010 26 w: ADD R7.w, PV.w, 1.0 0190 83810cfe 60e00010 27 w: ADD R7.w, PV.w, -R8.w 0192 819fc804 00230001 28 x: MULADD_IEEE R1.x, R4.z, PV.w, R1.x 0194 0180ec04 20230401 29 y: MULADD_IEEE R1.y, R4.w, R7.w, R1.y 0196 801f2c00 60100010 w: ADD R0.w, R0.w, 1.0 VEC_201 0026 00000006 81400000 LOOP_END @12 0028 00000063 a00c0000 ALU 4 @198 0198 80000403 40600c90 30 z: MOV R3.z, R3.y 0200 00000402 40400c90 31 z: MOV R2.z, R2.y 0202 80000403 60680c90 w: MOV R3.w, R3.y VEC_120 0204 80000402 60400c90 32 w: MOV R2.w, R2.y 0030 00000020 80400400 TEX 2 @64 0064 0002110c f00d1002 68808000 SET_GRADIENTS_V R2.xyzw, R2.xyzw, RID:17, SID:1 CT:NNNN 0068 0003110b f00d1003 68808000 SET_GRADIENTS_H R3.xyzw, R3.xyzw, RID:17, SID:1 CT:NNNN 0032 00000067 a0080000 ALU 3 @206 0206 800000fd 40200c90 33 z: MOV R1.z, [0x00000000 0].x 0208 00000000 0210 800008fe 60200c90 34 w: MOV R1.w, PV.z 0034 00000024 80400000 TEX 1 @72 0072 00011114 f00d1001 68808000 SAMPLE_G R1.xyzw, R1.xyzw, RID:17, SID:1 CT:NNNN 0036 8000006a a0180000 ALU 7 @212 KC0[CB0:0-31] 0212 8010c000 60030085 35 w: MULADD_IEEE R0.w, R0.x, KC0[6].x, KC0[5].x 0214 019fc001 00400110 36 x: MUL_IEEE R2.x, R1.x, PV.w 0216 8110c800 60030885 w: MULADD_IEEE R0.w, R0.z, KC0[6].z, KC0[5].z 0218 8010ec01 60400110 37 w: MUL_IEEE R2.w, R1.w, KC0[7].x 0220 01800801 40400110 38 z: MUL_IEEE R2.z, R1.z, R0.w 0222 8090c400 60030485 w: MULADD_IEEE R0.w, R0.y, KC0[6].y, KC0[5].y 0224 819fc401 20400110 39 y: MUL_IEEE R2.y, R1.y, PV.w 0038 c0010000 95300688 EXPORT_DONE PIXEL 0 R2.xyzw VPM EOP ===== SHADER_END ===============================================================