FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%16](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%16](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%16](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
SDL video target is 'x11'
SDL video target is 'x11'
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%16](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
SDL failed to create GL compatibility profile (whichProfile=0)!
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %21 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %22 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %23 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	EXP 15, 0, 0, 1, 1, %VGPR5<kill>, %VGPR4<kill>, %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8080300
c8090301
c80c0200
c80d0201
c8100100
c8110101
c8140000
c8150001
f800180f
02030405
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = fmul float %30, %11
  %42 = fmul float %30, %12
  %43 = fmul float %30, %13
  %44 = fmul float %30, %14
  %45 = fmul float %31, %15
  %46 = fadd float %45, %41
  %47 = fmul float %31, %16
  %48 = fadd float %47, %42
  %49 = fmul float %31, %17
  %50 = fadd float %49, %43
  %51 = fmul float %31, %18
  %52 = fadd float %51, %44
  %53 = fmul float %32, %19
  %54 = fadd float %53, %46
  %55 = fmul float %32, %20
  %56 = fadd float %55, %48
  %57 = fmul float %32, %21
  %58 = fadd float %57, %50
  %59 = fmul float %32, %22
  %60 = fadd float %59, %52
  %61 = fmul float %33, %23
  %62 = fadd float %61, %54
  %63 = fmul float %33, %24
  %64 = fadd float %63, %56
  %65 = fmul float %33, %25
  %66 = fadd float %65, %58
  %67 = fmul float %33, %26
  %68 = fadd float %67, %60
  %69 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
  %70 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
  %71 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
  %72 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %69, float %70, float %71, float %72)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%34](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_ADD_F32_e64 %VGPR4, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 %VGPR3, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR2, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 %VGPR1, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%27](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
10080004
c2020107
bf8c007f
d2820004
04100901
c202010b
bf8c007f
d2820004
04100902
c202010f
bf8c007f
d2820004
04100903
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04140901
c202010a
bf8c007f
d2820005
04140902
c202010e
bf8c007f
d2820005
04140903
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
04180901
c2020109
bf8c007f
d2820006
04180902
c202010d
bf8c007f
d2820006
04180903
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041c0901
c2020108
bf8c007f
d2820007
041c0902
c200010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
  %25 = bitcast i32 %24 to float
  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
  %27 = bitcast i32 %26 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
5e000101
c8060102
c80a0002
5e020302
f8001c0f
00010001
bf810000
Using breakpad crash handler
Setting breakpad minidump AppID = 400
Forcing breakpad minidump interfaces to load
Looking up breakpad interfaces from steamclient
Calling BreakpadMiniDumpSystemInit
Looking up breakpad interfaces from steamclient
Calling BreakpadMiniDumpSystemInit
Steam_SetMinidumpSteamID:  Caching Steam ID:  76561197992653503 [API loaded yes]
Steam_SetMinidumpSteamID:  Setting Steam ID:  76561197992653503
Did not detect any valid joysticks.
[0711/115053:ERROR:resource_bundle.cc(411)] Failed to load /home/lordh/.local/share/Steam/SteamApps/common/Portal/cef_gtk.pak
Some features may not be available.
[0711/115053:WARNING:proxy_service.cc(646)] PAC support disabled because there is no system implementation
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
  %36 = bitcast i32 %35 to float
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
  %36 = bitcast i32 %35 to float
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MOV OUT[0], TEMP[0]
  3: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
  %36 = bitcast i32 %35 to float
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..3]
DCL TEMP[0], LOCAL
IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
  0: MUL TEMP[0], CONST[0], IN[0].xxxx
  1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0]
  2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0]
  3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0]
  4: MOV OUT[1], IMM[0].xxxx
  5: MOV OUT[0], TEMP[0]
  6: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = fmul float %11, %30
  %35 = fmul float %12, %30
  %36 = fmul float %13, %30
  %37 = fmul float %14, %30
  %38 = fmul float %15, %31
  %39 = fadd float %38, %34
  %40 = fmul float %16, %31
  %41 = fadd float %40, %35
  %42 = fmul float %17, %31
  %43 = fadd float %42, %36
  %44 = fmul float %18, %31
  %45 = fadd float %44, %37
  %46 = fmul float %19, %32
  %47 = fadd float %46, %39
  %48 = fmul float %20, %32
  %49 = fadd float %48, %41
  %50 = fmul float %21, %32
  %51 = fadd float %50, %43
  %52 = fmul float %22, %32
  %53 = fadd float %52, %45
  %54 = fmul float %23, %33
  %55 = fadd float %54, %47
  %56 = fmul float %24, %33
  %57 = fadd float %56, %49
  %58 = fmul float %25, %33
  %59 = fadd float %58, %51
  %60 = fmul float %26, %33
  %61 = fadd float %60, %53
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %55, float %57, float %59, float %61)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%VGPR1<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR1, %VGPR1, %VGPR1, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%27](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e020280
f800020f
01010101
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
10080004
c2020107
bf8c007f
d2820004
04120204
c202010b
bf8c007f
d2820004
04120404
c202010f
bf8c007f
d2820004
04120604
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04160204
c202010a
bf8c007f
d2820005
04160404
c202010e
bf8c007f
d2820005
04160604
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
041a0204
c2020109
bf8c007f
d2820006
041a0404
c202010d
bf8c007f
d2820006
041a0604
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041e0204
c2020108
bf8c007f
d2820007
041e0404
c200010c
bf8c007f
d2820000
041e0600
f80008cf
04050600
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], CUBE
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %9)
  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %9)
  %28 = insertelement <4 x float> undef, float %24, i32 0
  %29 = insertelement <4 x float> %28, float %25, i32 1
  %30 = insertelement <4 x float> %29, float %26, i32 2
  %31 = insertelement <4 x float> %30, float %27, i32 3
  %32 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %31)
  %33 = extractelement <4 x float> %32, i32 0
  %34 = extractelement <4 x float> %32, i32 1
  %35 = extractelement <4 x float> %32, i32 2
  %36 = extractelement <4 x float> %32, i32 3
  %37 = call float @fabs(float %35)
  %38 = fdiv float 1.000000e+00, %37
  %39 = fmul float %33, %38
  %40 = fadd float %39, 1.500000e+00
  %41 = fmul float %34, %38
  %42 = fadd float %41, 1.500000e+00
  %43 = bitcast float %42 to i32
  %44 = bitcast float %40 to i32
  %45 = bitcast float %36 to i32
  %46 = insertelement <4 x i32> undef, i32 %43, i32 0
  %47 = insertelement <4 x i32> %46, i32 %44, i32 1
  %48 = insertelement <4 x i32> %47, i32 %45, i32 2
  %49 = insertelement <4 x i32> %48, i32 undef, i32 3
  %50 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %49, <32 x i8> %21, <16 x i8> %23, i32 4)
  %51 = extractelement <4 x float> %50, i32 0
  %52 = extractelement <4 x float> %50, i32 1
  %53 = extractelement <4 x float> %50, i32 2
  %54 = extractelement <4 x float> %50, i32 3
  %55 = call i32 @llvm.SI.packf16(float %51, float %52)
  %56 = bitcast i32 %55 to float
  %57 = call i32 @llvm.SI.packf16(float %53, float %54)
  %58 = bitcast i32 %57 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %56, float %58, float %56, float %58)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR7<def> = V_CUBESC_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR6<def> = V_CUBETC_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR8<def> = V_CUBEMA_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR9<def> = V_CUBEID_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR8, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_RCP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR6, %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR7<def> = V_MAD_F32 %VGPR7, %VGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR10<def> = KILL %VGPR10<undef>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8_VGPR9_VGPR10, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c8100200
c8110201
c8140300
c8150301
d28a0007
04120702
d28c0006
04120702
d28e0008
04120702
d2880009
04120702
d2060100
02010108
7e005500
7e0202ff
3fc00000
d2820008
04060106
d2820007
04060107
c0800300
c0c20500
bf8c007f
f0800f00
00010007
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], CUBE
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %9)
  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %9)
  %28 = insertelement <4 x float> undef, float %24, i32 0
  %29 = insertelement <4 x float> %28, float %25, i32 1
  %30 = insertelement <4 x float> %29, float %26, i32 2
  %31 = insertelement <4 x float> %30, float %27, i32 3
  %32 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %31)
  %33 = extractelement <4 x float> %32, i32 0
  %34 = extractelement <4 x float> %32, i32 1
  %35 = extractelement <4 x float> %32, i32 2
  %36 = extractelement <4 x float> %32, i32 3
  %37 = call float @fabs(float %35)
  %38 = fdiv float 1.000000e+00, %37
  %39 = fmul float %33, %38
  %40 = fadd float %39, 1.500000e+00
  %41 = fmul float %34, %38
  %42 = fadd float %41, 1.500000e+00
  %43 = bitcast float %42 to i32
  %44 = bitcast float %40 to i32
  %45 = bitcast float %36 to i32
  %46 = insertelement <4 x i32> undef, i32 %43, i32 0
  %47 = insertelement <4 x i32> %46, i32 %44, i32 1
  %48 = insertelement <4 x i32> %47, i32 %45, i32 2
  %49 = insertelement <4 x i32> %48, i32 undef, i32 3
  %50 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %49, <32 x i8> %21, <16 x i8> %23, i32 4)
  %51 = extractelement <4 x float> %50, i32 0
  %52 = extractelement <4 x float> %50, i32 1
  %53 = extractelement <4 x float> %50, i32 2
  %54 = extractelement <4 x float> %50, i32 3
  %55 = call i32 @llvm.SI.packf16(float %51, float %52)
  %56 = bitcast i32 %55 to float
  %57 = call i32 @llvm.SI.packf16(float %53, float %54)
  %58 = bitcast i32 %57 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %56, float %58, float %56, float %58)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR7<def> = V_CUBESC_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR6<def> = V_CUBETC_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR8<def> = V_CUBEMA_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR9<def> = V_CUBEID_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR8, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_RCP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR6, %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR7<def> = V_MAD_F32 %VGPR7, %VGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR10<def> = KILL %VGPR10<undef>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8_VGPR9_VGPR10, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c8100200
c8110201
c8140300
c8150301
d28a0007
04120702
d28c0006
04120702
d28e0008
04120702
d2880009
04120702
d2060100
02010108
7e005500
7e0202ff
3fc00000
d2820008
04060106
d2820007
04060107
c0800300
c0c20500
bf8c007f
f0800f00
00010007
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xyz, IN[0].xyzz
  1: TEX TEMP[0], TEMP[0], SAMP[0], CUBE
  2: MOV OUT[0], TEMP[0]
  3: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %27 = insertelement <4 x float> undef, float %24, i32 0
  %28 = insertelement <4 x float> %27, float %25, i32 1
  %29 = insertelement <4 x float> %28, float %26, i32 2
  %30 = insertelement <4 x float> %29, float 0.000000e+00, i32 3
  %31 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %30)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = extractelement <4 x float> %31, i32 3
  %36 = call float @fabs(float %34)
  %37 = fdiv float 1.000000e+00, %36
  %38 = fmul float %32, %37
  %39 = fadd float %38, 1.500000e+00
  %40 = fmul float %33, %37
  %41 = fadd float %40, 1.500000e+00
  %42 = bitcast float %41 to i32
  %43 = bitcast float %39 to i32
  %44 = bitcast float %35 to i32
  %45 = insertelement <4 x i32> undef, i32 %42, i32 0
  %46 = insertelement <4 x i32> %45, i32 %43, i32 1
  %47 = insertelement <4 x i32> %46, i32 %44, i32 2
  %48 = insertelement <4 x i32> %47, i32 undef, i32 3
  %49 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %48, <32 x i8> %21, <16 x i8> %23, i32 4)
  %50 = extractelement <4 x float> %49, i32 0
  %51 = extractelement <4 x float> %49, i32 1
  %52 = extractelement <4 x float> %49, i32 2
  %53 = extractelement <4 x float> %49, i32 3
  %54 = call i32 @llvm.SI.packf16(float %50, float %51)
  %55 = bitcast i32 %54 to float
  %56 = call i32 @llvm.SI.packf16(float %52, float %53)
  %57 = bitcast i32 %56 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %55, float %57, float %55, float %57)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR7<def> = V_CUBESC_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR6<def> = V_CUBETC_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR8<def> = V_CUBEMA_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR9<def> = V_CUBEID_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR8, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_RCP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR6, %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR7<def> = V_MAD_F32 %VGPR7, %VGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR10<def> = KILL %VGPR10<undef>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8_VGPR9_VGPR10, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c8100200
c8110201
7e0a0280
d28a0007
04120702
d28c0006
04120702
d28e0008
04120702
d2880009
04120702
d2060100
02010108
7e005500
7e0202ff
3fc00000
d2820008
04060106
d2820007
04060107
c0800300
c0c20500
bf8c007f
f0800f00
00010007
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..3]
DCL TEMP[0], LOCAL
IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
  0: MUL TEMP[0], CONST[0], IN[0].xxxx
  1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0]
  2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0]
  3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0]
  4: MOV OUT[1], IMM[0].xxxx
  5: MOV OUT[0], TEMP[0]
  6: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = fmul float %11, %30
  %35 = fmul float %12, %30
  %36 = fmul float %13, %30
  %37 = fmul float %14, %30
  %38 = fmul float %15, %31
  %39 = fadd float %38, %34
  %40 = fmul float %16, %31
  %41 = fadd float %40, %35
  %42 = fmul float %17, %31
  %43 = fadd float %42, %36
  %44 = fmul float %18, %31
  %45 = fadd float %44, %37
  %46 = fmul float %19, %32
  %47 = fadd float %46, %39
  %48 = fmul float %20, %32
  %49 = fadd float %48, %41
  %50 = fmul float %21, %32
  %51 = fadd float %50, %43
  %52 = fmul float %22, %32
  %53 = fadd float %52, %45
  %54 = fmul float %23, %33
  %55 = fadd float %54, %47
  %56 = fmul float %24, %33
  %57 = fadd float %56, %49
  %58 = fmul float %25, %33
  %59 = fadd float %58, %51
  %60 = fmul float %26, %33
  %61 = fadd float %60, %53
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %55, float %57, float %59, float %61)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%VGPR1<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR1, %VGPR1, %VGPR1, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%27](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e020280
f800020f
01010101
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
10080004
c2020107
bf8c007f
d2820004
04120204
c202010b
bf8c007f
d2820004
04120404
c202010f
bf8c007f
d2820004
04120604
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04160204
c202010a
bf8c007f
d2820005
04160404
c202010e
bf8c007f
d2820005
04160604
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
041a0204
c2020109
bf8c007f
d2820006
041a0404
c202010d
bf8c007f
d2820006
041a0604
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041e0204
c2020108
bf8c007f
d2820007
041e0404
c200010c
bf8c007f
d2820000
041e0600
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL OUT[0], COLOR
DCL CONST[0..3]
  0: MOV OUT[0], CONST[3]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
  %27 = bitcast i32 %26 to float
  %28 = call i32 @llvm.SI.packf16(float %24, float %25)
  %29 = bitcast i32 %28 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR0<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 %SGPR4<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 13
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0800100
bf8c007f
c202010e
c202810f
bf8c007f
7e000205
d25e0000
02020004
c202010c
c200010d
bf8c007f
7e020200
d25e0001
02020204
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = fmul float %30, %11
  %35 = fmul float %30, %12
  %36 = fmul float %30, %13
  %37 = fmul float %30, %14
  %38 = fmul float %31, %15
  %39 = fadd float %38, %34
  %40 = fmul float %31, %16
  %41 = fadd float %40, %35
  %42 = fmul float %31, %17
  %43 = fadd float %42, %36
  %44 = fmul float %31, %18
  %45 = fadd float %44, %37
  %46 = fmul float %32, %19
  %47 = fadd float %46, %39
  %48 = fmul float %32, %20
  %49 = fadd float %48, %41
  %50 = fmul float %32, %21
  %51 = fadd float %50, %43
  %52 = fmul float %32, %22
  %53 = fadd float %52, %45
  %54 = fmul float %33, %23
  %55 = fadd float %54, %47
  %56 = fmul float %33, %24
  %57 = fadd float %56, %49
  %58 = fmul float %33, %25
  %59 = fadd float %58, %51
  %60 = fmul float %33, %26
  %61 = fadd float %60, %53
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %55, float %57, float %59, float %61)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%27](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0820700
bf8c007f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
10080004
c2020107
bf8c007f
d2820004
04100901
c202010b
bf8c007f
d2820004
04100902
c202010f
bf8c007f
d2820004
04100903
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04140901
c202010a
bf8c007f
d2820005
04140902
c202010e
bf8c007f
d2820005
04140903
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
04180901
c2020109
bf8c007f
d2820006
04180902
c202010d
bf8c007f
d2820006
04180903
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041c0901
c2020108
bf8c007f
d2820007
041c0902
c200010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..29]
DCL TEMP[0..3], LOCAL
DCL TEMP[4], ARRAY(1), LOCAL
IMM[0] FLT32 {    1.0000,     1.1641,     0.0000,     2.0178}
IMM[1] FLT32 {    1.1641,     1.5958,     0.0000,    -0.8707}
IMM[2] FLT32 {    1.1641,    -0.8135,    -0.3914,     0.5297}
IMM[3] FLT32 {    1.1641,     0.0000,     2.0178,    -1.0817}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0].x, TEMP[0], SAMP[0], 2D
  2: MOV TEMP[0].x, TEMP[0].xxxx
  3: MOV TEMP[1].xy, IN[0].xyyy
  4: TEX TEMP[1].x, TEMP[1], SAMP[1], 2D
  5: MOV TEMP[2].xy, IN[0].xyyy
  6: TEX TEMP[2].x, TEMP[2], SAMP[2], 2D
  7: MOV TEMP[0].y, TEMP[1].xxxx
  8: MOV TEMP[0].z, TEMP[2].xxxx
  9: MOV TEMP[0].w, IMM[0].xxxx
 10: MAD TEMP[2].x, IN[1].wwww, CONST[12].wwww, -CONST[12].xxxx
 11: DP4 TEMP[1].x, TEMP[0], IMM[1]
 12: MIN TEMP[2].x, TEMP[2].xxxx, CONST[12].zzzz
 13: MOV_SAT TEMP[2].x, TEMP[2].xxxx
 14: DP4 TEMP[3].x, TEMP[0], IMM[2]
 15: MOV TEMP[1].y, TEMP[3].xxxx
 16: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
 17: DP4 TEMP[3].x, TEMP[0], IMM[3]
 18: MOV TEMP[1].z, TEMP[3].xxxx
 19: ADD TEMP[3].xyz, CONST[29].xyzz, -TEMP[1].xyzz
 20: MAD TEMP[0].xyz, TEMP[2].xxxx, TEMP[3].xyzz, TEMP[1].xyzz
 21: MOV TEMP[0].w, IMM[0].xxxx
 22: MOV TEMP[4], TEMP[0]
 23: MOV OUT[0], TEMP[4]
 24: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 204)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %28 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %29 = load <32 x i8> addrspace(2)* %28, !tbaa !0
  %30 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
  %32 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %33 = load <32 x i8> addrspace(2)* %32, !tbaa !0
  %34 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %37 = load <32 x i8> addrspace(2)* %36, !tbaa !0
  %38 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
  %40 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %41 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %42 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %43 = bitcast float %40 to i32
  %44 = bitcast float %41 to i32
  %45 = insertelement <2 x i32> undef, i32 %43, i32 0
  %46 = insertelement <2 x i32> %45, i32 %44, i32 1
  %47 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %46, <32 x i8> %29, <16 x i8> %31, i32 2)
  %48 = extractelement <4 x float> %47, i32 0
  %49 = bitcast float %40 to i32
  %50 = bitcast float %41 to i32
  %51 = insertelement <2 x i32> undef, i32 %49, i32 0
  %52 = insertelement <2 x i32> %51, i32 %50, i32 1
  %53 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %52, <32 x i8> %33, <16 x i8> %35, i32 2)
  %54 = extractelement <4 x float> %53, i32 0
  %55 = bitcast float %40 to i32
  %56 = bitcast float %41 to i32
  %57 = insertelement <2 x i32> undef, i32 %55, i32 0
  %58 = insertelement <2 x i32> %57, i32 %56, i32 1
  %59 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %58, <32 x i8> %37, <16 x i8> %39, i32 2)
  %60 = extractelement <4 x float> %59, i32 0
  %61 = fsub float -0.000000e+00, %22
  %62 = fmul float %42, %24
  %63 = fadd float %62, %61
  %64 = fmul float %48, 0x3FF2A04000000000
  %65 = fmul float %54, 0x3FF9886000000000
  %66 = fadd float %64, %65
  %67 = fmul float %60, 0.000000e+00
  %68 = fadd float %66, %67
  %69 = fmul float 1.000000e+00, 0xBFEBDC6800000000
  %70 = fadd float %68, %69
  %71 = fcmp uge float %63, %23
  %72 = select i1 %71, float %23, float %63
  %73 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
  %74 = fmul float %48, 0x3FF2A04000000000
  %75 = fmul float %54, 0xBFEA080000000000
  %76 = fadd float %74, %75
  %77 = fmul float %60, 0xBFD90D8000000000
  %78 = fadd float %76, %77
  %79 = fmul float 1.000000e+00, 0x3FE0F35800000000
  %80 = fadd float %78, %79
  %81 = fmul float %73, %73
  %82 = fmul float %48, 0x3FF2A04000000000
  %83 = fmul float %54, 0.000000e+00
  %84 = fadd float %82, %83
  %85 = fmul float %60, 0x4000248000000000
  %86 = fadd float %84, %85
  %87 = fmul float 1.000000e+00, 0xBFF14E8400000000
  %88 = fadd float %86, %87
  %89 = fsub float -0.000000e+00, %70
  %90 = fadd float %25, %89
  %91 = fsub float -0.000000e+00, %80
  %92 = fadd float %26, %91
  %93 = fsub float -0.000000e+00, %88
  %94 = fadd float %27, %93
  %95 = fmul float %81, %90
  %96 = fadd float %95, %70
  %97 = fmul float %81, %92
  %98 = fadd float %97, %80
  %99 = fmul float %81, %94
  %100 = fadd float %99, %88
  %101 = call i32 @llvm.SI.packf16(float %96, float %98)
  %102 = bitcast i32 %101 to float
  %103 = call i32 @llvm.SI.packf16(float %100, float 1.000000e+00)
  %104 = bitcast i32 %103 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %102, float %104, float %102, float %104)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%30](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%28](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2<def> = IMAGE_SAMPLE 1, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%34](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%32](tbaa=!"const")
	S_WAITCNT 112
	%VGPR3<def> = IMAGE_SAMPLE 1, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR7<def> = V_MUL_F32_e32 -8.134766e-01, %VGPR3, %EXEC<imp-use>
	%VGPR4<def> = V_MOV_B32_e32 1.164124e+00, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 8; mem:LD16[%38](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 16; mem:LD32[%36](tbaa=!"const")
	S_WAITCNT 127
	%VGPR5<def> = IMAGE_SAMPLE 1, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 -3.914490e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_MAD_F32 %VGPR5, %VGPR6<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 5.297050e-01, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 117
	S_WAITCNT 127
	%VGPR7<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 51
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 48
	S_WAITCNT 127
	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 50
	S_WAITCNT 127
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR0, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR0, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 1.595795e+00, %VGPR3, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR5, 0.000000e+00, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 -8.706551e-01, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 116
	S_WAITCNT 127
	%VGPR7<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR0, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR6<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 0.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %VGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 2.017822e+00, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR5<kill>, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e32 -1.081669e+00, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 118
	S_WAITCNT 127
	%VGPR3<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 %VGPR0<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8180100
c8190101
c8140000
c8150001
c0840300
c0c60500
bf8c007f
f0800100
00430205
c0840304
c0c60508
bf8c0070
f0800100
00430305
bf8c0770
100e06ff
bf504000
7e0802ff
3f950200
d2820007
041e0902
c0840308
c0c60510
bf8c007f
f0800100
00430505
7e0c02ff
bec86c00
bf8c0770
d2820006
041e0d05
060c0cff
3f079ac0
c0800100
bf8c007f
c2020175
bf8c007f
080e0c04
c8200700
c8210701
c2020133
bf8c007f
10001004
c2020130
bf8c007f
0a000004
c2020132
bf8c007f
d00c0006
02000900
7e020204
d2000000
001a0300
d2060800
02010100
10000100
d2820001
041a0f00
100c06ff
3fcc4300
d2820006
041a0902
d2820006
04190105
060c0cff
bf5ee340
c2020174
bf8c007f
080e0c04
d2820006
041a0f00
5e020306
10060680
d2820002
040e0902
7e0602ff
40012400
d2820002
040a0705
060404ff
bf8a7420
c2000176
bf8c007f
08060400
d2820000
040a0700
d25e0000
0201e500
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL CONST[0..20]
DCL TEMP[0..6], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[4]
  2: DP4 TEMP[2].x, TEMP[0], CONST[5]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[3].x, TEMP[0], CONST[17]
  5: DP4 TEMP[4].x, TEMP[0], CONST[18]
  6: MOV TEMP[3].y, TEMP[4].xxxx
  7: DP4 TEMP[4].x, TEMP[0], CONST[19]
  8: MOV TEMP[3].z, TEMP[4].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[7]
 10: MOV TEMP[5].w, TEMP[4].xxxx
 11: DP4 TEMP[0].x, TEMP[0], CONST[6]
 12: MOV TEMP[5].z, TEMP[0].xxxx
 13: MOV TEMP[1].zw, TEMP[5].wwzw
 14: MOV TEMP[3].w, TEMP[0].xxxx
 15: MOV TEMP[5].xy, IN[1].xyxx
 16: MOV TEMP[6], TEMP[1]
 17: MAD TEMP[0].x, TEMP[0].xxxx, CONST[0].zzzz, -TEMP[4].xxxx
 18: MOV TEMP[1].z, TEMP[0].xxxx
 19: MOV TEMP[1].y, -TEMP[2].xxxx
 20: MAD TEMP[1].xy, CONST[20].xyyy, TEMP[4].xxxx, TEMP[1].xyyy
 21: MOV OUT[2], TEMP[5]
 22: MOV OUT[3], TEMP[3]
 23: MOV OUT[0], TEMP[1]
 24: MOV OUT[1], TEMP[6]
 25: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 284)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 300)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 316)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
  %44 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %45 = load <16 x i8> addrspace(2)* %44, !tbaa !0
  %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %45, i32 0, i32 %5)
  %47 = extractelement <4 x float> %46, i32 0
  %48 = extractelement <4 x float> %46, i32 1
  %49 = extractelement <4 x float> %46, i32 2
  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
  %53 = extractelement <4 x float> %52, i32 0
  %54 = extractelement <4 x float> %52, i32 1
  %55 = fmul float %47, %12
  %56 = fadd float %55, %11
  %57 = fmul float %48, %12
  %58 = fadd float %57, %11
  %59 = fmul float %49, %12
  %60 = fadd float %59, %11
  %61 = fmul float %47, %11
  %62 = fadd float %61, %12
  %63 = fmul float %56, %14
  %64 = fmul float %58, %15
  %65 = fadd float %63, %64
  %66 = fmul float %60, %16
  %67 = fadd float %65, %66
  %68 = fmul float %62, %17
  %69 = fadd float %67, %68
  %70 = fmul float %56, %18
  %71 = fmul float %58, %19
  %72 = fadd float %70, %71
  %73 = fmul float %60, %20
  %74 = fadd float %72, %73
  %75 = fmul float %62, %21
  %76 = fadd float %74, %75
  %77 = fmul float %56, %30
  %78 = fmul float %58, %31
  %79 = fadd float %77, %78
  %80 = fmul float %60, %32
  %81 = fadd float %79, %80
  %82 = fmul float %62, %33
  %83 = fadd float %81, %82
  %84 = fmul float %56, %34
  %85 = fmul float %58, %35
  %86 = fadd float %84, %85
  %87 = fmul float %60, %36
  %88 = fadd float %86, %87
  %89 = fmul float %62, %37
  %90 = fadd float %88, %89
  %91 = fmul float %56, %38
  %92 = fmul float %58, %39
  %93 = fadd float %91, %92
  %94 = fmul float %60, %40
  %95 = fadd float %93, %94
  %96 = fmul float %62, %41
  %97 = fadd float %95, %96
  %98 = fmul float %56, %26
  %99 = fmul float %58, %27
  %100 = fadd float %98, %99
  %101 = fmul float %60, %28
  %102 = fadd float %100, %101
  %103 = fmul float %62, %29
  %104 = fadd float %102, %103
  %105 = fmul float %56, %22
  %106 = fmul float %58, %23
  %107 = fadd float %105, %106
  %108 = fmul float %60, %24
  %109 = fadd float %107, %108
  %110 = fmul float %62, %25
  %111 = fadd float %109, %110
  %112 = fsub float -0.000000e+00, %104
  %113 = fmul float %111, %13
  %114 = fadd float %113, %112
  %115 = fsub float -0.000000e+00, %76
  %116 = fmul float %42, %104
  %117 = fadd float %116, %69
  %118 = fmul float %43, %104
  %119 = fadd float %118, %115
  %120 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %121 = load <16 x i8> addrspace(2)* %120, !tbaa !0
  %122 = call float @llvm.SI.load.const(<16 x i8> %121, i32 0)
  %123 = fmul float %122, %69
  %124 = call float @llvm.SI.load.const(<16 x i8> %121, i32 4)
  %125 = fmul float %124, %76
  %126 = fadd float %123, %125
  %127 = call float @llvm.SI.load.const(<16 x i8> %121, i32 8)
  %128 = fmul float %127, %111
  %129 = fadd float %126, %128
  %130 = call float @llvm.SI.load.const(<16 x i8> %121, i32 12)
  %131 = fmul float %130, %104
  %132 = fadd float %129, %131
  %133 = call float @llvm.SI.load.const(<16 x i8> %121, i32 16)
  %134 = fmul float %133, %69
  %135 = call float @llvm.SI.load.const(<16 x i8> %121, i32 20)
  %136 = fmul float %135, %76
  %137 = fadd float %134, %136
  %138 = call float @llvm.SI.load.const(<16 x i8> %121, i32 24)
  %139 = fmul float %138, %111
  %140 = fadd float %137, %139
  %141 = call float @llvm.SI.load.const(<16 x i8> %121, i32 28)
  %142 = fmul float %141, %104
  %143 = fadd float %140, %142
  %144 = call float @llvm.SI.load.const(<16 x i8> %121, i32 32)
  %145 = fmul float %144, %69
  %146 = call float @llvm.SI.load.const(<16 x i8> %121, i32 36)
  %147 = fmul float %146, %76
  %148 = fadd float %145, %147
  %149 = call float @llvm.SI.load.const(<16 x i8> %121, i32 40)
  %150 = fmul float %149, %111
  %151 = fadd float %148, %150
  %152 = call float @llvm.SI.load.const(<16 x i8> %121, i32 44)
  %153 = fmul float %152, %104
  %154 = fadd float %151, %153
  %155 = call float @llvm.SI.load.const(<16 x i8> %121, i32 48)
  %156 = fmul float %155, %69
  %157 = call float @llvm.SI.load.const(<16 x i8> %121, i32 52)
  %158 = fmul float %157, %76
  %159 = fadd float %156, %158
  %160 = call float @llvm.SI.load.const(<16 x i8> %121, i32 56)
  %161 = fmul float %160, %111
  %162 = fadd float %159, %161
  %163 = call float @llvm.SI.load.const(<16 x i8> %121, i32 60)
  %164 = fmul float %163, %104
  %165 = fadd float %162, %164
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %132, float %143, float %154, float %165)
  %166 = call float @llvm.SI.load.const(<16 x i8> %121, i32 64)
  %167 = fmul float %166, %69
  %168 = call float @llvm.SI.load.const(<16 x i8> %121, i32 68)
  %169 = fmul float %168, %76
  %170 = fadd float %167, %169
  %171 = call float @llvm.SI.load.const(<16 x i8> %121, i32 72)
  %172 = fmul float %171, %111
  %173 = fadd float %170, %172
  %174 = call float @llvm.SI.load.const(<16 x i8> %121, i32 76)
  %175 = fmul float %174, %104
  %176 = fadd float %173, %175
  %177 = call float @llvm.SI.load.const(<16 x i8> %121, i32 80)
  %178 = fmul float %177, %69
  %179 = call float @llvm.SI.load.const(<16 x i8> %121, i32 84)
  %180 = fmul float %179, %76
  %181 = fadd float %178, %180
  %182 = call float @llvm.SI.load.const(<16 x i8> %121, i32 88)
  %183 = fmul float %182, %111
  %184 = fadd float %181, %183
  %185 = call float @llvm.SI.load.const(<16 x i8> %121, i32 92)
  %186 = fmul float %185, %104
  %187 = fadd float %184, %186
  %188 = call float @llvm.SI.load.const(<16 x i8> %121, i32 96)
  %189 = fmul float %188, %69
  %190 = call float @llvm.SI.load.const(<16 x i8> %121, i32 100)
  %191 = fmul float %190, %76
  %192 = fadd float %189, %191
  %193 = call float @llvm.SI.load.const(<16 x i8> %121, i32 104)
  %194 = fmul float %193, %111
  %195 = fadd float %192, %194
  %196 = call float @llvm.SI.load.const(<16 x i8> %121, i32 108)
  %197 = fmul float %196, %104
  %198 = fadd float %195, %197
  %199 = call float @llvm.SI.load.const(<16 x i8> %121, i32 112)
  %200 = fmul float %199, %69
  %201 = call float @llvm.SI.load.const(<16 x i8> %121, i32 116)
  %202 = fmul float %201, %76
  %203 = fadd float %200, %202
  %204 = call float @llvm.SI.load.const(<16 x i8> %121, i32 120)
  %205 = fmul float %204, %111
  %206 = fadd float %203, %205
  %207 = call float @llvm.SI.load.const(<16 x i8> %121, i32 124)
  %208 = fmul float %207, %104
  %209 = fadd float %206, %208
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %176, float %187, float %198, float %209)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %53, float %54, float %111, float %104)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %83, float %90, float %97, float %111)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %117, float %119, float %114, float %104)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%44](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6_VGPR7<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR4, %SGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR5, %SGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR4, %SGPR3<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7<imp-use,kill>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 19
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR5, %SGPR2<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 23
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR5, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%120](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 27
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 30
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 31
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 19
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 4; mem:LD16[%50](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR9, %VGPR10, %VGPR7, %VGPR8, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 77
	S_WAITCNT 15
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 76
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR1, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 78
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 79
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 73
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 72
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR1, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 74
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 75
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 69
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 68
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR1<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 70
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR3<kill>, %SGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 71
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR5<kill>, %SGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR1<kill>, %VGPR9<kill>, %VGPR0<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 80
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 81
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR6<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840700
bf8c007f
e00c2000
80020400
c0840100
bf8c0070
c2010901
c2018900
bf8c007f
7e060203
d2820001
040c0504
d2820002
040c0505
c2020911
bf8c007f
10100404
c2020910
bf8c007f
d2820008
04200901
d2820003
040c0506
c2020912
bf8c007f
d2820008
04200903
7e120202
d2820005
04240704
c2010913
bf8c007f
d2820004
04200505
c2010915
bf8c007f
100c0402
c2010914
bf8c007f
d2820006
04180501
c2010916
bf8c007f
d2820006
04180503
c2010917
bf8c007f
d2820006
04180505
c0800104
bf8c007f
c202010d
bf8c007f
100e0c04
c202010c
bf8c007f
d2820008
041e0804
c2020919
bf8c007f
100e0404
c2020918
bf8c007f
d2820007
041c0901
c202091a
bf8c007f
d2820007
041c0903
c202091b
bf8c007f
d2820007
041c0905
c202010e
bf8c007f
d2820009
04220e04
c202091d
bf8c007f
10100404
c202091c
bf8c007f
d2820008
04200901
c202091e
bf8c007f
d2820008
04200903
c202091f
bf8c007f
d2820008
04200905
c202010f
bf8c007f
d2820009
04261004
c2020109
bf8c007f
10140c04
c2020108
bf8c007f
d282000a
042a0804
c202010a
bf8c007f
d282000a
042a0e04
c202010b
bf8c007f
d282000a
042a1004
c2020105
bf8c007f
10160c04
c2020104
bf8c007f
d282000b
042e0804
c2020106
bf8c007f
d282000b
042e0e04
c2020107
bf8c007f
d282000b
042e1004
c2020101
bf8c007f
10180c04
c2020100
bf8c007f
d282000c
04320804
c2020102
bf8c007f
d282000c
04320e04
c2020103
bf8c007f
d282000c
04321004
f80000ef
090a0b0c
c202011d
bf8c000f
10120c04
c202011c
bf8c007f
d2820009
04260804
c202011e
bf8c007f
d2820009
04260e04
c202011f
bf8c007f
d2820009
04261004
c2020119
bf8c007f
10140c04
c2020118
bf8c007f
d282000a
042a0804
c202011a
bf8c007f
d282000a
042a0e04
c202011b
bf8c007f
d282000a
042a1004
c2020115
bf8c007f
10160c04
c2020114
bf8c007f
d282000b
042e0804
c2020116
bf8c007f
d282000b
042e0e04
c2020117
bf8c007f
d282000b
042e1004
c2020111
bf8c007f
10180c04
c2020110
bf8c007f
d282000c
04320804
c2020112
bf8c007f
d282000c
04320e04
c2000113
bf8c007f
d282000c
04321000
f80000ff
090a0b0c
c0800704
bf8c000f
e00c2000
80000900
bf8c0770
f800020f
08070a09
c200094d
bf8c000f
10000400
c200094c
bf8c007f
d2820000
04000101
c200094e
bf8c007f
d2820000
04000103
c200094f
bf8c007f
d2820000
04000105
c2000949
bf8c007f
10120400
c2000948
bf8c007f
d2820009
04240101
c200094a
bf8c007f
d2820009
04240103
c200094b
bf8c007f
d2820009
04240105
c2000945
bf8c007f
10040400
c2000944
bf8c007f
d2820001
04080101
c2000946
bf8c007f
d2820001
04040103
c2000947
bf8c007f
d2820001
04040105
f800021f
07000901
c2000950
bf8c000f
d2820000
04121000
c2000902
bf8c007f
10020e00
08021101
c2000951
bf8c007f
10041000
08040d02
f80008cf
08010200
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = fmul float %30, %11
  %35 = fmul float %30, %12
  %36 = fmul float %30, %13
  %37 = fmul float %30, %14
  %38 = fmul float %31, %15
  %39 = fadd float %38, %34
  %40 = fmul float %31, %16
  %41 = fadd float %40, %35
  %42 = fmul float %31, %17
  %43 = fadd float %42, %36
  %44 = fmul float %31, %18
  %45 = fadd float %44, %37
  %46 = fmul float %32, %19
  %47 = fadd float %46, %39
  %48 = fmul float %32, %20
  %49 = fadd float %48, %41
  %50 = fmul float %32, %21
  %51 = fadd float %50, %43
  %52 = fmul float %32, %22
  %53 = fadd float %52, %45
  %54 = fmul float %33, %23
  %55 = fadd float %54, %47
  %56 = fmul float %33, %24
  %57 = fadd float %56, %49
  %58 = fmul float %33, %25
  %59 = fadd float %58, %51
  %60 = fmul float %33, %26
  %61 = fadd float %60, %53
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %55, float %57, float %59, float %61)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%27](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0820700
bf8c007f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
10080004
c2020107
bf8c007f
d2820004
04100901
c202010b
bf8c007f
d2820004
04100902
c202010f
bf8c007f
d2820004
04100903
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04140901
c202010a
bf8c007f
d2820005
04140902
c202010e
bf8c007f
d2820005
04140903
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
04180901
c2020109
bf8c007f
d2820006
04180902
c202010d
bf8c007f
d2820006
04180903
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041c0901
c2020108
bf8c007f
d2820007
041c0902
c200010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %32, float %33, float %34)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 0, 0, 1, 1, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
f800180f
03020100
bf810000
FRAG
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL IN[3], GENERIC[22], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..30]
DCL TEMP[0..5], LOCAL
DCL TEMP[6], ARRAY(1), LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MAD TEMP[1].x, CONST[12].xxxx, CONST[21].yyyy, -IN[3].zzzz
  3: MAD TEMP[2].x, CONST[12].xxxx, CONST[20].zzzz, -IN[3].zzzz
  4: RCP TEMP[3].x, TEMP[2].xxxx
  5: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
  6: MUL TEMP[3].x, TEMP[1].xxxx, TEMP[3].xxxx
  7: MOV_SAT TEMP[3].x, TEMP[3].xxxx
  8: SGE TEMP[2].x, -TEMP[2].xxxx, IMM[0].xxxx
  9: F2I TEMP[2].x, -TEMP[2]
 10: UIF TEMP[2].xxxx :0
 11:   MOV TEMP[2].x, IMM[0].yyyy
 12: ELSE :0
 13:   MOV TEMP[2].x, TEMP[3].xxxx
 14: ENDIF
 15: MUL TEMP[3].x, IN[2].zzzz, CONST[21].wwww
 16: MAD TEMP[2].x, TEMP[3].xxxx, TEMP[2].xxxx, -CONST[21].xxxx
 17: MIN TEMP[2].x, TEMP[2].xxxx, CONST[21].zzzz
 18: MOV_SAT TEMP[2].x, TEMP[2].xxxx
 19: MAD TEMP[3].x, TEMP[2].xxxx, -TEMP[2].xxxx, TEMP[2].xxxx
 20: MUL TEMP[3].x, TEMP[3].xxxx, CONST[12].xxxx
 21: MAD TEMP[3].x, TEMP[2].xxxx, TEMP[2].xxxx, TEMP[3].xxxx
 22: MUL TEMP[4].x, TEMP[0].wwww, CONST[1].wwww
 23: MAD TEMP[5].x, TEMP[4].xxxx, IN[1].wwww, -TEMP[4].xxxx
 24: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[1].xyzz
 25: MAD TEMP[4].x, CONST[12].wwww, TEMP[5].xxxx, TEMP[4].xxxx
 26: MAD TEMP[1].xyz, TEMP[0].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 27: ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[4].xxxx
 28: MAD TEMP[2].x, CONST[12].zzzz, TEMP[2].xxxx, TEMP[4].xxxx
 29: MUL TEMP[1].xyz, TEMP[3].xxxx, TEMP[1].xyzz
 30: MAD TEMP[3].x, IN[2].zzzz, CONST[29].wwww, -TEMP[2].xxxx
 31: MAD TEMP[0].xyz, TEMP[0].xyzz, CONST[30].xxxx, TEMP[1].xyzz
 32: MAD TEMP[1].x, CONST[12].yyyy, TEMP[3].xxxx, TEMP[2].xxxx
 33: MOV TEMP[0].w, TEMP[1].xxxx
 34: MOV TEMP[6], TEMP[0]
 35: MOV OUT[0], TEMP[6]
 36: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 28)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 204)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 328)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 336)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 340)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 344)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 348)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %40 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0
  %42 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
  %44 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %45 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %46 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %47 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %48 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %49 = bitcast float %44 to i32
  %50 = bitcast float %45 to i32
  %51 = insertelement <2 x i32> undef, i32 %49, i32 0
  %52 = insertelement <2 x i32> %51, i32 %50, i32 1
  %53 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %52, <32 x i8> %41, <16 x i8> %43, i32 2)
  %54 = extractelement <4 x float> %53, i32 0
  %55 = extractelement <4 x float> %53, i32 1
  %56 = extractelement <4 x float> %53, i32 2
  %57 = extractelement <4 x float> %53, i32 3
  %58 = fsub float -0.000000e+00, %48
  %59 = fmul float %26, %32
  %60 = fadd float %59, %58
  %61 = fsub float -0.000000e+00, %48
  %62 = fmul float %26, %30
  %63 = fadd float %62, %61
  %64 = fdiv float 1.000000e+00, %63
  %65 = fmul float %63, %63
  %66 = fmul float %60, %64
  %67 = call float @llvm.AMDIL.clamp.(float %66, float 0.000000e+00, float 1.000000e+00)
  %68 = fsub float -0.000000e+00, %65
  %69 = fcmp uge float %68, 0.000000e+00
  %70 = select i1 %69, float 1.000000e+00, float 0.000000e+00
  %71 = fsub float -0.000000e+00, %70
  %72 = fptosi float %71 to i32
  %73 = bitcast i32 %72 to float
  %74 = bitcast float %73 to i32
  %75 = icmp ne i32 %74, 0
  %. = select i1 %75, float 1.000000e+00, float %67
  %76 = fmul float %47, %34
  %77 = fsub float -0.000000e+00, %31
  %78 = fmul float %76, %.
  %79 = fadd float %78, %77
  %80 = fcmp uge float %79, %33
  %81 = select i1 %80, float %33, float %79
  %82 = call float @llvm.AMDIL.clamp.(float %81, float 0.000000e+00, float 1.000000e+00)
  %83 = fsub float -0.000000e+00, %82
  %84 = fmul float %82, %83
  %85 = fadd float %84, %82
  %86 = fmul float %85, %26
  %87 = fmul float %82, %82
  %88 = fadd float %87, %86
  %89 = fmul float %57, %25
  %90 = fsub float -0.000000e+00, %89
  %91 = fmul float %89, %46
  %92 = fadd float %91, %90
  %93 = fmul float %54, %22
  %94 = fmul float %55, %23
  %95 = fmul float %56, %24
  %96 = fmul float %29, %92
  %97 = fadd float %96, %89
  %98 = fsub float -0.000000e+00, %39
  %99 = fmul float %93, %98
  %100 = fadd float %99, %35
  %101 = fsub float -0.000000e+00, %39
  %102 = fmul float %94, %101
  %103 = fadd float %102, %36
  %104 = fsub float -0.000000e+00, %39
  %105 = fmul float %95, %104
  %106 = fadd float %105, %37
  %107 = fsub float -0.000000e+00, %97
  %108 = fadd float %82, %107
  %109 = fmul float %28, %108
  %110 = fadd float %109, %97
  %111 = fmul float %88, %100
  %112 = fmul float %88, %103
  %113 = fmul float %88, %106
  %114 = fsub float -0.000000e+00, %110
  %115 = fmul float %47, %38
  %116 = fadd float %115, %114
  %117 = fmul float %93, %39
  %118 = fadd float %117, %111
  %119 = fmul float %94, %39
  %120 = fadd float %119, %112
  %121 = fmul float %95, %39
  %122 = fadd float %121, %113
  %123 = fmul float %27, %116
  %124 = fadd float %123, %110
  %125 = call i32 @llvm.SI.packf16(float %118, float %120)
  %126 = bitcast i32 %125 to float
  %127 = call i32 @llvm.SI.packf16(float %122, float %124)
  %128 = bitcast i32 %127 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %126, float %128, float %126, float %128)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%42](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%40](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR6, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_SUB_F32_e32 %VGPR7<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 51
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 48
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 85
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e64 %SGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 82
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e64 %SGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_SUB_F32_e32 %VGPR9<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_RCP_F32_e32 %VGPR9, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR7<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR8<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR8<def> = V_CVT_I32_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_NE_I32_e64 %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR7<kill>, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 87
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 84
	S_WAITCNT 127
	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR5<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 86
	S_WAITCNT 127
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR0, %SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR0, %VGPR6, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 50
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 119
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_SUB_F32_e32 %VGPR6<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 49
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR0, %VGPR0, %EXEC<imp-use>
	%VGPR6<def> = V_SUB_F32_e32 %VGPR0, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 120
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4, %VGPR6, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 118
	S_WAITCNT 127
	%VGPR7<def> = V_SUB_F32_e32 %SGPR5<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR0, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6<kill>, %SGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR6<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4, %VGPR6, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 117
	S_WAITCNT 127
	%VGPR7<def> = V_SUB_F32_e32 %SGPR5<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR0, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6<kill>, %SGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 116
	S_WAITCNT 127
	%VGPR3<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR2<kill>, %SGPR4<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR1<kill>, %VGPR0, %VGPR1, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430202
c0800100
bf8c0070
c2020107
bf8c007f
100c0a04
c81c0700
c81d0701
100e0f06
080e0d07
c2020133
bf8c007f
d2820006
041a0e04
c81c0e00
c81d0e01
c2020130
c2028155
bf8c007f
7e100205
d2100008
02021004
08100f08
c2028152
bf8c007f
7e120205
d2100009
02021204
08120f09
7e0e5509
100e0f08
d2060807
02010107
10101309
d2060008
22010108
d00c0008
02010108
d2000008
0021e480
d2060008
22010108
7e101108
d10a0008
02010108
d2000008
0021e507
c81c0a00
c81d0a01
c2028157
bf8c007f
10000e05
10001100
c2028154
bf8c007f
0a000005
c2028156
bf8c007f
d00c0006
02000b00
7e020205
d2000000
001a0300
d2060800
02010100
08020d00
c2028132
bf8c007f
d2820001
041a0205
c2028177
bf8c007f
100c0e05
080c0306
c2028131
bf8c007f
d2820001
04060c05
100c0100
080c0d00
100c0c04
d2820000
041a0100
c2020106
bf8c007f
100c0804
c2020178
bf8c007f
100e0c04
c2028176
bf8c007f
080e0e05
100e0f00
d2820006
041c0906
5e020306
c2028105
bf8c007f
100c0605
100e0c04
c2028175
bf8c007f
080e0e05
100e0f00
d2820006
041c0906
c2028104
bf8c007f
10040405
10060404
c2000174
bf8c007f
08060600
10000700
d2820000
04000902
5e000d00
f8001c0f
01000100
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL OUT[5], GENERIC[22]
DCL CONST[0..57]
DCL TEMP[0..6], LOCAL
  0: DP4 TEMP[0].x, IN[1], CONST[48]
  1: DP4 TEMP[1].x, IN[1], CONST[49]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: MAD TEMP[2].xyz, IN[2].xyzz, CONST[3].xxxx, IN[0].xyzz
  4: MOV TEMP[2].w, IN[0].wwww
  5: DP4 TEMP[1].x, TEMP[2], CONST[54]
  6: DP4 TEMP[3].x, TEMP[2], CONST[55]
  7: MOV TEMP[1].y, TEMP[3].xxxx
  8: DP4 TEMP[3].x, TEMP[2], CONST[56]
  9: MOV TEMP[1].z, TEMP[3].xxxx
 10: MOV TEMP[1].w, CONST[0].yyyy
 11: DP4 TEMP[3].x, TEMP[1], CONST[10]
 12: MOV TEMP[2].z, TEMP[3].xxxx
 13: DP4 TEMP[2].x, TEMP[1], CONST[8]
 14: DP4 TEMP[3].x, TEMP[1], CONST[9]
 15: MOV TEMP[2].y, TEMP[3].xxxx
 16: DP4 TEMP[3].x, TEMP[1], CONST[11]
 17: MOV TEMP[2].w, TEMP[3].xxxx
 18: DP4 TEMP[3].x, TEMP[1], CONST[13]
 19: MOV TEMP[4].z, TEMP[3].xxxx
 20: MOV TEMP[1].xyz, TEMP[1].xyzx
 21: MOV TEMP[5], TEMP[2]
 22: MOV TEMP[6].xy, TEMP[2].xyxx
 23: MOV TEMP[6].zw, TEMP[4].wwzw
 24: MOV TEMP[1].w, TEMP[3].xxxx
 25: MOV TEMP[3], TEMP[5]
 26: MAD TEMP[4].x, TEMP[2].zzzz, CONST[0].zzzz, -TEMP[2].wwww
 27: MOV TEMP[5].z, TEMP[4].xxxx
 28: MOV TEMP[5].y, -TEMP[2].yyyy
 29: MAD TEMP[5].xy, CONST[57].xyyy, TEMP[2].wwww, TEMP[5].xyyy
 30: MOV OUT[2], TEMP[0]
 31: MOV OUT[3], CONST[0].xxxx
 32: MOV OUT[0], TEMP[5]
 33: MOV OUT[1], TEMP[3]
 34: MOV OUT[4], TEMP[6]
 35: MOV OUT[5], TEMP[1]
 36: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 776)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 792)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 864)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 868)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 872)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 876)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 880)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 884)
  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 888)
  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 892)
  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 896)
  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 900)
  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 904)
  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 908)
  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 912)
  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 916)
  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
  %60 = extractelement <4 x float> %59, i32 0
  %61 = extractelement <4 x float> %59, i32 1
  %62 = extractelement <4 x float> %59, i32 2
  %63 = extractelement <4 x float> %59, i32 3
  %64 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
  %66 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %65, i32 0, i32 %5)
  %67 = extractelement <4 x float> %66, i32 0
  %68 = extractelement <4 x float> %66, i32 1
  %69 = extractelement <4 x float> %66, i32 2
  %70 = extractelement <4 x float> %66, i32 3
  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
  %74 = extractelement <4 x float> %73, i32 0
  %75 = extractelement <4 x float> %73, i32 1
  %76 = extractelement <4 x float> %73, i32 2
  %77 = fmul float %67, %35
  %78 = fmul float %68, %36
  %79 = fadd float %77, %78
  %80 = fmul float %69, %37
  %81 = fadd float %79, %80
  %82 = fmul float %70, %38
  %83 = fadd float %81, %82
  %84 = fmul float %67, %39
  %85 = fmul float %68, %40
  %86 = fadd float %84, %85
  %87 = fmul float %69, %41
  %88 = fadd float %86, %87
  %89 = fmul float %70, %42
  %90 = fadd float %88, %89
  %91 = fmul float %74, %14
  %92 = fadd float %91, %60
  %93 = fmul float %75, %14
  %94 = fadd float %93, %61
  %95 = fmul float %76, %14
  %96 = fadd float %95, %62
  %97 = fmul float %92, %43
  %98 = fmul float %94, %44
  %99 = fadd float %97, %98
  %100 = fmul float %96, %45
  %101 = fadd float %99, %100
  %102 = fmul float %63, %46
  %103 = fadd float %101, %102
  %104 = fmul float %92, %47
  %105 = fmul float %94, %48
  %106 = fadd float %104, %105
  %107 = fmul float %96, %49
  %108 = fadd float %106, %107
  %109 = fmul float %63, %50
  %110 = fadd float %108, %109
  %111 = fmul float %92, %51
  %112 = fmul float %94, %52
  %113 = fadd float %111, %112
  %114 = fmul float %96, %53
  %115 = fadd float %113, %114
  %116 = fmul float %63, %54
  %117 = fadd float %115, %116
  %118 = fmul float %103, %23
  %119 = fmul float %110, %24
  %120 = fadd float %118, %119
  %121 = fmul float %117, %25
  %122 = fadd float %120, %121
  %123 = fmul float %12, %26
  %124 = fadd float %122, %123
  %125 = fmul float %103, %15
  %126 = fmul float %110, %16
  %127 = fadd float %125, %126
  %128 = fmul float %117, %17
  %129 = fadd float %127, %128
  %130 = fmul float %12, %18
  %131 = fadd float %129, %130
  %132 = fmul float %103, %19
  %133 = fmul float %110, %20
  %134 = fadd float %132, %133
  %135 = fmul float %117, %21
  %136 = fadd float %134, %135
  %137 = fmul float %12, %22
  %138 = fadd float %136, %137
  %139 = fmul float %103, %27
  %140 = fmul float %110, %28
  %141 = fadd float %139, %140
  %142 = fmul float %117, %29
  %143 = fadd float %141, %142
  %144 = fmul float %12, %30
  %145 = fadd float %143, %144
  %146 = fmul float %103, %31
  %147 = fmul float %110, %32
  %148 = fadd float %146, %147
  %149 = fmul float %117, %33
  %150 = fadd float %148, %149
  %151 = fmul float %12, %34
  %152 = fadd float %150, %151
  %153 = fsub float -0.000000e+00, %145
  %154 = fmul float %124, %13
  %155 = fadd float %154, %153
  %156 = fsub float -0.000000e+00, %138
  %157 = fmul float %55, %145
  %158 = fadd float %157, %131
  %159 = fmul float %56, %145
  %160 = fadd float %159, %156
  %161 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %162 = load <16 x i8> addrspace(2)* %161, !tbaa !0
  %163 = call float @llvm.SI.load.const(<16 x i8> %162, i32 0)
  %164 = fmul float %163, %131
  %165 = call float @llvm.SI.load.const(<16 x i8> %162, i32 4)
  %166 = fmul float %165, %138
  %167 = fadd float %164, %166
  %168 = call float @llvm.SI.load.const(<16 x i8> %162, i32 8)
  %169 = fmul float %168, %124
  %170 = fadd float %167, %169
  %171 = call float @llvm.SI.load.const(<16 x i8> %162, i32 12)
  %172 = fmul float %171, %145
  %173 = fadd float %170, %172
  %174 = call float @llvm.SI.load.const(<16 x i8> %162, i32 16)
  %175 = fmul float %174, %131
  %176 = call float @llvm.SI.load.const(<16 x i8> %162, i32 20)
  %177 = fmul float %176, %138
  %178 = fadd float %175, %177
  %179 = call float @llvm.SI.load.const(<16 x i8> %162, i32 24)
  %180 = fmul float %179, %124
  %181 = fadd float %178, %180
  %182 = call float @llvm.SI.load.const(<16 x i8> %162, i32 28)
  %183 = fmul float %182, %145
  %184 = fadd float %181, %183
  %185 = call float @llvm.SI.load.const(<16 x i8> %162, i32 32)
  %186 = fmul float %185, %131
  %187 = call float @llvm.SI.load.const(<16 x i8> %162, i32 36)
  %188 = fmul float %187, %138
  %189 = fadd float %186, %188
  %190 = call float @llvm.SI.load.const(<16 x i8> %162, i32 40)
  %191 = fmul float %190, %124
  %192 = fadd float %189, %191
  %193 = call float @llvm.SI.load.const(<16 x i8> %162, i32 44)
  %194 = fmul float %193, %145
  %195 = fadd float %192, %194
  %196 = call float @llvm.SI.load.const(<16 x i8> %162, i32 48)
  %197 = fmul float %196, %131
  %198 = call float @llvm.SI.load.const(<16 x i8> %162, i32 52)
  %199 = fmul float %198, %138
  %200 = fadd float %197, %199
  %201 = call float @llvm.SI.load.const(<16 x i8> %162, i32 56)
  %202 = fmul float %201, %124
  %203 = fadd float %200, %202
  %204 = call float @llvm.SI.load.const(<16 x i8> %162, i32 60)
  %205 = fmul float %204, %145
  %206 = fadd float %203, %205
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %173, float %184, float %195, float %206)
  %207 = call float @llvm.SI.load.const(<16 x i8> %162, i32 64)
  %208 = fmul float %207, %131
  %209 = call float @llvm.SI.load.const(<16 x i8> %162, i32 68)
  %210 = fmul float %209, %138
  %211 = fadd float %208, %210
  %212 = call float @llvm.SI.load.const(<16 x i8> %162, i32 72)
  %213 = fmul float %212, %124
  %214 = fadd float %211, %213
  %215 = call float @llvm.SI.load.const(<16 x i8> %162, i32 76)
  %216 = fmul float %215, %145
  %217 = fadd float %214, %216
  %218 = call float @llvm.SI.load.const(<16 x i8> %162, i32 80)
  %219 = fmul float %218, %131
  %220 = call float @llvm.SI.load.const(<16 x i8> %162, i32 84)
  %221 = fmul float %220, %138
  %222 = fadd float %219, %221
  %223 = call float @llvm.SI.load.const(<16 x i8> %162, i32 88)
  %224 = fmul float %223, %124
  %225 = fadd float %222, %224
  %226 = call float @llvm.SI.load.const(<16 x i8> %162, i32 92)
  %227 = fmul float %226, %145
  %228 = fadd float %225, %227
  %229 = call float @llvm.SI.load.const(<16 x i8> %162, i32 96)
  %230 = fmul float %229, %131
  %231 = call float @llvm.SI.load.const(<16 x i8> %162, i32 100)
  %232 = fmul float %231, %138
  %233 = fadd float %230, %232
  %234 = call float @llvm.SI.load.const(<16 x i8> %162, i32 104)
  %235 = fmul float %234, %124
  %236 = fadd float %233, %235
  %237 = call float @llvm.SI.load.const(<16 x i8> %162, i32 108)
  %238 = fmul float %237, %145
  %239 = fadd float %236, %238
  %240 = call float @llvm.SI.load.const(<16 x i8> %162, i32 112)
  %241 = fmul float %240, %131
  %242 = call float @llvm.SI.load.const(<16 x i8> %162, i32 116)
  %243 = fmul float %242, %138
  %244 = fadd float %241, %243
  %245 = call float @llvm.SI.load.const(<16 x i8> %162, i32 120)
  %246 = fmul float %245, %124
  %247 = fadd float %244, %246
  %248 = call float @llvm.SI.load.const(<16 x i8> %162, i32 124)
  %249 = fmul float %248, %145
  %250 = fadd float %247, %249
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %217, float %228, float %239, float %250)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %83, float %90, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %11, float %11, float %11, float %11)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %131, float %138, float %152, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %103, float %110, float %117, float %152)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %158, float %160, float %155, float %145)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%57](tbaa=!"const")
	S_WAITCNT 127
	%VGPR3_VGPR4_VGPR5_VGPR6<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%71](tbaa=!"const")
	S_WAITCNT 112
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 12
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR9, %SGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR10, %SGPR2, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 217
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 216
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR7, %SGPR3<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR11, %SGPR2<kill>, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 218
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR9, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 219
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 221
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 220
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 222
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR9, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 223
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 225
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 224
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR7<kill>, %SGPR2<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 226
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR9<kill>, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 227
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-use,kill>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 35
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 37
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 36
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR3<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 38
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR3<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 39
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %SGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%161](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 41
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 40
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 42
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 43
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR2, %VGPR8<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 45
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %SGPR2, %VGPR9<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 9
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 11
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 29
	S_WAITCNT 15
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 28
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 30
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 31
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 25
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 24
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 26
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 27
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 21
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 20
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 22
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 23
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 17
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 16
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 18
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 19
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 4; mem:LD16[%64](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 112
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 198
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 199
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR11, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 194
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 195
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR11, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%VGPR0<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR8<kill>, %VGPR12<kill>, %VGPR0, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 15
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 %SGPR0, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %SGPR0, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR8<kill>, %VGPR9<kill>, %VGPR10<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 53
	S_WAITCNT 15
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 52
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR1, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 54
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 55
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %SGPR2<kill>, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR4, %VGPR5, %VGPR8, %VGPR0<kill>, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR1<kill>, %VGPR2<kill>, %VGPR3<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 228
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 229
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR5<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR7<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840700
bf8c007f
e00c2000
80020300
c0840708
bf8c0070
e00c2000
80020900
c0840100
bf8c0070
c201090c
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d2820007
040c0509
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0410050a
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10021003
c20189d8
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d2820001
04040707
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0414050b
c20109da
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d2820001
04040509
c20109db
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d2820001
04040506
c20109dd
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10041002
c20109dc
bf8c007f
d2820002
04080507
c20109de
bf8c007f
d2820002
04080509
c20109df
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d2820002
04080506
c2010921
bf8c007f
10140402
c2010920
bf8c007f
d282000a
04280501
c20109e1
bf8c007f
10101002
c20109e0
bf8c007f
d2820007
04200507
c20109e2
bf8c007f
d2820007
041c0509
c20109e3
bf8c007f
d2820003
041c0506
c2010922
bf8c007f
d2820004
04280503
c2010901
c2018923
bf8c007f
7e0a0203
d2820004
04120a02
c2018925
bf8c007f
100a0403
c2018924
bf8c007f
d2820005
04140701
c2018926
bf8c007f
d2820005
04140703
c2018927
bf8c007f
7e0c0203
d2820005
04160c02
c0860104
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c2000d0d
bf8c007f
100c0a00
c2000d0c
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d2820007
041a0800
c2000929
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100c0400
c2000928
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d2820006
04180101
c200092a
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d2820006
04180103
c200092b
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7e100200
d2820006
041a1002
c2000d0e
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d2820008
041e0c00
c200092d
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100e0400
c200092c
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d2820007
041c0101
c200092e
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d2820007
041c0103
c200092f
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7e120200
d2820007
041e1202
c2000d0f
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d2820008
04220e00
c2000d09
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10120a00
c2000d08
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d2820009
04260800
c2000d0a
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04260c00
c2000d0b
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d2820009
04260e00
c2000d05
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10140a00
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d282000a
042a0800
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d282000a
042a0c00
c2000d07
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d282000a
042a0e00
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10160a00
c2000d00
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d282000b
042e0800
c2000d02
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d282000b
042e0c00
c2000d03
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d282000b
042e0e00
f80000ef
08090a0b
c2000d1d
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10100a00
c2000d1c
bf8c007f
d2820008
04220800
c2000d1e
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d2820008
04220c00
c2000d1f
bf8c007f
d2820008
04220e00
c2000d19
bf8c007f
10120a00
c2000d18
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d2820009
04260800
c2000d1a
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d2820009
04260c00
c2000d1b
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d2820009
04260e00
c2000d15
bf8c007f
10140a00
c2000d14
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d282000a
042a0800
c2000d16
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d282000a
042a0c00
c2000d17
bf8c007f
d282000a
042a0e00
c2000d11
bf8c007f
10160a00
c2000d10
bf8c007f
d282000b
042e0800
c2000d12
bf8c007f
d282000b
042e0c00
c2000d13
bf8c007f
d282000b
042e0e00
f80000ff
08090a0b
c0820704
bf8c000f
e00c2000
80010800
c20009c5
bf8c0070
10001200
c20009c4
bf8c007f
d2820000
04000108
c20009c6
bf8c007f
d2820000
0400010a
c20009c7
bf8c007f
d282000c
0400010b
c20009c1
bf8c007f
10001200
c20009c0
bf8c007f
d2820000
04000108
c20009c2
bf8c007f
d2820000
0400010a
c20009c3
bf8c007f
d2820008
0400010b
7e000280
f800020f
00000c08
c2000900
bf8c000f
7e100200
7e120200
7e140200
7e160200
f800021f
0b0a0908
c2000935
bf8c000f
10100400
c2000934
bf8c007f
d2820008
04200101
c2000936
bf8c007f
d2820008
04200103
c2000937
bf8c007f
7e120200
d2820008
04221202
f800022f
00080504
f800023f
08030201
c20009e4
bf8c000f
d2820000
04120e00
c2000902
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10020c00
08020f01
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10040e00
08040b02
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07010200
bf810000
Could not load program cache file glbaseshaders.cfg
Could not find base GL shader cache file
CGLMShaderPair::SetProgramPair: Centroid masks differ at link time of vertex shader lightmappedgeneric_vs20 and pixel shader decalbasetimeslightmapalphablendselfillum2_ps20b!
Loaded program cache file "glshaders.cfg", total keyvalues: 189, total successfully linked: 189
Precache: Took 7749 ms, Vertex 486, Pixel 906
ConVarRef mat_dxlevel doesn't point to an existing ConVar
Game.so loaded for "Half-Life 2"
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = fmul float %30, %11
  %35 = fmul float %30, %12
  %36 = fmul float %30, %13
  %37 = fmul float %30, %14
  %38 = fmul float %31, %15
  %39 = fadd float %38, %34
  %40 = fmul float %31, %16
  %41 = fadd float %40, %35
  %42 = fmul float %31, %17
  %43 = fadd float %42, %36
  %44 = fmul float %31, %18
  %45 = fadd float %44, %37
  %46 = fmul float %32, %19
  %47 = fadd float %46, %39
  %48 = fmul float %32, %20
  %49 = fadd float %48, %41
  %50 = fmul float %32, %21
  %51 = fadd float %50, %43
  %52 = fmul float %32, %22
  %53 = fadd float %52, %45
  %54 = fmul float %33, %23
  %55 = fadd float %54, %47
  %56 = fmul float %33, %24
  %57 = fadd float %56, %49
  %58 = fmul float %33, %25
  %59 = fadd float %58, %51
  %60 = fmul float %33, %26
  %61 = fadd float %60, %53
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %55, float %57, float %59, float %61)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%27](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0820700
bf8c007f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
10080004
c2020107
bf8c007f
d2820004
04100901
c202010b
bf8c007f
d2820004
04100902
c202010f
bf8c007f
d2820004
04100903
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04140901
c202010a
bf8c007f
d2820005
04140902
c202010e
bf8c007f
d2820005
04140903
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
04180901
c2020109
bf8c007f
d2820006
04180902
c202010d
bf8c007f
d2820006
04180903
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041c0901
c2020108
bf8c007f
d2820007
041c0902
c200010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element
Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element
Fontconfig warning: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 78: saw unknown, expected number
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 3D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %9)
  %27 = bitcast float %24 to i32
  %28 = bitcast float %25 to i32
  %29 = bitcast float %26 to i32
  %30 = insertelement <4 x i32> undef, i32 %27, i32 0
  %31 = insertelement <4 x i32> %30, i32 %28, i32 1
  %32 = insertelement <4 x i32> %31, i32 %29, i32 2
  %33 = insertelement <4 x i32> %32, i32 undef, i32 3
  %34 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %33, <32 x i8> %21, <16 x i8> %23, i32 3)
  %35 = extractelement <4 x float> %34, i32 0
  %36 = extractelement <4 x float> %34, i32 1
  %37 = extractelement <4 x float> %34, i32 2
  %38 = extractelement <4 x float> %34, i32 3
  %39 = call i32 @llvm.SI.packf16(float %35, float %36)
  %40 = bitcast i32 %39 to float
  %41 = call i32 @llvm.SI.packf16(float %37, float %38)
  %42 = bitcast i32 %41 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def> = KILL %VGPR5<undef>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3_VGPR4_VGPR5<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c8100200
c8110201
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 3D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %9)
  %27 = bitcast float %24 to i32
  %28 = bitcast float %25 to i32
  %29 = bitcast float %26 to i32
  %30 = insertelement <4 x i32> undef, i32 %27, i32 0
  %31 = insertelement <4 x i32> %30, i32 %28, i32 1
  %32 = insertelement <4 x i32> %31, i32 %29, i32 2
  %33 = insertelement <4 x i32> %32, i32 undef, i32 3
  %34 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %33, <32 x i8> %21, <16 x i8> %23, i32 3)
  %35 = extractelement <4 x float> %34, i32 0
  %36 = extractelement <4 x float> %34, i32 1
  %37 = extractelement <4 x float> %34, i32 2
  %38 = extractelement <4 x float> %34, i32 3
  %39 = call i32 @llvm.SI.packf16(float %35, float %36)
  %40 = bitcast i32 %39 to float
  %41 = call i32 @llvm.SI.packf16(float %37, float %38)
  %42 = bitcast i32 %41 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def> = KILL %VGPR5<undef>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3_VGPR4_VGPR5<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c8100200
c8110201
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xyz, IN[0].xyzz
  1: TEX TEMP[0], TEMP[0], SAMP[0], 3D
  2: MOV OUT[0], TEMP[0]
  3: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %27 = bitcast float %24 to i32
  %28 = bitcast float %25 to i32
  %29 = bitcast float %26 to i32
  %30 = insertelement <4 x i32> undef, i32 %27, i32 0
  %31 = insertelement <4 x i32> %30, i32 %28, i32 1
  %32 = insertelement <4 x i32> %31, i32 %29, i32 2
  %33 = insertelement <4 x i32> %32, i32 undef, i32 3
  %34 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %33, <32 x i8> %21, <16 x i8> %23, i32 3)
  %35 = extractelement <4 x float> %34, i32 0
  %36 = extractelement <4 x float> %34, i32 1
  %37 = extractelement <4 x float> %34, i32 2
  %38 = extractelement <4 x float> %34, i32 3
  %39 = call i32 @llvm.SI.packf16(float %35, float %36)
  %40 = bitcast i32 %39 to float
  %41 = call i32 @llvm.SI.packf16(float %37, float %38)
  %42 = bitcast i32 %41 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def> = KILL %VGPR5<undef>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3_VGPR4_VGPR5<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c8100200
c8110201
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..3]
DCL TEMP[0], LOCAL
IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
  0: MUL TEMP[0], CONST[0], IN[0].xxxx
  1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0]
  2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0]
  3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0]
  4: MOV OUT[1], IMM[0].xxxx
  5: MOV OUT[0], TEMP[0]
  6: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = fmul float %11, %30
  %35 = fmul float %12, %30
  %36 = fmul float %13, %30
  %37 = fmul float %14, %30
  %38 = fmul float %15, %31
  %39 = fadd float %38, %34
  %40 = fmul float %16, %31
  %41 = fadd float %40, %35
  %42 = fmul float %17, %31
  %43 = fadd float %42, %36
  %44 = fmul float %18, %31
  %45 = fadd float %44, %37
  %46 = fmul float %19, %32
  %47 = fadd float %46, %39
  %48 = fmul float %20, %32
  %49 = fadd float %48, %41
  %50 = fmul float %21, %32
  %51 = fadd float %50, %43
  %52 = fmul float %22, %32
  %53 = fadd float %52, %45
  %54 = fmul float %23, %33
  %55 = fadd float %54, %47
  %56 = fmul float %24, %33
  %57 = fadd float %56, %49
  %58 = fmul float %25, %33
  %59 = fadd float %58, %51
  %60 = fmul float %26, %33
  %61 = fadd float %60, %53
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %55, float %57, float %59, float %61)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%VGPR1<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR1, %VGPR1, %VGPR1, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%27](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e020280
f800020f
01010101
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
10080004
c2020107
bf8c007f
d2820004
04120204
c202010b
bf8c007f
d2820004
04120404
c202010f
bf8c007f
d2820004
04120604
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04160204
c202010a
bf8c007f
d2820005
04160404
c202010e
bf8c007f
d2820005
04160604
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
041a0204
c2020109
bf8c007f
d2820006
041a0404
c202010d
bf8c007f
d2820006
041a0604
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041e0204
c2020108
bf8c007f
d2820007
041e0404
c200010c
bf8c007f
d2820000
041e0600
f80008cf
04050600
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL OUT[1], POSITION
DCL SAMP[0]
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV OUT[0], IMM[0].xxxy
  1: TEX OUT[1].z, IN[0], SAMP[0], 2D
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 2
  %32 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
  %33 = bitcast i32 %32 to float
  %34 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 1.000000e+00)
  %35 = bitcast i32 %34 to float
  call void @llvm.SI.export(i32 1, i32 0, i32 0, i32 8, i32 0, float %31, float %31, float %31, float %31)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %33, float %35, float %33, float %35)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0<def> = IMAGE_SAMPLE 4, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 1, 8, 0, 0, 0, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800400
00010002
bf8c0770
f8000081
00000000
bf8c070f
d25e0000
0201e480
d25e0001
02010080
f8001c0f
00010001
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL OUT[1], POSITION
DCL SAMP[0]
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV OUT[0], IMM[0].xxxy
  1: TEX OUT[1].z, IN[0], SAMP[0], 2D
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 2
  call void @llvm.SI.export(i32 1, i32 0, i32 0, i32 8, i32 0, float %31, float %31, float %31, float %31)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0<def> = IMAGE_SAMPLE 4, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 1, 8, 0, 0, 0, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR1<kill>, %VGPR1, %VGPR1, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800400
00010002
bf8c0770
f8000081
00000000
bf8c070f
7e0002f2
7e020280
f800180f
00010101
bf810000
FRAG
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL IN[3], GENERIC[22], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..30]
DCL TEMP[0..5], LOCAL
DCL TEMP[6], ARRAY(1), LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MAD TEMP[1].x, CONST[12].xxxx, CONST[21].yyyy, -IN[3].zzzz
  3: MAD TEMP[2].x, CONST[12].xxxx, CONST[20].zzzz, -IN[3].zzzz
  4: RCP TEMP[3].x, TEMP[2].xxxx
  5: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
  6: MUL TEMP[3].x, TEMP[1].xxxx, TEMP[3].xxxx
  7: MOV_SAT TEMP[3].x, TEMP[3].xxxx
  8: SGE TEMP[2].x, -TEMP[2].xxxx, IMM[0].xxxx
  9: F2I TEMP[2].x, -TEMP[2]
 10: UIF TEMP[2].xxxx :0
 11:   MOV TEMP[2].x, IMM[0].yyyy
 12: ELSE :0
 13:   MOV TEMP[2].x, TEMP[3].xxxx
 14: ENDIF
 15: MUL TEMP[3].x, IN[2].zzzz, CONST[21].wwww
 16: MAD TEMP[2].x, TEMP[3].xxxx, TEMP[2].xxxx, -CONST[21].xxxx
 17: MIN TEMP[2].x, TEMP[2].xxxx, CONST[21].zzzz
 18: MOV_SAT TEMP[2].x, TEMP[2].xxxx
 19: MAD TEMP[3].x, TEMP[2].xxxx, -TEMP[2].xxxx, TEMP[2].xxxx
 20: MUL TEMP[3].x, TEMP[3].xxxx, CONST[12].xxxx
 21: MAD TEMP[3].x, TEMP[2].xxxx, TEMP[2].xxxx, TEMP[3].xxxx
 22: MUL TEMP[4].x, TEMP[0].wwww, CONST[1].wwww
 23: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[1].xyzz
 24: MAD TEMP[5].x, TEMP[4].xxxx, IN[1].wwww, -TEMP[4].xxxx
 25: MUL TEMP[0].xyz, TEMP[0].xyzz, IN[1].xyzz
 26: MAD TEMP[4].x, CONST[12].wwww, TEMP[5].xxxx, TEMP[4].xxxx
 27: MAD TEMP[1].xyz, TEMP[0].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 28: ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[4].xxxx
 29: MAD TEMP[2].x, CONST[12].zzzz, TEMP[2].xxxx, TEMP[4].xxxx
 30: MUL TEMP[1].xyz, TEMP[3].xxxx, TEMP[1].xyzz
 31: MAD TEMP[3].x, IN[2].zzzz, CONST[29].wwww, -TEMP[2].xxxx
 32: MAD TEMP[0].xyz, TEMP[0].xyzz, CONST[30].xxxx, TEMP[1].xyzz
 33: MAD TEMP[1].x, CONST[12].yyyy, TEMP[3].xxxx, TEMP[2].xxxx
 34: MOV TEMP[0].w, TEMP[1].xxxx
 35: MOV TEMP[6], TEMP[0]
 36: MOV OUT[0], TEMP[6]
 37: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 28)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 204)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 328)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 336)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 340)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 344)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 348)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %40 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0
  %42 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
  %44 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %45 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %46 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %47 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %48 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %49 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %50 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %51 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %52 = bitcast float %44 to i32
  %53 = bitcast float %45 to i32
  %54 = insertelement <2 x i32> undef, i32 %52, i32 0
  %55 = insertelement <2 x i32> %54, i32 %53, i32 1
  %56 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %55, <32 x i8> %41, <16 x i8> %43, i32 2)
  %57 = extractelement <4 x float> %56, i32 0
  %58 = extractelement <4 x float> %56, i32 1
  %59 = extractelement <4 x float> %56, i32 2
  %60 = extractelement <4 x float> %56, i32 3
  %61 = fsub float -0.000000e+00, %51
  %62 = fmul float %26, %32
  %63 = fadd float %62, %61
  %64 = fsub float -0.000000e+00, %51
  %65 = fmul float %26, %30
  %66 = fadd float %65, %64
  %67 = fdiv float 1.000000e+00, %66
  %68 = fmul float %66, %66
  %69 = fmul float %63, %67
  %70 = call float @llvm.AMDIL.clamp.(float %69, float 0.000000e+00, float 1.000000e+00)
  %71 = fsub float -0.000000e+00, %68
  %72 = fcmp uge float %71, 0.000000e+00
  %73 = select i1 %72, float 1.000000e+00, float 0.000000e+00
  %74 = fsub float -0.000000e+00, %73
  %75 = fptosi float %74 to i32
  %76 = bitcast i32 %75 to float
  %77 = bitcast float %76 to i32
  %78 = icmp ne i32 %77, 0
  %. = select i1 %78, float 1.000000e+00, float %70
  %79 = fmul float %50, %34
  %80 = fsub float -0.000000e+00, %31
  %81 = fmul float %79, %.
  %82 = fadd float %81, %80
  %83 = fcmp uge float %82, %33
  %84 = select i1 %83, float %33, float %82
  %85 = call float @llvm.AMDIL.clamp.(float %84, float 0.000000e+00, float 1.000000e+00)
  %86 = fsub float -0.000000e+00, %85
  %87 = fmul float %85, %86
  %88 = fadd float %87, %85
  %89 = fmul float %88, %26
  %90 = fmul float %85, %85
  %91 = fadd float %90, %89
  %92 = fmul float %60, %25
  %93 = fmul float %57, %22
  %94 = fmul float %58, %23
  %95 = fmul float %59, %24
  %96 = fsub float -0.000000e+00, %92
  %97 = fmul float %92, %49
  %98 = fadd float %97, %96
  %99 = fmul float %93, %46
  %100 = fmul float %94, %47
  %101 = fmul float %95, %48
  %102 = fmul float %29, %98
  %103 = fadd float %102, %92
  %104 = fsub float -0.000000e+00, %39
  %105 = fmul float %99, %104
  %106 = fadd float %105, %35
  %107 = fsub float -0.000000e+00, %39
  %108 = fmul float %100, %107
  %109 = fadd float %108, %36
  %110 = fsub float -0.000000e+00, %39
  %111 = fmul float %101, %110
  %112 = fadd float %111, %37
  %113 = fsub float -0.000000e+00, %103
  %114 = fadd float %85, %113
  %115 = fmul float %28, %114
  %116 = fadd float %115, %103
  %117 = fmul float %91, %106
  %118 = fmul float %91, %109
  %119 = fmul float %91, %112
  %120 = fsub float -0.000000e+00, %116
  %121 = fmul float %50, %38
  %122 = fadd float %121, %120
  %123 = fmul float %99, %39
  %124 = fadd float %123, %117
  %125 = fmul float %100, %39
  %126 = fadd float %125, %118
  %127 = fmul float %101, %39
  %128 = fadd float %127, %119
  %129 = fmul float %27, %122
  %130 = fadd float %129, %116
  %131 = call i32 @llvm.SI.packf16(float %124, float %126)
  %132 = bitcast i32 %131 to float
  %133 = call i32 @llvm.SI.packf16(float %128, float %130)
  %134 = bitcast i32 %133 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %132, float %134, float %132, float %134)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%42](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%40](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR6, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_SUB_F32_e32 %VGPR7<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 51
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 48
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 85
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e64 %SGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 82
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e64 %SGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_SUB_F32_e32 %VGPR9<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_RCP_F32_e32 %VGPR9, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR7<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR8<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR8<def> = V_CVT_I32_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_NE_I32_e64 %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR7<kill>, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 87
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 84
	S_WAITCNT 127
	%VGPR8<def> = V_SUBREV_F32_e32 %SGPR5<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 86
	S_WAITCNT 127
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR8, %SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR9<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_SUB_F32_e32 %VGPR8, %VGPR6, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 50
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR5<kill>, %VGPR9<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 119
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_SUB_F32_e32 %VGPR7<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 49
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR8, %VGPR8, %EXEC<imp-use>
	%VGPR6<def> = V_SUB_F32_e32 %VGPR8, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR8<kill>, %VGPR8, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 120
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4, %VGPR8, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 118
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e32 %SGPR5<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR6, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8<kill>, %SGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4, %VGPR8, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 117
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e32 %SGPR5<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR6, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8<kill>, %SGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR4, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 116
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR7<kill>, %VGPR0, %VGPR7, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430202
c0800100
bf8c0070
c2020107
bf8c007f
100c0a04
c81c0700
c81d0701
100e0f06
080e0d07
c2020133
bf8c007f
d2820006
041a0e04
c81c0e00
c81d0e01
c2020130
c2028155
bf8c007f
7e100205
d2100008
02021004
08100f08
c2028152
bf8c007f
7e120205
d2100009
02021204
08120f09
7e0e5509
100e0f08
d2060807
02010107
10101309
d2060008
22010108
d00c0008
02010108
d2000008
0021e480
d2060008
22010108
7e101108
d10a0008
02010108
d2000008
0021e507
c81c0a00
c81d0a01
c2028157
bf8c007f
10120e05
10101109
c2028154
bf8c007f
0a101005
c2028156
bf8c007f
d00c0008
02000b08
7e120205
d2000008
00221308
d2060808
02010108
08120d08
c2028132
bf8c007f
d2820006
041a1205
c2028177
bf8c007f
100e0e05
080e0d07
c2028131
bf8c007f
d2820007
041a0e05
100c1108
080c0d08
100c0c04
d2820006
041a1108
c2020106
bf8c007f
10100804
c8240600
c8250601
10101308
c2020178
bf8c007f
10121004
c2028176
bf8c007f
08121205
10121306
d2820008
04240908
5e0e0f08
c2028105
bf8c007f
10100605
c8240500
c8250501
10101308
10121004
c2028175
bf8c007f
08121205
10121306
d2820008
04240908
c2028104
bf8c007f
10040405
c80c0400
c80d0401
10000702
10020004
c2000174
bf8c007f
08020200
10020306
d2820000
04040900
5e001100
f8001c0f
07000700
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL OUT[5], GENERIC[22]
DCL CONST[0..57]
DCL TEMP[0..7], LOCAL
IMM[0] FLT32 {    2.2000,     0.0000,     0.0000,     0.0000}
  0: LG2 TEMP[0].x, IN[1].xxxx
  1: LG2 TEMP[1].x, IN[1].yyyy
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: LG2 TEMP[1].x, IN[1].zzzz
  4: MOV TEMP[0].z, TEMP[1].xxxx
  5: MUL TEMP[0].xyz, TEMP[0].xyzz, IMM[0].xxxx
  6: EX2 TEMP[1].x, TEMP[0].xxxx
  7: EX2 TEMP[2].x, TEMP[0].yyyy
  8: MOV TEMP[1].y, TEMP[2].xxxx
  9: EX2 TEMP[2].x, TEMP[0].zzzz
 10: MOV TEMP[1].z, TEMP[2].xxxx
 11: DP4 TEMP[2].x, IN[2], CONST[48]
 12: DP4 TEMP[3].x, IN[2], CONST[49]
 13: MOV TEMP[2].y, TEMP[3].xxxx
 14: MAD TEMP[0].xyz, IN[3].xyzz, CONST[3].xxxx, IN[0].xyzz
 15: MOV TEMP[0].w, IN[0].wwww
 16: DP4 TEMP[3].x, TEMP[0], CONST[54]
 17: DP4 TEMP[4].x, TEMP[0], CONST[55]
 18: MOV TEMP[3].y, TEMP[4].xxxx
 19: DP4 TEMP[4].x, TEMP[0], CONST[56]
 20: MOV TEMP[3].z, TEMP[4].xxxx
 21: MOV TEMP[3].w, CONST[0].yyyy
 22: DP4 TEMP[4].x, TEMP[3], CONST[10]
 23: MOV TEMP[0].z, TEMP[4].xxxx
 24: DP4 TEMP[0].x, TEMP[3], CONST[8]
 25: DP4 TEMP[4].x, TEMP[3], CONST[9]
 26: MOV TEMP[0].y, TEMP[4].xxxx
 27: DP4 TEMP[4].x, TEMP[3], CONST[11]
 28: MOV TEMP[0].w, TEMP[4].xxxx
 29: DP4 TEMP[4].x, TEMP[3], CONST[13]
 30: MOV TEMP[5].z, TEMP[4].xxxx
 31: MOV TEMP[3].xyz, TEMP[3].xyzx
 32: MOV TEMP[6], TEMP[0]
 33: MOV TEMP[7].xy, TEMP[0].xyxx
 34: MOV TEMP[1].w, IN[1].wwww
 35: MOV TEMP[7].zw, TEMP[5].wwzw
 36: MOV TEMP[3].w, TEMP[4].xxxx
 37: MOV TEMP[4], TEMP[6]
 38: MAD TEMP[5].x, TEMP[0].zzzz, CONST[0].zzzz, -TEMP[0].wwww
 39: MOV TEMP[6].z, TEMP[5].xxxx
 40: MOV TEMP[6].y, -TEMP[0].yyyy
 41: MAD TEMP[6].xy, CONST[57].xyyy, TEMP[0].wwww, TEMP[6].xyyy
 42: MOV OUT[2], TEMP[2]
 43: MOV OUT[3], TEMP[1]
 44: MOV OUT[0], TEMP[6]
 45: MOV OUT[1], TEMP[4]
 46: MOV OUT[4], TEMP[7]
 47: MOV OUT[5], TEMP[3]
 48: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 776)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 792)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 864)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 868)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 872)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 876)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 880)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 884)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 888)
  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 892)
  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 896)
  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 900)
  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 904)
  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 908)
  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 912)
  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 916)
  %56 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %57 = load <16 x i8> addrspace(2)* %56, !tbaa !0
  %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %57, i32 0, i32 %5)
  %59 = extractelement <4 x float> %58, i32 0
  %60 = extractelement <4 x float> %58, i32 1
  %61 = extractelement <4 x float> %58, i32 2
  %62 = extractelement <4 x float> %58, i32 3
  %63 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %64 = load <16 x i8> addrspace(2)* %63, !tbaa !0
  %65 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %64, i32 0, i32 %5)
  %66 = extractelement <4 x float> %65, i32 0
  %67 = extractelement <4 x float> %65, i32 1
  %68 = extractelement <4 x float> %65, i32 2
  %69 = extractelement <4 x float> %65, i32 3
  %70 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %71 = load <16 x i8> addrspace(2)* %70, !tbaa !0
  %72 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %71, i32 0, i32 %5)
  %73 = extractelement <4 x float> %72, i32 0
  %74 = extractelement <4 x float> %72, i32 1
  %75 = extractelement <4 x float> %72, i32 2
  %76 = extractelement <4 x float> %72, i32 3
  %77 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %78 = load <16 x i8> addrspace(2)* %77, !tbaa !0
  %79 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %78, i32 0, i32 %5)
  %80 = extractelement <4 x float> %79, i32 0
  %81 = extractelement <4 x float> %79, i32 1
  %82 = extractelement <4 x float> %79, i32 2
  %83 = call float @llvm.log2.f32(float %66)
  %84 = call float @llvm.log2.f32(float %67)
  %85 = call float @llvm.log2.f32(float %68)
  %86 = fmul float %83, 0x40019999A0000000
  %87 = fmul float %84, 0x40019999A0000000
  %88 = fmul float %85, 0x40019999A0000000
  %89 = call float @llvm.AMDIL.exp.(float %86)
  %90 = call float @llvm.AMDIL.exp.(float %87)
  %91 = call float @llvm.AMDIL.exp.(float %88)
  %92 = fmul float %73, %34
  %93 = fmul float %74, %35
  %94 = fadd float %92, %93
  %95 = fmul float %75, %36
  %96 = fadd float %94, %95
  %97 = fmul float %76, %37
  %98 = fadd float %96, %97
  %99 = fmul float %73, %38
  %100 = fmul float %74, %39
  %101 = fadd float %99, %100
  %102 = fmul float %75, %40
  %103 = fadd float %101, %102
  %104 = fmul float %76, %41
  %105 = fadd float %103, %104
  %106 = fmul float %80, %13
  %107 = fadd float %106, %59
  %108 = fmul float %81, %13
  %109 = fadd float %108, %60
  %110 = fmul float %82, %13
  %111 = fadd float %110, %61
  %112 = fmul float %107, %42
  %113 = fmul float %109, %43
  %114 = fadd float %112, %113
  %115 = fmul float %111, %44
  %116 = fadd float %114, %115
  %117 = fmul float %62, %45
  %118 = fadd float %116, %117
  %119 = fmul float %107, %46
  %120 = fmul float %109, %47
  %121 = fadd float %119, %120
  %122 = fmul float %111, %48
  %123 = fadd float %121, %122
  %124 = fmul float %62, %49
  %125 = fadd float %123, %124
  %126 = fmul float %107, %50
  %127 = fmul float %109, %51
  %128 = fadd float %126, %127
  %129 = fmul float %111, %52
  %130 = fadd float %128, %129
  %131 = fmul float %62, %53
  %132 = fadd float %130, %131
  %133 = fmul float %118, %22
  %134 = fmul float %125, %23
  %135 = fadd float %133, %134
  %136 = fmul float %132, %24
  %137 = fadd float %135, %136
  %138 = fmul float %11, %25
  %139 = fadd float %137, %138
  %140 = fmul float %118, %14
  %141 = fmul float %125, %15
  %142 = fadd float %140, %141
  %143 = fmul float %132, %16
  %144 = fadd float %142, %143
  %145 = fmul float %11, %17
  %146 = fadd float %144, %145
  %147 = fmul float %118, %18
  %148 = fmul float %125, %19
  %149 = fadd float %147, %148
  %150 = fmul float %132, %20
  %151 = fadd float %149, %150
  %152 = fmul float %11, %21
  %153 = fadd float %151, %152
  %154 = fmul float %118, %26
  %155 = fmul float %125, %27
  %156 = fadd float %154, %155
  %157 = fmul float %132, %28
  %158 = fadd float %156, %157
  %159 = fmul float %11, %29
  %160 = fadd float %158, %159
  %161 = fmul float %118, %30
  %162 = fmul float %125, %31
  %163 = fadd float %161, %162
  %164 = fmul float %132, %32
  %165 = fadd float %163, %164
  %166 = fmul float %11, %33
  %167 = fadd float %165, %166
  %168 = fsub float -0.000000e+00, %160
  %169 = fmul float %139, %12
  %170 = fadd float %169, %168
  %171 = fsub float -0.000000e+00, %153
  %172 = fmul float %54, %160
  %173 = fadd float %172, %146
  %174 = fmul float %55, %160
  %175 = fadd float %174, %171
  %176 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %177 = load <16 x i8> addrspace(2)* %176, !tbaa !0
  %178 = call float @llvm.SI.load.const(<16 x i8> %177, i32 0)
  %179 = fmul float %178, %146
  %180 = call float @llvm.SI.load.const(<16 x i8> %177, i32 4)
  %181 = fmul float %180, %153
  %182 = fadd float %179, %181
  %183 = call float @llvm.SI.load.const(<16 x i8> %177, i32 8)
  %184 = fmul float %183, %139
  %185 = fadd float %182, %184
  %186 = call float @llvm.SI.load.const(<16 x i8> %177, i32 12)
  %187 = fmul float %186, %160
  %188 = fadd float %185, %187
  %189 = call float @llvm.SI.load.const(<16 x i8> %177, i32 16)
  %190 = fmul float %189, %146
  %191 = call float @llvm.SI.load.const(<16 x i8> %177, i32 20)
  %192 = fmul float %191, %153
  %193 = fadd float %190, %192
  %194 = call float @llvm.SI.load.const(<16 x i8> %177, i32 24)
  %195 = fmul float %194, %139
  %196 = fadd float %193, %195
  %197 = call float @llvm.SI.load.const(<16 x i8> %177, i32 28)
  %198 = fmul float %197, %160
  %199 = fadd float %196, %198
  %200 = call float @llvm.SI.load.const(<16 x i8> %177, i32 32)
  %201 = fmul float %200, %146
  %202 = call float @llvm.SI.load.const(<16 x i8> %177, i32 36)
  %203 = fmul float %202, %153
  %204 = fadd float %201, %203
  %205 = call float @llvm.SI.load.const(<16 x i8> %177, i32 40)
  %206 = fmul float %205, %139
  %207 = fadd float %204, %206
  %208 = call float @llvm.SI.load.const(<16 x i8> %177, i32 44)
  %209 = fmul float %208, %160
  %210 = fadd float %207, %209
  %211 = call float @llvm.SI.load.const(<16 x i8> %177, i32 48)
  %212 = fmul float %211, %146
  %213 = call float @llvm.SI.load.const(<16 x i8> %177, i32 52)
  %214 = fmul float %213, %153
  %215 = fadd float %212, %214
  %216 = call float @llvm.SI.load.const(<16 x i8> %177, i32 56)
  %217 = fmul float %216, %139
  %218 = fadd float %215, %217
  %219 = call float @llvm.SI.load.const(<16 x i8> %177, i32 60)
  %220 = fmul float %219, %160
  %221 = fadd float %218, %220
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %188, float %199, float %210, float %221)
  %222 = call float @llvm.SI.load.const(<16 x i8> %177, i32 64)
  %223 = fmul float %222, %146
  %224 = call float @llvm.SI.load.const(<16 x i8> %177, i32 68)
  %225 = fmul float %224, %153
  %226 = fadd float %223, %225
  %227 = call float @llvm.SI.load.const(<16 x i8> %177, i32 72)
  %228 = fmul float %227, %139
  %229 = fadd float %226, %228
  %230 = call float @llvm.SI.load.const(<16 x i8> %177, i32 76)
  %231 = fmul float %230, %160
  %232 = fadd float %229, %231
  %233 = call float @llvm.SI.load.const(<16 x i8> %177, i32 80)
  %234 = fmul float %233, %146
  %235 = call float @llvm.SI.load.const(<16 x i8> %177, i32 84)
  %236 = fmul float %235, %153
  %237 = fadd float %234, %236
  %238 = call float @llvm.SI.load.const(<16 x i8> %177, i32 88)
  %239 = fmul float %238, %139
  %240 = fadd float %237, %239
  %241 = call float @llvm.SI.load.const(<16 x i8> %177, i32 92)
  %242 = fmul float %241, %160
  %243 = fadd float %240, %242
  %244 = call float @llvm.SI.load.const(<16 x i8> %177, i32 96)
  %245 = fmul float %244, %146
  %246 = call float @llvm.SI.load.const(<16 x i8> %177, i32 100)
  %247 = fmul float %246, %153
  %248 = fadd float %245, %247
  %249 = call float @llvm.SI.load.const(<16 x i8> %177, i32 104)
  %250 = fmul float %249, %139
  %251 = fadd float %248, %250
  %252 = call float @llvm.SI.load.const(<16 x i8> %177, i32 108)
  %253 = fmul float %252, %160
  %254 = fadd float %251, %253
  %255 = call float @llvm.SI.load.const(<16 x i8> %177, i32 112)
  %256 = fmul float %255, %146
  %257 = call float @llvm.SI.load.const(<16 x i8> %177, i32 116)
  %258 = fmul float %257, %153
  %259 = fadd float %256, %258
  %260 = call float @llvm.SI.load.const(<16 x i8> %177, i32 120)
  %261 = fmul float %260, %139
  %262 = fadd float %259, %261
  %263 = call float @llvm.SI.load.const(<16 x i8> %177, i32 124)
  %264 = fmul float %263, %160
  %265 = fadd float %262, %264
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %232, float %243, float %254, float %265)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %98, float %105, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %89, float %90, float %91, float %69)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %146, float %153, float %167, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %118, float %125, float %132, float %167)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %173, float %175, float %170, float %160)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: nounwind readonly
declare float @llvm.log2.f32(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.exp.(float) #3

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%56](tbaa=!"const")
	S_WAITCNT 127
	%VGPR3_VGPR4_VGPR5_VGPR6<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%77](tbaa=!"const")
	S_WAITCNT 112
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 12
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR9, %SGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR10, %SGPR2, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 217
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 216
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR7, %SGPR3<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR11, %SGPR2<kill>, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 218
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR9, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 219
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 221
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 220
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 222
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR9, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 223
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 225
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 224
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR7<kill>, %SGPR2<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 226
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR9<kill>, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 227
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-use,kill>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 35
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 37
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 36
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR3<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 38
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR3<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 39
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %SGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%176](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 41
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 40
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 42
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 43
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR2, %VGPR8<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 45
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %SGPR2, %VGPR9<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 9
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 11
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 29
	S_WAITCNT 15
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 28
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 30
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 31
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 25
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 24
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 26
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 27
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 21
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 20
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 22
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 23
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 17
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 16
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 18
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 19
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%70](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 112
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 198
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 199
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR11, %SGPR0<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 194
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 195
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR11, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%VGPR8<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR9<kill>, %VGPR12<kill>, %VGPR8, %VGPR8, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 4; mem:LD16[%63](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_LOG_F32_e32 %VGPR11, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 2.200000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_EXP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_LOG_F32_e32 %VGPR10, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 2.200000e+00, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_EXP_F32_e32 %VGPR13<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_LOG_F32_e32 %VGPR9, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 2.200000e+00, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_EXP_F32_e32 %VGPR14<kill>, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR14<kill>, %VGPR13<kill>, %VGPR0<kill>, %VGPR12, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 53
	S_WAITCNT 15
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 52
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR1, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 54
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 55
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %SGPR2<kill>, %VGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR4, %VGPR5, %VGPR0, %VGPR8<kill>, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR1<kill>, %VGPR2<kill>, %VGPR3<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 228
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 229
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR5<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR7<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840700
bf8c007f
e00c2000
80020300
c084070c
bf8c0070
e00c2000
80020900
c0840100
bf8c0070
c201090c
bf8c007f
d2820007
040c0509
d2820008
0410050a
c20189d9
bf8c007f
10021003
c20189d8
bf8c007f
d2820001
04040707
d2820009
0414050b
c20109da
bf8c007f
d2820001
04040509
c20109db
bf8c007f
d2820001
04040506
c20109dd
bf8c007f
10041002
c20109dc
bf8c007f
d2820002
04080507
c20109de
bf8c007f
d2820002
04080509
c20109df
bf8c007f
d2820002
04080506
c2010921
bf8c007f
10140402
c2010920
bf8c007f
d282000a
04280501
c20109e1
bf8c007f
10101002
c20109e0
bf8c007f
d2820007
04200507
c20109e2
bf8c007f
d2820007
041c0509
c20109e3
bf8c007f
d2820003
041c0506
c2010922
bf8c007f
d2820004
04280503
c2010901
c2018923
bf8c007f
7e0a0203
d2820004
04120a02
c2018925
bf8c007f
100a0403
c2018924
bf8c007f
d2820005
04140701
c2018926
bf8c007f
d2820005
04140703
c2018927
bf8c007f
7e0c0203
d2820005
04160c02
c0860104
bf8c007f
c2000d0d
bf8c007f
100c0a00
c2000d0c
bf8c007f
d2820007
041a0800
c2000929
bf8c007f
100c0400
c2000928
bf8c007f
d2820006
04180101
c200092a
bf8c007f
d2820006
04180103
c200092b
bf8c007f
7e100200
d2820006
041a1002
c2000d0e
bf8c007f
d2820008
041e0c00
c200092d
bf8c007f
100e0400
c200092c
bf8c007f
d2820007
041c0101
c200092e
bf8c007f
d2820007
041c0103
c200092f
bf8c007f
7e120200
d2820007
041e1202
c2000d0f
bf8c007f
d2820008
04220e00
c2000d09
bf8c007f
10120a00
c2000d08
bf8c007f
d2820009
04260800
c2000d0a
bf8c007f
d2820009
04260c00
c2000d0b
bf8c007f
d2820009
04260e00
c2000d05
bf8c007f
10140a00
c2000d04
bf8c007f
d282000a
042a0800
c2000d06
bf8c007f
d282000a
042a0c00
c2000d07
bf8c007f
d282000a
042a0e00
c2000d01
bf8c007f
10160a00
c2000d00
bf8c007f
d282000b
042e0800
c2000d02
bf8c007f
d282000b
042e0c00
c2000d03
bf8c007f
d282000b
042e0e00
f80000ef
08090a0b
c2000d1d
bf8c000f
10100a00
c2000d1c
bf8c007f
d2820008
04220800
c2000d1e
bf8c007f
d2820008
04220c00
c2000d1f
bf8c007f
d2820008
04220e00
c2000d19
bf8c007f
10120a00
c2000d18
bf8c007f
d2820009
04260800
c2000d1a
bf8c007f
d2820009
04260c00
c2000d1b
bf8c007f
d2820009
04260e00
c2000d15
bf8c007f
10140a00
c2000d14
bf8c007f
d282000a
042a0800
c2000d16
bf8c007f
d282000a
042a0c00
c2000d17
bf8c007f
d282000a
042a0e00
c2000d11
bf8c007f
10160a00
c2000d10
bf8c007f
d282000b
042e0800
c2000d12
bf8c007f
d282000b
042e0c00
c2000d13
bf8c007f
d282000b
042e0e00
f80000ff
08090a0b
c0860708
bf8c000f
e00c2000
80030800
c20009c5
bf8c0070
10181200
c20009c4
bf8c007f
d282000c
04300108
c20009c6
bf8c007f
d282000c
0430010a
c20009c7
bf8c007f
d282000c
0430010b
c20009c1
bf8c007f
101a1200
c20009c0
bf8c007f
d282000d
04340108
c20009c2
bf8c007f
d282000d
0434010a
c20009c3
bf8c007f
d2820009
0434010b
7e100280
f800020f
08080c09
c0820704
bf8c000f
e00c2000
80010900
bf8c0770
7e004f0b
100000ff
400ccccd
7e004b00
7e1a4f0a
101a1aff
400ccccd
7e1a4b0d
7e1c4f09
101c1cff
400ccccd
7e1c4b0e
f800021f
0c000d0e
c2000935
bf8c000f
10000400
c2000934
bf8c007f
d2820000
04000101
c2000936
bf8c007f
d2820000
04000103
c2000937
bf8c007f
7e120200
d2820000
04021202
f800022f
08000504
f800023f
00030201
c20009e4
bf8c000f
d2820000
04120e00
c2000902
bf8c007f
10020c00
08020f01
c20009e5
bf8c007f
10040e00
08040b02
f80008cf
07010200
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = fmul float %30, %11
  %35 = fmul float %30, %12
  %36 = fmul float %30, %13
  %37 = fmul float %30, %14
  %38 = fmul float %31, %15
  %39 = fadd float %38, %34
  %40 = fmul float %31, %16
  %41 = fadd float %40, %35
  %42 = fmul float %31, %17
  %43 = fadd float %42, %36
  %44 = fmul float %31, %18
  %45 = fadd float %44, %37
  %46 = fmul float %32, %19
  %47 = fadd float %46, %39
  %48 = fmul float %32, %20
  %49 = fadd float %48, %41
  %50 = fmul float %32, %21
  %51 = fadd float %50, %43
  %52 = fmul float %32, %22
  %53 = fadd float %52, %45
  %54 = fmul float %33, %23
  %55 = fadd float %54, %47
  %56 = fmul float %33, %24
  %57 = fadd float %56, %49
  %58 = fmul float %33, %25
  %59 = fadd float %58, %51
  %60 = fmul float %33, %26
  %61 = fadd float %60, %53
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %55, float %57, float %59, float %61)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%27](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0820700
bf8c007f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
10080004
c2020107
bf8c007f
d2820004
04100901
c202010b
bf8c007f
d2820004
04100902
c202010f
bf8c007f
d2820004
04100903
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04140901
c202010a
bf8c007f
d2820005
04140902
c202010e
bf8c007f
d2820005
04140903
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
04180901
c2020109
bf8c007f
d2820006
04180902
c202010d
bf8c007f
d2820006
04180903
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041c0901
c2020108
bf8c007f
d2820007
041c0902
c200010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
  %25 = bitcast i32 %24 to float
  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
  %27 = bitcast i32 %26 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
5e000101
c8060102
c80a0002
5e020302
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%16](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
DCL TEMP[1], ARRAY(1), LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0].w, TEMP[0], SAMP[0], 2D
  2: MUL TEMP[0].x, TEMP[0].wwww, IN[0].wwww
  3: MOV TEMP[0].w, TEMP[0].xxxx
  4: MOV TEMP[0].xyz, IMM[0].xxxx
  5: MOV TEMP[1], TEMP[0]
  6: MOV OUT[0], TEMP[1]
  7: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %27 = bitcast float %25 to i32
  %28 = bitcast float %26 to i32
  %29 = insertelement <2 x i32> undef, i32 %27, i32 0
  %30 = insertelement <2 x i32> %29, i32 %28, i32 1
  %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %21, <16 x i8> %23, i32 2)
  %32 = extractelement <4 x float> %31, i32 3
  %33 = fmul float %32, %24
  %34 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 1.000000e+00)
  %35 = bitcast i32 %34 to float
  %36 = call i32 @llvm.SI.packf16(float 1.000000e+00, float %33)
  %37 = bitcast i32 %36 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %35, float %37, float %35, float %37)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 1.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 1.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0500
c80d0501
c8080400
c8090401
c0800300
c0c40500
bf8c007f
f0800800
00020202
c80c0300
c80d0301
bf8c0770
10000702
5e0000f2
d25e0001
0201e4f2
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL CONST[0..57]
DCL TEMP[0..5], LOCAL
  0: MOV TEMP[0].w, CONST[0].yyyy
  1: DP4 TEMP[0].x, IN[0], CONST[54]
  2: DP4 TEMP[1].x, IN[0], CONST[55]
  3: MOV TEMP[0].y, TEMP[1].xxxx
  4: DP4 TEMP[1].x, IN[0], CONST[56]
  5: MOV TEMP[0].z, TEMP[1].xxxx
  6: DP4 TEMP[1].x, TEMP[0], CONST[8]
  7: DP4 TEMP[2].x, TEMP[0], CONST[9]
  8: MOV TEMP[1].y, TEMP[2].xxxx
  9: DP4 TEMP[3].x, TEMP[0], CONST[10]
 10: MOV TEMP[1].z, TEMP[3].xxxx
 11: DP4 TEMP[0].x, TEMP[0], CONST[11]
 12: MOV TEMP[1].w, TEMP[0].xxxx
 13: MUL TEMP[4].xy, IN[1].yyyy, CONST[49].xyyy
 14: MAD TEMP[4].xy, IN[1].xxxx, CONST[48].xyyy, TEMP[4].xyyy
 15: MOV TEMP[5], TEMP[1]
 16: MAD TEMP[3].x, TEMP[3].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
 17: MOV TEMP[1].z, TEMP[3].xxxx
 18: MOV TEMP[1].y, -TEMP[2].xxxx
 19: MAD TEMP[1].xy, CONST[57].xyyy, TEMP[0].xxxx, TEMP[1].xyyy
 20: MOV OUT[3], TEMP[4]
 21: MOV OUT[0], TEMP[1]
 22: MOV OUT[2], TEMP[5]
 23: MOV_SAT OUT[1], CONST[47]
 24: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 752)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 756)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 760)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 764)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 864)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 868)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 872)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 876)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 880)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 884)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 888)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 892)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 896)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 900)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 904)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 908)
  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 912)
  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 916)
  %51 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %52, i32 0, i32 %5)
  %54 = extractelement <4 x float> %53, i32 0
  %55 = extractelement <4 x float> %53, i32 1
  %56 = extractelement <4 x float> %53, i32 2
  %57 = extractelement <4 x float> %53, i32 3
  %58 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %59 = load <16 x i8> addrspace(2)* %58, !tbaa !0
  %60 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %59, i32 0, i32 %5)
  %61 = extractelement <4 x float> %60, i32 0
  %62 = extractelement <4 x float> %60, i32 1
  %63 = fmul float %54, %37
  %64 = fmul float %55, %38
  %65 = fadd float %63, %64
  %66 = fmul float %56, %39
  %67 = fadd float %65, %66
  %68 = fmul float %57, %40
  %69 = fadd float %67, %68
  %70 = fmul float %54, %41
  %71 = fmul float %55, %42
  %72 = fadd float %70, %71
  %73 = fmul float %56, %43
  %74 = fadd float %72, %73
  %75 = fmul float %57, %44
  %76 = fadd float %74, %75
  %77 = fmul float %54, %45
  %78 = fmul float %55, %46
  %79 = fadd float %77, %78
  %80 = fmul float %56, %47
  %81 = fadd float %79, %80
  %82 = fmul float %57, %48
  %83 = fadd float %81, %82
  %84 = fmul float %69, %13
  %85 = fmul float %76, %14
  %86 = fadd float %84, %85
  %87 = fmul float %83, %15
  %88 = fadd float %86, %87
  %89 = fmul float %11, %16
  %90 = fadd float %88, %89
  %91 = fmul float %69, %17
  %92 = fmul float %76, %18
  %93 = fadd float %91, %92
  %94 = fmul float %83, %19
  %95 = fadd float %93, %94
  %96 = fmul float %11, %20
  %97 = fadd float %95, %96
  %98 = fmul float %69, %21
  %99 = fmul float %76, %22
  %100 = fadd float %98, %99
  %101 = fmul float %83, %23
  %102 = fadd float %100, %101
  %103 = fmul float %11, %24
  %104 = fadd float %102, %103
  %105 = fmul float %69, %25
  %106 = fmul float %76, %26
  %107 = fadd float %105, %106
  %108 = fmul float %83, %27
  %109 = fadd float %107, %108
  %110 = fmul float %11, %28
  %111 = fadd float %109, %110
  %112 = fmul float %62, %35
  %113 = fmul float %62, %36
  %114 = fmul float %61, %33
  %115 = fadd float %114, %112
  %116 = fmul float %61, %34
  %117 = fadd float %116, %113
  %118 = fsub float -0.000000e+00, %111
  %119 = fmul float %104, %12
  %120 = fadd float %119, %118
  %121 = fsub float -0.000000e+00, %97
  %122 = fmul float %49, %111
  %123 = fadd float %122, %90
  %124 = fmul float %50, %111
  %125 = fadd float %124, %121
  %126 = call float @llvm.AMDIL.clamp.(float %29, float 0.000000e+00, float 1.000000e+00)
  %127 = call float @llvm.AMDIL.clamp.(float %30, float 0.000000e+00, float 1.000000e+00)
  %128 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float 1.000000e+00)
  %129 = call float @llvm.AMDIL.clamp.(float %32, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %126, float %127, float %128, float %129)
  %130 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %131 = load <16 x i8> addrspace(2)* %130, !tbaa !0
  %132 = call float @llvm.SI.load.const(<16 x i8> %131, i32 0)
  %133 = fmul float %132, %90
  %134 = call float @llvm.SI.load.const(<16 x i8> %131, i32 4)
  %135 = fmul float %134, %97
  %136 = fadd float %133, %135
  %137 = call float @llvm.SI.load.const(<16 x i8> %131, i32 8)
  %138 = fmul float %137, %104
  %139 = fadd float %136, %138
  %140 = call float @llvm.SI.load.const(<16 x i8> %131, i32 12)
  %141 = fmul float %140, %111
  %142 = fadd float %139, %141
  %143 = call float @llvm.SI.load.const(<16 x i8> %131, i32 16)
  %144 = fmul float %143, %90
  %145 = call float @llvm.SI.load.const(<16 x i8> %131, i32 20)
  %146 = fmul float %145, %97
  %147 = fadd float %144, %146
  %148 = call float @llvm.SI.load.const(<16 x i8> %131, i32 24)
  %149 = fmul float %148, %104
  %150 = fadd float %147, %149
  %151 = call float @llvm.SI.load.const(<16 x i8> %131, i32 28)
  %152 = fmul float %151, %111
  %153 = fadd float %150, %152
  %154 = call float @llvm.SI.load.const(<16 x i8> %131, i32 32)
  %155 = fmul float %154, %90
  %156 = call float @llvm.SI.load.const(<16 x i8> %131, i32 36)
  %157 = fmul float %156, %97
  %158 = fadd float %155, %157
  %159 = call float @llvm.SI.load.const(<16 x i8> %131, i32 40)
  %160 = fmul float %159, %104
  %161 = fadd float %158, %160
  %162 = call float @llvm.SI.load.const(<16 x i8> %131, i32 44)
  %163 = fmul float %162, %111
  %164 = fadd float %161, %163
  %165 = call float @llvm.SI.load.const(<16 x i8> %131, i32 48)
  %166 = fmul float %165, %90
  %167 = call float @llvm.SI.load.const(<16 x i8> %131, i32 52)
  %168 = fmul float %167, %97
  %169 = fadd float %166, %168
  %170 = call float @llvm.SI.load.const(<16 x i8> %131, i32 56)
  %171 = fmul float %170, %104
  %172 = fadd float %169, %171
  %173 = call float @llvm.SI.load.const(<16 x i8> %131, i32 60)
  %174 = fmul float %173, %111
  %175 = fadd float %172, %174
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %142, float %153, float %164, float %175)
  %176 = call float @llvm.SI.load.const(<16 x i8> %131, i32 64)
  %177 = fmul float %176, %90
  %178 = call float @llvm.SI.load.const(<16 x i8> %131, i32 68)
  %179 = fmul float %178, %97
  %180 = fadd float %177, %179
  %181 = call float @llvm.SI.load.const(<16 x i8> %131, i32 72)
  %182 = fmul float %181, %104
  %183 = fadd float %180, %182
  %184 = call float @llvm.SI.load.const(<16 x i8> %131, i32 76)
  %185 = fmul float %184, %111
  %186 = fadd float %183, %185
  %187 = call float @llvm.SI.load.const(<16 x i8> %131, i32 80)
  %188 = fmul float %187, %90
  %189 = call float @llvm.SI.load.const(<16 x i8> %131, i32 84)
  %190 = fmul float %189, %97
  %191 = fadd float %188, %190
  %192 = call float @llvm.SI.load.const(<16 x i8> %131, i32 88)
  %193 = fmul float %192, %104
  %194 = fadd float %191, %193
  %195 = call float @llvm.SI.load.const(<16 x i8> %131, i32 92)
  %196 = fmul float %195, %111
  %197 = fadd float %194, %196
  %198 = call float @llvm.SI.load.const(<16 x i8> %131, i32 96)
  %199 = fmul float %198, %90
  %200 = call float @llvm.SI.load.const(<16 x i8> %131, i32 100)
  %201 = fmul float %200, %97
  %202 = fadd float %199, %201
  %203 = call float @llvm.SI.load.const(<16 x i8> %131, i32 104)
  %204 = fmul float %203, %104
  %205 = fadd float %202, %204
  %206 = call float @llvm.SI.load.const(<16 x i8> %131, i32 108)
  %207 = fmul float %206, %111
  %208 = fadd float %205, %207
  %209 = call float @llvm.SI.load.const(<16 x i8> %131, i32 112)
  %210 = fmul float %209, %90
  %211 = call float @llvm.SI.load.const(<16 x i8> %131, i32 116)
  %212 = fmul float %211, %97
  %213 = fadd float %210, %212
  %214 = call float @llvm.SI.load.const(<16 x i8> %131, i32 120)
  %215 = fmul float %214, %104
  %216 = fadd float %213, %215
  %217 = call float @llvm.SI.load.const(<16 x i8> %131, i32 124)
  %218 = fmul float %217, %111
  %219 = fadd float %216, %218
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %186, float %197, float %208, float %219)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %115, float %117, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %123, float %125, float %120, float %111)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 191
	S_WAITCNT 127
	%VGPR1<def> = V_ADD_F32_e64 %SGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 190
	S_WAITCNT 127
	%VGPR2<def> = V_ADD_F32_e64 %SGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 189
	S_WAITCNT 127
	%VGPR3<def> = V_ADD_F32_e64 %SGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 188
	S_WAITCNT 127
	%VGPR4<def> = V_ADD_F32_e64 %SGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%51](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 217
	S_WAITCNT 112
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 216
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 218
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 219
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR9, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 221
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 220
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 222
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 223
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR9, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR4, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 225
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 224
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 226
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 227
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR9, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 35
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %SGPR4, %VGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 37
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 36
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR4, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 38
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 39
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR4, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%130](tbaa=!"const")
	S_WAITCNT 127
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 41
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 40
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR4, %SGPR5<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 42
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR5<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 43
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR4, %VGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR5<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 45
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR4<kill>, %SGPR5<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %SGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR8<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29
	S_WAITCNT 15
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 30
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 31
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 19
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR8<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 4; mem:LD16[%58](tbaa=!"const")
	S_WAITCNT 15
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 112
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR5<kill>, %VGPR0<kill>, %VGPR6<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 228
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 229
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840100
bf8c007f
c20109bf
bf8c007f
d2060801
02010002
c20109be
bf8c007f
d2060802
02010002
c20109bd
bf8c007f
d2060803
02010002
c20109bc
bf8c007f
d2060804
02010002
f800020f
01020304
c0860700
bf8c000f
e00c2000
80030600
c20109d9
bf8c0070
10020e02
c20109d8
bf8c007f
d2820001
04040506
c20109da
bf8c007f
d2820001
04040508
c20109db
bf8c007f
d2820004
04040509
c20109dd
bf8c007f
10020e02
c20109dc
bf8c007f
d2820001
04040506
c20109de
bf8c007f
d2820001
04040508
c20109df
bf8c007f
d2820005
04040509
c2010921
bf8c007f
10020a02
c2010920
bf8c007f
d2820001
04040504
c20109e1
bf8c007f
10040e02
c20109e0
bf8c007f
d2820002
04080506
c20109e2
bf8c007f
d2820002
04080508
c20109e3
bf8c007f
d2820006
04080509
c2010922
bf8c007f
d2820001
04040506
c2020901
c2010923
bf8c007f
7e040202
d2820001
04060404
c2010925
bf8c007f
10040a02
c2010924
bf8c007f
d2820002
04080504
c2010926
bf8c007f
d2820002
04080506
c2010927
bf8c007f
7e060202
d2820002
040a0604
c0800104
bf8c007f
c202810d
bf8c007f
10060405
c202810c
bf8c007f
d2820007
040e0205
c2028929
bf8c007f
10060a05
c2028928
bf8c007f
d2820003
040c0b04
c202892a
bf8c007f
d2820003
040c0b06
c202892b
bf8c007f
7e100205
d2820003
040e1004
c202810e
bf8c007f
d2820007
041e0605
c202892d
bf8c007f
100a0a05
c202892c
bf8c007f
d2820004
04140b04
c202892e
bf8c007f
d2820004
04100b06
c202892f
bf8c007f
7e0a0205
d2820004
04120a04
c202010f
bf8c007f
d2820005
041e0804
c2020109
bf8c007f
100c0404
c2020108
bf8c007f
d2820006
041a0204
c202010a
bf8c007f
d2820006
041a0604
c202010b
bf8c007f
d2820006
041a0804
c2020105
bf8c007f
100e0404
c2020104
bf8c007f
d2820007
041e0204
c2020106
bf8c007f
d2820007
041e0604
c2020107
bf8c007f
d2820007
041e0804
c2020101
bf8c007f
10100404
c2020100
bf8c007f
d2820008
04220204
c2020102
bf8c007f
d2820008
04220604
c2020103
bf8c007f
d2820008
04220804
f80000ef
05060708
c202011d
bf8c000f
100a0404
c202011c
bf8c007f
d2820005
04160204
c202011e
bf8c007f
d2820005
04160604
c202011f
bf8c007f
d2820005
04160804
c2020119
bf8c007f
100c0404
c2020118
bf8c007f
d2820006
041a0204
c202011a
bf8c007f
d2820006
041a0604
c202011b
bf8c007f
d2820006
041a0804
c2020115
bf8c007f
100e0404
c2020114
bf8c007f
d2820007
041e0204
c2020116
bf8c007f
d2820007
041e0604
c2020117
bf8c007f
d2820007
041e0804
c2020111
bf8c007f
10100404
c2020110
bf8c007f
d2820008
04220204
c2020112
bf8c007f
d2820008
04220604
c2000113
bf8c007f
d2820008
04220800
f80000ff
05060708
c0800704
bf8c000f
e00c2000
80000500
c20009c5
bf8c0070
10000c00
c20009c1
bf8c007f
d2820000
04000105
c20009c4
bf8c007f
10120c00
c20009c0
bf8c007f
d2820005
04240105
7e0c0280
f800021f
06060005
c20009e4
bf8c000f
d2820000
04060800
c2000902
bf8c007f
10020600
08020901
c20009e5
bf8c007f
10060800
08040503
f80008cf
04010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
DCL TEMP[1], ARRAY(1), LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0].w, TEMP[0], SAMP[0], 2D
  2: MUL TEMP[0].x, TEMP[0].wwww, IN[0].wwww
  3: MOV TEMP[0].w, TEMP[0].xxxx
  4: MOV TEMP[0].xyz, IMM[0].xxxx
  5: MOV TEMP[1], TEMP[0]
  6: MOV OUT[0], TEMP[1]
  7: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %27 = bitcast float %25 to i32
  %28 = bitcast float %26 to i32
  %29 = insertelement <2 x i32> undef, i32 %27, i32 0
  %30 = insertelement <2 x i32> %29, i32 %28, i32 1
  %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %21, <16 x i8> %23, i32 2)
  %32 = extractelement <4 x float> %31, i32 3
  %33 = fmul float %32, %24
  %34 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 1.000000e+00)
  %35 = bitcast i32 %34 to float
  %36 = call i32 @llvm.SI.packf16(float 1.000000e+00, float %33)
  %37 = bitcast i32 %36 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %35, float %37, float %35, float %37)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 1.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 1.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0500
c80d0501
c8080400
c8090401
c0800300
c0c40500
bf8c007f
f0800800
00020202
c80c0300
c80d0301
bf8c0770
10000702
5e0000f2
d25e0001
0201e4f2
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL CONST[0..215]
DCL TEMP[0..7], LOCAL
DCL ADDR[0]
IMM[0] FLT32 {  765.0059,     0.0000,     0.0000,     0.0000}
IMM[1] INT32 {2, 1, 0, 0}
  0: ADD TEMP[0].xy, IN[1].xyyy, CONST[0].yyyy
  1: MUL TEMP[1].xyz, IN[2].zyxx, IMM[0].xxxx
  2: MUL TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy
  3: MOV TEMP[3].x, TEMP[1].xyzx
  4: ADD TEMP[4].x, TEMP[2].yyyy, TEMP[2].xxxx
  5: F2I TEMP[5].x, TEMP[1].yyyy
  6: UARL ADDR[0].x, TEMP[5].xxxx
  7: UARL ADDR[0].x, TEMP[5].xxxx
  8: MUL TEMP[5], TEMP[2].yyyy, CONST[ADDR[0].x+54]
  9: ADD TEMP[4].x, -TEMP[4].xxxx, CONST[0].yyyy
 10: F2I TEMP[6].x, TEMP[1].zzzz
 11: F2I TEMP[7].x, TEMP[1].xxxx
 12: UARL ADDR[0].x, TEMP[7].xxxx
 13: MAD TEMP[5], CONST[ADDR[0].x+54], TEMP[2].xxxx, TEMP[5]
 14: UARL ADDR[0].x, TEMP[6].xxxx
 15: MAD TEMP[5], CONST[ADDR[0].x+54], TEMP[4].xxxx, TEMP[5]
 16: DP4 TEMP[1].x, IN[0], TEMP[5]
 17: F2I TEMP[5].x, TEMP[1].yyyy
 18: UADD TEMP[5].x, TEMP[5].xxxx, IMM[1].xxxx
 19: F2I TEMP[6].x, TEMP[3].xxxx
 20: UADD TEMP[6].x, TEMP[6].xxxx, IMM[1].xxxx
 21: UARL ADDR[0].x, TEMP[6].xxxx
 22: MUL TEMP[6], CONST[ADDR[0].x+54], TEMP[2].xxxx
 23: UARL ADDR[0].x, TEMP[5].xxxx
 24: UARL ADDR[0].x, TEMP[5].xxxx
 25: MAD TEMP[0], TEMP[2].yyyy, CONST[ADDR[0].x+54], TEMP[6]
 26: F2I TEMP[5].x, TEMP[1].zzzz
 27: UADD TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
 28: F2I TEMP[6].x, TEMP[1].yyyy
 29: UADD TEMP[6].x, TEMP[6].xxxx, IMM[1].yyyy
 30: F2I TEMP[3].x, TEMP[3].xxxx
 31: UADD TEMP[3].x, TEMP[3].xxxx, IMM[1].yyyy
 32: UARL ADDR[0].x, TEMP[3].xxxx
 33: MUL TEMP[3], CONST[ADDR[0].x+54], TEMP[2].xxxx
 34: UARL ADDR[0].x, TEMP[6].xxxx
 35: MAD TEMP[2], TEMP[2].yyyy, CONST[ADDR[0].x+54], TEMP[3]
 36: UARL ADDR[0].x, TEMP[5].xxxx
 37: MAD TEMP[2], CONST[ADDR[0].x+54], TEMP[4].xxxx, TEMP[2]
 38: DP4 TEMP[2].x, IN[0], TEMP[2]
 39: MOV TEMP[1].y, TEMP[2].xxxx
 40: F2I TEMP[2].x, TEMP[1].zzzz
 41: UADD TEMP[2].x, TEMP[2].xxxx, IMM[1].xxxx
 42: UARL ADDR[0].x, TEMP[2].xxxx
 43: UARL ADDR[0].x, TEMP[2].xxxx
 44: MAD TEMP[2], CONST[ADDR[0].x+54], TEMP[4].xxxx, TEMP[0]
 45: DP4 TEMP[2].x, IN[0], TEMP[2]
 46: MOV TEMP[1].z, TEMP[2].xxxx
 47: MOV TEMP[1].w, CONST[0].yyyy
 48: DP4 TEMP[2].x, TEMP[1], CONST[8]
 49: DP4 TEMP[3].x, TEMP[1], CONST[9]
 50: MOV TEMP[2].y, TEMP[3].xxxx
 51: DP4 TEMP[4].x, TEMP[1], CONST[10]
 52: MOV TEMP[2].z, TEMP[4].xxxx
 53: DP4 TEMP[1].x, TEMP[1], CONST[11]
 54: MOV TEMP[2].w, TEMP[1].xxxx
 55: MUL TEMP[0].xy, IN[3].yyyy, CONST[49].xyyy
 56: MAD TEMP[0].xy, IN[3].xxxx, CONST[48].xyyy, TEMP[0].xyyy
 57: MOV TEMP[5], TEMP[2]
 58: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[1].xxxx
 59: MOV TEMP[2].z, TEMP[4].xxxx
 60: MOV TEMP[2].y, -TEMP[3].xxxx
 61: MAD TEMP[2].xy, CONST[215].xyyy, TEMP[1].xxxx, TEMP[2].xyyy
 62: MOV OUT[3], TEMP[0]
 63: MOV OUT[0], TEMP[2]
 64: MOV OUT[2], TEMP[5]
 65: MOV_SAT OUT[1], CONST[47]
 66: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 752)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 756)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 760)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 764)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 3440)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 3444)
  %39 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %40, i32 0, i32 %5)
  %42 = extractelement <4 x float> %41, i32 0
  %43 = extractelement <4 x float> %41, i32 1
  %44 = extractelement <4 x float> %41, i32 2
  %45 = extractelement <4 x float> %41, i32 3
  %46 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0
  %48 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %47, i32 0, i32 %5)
  %49 = extractelement <4 x float> %48, i32 0
  %50 = extractelement <4 x float> %48, i32 1
  %51 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %52, i32 0, i32 %5)
  %54 = extractelement <4 x float> %53, i32 0
  %55 = extractelement <4 x float> %53, i32 1
  %56 = extractelement <4 x float> %53, i32 2
  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
  %60 = extractelement <4 x float> %59, i32 0
  %61 = extractelement <4 x float> %59, i32 1
  %62 = fadd float %49, %11
  %63 = fadd float %50, %11
  %64 = fmul float %56, 0x4087E80C00000000
  %65 = fmul float %55, 0x4087E80C00000000
  %66 = fmul float %54, 0x4087E80C00000000
  %67 = fmul float %62, 0x3F00000000000000
  %68 = fmul float %63, 0x3F00000000000000
  %69 = fadd float %68, %67
  %70 = fptosi float %65 to i32
  %71 = bitcast i32 %70 to float
  %72 = bitcast float %71 to i32
  %73 = shl i32 %72, 4
  %74 = add i32 %73, 864
  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %74)
  %76 = fmul float %68, %75
  %77 = shl i32 %72, 4
  %78 = add i32 %77, 868
  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %78)
  %80 = fmul float %68, %79
  %81 = shl i32 %72, 4
  %82 = add i32 %81, 872
  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %82)
  %84 = fmul float %68, %83
  %85 = shl i32 %72, 4
  %86 = add i32 %85, 876
  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %86)
  %88 = fmul float %68, %87
  %89 = fsub float -0.000000e+00, %69
  %90 = fadd float %89, %11
  %91 = fptosi float %66 to i32
  %92 = bitcast i32 %91 to float
  %93 = fptosi float %64 to i32
  %94 = bitcast i32 %93 to float
  %95 = bitcast float %94 to i32
  %96 = shl i32 %95, 4
  %97 = add i32 %96, 864
  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %97)
  %99 = fmul float %98, %67
  %100 = fadd float %99, %76
  %101 = shl i32 %95, 4
  %102 = add i32 %101, 868
  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %102)
  %104 = fmul float %103, %67
  %105 = fadd float %104, %80
  %106 = shl i32 %95, 4
  %107 = add i32 %106, 872
  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %107)
  %109 = fmul float %108, %67
  %110 = fadd float %109, %84
  %111 = shl i32 %95, 4
  %112 = add i32 %111, 876
  %113 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %112)
  %114 = fmul float %113, %67
  %115 = fadd float %114, %88
  %116 = bitcast float %92 to i32
  %117 = shl i32 %116, 4
  %118 = add i32 %117, 864
  %119 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %118)
  %120 = fmul float %119, %90
  %121 = fadd float %120, %100
  %122 = shl i32 %116, 4
  %123 = add i32 %122, 868
  %124 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %123)
  %125 = fmul float %124, %90
  %126 = fadd float %125, %105
  %127 = shl i32 %116, 4
  %128 = add i32 %127, 872
  %129 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %128)
  %130 = fmul float %129, %90
  %131 = fadd float %130, %110
  %132 = shl i32 %116, 4
  %133 = add i32 %132, 876
  %134 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %133)
  %135 = fmul float %134, %90
  %136 = fadd float %135, %115
  %137 = fmul float %42, %121
  %138 = fmul float %43, %126
  %139 = fadd float %137, %138
  %140 = fmul float %44, %131
  %141 = fadd float %139, %140
  %142 = fmul float %45, %136
  %143 = fadd float %141, %142
  %144 = fptosi float %65 to i32
  %145 = bitcast i32 %144 to float
  %146 = bitcast float %145 to i32
  %147 = add i32 %146, 2
  %148 = bitcast i32 %147 to float
  %149 = fptosi float %64 to i32
  %150 = bitcast i32 %149 to float
  %151 = bitcast float %150 to i32
  %152 = add i32 %151, 2
  %153 = bitcast i32 %152 to float
  %154 = bitcast float %153 to i32
  %155 = shl i32 %154, 4
  %156 = add i32 %155, 864
  %157 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %156)
  %158 = fmul float %157, %67
  %159 = shl i32 %154, 4
  %160 = add i32 %159, 868
  %161 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %160)
  %162 = fmul float %161, %67
  %163 = shl i32 %154, 4
  %164 = add i32 %163, 872
  %165 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %164)
  %166 = fmul float %165, %67
  %167 = shl i32 %154, 4
  %168 = add i32 %167, 876
  %169 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %168)
  %170 = fmul float %169, %67
  %171 = bitcast float %148 to i32
  %172 = shl i32 %171, 4
  %173 = add i32 %172, 864
  %174 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %173)
  %175 = fmul float %68, %174
  %176 = fadd float %175, %158
  %177 = shl i32 %171, 4
  %178 = add i32 %177, 868
  %179 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %178)
  %180 = fmul float %68, %179
  %181 = fadd float %180, %162
  %182 = shl i32 %171, 4
  %183 = add i32 %182, 872
  %184 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %183)
  %185 = fmul float %68, %184
  %186 = fadd float %185, %166
  %187 = shl i32 %171, 4
  %188 = add i32 %187, 876
  %189 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %188)
  %190 = fmul float %68, %189
  %191 = fadd float %190, %170
  %192 = fptosi float %66 to i32
  %193 = bitcast i32 %192 to float
  %194 = bitcast float %193 to i32
  %195 = add i32 %194, 1
  %196 = bitcast i32 %195 to float
  %197 = fptosi float %65 to i32
  %198 = bitcast i32 %197 to float
  %199 = bitcast float %198 to i32
  %200 = add i32 %199, 1
  %201 = bitcast i32 %200 to float
  %202 = fptosi float %64 to i32
  %203 = bitcast i32 %202 to float
  %204 = bitcast float %203 to i32
  %205 = add i32 %204, 1
  %206 = bitcast i32 %205 to float
  %207 = bitcast float %206 to i32
  %208 = shl i32 %207, 4
  %209 = add i32 %208, 864
  %210 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %209)
  %211 = fmul float %210, %67
  %212 = shl i32 %207, 4
  %213 = add i32 %212, 868
  %214 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %213)
  %215 = fmul float %214, %67
  %216 = shl i32 %207, 4
  %217 = add i32 %216, 872
  %218 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %217)
  %219 = fmul float %218, %67
  %220 = shl i32 %207, 4
  %221 = add i32 %220, 876
  %222 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %221)
  %223 = fmul float %222, %67
  %224 = bitcast float %201 to i32
  %225 = shl i32 %224, 4
  %226 = add i32 %225, 864
  %227 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %226)
  %228 = fmul float %68, %227
  %229 = fadd float %228, %211
  %230 = shl i32 %224, 4
  %231 = add i32 %230, 868
  %232 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %231)
  %233 = fmul float %68, %232
  %234 = fadd float %233, %215
  %235 = shl i32 %224, 4
  %236 = add i32 %235, 872
  %237 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %236)
  %238 = fmul float %68, %237
  %239 = fadd float %238, %219
  %240 = shl i32 %224, 4
  %241 = add i32 %240, 876
  %242 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %241)
  %243 = fmul float %68, %242
  %244 = fadd float %243, %223
  %245 = bitcast float %196 to i32
  %246 = shl i32 %245, 4
  %247 = add i32 %246, 864
  %248 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %247)
  %249 = fmul float %248, %90
  %250 = fadd float %249, %229
  %251 = shl i32 %245, 4
  %252 = add i32 %251, 868
  %253 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %252)
  %254 = fmul float %253, %90
  %255 = fadd float %254, %234
  %256 = shl i32 %245, 4
  %257 = add i32 %256, 872
  %258 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %257)
  %259 = fmul float %258, %90
  %260 = fadd float %259, %239
  %261 = shl i32 %245, 4
  %262 = add i32 %261, 876
  %263 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %262)
  %264 = fmul float %263, %90
  %265 = fadd float %264, %244
  %266 = fmul float %42, %250
  %267 = fmul float %43, %255
  %268 = fadd float %266, %267
  %269 = fmul float %44, %260
  %270 = fadd float %268, %269
  %271 = fmul float %45, %265
  %272 = fadd float %270, %271
  %273 = fptosi float %66 to i32
  %274 = bitcast i32 %273 to float
  %275 = bitcast float %274 to i32
  %276 = add i32 %275, 2
  %277 = bitcast i32 %276 to float
  %278 = bitcast float %277 to i32
  %279 = shl i32 %278, 4
  %280 = add i32 %279, 864
  %281 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %280)
  %282 = fmul float %281, %90
  %283 = fadd float %282, %176
  %284 = shl i32 %278, 4
  %285 = add i32 %284, 868
  %286 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %285)
  %287 = fmul float %286, %90
  %288 = fadd float %287, %181
  %289 = shl i32 %278, 4
  %290 = add i32 %289, 872
  %291 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %290)
  %292 = fmul float %291, %90
  %293 = fadd float %292, %186
  %294 = shl i32 %278, 4
  %295 = add i32 %294, 876
  %296 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %295)
  %297 = fmul float %296, %90
  %298 = fadd float %297, %191
  %299 = fmul float %42, %283
  %300 = fmul float %43, %288
  %301 = fadd float %299, %300
  %302 = fmul float %44, %293
  %303 = fadd float %301, %302
  %304 = fmul float %45, %298
  %305 = fadd float %303, %304
  %306 = fmul float %143, %13
  %307 = fmul float %272, %14
  %308 = fadd float %306, %307
  %309 = fmul float %305, %15
  %310 = fadd float %308, %309
  %311 = fmul float %11, %16
  %312 = fadd float %310, %311
  %313 = fmul float %143, %17
  %314 = fmul float %272, %18
  %315 = fadd float %313, %314
  %316 = fmul float %305, %19
  %317 = fadd float %315, %316
  %318 = fmul float %11, %20
  %319 = fadd float %317, %318
  %320 = fmul float %143, %21
  %321 = fmul float %272, %22
  %322 = fadd float %320, %321
  %323 = fmul float %305, %23
  %324 = fadd float %322, %323
  %325 = fmul float %11, %24
  %326 = fadd float %324, %325
  %327 = fmul float %143, %25
  %328 = fmul float %272, %26
  %329 = fadd float %327, %328
  %330 = fmul float %305, %27
  %331 = fadd float %329, %330
  %332 = fmul float %11, %28
  %333 = fadd float %331, %332
  %334 = fmul float %61, %35
  %335 = fmul float %61, %36
  %336 = fmul float %60, %33
  %337 = fadd float %336, %334
  %338 = fmul float %60, %34
  %339 = fadd float %338, %335
  %340 = fsub float -0.000000e+00, %333
  %341 = fmul float %326, %12
  %342 = fadd float %341, %340
  %343 = fsub float -0.000000e+00, %319
  %344 = fmul float %37, %333
  %345 = fadd float %344, %312
  %346 = fmul float %38, %333
  %347 = fadd float %346, %343
  %348 = call float @llvm.AMDIL.clamp.(float %29, float 0.000000e+00, float 1.000000e+00)
  %349 = call float @llvm.AMDIL.clamp.(float %30, float 0.000000e+00, float 1.000000e+00)
  %350 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float 1.000000e+00)
  %351 = call float @llvm.AMDIL.clamp.(float %32, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %348, float %349, float %350, float %351)
  %352 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %353 = load <16 x i8> addrspace(2)* %352, !tbaa !0
  %354 = call float @llvm.SI.load.const(<16 x i8> %353, i32 0)
  %355 = fmul float %354, %312
  %356 = call float @llvm.SI.load.const(<16 x i8> %353, i32 4)
  %357 = fmul float %356, %319
  %358 = fadd float %355, %357
  %359 = call float @llvm.SI.load.const(<16 x i8> %353, i32 8)
  %360 = fmul float %359, %326
  %361 = fadd float %358, %360
  %362 = call float @llvm.SI.load.const(<16 x i8> %353, i32 12)
  %363 = fmul float %362, %333
  %364 = fadd float %361, %363
  %365 = call float @llvm.SI.load.const(<16 x i8> %353, i32 16)
  %366 = fmul float %365, %312
  %367 = call float @llvm.SI.load.const(<16 x i8> %353, i32 20)
  %368 = fmul float %367, %319
  %369 = fadd float %366, %368
  %370 = call float @llvm.SI.load.const(<16 x i8> %353, i32 24)
  %371 = fmul float %370, %326
  %372 = fadd float %369, %371
  %373 = call float @llvm.SI.load.const(<16 x i8> %353, i32 28)
  %374 = fmul float %373, %333
  %375 = fadd float %372, %374
  %376 = call float @llvm.SI.load.const(<16 x i8> %353, i32 32)
  %377 = fmul float %376, %312
  %378 = call float @llvm.SI.load.const(<16 x i8> %353, i32 36)
  %379 = fmul float %378, %319
  %380 = fadd float %377, %379
  %381 = call float @llvm.SI.load.const(<16 x i8> %353, i32 40)
  %382 = fmul float %381, %326
  %383 = fadd float %380, %382
  %384 = call float @llvm.SI.load.const(<16 x i8> %353, i32 44)
  %385 = fmul float %384, %333
  %386 = fadd float %383, %385
  %387 = call float @llvm.SI.load.const(<16 x i8> %353, i32 48)
  %388 = fmul float %387, %312
  %389 = call float @llvm.SI.load.const(<16 x i8> %353, i32 52)
  %390 = fmul float %389, %319
  %391 = fadd float %388, %390
  %392 = call float @llvm.SI.load.const(<16 x i8> %353, i32 56)
  %393 = fmul float %392, %326
  %394 = fadd float %391, %393
  %395 = call float @llvm.SI.load.const(<16 x i8> %353, i32 60)
  %396 = fmul float %395, %333
  %397 = fadd float %394, %396
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %364, float %375, float %386, float %397)
  %398 = call float @llvm.SI.load.const(<16 x i8> %353, i32 64)
  %399 = fmul float %398, %312
  %400 = call float @llvm.SI.load.const(<16 x i8> %353, i32 68)
  %401 = fmul float %400, %319
  %402 = fadd float %399, %401
  %403 = call float @llvm.SI.load.const(<16 x i8> %353, i32 72)
  %404 = fmul float %403, %326
  %405 = fadd float %402, %404
  %406 = call float @llvm.SI.load.const(<16 x i8> %353, i32 76)
  %407 = fmul float %406, %333
  %408 = fadd float %405, %407
  %409 = call float @llvm.SI.load.const(<16 x i8> %353, i32 80)
  %410 = fmul float %409, %312
  %411 = call float @llvm.SI.load.const(<16 x i8> %353, i32 84)
  %412 = fmul float %411, %319
  %413 = fadd float %410, %412
  %414 = call float @llvm.SI.load.const(<16 x i8> %353, i32 88)
  %415 = fmul float %414, %326
  %416 = fadd float %413, %415
  %417 = call float @llvm.SI.load.const(<16 x i8> %353, i32 92)
  %418 = fmul float %417, %333
  %419 = fadd float %416, %418
  %420 = call float @llvm.SI.load.const(<16 x i8> %353, i32 96)
  %421 = fmul float %420, %312
  %422 = call float @llvm.SI.load.const(<16 x i8> %353, i32 100)
  %423 = fmul float %422, %319
  %424 = fadd float %421, %423
  %425 = call float @llvm.SI.load.const(<16 x i8> %353, i32 104)
  %426 = fmul float %425, %326
  %427 = fadd float %424, %426
  %428 = call float @llvm.SI.load.const(<16 x i8> %353, i32 108)
  %429 = fmul float %428, %333
  %430 = fadd float %427, %429
  %431 = call float @llvm.SI.load.const(<16 x i8> %353, i32 112)
  %432 = fmul float %431, %312
  %433 = call float @llvm.SI.load.const(<16 x i8> %353, i32 116)
  %434 = fmul float %433, %319
  %435 = fadd float %432, %434
  %436 = call float @llvm.SI.load.const(<16 x i8> %353, i32 120)
  %437 = fmul float %436, %326
  %438 = fadd float %435, %437
  %439 = call float @llvm.SI.load.const(<16 x i8> %353, i32 124)
  %440 = fmul float %439, %333
  %441 = fadd float %438, %440
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %408, float %419, float %430, float %441)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %337, float %339, float %186, float %191)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %345, float %347, float %342, float %333)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 191
	S_WAITCNT 127
	%VGPR1<def> = V_ADD_F32_e64 %SGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 190
	S_WAITCNT 127
	%VGPR2<def> = V_ADD_F32_e64 %SGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 189
	S_WAITCNT 127
	%VGPR3<def> = V_ADD_F32_e64 %SGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 188
	S_WAITCNT 127
	%VGPR4<def> = V_ADD_F32_e64 %SGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%51](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR1<def> = V_MUL_F32_e32 7.650059e+02, %VGPR7, %EXEC<imp-use>
	%VGPR5<def> = V_CVT_I32_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_LSHLREV_B32_e32 4, %VGPR5, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_I32_e32 864, %VGPR4, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR3<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%46](tbaa=!"const")
	S_WAITCNT 112
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 112
	%VGPR2<def> = V_ADD_F32_e32 %SGPR2, %VGPR14, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 3.051758e-05, %VGPR2, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR1, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 7.650059e+02, %VGPR8, %EXEC<imp-use>
	%VGPR10<def> = V_CVT_I32_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_LSHLREV_B32_e32 4, %VGPR10, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_I32_e32 864, %VGPR12, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR17<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 %SGPR2, %VGPR13, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%VGPR3<def> = V_MUL_F32_e32 3.051758e-05, %VGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR14<def> = V_MAD_F32 %VGPR17<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 3.051758e-05, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %VGPR11<kill>, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %SGPR2, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 7.650059e+02, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%VGPR11<def> = V_CVT_I32_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_LSHLREV_B32_e32 4, %VGPR11, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_I32_e32 864, %VGPR13, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR6<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR6<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR14<def> = V_MAD_F32 %VGPR6<kill>, %VGPR2, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_I32_e32 868, %VGPR4, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR6<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR6<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_MUL_F32_e32 %VGPR1, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_I32_e32 868, %VGPR12, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR7<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR7<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_MAD_F32 %VGPR7<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_I32_e32 868, %VGPR13, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR7<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR7<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MAD_F32 %VGPR7<kill>, %VGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%39](tbaa=!"const")
	S_WAITCNT 127
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MUL_F32_e32 %VGPR7, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR6, %VGPR14<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_I32_e32 872, %VGPR4, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR15<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MUL_F32_e32 %VGPR1, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_I32_e32 872, %VGPR12, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR16<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR16<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MAD_F32 %VGPR16<kill>, %VGPR3, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_I32_e32 872, %VGPR13, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR16<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR16<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MAD_F32 %VGPR16<kill>, %VGPR2, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR8, %VGPR15<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 876, %VGPR4<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR4<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_MUL_F32_e32 %VGPR1, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_I32_e32 876, %VGPR12<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR12<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR12<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_MAD_F32 %VGPR12<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_I32_e32 876, %VGPR13<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR12<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR12<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_MAD_F32 %VGPR12<kill>, %VGPR2, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR9, %VGPR4<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_I32_e32 1, %VGPR10, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR12<def> = V_LSHLREV_B32_e32 4, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 864, %VGPR12, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR13<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR13<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR14<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 1, %VGPR5, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR13<def> = V_LSHLREV_B32_e32 4, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_I32_e32 864, %VGPR13, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR15<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MAD_F32 %VGPR1, %VGPR15<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_I32_e32 1, %VGPR11, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR14<def> = V_LSHLREV_B32_e32 4, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_I32_e32 864, %VGPR14, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR16<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR16<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MAD_F32 %VGPR16<kill>, %VGPR2, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_I32_e32 868, %VGPR12, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR16<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR16<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_I32_e32 868, %VGPR13, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR17<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR17<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR16<def> = V_MAD_F32 %VGPR1, %VGPR17<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_I32_e32 868, %VGPR14, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR17<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR17<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR16<def> = V_MAD_F32 %VGPR17<kill>, %VGPR2, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR7, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR6, %VGPR15<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_I32_e32 872, %VGPR12, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR16<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR16<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_I32_e32 872, %VGPR13, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR17<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR17<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR16<def> = V_MAD_F32 %VGPR1, %VGPR17<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_I32_e32 872, %VGPR14, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR17<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR17<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR16<def> = V_MAD_F32 %VGPR17<kill>, %VGPR2, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR8, %VGPR16<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_I32_e32 876, %VGPR12<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR12<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR12<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 876, %VGPR13<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR13<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR13<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR12<def> = V_MAD_F32 %VGPR1, %VGPR13<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 876, %VGPR14<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR13<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR13<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR12<def> = V_MAD_F32 %VGPR13<kill>, %VGPR2, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR9, %VGPR12<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR12, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR4, %SGPR3<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_I32_e32 2, %VGPR10<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR10<def> = V_LSHLREV_B32_e32 4, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_I32_e32 864, %VGPR10, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR14<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR14<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 2, %VGPR5<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR14<def> = V_LSHLREV_B32_e32 4, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 864, %VGPR14, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR5<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR5<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MAD_F32 %VGPR1, %VGPR5<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_I32_e32 2, %VGPR11<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR11<def> = V_LSHLREV_B32_e32 4, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_I32_e32 864, %VGPR11, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR15<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MAD_F32 %VGPR15<kill>, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_I32_e32 868, %VGPR10, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR15<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_I32_e32 868, %VGPR14, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR16<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR16<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MAD_F32 %VGPR1, %VGPR16<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_I32_e32 868, %VGPR11, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR16<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR16<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MAD_F32 %VGPR16<kill>, %VGPR2, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR7, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR6, %VGPR5<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 872, %VGPR10, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR5<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR5<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_I32_e32 872, %VGPR14, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR16<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR16<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MAD_F32 %VGPR1, %VGPR16<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_I32_e32 872, %VGPR11, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR16<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR16<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR16<def> = V_MAD_F32 %VGPR16<kill>, %VGPR2, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR8, %VGPR16<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_I32_e32 876, %VGPR10<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR10<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR10<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR3<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_I32_e32 876, %VGPR14<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR10<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR10<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR1<def> = V_MAD_F32 %VGPR1<kill>, %VGPR10<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_I32_e32 876, %VGPR11<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR3<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR3<kill>, %VGPR2<kill>, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR9, %VGPR2<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR3<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 35
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR2, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 37
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR12, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 36
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR4, %SGPR3<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 38
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR3<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 39
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR2, %VGPR6<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%352](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 41
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR12, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 40
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR4, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 42
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 43
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR2, %VGPR9<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 45
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR4<kill>, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR7<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR2<kill>, %VGPR7<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 9
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR2, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 11
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR2, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR2, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 29
	S_WAITCNT 15
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 28
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR0<kill>, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 30
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 31
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 25
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 24
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR2, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 26
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 27
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 21
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 20
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR2, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 22
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 23
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 17
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 16
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR2, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 18
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 19
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 12; mem:LD16[%57](tbaa=!"const")
	S_WAITCNT 15
	%VGPR7_VGPR8_VGPR9_VGPR10<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 112
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8_VGPR9_VGPR10<imp-use,kill>
	EXP 15, 33, 0, 0, 0, %VGPR7<kill>, %VGPR0<kill>, %VGPR5<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_MOV_B32 3440
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_SGPR %SGPR8_SGPR9_SGPR10_SGPR11, %SGPR0<kill>
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_MOV_B32 3444
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_SGPR %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0<kill>
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840100
bf8c007f
c20109bf
bf8c007f
d2060801
02010002
c20109be
bf8c007f
d2060802
02010002
c20109bd
bf8c007f
d2060803
02010002
c20109bc
bf8c007f
d2060804
02010002
f800020f
01020304
c0860708
bf8c000f
e00c2000
80030600
bf8c0770
10020eff
443f4060
7e0a1101
34080a84
4a0208ff
00000360
e0301000
80020301
c0860704
bf8c0070
e00c2000
80030d00
c2010901
bf8c0070
06041c02
100204ff
38000000
10160701
100610ff
443f4060
7e141103
34181484
4a0618ff
00000360
e0301000
80021103
06061a02
100606ff
38000000
bf8c0770
d282000e
042e0711
7e1602ff
38000000
d2820002
040e1702
08040402
100c0cff
443f4060
7e161106
341a1684
4a0c1aff
00000360
e0301000
80020606
bf8c0770
d282000e
043a0506
4a0c08ff
00000364
e0301000
80020606
bf8c0770
100c0d01
4a0e18ff
00000364
e0301000
80020707
bf8c0770
d2820006
041a0707
4a0e1aff
00000364
e0301000
80020707
bf8c0770
d282000f
041a0507
c0860700
bf8c007f
e00c2000
80030600
bf8c0770
101e1f07
d282000e
043e1d06
4a1e08ff
00000368
e0301000
80020f0f
bf8c0770
101e1f01
4a2018ff
00000368
e0301000
80021010
bf8c0770
d282000f
043e0710
4a201aff
00000368
e0301000
80021010
bf8c0770
d282000f
043e0510
d282000e
043a1f08
4a0808ff
0000036c
e0301000
80020404
bf8c0770
10080901
4a1818ff
0000036c
e0301000
80020c0c
bf8c0770
d2820004
0412070c
4a181aff
0000036c
e0301000
80020c0c
bf8c0770
d2820004
0412050c
d2820004
043a0909
4a181481
34181884
4a1a18ff
00000360
e0301000
80020d0d
bf8c0770
101c070d
4a1a0a81
341a1a84
4a1e1aff
00000360
e0301000
80020f0f
bf8c0770
d282000f
043a1f01
4a1c1681
341c1c84
4a201cff
00000360
e0301000
80021010
bf8c0770
d282000f
043e0510
4a2018ff
00000364
e0301000
80021010
bf8c0770
10200710
4a221aff
00000364
e0301000
80021111
bf8c0770
d2820010
04422301
4a221cff
00000364
e0301000
80021111
bf8c0770
d2820010
04420511
10202107
d282000f
04421f06
4a2018ff
00000368
e0301000
80021010
bf8c0770
10200710
4a221aff
00000368
e0301000
80021111
bf8c0770
d2820010
04422301
4a221cff
00000368
e0301000
80021111
bf8c0770
d2820010
04420511
d282000f
043e2108
4a1818ff
0000036c
e0301000
80020c0c
bf8c0770
1018070c
4a1a1aff
0000036c
e0301000
80020d0d
bf8c0770
d282000c
04321b01
4a1a1cff
0000036c
e0301000
80020d0d
bf8c0770
d282000c
0432050d
d282000c
043e1909
c2018921
bf8c007f
101a1803
c2018920
bf8c007f
d282000d
04340704
4a141482
34141484
4a1c14ff
00000360
e0301000
80020e0e
bf8c0770
101e070e
4a0a0a82
341c0a84
4a0a1cff
00000360
e0301000
80020505
bf8c0770
d2820005
043e0b01
4a161682
34161684
4a1e16ff
00000360
e0301000
80020f0f
bf8c0770
d2820005
0416050f
4a1e14ff
00000364
e0301000
80020f0f
bf8c0770
101e070f
4a201cff
00000364
e0301000
80021010
bf8c0770
d282000f
043e2101
4a2016ff
00000364
e0301000
80021010
bf8c0770
d282000f
043e0510
101e1f07
d282000f
043e0b06
4a0a14ff
00000368
e0301000
80020505
bf8c0770
100a0705
4a201cff
00000368
e0301000
80021010
bf8c0770
d2820005
04162101
4a2016ff
00000368
e0301000
80021010
bf8c0770
d2820010
04160510
d282000f
043e2108
4a1414ff
0000036c
e0301000
80020a0a
bf8c0770
1006070a
4a141cff
0000036c
e0301000
80020a0a
bf8c0770
d2820001
040e1501
4a0616ff
0000036c
e0301000
80020303
bf8c0770
d2820002
04060503
d2820007
043e0509
c2018922
bf8c007f
d2820002
04340707
c2018923
bf8c007f
7e060203
d2820002
040a0602
c2018925
bf8c007f
10061803
c2018924
bf8c007f
d2820003
040c0704
c2018926
bf8c007f
d2820003
040c0707
c2018927
bf8c007f
7e0c0203
d2820003
040e0c02
c0860104
bf8c007f
c2000d0d
bf8c007f
100c0600
c2000d0c
bf8c007f
d2820008
041a0400
c2000929
bf8c007f
100c1800
c2000928
bf8c007f
d2820006
04180104
c200092a
bf8c007f
d2820006
04180107
c200092b
bf8c007f
7e120200
d2820006
041a1202
c2000d0e
bf8c007f
d2820008
04220c00
c200092d
bf8c007f
10121800
c200092c
bf8c007f
d2820004
04240104
c200092e
bf8c007f
d2820004
04100107
c200092f
bf8c007f
7e0e0200
d2820004
04120e02
c2000d0f
bf8c007f
d2820007
04220800
c2000d09
bf8c007f
10100600
c2000d08
bf8c007f
d2820008
04220400
c2000d0a
bf8c007f
d2820008
04220c00
c2000d0b
bf8c007f
d2820008
04220800
c2000d05
bf8c007f
10120600
c2000d04
bf8c007f
d2820009
04260400
c2000d06
bf8c007f
d2820009
04260c00
c2000d07
bf8c007f
d2820009
04260800
c2000d01
bf8c007f
10140600
c2000d00
bf8c007f
d282000a
042a0400
c2000d02
bf8c007f
d282000a
042a0c00
c2000d03
bf8c007f
d282000a
042a0800
f80000ef
0708090a
c2000d1d
bf8c000f
100e0600
c2000d1c
bf8c007f
d2820007
041e0400
c2000d1e
bf8c007f
d2820007
041e0c00
c2000d1f
bf8c007f
d2820007
041e0800
c2000d19
bf8c007f
10100600
c2000d18
bf8c007f
d2820008
04220400
c2000d1a
bf8c007f
d2820008
04220c00
c2000d1b
bf8c007f
d2820008
04220800
c2000d15
bf8c007f
10120600
c2000d14
bf8c007f
d2820009
04260400
c2000d16
bf8c007f
d2820009
04260c00
c2000d17
bf8c007f
d2820009
04260800
c2000d11
bf8c007f
10140600
c2000d10
bf8c007f
d282000a
042a0400
c2000d12
bf8c007f
d282000a
042a0c00
c2000d13
bf8c007f
d282000a
042a0800
f80000ff
0708090a
c080070c
bf8c000f
e00c2000
80000700
c20009c5
bf8c0070
10001000
c20009c1
bf8c007f
d2820000
04000107
c20009c4
bf8c007f
10161000
c20009c0
bf8c007f
d2820007
042c0107
f800021f
01050007
be8003ff
00000d70
c2000800
bf8c000f
d2820000
040a0800
c2000902
bf8c007f
10020c00
08020901
be8003ff
00000d74
c2000800
bf8c007f
10040800
08040702
f80008cf
04010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE
DCL IN[4], GENERIC[22], PERSPECTIVE, CENTROID
DCL IN[5], GENERIC[23], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..30]
DCL TEMP[0..5], LOCAL
DCL TEMP[6], ARRAY(1), LOCAL
IMM[0] FLT32 {    2.0000,    -1.0000,     1.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[4].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[1], 2D
  2: MOV TEMP[1].xy, IN[4].wzzz
  3: TEX TEMP[1].xyz, TEMP[1], SAMP[1], 2D
  4: MOV TEMP[2].xy, IN[1].xyyy
  5: TEX TEMP[2].xyz, TEMP[2], SAMP[2], 2D
  6: MOV TEMP[3].xy, IN[5].xyyy
  7: TEX TEMP[3].xyz, TEMP[3], SAMP[1], 2D
  8: MOV TEMP[4].xy, IN[2].xyyy
  9: TEX TEMP[4].xyz, TEMP[4], SAMP[3], 2D
 10: MOV TEMP[5].xy, IN[1].xyyy
 11: TEX TEMP[5].xyz, TEMP[5], SAMP[0], 2D
 12: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].yyyy
 13: MAD TEMP[0].xyz, TEMP[2].xxxx, TEMP[0].xyzz, TEMP[1].xyzz
 14: MAD TEMP[0].xyz, TEMP[2].zzzz, TEMP[3].xyzz, TEMP[0].xyzz
 15: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[12].xyzz
 16: MUL TEMP[1].xyz, TEMP[4].xyzz, CONST[8].xyzz
 17: MAD TEMP[1].xyz, IMM[0].xxxx, TEMP[1].xyzz, IMM[0].yyyy
 18: MAD TEMP[1].xyz, CONST[8].wwww, TEMP[1].xyzz, IMM[0].zzzz
 19: MUL TEMP[2].xyz, TEMP[5].xyzz, TEMP[1].xyzz
 20: MUL TEMP[2].xyz, TEMP[2].xyzz, IN[0].xyzz
 21: MAD TEMP[3].x, IN[3].wwww, CONST[11].wwww, -CONST[11].xxxx
 22: MUL TEMP[2].xyz, TEMP[0].xyzz, TEMP[2].xyzz
 23: MIN TEMP[0].x, TEMP[3].xxxx, CONST[11].zzzz
 24: MOV_SAT TEMP[0].x, TEMP[0].xxxx
 25: MAD TEMP[1].xyz, TEMP[2].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 26: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx
 27: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[0].xxxx
 28: MAD TEMP[2].xyz, TEMP[2].xyzz, CONST[30].xxxx, TEMP[1].xyzz
 29: MUL TEMP[0].x, IN[3].wwww, CONST[29].wwww
 30: MOV TEMP[2].w, TEMP[0].xxxx
 31: MOV TEMP[6], TEMP[2]
 32: MOV OUT[0], TEMP[6]
 33: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 136)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 140)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 188)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %42 = load <32 x i8> addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %46 = load <32 x i8> addrspace(2)* %45, !tbaa !0
  %47 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %50 = load <32 x i8> addrspace(2)* %49, !tbaa !0
  %51 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %54 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %55 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %56 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %57 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %59 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %60 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
  %61 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %6)
  %62 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %6)
  %63 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %6)
  %64 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %6)
  %65 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %6)
  %66 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %6)
  %67 = bitcast float %61 to i32
  %68 = bitcast float %62 to i32
  %69 = insertelement <2 x i32> undef, i32 %67, i32 0
  %70 = insertelement <2 x i32> %69, i32 %68, i32 1
  %71 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %70, <32 x i8> %42, <16 x i8> %44, i32 2)
  %72 = extractelement <4 x float> %71, i32 0
  %73 = extractelement <4 x float> %71, i32 1
  %74 = extractelement <4 x float> %71, i32 2
  %75 = bitcast float %64 to i32
  %76 = bitcast float %63 to i32
  %77 = insertelement <2 x i32> undef, i32 %75, i32 0
  %78 = insertelement <2 x i32> %77, i32 %76, i32 1
  %79 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %78, <32 x i8> %42, <16 x i8> %44, i32 2)
  %80 = extractelement <4 x float> %79, i32 0
  %81 = extractelement <4 x float> %79, i32 1
  %82 = extractelement <4 x float> %79, i32 2
  %83 = bitcast float %56 to i32
  %84 = bitcast float %57 to i32
  %85 = insertelement <2 x i32> undef, i32 %83, i32 0
  %86 = insertelement <2 x i32> %85, i32 %84, i32 1
  %87 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %86, <32 x i8> %46, <16 x i8> %48, i32 2)
  %88 = extractelement <4 x float> %87, i32 0
  %89 = extractelement <4 x float> %87, i32 1
  %90 = extractelement <4 x float> %87, i32 2
  %91 = bitcast float %65 to i32
  %92 = bitcast float %66 to i32
  %93 = insertelement <2 x i32> undef, i32 %91, i32 0
  %94 = insertelement <2 x i32> %93, i32 %92, i32 1
  %95 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %94, <32 x i8> %42, <16 x i8> %44, i32 2)
  %96 = extractelement <4 x float> %95, i32 0
  %97 = extractelement <4 x float> %95, i32 1
  %98 = extractelement <4 x float> %95, i32 2
  %99 = bitcast float %58 to i32
  %100 = bitcast float %59 to i32
  %101 = insertelement <2 x i32> undef, i32 %99, i32 0
  %102 = insertelement <2 x i32> %101, i32 %100, i32 1
  %103 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %102, <32 x i8> %50, <16 x i8> %52, i32 2)
  %104 = extractelement <4 x float> %103, i32 0
  %105 = extractelement <4 x float> %103, i32 1
  %106 = extractelement <4 x float> %103, i32 2
  %107 = bitcast float %56 to i32
  %108 = bitcast float %57 to i32
  %109 = insertelement <2 x i32> undef, i32 %107, i32 0
  %110 = insertelement <2 x i32> %109, i32 %108, i32 1
  %111 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %110, <32 x i8> %38, <16 x i8> %40, i32 2)
  %112 = extractelement <4 x float> %111, i32 0
  %113 = extractelement <4 x float> %111, i32 1
  %114 = extractelement <4 x float> %111, i32 2
  %115 = fmul float %80, %89
  %116 = fmul float %81, %89
  %117 = fmul float %82, %89
  %118 = fmul float %88, %72
  %119 = fadd float %118, %115
  %120 = fmul float %88, %73
  %121 = fadd float %120, %116
  %122 = fmul float %88, %74
  %123 = fadd float %122, %117
  %124 = fmul float %90, %96
  %125 = fadd float %124, %119
  %126 = fmul float %90, %97
  %127 = fadd float %126, %121
  %128 = fmul float %90, %98
  %129 = fadd float %128, %123
  %130 = fmul float %125, %29
  %131 = fmul float %127, %30
  %132 = fmul float %129, %31
  %133 = fmul float %104, %22
  %134 = fmul float %105, %23
  %135 = fmul float %106, %24
  %136 = fmul float 2.000000e+00, %133
  %137 = fadd float %136, -1.000000e+00
  %138 = fmul float 2.000000e+00, %134
  %139 = fadd float %138, -1.000000e+00
  %140 = fmul float 2.000000e+00, %135
  %141 = fadd float %140, -1.000000e+00
  %142 = fmul float %25, %137
  %143 = fadd float %142, 1.000000e+00
  %144 = fmul float %25, %139
  %145 = fadd float %144, 1.000000e+00
  %146 = fmul float %25, %141
  %147 = fadd float %146, 1.000000e+00
  %148 = fmul float %112, %143
  %149 = fmul float %113, %145
  %150 = fmul float %114, %147
  %151 = fmul float %148, %53
  %152 = fmul float %149, %54
  %153 = fmul float %150, %55
  %154 = fsub float -0.000000e+00, %26
  %155 = fmul float %60, %28
  %156 = fadd float %155, %154
  %157 = fmul float %130, %151
  %158 = fmul float %131, %152
  %159 = fmul float %132, %153
  %160 = fcmp uge float %156, %27
  %161 = select i1 %160, float %27, float %156
  %162 = call float @llvm.AMDIL.clamp.(float %161, float 0.000000e+00, float 1.000000e+00)
  %163 = fsub float -0.000000e+00, %36
  %164 = fmul float %157, %163
  %165 = fadd float %164, %32
  %166 = fsub float -0.000000e+00, %36
  %167 = fmul float %158, %166
  %168 = fadd float %167, %33
  %169 = fsub float -0.000000e+00, %36
  %170 = fmul float %159, %169
  %171 = fadd float %170, %34
  %172 = fmul float %162, %162
  %173 = fmul float %165, %172
  %174 = fmul float %168, %172
  %175 = fmul float %171, %172
  %176 = fmul float %157, %36
  %177 = fadd float %176, %173
  %178 = fmul float %158, %36
  %179 = fadd float %178, %174
  %180 = fmul float %159, %36
  %181 = fadd float %180, %175
  %182 = fmul float %60, %35
  %183 = call i32 @llvm.SI.packf16(float %177, float %179)
  %184 = bitcast i32 %183 to float
  %185 = call i32 @llvm.SI.packf16(float %181, float %182)
  %186 = bitcast i32 %185 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %184, float %186, float %184, float %186)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%47](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%45](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR2, 2, 4, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR3, 2, 4, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR2, 3, 4, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<tied0>, %VGPR3, 3, 4, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%43](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%41](tbaa=!"const")
	S_WAITCNT 112
	%VGPR7_VGPR8_VGPR9<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MUL_F32_e32 %VGPR8, %VGPR5, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR2, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<tied0>, %VGPR3, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR2, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<tied0>, %VGPR3, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10_VGPR11_VGPR12<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR10_VGPR11<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MAD_F32 %VGPR4, %VGPR11, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR2, 1, 5, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-def>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<tied0>, %VGPR3, 1, 5, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR2, 0, 5, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<tied0>, %VGPR3, 0, 5, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR15_VGPR16_VGPR17<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR15_VGPR16<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %VGPR16, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR18_VGPR19<imp-def>
	%VGPR19<def,tied1> = V_INTERP_P2_F32 %VGPR19<tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR18_VGPR19<imp-use,kill>, %VGPR18_VGPR19<imp-def>
	%VGPR18<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR18_VGPR19<imp-use,kill>, %VGPR18_VGPR19<imp-def>
	%VGPR18<def,tied1> = V_INTERP_P2_F32 %VGPR18<tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR18_VGPR19<imp-use,kill>, %VGPR18_VGPR19<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 12; mem:LD16[%51](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 24; mem:LD32[%49](tbaa=!"const")
	S_WAITCNT 127
	%VGPR18_VGPR19_VGPR20<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR18_VGPR19<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33
	S_WAITCNT 112
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0, %VGPR19, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR19, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 35
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %SGPR0, %VGPR3<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%39](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%37](tbaa=!"const")
	S_WAITCNT 127
	%VGPR21_VGPR22_VGPR23<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR3<def> = V_MUL_F32_e32 %VGPR22, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 120
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR1, %VGPR13, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 117
	S_WAITCNT 127
	%VGPR14<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 3, %M0<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR24<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR13<kill>, %SGPR1, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR7, %VGPR5, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR4, %VGPR10, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR6, %VGPR15, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32
	S_WAITCNT 127
	%VGPR24<def> = V_MUL_F32_e32 %SGPR2, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR18, %SGPR2<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %SGPR0, %VGPR24<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR21, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR25<def,tied1> = V_INTERP_P2_F32 %VGPR25<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR1, %VGPR14, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 116
	S_WAITCNT 127
	%VGPR24<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR14<kill>, %SGPR1, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR14<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR9, %VGPR5, %EXEC<imp-use>, %VGPR7_VGPR8_VGPR9<imp-use,kill>
	%VGPR7<def> = V_MAD_F32 %VGPR4, %VGPR12, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12<imp-use,kill>
	%VGPR4<def> = V_MAD_F32 %VGPR6, %VGPR17, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR4_VGPR5_VGPR6<imp-use,kill>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2, %VGPR20, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR20, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20<imp-use,kill>
	%VGPR5<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR23, %VGPR5<kill>, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23<imp-use,kill>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR1, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 118
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR1<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 119
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR13<kill>, %VGPR0<kill>, %VGPR13, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8380500
c8390501
c8340400
c8350401
c0840308
c0c60510
bf8c007f
f0800700
0043040d
c8201202
c8211203
c81c1302
c81d1303
c0840304
c0c60508
bf8c0070
f0800700
00430707
bf8c0770
101e0b08
c82c1102
c82d1103
c8281002
c8291003
f0800700
00430a0a
bf8c0770
d2820012
043e1704
c8401502
c8411503
c83c1402
c83d1403
f0800700
00430f0f
bf8c0770
d2820002
044a2106
c0840100
bf8c007f
c2000931
bf8c007f
10040400
c84c0900
c84d0901
c8480800
c8490801
c086030c
c0c80518
bf8c007f
f0800700
00641212
c2000921
bf8c0070
10062600
d2820003
040c0113
060606f3
c2000923
bf8c007f
d2820003
03ca0600
c0860300
c0c80500
bf8c007f
f0800700
0064150d
bf8c0770
10060716
c8340100
c8350101
10061b03
101a0702
c2008978
bf8c007f
10041a01
c2010975
bf8c007f
081c0402
c8080f00
c8090f01
c201092f
bf8c007f
10060402
c201092c
bf8c007f
0a060602
c201092e
bf8c007f
d00c0004
02000503
7e300202
d2000003
00123103
d2060803
02010103
10060703
101c070e
d282000d
0438030d
101c0b07
d282000e
043a1504
d282000e
043a1f06
c2010930
bf8c007f
101c1c02
c2010920
bf8c007f
10302402
d2820018
04600512
063030f3
d2820018
03ca3000
10303115
c8640000
c8650001
10303318
101c310e
10301c01
c2010974
bf8c007f
08303002
10300718
d282000e
0460030e
5e1a1b0e
100e0b09
d2820007
041e1904
d2820004
041e2306
c2010932
bf8c007f
10080802
c2010922
bf8c007f
100a2802
d2820005
04140514
060a0af3
d2820005
03ca0a00
100a0b17
c8180200
c8190201
10000d05
10000104
10020001
c2000976
bf8c007f
08020200
10020701
d2820000
04040300
c2000977
bf8c007f
10020400
5e000300
f8001c0f
000d000d
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL OUT[7], GENERIC[23]
DCL CONST[0..55]
DCL TEMP[0..11], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[52]
  2: DP4 TEMP[2].x, TEMP[0], CONST[53]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[54]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[6]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: MUL TEMP[5].xy, IN[1].xyyy, CONST[48].xyyy
 12: DP4 TEMP[6].x, TEMP[0], CONST[7]
 13: MOV TEMP[2].w, TEMP[6].xxxx
 14: ADD TEMP[7].x, TEMP[5].yyyy, TEMP[5].xxxx
 15: DP4 TEMP[8].x, TEMP[0], CONST[12]
 16: ADD TEMP[7].x, TEMP[7].xxxx, CONST[48].wwww
 17: MUL TEMP[5].xy, IN[1].xyyy, CONST[49].xyyy
 18: MUL TEMP[0].xy, IN[1].xyyy, CONST[50].xyyy
 19: ADD TEMP[9].x, TEMP[5].yyyy, TEMP[5].xxxx
 20: ADD TEMP[10].x, TEMP[0].yyyy, TEMP[0].xxxx
 21: ADD TEMP[9].x, TEMP[9].xxxx, CONST[49].wwww
 22: MOV TEMP[7].y, TEMP[9].xxxx
 23: ADD TEMP[9].x, TEMP[10].xxxx, CONST[50].wwww
 24: MUL TEMP[5].xy, IN[1].xyyy, CONST[51].xyyy
 25: MUL TEMP[0].xy, IN[1].xyyy, CONST[14].xyyy
 26: ADD TEMP[10].x, TEMP[5].yyyy, TEMP[5].xxxx
 27: ADD TEMP[11].x, TEMP[0].yyyy, TEMP[0].xxxx
 28: ADD TEMP[10].x, TEMP[10].xxxx, CONST[51].wwww
 29: MOV TEMP[9].y, TEMP[10].xxxx
 30: ADD TEMP[10].x, TEMP[11].xxxx, CONST[14].wwww
 31: MOV TEMP[10].z, TEMP[10].xxxx
 32: MUL TEMP[5].xy, IN[1].xyyy, CONST[15].xyyy
 33: ADD TEMP[0].xy, IN[3].xyyy, IN[2].xyyy
 34: ADD TEMP[5].x, TEMP[5].yyyy, TEMP[5].xxxx
 35: ADD TEMP[11].xy, TEMP[0].yxxx, IN[3].yxxx
 36: MOV TEMP[0].zw, TEMP[11].yyxy
 37: ADD TEMP[5].x, TEMP[5].xxxx, CONST[15].wwww
 38: MOV TEMP[10].w, TEMP[5].xxxx
 39: MOV TEMP[0], TEMP[0]
 40: ADD TEMP[10].xy, TEMP[11].yxxx, IN[3].xyyy
 41: MOV TEMP[1].w, TEMP[8].xxxx
 42: MOV TEMP[9].zw, CONST[0].xxxx
 43: MAD TEMP[5], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 44: MOV TEMP[8], TEMP[2]
 45: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[6].xxxx
 46: MOV TEMP[2].z, TEMP[4].xxxx
 47: MOV TEMP[2].y, -TEMP[3].xxxx
 48: MAD TEMP[2].xy, CONST[55].xyyy, TEMP[6].xxxx, TEMP[2].xyyy
 49: MOV OUT[3], TEMP[7]
 50: MOV OUT[4], TEMP[9]
 51: MOV OUT[6], TEMP[0]
 52: MOV OUT[7], TEMP[10]
 53: MOV OUT[0], TEMP[2]
 54: MOV OUT[5], TEMP[1]
 55: MOV OUT[2], TEMP[8]
 56: MOV_SAT OUT[1], TEMP[5]
 57: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 252)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 764)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 800)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 804)
  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 812)
  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 816)
  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 820)
  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 828)
  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 832)
  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 836)
  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 840)
  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 844)
  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 848)
  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 852)
  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 856)
  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 860)
  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 864)
  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 868)
  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 872)
  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 876)
  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 880)
  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 884)
  %67 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
  %69 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %5)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = extractelement <4 x float> %69, i32 2
  %73 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %74 = load <16 x i8> addrspace(2)* %73, !tbaa !0
  %75 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %74, i32 0, i32 %5)
  %76 = extractelement <4 x float> %75, i32 0
  %77 = extractelement <4 x float> %75, i32 1
  %78 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %79 = load <16 x i8> addrspace(2)* %78, !tbaa !0
  %80 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %79, i32 0, i32 %5)
  %81 = extractelement <4 x float> %80, i32 0
  %82 = extractelement <4 x float> %80, i32 1
  %83 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %84 = load <16 x i8> addrspace(2)* %83, !tbaa !0
  %85 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %84, i32 0, i32 %5)
  %86 = extractelement <4 x float> %85, i32 0
  %87 = extractelement <4 x float> %85, i32 1
  %88 = fmul float %70, %12
  %89 = fadd float %88, %11
  %90 = fmul float %71, %12
  %91 = fadd float %90, %11
  %92 = fmul float %72, %12
  %93 = fadd float %92, %11
  %94 = fmul float %70, %11
  %95 = fadd float %94, %12
  %96 = fmul float %89, %53
  %97 = fmul float %91, %54
  %98 = fadd float %96, %97
  %99 = fmul float %93, %55
  %100 = fadd float %98, %99
  %101 = fmul float %95, %56
  %102 = fadd float %100, %101
  %103 = fmul float %89, %57
  %104 = fmul float %91, %58
  %105 = fadd float %103, %104
  %106 = fmul float %93, %59
  %107 = fadd float %105, %106
  %108 = fmul float %95, %60
  %109 = fadd float %107, %108
  %110 = fmul float %89, %61
  %111 = fmul float %91, %62
  %112 = fadd float %110, %111
  %113 = fmul float %93, %63
  %114 = fadd float %112, %113
  %115 = fmul float %95, %64
  %116 = fadd float %114, %115
  %117 = fmul float %89, %14
  %118 = fmul float %91, %15
  %119 = fadd float %117, %118
  %120 = fmul float %93, %16
  %121 = fadd float %119, %120
  %122 = fmul float %95, %17
  %123 = fadd float %121, %122
  %124 = fmul float %89, %18
  %125 = fmul float %91, %19
  %126 = fadd float %124, %125
  %127 = fmul float %93, %20
  %128 = fadd float %126, %127
  %129 = fmul float %95, %21
  %130 = fadd float %128, %129
  %131 = fmul float %89, %22
  %132 = fmul float %91, %23
  %133 = fadd float %131, %132
  %134 = fmul float %93, %24
  %135 = fadd float %133, %134
  %136 = fmul float %95, %25
  %137 = fadd float %135, %136
  %138 = fmul float %76, %41
  %139 = fmul float %77, %42
  %140 = fmul float %89, %26
  %141 = fmul float %91, %27
  %142 = fadd float %140, %141
  %143 = fmul float %93, %28
  %144 = fadd float %142, %143
  %145 = fmul float %95, %29
  %146 = fadd float %144, %145
  %147 = fadd float %139, %138
  %148 = fmul float %89, %30
  %149 = fmul float %91, %31
  %150 = fadd float %148, %149
  %151 = fmul float %93, %32
  %152 = fadd float %150, %151
  %153 = fmul float %95, %33
  %154 = fadd float %152, %153
  %155 = fadd float %147, %43
  %156 = fmul float %76, %44
  %157 = fmul float %77, %45
  %158 = fmul float %76, %47
  %159 = fmul float %77, %48
  %160 = fadd float %157, %156
  %161 = fadd float %159, %158
  %162 = fadd float %160, %46
  %163 = fadd float %161, %49
  %164 = fmul float %76, %50
  %165 = fmul float %77, %51
  %166 = fmul float %76, %34
  %167 = fmul float %77, %35
  %168 = fadd float %165, %164
  %169 = fadd float %167, %166
  %170 = fadd float %168, %52
  %171 = fadd float %169, %36
  %172 = fmul float %76, %37
  %173 = fmul float %77, %38
  %174 = fadd float %86, %81
  %175 = fadd float %87, %82
  %176 = fadd float %173, %172
  %177 = fadd float %175, %87
  %178 = fadd float %174, %86
  %179 = fadd float %176, %39
  %180 = fadd float %178, %86
  %181 = fadd float %177, %87
  %182 = fmul float %40, %11
  %183 = fadd float %182, %12
  %184 = fmul float %40, %11
  %185 = fadd float %184, %12
  %186 = fmul float %40, %11
  %187 = fadd float %186, %12
  %188 = fmul float %40, %12
  %189 = fadd float %188, %11
  %190 = fsub float -0.000000e+00, %146
  %191 = fmul float %137, %13
  %192 = fadd float %191, %190
  %193 = fsub float -0.000000e+00, %130
  %194 = fmul float %65, %146
  %195 = fadd float %194, %123
  %196 = fmul float %66, %146
  %197 = fadd float %196, %193
  %198 = call float @llvm.AMDIL.clamp.(float %183, float 0.000000e+00, float 1.000000e+00)
  %199 = call float @llvm.AMDIL.clamp.(float %185, float 0.000000e+00, float 1.000000e+00)
  %200 = call float @llvm.AMDIL.clamp.(float %187, float 0.000000e+00, float 1.000000e+00)
  %201 = call float @llvm.AMDIL.clamp.(float %189, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %198, float %199, float %200, float %201)
  %202 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %203 = load <16 x i8> addrspace(2)* %202, !tbaa !0
  %204 = call float @llvm.SI.load.const(<16 x i8> %203, i32 0)
  %205 = fmul float %204, %123
  %206 = call float @llvm.SI.load.const(<16 x i8> %203, i32 4)
  %207 = fmul float %206, %130
  %208 = fadd float %205, %207
  %209 = call float @llvm.SI.load.const(<16 x i8> %203, i32 8)
  %210 = fmul float %209, %137
  %211 = fadd float %208, %210
  %212 = call float @llvm.SI.load.const(<16 x i8> %203, i32 12)
  %213 = fmul float %212, %146
  %214 = fadd float %211, %213
  %215 = call float @llvm.SI.load.const(<16 x i8> %203, i32 16)
  %216 = fmul float %215, %123
  %217 = call float @llvm.SI.load.const(<16 x i8> %203, i32 20)
  %218 = fmul float %217, %130
  %219 = fadd float %216, %218
  %220 = call float @llvm.SI.load.const(<16 x i8> %203, i32 24)
  %221 = fmul float %220, %137
  %222 = fadd float %219, %221
  %223 = call float @llvm.SI.load.const(<16 x i8> %203, i32 28)
  %224 = fmul float %223, %146
  %225 = fadd float %222, %224
  %226 = call float @llvm.SI.load.const(<16 x i8> %203, i32 32)
  %227 = fmul float %226, %123
  %228 = call float @llvm.SI.load.const(<16 x i8> %203, i32 36)
  %229 = fmul float %228, %130
  %230 = fadd float %227, %229
  %231 = call float @llvm.SI.load.const(<16 x i8> %203, i32 40)
  %232 = fmul float %231, %137
  %233 = fadd float %230, %232
  %234 = call float @llvm.SI.load.const(<16 x i8> %203, i32 44)
  %235 = fmul float %234, %146
  %236 = fadd float %233, %235
  %237 = call float @llvm.SI.load.const(<16 x i8> %203, i32 48)
  %238 = fmul float %237, %123
  %239 = call float @llvm.SI.load.const(<16 x i8> %203, i32 52)
  %240 = fmul float %239, %130
  %241 = fadd float %238, %240
  %242 = call float @llvm.SI.load.const(<16 x i8> %203, i32 56)
  %243 = fmul float %242, %137
  %244 = fadd float %241, %243
  %245 = call float @llvm.SI.load.const(<16 x i8> %203, i32 60)
  %246 = fmul float %245, %146
  %247 = fadd float %244, %246
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %214, float %225, float %236, float %247)
  %248 = call float @llvm.SI.load.const(<16 x i8> %203, i32 64)
  %249 = fmul float %248, %123
  %250 = call float @llvm.SI.load.const(<16 x i8> %203, i32 68)
  %251 = fmul float %250, %130
  %252 = fadd float %249, %251
  %253 = call float @llvm.SI.load.const(<16 x i8> %203, i32 72)
  %254 = fmul float %253, %137
  %255 = fadd float %252, %254
  %256 = call float @llvm.SI.load.const(<16 x i8> %203, i32 76)
  %257 = fmul float %256, %146
  %258 = fadd float %255, %257
  %259 = call float @llvm.SI.load.const(<16 x i8> %203, i32 80)
  %260 = fmul float %259, %123
  %261 = call float @llvm.SI.load.const(<16 x i8> %203, i32 84)
  %262 = fmul float %261, %130
  %263 = fadd float %260, %262
  %264 = call float @llvm.SI.load.const(<16 x i8> %203, i32 88)
  %265 = fmul float %264, %137
  %266 = fadd float %263, %265
  %267 = call float @llvm.SI.load.const(<16 x i8> %203, i32 92)
  %268 = fmul float %267, %146
  %269 = fadd float %266, %268
  %270 = call float @llvm.SI.load.const(<16 x i8> %203, i32 96)
  %271 = fmul float %270, %123
  %272 = call float @llvm.SI.load.const(<16 x i8> %203, i32 100)
  %273 = fmul float %272, %130
  %274 = fadd float %271, %273
  %275 = call float @llvm.SI.load.const(<16 x i8> %203, i32 104)
  %276 = fmul float %275, %137
  %277 = fadd float %274, %276
  %278 = call float @llvm.SI.load.const(<16 x i8> %203, i32 108)
  %279 = fmul float %278, %146
  %280 = fadd float %277, %279
  %281 = call float @llvm.SI.load.const(<16 x i8> %203, i32 112)
  %282 = fmul float %281, %123
  %283 = call float @llvm.SI.load.const(<16 x i8> %203, i32 116)
  %284 = fmul float %283, %130
  %285 = fadd float %282, %284
  %286 = call float @llvm.SI.load.const(<16 x i8> %203, i32 120)
  %287 = fmul float %286, %137
  %288 = fadd float %285, %287
  %289 = call float @llvm.SI.load.const(<16 x i8> %203, i32 124)
  %290 = fmul float %289, %146
  %291 = fadd float %288, %290
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %258, float %269, float %280, float %291)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %155, float %162, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %163, float %170, float %11, float %11)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %102, float %109, float %116, float %154)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %174, float %175, float %177, float %178)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %180, float %181, float %171, float %179)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %195, float %197, float %192, float %146)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 191
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR4, %VGPR1, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%67](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_MAD_F32 %VGPR8, %SGPR3, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR9, %SGPR3, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR10, %SGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR3<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8, %SGPR2, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 19
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR4, %SGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 23
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%202](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR4, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 27
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR4, %SGPR0<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 9
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 11
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 29
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 28
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 30
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 31
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 25
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 24
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 26
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 27
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 21
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 20
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 22
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 23
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 17
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 16
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 18
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 19
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%73](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 112
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 199
	S_WAITCNT 127
	%VGPR13<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 195
	S_WAITCNT 127
	%VGPR14<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR14<kill>, %VGPR13<kill>, %VGPR15<kill>, %VGPR15, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 204
	S_WAITCNT 15
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 205
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 207
	S_WAITCNT 127
	%VGPR13<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 200
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 201
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 203
	S_WAITCNT 127
	%VGPR14<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%VGPR16<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR14<kill>, %VGPR13<kill>, %VGPR15<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 15
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR4, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 51
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 217
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 216
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR4, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 218
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 219
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 213
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 212
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR4, %SGPR0<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 214
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 215
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 209
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 208
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR4<kill>, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 210
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR7<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 211
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR8<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR4<kill>, %VGPR15<kill>, %VGPR14<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%78](tbaa=!"const")
	S_WAITCNT 15
	%VGPR17_VGPR18_VGPR19_VGPR20<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 12; mem:LD16[%83](tbaa=!"const")
	S_WAITCNT 112
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_ADD_F32_e32 %VGPR13, %VGPR17, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR6, %VGPR13, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e32 %VGPR14, %VGPR18, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR7, %VGPR14, %EXEC<imp-use>
	EXP 15, 36, 0, 0, 0, %VGPR6<kill>, %VGPR7<kill>, %VGPR4, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 60
	S_WAITCNT 15
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 61
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 63
	S_WAITCNT 127
	%VGPR6<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 56
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 57
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 59
	S_WAITCNT 127
	%VGPR7<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR14, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR0<kill>, %VGPR13, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	EXP 15, 37, 0, 0, 0, %VGPR0<kill>, %VGPR4<kill>, %VGPR7<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 220
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 221
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR5<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840100
bf8c007f
c20209bf
c2010900
bf8c007f
7e040202
c2018901
bf8c007f
7e020203
d2820003
040a0204
d2060803
02010103
d2820004
04060404
d2060804
02010104
f800020f
03040404
c0860700
bf8c000f
e00c2000
80030800
bf8c0770
d2820004
04080708
d2820006
04080709
c2020911
bf8c007f
10060c04
c2020910
bf8c007f
d2820003
040c0904
d2820007
0408070a
c2018912
bf8c007f
d2820002
040c0707
d2820008
04040508
c2018913
bf8c007f
d2820001
04080708
c2018915
bf8c007f
10040c03
c2018914
bf8c007f
d2820002
04080704
c2018916
bf8c007f
d2820002
04080707
c2018917
bf8c007f
d2820002
04080708
c0860104
bf8c007f
c2000d0d
bf8c007f
10060400
c2000d0c
bf8c007f
d2820005
040e0200
c2000919
bf8c007f
10060c00
c2000918
bf8c007f
d2820003
040c0104
c200091a
bf8c007f
d2820003
040c0107
c200091b
bf8c007f
d2820003
040c0108
c2000d0e
bf8c007f
d2820009
04160600
c200091d
bf8c007f
100a0c00
c200091c
bf8c007f
d2820005
04140104
c200091e
bf8c007f
d2820005
04140107
c200091f
bf8c007f
d2820005
04140108
c2000d0f
bf8c007f
d2820009
04260a00
c2000d09
bf8c007f
10140400
c2000d08
bf8c007f
d282000a
042a0200
c2000d0a
bf8c007f
d282000a
042a0600
c2000d0b
bf8c007f
d282000a
042a0a00
c2000d05
bf8c007f
10160400
c2000d04
bf8c007f
d282000b
042e0200
c2000d06
bf8c007f
d282000b
042e0600
c2000d07
bf8c007f
d282000b
042e0a00
c2000d01
bf8c007f
10180400
c2000d00
bf8c007f
d282000c
04320200
c2000d02
bf8c007f
d282000c
04320600
c2000d03
bf8c007f
d282000c
04320a00
f80000ef
090a0b0c
c2000d1d
bf8c000f
10120400
c2000d1c
bf8c007f
d2820009
04260200
c2000d1e
bf8c007f
d2820009
04260600
c2000d1f
bf8c007f
d2820009
04260a00
c2000d19
bf8c007f
10140400
c2000d18
bf8c007f
d282000a
042a0200
c2000d1a
bf8c007f
d282000a
042a0600
c2000d1b
bf8c007f
d282000a
042a0a00
c2000d15
bf8c007f
10160400
c2000d14
bf8c007f
d282000b
042e0200
c2000d16
bf8c007f
d282000b
042e0600
c2000d17
bf8c007f
d282000b
042e0a00
c2000d11
bf8c007f
10180400
c2000d10
bf8c007f
d282000c
04320200
c2000d12
bf8c007f
d282000c
04320600
c2000d13
bf8c007f
d282000c
04320a00
f80000ff
090a0b0c
c0860704
bf8c000f
e00c2000
80030900
c20009c4
bf8c0070
101a1200
c20009c5
bf8c007f
d282000d
0434010a
c20009c7
bf8c007f
061a1a00
c20009c0
bf8c007f
101c1200
c20009c1
bf8c007f
d282000e
0438010a
c20009c3
bf8c007f
061c1c00
7e1e0280
f800021f
0f0f0d0e
c20009cc
bf8c000f
101a1200
c20009cd
bf8c007f
d282000d
0434010a
c20009cf
bf8c007f
061a1a00
c20009c8
bf8c007f
101c1200
c20009c9
bf8c007f
d282000e
0438010a
c20009cb
bf8c007f
061c1c00
7e1e0202
7e200202
f800022f
100f0d0e
c2000931
bf8c000f
101a0c00
c2000930
bf8c007f
d282000d
04340104
c2000932
bf8c007f
d282000d
04340107
c2000933
bf8c007f
d282000d
04340108
c20009d9
bf8c007f
101c0c00
c20009d8
bf8c007f
d282000e
04380104
c20009da
bf8c007f
d282000e
04380107
c20009db
bf8c007f
d282000e
04380108
c20009d5
bf8c007f
101e0c00
c20009d4
bf8c007f
d282000f
043c0104
c20009d6
bf8c007f
d282000f
043c0107
c20009d7
bf8c007f
d282000f
043c0108
c20009d1
bf8c007f
100c0c00
c20009d0
bf8c007f
d2820004
04180104
c20009d2
bf8c007f
d2820004
04100107
c20009d3
bf8c007f
d2820004
04100108
f800023f
0d0e0f04
c0800708
bf8c000f
e00c2000
80001100
c080070c
bf8c0070
e00c2000
80000d00
bf8c0770
060c230d
06001b06
060e250e
06081d07
f800024f
00040706
c200093c
bf8c000f
100c1200
c200093d
bf8c007f
d2820006
0418010a
c200093f
bf8c007f
060c0c00
c2000938
bf8c007f
100e1200
c2000939
bf8c007f
d2820007
041c010a
c200093b
bf8c007f
060e0e00
06081d04
06001b00
f800025f
06070400
c20009dc
bf8c000f
d2820000
04060a00
c2000902
bf8c007f
10020600
08020b01
c20009dd
bf8c007f
10060a00
08040503
f80008cf
05010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..30]
DCL TEMP[0..2], LOCAL
DCL TEMP[3], ARRAY(1), LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
  2: MUL TEMP[0].xyz, TEMP[0].xyzz, IN[0].xyzz
  3: MAD TEMP[1].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
  4: MOV TEMP[2].xy, IN[3].xyyy
  5: TEX TEMP[2].xyz, TEMP[2], SAMP[1], 2D
  6: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[12].xyzz
  7: MIN TEMP[1].x, TEMP[1].xxxx, CONST[11].zzzz
  8: MOV_SAT TEMP[1].x, TEMP[1].xxxx
  9: MUL TEMP[2].xyz, TEMP[0].xyzz, TEMP[2].xyzz
 10: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 11: MAD TEMP[0].xyz, TEMP[2].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 12: MUL TEMP[0].xyz, TEMP[1].xxxx, TEMP[0].xyzz
 13: MAD TEMP[2].xyz, TEMP[2].xyzz, CONST[30].xxxx, TEMP[0].xyzz
 14: MUL TEMP[0].x, IN[2].wwww, CONST[29].wwww
 15: MOV TEMP[2].w, TEMP[0].xxxx
 16: MOV TEMP[3], TEMP[2]
 17: MOV OUT[0], TEMP[3]
 18: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 188)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %33 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0
  %35 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %43 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %44 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %45 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %46 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %47 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %6)
  %48 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %6)
  %49 = bitcast float %44 to i32
  %50 = bitcast float %45 to i32
  %51 = insertelement <2 x i32> undef, i32 %49, i32 0
  %52 = insertelement <2 x i32> %51, i32 %50, i32 1
  %53 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %52, <32 x i8> %34, <16 x i8> %36, i32 2)
  %54 = extractelement <4 x float> %53, i32 0
  %55 = extractelement <4 x float> %53, i32 1
  %56 = extractelement <4 x float> %53, i32 2
  %57 = fmul float %54, %41
  %58 = fmul float %55, %42
  %59 = fmul float %56, %43
  %60 = fsub float -0.000000e+00, %22
  %61 = fmul float %46, %24
  %62 = fadd float %61, %60
  %63 = bitcast float %47 to i32
  %64 = bitcast float %48 to i32
  %65 = insertelement <2 x i32> undef, i32 %63, i32 0
  %66 = insertelement <2 x i32> %65, i32 %64, i32 1
  %67 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %66, <32 x i8> %38, <16 x i8> %40, i32 2)
  %68 = extractelement <4 x float> %67, i32 0
  %69 = extractelement <4 x float> %67, i32 1
  %70 = extractelement <4 x float> %67, i32 2
  %71 = fmul float %68, %25
  %72 = fmul float %69, %26
  %73 = fmul float %70, %27
  %74 = fcmp uge float %62, %23
  %75 = select i1 %74, float %23, float %62
  %76 = call float @llvm.AMDIL.clamp.(float %75, float 0.000000e+00, float 1.000000e+00)
  %77 = fmul float %57, %71
  %78 = fmul float %58, %72
  %79 = fmul float %59, %73
  %80 = fmul float %76, %76
  %81 = fsub float -0.000000e+00, %32
  %82 = fmul float %77, %81
  %83 = fadd float %82, %28
  %84 = fsub float -0.000000e+00, %32
  %85 = fmul float %78, %84
  %86 = fadd float %85, %29
  %87 = fsub float -0.000000e+00, %32
  %88 = fmul float %79, %87
  %89 = fadd float %88, %30
  %90 = fmul float %80, %83
  %91 = fmul float %80, %86
  %92 = fmul float %80, %89
  %93 = fmul float %77, %32
  %94 = fadd float %93, %90
  %95 = fmul float %78, %32
  %96 = fadd float %95, %91
  %97 = fmul float %79, %32
  %98 = fadd float %97, %92
  %99 = fmul float %46, %31
  %100 = call i32 @llvm.SI.packf16(float %94, float %96)
  %101 = bitcast i32 %100 to float
  %102 = call i32 @llvm.SI.packf16(float %98, float %99)
  %103 = bitcast i32 %102 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %101, float %103, float %101, float %103)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR2, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR3, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR2, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR3, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%39](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%37](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%35](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%33](tbaa=!"const")
	S_WAITCNT 127
	%VGPR5_VGPR6_VGPR7<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR9<def> = V_MUL_F32_e32 %VGPR6, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 120
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0, %VGPR10, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 117
	S_WAITCNT 127
	%VGPR11<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR9<def> = V_SUBREV_F32_e32 %SGPR1<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR9, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 %VGPR9<kill>, %VGPR12<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e64 %VGPR9<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR9, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR10<kill>, %SGPR0, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR5, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0, %VGPR11, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 116
	S_WAITCNT 127
	%VGPR12<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR9, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %SGPR0, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR11<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR4, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4<imp-use,kill>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR7, %VGPR3<kill>, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0, %VGPR0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 118
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 119
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR10<kill>, %VGPR0<kill>, %VGPR10, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140d02
c8150d03
c8100c02
c8110c03
c0840304
c0c60508
bf8c007f
f0800700
00430204
c0840100
bf8c0070
c2000931
bf8c007f
10100600
c8180500
c8190501
c8140400
c8150401
c0800300
c0c60500
bf8c007f
f0800700
00030505
c8240100
c8250101
bf8c0770
10121306
10141109
c2000978
bf8c007f
10101400
c2008975
bf8c007f
08161001
c8200b00
c8210b01
c200892f
bf8c007f
10121001
c200892c
bf8c007f
0a121201
c200892e
bf8c007f
d00c0002
02000309
7e180201
d2000009
000a1909
d2060809
02010109
10121309
10161709
d282000a
042c010a
c2008930
bf8c007f
10160401
c8300000
c8310001
10181905
1016170c
10181600
c2008974
bf8c007f
08181801
10181909
d282000b
0430010b
5e14150b
c2008932
bf8c007f
10040801
c80c0200
c80d0201
10000707
10000500
10020000
c2008976
bf8c007f
08020201
10020309
d2820000
04040100
c2000977
bf8c007f
10021000
5e000300
f8001c0f
000a000a
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL CONST[0..51]
DCL TEMP[0..8], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[12]
 10: DP4 TEMP[5].x, TEMP[0], CONST[6]
 11: MOV TEMP[2].z, TEMP[5].xxxx
 12: DP4 TEMP[0].x, TEMP[0], CONST[7]
 13: MOV TEMP[2].w, TEMP[0].xxxx
 14: MOV TEMP[1].w, TEMP[4].xxxx
 15: MOV TEMP[4].xy, IN[1].xyxx
 16: MUL TEMP[6], IN[2].xyxx, CONST[0].yyxx
 17: MAD TEMP[7], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 18: MOV TEMP[8], TEMP[2]
 19: MAD TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
 20: MOV TEMP[2].z, TEMP[5].xxxx
 21: MOV TEMP[2].y, -TEMP[3].xxxx
 22: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[0].xxxx, TEMP[2].xyyy
 23: MOV OUT[3], TEMP[4]
 24: MOV OUT[5], TEMP[6]
 25: MOV OUT[0], TEMP[2]
 26: MOV OUT[4], TEMP[1]
 27: MOV OUT[2], TEMP[8]
 28: MOV_SAT OUT[1], TEMP[7]
 29: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 764)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 776)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 792)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 800)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 804)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 808)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 812)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 816)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 820)
  %49 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0
  %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %5)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = extractelement <4 x float> %51, i32 1
  %54 = extractelement <4 x float> %51, i32 2
  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
  %62 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %5)
  %63 = extractelement <4 x float> %62, i32 0
  %64 = extractelement <4 x float> %62, i32 1
  %65 = fmul float %52, %12
  %66 = fadd float %65, %11
  %67 = fmul float %53, %12
  %68 = fadd float %67, %11
  %69 = fmul float %54, %12
  %70 = fadd float %69, %11
  %71 = fmul float %52, %11
  %72 = fadd float %71, %12
  %73 = fmul float %66, %35
  %74 = fmul float %68, %36
  %75 = fadd float %73, %74
  %76 = fmul float %70, %37
  %77 = fadd float %75, %76
  %78 = fmul float %72, %38
  %79 = fadd float %77, %78
  %80 = fmul float %66, %39
  %81 = fmul float %68, %40
  %82 = fadd float %80, %81
  %83 = fmul float %70, %41
  %84 = fadd float %82, %83
  %85 = fmul float %72, %42
  %86 = fadd float %84, %85
  %87 = fmul float %66, %43
  %88 = fmul float %68, %44
  %89 = fadd float %87, %88
  %90 = fmul float %70, %45
  %91 = fadd float %89, %90
  %92 = fmul float %72, %46
  %93 = fadd float %91, %92
  %94 = fmul float %66, %14
  %95 = fmul float %68, %15
  %96 = fadd float %94, %95
  %97 = fmul float %70, %16
  %98 = fadd float %96, %97
  %99 = fmul float %72, %17
  %100 = fadd float %98, %99
  %101 = fmul float %66, %18
  %102 = fmul float %68, %19
  %103 = fadd float %101, %102
  %104 = fmul float %70, %20
  %105 = fadd float %103, %104
  %106 = fmul float %72, %21
  %107 = fadd float %105, %106
  %108 = fmul float %66, %30
  %109 = fmul float %68, %31
  %110 = fadd float %108, %109
  %111 = fmul float %70, %32
  %112 = fadd float %110, %111
  %113 = fmul float %72, %33
  %114 = fadd float %112, %113
  %115 = fmul float %66, %22
  %116 = fmul float %68, %23
  %117 = fadd float %115, %116
  %118 = fmul float %70, %24
  %119 = fadd float %117, %118
  %120 = fmul float %72, %25
  %121 = fadd float %119, %120
  %122 = fmul float %66, %26
  %123 = fmul float %68, %27
  %124 = fadd float %122, %123
  %125 = fmul float %70, %28
  %126 = fadd float %124, %125
  %127 = fmul float %72, %29
  %128 = fadd float %126, %127
  %129 = fmul float %63, %12
  %130 = fmul float %64, %12
  %131 = fmul float %63, %11
  %132 = fmul float %63, %11
  %133 = fmul float %34, %11
  %134 = fadd float %133, %12
  %135 = fmul float %34, %11
  %136 = fadd float %135, %12
  %137 = fmul float %34, %11
  %138 = fadd float %137, %12
  %139 = fmul float %34, %12
  %140 = fadd float %139, %11
  %141 = fsub float -0.000000e+00, %128
  %142 = fmul float %121, %13
  %143 = fadd float %142, %141
  %144 = fsub float -0.000000e+00, %107
  %145 = fmul float %47, %128
  %146 = fadd float %145, %100
  %147 = fmul float %48, %128
  %148 = fadd float %147, %144
  %149 = call float @llvm.AMDIL.clamp.(float %134, float 0.000000e+00, float 1.000000e+00)
  %150 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
  %151 = call float @llvm.AMDIL.clamp.(float %138, float 0.000000e+00, float 1.000000e+00)
  %152 = call float @llvm.AMDIL.clamp.(float %140, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %149, float %150, float %151, float %152)
  %153 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %154 = load <16 x i8> addrspace(2)* %153, !tbaa !0
  %155 = call float @llvm.SI.load.const(<16 x i8> %154, i32 0)
  %156 = fmul float %155, %100
  %157 = call float @llvm.SI.load.const(<16 x i8> %154, i32 4)
  %158 = fmul float %157, %107
  %159 = fadd float %156, %158
  %160 = call float @llvm.SI.load.const(<16 x i8> %154, i32 8)
  %161 = fmul float %160, %121
  %162 = fadd float %159, %161
  %163 = call float @llvm.SI.load.const(<16 x i8> %154, i32 12)
  %164 = fmul float %163, %128
  %165 = fadd float %162, %164
  %166 = call float @llvm.SI.load.const(<16 x i8> %154, i32 16)
  %167 = fmul float %166, %100
  %168 = call float @llvm.SI.load.const(<16 x i8> %154, i32 20)
  %169 = fmul float %168, %107
  %170 = fadd float %167, %169
  %171 = call float @llvm.SI.load.const(<16 x i8> %154, i32 24)
  %172 = fmul float %171, %121
  %173 = fadd float %170, %172
  %174 = call float @llvm.SI.load.const(<16 x i8> %154, i32 28)
  %175 = fmul float %174, %128
  %176 = fadd float %173, %175
  %177 = call float @llvm.SI.load.const(<16 x i8> %154, i32 32)
  %178 = fmul float %177, %100
  %179 = call float @llvm.SI.load.const(<16 x i8> %154, i32 36)
  %180 = fmul float %179, %107
  %181 = fadd float %178, %180
  %182 = call float @llvm.SI.load.const(<16 x i8> %154, i32 40)
  %183 = fmul float %182, %121
  %184 = fadd float %181, %183
  %185 = call float @llvm.SI.load.const(<16 x i8> %154, i32 44)
  %186 = fmul float %185, %128
  %187 = fadd float %184, %186
  %188 = call float @llvm.SI.load.const(<16 x i8> %154, i32 48)
  %189 = fmul float %188, %100
  %190 = call float @llvm.SI.load.const(<16 x i8> %154, i32 52)
  %191 = fmul float %190, %107
  %192 = fadd float %189, %191
  %193 = call float @llvm.SI.load.const(<16 x i8> %154, i32 56)
  %194 = fmul float %193, %121
  %195 = fadd float %192, %194
  %196 = call float @llvm.SI.load.const(<16 x i8> %154, i32 60)
  %197 = fmul float %196, %128
  %198 = fadd float %195, %197
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %165, float %176, float %187, float %198)
  %199 = call float @llvm.SI.load.const(<16 x i8> %154, i32 64)
  %200 = fmul float %199, %100
  %201 = call float @llvm.SI.load.const(<16 x i8> %154, i32 68)
  %202 = fmul float %201, %107
  %203 = fadd float %200, %202
  %204 = call float @llvm.SI.load.const(<16 x i8> %154, i32 72)
  %205 = fmul float %204, %121
  %206 = fadd float %203, %205
  %207 = call float @llvm.SI.load.const(<16 x i8> %154, i32 76)
  %208 = fmul float %207, %128
  %209 = fadd float %206, %208
  %210 = call float @llvm.SI.load.const(<16 x i8> %154, i32 80)
  %211 = fmul float %210, %100
  %212 = call float @llvm.SI.load.const(<16 x i8> %154, i32 84)
  %213 = fmul float %212, %107
  %214 = fadd float %211, %213
  %215 = call float @llvm.SI.load.const(<16 x i8> %154, i32 88)
  %216 = fmul float %215, %121
  %217 = fadd float %214, %216
  %218 = call float @llvm.SI.load.const(<16 x i8> %154, i32 92)
  %219 = fmul float %218, %128
  %220 = fadd float %217, %219
  %221 = call float @llvm.SI.load.const(<16 x i8> %154, i32 96)
  %222 = fmul float %221, %100
  %223 = call float @llvm.SI.load.const(<16 x i8> %154, i32 100)
  %224 = fmul float %223, %107
  %225 = fadd float %222, %224
  %226 = call float @llvm.SI.load.const(<16 x i8> %154, i32 104)
  %227 = fmul float %226, %121
  %228 = fadd float %225, %227
  %229 = call float @llvm.SI.load.const(<16 x i8> %154, i32 108)
  %230 = fmul float %229, %128
  %231 = fadd float %228, %230
  %232 = call float @llvm.SI.load.const(<16 x i8> %154, i32 112)
  %233 = fmul float %232, %100
  %234 = call float @llvm.SI.load.const(<16 x i8> %154, i32 116)
  %235 = fmul float %234, %107
  %236 = fadd float %233, %235
  %237 = call float @llvm.SI.load.const(<16 x i8> %154, i32 120)
  %238 = fmul float %237, %121
  %239 = fadd float %236, %238
  %240 = call float @llvm.SI.load.const(<16 x i8> %154, i32 124)
  %241 = fmul float %240, %128
  %242 = fadd float %239, %241
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %209, float %220, float %231, float %242)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %58, float %59, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %79, float %86, float %93, float %114)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %129, float %130, float %131, float %132)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %146, float %148, float %143, float %128)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 191
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR4, %VGPR1, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%49](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6, %SGPR3, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 19
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 23
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%153](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 27
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 9
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 11
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 29
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 28
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 30
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 31
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 25
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 24
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 26
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 27
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 21
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 20
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 22
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 23
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 17
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 16
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 18
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 19
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%55](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13<kill>, %VGPR13, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 51
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 201
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 200
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 202
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 203
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 198
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 199
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 194
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 195
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR2<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 8; mem:LD16[%60](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	EXP 15, 35, 0, 0, 0, %VGPR4<kill>, %VGPR2<kill>, %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 204
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 205
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840100
bf8c007f
c20209bf
c2018900
bf8c007f
7e060203
c2010901
bf8c007f
7e020202
d2820002
040e0204
d2060802
02010102
d2820004
04060604
d2060804
02010104
f800020f
02040404
c0860700
bf8c000f
e00c2000
80030600
bf8c0770
d2820002
040c0506
d2820004
040c0507
c2020911
bf8c007f
100a0804
c2020910
bf8c007f
d282000a
04140902
d2820005
040c0508
c2020912
bf8c007f
d2820003
04280905
d2820006
04040706
c2020913
bf8c007f
d2820001
040c0906
c2020915
bf8c007f
10060804
c2020914
bf8c007f
d2820003
040c0902
c2020916
bf8c007f
d2820003
040c0905
c2020917
bf8c007f
d2820003
040c0906
c0860104
bf8c007f
c2000d0d
bf8c007f
100e0600
c2000d0c
bf8c007f
d2820008
041e0200
c2000919
bf8c007f
100e0800
c2000918
bf8c007f
d2820007
041c0102
c200091a
bf8c007f
d2820007
041c0105
c200091b
bf8c007f
d2820007
041c0106
c2000d0e
bf8c007f
d2820009
04220e00
c200091d
bf8c007f
10100800
c200091c
bf8c007f
d2820008
04200102
c200091e
bf8c007f
d2820008
04200105
c200091f
bf8c007f
d2820008
04200106
c2000d0f
bf8c007f
d2820009
04261000
c2000d09
bf8c007f
10140600
c2000d08
bf8c007f
d282000a
042a0200
c2000d0a
bf8c007f
d282000a
042a0e00
c2000d0b
bf8c007f
d282000a
042a1000
c2000d05
bf8c007f
10160600
c2000d04
bf8c007f
d282000b
042e0200
c2000d06
bf8c007f
d282000b
042e0e00
c2000d07
bf8c007f
d282000b
042e1000
c2000d01
bf8c007f
10180600
c2000d00
bf8c007f
d282000c
04320200
c2000d02
bf8c007f
d282000c
04320e00
c2000d03
bf8c007f
d282000c
04321000
f80000ef
090a0b0c
c2000d1d
bf8c000f
10120600
c2000d1c
bf8c007f
d2820009
04260200
c2000d1e
bf8c007f
d2820009
04260e00
c2000d1f
bf8c007f
d2820009
04261000
c2000d19
bf8c007f
10140600
c2000d18
bf8c007f
d282000a
042a0200
c2000d1a
bf8c007f
d282000a
042a0e00
c2000d1b
bf8c007f
d282000a
042a1000
c2000d15
bf8c007f
10160600
c2000d14
bf8c007f
d282000b
042e0200
c2000d16
bf8c007f
d282000b
042e0e00
c2000d17
bf8c007f
d282000b
042e1000
c2000d11
bf8c007f
10180600
c2000d10
bf8c007f
d282000c
04320200
c2000d12
bf8c007f
d282000c
04320e00
c2000d13
bf8c007f
d282000c
04321000
f80000ff
090a0b0c
c0860704
bf8c000f
e00c2000
80030900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c2000931
bf8c000f
10120800
c2000930
bf8c007f
d2820009
04240102
c2000932
bf8c007f
d2820009
04240105
c2000933
bf8c007f
d2820009
04240106
c20009c9
bf8c007f
10140800
c20009c8
bf8c007f
d282000a
04280102
c20009ca
bf8c007f
d282000a
04280105
c20009cb
bf8c007f
d282000a
04280106
c20009c5
bf8c007f
10160800
c20009c4
bf8c007f
d282000b
042c0102
c20009c6
bf8c007f
d282000b
042c0105
c20009c7
bf8c007f
d282000b
042c0106
c20009c1
bf8c007f
10080800
c20009c0
bf8c007f
d2820002
04100102
c20009c2
bf8c007f
d2820002
04080105
c20009c3
bf8c007f
d2820002
04080106
f800022f
090a0b02
c0820708
bf8c000f
e00c2000
80010900
bf8c0770
10001203
10041402
10081202
f800023f
00000204
c20009cc
bf8c000f
d2820000
04061000
c2000902
bf8c007f
10020e00
08021101
c20009cd
bf8c007f
10041000
08040702
f80008cf
08010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..30]
DCL TEMP[0..3], LOCAL
DCL TEMP[4], ARRAY(1), LOCAL
  0: MOV TEMP[0].xy, IN[3].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[1], 2D
  2: MOV TEMP[1].xy, IN[1].xyyy
  3: TEX TEMP[1], TEMP[1], SAMP[0], 2D
  4: MUL TEMP[2].xyz, TEMP[0].xyzz, CONST[12].xyzz
  5: MUL TEMP[0].xyz, TEMP[1].xyzz, IN[0].xyzz
  6: MUL TEMP[0].xyz, TEMP[2].xyzz, TEMP[0].xyzz
  7: MAD TEMP[2].xyz, TEMP[1].xyzz, IN[0].xyzz, -TEMP[0].xyzz
  8: MAD TEMP[3].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
  9: MAD TEMP[2].xyz, TEMP[1].wwww, TEMP[2].xyzz, TEMP[0].xyzz
 10: MIN TEMP[1].x, TEMP[3].xxxx, CONST[11].zzzz
 11: MOV_SAT TEMP[1].x, TEMP[1].xxxx
 12: MAD TEMP[0].xyz, TEMP[2].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 13: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 14: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx
 15: MAD TEMP[2].xyz, TEMP[2].xyzz, CONST[30].xxxx, TEMP[0].xyzz
 16: MUL TEMP[0].x, IN[2].wwww, CONST[29].wwww
 17: MOV TEMP[2].w, TEMP[0].xxxx
 18: MOV TEMP[4], TEMP[2]
 19: MOV OUT[0], TEMP[4]
 20: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 188)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %33 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0
  %35 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %43 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %44 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %45 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %46 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %47 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %6)
  %48 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %6)
  %49 = bitcast float %47 to i32
  %50 = bitcast float %48 to i32
  %51 = insertelement <2 x i32> undef, i32 %49, i32 0
  %52 = insertelement <2 x i32> %51, i32 %50, i32 1
  %53 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %52, <32 x i8> %38, <16 x i8> %40, i32 2)
  %54 = extractelement <4 x float> %53, i32 0
  %55 = extractelement <4 x float> %53, i32 1
  %56 = extractelement <4 x float> %53, i32 2
  %57 = bitcast float %44 to i32
  %58 = bitcast float %45 to i32
  %59 = insertelement <2 x i32> undef, i32 %57, i32 0
  %60 = insertelement <2 x i32> %59, i32 %58, i32 1
  %61 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %60, <32 x i8> %34, <16 x i8> %36, i32 2)
  %62 = extractelement <4 x float> %61, i32 0
  %63 = extractelement <4 x float> %61, i32 1
  %64 = extractelement <4 x float> %61, i32 2
  %65 = extractelement <4 x float> %61, i32 3
  %66 = fmul float %54, %25
  %67 = fmul float %55, %26
  %68 = fmul float %56, %27
  %69 = fmul float %62, %41
  %70 = fmul float %63, %42
  %71 = fmul float %64, %43
  %72 = fmul float %66, %69
  %73 = fmul float %67, %70
  %74 = fmul float %68, %71
  %75 = fsub float -0.000000e+00, %72
  %76 = fmul float %62, %41
  %77 = fadd float %76, %75
  %78 = fsub float -0.000000e+00, %73
  %79 = fmul float %63, %42
  %80 = fadd float %79, %78
  %81 = fsub float -0.000000e+00, %74
  %82 = fmul float %64, %43
  %83 = fadd float %82, %81
  %84 = fsub float -0.000000e+00, %22
  %85 = fmul float %46, %24
  %86 = fadd float %85, %84
  %87 = fmul float %65, %77
  %88 = fadd float %87, %72
  %89 = fmul float %65, %80
  %90 = fadd float %89, %73
  %91 = fmul float %65, %83
  %92 = fadd float %91, %74
  %93 = fcmp uge float %86, %23
  %94 = select i1 %93, float %23, float %86
  %95 = call float @llvm.AMDIL.clamp.(float %94, float 0.000000e+00, float 1.000000e+00)
  %96 = fsub float -0.000000e+00, %32
  %97 = fmul float %88, %96
  %98 = fadd float %97, %28
  %99 = fsub float -0.000000e+00, %32
  %100 = fmul float %90, %99
  %101 = fadd float %100, %29
  %102 = fsub float -0.000000e+00, %32
  %103 = fmul float %92, %102
  %104 = fadd float %103, %30
  %105 = fmul float %95, %95
  %106 = fmul float %98, %105
  %107 = fmul float %101, %105
  %108 = fmul float %104, %105
  %109 = fmul float %88, %32
  %110 = fadd float %109, %106
  %111 = fmul float %90, %32
  %112 = fadd float %111, %107
  %113 = fmul float %92, %32
  %114 = fadd float %113, %108
  %115 = fmul float %46, %31
  %116 = call i32 @llvm.SI.packf16(float %110, float %112)
  %117 = bitcast i32 %116 to float
  %118 = call i32 @llvm.SI.packf16(float %114, float %115)
  %119 = bitcast i32 %118 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %117, float %119, float %117, float %119)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%35](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%33](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6_VGPR7<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR11<def> = V_MUL_F32_e32 %VGPR5, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR2, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<tied0>, %VGPR3, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR2, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR3, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%39](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%37](tbaa=!"const")
	S_WAITCNT 127
	%VGPR8_VGPR9_VGPR10<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR8_VGPR9<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 49
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR7, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 120
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4, %VGPR11, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 117
	S_WAITCNT 127
	%VGPR12<def> = V_SUB_F32_e32 %SGPR5<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 47
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 44
	S_WAITCNT 127
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR5<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 46
	S_WAITCNT 127
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR13<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %SGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR4, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 48
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR12<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR7, %VGPR12<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %SGPR4, %VGPR12, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 116
	S_WAITCNT 127
	%VGPR13<def> = V_SUB_F32_e32 %SGPR5<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %SGPR4, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR12<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR6, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 50
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR10, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10<imp-use,kill>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR0<def> = V_SUB_F32_e32 %VGPR0<kill>, %VGPR1, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR7, %VGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7<imp-use,kill>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR4, %VGPR0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 118
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR5<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 119
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR11<kill>, %VGPR0<kill>, %VGPR11, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140500
c8150501
c8100400
c8110401
c0840300
c0c60500
bf8c007f
f0800f00
00430404
c8200100
c8210101
bf8c0770
10161105
c8240d02
c8250d03
c8200c02
c8210c03
c0840304
c0c60508
bf8c007f
f0800700
00430808
c0800100
bf8c0070
c2020131
bf8c007f
10041204
10041702
0806050b
d282000b
040a0707
c2020178
bf8c007f
10041604
c2028175
bf8c007f
08180405
c8080b00
c8090b01
c202812f
bf8c007f
10060405
c202812c
bf8c007f
0a060605
c202812e
bf8c007f
d00c0008
02000b03
7e1a0205
d2000003
00221b03
d2060803
02010103
10060703
1018070c
d282000b
0430090b
c8300000
c8310001
10181904
c2028130
bf8c007f
101a1005
101a190d
08181b0c
d282000c
04361907
101a1804
c2028174
bf8c007f
081a1a05
101a070d
d282000c
0434090c
5e16170c
c8300200
c8310201
10001906
c2028132
bf8c007f
10021405
10020101
08000300
d2820000
04060107
10020004
c2028176
bf8c007f
08020205
10020701
d2820000
04040900
c2000177
bf8c007f
10020400
5e000300
f8001c0f
000b000b
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL CONST[0..51]
DCL TEMP[0..8], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[12]
 10: DP4 TEMP[5].x, TEMP[0], CONST[6]
 11: MOV TEMP[2].z, TEMP[5].xxxx
 12: DP4 TEMP[0].x, TEMP[0], CONST[7]
 13: MOV TEMP[2].w, TEMP[0].xxxx
 14: MOV TEMP[1].w, TEMP[4].xxxx
 15: MOV TEMP[4].xy, IN[1].xyxx
 16: MUL TEMP[6], IN[2].xyxx, CONST[0].yyxx
 17: MAD TEMP[7], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 18: MOV TEMP[8], TEMP[2]
 19: MAD TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
 20: MOV TEMP[2].z, TEMP[5].xxxx
 21: MOV TEMP[2].y, -TEMP[3].xxxx
 22: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[0].xxxx, TEMP[2].xyyy
 23: MOV OUT[3], TEMP[4]
 24: MOV OUT[5], TEMP[6]
 25: MOV OUT[0], TEMP[2]
 26: MOV OUT[4], TEMP[1]
 27: MOV OUT[2], TEMP[8]
 28: MOV_SAT OUT[1], TEMP[7]
 29: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 764)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 776)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 792)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 800)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 804)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 808)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 812)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 816)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 820)
  %49 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0
  %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %5)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = extractelement <4 x float> %51, i32 1
  %54 = extractelement <4 x float> %51, i32 2
  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
  %62 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %5)
  %63 = extractelement <4 x float> %62, i32 0
  %64 = extractelement <4 x float> %62, i32 1
  %65 = fmul float %52, %12
  %66 = fadd float %65, %11
  %67 = fmul float %53, %12
  %68 = fadd float %67, %11
  %69 = fmul float %54, %12
  %70 = fadd float %69, %11
  %71 = fmul float %52, %11
  %72 = fadd float %71, %12
  %73 = fmul float %66, %35
  %74 = fmul float %68, %36
  %75 = fadd float %73, %74
  %76 = fmul float %70, %37
  %77 = fadd float %75, %76
  %78 = fmul float %72, %38
  %79 = fadd float %77, %78
  %80 = fmul float %66, %39
  %81 = fmul float %68, %40
  %82 = fadd float %80, %81
  %83 = fmul float %70, %41
  %84 = fadd float %82, %83
  %85 = fmul float %72, %42
  %86 = fadd float %84, %85
  %87 = fmul float %66, %43
  %88 = fmul float %68, %44
  %89 = fadd float %87, %88
  %90 = fmul float %70, %45
  %91 = fadd float %89, %90
  %92 = fmul float %72, %46
  %93 = fadd float %91, %92
  %94 = fmul float %66, %14
  %95 = fmul float %68, %15
  %96 = fadd float %94, %95
  %97 = fmul float %70, %16
  %98 = fadd float %96, %97
  %99 = fmul float %72, %17
  %100 = fadd float %98, %99
  %101 = fmul float %66, %18
  %102 = fmul float %68, %19
  %103 = fadd float %101, %102
  %104 = fmul float %70, %20
  %105 = fadd float %103, %104
  %106 = fmul float %72, %21
  %107 = fadd float %105, %106
  %108 = fmul float %66, %30
  %109 = fmul float %68, %31
  %110 = fadd float %108, %109
  %111 = fmul float %70, %32
  %112 = fadd float %110, %111
  %113 = fmul float %72, %33
  %114 = fadd float %112, %113
  %115 = fmul float %66, %22
  %116 = fmul float %68, %23
  %117 = fadd float %115, %116
  %118 = fmul float %70, %24
  %119 = fadd float %117, %118
  %120 = fmul float %72, %25
  %121 = fadd float %119, %120
  %122 = fmul float %66, %26
  %123 = fmul float %68, %27
  %124 = fadd float %122, %123
  %125 = fmul float %70, %28
  %126 = fadd float %124, %125
  %127 = fmul float %72, %29
  %128 = fadd float %126, %127
  %129 = fmul float %63, %12
  %130 = fmul float %64, %12
  %131 = fmul float %63, %11
  %132 = fmul float %63, %11
  %133 = fmul float %34, %11
  %134 = fadd float %133, %12
  %135 = fmul float %34, %11
  %136 = fadd float %135, %12
  %137 = fmul float %34, %11
  %138 = fadd float %137, %12
  %139 = fmul float %34, %12
  %140 = fadd float %139, %11
  %141 = fsub float -0.000000e+00, %128
  %142 = fmul float %121, %13
  %143 = fadd float %142, %141
  %144 = fsub float -0.000000e+00, %107
  %145 = fmul float %47, %128
  %146 = fadd float %145, %100
  %147 = fmul float %48, %128
  %148 = fadd float %147, %144
  %149 = call float @llvm.AMDIL.clamp.(float %134, float 0.000000e+00, float 1.000000e+00)
  %150 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
  %151 = call float @llvm.AMDIL.clamp.(float %138, float 0.000000e+00, float 1.000000e+00)
  %152 = call float @llvm.AMDIL.clamp.(float %140, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %149, float %150, float %151, float %152)
  %153 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %154 = load <16 x i8> addrspace(2)* %153, !tbaa !0
  %155 = call float @llvm.SI.load.const(<16 x i8> %154, i32 0)
  %156 = fmul float %155, %100
  %157 = call float @llvm.SI.load.const(<16 x i8> %154, i32 4)
  %158 = fmul float %157, %107
  %159 = fadd float %156, %158
  %160 = call float @llvm.SI.load.const(<16 x i8> %154, i32 8)
  %161 = fmul float %160, %121
  %162 = fadd float %159, %161
  %163 = call float @llvm.SI.load.const(<16 x i8> %154, i32 12)
  %164 = fmul float %163, %128
  %165 = fadd float %162, %164
  %166 = call float @llvm.SI.load.const(<16 x i8> %154, i32 16)
  %167 = fmul float %166, %100
  %168 = call float @llvm.SI.load.const(<16 x i8> %154, i32 20)
  %169 = fmul float %168, %107
  %170 = fadd float %167, %169
  %171 = call float @llvm.SI.load.const(<16 x i8> %154, i32 24)
  %172 = fmul float %171, %121
  %173 = fadd float %170, %172
  %174 = call float @llvm.SI.load.const(<16 x i8> %154, i32 28)
  %175 = fmul float %174, %128
  %176 = fadd float %173, %175
  %177 = call float @llvm.SI.load.const(<16 x i8> %154, i32 32)
  %178 = fmul float %177, %100
  %179 = call float @llvm.SI.load.const(<16 x i8> %154, i32 36)
  %180 = fmul float %179, %107
  %181 = fadd float %178, %180
  %182 = call float @llvm.SI.load.const(<16 x i8> %154, i32 40)
  %183 = fmul float %182, %121
  %184 = fadd float %181, %183
  %185 = call float @llvm.SI.load.const(<16 x i8> %154, i32 44)
  %186 = fmul float %185, %128
  %187 = fadd float %184, %186
  %188 = call float @llvm.SI.load.const(<16 x i8> %154, i32 48)
  %189 = fmul float %188, %100
  %190 = call float @llvm.SI.load.const(<16 x i8> %154, i32 52)
  %191 = fmul float %190, %107
  %192 = fadd float %189, %191
  %193 = call float @llvm.SI.load.const(<16 x i8> %154, i32 56)
  %194 = fmul float %193, %121
  %195 = fadd float %192, %194
  %196 = call float @llvm.SI.load.const(<16 x i8> %154, i32 60)
  %197 = fmul float %196, %128
  %198 = fadd float %195, %197
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %165, float %176, float %187, float %198)
  %199 = call float @llvm.SI.load.const(<16 x i8> %154, i32 64)
  %200 = fmul float %199, %100
  %201 = call float @llvm.SI.load.const(<16 x i8> %154, i32 68)
  %202 = fmul float %201, %107
  %203 = fadd float %200, %202
  %204 = call float @llvm.SI.load.const(<16 x i8> %154, i32 72)
  %205 = fmul float %204, %121
  %206 = fadd float %203, %205
  %207 = call float @llvm.SI.load.const(<16 x i8> %154, i32 76)
  %208 = fmul float %207, %128
  %209 = fadd float %206, %208
  %210 = call float @llvm.SI.load.const(<16 x i8> %154, i32 80)
  %211 = fmul float %210, %100
  %212 = call float @llvm.SI.load.const(<16 x i8> %154, i32 84)
  %213 = fmul float %212, %107
  %214 = fadd float %211, %213
  %215 = call float @llvm.SI.load.const(<16 x i8> %154, i32 88)
  %216 = fmul float %215, %121
  %217 = fadd float %214, %216
  %218 = call float @llvm.SI.load.const(<16 x i8> %154, i32 92)
  %219 = fmul float %218, %128
  %220 = fadd float %217, %219
  %221 = call float @llvm.SI.load.const(<16 x i8> %154, i32 96)
  %222 = fmul float %221, %100
  %223 = call float @llvm.SI.load.const(<16 x i8> %154, i32 100)
  %224 = fmul float %223, %107
  %225 = fadd float %222, %224
  %226 = call float @llvm.SI.load.const(<16 x i8> %154, i32 104)
  %227 = fmul float %226, %121
  %228 = fadd float %225, %227
  %229 = call float @llvm.SI.load.const(<16 x i8> %154, i32 108)
  %230 = fmul float %229, %128
  %231 = fadd float %228, %230
  %232 = call float @llvm.SI.load.const(<16 x i8> %154, i32 112)
  %233 = fmul float %232, %100
  %234 = call float @llvm.SI.load.const(<16 x i8> %154, i32 116)
  %235 = fmul float %234, %107
  %236 = fadd float %233, %235
  %237 = call float @llvm.SI.load.const(<16 x i8> %154, i32 120)
  %238 = fmul float %237, %121
  %239 = fadd float %236, %238
  %240 = call float @llvm.SI.load.const(<16 x i8> %154, i32 124)
  %241 = fmul float %240, %128
  %242 = fadd float %239, %241
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %209, float %220, float %231, float %242)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %58, float %59, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %79, float %86, float %93, float %114)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %129, float %130, float %131, float %132)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %146, float %148, float %143, float %128)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 191
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR4, %VGPR1, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%49](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6, %SGPR3, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 19
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 23
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%153](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 27
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 9
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 11
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 29
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 28
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 30
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 31
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 25
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 24
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 26
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 27
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 21
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 20
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 22
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 23
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 17
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 16
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 18
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 19
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%55](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13<kill>, %VGPR13, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 51
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 201
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 200
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 202
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 203
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 198
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 199
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 194
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 195
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR2<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 8; mem:LD16[%60](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	EXP 15, 35, 0, 0, 0, %VGPR4<kill>, %VGPR2<kill>, %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 204
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 205
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840100
bf8c007f
c20209bf
c2018900
bf8c007f
7e060203
c2010901
bf8c007f
7e020202
d2820002
040e0204
d2060802
02010102
d2820004
04060604
d2060804
02010104
f800020f
02040404
c0860700
bf8c000f
e00c2000
80030600
bf8c0770
d2820002
040c0506
d2820004
040c0507
c2020911
bf8c007f
100a0804
c2020910
bf8c007f
d282000a
04140902
d2820005
040c0508
c2020912
bf8c007f
d2820003
04280905
d2820006
04040706
c2020913
bf8c007f
d2820001
040c0906
c2020915
bf8c007f
10060804
c2020914
bf8c007f
d2820003
040c0902
c2020916
bf8c007f
d2820003
040c0905
c2020917
bf8c007f
d2820003
040c0906
c0860104
bf8c007f
c2000d0d
bf8c007f
100e0600
c2000d0c
bf8c007f
d2820008
041e0200
c2000919
bf8c007f
100e0800
c2000918
bf8c007f
d2820007
041c0102
c200091a
bf8c007f
d2820007
041c0105
c200091b
bf8c007f
d2820007
041c0106
c2000d0e
bf8c007f
d2820009
04220e00
c200091d
bf8c007f
10100800
c200091c
bf8c007f
d2820008
04200102
c200091e
bf8c007f
d2820008
04200105
c200091f
bf8c007f
d2820008
04200106
c2000d0f
bf8c007f
d2820009
04261000
c2000d09
bf8c007f
10140600
c2000d08
bf8c007f
d282000a
042a0200
c2000d0a
bf8c007f
d282000a
042a0e00
c2000d0b
bf8c007f
d282000a
042a1000
c2000d05
bf8c007f
10160600
c2000d04
bf8c007f
d282000b
042e0200
c2000d06
bf8c007f
d282000b
042e0e00
c2000d07
bf8c007f
d282000b
042e1000
c2000d01
bf8c007f
10180600
c2000d00
bf8c007f
d282000c
04320200
c2000d02
bf8c007f
d282000c
04320e00
c2000d03
bf8c007f
d282000c
04321000
f80000ef
090a0b0c
c2000d1d
bf8c000f
10120600
c2000d1c
bf8c007f
d2820009
04260200
c2000d1e
bf8c007f
d2820009
04260e00
c2000d1f
bf8c007f
d2820009
04261000
c2000d19
bf8c007f
10140600
c2000d18
bf8c007f
d282000a
042a0200
c2000d1a
bf8c007f
d282000a
042a0e00
c2000d1b
bf8c007f
d282000a
042a1000
c2000d15
bf8c007f
10160600
c2000d14
bf8c007f
d282000b
042e0200
c2000d16
bf8c007f
d282000b
042e0e00
c2000d17
bf8c007f
d282000b
042e1000
c2000d11
bf8c007f
10180600
c2000d10
bf8c007f
d282000c
04320200
c2000d12
bf8c007f
d282000c
04320e00
c2000d13
bf8c007f
d282000c
04321000
f80000ff
090a0b0c
c0860704
bf8c000f
e00c2000
80030900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c2000931
bf8c000f
10120800
c2000930
bf8c007f
d2820009
04240102
c2000932
bf8c007f
d2820009
04240105
c2000933
bf8c007f
d2820009
04240106
c20009c9
bf8c007f
10140800
c20009c8
bf8c007f
d282000a
04280102
c20009ca
bf8c007f
d282000a
04280105
c20009cb
bf8c007f
d282000a
04280106
c20009c5
bf8c007f
10160800
c20009c4
bf8c007f
d282000b
042c0102
c20009c6
bf8c007f
d282000b
042c0105
c20009c7
bf8c007f
d282000b
042c0106
c20009c1
bf8c007f
10080800
c20009c0
bf8c007f
d2820002
04100102
c20009c2
bf8c007f
d2820002
04080105
c20009c3
bf8c007f
d2820002
04080106
f800022f
090a0b02
c0820708
bf8c000f
e00c2000
80010900
bf8c0770
10001203
10041402
10081202
f800023f
00000204
c20009cc
bf8c000f
d2820000
04061000
c2000902
bf8c007f
10020e00
08021101
c20009cd
bf8c007f
10041000
08040702
f80008cf
08010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..30]
DCL TEMP[0..3], LOCAL
DCL TEMP[4], ARRAY(1), LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MOV TEMP[1].xy, IN[3].xyyy
  3: TEX TEMP[2].xyz, TEMP[1], SAMP[1], 2D
  4: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[12].xyzz
  5: MAD TEMP[3].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
  6: MUL TEMP[1].xyz, TEMP[0].xyzz, IN[0].xyzz
  7: MIN TEMP[3].x, TEMP[3].xxxx, CONST[11].zzzz
  8: MOV_SAT TEMP[3].x, TEMP[3].xxxx
  9: MUL TEMP[1].xyz, TEMP[2].xyzz, TEMP[1].xyzz
 10: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[3].xxxx
 11: MAD TEMP[2].xyz, TEMP[1].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 12: MUL TEMP[2].xyz, TEMP[3].xxxx, TEMP[2].xyzz
 13: MUL TEMP[3].x, IN[0].wwww, CONST[12].wwww
 14: MAD TEMP[1].xyz, TEMP[1].xyzz, CONST[30].xxxx, TEMP[2].xyzz
 15: MUL TEMP[0].x, TEMP[0].wwww, TEMP[3].xxxx
 16: MOV TEMP[1].w, TEMP[0].xxxx
 17: MOV TEMP[4], TEMP[1]
 18: MOV OUT[0], TEMP[4]
 19: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 188)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 204)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %33 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0
  %35 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %43 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %44 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %45 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %46 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %47 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %48 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %6)
  %49 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %6)
  %50 = bitcast float %45 to i32
  %51 = bitcast float %46 to i32
  %52 = insertelement <2 x i32> undef, i32 %50, i32 0
  %53 = insertelement <2 x i32> %52, i32 %51, i32 1
  %54 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %53, <32 x i8> %34, <16 x i8> %36, i32 2)
  %55 = extractelement <4 x float> %54, i32 0
  %56 = extractelement <4 x float> %54, i32 1
  %57 = extractelement <4 x float> %54, i32 2
  %58 = extractelement <4 x float> %54, i32 3
  %59 = bitcast float %48 to i32
  %60 = bitcast float %49 to i32
  %61 = insertelement <2 x i32> undef, i32 %59, i32 0
  %62 = insertelement <2 x i32> %61, i32 %60, i32 1
  %63 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %62, <32 x i8> %38, <16 x i8> %40, i32 2)
  %64 = extractelement <4 x float> %63, i32 0
  %65 = extractelement <4 x float> %63, i32 1
  %66 = extractelement <4 x float> %63, i32 2
  %67 = fmul float %64, %25
  %68 = fmul float %65, %26
  %69 = fmul float %66, %27
  %70 = fsub float -0.000000e+00, %22
  %71 = fmul float %47, %24
  %72 = fadd float %71, %70
  %73 = fmul float %55, %41
  %74 = fmul float %56, %42
  %75 = fmul float %57, %43
  %76 = fcmp uge float %72, %23
  %77 = select i1 %76, float %23, float %72
  %78 = call float @llvm.AMDIL.clamp.(float %77, float 0.000000e+00, float 1.000000e+00)
  %79 = fmul float %67, %73
  %80 = fmul float %68, %74
  %81 = fmul float %69, %75
  %82 = fmul float %78, %78
  %83 = fsub float -0.000000e+00, %32
  %84 = fmul float %79, %83
  %85 = fadd float %84, %29
  %86 = fsub float -0.000000e+00, %32
  %87 = fmul float %80, %86
  %88 = fadd float %87, %30
  %89 = fsub float -0.000000e+00, %32
  %90 = fmul float %81, %89
  %91 = fadd float %90, %31
  %92 = fmul float %82, %85
  %93 = fmul float %82, %88
  %94 = fmul float %82, %91
  %95 = fmul float %44, %28
  %96 = fmul float %79, %32
  %97 = fadd float %96, %92
  %98 = fmul float %80, %32
  %99 = fadd float %98, %93
  %100 = fmul float %81, %32
  %101 = fadd float %100, %94
  %102 = fmul float %58, %95
  %103 = fcmp uge float %102, 0x3FD3131320000000
  %104 = sext i1 %103 to i32
  %105 = trunc i32 %104 to i1
  %106 = select i1 %105, float 1.000000e+00, float -1.000000e+00
  call void @llvm.AMDGPU.kill(float %106)
  %107 = call i32 @llvm.SI.packf16(float %97, float %99)
  %108 = bitcast i32 %107 to float
  %109 = call i32 @llvm.SI.packf16(float %101, float %102)
  %110 = bitcast i32 %109 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %108, float %110, float %108, float %110)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.AMDGPU.kill(float)

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%35](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%33](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6_VGPR7<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 51
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR7, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 2.980392e-01, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 -1.000000e+00, 1.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VCC<def> = V_CMPX_LE_F32_e32 0, %VGPR9<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR5, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR2, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<tied0>, %VGPR3, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR2, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<tied0>, %VGPR3, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%39](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%37](tbaa=!"const")
	S_WAITCNT 127
	%VGPR9_VGPR10_VGPR11<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR9_VGPR10<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 112
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR10, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 120
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0, %VGPR3, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 117
	S_WAITCNT 127
	%VGPR12<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR2<def> = V_SUBREV_F32_e32 %SGPR1<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR13<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR2, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %SGPR0, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR4, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0, %VGPR12, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 116
	S_WAITCNT 127
	%VGPR13<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR2, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %SGPR0, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR12<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR6, %VGPR12<kill>, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7<imp-use,kill>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR11, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0, %VGPR0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 118
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR3<kill>, %VGPR0<kill>, %VGPR3, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140500
c8150501
c8100400
c8110401
c0840300
c0c60500
bf8c007f
f0800f00
00430404
c8200300
c8210301
c0840100
bf8c0070
c2000933
bf8c007f
10101000
10101107
7e1202ff
3e989899
d00c0000
02021308
d2000009
0001e4f3
7c261280
c8240100
c8250101
10181305
c8280d02
c8290d03
c8240c02
c8250c03
c0800304
c0c60508
bf8c007f
f0800700
00030909
c2000931
bf8c0070
10041400
10061902
c2000978
bf8c007f
10040600
c2008975
bf8c007f
08180401
c8080b00
c8090b01
c200892f
bf8c007f
10040401
c200892c
bf8c007f
0a040401
c200892e
bf8c007f
d00c0002
02000302
7e1a0201
d2000002
000a1b02
d2060802
02010102
10040502
10181902
d2820003
04300103
c8300000
c8310001
10181904
c2008930
bf8c007f
101a1201
1018190d
101a1800
c2008974
bf8c007f
081a1a01
101a1b02
d282000c
0434010c
5e06070c
c8300200
c8310201
10001906
c2008932
bf8c007f
10021601
10000101
10020000
c2008976
bf8c007f
08020201
10020302
d2820000
04040100
5e001100
f8001c0f
00030003
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL CONST[0..51]
DCL TEMP[0..8], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[12]
 10: DP4 TEMP[5].x, TEMP[0], CONST[6]
 11: MOV TEMP[2].z, TEMP[5].xxxx
 12: DP4 TEMP[0].x, TEMP[0], CONST[7]
 13: MOV TEMP[2].w, TEMP[0].xxxx
 14: MOV TEMP[1].w, TEMP[4].xxxx
 15: MOV TEMP[4].xy, IN[1].xyxx
 16: MUL TEMP[6], IN[2].xyxx, CONST[0].yyxx
 17: MAD TEMP[7], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 18: MOV TEMP[8], TEMP[2]
 19: MAD TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
 20: MOV TEMP[2].z, TEMP[5].xxxx
 21: MOV TEMP[2].y, -TEMP[3].xxxx
 22: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[0].xxxx, TEMP[2].xyyy
 23: MOV OUT[3], TEMP[4]
 24: MOV OUT[5], TEMP[6]
 25: MOV OUT[0], TEMP[2]
 26: MOV OUT[4], TEMP[1]
 27: MOV OUT[2], TEMP[8]
 28: MOV_SAT OUT[1], TEMP[7]
 29: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 764)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 776)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 792)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 800)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 804)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 808)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 812)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 816)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 820)
  %49 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0
  %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %5)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = extractelement <4 x float> %51, i32 1
  %54 = extractelement <4 x float> %51, i32 2
  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
  %62 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %5)
  %63 = extractelement <4 x float> %62, i32 0
  %64 = extractelement <4 x float> %62, i32 1
  %65 = fmul float %52, %12
  %66 = fadd float %65, %11
  %67 = fmul float %53, %12
  %68 = fadd float %67, %11
  %69 = fmul float %54, %12
  %70 = fadd float %69, %11
  %71 = fmul float %52, %11
  %72 = fadd float %71, %12
  %73 = fmul float %66, %35
  %74 = fmul float %68, %36
  %75 = fadd float %73, %74
  %76 = fmul float %70, %37
  %77 = fadd float %75, %76
  %78 = fmul float %72, %38
  %79 = fadd float %77, %78
  %80 = fmul float %66, %39
  %81 = fmul float %68, %40
  %82 = fadd float %80, %81
  %83 = fmul float %70, %41
  %84 = fadd float %82, %83
  %85 = fmul float %72, %42
  %86 = fadd float %84, %85
  %87 = fmul float %66, %43
  %88 = fmul float %68, %44
  %89 = fadd float %87, %88
  %90 = fmul float %70, %45
  %91 = fadd float %89, %90
  %92 = fmul float %72, %46
  %93 = fadd float %91, %92
  %94 = fmul float %66, %14
  %95 = fmul float %68, %15
  %96 = fadd float %94, %95
  %97 = fmul float %70, %16
  %98 = fadd float %96, %97
  %99 = fmul float %72, %17
  %100 = fadd float %98, %99
  %101 = fmul float %66, %18
  %102 = fmul float %68, %19
  %103 = fadd float %101, %102
  %104 = fmul float %70, %20
  %105 = fadd float %103, %104
  %106 = fmul float %72, %21
  %107 = fadd float %105, %106
  %108 = fmul float %66, %30
  %109 = fmul float %68, %31
  %110 = fadd float %108, %109
  %111 = fmul float %70, %32
  %112 = fadd float %110, %111
  %113 = fmul float %72, %33
  %114 = fadd float %112, %113
  %115 = fmul float %66, %22
  %116 = fmul float %68, %23
  %117 = fadd float %115, %116
  %118 = fmul float %70, %24
  %119 = fadd float %117, %118
  %120 = fmul float %72, %25
  %121 = fadd float %119, %120
  %122 = fmul float %66, %26
  %123 = fmul float %68, %27
  %124 = fadd float %122, %123
  %125 = fmul float %70, %28
  %126 = fadd float %124, %125
  %127 = fmul float %72, %29
  %128 = fadd float %126, %127
  %129 = fmul float %63, %12
  %130 = fmul float %64, %12
  %131 = fmul float %63, %11
  %132 = fmul float %63, %11
  %133 = fmul float %34, %11
  %134 = fadd float %133, %12
  %135 = fmul float %34, %11
  %136 = fadd float %135, %12
  %137 = fmul float %34, %11
  %138 = fadd float %137, %12
  %139 = fmul float %34, %12
  %140 = fadd float %139, %11
  %141 = fsub float -0.000000e+00, %128
  %142 = fmul float %121, %13
  %143 = fadd float %142, %141
  %144 = fsub float -0.000000e+00, %107
  %145 = fmul float %47, %128
  %146 = fadd float %145, %100
  %147 = fmul float %48, %128
  %148 = fadd float %147, %144
  %149 = call float @llvm.AMDIL.clamp.(float %134, float 0.000000e+00, float 1.000000e+00)
  %150 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
  %151 = call float @llvm.AMDIL.clamp.(float %138, float 0.000000e+00, float 1.000000e+00)
  %152 = call float @llvm.AMDIL.clamp.(float %140, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %149, float %150, float %151, float %152)
  %153 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %154 = load <16 x i8> addrspace(2)* %153, !tbaa !0
  %155 = call float @llvm.SI.load.const(<16 x i8> %154, i32 0)
  %156 = fmul float %155, %100
  %157 = call float @llvm.SI.load.const(<16 x i8> %154, i32 4)
  %158 = fmul float %157, %107
  %159 = fadd float %156, %158
  %160 = call float @llvm.SI.load.const(<16 x i8> %154, i32 8)
  %161 = fmul float %160, %121
  %162 = fadd float %159, %161
  %163 = call float @llvm.SI.load.const(<16 x i8> %154, i32 12)
  %164 = fmul float %163, %128
  %165 = fadd float %162, %164
  %166 = call float @llvm.SI.load.const(<16 x i8> %154, i32 16)
  %167 = fmul float %166, %100
  %168 = call float @llvm.SI.load.const(<16 x i8> %154, i32 20)
  %169 = fmul float %168, %107
  %170 = fadd float %167, %169
  %171 = call float @llvm.SI.load.const(<16 x i8> %154, i32 24)
  %172 = fmul float %171, %121
  %173 = fadd float %170, %172
  %174 = call float @llvm.SI.load.const(<16 x i8> %154, i32 28)
  %175 = fmul float %174, %128
  %176 = fadd float %173, %175
  %177 = call float @llvm.SI.load.const(<16 x i8> %154, i32 32)
  %178 = fmul float %177, %100
  %179 = call float @llvm.SI.load.const(<16 x i8> %154, i32 36)
  %180 = fmul float %179, %107
  %181 = fadd float %178, %180
  %182 = call float @llvm.SI.load.const(<16 x i8> %154, i32 40)
  %183 = fmul float %182, %121
  %184 = fadd float %181, %183
  %185 = call float @llvm.SI.load.const(<16 x i8> %154, i32 44)
  %186 = fmul float %185, %128
  %187 = fadd float %184, %186
  %188 = call float @llvm.SI.load.const(<16 x i8> %154, i32 48)
  %189 = fmul float %188, %100
  %190 = call float @llvm.SI.load.const(<16 x i8> %154, i32 52)
  %191 = fmul float %190, %107
  %192 = fadd float %189, %191
  %193 = call float @llvm.SI.load.const(<16 x i8> %154, i32 56)
  %194 = fmul float %193, %121
  %195 = fadd float %192, %194
  %196 = call float @llvm.SI.load.const(<16 x i8> %154, i32 60)
  %197 = fmul float %196, %128
  %198 = fadd float %195, %197
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %165, float %176, float %187, float %198)
  %199 = call float @llvm.SI.load.const(<16 x i8> %154, i32 64)
  %200 = fmul float %199, %100
  %201 = call float @llvm.SI.load.const(<16 x i8> %154, i32 68)
  %202 = fmul float %201, %107
  %203 = fadd float %200, %202
  %204 = call float @llvm.SI.load.const(<16 x i8> %154, i32 72)
  %205 = fmul float %204, %121
  %206 = fadd float %203, %205
  %207 = call float @llvm.SI.load.const(<16 x i8> %154, i32 76)
  %208 = fmul float %207, %128
  %209 = fadd float %206, %208
  %210 = call float @llvm.SI.load.const(<16 x i8> %154, i32 80)
  %211 = fmul float %210, %100
  %212 = call float @llvm.SI.load.const(<16 x i8> %154, i32 84)
  %213 = fmul float %212, %107
  %214 = fadd float %211, %213
  %215 = call float @llvm.SI.load.const(<16 x i8> %154, i32 88)
  %216 = fmul float %215, %121
  %217 = fadd float %214, %216
  %218 = call float @llvm.SI.load.const(<16 x i8> %154, i32 92)
  %219 = fmul float %218, %128
  %220 = fadd float %217, %219
  %221 = call float @llvm.SI.load.const(<16 x i8> %154, i32 96)
  %222 = fmul float %221, %100
  %223 = call float @llvm.SI.load.const(<16 x i8> %154, i32 100)
  %224 = fmul float %223, %107
  %225 = fadd float %222, %224
  %226 = call float @llvm.SI.load.const(<16 x i8> %154, i32 104)
  %227 = fmul float %226, %121
  %228 = fadd float %225, %227
  %229 = call float @llvm.SI.load.const(<16 x i8> %154, i32 108)
  %230 = fmul float %229, %128
  %231 = fadd float %228, %230
  %232 = call float @llvm.SI.load.const(<16 x i8> %154, i32 112)
  %233 = fmul float %232, %100
  %234 = call float @llvm.SI.load.const(<16 x i8> %154, i32 116)
  %235 = fmul float %234, %107
  %236 = fadd float %233, %235
  %237 = call float @llvm.SI.load.const(<16 x i8> %154, i32 120)
  %238 = fmul float %237, %121
  %239 = fadd float %236, %238
  %240 = call float @llvm.SI.load.const(<16 x i8> %154, i32 124)
  %241 = fmul float %240, %128
  %242 = fadd float %239, %241
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %209, float %220, float %231, float %242)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %58, float %59, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %79, float %86, float %93, float %114)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %129, float %130, float %131, float %132)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %146, float %148, float %143, float %128)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 191
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR4, %VGPR1, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%49](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6, %SGPR3, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 19
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 23
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%153](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 27
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 9
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 11
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 29
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 28
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 30
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 31
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 25
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 24
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 26
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 27
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 21
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 20
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 22
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 23
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 17
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 16
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 18
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 19
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%55](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13<kill>, %VGPR13, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 51
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 201
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 200
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 202
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 203
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 198
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 199
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 194
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 195
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR2<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 8; mem:LD16[%60](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	EXP 15, 35, 0, 0, 0, %VGPR4<kill>, %VGPR2<kill>, %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 204
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 205
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840100
bf8c007f
c20209bf
c2018900
bf8c007f
7e060203
c2010901
bf8c007f
7e020202
d2820002
040e0204
d2060802
02010102
d2820004
04060604
d2060804
02010104
f800020f
02040404
c0860700
bf8c000f
e00c2000
80030600
bf8c0770
d2820002
040c0506
d2820004
040c0507
c2020911
bf8c007f
100a0804
c2020910
bf8c007f
d282000a
04140902
d2820005
040c0508
c2020912
bf8c007f
d2820003
04280905
d2820006
04040706
c2020913
bf8c007f
d2820001
040c0906
c2020915
bf8c007f
10060804
c2020914
bf8c007f
d2820003
040c0902
c2020916
bf8c007f
d2820003
040c0905
c2020917
bf8c007f
d2820003
040c0906
c0860104
bf8c007f
c2000d0d
bf8c007f
100e0600
c2000d0c
bf8c007f
d2820008
041e0200
c2000919
bf8c007f
100e0800
c2000918
bf8c007f
d2820007
041c0102
c200091a
bf8c007f
d2820007
041c0105
c200091b
bf8c007f
d2820007
041c0106
c2000d0e
bf8c007f
d2820009
04220e00
c200091d
bf8c007f
10100800
c200091c
bf8c007f
d2820008
04200102
c200091e
bf8c007f
d2820008
04200105
c200091f
bf8c007f
d2820008
04200106
c2000d0f
bf8c007f
d2820009
04261000
c2000d09
bf8c007f
10140600
c2000d08
bf8c007f
d282000a
042a0200
c2000d0a
bf8c007f
d282000a
042a0e00
c2000d0b
bf8c007f
d282000a
042a1000
c2000d05
bf8c007f
10160600
c2000d04
bf8c007f
d282000b
042e0200
c2000d06
bf8c007f
d282000b
042e0e00
c2000d07
bf8c007f
d282000b
042e1000
c2000d01
bf8c007f
10180600
c2000d00
bf8c007f
d282000c
04320200
c2000d02
bf8c007f
d282000c
04320e00
c2000d03
bf8c007f
d282000c
04321000
f80000ef
090a0b0c
c2000d1d
bf8c000f
10120600
c2000d1c
bf8c007f
d2820009
04260200
c2000d1e
bf8c007f
d2820009
04260e00
c2000d1f
bf8c007f
d2820009
04261000
c2000d19
bf8c007f
10140600
c2000d18
bf8c007f
d282000a
042a0200
c2000d1a
bf8c007f
d282000a
042a0e00
c2000d1b
bf8c007f
d282000a
042a1000
c2000d15
bf8c007f
10160600
c2000d14
bf8c007f
d282000b
042e0200
c2000d16
bf8c007f
d282000b
042e0e00
c2000d17
bf8c007f
d282000b
042e1000
c2000d11
bf8c007f
10180600
c2000d10
bf8c007f
d282000c
04320200
c2000d12
bf8c007f
d282000c
04320e00
c2000d13
bf8c007f
d282000c
04321000
f80000ff
090a0b0c
c0860704
bf8c000f
e00c2000
80030900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c2000931
bf8c000f
10120800
c2000930
bf8c007f
d2820009
04240102
c2000932
bf8c007f
d2820009
04240105
c2000933
bf8c007f
d2820009
04240106
c20009c9
bf8c007f
10140800
c20009c8
bf8c007f
d282000a
04280102
c20009ca
bf8c007f
d282000a
04280105
c20009cb
bf8c007f
d282000a
04280106
c20009c5
bf8c007f
10160800
c20009c4
bf8c007f
d282000b
042c0102
c20009c6
bf8c007f
d282000b
042c0105
c20009c7
bf8c007f
d282000b
042c0106
c20009c1
bf8c007f
10080800
c20009c0
bf8c007f
d2820002
04100102
c20009c2
bf8c007f
d2820002
04080105
c20009c3
bf8c007f
d2820002
04080106
f800022f
090a0b02
c0820708
bf8c000f
e00c2000
80010900
bf8c0770
10001203
10041402
10081202
f800023f
00000204
c20009cc
bf8c000f
d2820000
04061000
c2000902
bf8c007f
10020e00
08021101
c20009cd
bf8c007f
10041000
08040702
f80008cf
08010200
bf810000
FRAG
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL CONST[0..29]
DCL TEMP[0], LOCAL
DCL TEMP[1], ARRAY(1), LOCAL
IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
  0: MUL TEMP[0].x, IN[0].xxxx, CONST[29].wwww
  1: MOV TEMP[0].w, TEMP[0].xxxx
  2: MOV TEMP[0].xyz, IMM[0].xxxx
  3: MOV TEMP[1], TEMP[0]
  4: MOV OUT[0], TEMP[1]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %23 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %24 = fmul float %23, %22
  %25 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
  %26 = bitcast i32 %25 to float
  %27 = call i32 @llvm.SI.packf16(float 0.000000e+00, float %24)
  %28 = bitcast i32 %27 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %26, float %28, float %26, float %28)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 119
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 0.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8080000
c8090001
c0800100
bf8c007f
c2000177
bf8c007f
10000400
5e000080
d25e0001
02010080
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL CONST[0..8]
DCL TEMP[0..5], LOCAL
  0: DP4 TEMP[0].x, IN[0], CONST[4]
  1: DP4 TEMP[1].x, IN[0], CONST[5]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: DP4 TEMP[2].x, IN[0], CONST[7]
  4: MOV TEMP[3].w, TEMP[2].xxxx
  5: DP4 TEMP[4].x, IN[0], CONST[6]
  6: MOV TEMP[3].z, TEMP[4].xxxx
  7: MOV TEMP[0].zw, TEMP[3].wwzw
  8: MOV TEMP[3].x, TEMP[4].xxxx
  9: MOV TEMP[5], TEMP[0]
 10: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[2].xxxx
 11: MOV TEMP[0].z, TEMP[4].xxxx
 12: MOV TEMP[0].y, -TEMP[1].xxxx
 13: MAD TEMP[0].xy, CONST[8].xyyy, TEMP[2].xxxx, TEMP[0].xyyy
 14: MOV OUT[2], TEMP[3]
 15: MOV OUT[0], TEMP[0]
 16: MOV OUT[1], TEMP[5]
 17: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
  %30 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
  %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %5)
  %33 = extractelement <4 x float> %32, i32 0
  %34 = extractelement <4 x float> %32, i32 1
  %35 = extractelement <4 x float> %32, i32 2
  %36 = extractelement <4 x float> %32, i32 3
  %37 = fmul float %33, %12
  %38 = fmul float %34, %13
  %39 = fadd float %37, %38
  %40 = fmul float %35, %14
  %41 = fadd float %39, %40
  %42 = fmul float %36, %15
  %43 = fadd float %41, %42
  %44 = fmul float %33, %16
  %45 = fmul float %34, %17
  %46 = fadd float %44, %45
  %47 = fmul float %35, %18
  %48 = fadd float %46, %47
  %49 = fmul float %36, %19
  %50 = fadd float %48, %49
  %51 = fmul float %33, %24
  %52 = fmul float %34, %25
  %53 = fadd float %51, %52
  %54 = fmul float %35, %26
  %55 = fadd float %53, %54
  %56 = fmul float %36, %27
  %57 = fadd float %55, %56
  %58 = fmul float %33, %20
  %59 = fmul float %34, %21
  %60 = fadd float %58, %59
  %61 = fmul float %35, %22
  %62 = fadd float %60, %61
  %63 = fmul float %36, %23
  %64 = fadd float %62, %63
  %65 = fsub float -0.000000e+00, %57
  %66 = fmul float %64, %11
  %67 = fadd float %66, %65
  %68 = fsub float -0.000000e+00, %50
  %69 = fmul float %28, %57
  %70 = fadd float %69, %43
  %71 = fmul float %29, %57
  %72 = fadd float %71, %68
  %73 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %74 = load <16 x i8> addrspace(2)* %73, !tbaa !0
  %75 = call float @llvm.SI.load.const(<16 x i8> %74, i32 0)
  %76 = fmul float %75, %43
  %77 = call float @llvm.SI.load.const(<16 x i8> %74, i32 4)
  %78 = fmul float %77, %50
  %79 = fadd float %76, %78
  %80 = call float @llvm.SI.load.const(<16 x i8> %74, i32 8)
  %81 = fmul float %80, %64
  %82 = fadd float %79, %81
  %83 = call float @llvm.SI.load.const(<16 x i8> %74, i32 12)
  %84 = fmul float %83, %57
  %85 = fadd float %82, %84
  %86 = call float @llvm.SI.load.const(<16 x i8> %74, i32 16)
  %87 = fmul float %86, %43
  %88 = call float @llvm.SI.load.const(<16 x i8> %74, i32 20)
  %89 = fmul float %88, %50
  %90 = fadd float %87, %89
  %91 = call float @llvm.SI.load.const(<16 x i8> %74, i32 24)
  %92 = fmul float %91, %64
  %93 = fadd float %90, %92
  %94 = call float @llvm.SI.load.const(<16 x i8> %74, i32 28)
  %95 = fmul float %94, %57
  %96 = fadd float %93, %95
  %97 = call float @llvm.SI.load.const(<16 x i8> %74, i32 32)
  %98 = fmul float %97, %43
  %99 = call float @llvm.SI.load.const(<16 x i8> %74, i32 36)
  %100 = fmul float %99, %50
  %101 = fadd float %98, %100
  %102 = call float @llvm.SI.load.const(<16 x i8> %74, i32 40)
  %103 = fmul float %102, %64
  %104 = fadd float %101, %103
  %105 = call float @llvm.SI.load.const(<16 x i8> %74, i32 44)
  %106 = fmul float %105, %57
  %107 = fadd float %104, %106
  %108 = call float @llvm.SI.load.const(<16 x i8> %74, i32 48)
  %109 = fmul float %108, %43
  %110 = call float @llvm.SI.load.const(<16 x i8> %74, i32 52)
  %111 = fmul float %110, %50
  %112 = fadd float %109, %111
  %113 = call float @llvm.SI.load.const(<16 x i8> %74, i32 56)
  %114 = fmul float %113, %64
  %115 = fadd float %112, %114
  %116 = call float @llvm.SI.load.const(<16 x i8> %74, i32 60)
  %117 = fmul float %116, %57
  %118 = fadd float %115, %117
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %85, float %96, float %107, float %118)
  %119 = call float @llvm.SI.load.const(<16 x i8> %74, i32 64)
  %120 = fmul float %119, %43
  %121 = call float @llvm.SI.load.const(<16 x i8> %74, i32 68)
  %122 = fmul float %121, %50
  %123 = fadd float %120, %122
  %124 = call float @llvm.SI.load.const(<16 x i8> %74, i32 72)
  %125 = fmul float %124, %64
  %126 = fadd float %123, %125
  %127 = call float @llvm.SI.load.const(<16 x i8> %74, i32 76)
  %128 = fmul float %127, %57
  %129 = fadd float %126, %128
  %130 = call float @llvm.SI.load.const(<16 x i8> %74, i32 80)
  %131 = fmul float %130, %43
  %132 = call float @llvm.SI.load.const(<16 x i8> %74, i32 84)
  %133 = fmul float %132, %50
  %134 = fadd float %131, %133
  %135 = call float @llvm.SI.load.const(<16 x i8> %74, i32 88)
  %136 = fmul float %135, %64
  %137 = fadd float %134, %136
  %138 = call float @llvm.SI.load.const(<16 x i8> %74, i32 92)
  %139 = fmul float %138, %57
  %140 = fadd float %137, %139
  %141 = call float @llvm.SI.load.const(<16 x i8> %74, i32 96)
  %142 = fmul float %141, %43
  %143 = call float @llvm.SI.load.const(<16 x i8> %74, i32 100)
  %144 = fmul float %143, %50
  %145 = fadd float %142, %144
  %146 = call float @llvm.SI.load.const(<16 x i8> %74, i32 104)
  %147 = fmul float %146, %64
  %148 = fadd float %145, %147
  %149 = call float @llvm.SI.load.const(<16 x i8> %74, i32 108)
  %150 = fmul float %149, %57
  %151 = fadd float %148, %150
  %152 = call float @llvm.SI.load.const(<16 x i8> %74, i32 112)
  %153 = fmul float %152, %43
  %154 = call float @llvm.SI.load.const(<16 x i8> %74, i32 116)
  %155 = fmul float %154, %50
  %156 = fadd float %153, %155
  %157 = call float @llvm.SI.load.const(<16 x i8> %74, i32 120)
  %158 = fmul float %157, %64
  %159 = fadd float %156, %158
  %160 = call float @llvm.SI.load.const(<16 x i8> %74, i32 124)
  %161 = fmul float %160, %57
  %162 = fadd float %159, %161
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %129, float %140, float %151, float %162)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %64, float 0.000000e+00, float %64, float %57)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %70, float %72, float %67, float %57)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%30](tbaa=!"const")
	S_WAITCNT 127
	%VGPR3_VGPR4_VGPR5_VGPR6<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 17
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 16
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 18
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR5, %SGPR2<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 19
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 21
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 20
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 22
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR5, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 23
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%73](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR8<kill>, %VGPR0, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 25
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 24
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR3, %SGPR8<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 26
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 27
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR8<kill>, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 29
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 28
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR3, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 30
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 31
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-use,kill>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR8<kill>, %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR8<kill>, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR8<kill>, %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR8<kill>, %VGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR8<kill>, %VGPR0, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR8<kill>, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29
	S_WAITCNT 15
	%VGPR4<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 30
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR2, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 31
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR8<kill>, %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR8<kill>, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR8<kill>, %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR8<kill>, %VGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR8<kill>, %VGPR0, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR8<kill>, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 19
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR2, %VGPR4<kill>, %VGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 32
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 2
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7<kill>, 33
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR4<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR1<kill>, %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0820700
bf8c007f
e00c2000
80010300
c0820100
bf8c0070
c2010511
bf8c007f
10000802
c2010510
bf8c007f
d2820000
04000503
c2010512
bf8c007f
d2820000
04000505
c2010513
bf8c007f
d2820000
04000506
c2010515
bf8c007f
10020802
c2010514
bf8c007f
d2820001
04040503
c2010516
bf8c007f
d2820001
04040505
c2010517
bf8c007f
d2820001
04040506
c0800104
bf8c007f
c204010d
bf8c007f
10040208
c204010c
bf8c007f
d2820007
040a0008
c2040519
bf8c007f
10040808
c2040518
bf8c007f
d2820002
04081103
c204051a
bf8c007f
d2820002
04081105
c204051b
bf8c007f
d2820002
04081106
c204010e
bf8c007f
d2820007
041e0408
c204051d
bf8c007f
10100808
c204051c
bf8c007f
d2820008
04201103
c204051e
bf8c007f
d2820008
04201105
c204051f
bf8c007f
d2820003
04201106
c204010f
bf8c007f
d2820004
041e0608
c2040109
bf8c007f
100a0208
c2040108
bf8c007f
d2820005
04160008
c204010a
bf8c007f
d2820005
04160408
c204010b
bf8c007f
d2820005
04160608
c2040105
bf8c007f
100c0208
c2040104
bf8c007f
d2820006
041a0008
c2040106
bf8c007f
d2820006
041a0408
c2040107
bf8c007f
d2820006
041a0608
c2040101
bf8c007f
100e0208
c2040100
bf8c007f
d2820007
041e0008
c2040102
bf8c007f
d2820007
041e0408
c2040103
bf8c007f
d2820007
041e0608
f80000ef
04050607
c204011d
bf8c000f
10080208
c204011c
bf8c007f
d2820004
04120008
c204011e
bf8c007f
d2820004
04120408
c204011f
bf8c007f
d2820004
04120608
c2040119
bf8c007f
100a0208
c2040118
bf8c007f
d2820005
04160008
c204011a
bf8c007f
d2820005
04160408
c204011b
bf8c007f
d2820005
04160608
c2040115
bf8c007f
100c0208
c2040114
bf8c007f
d2820006
041a0008
c2040116
bf8c007f
d2820006
041a0408
c2040117
bf8c007f
d2820006
041a0608
c2040111
bf8c007f
100e0208
c2040110
bf8c007f
d2820007
041e0008
c2040112
bf8c007f
d2820007
041e0408
c2000113
bf8c007f
d2820007
041e0600
f80000ff
04050607
bf8c070f
7e080280
f800020f
03020402
c2000520
bf8c000f
d2820000
04020600
c2000502
bf8c007f
10040400
08040702
c2000521
bf8c007f
10080600
08020304
f80008cf
03020100
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE
DCL IN[4], GENERIC[22], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..30]
DCL TEMP[0..2], LOCAL
DCL TEMP[3], ARRAY(1), LOCAL
IMM[0] FLT32 {    2.0000,    -1.0000,     1.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[2].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[2], 2D
  2: MOV TEMP[1].xy, IN[1].xyyy
  3: TEX TEMP[1].xyz, TEMP[1], SAMP[0], 2D
  4: MOV TEMP[2].xy, IN[4].xyyy
  5: TEX TEMP[2].xyz, TEMP[2], SAMP[1], 2D
  6: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[8].xyzz
  7: MAD TEMP[0].xyz, IMM[0].xxxx, TEMP[0].xyzz, IMM[0].yyyy
  8: MAD TEMP[0].xyz, CONST[8].wwww, TEMP[0].xyzz, IMM[0].zzzz
  9: MUL TEMP[0].xyz, TEMP[1].xyzz, TEMP[0].xyzz
 10: MUL TEMP[0].xyz, TEMP[0].xyzz, IN[0].xyzz
 11: MUL TEMP[1].xyz, TEMP[2].xyzz, CONST[12].xyzz
 12: MAD TEMP[2].x, IN[3].wwww, CONST[11].wwww, -CONST[11].xxxx
 13: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[1].xyzz
 14: MIN TEMP[2].x, TEMP[2].xxxx, CONST[11].zzzz
 15: MOV_SAT TEMP[2].x, TEMP[2].xxxx
 16: MAD TEMP[0].xyz, TEMP[1].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 17: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
 18: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
 19: MAD TEMP[1].xyz, TEMP[1].xyzz, CONST[30].xxxx, TEMP[0].xyzz
 20: MUL TEMP[0].x, IN[3].wwww, CONST[29].wwww
 21: MOV TEMP[1].w, TEMP[0].xxxx
 22: MOV TEMP[3], TEMP[1]
 23: MOV OUT[0], TEMP[3]
 24: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 136)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 140)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 188)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %42 = load <32 x i8> addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %46 = load <32 x i8> addrspace(2)* %45, !tbaa !0
  %47 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %50 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %51 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %52 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %53 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %54 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %55 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %56 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
  %57 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %6)
  %58 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %6)
  %59 = bitcast float %54 to i32
  %60 = bitcast float %55 to i32
  %61 = insertelement <2 x i32> undef, i32 %59, i32 0
  %62 = insertelement <2 x i32> %61, i32 %60, i32 1
  %63 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %62, <32 x i8> %46, <16 x i8> %48, i32 2)
  %64 = extractelement <4 x float> %63, i32 0
  %65 = extractelement <4 x float> %63, i32 1
  %66 = extractelement <4 x float> %63, i32 2
  %67 = bitcast float %52 to i32
  %68 = bitcast float %53 to i32
  %69 = insertelement <2 x i32> undef, i32 %67, i32 0
  %70 = insertelement <2 x i32> %69, i32 %68, i32 1
  %71 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %70, <32 x i8> %38, <16 x i8> %40, i32 2)
  %72 = extractelement <4 x float> %71, i32 0
  %73 = extractelement <4 x float> %71, i32 1
  %74 = extractelement <4 x float> %71, i32 2
  %75 = bitcast float %57 to i32
  %76 = bitcast float %58 to i32
  %77 = insertelement <2 x i32> undef, i32 %75, i32 0
  %78 = insertelement <2 x i32> %77, i32 %76, i32 1
  %79 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %78, <32 x i8> %42, <16 x i8> %44, i32 2)
  %80 = extractelement <4 x float> %79, i32 0
  %81 = extractelement <4 x float> %79, i32 1
  %82 = extractelement <4 x float> %79, i32 2
  %83 = fmul float %64, %22
  %84 = fmul float %65, %23
  %85 = fmul float %66, %24
  %86 = fmul float 2.000000e+00, %83
  %87 = fadd float %86, -1.000000e+00
  %88 = fmul float 2.000000e+00, %84
  %89 = fadd float %88, -1.000000e+00
  %90 = fmul float 2.000000e+00, %85
  %91 = fadd float %90, -1.000000e+00
  %92 = fmul float %25, %87
  %93 = fadd float %92, 1.000000e+00
  %94 = fmul float %25, %89
  %95 = fadd float %94, 1.000000e+00
  %96 = fmul float %25, %91
  %97 = fadd float %96, 1.000000e+00
  %98 = fmul float %72, %93
  %99 = fmul float %73, %95
  %100 = fmul float %74, %97
  %101 = fmul float %98, %49
  %102 = fmul float %99, %50
  %103 = fmul float %100, %51
  %104 = fmul float %80, %29
  %105 = fmul float %81, %30
  %106 = fmul float %82, %31
  %107 = fsub float -0.000000e+00, %26
  %108 = fmul float %56, %28
  %109 = fadd float %108, %107
  %110 = fmul float %101, %104
  %111 = fmul float %102, %105
  %112 = fmul float %103, %106
  %113 = fcmp uge float %109, %27
  %114 = select i1 %113, float %27, float %109
  %115 = call float @llvm.AMDIL.clamp.(float %114, float 0.000000e+00, float 1.000000e+00)
  %116 = fsub float -0.000000e+00, %36
  %117 = fmul float %110, %116
  %118 = fadd float %117, %32
  %119 = fsub float -0.000000e+00, %36
  %120 = fmul float %111, %119
  %121 = fadd float %120, %33
  %122 = fsub float -0.000000e+00, %36
  %123 = fmul float %112, %122
  %124 = fadd float %123, %34
  %125 = fmul float %115, %115
  %126 = fmul float %118, %125
  %127 = fmul float %121, %125
  %128 = fmul float %124, %125
  %129 = fmul float %110, %36
  %130 = fadd float %129, %126
  %131 = fmul float %111, %36
  %132 = fadd float %131, %127
  %133 = fmul float %112, %36
  %134 = fadd float %133, %128
  %135 = fmul float %56, %35
  %136 = call i32 @llvm.SI.packf16(float %130, float %132)
  %137 = bitcast i32 %136 to float
  %138 = call i32 @llvm.SI.packf16(float %134, float %135)
  %139 = bitcast i32 %138 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %137, float %139, float %137, float %139)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%47](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%45](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0, %VGPR5, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR7<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 35
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0, %VGPR7<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%39](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%37](tbaa=!"const")
	S_WAITCNT 127
	%VGPR7_VGPR8_VGPR9<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR10<def> = V_MUL_F32_e32 %VGPR8, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR2, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<tied0>, %VGPR3, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR2, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<tied0>, %VGPR3, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%43](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%41](tbaa=!"const")
	S_WAITCNT 127
	%VGPR10_VGPR11_VGPR12<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR10_VGPR11<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 112
	%VGPR2<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 120
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR1, %VGPR13, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 117
	S_WAITCNT 127
	%VGPR14<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 3, %M0<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR15<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR13<kill>, %SGPR1, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR2, %VGPR4, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR4, %SGPR2<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %SGPR0, %VGPR14<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR7, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR10, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %SGPR1, %VGPR14, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 116
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR14<kill>, %SGPR1, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR14<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR2, %VGPR6, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR9, %VGPR4<kill>, %EXEC<imp-use>, %VGPR7_VGPR8_VGPR9<imp-use,kill>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR12, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR1, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 118
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR1<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 119
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR13<kill>, %VGPR0<kill>, %VGPR13, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140900
c8150901
c8100800
c8110801
c0840308
c0c60510
bf8c007f
f0800700
00430404
c0840100
bf8c0070
c2000921
bf8c007f
100e0a00
d2820007
041c0105
060e0ef3
c2000923
bf8c007f
d282000a
03ca0e00
c8200500
c8210501
c81c0400
c81d0401
c0860300
c0c80500
bf8c007f
f0800700
00640707
bf8c0770
10141508
c82c0100
c82d0101
101a170a
c82c1102
c82d1103
c8281002
c8291003
c0860304
c0c80508
bf8c007f
f0800700
00640a0a
c2008931
bf8c0070
10041601
101a050d
c2008978
bf8c007f
10041a01
c2010975
bf8c007f
081c0402
c8080f00
c8090f01
c201092f
bf8c007f
10060402
c201092c
bf8c007f
0a060602
c201092e
bf8c007f
d00c0004
02000503
7e1e0202
d2000003
00121f03
d2060803
02010103
10060703
101c070e
d282000d
0438030d
c2010920
bf8c007f
101c0802
d282000e
04380504
061c1cf3
d282000e
03ca1c00
101c1d07
c83c0000
c83d0001
101c1f0e
c2010930
bf8c007f
101e1402
101c1f0e
101e1c01
c2010974
bf8c007f
081e1e02
101e070f
d282000e
043c030e
5e1a1b0e
c2010922
bf8c007f
101c0c02
d2820004
04380506
060808f3
d2820004
03ca0800
10080909
c8140200
c8150201
10000b04
c2000932
bf8c007f
10021800
10000300
10020001
c2000976
bf8c007f
08020200
10020701
d2820000
04040300
c2000977
bf8c007f
10020400
5e000300
f8001c0f
000d000d
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL CONST[0..55]
DCL TEMP[0..9], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[52]
  2: DP4 TEMP[2].x, TEMP[0], CONST[53]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[54]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[6]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: DP4 TEMP[5].x, TEMP[0], CONST[7]
 12: MOV TEMP[2].w, TEMP[5].xxxx
 13: DP4 TEMP[6].x, TEMP[0], CONST[12]
 14: MUL TEMP[0].xy, IN[1].xyyy, CONST[48].xyyy
 15: ADD TEMP[7].x, TEMP[0].yyyy, TEMP[0].xxxx
 16: MUL TEMP[0].xy, IN[1].xyyy, CONST[49].xyyy
 17: ADD TEMP[7].x, TEMP[7].xxxx, CONST[48].wwww
 18: ADD TEMP[8].x, TEMP[0].yyyy, TEMP[0].xxxx
 19: ADD TEMP[8].x, TEMP[8].xxxx, CONST[49].wwww
 20: MOV TEMP[7].y, TEMP[8].xxxx
 21: MUL TEMP[0].xy, IN[1].xyyy, CONST[50].xyyy
 22: ADD TEMP[8].x, TEMP[0].yyyy, TEMP[0].xxxx
 23: MUL TEMP[0].xy, IN[1].xyyy, CONST[51].xyyy
 24: ADD TEMP[8].x, TEMP[8].xxxx, CONST[50].wwww
 25: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx
 26: ADD TEMP[0].x, TEMP[0].xxxx, CONST[51].wwww
 27: MOV TEMP[8].y, TEMP[0].xxxx
 28: MOV TEMP[1].w, TEMP[6].xxxx
 29: MOV TEMP[8].zw, CONST[0].xxxx
 30: MUL TEMP[0], IN[2].xyxx, CONST[0].yyxx
 31: MAD TEMP[6], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 32: MOV TEMP[9], TEMP[2]
 33: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[5].xxxx
 34: MOV TEMP[2].z, TEMP[4].xxxx
 35: MOV TEMP[2].y, -TEMP[3].xxxx
 36: MAD TEMP[2].xy, CONST[55].xyyy, TEMP[5].xxxx, TEMP[2].xyyy
 37: MOV OUT[3], TEMP[7]
 38: MOV OUT[4], TEMP[8]
 39: MOV OUT[6], TEMP[0]
 40: MOV OUT[0], TEMP[2]
 41: MOV OUT[5], TEMP[1]
 42: MOV OUT[2], TEMP[9]
 43: MOV_SAT OUT[1], TEMP[6]
 44: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 764)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 800)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 804)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 812)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 816)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 820)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 828)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 832)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 836)
  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 840)
  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 844)
  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 848)
  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 852)
  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 856)
  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 860)
  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 864)
  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 868)
  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 872)
  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 876)
  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 880)
  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 884)
  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
  %64 = extractelement <4 x float> %63, i32 0
  %65 = extractelement <4 x float> %63, i32 1
  %66 = extractelement <4 x float> %63, i32 2
  %67 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
  %69 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %5)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %73 = load <16 x i8> addrspace(2)* %72, !tbaa !0
  %74 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %73, i32 0, i32 %5)
  %75 = extractelement <4 x float> %74, i32 0
  %76 = extractelement <4 x float> %74, i32 1
  %77 = fmul float %64, %12
  %78 = fadd float %77, %11
  %79 = fmul float %65, %12
  %80 = fadd float %79, %11
  %81 = fmul float %66, %12
  %82 = fadd float %81, %11
  %83 = fmul float %64, %11
  %84 = fadd float %83, %12
  %85 = fmul float %78, %47
  %86 = fmul float %80, %48
  %87 = fadd float %85, %86
  %88 = fmul float %82, %49
  %89 = fadd float %87, %88
  %90 = fmul float %84, %50
  %91 = fadd float %89, %90
  %92 = fmul float %78, %51
  %93 = fmul float %80, %52
  %94 = fadd float %92, %93
  %95 = fmul float %82, %53
  %96 = fadd float %94, %95
  %97 = fmul float %84, %54
  %98 = fadd float %96, %97
  %99 = fmul float %78, %55
  %100 = fmul float %80, %56
  %101 = fadd float %99, %100
  %102 = fmul float %82, %57
  %103 = fadd float %101, %102
  %104 = fmul float %84, %58
  %105 = fadd float %103, %104
  %106 = fmul float %78, %14
  %107 = fmul float %80, %15
  %108 = fadd float %106, %107
  %109 = fmul float %82, %16
  %110 = fadd float %108, %109
  %111 = fmul float %84, %17
  %112 = fadd float %110, %111
  %113 = fmul float %78, %18
  %114 = fmul float %80, %19
  %115 = fadd float %113, %114
  %116 = fmul float %82, %20
  %117 = fadd float %115, %116
  %118 = fmul float %84, %21
  %119 = fadd float %117, %118
  %120 = fmul float %78, %22
  %121 = fmul float %80, %23
  %122 = fadd float %120, %121
  %123 = fmul float %82, %24
  %124 = fadd float %122, %123
  %125 = fmul float %84, %25
  %126 = fadd float %124, %125
  %127 = fmul float %78, %26
  %128 = fmul float %80, %27
  %129 = fadd float %127, %128
  %130 = fmul float %82, %28
  %131 = fadd float %129, %130
  %132 = fmul float %84, %29
  %133 = fadd float %131, %132
  %134 = fmul float %78, %30
  %135 = fmul float %80, %31
  %136 = fadd float %134, %135
  %137 = fmul float %82, %32
  %138 = fadd float %136, %137
  %139 = fmul float %84, %33
  %140 = fadd float %138, %139
  %141 = fmul float %70, %35
  %142 = fmul float %71, %36
  %143 = fadd float %142, %141
  %144 = fmul float %70, %38
  %145 = fmul float %71, %39
  %146 = fadd float %143, %37
  %147 = fadd float %145, %144
  %148 = fadd float %147, %40
  %149 = fmul float %70, %41
  %150 = fmul float %71, %42
  %151 = fadd float %150, %149
  %152 = fmul float %70, %44
  %153 = fmul float %71, %45
  %154 = fadd float %151, %43
  %155 = fadd float %153, %152
  %156 = fadd float %155, %46
  %157 = fmul float %75, %12
  %158 = fmul float %76, %12
  %159 = fmul float %75, %11
  %160 = fmul float %75, %11
  %161 = fmul float %34, %11
  %162 = fadd float %161, %12
  %163 = fmul float %34, %11
  %164 = fadd float %163, %12
  %165 = fmul float %34, %11
  %166 = fadd float %165, %12
  %167 = fmul float %34, %12
  %168 = fadd float %167, %11
  %169 = fsub float -0.000000e+00, %133
  %170 = fmul float %126, %13
  %171 = fadd float %170, %169
  %172 = fsub float -0.000000e+00, %119
  %173 = fmul float %59, %133
  %174 = fadd float %173, %112
  %175 = fmul float %60, %133
  %176 = fadd float %175, %172
  %177 = call float @llvm.AMDIL.clamp.(float %162, float 0.000000e+00, float 1.000000e+00)
  %178 = call float @llvm.AMDIL.clamp.(float %164, float 0.000000e+00, float 1.000000e+00)
  %179 = call float @llvm.AMDIL.clamp.(float %166, float 0.000000e+00, float 1.000000e+00)
  %180 = call float @llvm.AMDIL.clamp.(float %168, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %177, float %178, float %179, float %180)
  %181 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %182 = load <16 x i8> addrspace(2)* %181, !tbaa !0
  %183 = call float @llvm.SI.load.const(<16 x i8> %182, i32 0)
  %184 = fmul float %183, %112
  %185 = call float @llvm.SI.load.const(<16 x i8> %182, i32 4)
  %186 = fmul float %185, %119
  %187 = fadd float %184, %186
  %188 = call float @llvm.SI.load.const(<16 x i8> %182, i32 8)
  %189 = fmul float %188, %126
  %190 = fadd float %187, %189
  %191 = call float @llvm.SI.load.const(<16 x i8> %182, i32 12)
  %192 = fmul float %191, %133
  %193 = fadd float %190, %192
  %194 = call float @llvm.SI.load.const(<16 x i8> %182, i32 16)
  %195 = fmul float %194, %112
  %196 = call float @llvm.SI.load.const(<16 x i8> %182, i32 20)
  %197 = fmul float %196, %119
  %198 = fadd float %195, %197
  %199 = call float @llvm.SI.load.const(<16 x i8> %182, i32 24)
  %200 = fmul float %199, %126
  %201 = fadd float %198, %200
  %202 = call float @llvm.SI.load.const(<16 x i8> %182, i32 28)
  %203 = fmul float %202, %133
  %204 = fadd float %201, %203
  %205 = call float @llvm.SI.load.const(<16 x i8> %182, i32 32)
  %206 = fmul float %205, %112
  %207 = call float @llvm.SI.load.const(<16 x i8> %182, i32 36)
  %208 = fmul float %207, %119
  %209 = fadd float %206, %208
  %210 = call float @llvm.SI.load.const(<16 x i8> %182, i32 40)
  %211 = fmul float %210, %126
  %212 = fadd float %209, %211
  %213 = call float @llvm.SI.load.const(<16 x i8> %182, i32 44)
  %214 = fmul float %213, %133
  %215 = fadd float %212, %214
  %216 = call float @llvm.SI.load.const(<16 x i8> %182, i32 48)
  %217 = fmul float %216, %112
  %218 = call float @llvm.SI.load.const(<16 x i8> %182, i32 52)
  %219 = fmul float %218, %119
  %220 = fadd float %217, %219
  %221 = call float @llvm.SI.load.const(<16 x i8> %182, i32 56)
  %222 = fmul float %221, %126
  %223 = fadd float %220, %222
  %224 = call float @llvm.SI.load.const(<16 x i8> %182, i32 60)
  %225 = fmul float %224, %133
  %226 = fadd float %223, %225
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %193, float %204, float %215, float %226)
  %227 = call float @llvm.SI.load.const(<16 x i8> %182, i32 64)
  %228 = fmul float %227, %112
  %229 = call float @llvm.SI.load.const(<16 x i8> %182, i32 68)
  %230 = fmul float %229, %119
  %231 = fadd float %228, %230
  %232 = call float @llvm.SI.load.const(<16 x i8> %182, i32 72)
  %233 = fmul float %232, %126
  %234 = fadd float %231, %233
  %235 = call float @llvm.SI.load.const(<16 x i8> %182, i32 76)
  %236 = fmul float %235, %133
  %237 = fadd float %234, %236
  %238 = call float @llvm.SI.load.const(<16 x i8> %182, i32 80)
  %239 = fmul float %238, %112
  %240 = call float @llvm.SI.load.const(<16 x i8> %182, i32 84)
  %241 = fmul float %240, %119
  %242 = fadd float %239, %241
  %243 = call float @llvm.SI.load.const(<16 x i8> %182, i32 88)
  %244 = fmul float %243, %126
  %245 = fadd float %242, %244
  %246 = call float @llvm.SI.load.const(<16 x i8> %182, i32 92)
  %247 = fmul float %246, %133
  %248 = fadd float %245, %247
  %249 = call float @llvm.SI.load.const(<16 x i8> %182, i32 96)
  %250 = fmul float %249, %112
  %251 = call float @llvm.SI.load.const(<16 x i8> %182, i32 100)
  %252 = fmul float %251, %119
  %253 = fadd float %250, %252
  %254 = call float @llvm.SI.load.const(<16 x i8> %182, i32 104)
  %255 = fmul float %254, %126
  %256 = fadd float %253, %255
  %257 = call float @llvm.SI.load.const(<16 x i8> %182, i32 108)
  %258 = fmul float %257, %133
  %259 = fadd float %256, %258
  %260 = call float @llvm.SI.load.const(<16 x i8> %182, i32 112)
  %261 = fmul float %260, %112
  %262 = call float @llvm.SI.load.const(<16 x i8> %182, i32 116)
  %263 = fmul float %262, %119
  %264 = fadd float %261, %263
  %265 = call float @llvm.SI.load.const(<16 x i8> %182, i32 120)
  %266 = fmul float %265, %126
  %267 = fadd float %264, %266
  %268 = call float @llvm.SI.load.const(<16 x i8> %182, i32 124)
  %269 = fmul float %268, %133
  %270 = fadd float %267, %269
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %237, float %248, float %259, float %270)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %146, float %148, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %154, float %156, float %11, float %11)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %91, float %98, float %105, float %140)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %157, float %158, float %159, float %160)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %174, float %176, float %171, float %133)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 191
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR4, %VGPR1, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%61](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6, %SGPR3, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 19
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 23
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%181](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 27
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 9
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 11
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 29
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 28
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 30
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 31
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 25
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 24
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 26
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 27
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 21
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 20
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 22
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 23
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 17
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 16
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 18
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 19
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%67](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 112
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 199
	S_WAITCNT 127
	%VGPR13<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 195
	S_WAITCNT 127
	%VGPR14<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR14<kill>, %VGPR13<kill>, %VGPR15<kill>, %VGPR15, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 204
	S_WAITCNT 15
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 205
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 207
	S_WAITCNT 127
	%VGPR13<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 200
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 201
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 203
	S_WAITCNT 127
	%VGPR9<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR9<kill>, %VGPR13<kill>, %VGPR10<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 51
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 217
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 216
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 218
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 219
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 213
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 212
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 214
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 215
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 209
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 208
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 210
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 211
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR2<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 8; mem:LD16[%72](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	EXP 15, 36, 0, 0, 0, %VGPR4<kill>, %VGPR2<kill>, %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 220
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 221
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840100
bf8c007f
c20209bf
c2018900
bf8c007f
7e060203
c2010901
bf8c007f
7e020202
d2820002
040e0204
d2060802
02010102
d2820004
04060604
d2060804
02010104
f800020f
02040404
c0860700
bf8c000f
e00c2000
80030600
bf8c0770
d2820002
040c0506
d2820004
040c0507
c2020911
bf8c007f
100a0804
c2020910
bf8c007f
d282000a
04140902
d2820005
040c0508
c2020912
bf8c007f
d2820003
04280905
d2820006
04040706
c2020913
bf8c007f
d2820001
040c0906
c2020915
bf8c007f
10060804
c2020914
bf8c007f
d2820003
040c0902
c2020916
bf8c007f
d2820003
040c0905
c2020917
bf8c007f
d2820003
040c0906
c0860104
bf8c007f
c2000d0d
bf8c007f
100e0600
c2000d0c
bf8c007f
d2820008
041e0200
c2000919
bf8c007f
100e0800
c2000918
bf8c007f
d2820007
041c0102
c200091a
bf8c007f
d2820007
041c0105
c200091b
bf8c007f
d2820007
041c0106
c2000d0e
bf8c007f
d2820009
04220e00
c200091d
bf8c007f
10100800
c200091c
bf8c007f
d2820008
04200102
c200091e
bf8c007f
d2820008
04200105
c200091f
bf8c007f
d2820008
04200106
c2000d0f
bf8c007f
d2820009
04261000
c2000d09
bf8c007f
10140600
c2000d08
bf8c007f
d282000a
042a0200
c2000d0a
bf8c007f
d282000a
042a0e00
c2000d0b
bf8c007f
d282000a
042a1000
c2000d05
bf8c007f
10160600
c2000d04
bf8c007f
d282000b
042e0200
c2000d06
bf8c007f
d282000b
042e0e00
c2000d07
bf8c007f
d282000b
042e1000
c2000d01
bf8c007f
10180600
c2000d00
bf8c007f
d282000c
04320200
c2000d02
bf8c007f
d282000c
04320e00
c2000d03
bf8c007f
d282000c
04321000
f80000ef
090a0b0c
c2000d1d
bf8c000f
10120600
c2000d1c
bf8c007f
d2820009
04260200
c2000d1e
bf8c007f
d2820009
04260e00
c2000d1f
bf8c007f
d2820009
04261000
c2000d19
bf8c007f
10140600
c2000d18
bf8c007f
d282000a
042a0200
c2000d1a
bf8c007f
d282000a
042a0e00
c2000d1b
bf8c007f
d282000a
042a1000
c2000d15
bf8c007f
10160600
c2000d14
bf8c007f
d282000b
042e0200
c2000d16
bf8c007f
d282000b
042e0e00
c2000d17
bf8c007f
d282000b
042e1000
c2000d11
bf8c007f
10180600
c2000d10
bf8c007f
d282000c
04320200
c2000d12
bf8c007f
d282000c
04320e00
c2000d13
bf8c007f
d282000c
04321000
f80000ff
090a0b0c
c0860704
bf8c000f
e00c2000
80030900
c20009c4
bf8c0070
101a1200
c20009c5
bf8c007f
d282000d
0434010a
c20009c7
bf8c007f
061a1a00
c20009c0
bf8c007f
101c1200
c20009c1
bf8c007f
d282000e
0438010a
c20009c3
bf8c007f
061c1c00
7e1e0280
f800021f
0f0f0d0e
c20009cc
bf8c000f
101a1200
c20009cd
bf8c007f
d282000d
0434010a
c20009cf
bf8c007f
061a1a00
c20009c8
bf8c007f
101c1200
c20009c9
bf8c007f
d2820009
0438010a
c20009cb
bf8c007f
06121200
7e140203
7e160203
f800022f
0b0a0d09
c2000931
bf8c000f
10120800
c2000930
bf8c007f
d2820009
04240102
c2000932
bf8c007f
d2820009
04240105
c2000933
bf8c007f
d2820009
04240106
c20009d9
bf8c007f
10140800
c20009d8
bf8c007f
d282000a
04280102
c20009da
bf8c007f
d282000a
04280105
c20009db
bf8c007f
d282000a
04280106
c20009d5
bf8c007f
10160800
c20009d4
bf8c007f
d282000b
042c0102
c20009d6
bf8c007f
d282000b
042c0105
c20009d7
bf8c007f
d282000b
042c0106
c20009d1
bf8c007f
10080800
c20009d0
bf8c007f
d2820002
04100102
c20009d2
bf8c007f
d2820002
04080105
c20009d3
bf8c007f
d2820002
04080106
f800023f
090a0b02
c0820708
bf8c000f
e00c2000
80010900
bf8c0770
10001203
10041402
10081202
f800024f
00000204
c20009dc
bf8c000f
d2820000
04061000
c2000902
bf8c007f
10020e00
08021101
c20009dd
bf8c007f
10041000
08040702
f80008cf
08010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE
DCL IN[4], GENERIC[22], PERSPECTIVE
DCL IN[5], GENERIC[23], PERSPECTIVE
DCL IN[6], GENERIC[24], PERSPECTIVE, CENTROID
DCL IN[7], GENERIC[25], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..30]
DCL TEMP[0..8], LOCAL
DCL TEMP[9], ARRAY(1), LOCAL
IMM[0] FLT32 {   -0.4082,     0.7071,     0.5774,    -0.4082}
IMM[1] FLT32 {    0.8165,     0.0000,     0.5774,    -0.4082}
IMM[2] FLT32 {   -0.4082,    -0.7071,     0.5774,     0.0000}
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[3], 2D
  2: ADD TEMP[1].xyz, -IN[2].xyzz, CONST[10].xyzz
  3: MUL TEMP[2].xyz, TEMP[0].yyyy, IMM[0].xyzz
  4: MAD TEMP[2].xyz, TEMP[0].xxxx, IMM[1].xyzz, TEMP[2].xyzz
  5: MAD TEMP[2].xyz, TEMP[0].zzzz, IMM[2].xyzz, TEMP[2].xyzz
  6: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
  7: RSQ TEMP[3].x, TEMP[3].xxxx
  8: MUL TEMP[3].xyz, TEMP[2].xyzz, TEMP[3].xxxx
  9: DP3 TEMP[2].x, TEMP[3].xyzz, IN[3].xyzz
 10: DP3 TEMP[4].x, TEMP[3].xyzz, IN[4].xyzz
 11: MOV TEMP[2].y, TEMP[4].xxxx
 12: DP3 TEMP[4].x, TEMP[3].xyzz, IN[5].xyzz
 13: MOV TEMP[2].z, TEMP[4].xxxx
 14: DP3 TEMP[4].x, TEMP[2].xyzz, TEMP[1].xyzz
 15: ADD TEMP[4].x, TEMP[4].xxxx, TEMP[4].xxxx
 16: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[2].xyzz
 17: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[5].xxxx
 18: MAD TEMP[2].xyz, TEMP[4].xxxx, TEMP[2].xyzz, -TEMP[1].xyzz
 19: MOV TEMP[4].xyz, TEMP[2].xyzz
 20: TEX TEMP[4].xyz, TEMP[4], SAMP[2], CUBE
 21: MOV TEMP[5].xy, IN[1].xyyy
 22: TEX TEMP[5].xyz, TEMP[5], SAMP[0], 2D
 23: MOV TEMP[6].xy, IN[6].wzzz
 24: TEX TEMP[6].xyz, TEMP[6], SAMP[1], 2D
 25: MOV TEMP[7].xy, IN[6].xyyy
 26: TEX TEMP[7].xyz, TEMP[7], SAMP[1], 2D
 27: MOV TEMP[8].xy, IN[7].xyyy
 28: TEX TEMP[8].xyz, TEMP[8], SAMP[1], 2D
 29: MUL TEMP[4].xyz, TEMP[4].xyzz, CONST[30].zzzz
 30: MUL TEMP[4].xyz, TEMP[4].xyzz, CONST[0].xyzz
 31: MUL TEMP[5].xyz, TEMP[5].xyzz, IN[0].xyzz
 32: MUL TEMP[3].xyz, TEMP[0].yyyy, TEMP[6].xyzz
 33: MAD TEMP[1].xyz, TEMP[0].xxxx, TEMP[7].xyzz, TEMP[3].xyzz
 34: MAD TEMP[0].xyz, TEMP[0].zzzz, TEMP[8].xyzz, TEMP[1].xyzz
 35: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[12].xyzz
 36: MAD TEMP[1].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
 37: MAD TEMP[0].xyz, TEMP[5].xyzz, TEMP[0].xyzz, TEMP[4].xyzz
 38: MIN TEMP[1].x, TEMP[1].xxxx, CONST[11].zzzz
 39: MOV_SAT TEMP[1].x, TEMP[1].xxxx
 40: MAD TEMP[2].xyz, TEMP[0].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 41: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 42: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[1].xxxx
 43: MAD TEMP[0].xyz, TEMP[0].xyzz, CONST[30].xxxx, TEMP[2].xyzz
 44: MUL TEMP[1].x, IN[2].wwww, CONST[29].wwww
 45: MOV TEMP[0].w, TEMP[1].xxxx
 46: MOV TEMP[9], TEMP[0]
 47: MOV OUT[0], TEMP[9]
 48: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 160)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 164)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 168)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 188)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 488)
  %40 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0
  %42 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
  %44 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %45 = load <32 x i8> addrspace(2)* %44, !tbaa !0
  %46 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0
  %48 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %49 = load <32 x i8> addrspace(2)* %48, !tbaa !0
  %50 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %53 = load <32 x i8> addrspace(2)* %52, !tbaa !0
  %54 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
  %56 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %57 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %59 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %60 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %61 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %62 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %63 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %64 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %65 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
  %66 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
  %67 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %68 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
  %69 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
  %70 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
  %71 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
  %72 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
  %73 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
  %74 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %6)
  %75 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %6)
  %76 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %3, <2 x i32> %6)
  %77 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %3, <2 x i32> %6)
  %78 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %3, <2 x i32> %6)
  %79 = call float @llvm.SI.fs.interp(i32 1, i32 7, i32 %3, <2 x i32> %6)
  %80 = bitcast float %59 to i32
  %81 = bitcast float %60 to i32
  %82 = insertelement <2 x i32> undef, i32 %80, i32 0
  %83 = insertelement <2 x i32> %82, i32 %81, i32 1
  %84 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %83, <32 x i8> %53, <16 x i8> %55, i32 2)
  %85 = extractelement <4 x float> %84, i32 0
  %86 = extractelement <4 x float> %84, i32 1
  %87 = extractelement <4 x float> %84, i32 2
  %88 = fsub float -0.000000e+00, %61
  %89 = fadd float %88, %25
  %90 = fsub float -0.000000e+00, %62
  %91 = fadd float %90, %26
  %92 = fsub float -0.000000e+00, %63
  %93 = fadd float %92, %27
  %94 = fmul float %86, 0xBFDA20BDA0000000
  %95 = fmul float %86, 0x3FE6A09E60000000
  %96 = fmul float %86, 0x3FE279A740000000
  %97 = fmul float %85, 0x3FEA20BD80000000
  %98 = fadd float %97, %94
  %99 = fmul float %85, 0.000000e+00
  %100 = fadd float %99, %95
  %101 = fmul float %85, 0x3FE279A740000000
  %102 = fadd float %101, %96
  %103 = fmul float %87, 0xBFDA20BD20000000
  %104 = fadd float %103, %98
  %105 = fmul float %87, 0xBFE6A09E80000000
  %106 = fadd float %105, %100
  %107 = fmul float %87, 0x3FE279A740000000
  %108 = fadd float %107, %102
  %109 = fmul float %104, %104
  %110 = fmul float %106, %106
  %111 = fadd float %110, %109
  %112 = fmul float %108, %108
  %113 = fadd float %111, %112
  %114 = call float @fabs(float %113)
  %115 = call float @llvm.AMDGPU.rsq(float %114)
  %116 = fmul float %104, %115
  %117 = fmul float %106, %115
  %118 = fmul float %108, %115
  %119 = fmul float %116, %65
  %120 = fmul float %117, %66
  %121 = fadd float %120, %119
  %122 = fmul float %118, %67
  %123 = fadd float %121, %122
  %124 = fmul float %116, %68
  %125 = fmul float %117, %69
  %126 = fadd float %125, %124
  %127 = fmul float %118, %70
  %128 = fadd float %126, %127
  %129 = fmul float %116, %71
  %130 = fmul float %117, %72
  %131 = fadd float %130, %129
  %132 = fmul float %118, %73
  %133 = fadd float %131, %132
  %134 = fmul float %123, %89
  %135 = fmul float %128, %91
  %136 = fadd float %135, %134
  %137 = fmul float %133, %93
  %138 = fadd float %136, %137
  %139 = fadd float %138, %138
  %140 = fmul float %123, %123
  %141 = fmul float %128, %128
  %142 = fadd float %141, %140
  %143 = fmul float %133, %133
  %144 = fadd float %142, %143
  %145 = fmul float %89, %144
  %146 = fmul float %91, %144
  %147 = fmul float %93, %144
  %148 = fsub float -0.000000e+00, %145
  %149 = fmul float %139, %123
  %150 = fadd float %149, %148
  %151 = fsub float -0.000000e+00, %146
  %152 = fmul float %139, %128
  %153 = fadd float %152, %151
  %154 = fsub float -0.000000e+00, %147
  %155 = fmul float %139, %133
  %156 = fadd float %155, %154
  %157 = insertelement <4 x float> undef, float %150, i32 0
  %158 = insertelement <4 x float> %157, float %153, i32 1
  %159 = insertelement <4 x float> %158, float %156, i32 2
  %160 = insertelement <4 x float> %159, float 0.000000e+00, i32 3
  %161 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %160)
  %162 = extractelement <4 x float> %161, i32 0
  %163 = extractelement <4 x float> %161, i32 1
  %164 = extractelement <4 x float> %161, i32 2
  %165 = extractelement <4 x float> %161, i32 3
  %166 = call float @fabs(float %164)
  %167 = fdiv float 1.000000e+00, %166
  %168 = fmul float %162, %167
  %169 = fadd float %168, 1.500000e+00
  %170 = fmul float %163, %167
  %171 = fadd float %170, 1.500000e+00
  %172 = bitcast float %171 to i32
  %173 = bitcast float %169 to i32
  %174 = bitcast float %165 to i32
  %175 = insertelement <4 x i32> undef, i32 %172, i32 0
  %176 = insertelement <4 x i32> %175, i32 %173, i32 1
  %177 = insertelement <4 x i32> %176, i32 %174, i32 2
  %178 = insertelement <4 x i32> %177, i32 undef, i32 3
  %179 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %178, <32 x i8> %49, <16 x i8> %51, i32 4)
  %180 = extractelement <4 x float> %179, i32 0
  %181 = extractelement <4 x float> %179, i32 1
  %182 = extractelement <4 x float> %179, i32 2
  %183 = bitcast float %59 to i32
  %184 = bitcast float %60 to i32
  %185 = insertelement <2 x i32> undef, i32 %183, i32 0
  %186 = insertelement <2 x i32> %185, i32 %184, i32 1
  %187 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %186, <32 x i8> %41, <16 x i8> %43, i32 2)
  %188 = extractelement <4 x float> %187, i32 0
  %189 = extractelement <4 x float> %187, i32 1
  %190 = extractelement <4 x float> %187, i32 2
  %191 = bitcast float %77 to i32
  %192 = bitcast float %76 to i32
  %193 = insertelement <2 x i32> undef, i32 %191, i32 0
  %194 = insertelement <2 x i32> %193, i32 %192, i32 1
  %195 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %194, <32 x i8> %45, <16 x i8> %47, i32 2)
  %196 = extractelement <4 x float> %195, i32 0
  %197 = extractelement <4 x float> %195, i32 1
  %198 = extractelement <4 x float> %195, i32 2
  %199 = bitcast float %74 to i32
  %200 = bitcast float %75 to i32
  %201 = insertelement <2 x i32> undef, i32 %199, i32 0
  %202 = insertelement <2 x i32> %201, i32 %200, i32 1
  %203 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %202, <32 x i8> %45, <16 x i8> %47, i32 2)
  %204 = extractelement <4 x float> %203, i32 0
  %205 = extractelement <4 x float> %203, i32 1
  %206 = extractelement <4 x float> %203, i32 2
  %207 = bitcast float %78 to i32
  %208 = bitcast float %79 to i32
  %209 = insertelement <2 x i32> undef, i32 %207, i32 0
  %210 = insertelement <2 x i32> %209, i32 %208, i32 1
  %211 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %210, <32 x i8> %45, <16 x i8> %47, i32 2)
  %212 = extractelement <4 x float> %211, i32 0
  %213 = extractelement <4 x float> %211, i32 1
  %214 = extractelement <4 x float> %211, i32 2
  %215 = fmul float %180, %39
  %216 = fmul float %181, %39
  %217 = fmul float %182, %39
  %218 = fmul float %215, %22
  %219 = fmul float %216, %23
  %220 = fmul float %217, %24
  %221 = fmul float %188, %56
  %222 = fmul float %189, %57
  %223 = fmul float %190, %58
  %224 = fmul float %86, %196
  %225 = fmul float %86, %197
  %226 = fmul float %86, %198
  %227 = fmul float %85, %204
  %228 = fadd float %227, %224
  %229 = fmul float %85, %205
  %230 = fadd float %229, %225
  %231 = fmul float %85, %206
  %232 = fadd float %231, %226
  %233 = fmul float %87, %212
  %234 = fadd float %233, %228
  %235 = fmul float %87, %213
  %236 = fadd float %235, %230
  %237 = fmul float %87, %214
  %238 = fadd float %237, %232
  %239 = fmul float %234, %31
  %240 = fmul float %236, %32
  %241 = fmul float %238, %33
  %242 = fsub float -0.000000e+00, %28
  %243 = fmul float %64, %30
  %244 = fadd float %243, %242
  %245 = fmul float %221, %239
  %246 = fadd float %245, %218
  %247 = fmul float %222, %240
  %248 = fadd float %247, %219
  %249 = fmul float %223, %241
  %250 = fadd float %249, %220
  %251 = fcmp uge float %244, %29
  %252 = select i1 %251, float %29, float %244
  %253 = call float @llvm.AMDIL.clamp.(float %252, float 0.000000e+00, float 1.000000e+00)
  %254 = fsub float -0.000000e+00, %38
  %255 = fmul float %246, %254
  %256 = fadd float %255, %34
  %257 = fsub float -0.000000e+00, %38
  %258 = fmul float %248, %257
  %259 = fadd float %258, %35
  %260 = fsub float -0.000000e+00, %38
  %261 = fmul float %250, %260
  %262 = fadd float %261, %36
  %263 = fmul float %253, %253
  %264 = fmul float %256, %263
  %265 = fmul float %259, %263
  %266 = fmul float %262, %263
  %267 = fmul float %246, %38
  %268 = fadd float %267, %264
  %269 = fmul float %248, %38
  %270 = fadd float %269, %265
  %271 = fmul float %250, %38
  %272 = fadd float %271, %266
  %273 = fmul float %64, %37
  %274 = call i32 @llvm.SI.packf16(float %268, float %270)
  %275 = bitcast i32 %274 to float
  %276 = call i32 @llvm.SI.packf16(float %272, float %273)
  %277 = bitcast i32 %276 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %275, float %277, float %275, float %277)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #3

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #3

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 12; mem:LD16[%54](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 24; mem:LD32[%52](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR9<def> = V_MUL_F32_e32 7.071068e-01, %VGPR5, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR4, 0.000000e+00, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 -7.071068e-01, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR6, %VGPR10<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 -4.082483e-01, %VGPR5, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 8.164966e-01, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR4, %VGPR11<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 -4.082482e-01, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR6, %VGPR11<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR12, %VGPR12, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR10, %VGPR10, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 5.773503e-01, %VGPR5, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 5.773503e-01, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR4, %VGPR13, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR6, %VGPR13<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR9, %VGPR9, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_RSQ_LEGACY_F32_e32 %VGPR11<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR12, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR10, %VGPR14<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR13, %VGPR9<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR12, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR10, %VGPR14<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR13, %VGPR14<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR11, %VGPR11, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR9, %VGPR9, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR10<kill>, %VGPR15<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR13<kill>, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR10, %VGPR10, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 41
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR15, %VGPR12, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 40
	S_WAITCNT 127
	%VGPR14<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR11, %VGPR14, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR9, %VGPR15<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 42
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR10, %VGPR15, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e32 %VGPR16<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR16, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %VGPR9<kill>, %VGPR13<kill>, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR16, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR9<kill>, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR20<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR10<def> = V_CUBESC_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR9<def> = V_CUBETC_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR11<def> = V_CUBEMA_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR12<def> = V_CUBEID_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR17<def> = V_ADD_F32_e64 %VGPR11, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_RCP_F32_e32 %VGPR17<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR9, %VGPR17, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR10<def> = V_MAD_F32 %VGPR10, %VGPR17<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR13<def> = KILL %VGPR13<undef>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%50](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%48](tbaa=!"const")
	S_WAITCNT 127
	%VGPR9_VGPR10_VGPR11<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR10_VGPR11_VGPR12_VGPR13, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 122
	S_WAITCNT 112
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0, %VGPR10, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR24<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR2, 2, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-def>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<tied0>, %VGPR3, 2, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR2, 3, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<tied0>, %VGPR3, 3, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%46](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%44](tbaa=!"const")
	S_WAITCNT 127
	%VGPR12_VGPR13_VGPR14<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR12_VGPR13<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %VGPR5, %VGPR13, %EXEC<imp-use>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR2, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-def>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<tied0>, %VGPR3, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR2, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<tied0>, %VGPR3, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR15_VGPR16_VGPR17<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR15_VGPR16<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MAD_F32 %VGPR4, %VGPR16, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_INTERP_P1_F32 %VGPR2, 1, 7, %M0<kill>, %EXEC<imp-use>, %VGPR19_VGPR20<imp-def>
	%VGPR20<def,tied1> = V_INTERP_P2_F32 %VGPR20<tied0>, %VGPR3, 1, 7, %M0<kill>, %EXEC<imp-use>, %VGPR19_VGPR20<imp-use,kill>, %VGPR19_VGPR20<imp-def>
	%VGPR19<def> = V_INTERP_P1_F32 %VGPR2, 0, 7, %M0<kill>, %EXEC<imp-use>, %VGPR19_VGPR20<imp-use,kill>, %VGPR19_VGPR20<imp-def>
	%VGPR19<def,tied1> = V_INTERP_P2_F32 %VGPR19<tied0>, %VGPR3, 0, 7, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR19_VGPR20<imp-use,kill>, %VGPR19_VGPR20<imp-def>
	%VGPR21_VGPR22_VGPR23<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR19_VGPR20<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %VGPR22, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%42](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%40](tbaa=!"const")
	S_WAITCNT 127
	%VGPR18_VGPR19_VGPR20<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR3<def> = V_MUL_F32_e32 %VGPR19, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR3<kill>, %VGPR2<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 120
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR1, %VGPR7, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 117
	S_WAITCNT 127
	%VGPR8<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR24<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR7<kill>, %SGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0, %VGPR9, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR5, %VGPR12, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR4, %VGPR15, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR6, %VGPR21, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR24<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR25<def,tied1> = V_INTERP_P2_F32 %VGPR25<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR18, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR25<kill>, %VGPR24<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR1, %VGPR8, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 116
	S_WAITCNT 127
	%VGPR24<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8<kill>, %SGPR1, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR11, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR5, %VGPR14, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14<imp-use,kill>
	%VGPR9<def> = V_MAD_F32 %VGPR4, %VGPR17, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR15_VGPR16_VGPR17<imp-use,kill>
	%VGPR4<def> = V_MAD_F32 %VGPR6, %VGPR23, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23<imp-use,kill>, %VGPR4_VGPR5_VGPR6<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR20, %VGPR5<kill>, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20<imp-use,kill>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %VGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR1, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 118
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR1<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 119
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR7<kill>, %VGPR0<kill>, %VGPR7, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8200500
c8210501
c81c0400
c81d0401
c084030c
c0c60518
bf8c007f
f0800700
00430407
bf8c0770
10120aff
3f3504f3
d2820009
04250104
7e1402ff
bf3504f4
d282000a
04261506
10120aff
bed105ed
7e1602ff
3f5105ec
d2820009
04261704
7e1602ff
bed105e9
d282000c
04261706
1012190c
d282000b
0426150a
10120aff
3f13cd3a
7e1a02ff
3f13cd3a
d2820009
04261b04
d2820009
04261b06
d282000b
042e1309
d206010b
0201010b
7e165b0b
1014170a
1018170c
c8341000
c8351001
101a1b0c
c8381100
c8391101
d282000e
04361d0a
101a1709
c8241200
c8251201
d2820009
043a130d
c82c0c00
c82d0c01
1016170c
c8380d00
c8390d01
d282000b
042e1d0a
c8380e00
c8390e01
d282000b
042e1d0d
101c170b
d282000e
043a1309
c83c1400
c83d1401
10181f0c
c83c1500
c83d1501
d282000a
04321f0a
c8301600
c8311601
d282000a
042a190d
d282000c
043a150a
c8340900
c8350901
c0840100
bf8c007f
c2000929
bf8c007f
081e1a00
101a190f
c8380800
c8390801
c2000928
bf8c007f
081c1c00
10201d0b
d2820010
04421f09
c83c0a00
c83d0a01
c200092a
bf8c007f
081e1e00
d2820010
04421f0a
06202110
10121310
08241b09
1012190e
10161710
0822130b
1012190f
10141510
0826130a
7e280280
d28a000a
044e2511
d28c0009
044e2511
d28e000b
044e2511
d288000c
044e2511
d2060111
0201010b
7e225511
7e2402ff
3fc00000
d282000b
044a2309
d282000a
044a230a
c0860308
c0c80510
bf8c007f
f0800700
0064090a
c200097a
bf8c0070
10181400
c2008901
bf8c007f
10301801
c8341a02
c8351a03
c8301b02
c8311b03
c0860304
c0c80508
bf8c007f
f0800700
00640c0c
bf8c0770
10241b05
c8401902
c8411903
c83c1802
c83d1803
f0800700
00640f0f
bf8c0770
d2820012
044a2104
c8501d02
c8511d03
c84c1c02
c84d1c03
f0800700
00641513
bf8c0770
d2820002
044a2d06
c2008931
bf8c007f
10040401
c0860300
c0c80500
bf8c007f
f0800700
00641207
c80c0100
c80d0101
bf8c0770
10060713
d2820007
04620503
c2008978
bf8c007f
10040e01
c2010975
bf8c007f
08100402
c8080b00
c8090b01
c201092f
bf8c007f
10060402
c201092c
bf8c007f
0a060602
c201092e
bf8c007f
d00c0004
02000503
7e300202
d2000003
00123103
d2060803
02010103
10060703
10100708
d2820007
04200307
10101200
c2010900
bf8c007f
10101002
10301905
d2820018
04621f04
d2820018
04622b06
c2010930
bf8c007f
10303002
c8640000
c8650001
10323312
d2820008
04223119
10301001
c2010974
bf8c007f
08303002
10300718
d2820008
04600308
5e0e0f08
10101600
c2000902
bf8c007f
10101000
10121d05
d2820009
04262304
d2820004
04262f06
c2000932
bf8c007f
10080800
c8140200
c8150201
10000b14
d2820000
04220900
10020001
c2000976
bf8c007f
08020200
10020701
d2820000
04040300
c2000977
bf8c007f
10020400
5e000300
f8001c0f
00070007
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL OUT[7], GENERIC[23]
DCL OUT[8], GENERIC[24]
DCL OUT[9], GENERIC[25]
DCL CONST[0..51]
DCL TEMP[0..12], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[6]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: DP4 TEMP[5].x, TEMP[0], CONST[7]
 12: MOV TEMP[2].w, TEMP[5].xxxx
 13: DP4 TEMP[6].x, TEMP[0], CONST[12]
 14: DP3 TEMP[7].x, IN[1].xyzz, CONST[48].xyzz
 15: MOV TEMP[7].z, TEMP[7].xxxx
 16: DP3 TEMP[8].x, IN[1].xyzz, CONST[49].xyzz
 17: MOV TEMP[8].z, TEMP[8].xxxx
 18: DP3 TEMP[9].x, IN[1].xyzz, CONST[50].xyzz
 19: MOV TEMP[9].z, TEMP[9].xxxx
 20: DP3 TEMP[7].x, IN[5].xyzz, CONST[48].xyzz
 21: DP3 TEMP[8].x, IN[5].xyzz, CONST[49].xyzz
 22: DP3 TEMP[9].x, IN[5].xyzz, CONST[50].xyzz
 23: DP3 TEMP[10].x, IN[6].xyzz, CONST[48].xyzz
 24: MOV TEMP[7].y, TEMP[10].xxxx
 25: ADD TEMP[0].xy, IN[4].xyyy, IN[3].xyyy
 26: DP3 TEMP[10].x, IN[6].xyzz, CONST[49].xyzz
 27: MOV TEMP[8].y, TEMP[10].xxxx
 28: ADD TEMP[10].xy, TEMP[0].yxxx, IN[4].yxxx
 29: MOV TEMP[0].zw, TEMP[10].yyxy
 30: DP3 TEMP[11].x, IN[6].xyzz, CONST[50].xyzz
 31: MOV TEMP[9].y, TEMP[11].xxxx
 32: MOV TEMP[0], TEMP[0]
 33: ADD TEMP[10].xy, TEMP[10].yxxx, IN[4].xyyy
 34: MOV TEMP[1].w, TEMP[6].xxxx
 35: MOV TEMP[6].xy, IN[2].xyxx
 36: MOV TEMP[10].zw, IN[2].yyxy
 37: MAD TEMP[11], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 38: MOV TEMP[12], TEMP[2]
 39: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[5].xxxx
 40: MOV TEMP[2].z, TEMP[4].xxxx
 41: MOV TEMP[2].y, -TEMP[3].xxxx
 42: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[5].xxxx, TEMP[2].xyyy
 43: MOV OUT[3], TEMP[6]
 44: MOV OUT[8], TEMP[0]
 45: MOV OUT[9], TEMP[10]
 46: MOV OUT[0], TEMP[2]
 47: MOV OUT[4], TEMP[1]
 48: MOV OUT[2], TEMP[12]
 49: MOV OUT[5], TEMP[7]
 50: MOV OUT[6], TEMP[8]
 51: MOV_SAT OUT[1], TEMP[11]
 52: MOV OUT[7], TEMP[9]
 53: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 764)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 776)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 792)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 800)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 804)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 808)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 812)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 816)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 820)
  %49 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0
  %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %5)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = extractelement <4 x float> %51, i32 1
  %54 = extractelement <4 x float> %51, i32 2
  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = extractelement <4 x float> %57, i32 2
  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
  %64 = extractelement <4 x float> %63, i32 0
  %65 = extractelement <4 x float> %63, i32 1
  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
  %69 = extractelement <4 x float> %68, i32 0
  %70 = extractelement <4 x float> %68, i32 1
  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
  %74 = extractelement <4 x float> %73, i32 0
  %75 = extractelement <4 x float> %73, i32 1
  %76 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
  %77 = load <16 x i8> addrspace(2)* %76, !tbaa !0
  %78 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %77, i32 0, i32 %5)
  %79 = extractelement <4 x float> %78, i32 0
  %80 = extractelement <4 x float> %78, i32 1
  %81 = extractelement <4 x float> %78, i32 2
  %82 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
  %83 = load <16 x i8> addrspace(2)* %82, !tbaa !0
  %84 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %83, i32 0, i32 %5)
  %85 = extractelement <4 x float> %84, i32 0
  %86 = extractelement <4 x float> %84, i32 1
  %87 = extractelement <4 x float> %84, i32 2
  %88 = fmul float %52, %12
  %89 = fadd float %88, %11
  %90 = fmul float %53, %12
  %91 = fadd float %90, %11
  %92 = fmul float %54, %12
  %93 = fadd float %92, %11
  %94 = fmul float %52, %11
  %95 = fadd float %94, %12
  %96 = fmul float %89, %35
  %97 = fmul float %91, %36
  %98 = fadd float %96, %97
  %99 = fmul float %93, %37
  %100 = fadd float %98, %99
  %101 = fmul float %95, %38
  %102 = fadd float %100, %101
  %103 = fmul float %89, %39
  %104 = fmul float %91, %40
  %105 = fadd float %103, %104
  %106 = fmul float %93, %41
  %107 = fadd float %105, %106
  %108 = fmul float %95, %42
  %109 = fadd float %107, %108
  %110 = fmul float %89, %43
  %111 = fmul float %91, %44
  %112 = fadd float %110, %111
  %113 = fmul float %93, %45
  %114 = fadd float %112, %113
  %115 = fmul float %95, %46
  %116 = fadd float %114, %115
  %117 = fmul float %89, %14
  %118 = fmul float %91, %15
  %119 = fadd float %117, %118
  %120 = fmul float %93, %16
  %121 = fadd float %119, %120
  %122 = fmul float %95, %17
  %123 = fadd float %121, %122
  %124 = fmul float %89, %18
  %125 = fmul float %91, %19
  %126 = fadd float %124, %125
  %127 = fmul float %93, %20
  %128 = fadd float %126, %127
  %129 = fmul float %95, %21
  %130 = fadd float %128, %129
  %131 = fmul float %89, %22
  %132 = fmul float %91, %23
  %133 = fadd float %131, %132
  %134 = fmul float %93, %24
  %135 = fadd float %133, %134
  %136 = fmul float %95, %25
  %137 = fadd float %135, %136
  %138 = fmul float %89, %26
  %139 = fmul float %91, %27
  %140 = fadd float %138, %139
  %141 = fmul float %93, %28
  %142 = fadd float %140, %141
  %143 = fmul float %95, %29
  %144 = fadd float %142, %143
  %145 = fmul float %89, %30
  %146 = fmul float %91, %31
  %147 = fadd float %145, %146
  %148 = fmul float %93, %32
  %149 = fadd float %147, %148
  %150 = fmul float %95, %33
  %151 = fadd float %149, %150
  %152 = fmul float %58, %35
  %153 = fmul float %59, %36
  %154 = fadd float %153, %152
  %155 = fmul float %60, %37
  %156 = fadd float %154, %155
  %157 = fmul float %58, %39
  %158 = fmul float %59, %40
  %159 = fadd float %158, %157
  %160 = fmul float %60, %41
  %161 = fadd float %159, %160
  %162 = fmul float %58, %43
  %163 = fmul float %59, %44
  %164 = fadd float %163, %162
  %165 = fmul float %60, %45
  %166 = fadd float %164, %165
  %167 = fmul float %79, %35
  %168 = fmul float %80, %36
  %169 = fadd float %168, %167
  %170 = fmul float %81, %37
  %171 = fadd float %169, %170
  %172 = fmul float %79, %39
  %173 = fmul float %80, %40
  %174 = fadd float %173, %172
  %175 = fmul float %81, %41
  %176 = fadd float %174, %175
  %177 = fmul float %79, %43
  %178 = fmul float %80, %44
  %179 = fadd float %178, %177
  %180 = fmul float %81, %45
  %181 = fadd float %179, %180
  %182 = fmul float %85, %35
  %183 = fmul float %86, %36
  %184 = fadd float %183, %182
  %185 = fmul float %87, %37
  %186 = fadd float %184, %185
  %187 = fadd float %74, %69
  %188 = fadd float %75, %70
  %189 = fmul float %85, %39
  %190 = fmul float %86, %40
  %191 = fadd float %190, %189
  %192 = fmul float %87, %41
  %193 = fadd float %191, %192
  %194 = fadd float %188, %75
  %195 = fadd float %187, %74
  %196 = fmul float %85, %43
  %197 = fmul float %86, %44
  %198 = fadd float %197, %196
  %199 = fmul float %87, %45
  %200 = fadd float %198, %199
  %201 = fadd float %195, %74
  %202 = fadd float %194, %75
  %203 = fmul float %34, %11
  %204 = fadd float %203, %12
  %205 = fmul float %34, %11
  %206 = fadd float %205, %12
  %207 = fmul float %34, %11
  %208 = fadd float %207, %12
  %209 = fmul float %34, %12
  %210 = fadd float %209, %11
  %211 = fsub float -0.000000e+00, %144
  %212 = fmul float %137, %13
  %213 = fadd float %212, %211
  %214 = fsub float -0.000000e+00, %130
  %215 = fmul float %47, %144
  %216 = fadd float %215, %123
  %217 = fmul float %48, %144
  %218 = fadd float %217, %214
  %219 = call float @llvm.AMDIL.clamp.(float %204, float 0.000000e+00, float 1.000000e+00)
  %220 = call float @llvm.AMDIL.clamp.(float %206, float 0.000000e+00, float 1.000000e+00)
  %221 = call float @llvm.AMDIL.clamp.(float %208, float 0.000000e+00, float 1.000000e+00)
  %222 = call float @llvm.AMDIL.clamp.(float %210, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %219, float %220, float %221, float %222)
  %223 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %224 = load <16 x i8> addrspace(2)* %223, !tbaa !0
  %225 = call float @llvm.SI.load.const(<16 x i8> %224, i32 0)
  %226 = fmul float %225, %123
  %227 = call float @llvm.SI.load.const(<16 x i8> %224, i32 4)
  %228 = fmul float %227, %130
  %229 = fadd float %226, %228
  %230 = call float @llvm.SI.load.const(<16 x i8> %224, i32 8)
  %231 = fmul float %230, %137
  %232 = fadd float %229, %231
  %233 = call float @llvm.SI.load.const(<16 x i8> %224, i32 12)
  %234 = fmul float %233, %144
  %235 = fadd float %232, %234
  %236 = call float @llvm.SI.load.const(<16 x i8> %224, i32 16)
  %237 = fmul float %236, %123
  %238 = call float @llvm.SI.load.const(<16 x i8> %224, i32 20)
  %239 = fmul float %238, %130
  %240 = fadd float %237, %239
  %241 = call float @llvm.SI.load.const(<16 x i8> %224, i32 24)
  %242 = fmul float %241, %137
  %243 = fadd float %240, %242
  %244 = call float @llvm.SI.load.const(<16 x i8> %224, i32 28)
  %245 = fmul float %244, %144
  %246 = fadd float %243, %245
  %247 = call float @llvm.SI.load.const(<16 x i8> %224, i32 32)
  %248 = fmul float %247, %123
  %249 = call float @llvm.SI.load.const(<16 x i8> %224, i32 36)
  %250 = fmul float %249, %130
  %251 = fadd float %248, %250
  %252 = call float @llvm.SI.load.const(<16 x i8> %224, i32 40)
  %253 = fmul float %252, %137
  %254 = fadd float %251, %253
  %255 = call float @llvm.SI.load.const(<16 x i8> %224, i32 44)
  %256 = fmul float %255, %144
  %257 = fadd float %254, %256
  %258 = call float @llvm.SI.load.const(<16 x i8> %224, i32 48)
  %259 = fmul float %258, %123
  %260 = call float @llvm.SI.load.const(<16 x i8> %224, i32 52)
  %261 = fmul float %260, %130
  %262 = fadd float %259, %261
  %263 = call float @llvm.SI.load.const(<16 x i8> %224, i32 56)
  %264 = fmul float %263, %137
  %265 = fadd float %262, %264
  %266 = call float @llvm.SI.load.const(<16 x i8> %224, i32 60)
  %267 = fmul float %266, %144
  %268 = fadd float %265, %267
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %235, float %246, float %257, float %268)
  %269 = call float @llvm.SI.load.const(<16 x i8> %224, i32 64)
  %270 = fmul float %269, %123
  %271 = call float @llvm.SI.load.const(<16 x i8> %224, i32 68)
  %272 = fmul float %271, %130
  %273 = fadd float %270, %272
  %274 = call float @llvm.SI.load.const(<16 x i8> %224, i32 72)
  %275 = fmul float %274, %137
  %276 = fadd float %273, %275
  %277 = call float @llvm.SI.load.const(<16 x i8> %224, i32 76)
  %278 = fmul float %277, %144
  %279 = fadd float %276, %278
  %280 = call float @llvm.SI.load.const(<16 x i8> %224, i32 80)
  %281 = fmul float %280, %123
  %282 = call float @llvm.SI.load.const(<16 x i8> %224, i32 84)
  %283 = fmul float %282, %130
  %284 = fadd float %281, %283
  %285 = call float @llvm.SI.load.const(<16 x i8> %224, i32 88)
  %286 = fmul float %285, %137
  %287 = fadd float %284, %286
  %288 = call float @llvm.SI.load.const(<16 x i8> %224, i32 92)
  %289 = fmul float %288, %144
  %290 = fadd float %287, %289
  %291 = call float @llvm.SI.load.const(<16 x i8> %224, i32 96)
  %292 = fmul float %291, %123
  %293 = call float @llvm.SI.load.const(<16 x i8> %224, i32 100)
  %294 = fmul float %293, %130
  %295 = fadd float %292, %294
  %296 = call float @llvm.SI.load.const(<16 x i8> %224, i32 104)
  %297 = fmul float %296, %137
  %298 = fadd float %295, %297
  %299 = call float @llvm.SI.load.const(<16 x i8> %224, i32 108)
  %300 = fmul float %299, %144
  %301 = fadd float %298, %300
  %302 = call float @llvm.SI.load.const(<16 x i8> %224, i32 112)
  %303 = fmul float %302, %123
  %304 = call float @llvm.SI.load.const(<16 x i8> %224, i32 116)
  %305 = fmul float %304, %130
  %306 = fadd float %303, %305
  %307 = call float @llvm.SI.load.const(<16 x i8> %224, i32 120)
  %308 = fmul float %307, %137
  %309 = fadd float %306, %308
  %310 = call float @llvm.SI.load.const(<16 x i8> %224, i32 124)
  %311 = fmul float %310, %144
  %312 = fadd float %309, %311
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %279, float %290, float %301, float %312)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %64, float %65, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %102, float %109, float %116, float %151)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %171, float %186, float %156, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %176, float %193, float %161, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %181, float %200, float %166, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %187, float %188, float %194, float %195)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %201, float %202, float %64, float %65)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %216, float %218, float %213, float %144)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 191
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR4, %VGPR1, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%49](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR3, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR9, %SGPR3, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR10, %SGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR3<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 19
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 23
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%223](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 27
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 30
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 31
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 19
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%61](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 15
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 51
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 201
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR0, %VGPR6, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 200
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR5, %SGPR1, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 202
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR7, %SGPR2, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 203
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR8, %SGPR3<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 127
	%VGPR16<def> = V_MUL_F32_e32 %SGPR3, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR5, %SGPR4, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 198
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR7, %SGPR5, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 199
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR8, %SGPR12<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR12, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR5<kill>, %SGPR14, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 194
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR7<kill>, %SGPR13, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 195
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR8<kill>, %SGPR15<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR5<kill>, %VGPR16<kill>, %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%55](tbaa=!"const")
	S_WAITCNT 15
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR14<def> = V_MUL_F32_e32 %SGPR14, %VGPR5, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR6, %SGPR12, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR7, %SGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 24; mem:LD16[%82](tbaa=!"const")
	S_WAITCNT 127
	%VGPR14_VGPR15_VGPR16_VGPR17<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %SGPR14, %VGPR14, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR15, %SGPR12, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR16, %SGPR13, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%76](tbaa=!"const")
	S_WAITCNT 127
	%VGPR18_VGPR19_VGPR20_VGPR21<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR24<def> = V_MUL_F32_e32 %SGPR14<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR19, %SGPR12<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR20, %SGPR13<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR24<kill>, %VGPR23<kill>, %VGPR22<kill>, %VGPR13, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR22<def> = V_MUL_F32_e32 %SGPR4, %VGPR5, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR6, %SGPR3, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR7, %SGPR5, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %SGPR4, %VGPR14, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR15, %SGPR3, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR16, %SGPR5, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR19, %SGPR3<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR20, %SGPR5<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 36, 0, 0, 0, %VGPR24<kill>, %VGPR23<kill>, %VGPR22<kill>, %VGPR13, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR22<def> = V_MUL_F32_e32 %SGPR1, %VGPR5, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR6, %SGPR0, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR7, %SGPR2, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR1, %VGPR14, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR15, %SGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR16, %SGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR19, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR20, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>
	EXP 15, 37, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%66](tbaa=!"const")
	S_WAITCNT 15
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 16; mem:LD16[%71](tbaa=!"const")
	S_WAITCNT 112
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR17<def> = V_ADD_F32_e32 %VGPR5, %VGPR13, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR17, %VGPR5, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e32 %VGPR6, %VGPR14, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR13, %VGPR6, %EXEC<imp-use>
	EXP 15, 38, 0, 0, 0, %VGPR17<kill>, %VGPR13<kill>, %VGPR14, %VGPR0, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR13<def> = V_ADD_F32_e32 %VGPR14<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR0<kill>, %VGPR5, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	EXP 15, 39, 0, 0, 0, %VGPR0<kill>, %VGPR13<kill>, %VGPR9, %VGPR10, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 204
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 205
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840100
bf8c007f
c20209bf
c2010900
bf8c007f
7e040202
c2018901
bf8c007f
7e020203
d2820003
040a0204
d2060803
02010103
d2820004
04060404
d2060804
02010104
f800020f
03040404
c0860700
bf8c000f
e00c2000
80030800
bf8c0770
d2820005
04080708
d2820006
04080709
c2020911
bf8c007f
10060c04
c2020910
bf8c007f
d2820003
040c0905
d2820007
0408070a
c2018912
bf8c007f
d2820002
040c0707
d2820008
04040508
c2010913
bf8c007f
d2820001
04080508
c2010915
bf8c007f
10040c02
c2010914
bf8c007f
d2820002
04080505
c2010916
bf8c007f
d2820002
04080507
c2010917
bf8c007f
d2820002
04080508
c0800104
bf8c007f
c202010d
bf8c007f
10060404
c202010c
bf8c007f
d2820004
040e0204
c2020919
bf8c007f
10060c04
c2020918
bf8c007f
d2820003
040c0905
c202091a
bf8c007f
d2820003
040c0907
c202091b
bf8c007f
d2820003
040c0908
c202010e
bf8c007f
d2820009
04120604
c202091d
bf8c007f
10080c04
c202091c
bf8c007f
d2820004
04100905
c202091e
bf8c007f
d2820004
04100907
c202091f
bf8c007f
d2820004
04100908
c202010f
bf8c007f
d2820009
04260804
c2020109
bf8c007f
10140404
c2020108
bf8c007f
d282000a
042a0204
c202010a
bf8c007f
d282000a
042a0604
c202010b
bf8c007f
d282000a
042a0804
c2020105
bf8c007f
10160404
c2020104
bf8c007f
d282000b
042e0204
c2020106
bf8c007f
d282000b
042e0604
c2020107
bf8c007f
d282000b
042e0804
c2020101
bf8c007f
10180404
c2020100
bf8c007f
d282000c
04320204
c2020102
bf8c007f
d282000c
04320604
c2020103
bf8c007f
d282000c
04320804
f80000ef
090a0b0c
c202011d
bf8c000f
10120404
c202011c
bf8c007f
d2820009
04260204
c202011e
bf8c007f
d2820009
04260604
c202011f
bf8c007f
d2820009
04260804
c2020119
bf8c007f
10140404
c2020118
bf8c007f
d282000a
042a0204
c202011a
bf8c007f
d282000a
042a0604
c202011b
bf8c007f
d282000a
042a0804
c2020115
bf8c007f
10160404
c2020114
bf8c007f
d282000b
042e0204
c2020116
bf8c007f
d282000b
042e0604
c2020117
bf8c007f
d282000b
042e0804
c2020111
bf8c007f
10180404
c2020110
bf8c007f
d282000c
04320204
c2020112
bf8c007f
d282000c
04320604
c2000113
bf8c007f
d282000c
04320800
f80000ff
090a0b0c
c0800708
bf8c000f
e00c2000
80000900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c2000931
bf8c000f
101c0c00
c2000930
bf8c007f
d282000e
04380105
c2000932
bf8c007f
d282000e
04380107
c2000933
bf8c007f
d282000e
04380108
c20009c9
bf8c007f
101e0c00
c20089c8
bf8c007f
d282000f
043c0305
c20109ca
bf8c007f
d282000f
043c0507
c20189cb
bf8c007f
d282000f
043c0708
c20189c5
bf8c007f
10200c03
c20209c4
bf8c007f
d2820010
04400905
c20289c6
bf8c007f
d2820010
04400b07
c20609c7
bf8c007f
d2820010
04401908
c20609c1
bf8c007f
100c0c0c
c20709c0
bf8c007f
d2820005
04181d05
c20689c2
bf8c007f
d2820005
04141b07
c20789c3
bf8c007f
d2820005
04141f08
f800022f
0e0f1005
c0880704
bf8c000f
e00c2000
80040500
bf8c0770
101c0a0e
d282000e
04381906
d2820016
04381b07
c0880718
bf8c007f
e00c2000
80040e00
bf8c0770
10241c0e
d2820012
0448190f
d2820017
04481b10
c0880714
bf8c007f
e00c2000
80041200
bf8c0770
1030240e
d2820018
04601913
d2820018
04601b14
f800023f
0d161718
bf8c070f
102c0a04
d2820016
04580706
d2820016
04580b07
102e1c04
d2820017
045c070f
d2820017
045c0b10
10302404
d2820018
04600713
d2820018
04600b14
f800024f
0d161718
bf8c070f
102c0a01
d2820016
04580106
d2820005
04580507
100c1c01
d2820006
0418010f
d2820006
04180510
100e2401
d2820007
041c0113
d2820007
041c0514
f800025f
0d050607
c080070c
bf8c000f
e00c2000
80000d00
c0800710
bf8c0070
e00c2000
80000500
bf8c0770
06221b05
06000b11
061a1d06
061c0d0d
f800026f
000e0d11
bf8c070f
061a0d0e
06000b00
f800027f
0a090d00
c20009cc
bf8c000f
d2820000
04060800
c2000902
bf8c007f
10020600
08020901
c20009cd
bf8c007f
10060800
08040503
f80008cf
04010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE
DCL IN[4], GENERIC[22], PERSPECTIVE
DCL IN[5], GENERIC[23], PERSPECTIVE
DCL IN[6], GENERIC[24], PERSPECTIVE, CENTROID
DCL IN[7], GENERIC[25], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..30]
DCL TEMP[0..9], LOCAL
DCL TEMP[10], ARRAY(1), LOCAL
IMM[0] FLT32 {    2.0000,    -1.0000,     1.0000,    -0.7071}
IMM[1] FLT32 {    0.8165,     0.0000,     0.5774,    -0.4082}
IMM[2] FLT32 {   -0.4082,     0.7071,     0.5774,    -0.4082}
IMM[3] FLT32 {   -0.4082,    -0.7071,     0.5774,     0.0000}
  0: MOV TEMP[0].xy, IN[7].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[1], 2D
  2: MOV TEMP[1].xy, IN[6].xyyy
  3: TEX TEMP[1].xyz, TEMP[1], SAMP[1], 2D
  4: MOV TEMP[2].xy, IN[1].xyyy
  5: TEX TEMP[2].xyz, TEMP[2], SAMP[3], 2D
  6: MAD TEMP[3].xyz, IMM[0].xxxx, TEMP[2].xyzz, IMM[0].yyyy
  7: DP3 TEMP[2].x, TEMP[3].xyzz, IN[3].xyzz
  8: DP3 TEMP[4].x, TEMP[3].xyzz, IN[4].xyzz
  9: MOV TEMP[2].y, TEMP[4].xxxx
 10: DP3 TEMP[4].x, TEMP[3].xyzz, IN[5].xyzz
 11: MOV TEMP[2].z, TEMP[4].xxxx
 12: ADD TEMP[4].xyz, -IN[2].xyzz, CONST[10].xyzz
 13: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[4].xyzz
 14: DP3 TEMP[6].x, TEMP[2].xyzz, TEMP[2].xyzz
 15: ADD TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx
 16: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[6].xxxx
 17: MAD TEMP[2].xyz, TEMP[5].xxxx, TEMP[2].xyzz, -TEMP[4].xyzz
 18: MOV TEMP[5].xy, IN[6].wzzz
 19: TEX TEMP[5].xyz, TEMP[5], SAMP[1], 2D
 20: MOV TEMP[6].xyz, TEMP[2].xyzz
 21: TEX TEMP[6].xyz, TEMP[6], SAMP[2], CUBE
 22: MOV TEMP[7].xy, IN[1].xyyy
 23: TEX TEMP[7].xyz, TEMP[7], SAMP[0], 2D
 24: DP3 TEMP[8].x, TEMP[3].xyzz, IMM[1].xyzz
 25: MOV_SAT TEMP[8].x, TEMP[8].xxxx
 26: DP3 TEMP[9].x, TEMP[3].xyzz, IMM[2].xyzz
 27: MOV_SAT TEMP[9].x, TEMP[9].xxxx
 28: MOV TEMP[8].y, TEMP[9].xxxx
 29: DP3 TEMP[9].x, TEMP[3].xyzz, IMM[3].xyzz
 30: MOV_SAT TEMP[9].x, TEMP[9].xxxx
 31: MOV TEMP[8].z, TEMP[9].xxxx
 32: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[8].xyzz
 33: MUL TEMP[3].xyz, TEMP[5].xyzz, TEMP[8].yyyy
 34: MAD TEMP[1].xyz, TEMP[8].xxxx, TEMP[1].xyzz, TEMP[3].xyzz
 35: DP3 TEMP[3].x, TEMP[8].xyzz, IMM[0].zzzz
 36: MAD TEMP[0].xyz, TEMP[8].zzzz, TEMP[0].xyzz, TEMP[1].xyzz
 37: RCP TEMP[3].x, TEMP[3].xxxx
 38: MUL TEMP[1].xyz, TEMP[3].xxxx, CONST[12].xyzz
 39: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xyzz
 40: MUL TEMP[4].xyz, TEMP[6].xyzz, CONST[30].zzzz
 41: MUL TEMP[4].xyz, TEMP[4].xyzz, CONST[0].xyzz
 42: MUL TEMP[2].xyz, TEMP[7].xyzz, IN[0].xyzz
 43: MAD TEMP[1].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
 44: MAD TEMP[2].xyz, TEMP[2].xyzz, TEMP[0].xyzz, TEMP[4].xyzz
 45: MIN TEMP[0].x, TEMP[1].xxxx, CONST[11].zzzz
 46: MOV_SAT TEMP[0].x, TEMP[0].xxxx
 47: MAD TEMP[4].xyz, TEMP[2].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 48: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx
 49: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[0].xxxx
 50: MAD TEMP[2].xyz, TEMP[2].xyzz, CONST[30].xxxx, TEMP[4].xyzz
 51: MUL TEMP[0].x, IN[2].wwww, CONST[29].wwww
 52: MOV TEMP[2].w, TEMP[0].xxxx
 53: MOV TEMP[10], TEMP[2]
 54: MOV OUT[0], TEMP[10]
 55: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 160)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 164)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 168)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 188)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 488)
  %40 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0
  %42 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
  %44 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %45 = load <32 x i8> addrspace(2)* %44, !tbaa !0
  %46 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0
  %48 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %49 = load <32 x i8> addrspace(2)* %48, !tbaa !0
  %50 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %53 = load <32 x i8> addrspace(2)* %52, !tbaa !0
  %54 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
  %56 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %57 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %59 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %60 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %61 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %62 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %63 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %64 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %65 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
  %66 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
  %67 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %68 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
  %69 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
  %70 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
  %71 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
  %72 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
  %73 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
  %74 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %6)
  %75 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %6)
  %76 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %3, <2 x i32> %6)
  %77 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %3, <2 x i32> %6)
  %78 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %3, <2 x i32> %6)
  %79 = call float @llvm.SI.fs.interp(i32 1, i32 7, i32 %3, <2 x i32> %6)
  %80 = bitcast float %78 to i32
  %81 = bitcast float %79 to i32
  %82 = insertelement <2 x i32> undef, i32 %80, i32 0
  %83 = insertelement <2 x i32> %82, i32 %81, i32 1
  %84 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %83, <32 x i8> %45, <16 x i8> %47, i32 2)
  %85 = extractelement <4 x float> %84, i32 0
  %86 = extractelement <4 x float> %84, i32 1
  %87 = extractelement <4 x float> %84, i32 2
  %88 = bitcast float %74 to i32
  %89 = bitcast float %75 to i32
  %90 = insertelement <2 x i32> undef, i32 %88, i32 0
  %91 = insertelement <2 x i32> %90, i32 %89, i32 1
  %92 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %91, <32 x i8> %45, <16 x i8> %47, i32 2)
  %93 = extractelement <4 x float> %92, i32 0
  %94 = extractelement <4 x float> %92, i32 1
  %95 = extractelement <4 x float> %92, i32 2
  %96 = bitcast float %59 to i32
  %97 = bitcast float %60 to i32
  %98 = insertelement <2 x i32> undef, i32 %96, i32 0
  %99 = insertelement <2 x i32> %98, i32 %97, i32 1
  %100 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %99, <32 x i8> %53, <16 x i8> %55, i32 2)
  %101 = extractelement <4 x float> %100, i32 0
  %102 = extractelement <4 x float> %100, i32 1
  %103 = extractelement <4 x float> %100, i32 2
  %104 = fmul float 2.000000e+00, %101
  %105 = fadd float %104, -1.000000e+00
  %106 = fmul float 2.000000e+00, %102
  %107 = fadd float %106, -1.000000e+00
  %108 = fmul float 2.000000e+00, %103
  %109 = fadd float %108, -1.000000e+00
  %110 = fmul float %105, %65
  %111 = fmul float %107, %66
  %112 = fadd float %111, %110
  %113 = fmul float %109, %67
  %114 = fadd float %112, %113
  %115 = fmul float %105, %68
  %116 = fmul float %107, %69
  %117 = fadd float %116, %115
  %118 = fmul float %109, %70
  %119 = fadd float %117, %118
  %120 = fmul float %105, %71
  %121 = fmul float %107, %72
  %122 = fadd float %121, %120
  %123 = fmul float %109, %73
  %124 = fadd float %122, %123
  %125 = fsub float -0.000000e+00, %61
  %126 = fadd float %125, %25
  %127 = fsub float -0.000000e+00, %62
  %128 = fadd float %127, %26
  %129 = fsub float -0.000000e+00, %63
  %130 = fadd float %129, %27
  %131 = fmul float %114, %126
  %132 = fmul float %119, %128
  %133 = fadd float %132, %131
  %134 = fmul float %124, %130
  %135 = fadd float %133, %134
  %136 = fmul float %114, %114
  %137 = fmul float %119, %119
  %138 = fadd float %137, %136
  %139 = fmul float %124, %124
  %140 = fadd float %138, %139
  %141 = fadd float %135, %135
  %142 = fmul float %126, %140
  %143 = fmul float %128, %140
  %144 = fmul float %130, %140
  %145 = fsub float -0.000000e+00, %142
  %146 = fmul float %141, %114
  %147 = fadd float %146, %145
  %148 = fsub float -0.000000e+00, %143
  %149 = fmul float %141, %119
  %150 = fadd float %149, %148
  %151 = fsub float -0.000000e+00, %144
  %152 = fmul float %141, %124
  %153 = fadd float %152, %151
  %154 = bitcast float %77 to i32
  %155 = bitcast float %76 to i32
  %156 = insertelement <2 x i32> undef, i32 %154, i32 0
  %157 = insertelement <2 x i32> %156, i32 %155, i32 1
  %158 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %157, <32 x i8> %45, <16 x i8> %47, i32 2)
  %159 = extractelement <4 x float> %158, i32 0
  %160 = extractelement <4 x float> %158, i32 1
  %161 = extractelement <4 x float> %158, i32 2
  %162 = insertelement <4 x float> undef, float %147, i32 0
  %163 = insertelement <4 x float> %162, float %150, i32 1
  %164 = insertelement <4 x float> %163, float %153, i32 2
  %165 = insertelement <4 x float> %164, float 0.000000e+00, i32 3
  %166 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %165)
  %167 = extractelement <4 x float> %166, i32 0
  %168 = extractelement <4 x float> %166, i32 1
  %169 = extractelement <4 x float> %166, i32 2
  %170 = extractelement <4 x float> %166, i32 3
  %171 = call float @fabs(float %169)
  %172 = fdiv float 1.000000e+00, %171
  %173 = fmul float %167, %172
  %174 = fadd float %173, 1.500000e+00
  %175 = fmul float %168, %172
  %176 = fadd float %175, 1.500000e+00
  %177 = bitcast float %176 to i32
  %178 = bitcast float %174 to i32
  %179 = bitcast float %170 to i32
  %180 = insertelement <4 x i32> undef, i32 %177, i32 0
  %181 = insertelement <4 x i32> %180, i32 %178, i32 1
  %182 = insertelement <4 x i32> %181, i32 %179, i32 2
  %183 = insertelement <4 x i32> %182, i32 undef, i32 3
  %184 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %183, <32 x i8> %49, <16 x i8> %51, i32 4)
  %185 = extractelement <4 x float> %184, i32 0
  %186 = extractelement <4 x float> %184, i32 1
  %187 = extractelement <4 x float> %184, i32 2
  %188 = bitcast float %59 to i32
  %189 = bitcast float %60 to i32
  %190 = insertelement <2 x i32> undef, i32 %188, i32 0
  %191 = insertelement <2 x i32> %190, i32 %189, i32 1
  %192 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %191, <32 x i8> %41, <16 x i8> %43, i32 2)
  %193 = extractelement <4 x float> %192, i32 0
  %194 = extractelement <4 x float> %192, i32 1
  %195 = extractelement <4 x float> %192, i32 2
  %196 = fmul float %105, 0x3FEA20BD80000000
  %197 = fmul float %107, 0.000000e+00
  %198 = fadd float %197, %196
  %199 = fmul float %109, 0x3FE279A740000000
  %200 = fadd float %198, %199
  %201 = call float @llvm.AMDIL.clamp.(float %200, float 0.000000e+00, float 1.000000e+00)
  %202 = fmul float %105, 0xBFDA20BDA0000000
  %203 = fmul float %107, 0x3FE6A09E60000000
  %204 = fadd float %203, %202
  %205 = fmul float %109, 0x3FE279A740000000
  %206 = fadd float %204, %205
  %207 = call float @llvm.AMDIL.clamp.(float %206, float 0.000000e+00, float 1.000000e+00)
  %208 = fmul float %105, 0xBFDA20BD20000000
  %209 = fmul float %107, 0xBFE6A09E80000000
  %210 = fadd float %209, %208
  %211 = fmul float %109, 0x3FE279A740000000
  %212 = fadd float %210, %211
  %213 = call float @llvm.AMDIL.clamp.(float %212, float 0.000000e+00, float 1.000000e+00)
  %214 = fmul float %201, %201
  %215 = fmul float %207, %207
  %216 = fmul float %213, %213
  %217 = fmul float %159, %215
  %218 = fmul float %160, %215
  %219 = fmul float %161, %215
  %220 = fmul float %214, %93
  %221 = fadd float %220, %217
  %222 = fmul float %214, %94
  %223 = fadd float %222, %218
  %224 = fmul float %214, %95
  %225 = fadd float %224, %219
  %226 = fmul float %214, 1.000000e+00
  %227 = fmul float %215, 1.000000e+00
  %228 = fadd float %227, %226
  %229 = fmul float %216, 1.000000e+00
  %230 = fadd float %228, %229
  %231 = fmul float %216, %85
  %232 = fadd float %231, %221
  %233 = fmul float %216, %86
  %234 = fadd float %233, %223
  %235 = fmul float %216, %87
  %236 = fadd float %235, %225
  %237 = fdiv float 1.000000e+00, %230
  %238 = fmul float %237, %31
  %239 = fmul float %237, %32
  %240 = fmul float %237, %33
  %241 = fmul float %232, %238
  %242 = fmul float %234, %239
  %243 = fmul float %236, %240
  %244 = fmul float %185, %39
  %245 = fmul float %186, %39
  %246 = fmul float %187, %39
  %247 = fmul float %244, %22
  %248 = fmul float %245, %23
  %249 = fmul float %246, %24
  %250 = fmul float %193, %56
  %251 = fmul float %194, %57
  %252 = fmul float %195, %58
  %253 = fsub float -0.000000e+00, %28
  %254 = fmul float %64, %30
  %255 = fadd float %254, %253
  %256 = fmul float %250, %241
  %257 = fadd float %256, %247
  %258 = fmul float %251, %242
  %259 = fadd float %258, %248
  %260 = fmul float %252, %243
  %261 = fadd float %260, %249
  %262 = fcmp uge float %255, %29
  %263 = select i1 %262, float %29, float %255
  %264 = call float @llvm.AMDIL.clamp.(float %263, float 0.000000e+00, float 1.000000e+00)
  %265 = fsub float -0.000000e+00, %38
  %266 = fmul float %257, %265
  %267 = fadd float %266, %34
  %268 = fsub float -0.000000e+00, %38
  %269 = fmul float %259, %268
  %270 = fadd float %269, %35
  %271 = fsub float -0.000000e+00, %38
  %272 = fmul float %261, %271
  %273 = fadd float %272, %36
  %274 = fmul float %264, %264
  %275 = fmul float %267, %274
  %276 = fmul float %270, %274
  %277 = fmul float %273, %274
  %278 = fmul float %257, %38
  %279 = fadd float %278, %275
  %280 = fmul float %259, %38
  %281 = fadd float %280, %276
  %282 = fmul float %261, %38
  %283 = fadd float %282, %277
  %284 = fmul float %64, %37
  %285 = call i32 @llvm.SI.packf16(float %279, float %281)
  %286 = bitcast i32 %285 to float
  %287 = call i32 @llvm.SI.packf16(float %283, float %284)
  %288 = bitcast i32 %287 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %286, float %288, float %286, float %288)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 12; mem:LD16[%54](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 24; mem:LD32[%52](tbaa=!"const")
	S_WAITCNT 127
	%VGPR8_VGPR9_VGPR10<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_ADD_F32_e32 %VGPR8, %VGPR8, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR6, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e32 %VGPR9, %VGPR9, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR7, %VGPR12<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e32 %VGPR10, %VGPR10, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10<imp-use,kill>
	%VGPR8<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR8, %VGPR9<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR6, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR7, %VGPR11<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR8, %VGPR11<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR10, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR9, %VGPR9, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR6, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR7, %VGPR13<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR8, %VGPR13<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 41
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR15, %VGPR12, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 40
	S_WAITCNT 127
	%VGPR14<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR10, %VGPR14, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR9, %VGPR15<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 42
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR11, %VGPR15, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e32 %VGPR16<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR16, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %VGPR9<kill>, %VGPR13<kill>, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR16, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR20<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR10<def> = V_CUBESC_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR9<def> = V_CUBETC_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR11<def> = V_CUBEMA_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR12<def> = V_CUBEID_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR17<def> = V_ADD_F32_e64 %VGPR11, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_RCP_F32_e32 %VGPR17<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR9, %VGPR17, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR10<def> = V_MAD_F32 %VGPR10, %VGPR17<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR13<def> = KILL %VGPR13<undef>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%50](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%48](tbaa=!"const")
	S_WAITCNT 127
	%VGPR9_VGPR10_VGPR11<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR10_VGPR11_VGPR12_VGPR13, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 122
	S_WAITCNT 112
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0, %VGPR10, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR20<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 -4.082483e-01, %VGPR6, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 7.071068e-01, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR7, %VGPR13<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_MOV_B32_e32 5.773503e-01, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR8, %VGPR21, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 %VGPR12<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR24, %VGPR24, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR2, 2, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<tied0>, %VGPR3, 2, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR2, 3, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<tied0>, %VGPR3, 3, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%46](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%44](tbaa=!"const")
	S_WAITCNT 127
	%VGPR13_VGPR14_VGPR15<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR22<def> = V_MUL_F32_e32 %VGPR14, %VGPR12, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 8.164966e-01, %VGPR6, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR7, 0.000000e+00, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR8, %VGPR21, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e64 %VGPR16<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR18<def> = V_INTERP_P1_F32 %VGPR2, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR17_VGPR18<imp-def>
	%VGPR18<def,tied1> = V_INTERP_P2_F32 %VGPR18<tied0>, %VGPR3, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR17_VGPR18<imp-use,kill>, %VGPR17_VGPR18<imp-def>
	%VGPR17<def> = V_INTERP_P1_F32 %VGPR2, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR17_VGPR18<imp-use,kill>, %VGPR17_VGPR18<imp-def>
	%VGPR17<def,tied1> = V_INTERP_P2_F32 %VGPR17<tied0>, %VGPR3, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR17_VGPR18<imp-use,kill>, %VGPR17_VGPR18<imp-def>
	%VGPR17_VGPR18_VGPR19<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR17_VGPR18<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR25<def> = V_MAD_F32 %VGPR16, %VGPR18, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 -4.082482e-01, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MOV_B32_e32 -7.071068e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR7<kill>, %VGPR22<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR8<kill>, %VGPR21<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR6<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR7, %VGPR7, %EXEC<imp-use>
	%VGPR22<def> = V_INTERP_P1_F32 %VGPR2, 1, 7, %M0<kill>, %EXEC<imp-use>, %VGPR21_VGPR22<imp-def>
	%VGPR22<def,tied1> = V_INTERP_P2_F32 %VGPR22<tied0>, %VGPR3, 1, 7, %M0<kill>, %EXEC<imp-use>, %VGPR21_VGPR22<imp-use,kill>, %VGPR21_VGPR22<imp-def>
	%VGPR21<def> = V_INTERP_P1_F32 %VGPR2, 0, 7, %M0<kill>, %EXEC<imp-use>, %VGPR21_VGPR22<imp-use,kill>, %VGPR21_VGPR22<imp-def>
	%VGPR21<def,tied1> = V_INTERP_P2_F32 %VGPR21<tied0>, %VGPR3, 0, 7, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR21_VGPR22<imp-use,kill>, %VGPR21_VGPR22<imp-def>
	%VGPR21_VGPR22_VGPR23<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR21_VGPR22<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %VGPR22, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR24<kill>, %VGPR24, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR7<kill>, %VGPR7, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_RCP_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%42](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%40](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MUL_F32_e32 %VGPR3, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR5<kill>, %VGPR8<kill>, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 120
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR1, %VGPR20, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 117
	S_WAITCNT 127
	%VGPR24<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR8<def> = V_SUBREV_F32_e32 %SGPR2<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR8, %SGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR25<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR20<kill>, %SGPR1, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR0, %VGPR9, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR24<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR13, %VGPR12, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR16, %VGPR17, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR6, %VGPR21, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR26<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR26<def,tied1> = V_INTERP_P2_F32 %VGPR26<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR2, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR26<kill>, %VGPR25<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %SGPR1, %VGPR24, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 116
	S_WAITCNT 127
	%VGPR25<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR24<kill>, %SGPR1, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR24<kill>, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR11, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR15, %VGPR12<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15<imp-use,kill>
	%VGPR10<def> = V_MAD_F32 %VGPR16<kill>, %VGPR19, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19<imp-use,kill>
	%VGPR6<def> = V_MAD_F32 %VGPR6<kill>, %VGPR23, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR4, %VGPR7<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4<imp-use,kill>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %VGPR6<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR1, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 118
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR1<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 119
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR20<kill>, %VGPR0<kill>, %VGPR20, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140500
c8150501
c8100400
c8110401
c084030c
c0c60518
bf8c007f
f0800700
00430804
bf8c0770
060c1108
060c0cf3
c81c1000
c81d1001
10160f06
060e1309
060e0ef3
c8301100
c8311101
d282000b
042e1907
0610150a
061010f3
c8241200
c8251201
d2820009
042e1308
c8280c00
c8290c01
10141506
c82c0d00
c82d0d01
d282000a
042a1707
c82c0e00
c82d0e01
d282000a
042a1708
1016150a
d282000c
042e1309
c82c1400
c82d1401
10161706
c8341500
c8351501
d282000b
042e1b07
c8341600
c8351601
d282000b
042e1b08
d282000c
0432170b
c8340900
c8350901
c0840100
bf8c007f
c2000929
bf8c007f
081e1a00
101a190f
c8380800
c8390801
c2000928
bf8c007f
081c1c00
10201d0a
d2820010
04421f09
c83c0a00
c83d0a01
c200092a
bf8c007f
081e1e00
d2820010
04421f0b
06202110
10121310
08241b09
1012190e
10141510
0822130a
1012190f
10141710
0826130a
7e280280
d28a000a
044e2511
d28c0009
044e2511
d28e000b
044e2511
d288000c
044e2511
d2060111
0201010b
7e225511
7e2402ff
3fc00000
d282000b
044a2309
d282000a
044a230a
c0860308
c0c80510
bf8c007f
f0800700
0064090a
c200097a
bf8c0070
10181400
c2008901
bf8c007f
10281801
10180cff
bed105ed
7e1a02ff
3f3504f3
d282000c
04321b07
7e2a02ff
3f13cd3a
d282000c
04322b08
d2060818
0201010c
10183118
c8381a02
c8391a03
c8341b02
c8351b03
c0860304
c0c80508
bf8c007f
f0800700
00640d0d
bf8c0770
102c190e
10200cff
3f5105ec
d2820010
04410107
d2820010
04422b08
d2060810
02010110
10202110
c8481902
c8491903
c8441802
c8451803
f0800700
00641111
bf8c0770
d2820019
045a2510
100c0cff
bed105e9
7e2c02ff
bf3504f4
d2820006
041a2d07
d2820006
041a2b08
d2060807
02010106
100c0f07
c8581d02
c8591d03
c8541c02
c8551c03
f0800700
00641515
bf8c0770
d2820002
04662d06
d2820003
04423118
d2820003
040e0f07
7e0e5503
c2008931
bf8c007f
10060e01
10100702
c0860300
c0c80500
bf8c007f
f0800700
00640204
c8140100
c8150101
bf8c0770
100a0b03
d2820014
04521105
c2008978
bf8c007f
100a2801
c2010975
bf8c007f
08300a02
c8140b00
c8150b01
c201092f
bf8c007f
10100a02
c201092c
bf8c007f
0a101002
c201092e
bf8c007f
d00c0004
02000508
7e320202
d2000008
00123308
d2060808
02010108
10101108
10301118
d2820014
04600314
10301200
c2010900
bf8c007f
10303002
1032190d
d2820019
04662310
d2820019
04662b06
c2010930
bf8c007f
10340e02
10323519
c8680000
c8690001
10343502
d2820018
0462331a
10323001
c2010974
bf8c007f
08323202
10321119
d2820018
04640318
5e282918
10121600
c2000902
bf8c007f
10121200
1014190f
d282000a
042a2710
d2820006
042a2f06
c2000932
bf8c007f
100e0e00
100c0f06
c81c0200
c81d0201
10000f04
d2820000
04260d00
10020001
c2000976
bf8c007f
08020200
10021101
d2820000
04040300
c2000977
bf8c007f
10020a00
5e000300
f8001c0f
00140014
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL OUT[7], GENERIC[23]
DCL OUT[8], GENERIC[24]
DCL OUT[9], GENERIC[25]
DCL CONST[0..51]
DCL TEMP[0..12], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[6]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: DP4 TEMP[5].x, TEMP[0], CONST[7]
 12: MOV TEMP[2].w, TEMP[5].xxxx
 13: DP4 TEMP[6].x, TEMP[0], CONST[12]
 14: DP3 TEMP[7].x, IN[1].xyzz, CONST[48].xyzz
 15: MOV TEMP[7].z, TEMP[7].xxxx
 16: DP3 TEMP[8].x, IN[1].xyzz, CONST[49].xyzz
 17: MOV TEMP[8].z, TEMP[8].xxxx
 18: DP3 TEMP[9].x, IN[1].xyzz, CONST[50].xyzz
 19: MOV TEMP[9].z, TEMP[9].xxxx
 20: DP3 TEMP[7].x, IN[5].xyzz, CONST[48].xyzz
 21: DP3 TEMP[8].x, IN[5].xyzz, CONST[49].xyzz
 22: DP3 TEMP[9].x, IN[5].xyzz, CONST[50].xyzz
 23: DP3 TEMP[10].x, IN[6].xyzz, CONST[48].xyzz
 24: MOV TEMP[7].y, TEMP[10].xxxx
 25: ADD TEMP[0].xy, IN[4].xyyy, IN[3].xyyy
 26: DP3 TEMP[10].x, IN[6].xyzz, CONST[49].xyzz
 27: MOV TEMP[8].y, TEMP[10].xxxx
 28: ADD TEMP[10].xy, TEMP[0].yxxx, IN[4].yxxx
 29: MOV TEMP[0].zw, TEMP[10].yyxy
 30: DP3 TEMP[11].x, IN[6].xyzz, CONST[50].xyzz
 31: MOV TEMP[9].y, TEMP[11].xxxx
 32: MOV TEMP[0], TEMP[0]
 33: ADD TEMP[10].xy, TEMP[10].yxxx, IN[4].xyyy
 34: MOV TEMP[1].w, TEMP[6].xxxx
 35: MOV TEMP[6].xy, IN[2].xyxx
 36: MOV TEMP[10].zw, IN[2].yyxy
 37: MAD TEMP[11], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 38: MOV TEMP[12], TEMP[2]
 39: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[5].xxxx
 40: MOV TEMP[2].z, TEMP[4].xxxx
 41: MOV TEMP[2].y, -TEMP[3].xxxx
 42: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[5].xxxx, TEMP[2].xyyy
 43: MOV OUT[3], TEMP[6]
 44: MOV OUT[8], TEMP[0]
 45: MOV OUT[9], TEMP[10]
 46: MOV OUT[0], TEMP[2]
 47: MOV OUT[4], TEMP[1]
 48: MOV OUT[2], TEMP[12]
 49: MOV OUT[5], TEMP[7]
 50: MOV OUT[6], TEMP[8]
 51: MOV_SAT OUT[1], TEMP[11]
 52: MOV OUT[7], TEMP[9]
 53: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 764)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 776)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 792)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 800)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 804)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 808)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 812)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 816)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 820)
  %49 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0
  %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %5)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = extractelement <4 x float> %51, i32 1
  %54 = extractelement <4 x float> %51, i32 2
  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = extractelement <4 x float> %57, i32 2
  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
  %64 = extractelement <4 x float> %63, i32 0
  %65 = extractelement <4 x float> %63, i32 1
  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
  %69 = extractelement <4 x float> %68, i32 0
  %70 = extractelement <4 x float> %68, i32 1
  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
  %74 = extractelement <4 x float> %73, i32 0
  %75 = extractelement <4 x float> %73, i32 1
  %76 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
  %77 = load <16 x i8> addrspace(2)* %76, !tbaa !0
  %78 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %77, i32 0, i32 %5)
  %79 = extractelement <4 x float> %78, i32 0
  %80 = extractelement <4 x float> %78, i32 1
  %81 = extractelement <4 x float> %78, i32 2
  %82 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
  %83 = load <16 x i8> addrspace(2)* %82, !tbaa !0
  %84 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %83, i32 0, i32 %5)
  %85 = extractelement <4 x float> %84, i32 0
  %86 = extractelement <4 x float> %84, i32 1
  %87 = extractelement <4 x float> %84, i32 2
  %88 = fmul float %52, %12
  %89 = fadd float %88, %11
  %90 = fmul float %53, %12
  %91 = fadd float %90, %11
  %92 = fmul float %54, %12
  %93 = fadd float %92, %11
  %94 = fmul float %52, %11
  %95 = fadd float %94, %12
  %96 = fmul float %89, %35
  %97 = fmul float %91, %36
  %98 = fadd float %96, %97
  %99 = fmul float %93, %37
  %100 = fadd float %98, %99
  %101 = fmul float %95, %38
  %102 = fadd float %100, %101
  %103 = fmul float %89, %39
  %104 = fmul float %91, %40
  %105 = fadd float %103, %104
  %106 = fmul float %93, %41
  %107 = fadd float %105, %106
  %108 = fmul float %95, %42
  %109 = fadd float %107, %108
  %110 = fmul float %89, %43
  %111 = fmul float %91, %44
  %112 = fadd float %110, %111
  %113 = fmul float %93, %45
  %114 = fadd float %112, %113
  %115 = fmul float %95, %46
  %116 = fadd float %114, %115
  %117 = fmul float %89, %14
  %118 = fmul float %91, %15
  %119 = fadd float %117, %118
  %120 = fmul float %93, %16
  %121 = fadd float %119, %120
  %122 = fmul float %95, %17
  %123 = fadd float %121, %122
  %124 = fmul float %89, %18
  %125 = fmul float %91, %19
  %126 = fadd float %124, %125
  %127 = fmul float %93, %20
  %128 = fadd float %126, %127
  %129 = fmul float %95, %21
  %130 = fadd float %128, %129
  %131 = fmul float %89, %22
  %132 = fmul float %91, %23
  %133 = fadd float %131, %132
  %134 = fmul float %93, %24
  %135 = fadd float %133, %134
  %136 = fmul float %95, %25
  %137 = fadd float %135, %136
  %138 = fmul float %89, %26
  %139 = fmul float %91, %27
  %140 = fadd float %138, %139
  %141 = fmul float %93, %28
  %142 = fadd float %140, %141
  %143 = fmul float %95, %29
  %144 = fadd float %142, %143
  %145 = fmul float %89, %30
  %146 = fmul float %91, %31
  %147 = fadd float %145, %146
  %148 = fmul float %93, %32
  %149 = fadd float %147, %148
  %150 = fmul float %95, %33
  %151 = fadd float %149, %150
  %152 = fmul float %58, %35
  %153 = fmul float %59, %36
  %154 = fadd float %153, %152
  %155 = fmul float %60, %37
  %156 = fadd float %154, %155
  %157 = fmul float %58, %39
  %158 = fmul float %59, %40
  %159 = fadd float %158, %157
  %160 = fmul float %60, %41
  %161 = fadd float %159, %160
  %162 = fmul float %58, %43
  %163 = fmul float %59, %44
  %164 = fadd float %163, %162
  %165 = fmul float %60, %45
  %166 = fadd float %164, %165
  %167 = fmul float %79, %35
  %168 = fmul float %80, %36
  %169 = fadd float %168, %167
  %170 = fmul float %81, %37
  %171 = fadd float %169, %170
  %172 = fmul float %79, %39
  %173 = fmul float %80, %40
  %174 = fadd float %173, %172
  %175 = fmul float %81, %41
  %176 = fadd float %174, %175
  %177 = fmul float %79, %43
  %178 = fmul float %80, %44
  %179 = fadd float %178, %177
  %180 = fmul float %81, %45
  %181 = fadd float %179, %180
  %182 = fmul float %85, %35
  %183 = fmul float %86, %36
  %184 = fadd float %183, %182
  %185 = fmul float %87, %37
  %186 = fadd float %184, %185
  %187 = fadd float %74, %69
  %188 = fadd float %75, %70
  %189 = fmul float %85, %39
  %190 = fmul float %86, %40
  %191 = fadd float %190, %189
  %192 = fmul float %87, %41
  %193 = fadd float %191, %192
  %194 = fadd float %188, %75
  %195 = fadd float %187, %74
  %196 = fmul float %85, %43
  %197 = fmul float %86, %44
  %198 = fadd float %197, %196
  %199 = fmul float %87, %45
  %200 = fadd float %198, %199
  %201 = fadd float %195, %74
  %202 = fadd float %194, %75
  %203 = fmul float %34, %11
  %204 = fadd float %203, %12
  %205 = fmul float %34, %11
  %206 = fadd float %205, %12
  %207 = fmul float %34, %11
  %208 = fadd float %207, %12
  %209 = fmul float %34, %12
  %210 = fadd float %209, %11
  %211 = fsub float -0.000000e+00, %144
  %212 = fmul float %137, %13
  %213 = fadd float %212, %211
  %214 = fsub float -0.000000e+00, %130
  %215 = fmul float %47, %144
  %216 = fadd float %215, %123
  %217 = fmul float %48, %144
  %218 = fadd float %217, %214
  %219 = call float @llvm.AMDIL.clamp.(float %204, float 0.000000e+00, float 1.000000e+00)
  %220 = call float @llvm.AMDIL.clamp.(float %206, float 0.000000e+00, float 1.000000e+00)
  %221 = call float @llvm.AMDIL.clamp.(float %208, float 0.000000e+00, float 1.000000e+00)
  %222 = call float @llvm.AMDIL.clamp.(float %210, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %219, float %220, float %221, float %222)
  %223 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %224 = load <16 x i8> addrspace(2)* %223, !tbaa !0
  %225 = call float @llvm.SI.load.const(<16 x i8> %224, i32 0)
  %226 = fmul float %225, %123
  %227 = call float @llvm.SI.load.const(<16 x i8> %224, i32 4)
  %228 = fmul float %227, %130
  %229 = fadd float %226, %228
  %230 = call float @llvm.SI.load.const(<16 x i8> %224, i32 8)
  %231 = fmul float %230, %137
  %232 = fadd float %229, %231
  %233 = call float @llvm.SI.load.const(<16 x i8> %224, i32 12)
  %234 = fmul float %233, %144
  %235 = fadd float %232, %234
  %236 = call float @llvm.SI.load.const(<16 x i8> %224, i32 16)
  %237 = fmul float %236, %123
  %238 = call float @llvm.SI.load.const(<16 x i8> %224, i32 20)
  %239 = fmul float %238, %130
  %240 = fadd float %237, %239
  %241 = call float @llvm.SI.load.const(<16 x i8> %224, i32 24)
  %242 = fmul float %241, %137
  %243 = fadd float %240, %242
  %244 = call float @llvm.SI.load.const(<16 x i8> %224, i32 28)
  %245 = fmul float %244, %144
  %246 = fadd float %243, %245
  %247 = call float @llvm.SI.load.const(<16 x i8> %224, i32 32)
  %248 = fmul float %247, %123
  %249 = call float @llvm.SI.load.const(<16 x i8> %224, i32 36)
  %250 = fmul float %249, %130
  %251 = fadd float %248, %250
  %252 = call float @llvm.SI.load.const(<16 x i8> %224, i32 40)
  %253 = fmul float %252, %137
  %254 = fadd float %251, %253
  %255 = call float @llvm.SI.load.const(<16 x i8> %224, i32 44)
  %256 = fmul float %255, %144
  %257 = fadd float %254, %256
  %258 = call float @llvm.SI.load.const(<16 x i8> %224, i32 48)
  %259 = fmul float %258, %123
  %260 = call float @llvm.SI.load.const(<16 x i8> %224, i32 52)
  %261 = fmul float %260, %130
  %262 = fadd float %259, %261
  %263 = call float @llvm.SI.load.const(<16 x i8> %224, i32 56)
  %264 = fmul float %263, %137
  %265 = fadd float %262, %264
  %266 = call float @llvm.SI.load.const(<16 x i8> %224, i32 60)
  %267 = fmul float %266, %144
  %268 = fadd float %265, %267
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %235, float %246, float %257, float %268)
  %269 = call float @llvm.SI.load.const(<16 x i8> %224, i32 64)
  %270 = fmul float %269, %123
  %271 = call float @llvm.SI.load.const(<16 x i8> %224, i32 68)
  %272 = fmul float %271, %130
  %273 = fadd float %270, %272
  %274 = call float @llvm.SI.load.const(<16 x i8> %224, i32 72)
  %275 = fmul float %274, %137
  %276 = fadd float %273, %275
  %277 = call float @llvm.SI.load.const(<16 x i8> %224, i32 76)
  %278 = fmul float %277, %144
  %279 = fadd float %276, %278
  %280 = call float @llvm.SI.load.const(<16 x i8> %224, i32 80)
  %281 = fmul float %280, %123
  %282 = call float @llvm.SI.load.const(<16 x i8> %224, i32 84)
  %283 = fmul float %282, %130
  %284 = fadd float %281, %283
  %285 = call float @llvm.SI.load.const(<16 x i8> %224, i32 88)
  %286 = fmul float %285, %137
  %287 = fadd float %284, %286
  %288 = call float @llvm.SI.load.const(<16 x i8> %224, i32 92)
  %289 = fmul float %288, %144
  %290 = fadd float %287, %289
  %291 = call float @llvm.SI.load.const(<16 x i8> %224, i32 96)
  %292 = fmul float %291, %123
  %293 = call float @llvm.SI.load.const(<16 x i8> %224, i32 100)
  %294 = fmul float %293, %130
  %295 = fadd float %292, %294
  %296 = call float @llvm.SI.load.const(<16 x i8> %224, i32 104)
  %297 = fmul float %296, %137
  %298 = fadd float %295, %297
  %299 = call float @llvm.SI.load.const(<16 x i8> %224, i32 108)
  %300 = fmul float %299, %144
  %301 = fadd float %298, %300
  %302 = call float @llvm.SI.load.const(<16 x i8> %224, i32 112)
  %303 = fmul float %302, %123
  %304 = call float @llvm.SI.load.const(<16 x i8> %224, i32 116)
  %305 = fmul float %304, %130
  %306 = fadd float %303, %305
  %307 = call float @llvm.SI.load.const(<16 x i8> %224, i32 120)
  %308 = fmul float %307, %137
  %309 = fadd float %306, %308
  %310 = call float @llvm.SI.load.const(<16 x i8> %224, i32 124)
  %311 = fmul float %310, %144
  %312 = fadd float %309, %311
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %279, float %290, float %301, float %312)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %64, float %65, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %102, float %109, float %116, float %151)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %171, float %186, float %156, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %176, float %193, float %161, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %181, float %200, float %166, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %187, float %188, float %194, float %195)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %201, float %202, float %64, float %65)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %216, float %218, float %213, float %144)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 191
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR4, %VGPR1, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%49](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR3, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR9, %SGPR3, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR10, %SGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR3<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 19
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 23
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%223](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 27
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 30
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 31
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 19
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%61](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 15
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 51
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 201
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR0, %VGPR6, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 200
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR5, %SGPR1, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 202
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR7, %SGPR2, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 203
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR8, %SGPR3<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 127
	%VGPR16<def> = V_MUL_F32_e32 %SGPR3, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR5, %SGPR4, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 198
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR7, %SGPR5, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 199
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR8, %SGPR12<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR12, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR5<kill>, %SGPR14, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 194
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR7<kill>, %SGPR13, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 195
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR8<kill>, %SGPR15<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR5<kill>, %VGPR16<kill>, %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%55](tbaa=!"const")
	S_WAITCNT 15
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR14<def> = V_MUL_F32_e32 %SGPR14, %VGPR5, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR6, %SGPR12, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR7, %SGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 24; mem:LD16[%82](tbaa=!"const")
	S_WAITCNT 127
	%VGPR14_VGPR15_VGPR16_VGPR17<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %SGPR14, %VGPR14, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR15, %SGPR12, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR16, %SGPR13, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%76](tbaa=!"const")
	S_WAITCNT 127
	%VGPR18_VGPR19_VGPR20_VGPR21<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR24<def> = V_MUL_F32_e32 %SGPR14<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR19, %SGPR12<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR20, %SGPR13<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR24<kill>, %VGPR23<kill>, %VGPR22<kill>, %VGPR13, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR22<def> = V_MUL_F32_e32 %SGPR4, %VGPR5, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR6, %SGPR3, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR7, %SGPR5, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %SGPR4, %VGPR14, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR15, %SGPR3, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR16, %SGPR5, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR19, %SGPR3<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR20, %SGPR5<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 36, 0, 0, 0, %VGPR24<kill>, %VGPR23<kill>, %VGPR22<kill>, %VGPR13, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR22<def> = V_MUL_F32_e32 %SGPR1, %VGPR5, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR6, %SGPR0, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR7, %SGPR2, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR1, %VGPR14, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR15, %SGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR16, %SGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR19, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR20, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>
	EXP 15, 37, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%66](tbaa=!"const")
	S_WAITCNT 15
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 16; mem:LD16[%71](tbaa=!"const")
	S_WAITCNT 112
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR17<def> = V_ADD_F32_e32 %VGPR5, %VGPR13, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR17, %VGPR5, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e32 %VGPR6, %VGPR14, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR13, %VGPR6, %EXEC<imp-use>
	EXP 15, 38, 0, 0, 0, %VGPR17<kill>, %VGPR13<kill>, %VGPR14, %VGPR0, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR13<def> = V_ADD_F32_e32 %VGPR14<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR0<kill>, %VGPR5, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	EXP 15, 39, 0, 0, 0, %VGPR0<kill>, %VGPR13<kill>, %VGPR9, %VGPR10, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 204
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 205
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840100
bf8c007f
c20209bf
c2010900
bf8c007f
7e040202
c2018901
bf8c007f
7e020203
d2820003
040a0204
d2060803
02010103
d2820004
04060404
d2060804
02010104
f800020f
03040404
c0860700
bf8c000f
e00c2000
80030800
bf8c0770
d2820005
04080708
d2820006
04080709
c2020911
bf8c007f
10060c04
c2020910
bf8c007f
d2820003
040c0905
d2820007
0408070a
c2018912
bf8c007f
d2820002
040c0707
d2820008
04040508
c2010913
bf8c007f
d2820001
04080508
c2010915
bf8c007f
10040c02
c2010914
bf8c007f
d2820002
04080505
c2010916
bf8c007f
d2820002
04080507
c2010917
bf8c007f
d2820002
04080508
c0800104
bf8c007f
c202010d
bf8c007f
10060404
c202010c
bf8c007f
d2820004
040e0204
c2020919
bf8c007f
10060c04
c2020918
bf8c007f
d2820003
040c0905
c202091a
bf8c007f
d2820003
040c0907
c202091b
bf8c007f
d2820003
040c0908
c202010e
bf8c007f
d2820009
04120604
c202091d
bf8c007f
10080c04
c202091c
bf8c007f
d2820004
04100905
c202091e
bf8c007f
d2820004
04100907
c202091f
bf8c007f
d2820004
04100908
c202010f
bf8c007f
d2820009
04260804
c2020109
bf8c007f
10140404
c2020108
bf8c007f
d282000a
042a0204
c202010a
bf8c007f
d282000a
042a0604
c202010b
bf8c007f
d282000a
042a0804
c2020105
bf8c007f
10160404
c2020104
bf8c007f
d282000b
042e0204
c2020106
bf8c007f
d282000b
042e0604
c2020107
bf8c007f
d282000b
042e0804
c2020101
bf8c007f
10180404
c2020100
bf8c007f
d282000c
04320204
c2020102
bf8c007f
d282000c
04320604
c2020103
bf8c007f
d282000c
04320804
f80000ef
090a0b0c
c202011d
bf8c000f
10120404
c202011c
bf8c007f
d2820009
04260204
c202011e
bf8c007f
d2820009
04260604
c202011f
bf8c007f
d2820009
04260804
c2020119
bf8c007f
10140404
c2020118
bf8c007f
d282000a
042a0204
c202011a
bf8c007f
d282000a
042a0604
c202011b
bf8c007f
d282000a
042a0804
c2020115
bf8c007f
10160404
c2020114
bf8c007f
d282000b
042e0204
c2020116
bf8c007f
d282000b
042e0604
c2020117
bf8c007f
d282000b
042e0804
c2020111
bf8c007f
10180404
c2020110
bf8c007f
d282000c
04320204
c2020112
bf8c007f
d282000c
04320604
c2000113
bf8c007f
d282000c
04320800
f80000ff
090a0b0c
c0800708
bf8c000f
e00c2000
80000900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c2000931
bf8c000f
101c0c00
c2000930
bf8c007f
d282000e
04380105
c2000932
bf8c007f
d282000e
04380107
c2000933
bf8c007f
d282000e
04380108
c20009c9
bf8c007f
101e0c00
c20089c8
bf8c007f
d282000f
043c0305
c20109ca
bf8c007f
d282000f
043c0507
c20189cb
bf8c007f
d282000f
043c0708
c20189c5
bf8c007f
10200c03
c20209c4
bf8c007f
d2820010
04400905
c20289c6
bf8c007f
d2820010
04400b07
c20609c7
bf8c007f
d2820010
04401908
c20609c1
bf8c007f
100c0c0c
c20709c0
bf8c007f
d2820005
04181d05
c20689c2
bf8c007f
d2820005
04141b07
c20789c3
bf8c007f
d2820005
04141f08
f800022f
0e0f1005
c0880704
bf8c000f
e00c2000
80040500
bf8c0770
101c0a0e
d282000e
04381906
d2820016
04381b07
c0880718
bf8c007f
e00c2000
80040e00
bf8c0770
10241c0e
d2820012
0448190f
d2820017
04481b10
c0880714
bf8c007f
e00c2000
80041200
bf8c0770
1030240e
d2820018
04601913
d2820018
04601b14
f800023f
0d161718
bf8c070f
102c0a04
d2820016
04580706
d2820016
04580b07
102e1c04
d2820017
045c070f
d2820017
045c0b10
10302404
d2820018
04600713
d2820018
04600b14
f800024f
0d161718
bf8c070f
102c0a01
d2820016
04580106
d2820005
04580507
100c1c01
d2820006
0418010f
d2820006
04180510
100e2401
d2820007
041c0113
d2820007
041c0514
f800025f
0d050607
c080070c
bf8c000f
e00c2000
80000d00
c0800710
bf8c0070
e00c2000
80000500
bf8c0770
06221b05
06000b11
061a1d06
061c0d0d
f800026f
000e0d11
bf8c070f
061a0d0e
06000b00
f800027f
0a090d00
c20009cc
bf8c000f
d2820000
04060800
c2000902
bf8c007f
10020600
08020901
c20009cd
bf8c007f
10060800
08040503
f80008cf
04010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE
DCL IN[4], GENERIC[22], PERSPECTIVE
DCL IN[5], GENERIC[23], PERSPECTIVE
DCL IN[6], GENERIC[24], PERSPECTIVE, CENTROID
DCL IN[7], GENERIC[25], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..30]
DCL TEMP[0..8], LOCAL
DCL TEMP[9], ARRAY(1), LOCAL
IMM[0] FLT32 {   -0.4082,     0.7071,     0.5774,    -0.4082}
IMM[1] FLT32 {    0.8165,     0.0000,     0.5774,    -0.4082}
IMM[2] FLT32 {   -0.4082,    -0.7071,     0.5774,     0.0000}
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[3], 2D
  2: ADD TEMP[1].xyz, -IN[2].xyzz, CONST[10].xyzz
  3: MUL TEMP[2].xyz, TEMP[0].yyyy, IMM[0].xyzz
  4: MAD TEMP[2].xyz, TEMP[0].xxxx, IMM[1].xyzz, TEMP[2].xyzz
  5: MAD TEMP[2].xyz, TEMP[0].zzzz, IMM[2].xyzz, TEMP[2].xyzz
  6: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
  7: RSQ TEMP[3].x, TEMP[3].xxxx
  8: MUL TEMP[3].xyz, TEMP[2].xyzz, TEMP[3].xxxx
  9: DP3 TEMP[2].x, TEMP[3].xyzz, IN[3].xyzz
 10: DP3 TEMP[4].x, TEMP[3].xyzz, IN[4].xyzz
 11: MOV TEMP[2].y, TEMP[4].xxxx
 12: DP3 TEMP[4].x, TEMP[3].xyzz, IN[5].xyzz
 13: MOV TEMP[2].z, TEMP[4].xxxx
 14: DP3 TEMP[4].x, TEMP[2].xyzz, TEMP[1].xyzz
 15: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[2].xyzz
 16: ADD TEMP[4].x, TEMP[4].xxxx, TEMP[4].xxxx
 17: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[5].xxxx
 18: MAD TEMP[2].xyz, TEMP[4].xxxx, TEMP[2].xyzz, -TEMP[1].xyzz
 19: MOV TEMP[4].xyz, TEMP[2].xyzz
 20: TEX TEMP[4].xyz, TEMP[4], SAMP[2], CUBE
 21: MOV TEMP[5].xy, IN[1].xyyy
 22: TEX TEMP[5].xyz, TEMP[5], SAMP[0], 2D
 23: MOV TEMP[6].xy, IN[6].wzzz
 24: TEX TEMP[6].xyz, TEMP[6], SAMP[1], 2D
 25: MOV TEMP[7].xy, IN[6].xyyy
 26: TEX TEMP[7].xyz, TEMP[7], SAMP[1], 2D
 27: MOV TEMP[8].xy, IN[7].xyyy
 28: TEX TEMP[8].xyz, TEMP[8], SAMP[1], 2D
 29: MUL TEMP[4].xyz, TEMP[4].xyzz, CONST[30].zzzz
 30: MUL TEMP[4].xyz, TEMP[0].wwww, TEMP[4].xyzz
 31: MUL TEMP[4].xyz, TEMP[4].xyzz, CONST[0].xyzz
 32: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[4].xyzz
 33: MUL TEMP[5].xyz, TEMP[5].xyzz, IN[0].xyzz
 34: MUL TEMP[3].xyz, TEMP[0].yyyy, TEMP[6].xyzz
 35: MAD TEMP[1].xyz, TEMP[0].xxxx, TEMP[7].xyzz, TEMP[3].xyzz
 36: MAD TEMP[0].xyz, TEMP[0].zzzz, TEMP[8].xyzz, TEMP[1].xyzz
 37: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[12].xyzz
 38: MAD TEMP[1].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
 39: MAD TEMP[0].xyz, TEMP[5].xyzz, TEMP[0].xyzz, TEMP[4].xyzz
 40: MIN TEMP[1].x, TEMP[1].xxxx, CONST[11].zzzz
 41: MOV_SAT TEMP[1].x, TEMP[1].xxxx
 42: MAD TEMP[2].xyz, TEMP[0].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 43: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 44: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[1].xxxx
 45: MAD TEMP[0].xyz, TEMP[0].xyzz, CONST[30].xxxx, TEMP[2].xyzz
 46: MUL TEMP[1].x, IN[2].wwww, CONST[29].wwww
 47: MOV TEMP[0].w, TEMP[1].xxxx
 48: MOV TEMP[9], TEMP[0]
 49: MOV OUT[0], TEMP[9]
 50: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 160)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 164)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 168)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 188)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 488)
  %40 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0
  %42 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
  %44 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %45 = load <32 x i8> addrspace(2)* %44, !tbaa !0
  %46 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0
  %48 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %49 = load <32 x i8> addrspace(2)* %48, !tbaa !0
  %50 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %53 = load <32 x i8> addrspace(2)* %52, !tbaa !0
  %54 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
  %56 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %57 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %59 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %60 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %61 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %62 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %63 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %64 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %65 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
  %66 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
  %67 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %68 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
  %69 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
  %70 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
  %71 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
  %72 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
  %73 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
  %74 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %6)
  %75 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %6)
  %76 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %3, <2 x i32> %6)
  %77 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %3, <2 x i32> %6)
  %78 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %3, <2 x i32> %6)
  %79 = call float @llvm.SI.fs.interp(i32 1, i32 7, i32 %3, <2 x i32> %6)
  %80 = bitcast float %59 to i32
  %81 = bitcast float %60 to i32
  %82 = insertelement <2 x i32> undef, i32 %80, i32 0
  %83 = insertelement <2 x i32> %82, i32 %81, i32 1
  %84 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %83, <32 x i8> %53, <16 x i8> %55, i32 2)
  %85 = extractelement <4 x float> %84, i32 0
  %86 = extractelement <4 x float> %84, i32 1
  %87 = extractelement <4 x float> %84, i32 2
  %88 = extractelement <4 x float> %84, i32 3
  %89 = fsub float -0.000000e+00, %61
  %90 = fadd float %89, %25
  %91 = fsub float -0.000000e+00, %62
  %92 = fadd float %91, %26
  %93 = fsub float -0.000000e+00, %63
  %94 = fadd float %93, %27
  %95 = fmul float %86, 0xBFDA20BDA0000000
  %96 = fmul float %86, 0x3FE6A09E60000000
  %97 = fmul float %86, 0x3FE279A740000000
  %98 = fmul float %85, 0x3FEA20BD80000000
  %99 = fadd float %98, %95
  %100 = fmul float %85, 0.000000e+00
  %101 = fadd float %100, %96
  %102 = fmul float %85, 0x3FE279A740000000
  %103 = fadd float %102, %97
  %104 = fmul float %87, 0xBFDA20BD20000000
  %105 = fadd float %104, %99
  %106 = fmul float %87, 0xBFE6A09E80000000
  %107 = fadd float %106, %101
  %108 = fmul float %87, 0x3FE279A740000000
  %109 = fadd float %108, %103
  %110 = fmul float %105, %105
  %111 = fmul float %107, %107
  %112 = fadd float %111, %110
  %113 = fmul float %109, %109
  %114 = fadd float %112, %113
  %115 = call float @fabs(float %114)
  %116 = call float @llvm.AMDGPU.rsq(float %115)
  %117 = fmul float %105, %116
  %118 = fmul float %107, %116
  %119 = fmul float %109, %116
  %120 = fmul float %117, %65
  %121 = fmul float %118, %66
  %122 = fadd float %121, %120
  %123 = fmul float %119, %67
  %124 = fadd float %122, %123
  %125 = fmul float %117, %68
  %126 = fmul float %118, %69
  %127 = fadd float %126, %125
  %128 = fmul float %119, %70
  %129 = fadd float %127, %128
  %130 = fmul float %117, %71
  %131 = fmul float %118, %72
  %132 = fadd float %131, %130
  %133 = fmul float %119, %73
  %134 = fadd float %132, %133
  %135 = fmul float %124, %90
  %136 = fmul float %129, %92
  %137 = fadd float %136, %135
  %138 = fmul float %134, %94
  %139 = fadd float %137, %138
  %140 = fmul float %124, %124
  %141 = fmul float %129, %129
  %142 = fadd float %141, %140
  %143 = fmul float %134, %134
  %144 = fadd float %142, %143
  %145 = fadd float %139, %139
  %146 = fmul float %90, %144
  %147 = fmul float %92, %144
  %148 = fmul float %94, %144
  %149 = fsub float -0.000000e+00, %146
  %150 = fmul float %145, %124
  %151 = fadd float %150, %149
  %152 = fsub float -0.000000e+00, %147
  %153 = fmul float %145, %129
  %154 = fadd float %153, %152
  %155 = fsub float -0.000000e+00, %148
  %156 = fmul float %145, %134
  %157 = fadd float %156, %155
  %158 = insertelement <4 x float> undef, float %151, i32 0
  %159 = insertelement <4 x float> %158, float %154, i32 1
  %160 = insertelement <4 x float> %159, float %157, i32 2
  %161 = insertelement <4 x float> %160, float 0.000000e+00, i32 3
  %162 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %161)
  %163 = extractelement <4 x float> %162, i32 0
  %164 = extractelement <4 x float> %162, i32 1
  %165 = extractelement <4 x float> %162, i32 2
  %166 = extractelement <4 x float> %162, i32 3
  %167 = call float @fabs(float %165)
  %168 = fdiv float 1.000000e+00, %167
  %169 = fmul float %163, %168
  %170 = fadd float %169, 1.500000e+00
  %171 = fmul float %164, %168
  %172 = fadd float %171, 1.500000e+00
  %173 = bitcast float %172 to i32
  %174 = bitcast float %170 to i32
  %175 = bitcast float %166 to i32
  %176 = insertelement <4 x i32> undef, i32 %173, i32 0
  %177 = insertelement <4 x i32> %176, i32 %174, i32 1
  %178 = insertelement <4 x i32> %177, i32 %175, i32 2
  %179 = insertelement <4 x i32> %178, i32 undef, i32 3
  %180 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %179, <32 x i8> %49, <16 x i8> %51, i32 4)
  %181 = extractelement <4 x float> %180, i32 0
  %182 = extractelement <4 x float> %180, i32 1
  %183 = extractelement <4 x float> %180, i32 2
  %184 = bitcast float %59 to i32
  %185 = bitcast float %60 to i32
  %186 = insertelement <2 x i32> undef, i32 %184, i32 0
  %187 = insertelement <2 x i32> %186, i32 %185, i32 1
  %188 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %187, <32 x i8> %41, <16 x i8> %43, i32 2)
  %189 = extractelement <4 x float> %188, i32 0
  %190 = extractelement <4 x float> %188, i32 1
  %191 = extractelement <4 x float> %188, i32 2
  %192 = bitcast float %77 to i32
  %193 = bitcast float %76 to i32
  %194 = insertelement <2 x i32> undef, i32 %192, i32 0
  %195 = insertelement <2 x i32> %194, i32 %193, i32 1
  %196 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %195, <32 x i8> %45, <16 x i8> %47, i32 2)
  %197 = extractelement <4 x float> %196, i32 0
  %198 = extractelement <4 x float> %196, i32 1
  %199 = extractelement <4 x float> %196, i32 2
  %200 = bitcast float %74 to i32
  %201 = bitcast float %75 to i32
  %202 = insertelement <2 x i32> undef, i32 %200, i32 0
  %203 = insertelement <2 x i32> %202, i32 %201, i32 1
  %204 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %203, <32 x i8> %45, <16 x i8> %47, i32 2)
  %205 = extractelement <4 x float> %204, i32 0
  %206 = extractelement <4 x float> %204, i32 1
  %207 = extractelement <4 x float> %204, i32 2
  %208 = bitcast float %78 to i32
  %209 = bitcast float %79 to i32
  %210 = insertelement <2 x i32> undef, i32 %208, i32 0
  %211 = insertelement <2 x i32> %210, i32 %209, i32 1
  %212 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %211, <32 x i8> %45, <16 x i8> %47, i32 2)
  %213 = extractelement <4 x float> %212, i32 0
  %214 = extractelement <4 x float> %212, i32 1
  %215 = extractelement <4 x float> %212, i32 2
  %216 = fmul float %181, %39
  %217 = fmul float %182, %39
  %218 = fmul float %183, %39
  %219 = fmul float %88, %216
  %220 = fmul float %88, %217
  %221 = fmul float %88, %218
  %222 = fmul float %219, %22
  %223 = fmul float %220, %23
  %224 = fmul float %221, %24
  %225 = fmul float %222, %222
  %226 = fmul float %223, %223
  %227 = fmul float %224, %224
  %228 = fmul float %189, %56
  %229 = fmul float %190, %57
  %230 = fmul float %191, %58
  %231 = fmul float %86, %197
  %232 = fmul float %86, %198
  %233 = fmul float %86, %199
  %234 = fmul float %85, %205
  %235 = fadd float %234, %231
  %236 = fmul float %85, %206
  %237 = fadd float %236, %232
  %238 = fmul float %85, %207
  %239 = fadd float %238, %233
  %240 = fmul float %87, %213
  %241 = fadd float %240, %235
  %242 = fmul float %87, %214
  %243 = fadd float %242, %237
  %244 = fmul float %87, %215
  %245 = fadd float %244, %239
  %246 = fmul float %241, %31
  %247 = fmul float %243, %32
  %248 = fmul float %245, %33
  %249 = fsub float -0.000000e+00, %28
  %250 = fmul float %64, %30
  %251 = fadd float %250, %249
  %252 = fmul float %228, %246
  %253 = fadd float %252, %225
  %254 = fmul float %229, %247
  %255 = fadd float %254, %226
  %256 = fmul float %230, %248
  %257 = fadd float %256, %227
  %258 = fcmp uge float %251, %29
  %259 = select i1 %258, float %29, float %251
  %260 = call float @llvm.AMDIL.clamp.(float %259, float 0.000000e+00, float 1.000000e+00)
  %261 = fsub float -0.000000e+00, %38
  %262 = fmul float %253, %261
  %263 = fadd float %262, %34
  %264 = fsub float -0.000000e+00, %38
  %265 = fmul float %255, %264
  %266 = fadd float %265, %35
  %267 = fsub float -0.000000e+00, %38
  %268 = fmul float %257, %267
  %269 = fadd float %268, %36
  %270 = fmul float %260, %260
  %271 = fmul float %263, %270
  %272 = fmul float %266, %270
  %273 = fmul float %269, %270
  %274 = fmul float %253, %38
  %275 = fadd float %274, %271
  %276 = fmul float %255, %38
  %277 = fadd float %276, %272
  %278 = fmul float %257, %38
  %279 = fadd float %278, %273
  %280 = fmul float %64, %37
  %281 = call i32 @llvm.SI.packf16(float %275, float %277)
  %282 = bitcast i32 %281 to float
  %283 = call i32 @llvm.SI.packf16(float %279, float %280)
  %284 = bitcast i32 %283 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %282, float %284, float %282, float %284)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #3

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #3

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 12; mem:LD16[%54](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 24; mem:LD32[%52](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6_VGPR7<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR8_VGPR9, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR10<def> = V_MUL_F32_e32 7.071068e-01, %VGPR5, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR4, 0.000000e+00, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 -7.071068e-01, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR6, %VGPR11<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 -4.082483e-01, %VGPR5, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 8.164966e-01, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR4, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 -4.082482e-01, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR6, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR13, %VGPR13, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 5.773503e-01, %VGPR5, %EXEC<imp-use>
	%VGPR14<def> = V_MOV_B32_e32 5.773503e-01, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR4, %VGPR14, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR6, %VGPR14<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR10, %VGPR10, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_F32_e64 %VGPR12<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_RSQ_LEGACY_F32_e32 %VGPR12<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR13, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR11, %VGPR15<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR14, %VGPR10<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR13, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR11, %VGPR15<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR14, %VGPR15<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR12, %VGPR12, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR10, %VGPR10, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR0, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<kill,tied0>, %VGPR1, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR0, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<kill,tied0>, %VGPR1, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %VGPR16<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR14<kill>, %VGPR13<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 41
	S_WAITCNT 127
	%VGPR16<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR16, %VGPR13, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 40
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR12, %VGPR15, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR10, %VGPR16<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 42
	S_WAITCNT 127
	%VGPR16<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR11, %VGPR16, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e32 %VGPR17<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR17, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 %VGPR10<kill>, %VGPR14<kill>, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-def>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR17, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %VGPR12<kill>, %VGPR10<kill>, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-def>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR10<kill>, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-def>
	%VGPR21<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-def>
	%VGPR11<def> = V_CUBESC_F32 %VGPR18, %VGPR19, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR10<def> = V_CUBETC_F32 %VGPR18, %VGPR19, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR12<def> = V_CUBEMA_F32 %VGPR18, %VGPR19, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR13<def> = V_CUBEID_F32 %VGPR18, %VGPR19, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR18<def> = V_ADD_F32_e64 %VGPR12, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_RCP_F32_e32 %VGPR18<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR10, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR11<def> = V_MAD_F32 %VGPR11, %VGPR18<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR14<def> = KILL %VGPR14<undef>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%50](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%48](tbaa=!"const")
	S_WAITCNT 127
	%VGPR10_VGPR11_VGPR12<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR11_VGPR12_VGPR13_VGPR14, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 122
	S_WAITCNT 112
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0, %VGPR11, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR7, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR2, 2, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<tied0>, %VGPR3, 2, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR2, 3, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<tied0>, %VGPR3, 3, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%46](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%44](tbaa=!"const")
	S_WAITCNT 127
	%VGPR13_VGPR14_VGPR15<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR19<def> = V_MUL_F32_e32 %VGPR5, %VGPR14, %EXEC<imp-use>
	%VGPR17<def> = V_INTERP_P1_F32 %VGPR2, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-def>
	%VGPR17<def,tied1> = V_INTERP_P2_F32 %VGPR17<tied0>, %VGPR3, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-use,kill>, %VGPR16_VGPR17<imp-def>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR2, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-use,kill>, %VGPR16_VGPR17<imp-def>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<tied0>, %VGPR3, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-use,kill>, %VGPR16_VGPR17<imp-def>
	%VGPR16_VGPR17_VGPR18<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR16_VGPR17<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR19<def> = V_MAD_F32 %VGPR4, %VGPR17, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_INTERP_P1_F32 %VGPR2, 1, 7, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-def>
	%VGPR21<def,tied1> = V_INTERP_P2_F32 %VGPR21<tied0>, %VGPR3, 1, 7, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-use,kill>, %VGPR20_VGPR21<imp-def>
	%VGPR20<def> = V_INTERP_P1_F32 %VGPR2, 0, 7, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-use,kill>, %VGPR20_VGPR21<imp-def>
	%VGPR20<def,tied1> = V_INTERP_P2_F32 %VGPR20<tied0>, %VGPR3, 0, 7, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR20_VGPR21<imp-use,kill>, %VGPR20_VGPR21<imp-def>
	%VGPR22_VGPR23_VGPR24<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR20_VGPR21<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %VGPR23, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%42](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%40](tbaa=!"const")
	S_WAITCNT 127
	%VGPR19_VGPR20_VGPR21<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR8_VGPR9<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR3<def> = V_MUL_F32_e32 %VGPR20, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR3<kill>, %VGPR2<kill>, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 120
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR1, %VGPR8, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 117
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR25<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8<kill>, %SGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0, %VGPR10, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR7, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR5, %VGPR13, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR4, %VGPR16, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR6, %VGPR22, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR25<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR26<def,tied1> = V_INTERP_P2_F32 %VGPR26<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR19, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR26<kill>, %VGPR25<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %SGPR1, %VGPR9, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 116
	S_WAITCNT 127
	%VGPR25<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR9<kill>, %SGPR1, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR12, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12<imp-use,kill>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR7, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR5, %VGPR15, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15<imp-use,kill>
	%VGPR10<def> = V_MAD_F32 %VGPR4, %VGPR18, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR16_VGPR17_VGPR18<imp-use,kill>
	%VGPR4<def> = V_MAD_F32 %VGPR6, %VGPR24, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR22_VGPR23_VGPR24<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR21, %VGPR5<kill>, %EXEC<imp-use>, %VGPR19_VGPR20_VGPR21<imp-use,kill>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %VGPR4<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR1, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 118
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR1<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 119
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR8<kill>, %VGPR0<kill>, %VGPR8, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8240500
c8250501
c8200400
c8210401
c084030c
c0c60518
bf8c007f
f0800f00
00430408
bf8c0770
10140aff
3f3504f3
d282000a
04290104
7e1602ff
bf3504f4
d282000b
042a1706
10140aff
bed105ed
7e1802ff
3f5105ec
d282000a
042a1904
7e1802ff
bed105e9
d282000d
042a1906
10141b0d
d282000c
042a170b
10140aff
3f13cd3a
7e1c02ff
3f13cd3a
d282000a
042a1d04
d282000a
042a1d06
d282000c
0432150a
d206010c
0201010c
7e185b0c
1016190b
101a190d
c8381000
c8391001
101c1d0d
c83c1100
c83d1101
d282000f
043a1f0b
101c190a
c8281200
c8291201
d282000a
043e150e
c8300c00
c8310c01
1018190d
c83c0d00
c83d0d01
d282000c
04321f0b
c83c0e00
c83d0e01
d282000c
04321f0e
101e190c
d282000f
043e150a
c8401400
c8411401
101a210d
c8401500
c8411501
d282000b
0436210b
c8341600
c8351601
d282000b
042e1b0e
d282000d
043e170b
c8380900
c8390901
c0840100
bf8c007f
c2000929
bf8c007f
08201c00
101c1b10
c83c0800
c83d0801
c2000928
bf8c007f
081e1e00
10221f0c
d2820011
0446210a
c8400a00
c8410a01
c200092a
bf8c007f
08202000
d2820011
0446210b
06222311
10141511
08261d0a
10141b0f
10181911
0824150c
10141b10
10161711
0828150b
7e2a0280
d28a000b
04522712
d28c000a
04522712
d28e000c
04522712
d288000d
04522712
d2060112
0201010c
7e245512
7e2602ff
3fc00000
d282000c
044e250a
d282000b
044e250b
c0860308
c0c80510
bf8c007f
f0800700
00640a0b
c200097a
bf8c0070
101a1600
101a1b07
c2008901
bf8c007f
101a1a01
10321b0d
c8381a02
c8391a03
c8341b02
c8351b03
c0860304
c0c80508
bf8c007f
f0800700
00640d0d
bf8c0770
10261d05
c8441902
c8451903
c8401802
c8411803
f0800700
00641010
bf8c0770
d2820013
044e2304
c8541d02
c8551d03
c8501c02
c8511c03
f0800700
00641614
bf8c0770
d2820002
044e2f06
c2008931
bf8c007f
10040401
c0860300
c0c80500
bf8c007f
f0800700
00641308
c80c0100
c80d0101
bf8c0770
10060714
d2820008
04660503
c2008978
bf8c007f
10041001
c2010975
bf8c007f
08120402
c8080b00
c8090b01
c201092f
bf8c007f
10060402
c201092c
bf8c007f
0a060602
c201092e
bf8c007f
d00c0004
02000503
7e320202
d2000003
00123303
d2060803
02010103
10060703
10120709
d2820008
04240308
10121400
10121307
c2010900
bf8c007f
10121202
10121309
10321b05
d2820019
04662104
d2820019
04662d06
c2010930
bf8c007f
10323202
c8680000
c8690001
10343513
d2820009
0426331a
10321201
c2010974
bf8c007f
08323202
10320719
d2820009
04640309
5e101109
10121800
10121307
c2000902
bf8c007f
10121200
10121309
10141f05
d282000a
042a2504
d2820004
042a3106
c2000932
bf8c007f
10080800
c8140200
c8150201
10000b15
d2820000
04260900
10020001
c2000976
bf8c007f
08020200
10020701
d2820000
04040300
c2000977
bf8c007f
10020400
5e000300
f8001c0f
00080008
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL OUT[7], GENERIC[23]
DCL OUT[8], GENERIC[24]
DCL OUT[9], GENERIC[25]
DCL CONST[0..51]
DCL TEMP[0..12], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[6]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: DP4 TEMP[5].x, TEMP[0], CONST[7]
 12: MOV TEMP[2].w, TEMP[5].xxxx
 13: DP4 TEMP[6].x, TEMP[0], CONST[12]
 14: DP3 TEMP[7].x, IN[1].xyzz, CONST[48].xyzz
 15: MOV TEMP[7].z, TEMP[7].xxxx
 16: DP3 TEMP[8].x, IN[1].xyzz, CONST[49].xyzz
 17: MOV TEMP[8].z, TEMP[8].xxxx
 18: DP3 TEMP[9].x, IN[1].xyzz, CONST[50].xyzz
 19: MOV TEMP[9].z, TEMP[9].xxxx
 20: DP3 TEMP[7].x, IN[5].xyzz, CONST[48].xyzz
 21: DP3 TEMP[8].x, IN[5].xyzz, CONST[49].xyzz
 22: DP3 TEMP[9].x, IN[5].xyzz, CONST[50].xyzz
 23: DP3 TEMP[10].x, IN[6].xyzz, CONST[48].xyzz
 24: MOV TEMP[7].y, TEMP[10].xxxx
 25: ADD TEMP[0].xy, IN[4].xyyy, IN[3].xyyy
 26: DP3 TEMP[10].x, IN[6].xyzz, CONST[49].xyzz
 27: MOV TEMP[8].y, TEMP[10].xxxx
 28: ADD TEMP[10].xy, TEMP[0].yxxx, IN[4].yxxx
 29: MOV TEMP[0].zw, TEMP[10].yyxy
 30: DP3 TEMP[11].x, IN[6].xyzz, CONST[50].xyzz
 31: MOV TEMP[9].y, TEMP[11].xxxx
 32: MOV TEMP[0], TEMP[0]
 33: ADD TEMP[10].xy, TEMP[10].yxxx, IN[4].xyyy
 34: MOV TEMP[1].w, TEMP[6].xxxx
 35: MOV TEMP[6].xy, IN[2].xyxx
 36: MOV TEMP[10].zw, IN[2].yyxy
 37: MAD TEMP[11], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 38: MOV TEMP[12], TEMP[2]
 39: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[5].xxxx
 40: MOV TEMP[2].z, TEMP[4].xxxx
 41: MOV TEMP[2].y, -TEMP[3].xxxx
 42: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[5].xxxx, TEMP[2].xyyy
 43: MOV OUT[3], TEMP[6]
 44: MOV OUT[8], TEMP[0]
 45: MOV OUT[9], TEMP[10]
 46: MOV OUT[0], TEMP[2]
 47: MOV OUT[4], TEMP[1]
 48: MOV OUT[2], TEMP[12]
 49: MOV OUT[5], TEMP[7]
 50: MOV OUT[6], TEMP[8]
 51: MOV_SAT OUT[1], TEMP[11]
 52: MOV OUT[7], TEMP[9]
 53: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 764)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 776)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 792)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 800)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 804)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 808)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 812)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 816)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 820)
  %49 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0
  %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %5)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = extractelement <4 x float> %51, i32 1
  %54 = extractelement <4 x float> %51, i32 2
  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = extractelement <4 x float> %57, i32 2
  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
  %64 = extractelement <4 x float> %63, i32 0
  %65 = extractelement <4 x float> %63, i32 1
  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
  %69 = extractelement <4 x float> %68, i32 0
  %70 = extractelement <4 x float> %68, i32 1
  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
  %74 = extractelement <4 x float> %73, i32 0
  %75 = extractelement <4 x float> %73, i32 1
  %76 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
  %77 = load <16 x i8> addrspace(2)* %76, !tbaa !0
  %78 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %77, i32 0, i32 %5)
  %79 = extractelement <4 x float> %78, i32 0
  %80 = extractelement <4 x float> %78, i32 1
  %81 = extractelement <4 x float> %78, i32 2
  %82 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
  %83 = load <16 x i8> addrspace(2)* %82, !tbaa !0
  %84 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %83, i32 0, i32 %5)
  %85 = extractelement <4 x float> %84, i32 0
  %86 = extractelement <4 x float> %84, i32 1
  %87 = extractelement <4 x float> %84, i32 2
  %88 = fmul float %52, %12
  %89 = fadd float %88, %11
  %90 = fmul float %53, %12
  %91 = fadd float %90, %11
  %92 = fmul float %54, %12
  %93 = fadd float %92, %11
  %94 = fmul float %52, %11
  %95 = fadd float %94, %12
  %96 = fmul float %89, %35
  %97 = fmul float %91, %36
  %98 = fadd float %96, %97
  %99 = fmul float %93, %37
  %100 = fadd float %98, %99
  %101 = fmul float %95, %38
  %102 = fadd float %100, %101
  %103 = fmul float %89, %39
  %104 = fmul float %91, %40
  %105 = fadd float %103, %104
  %106 = fmul float %93, %41
  %107 = fadd float %105, %106
  %108 = fmul float %95, %42
  %109 = fadd float %107, %108
  %110 = fmul float %89, %43
  %111 = fmul float %91, %44
  %112 = fadd float %110, %111
  %113 = fmul float %93, %45
  %114 = fadd float %112, %113
  %115 = fmul float %95, %46
  %116 = fadd float %114, %115
  %117 = fmul float %89, %14
  %118 = fmul float %91, %15
  %119 = fadd float %117, %118
  %120 = fmul float %93, %16
  %121 = fadd float %119, %120
  %122 = fmul float %95, %17
  %123 = fadd float %121, %122
  %124 = fmul float %89, %18
  %125 = fmul float %91, %19
  %126 = fadd float %124, %125
  %127 = fmul float %93, %20
  %128 = fadd float %126, %127
  %129 = fmul float %95, %21
  %130 = fadd float %128, %129
  %131 = fmul float %89, %22
  %132 = fmul float %91, %23
  %133 = fadd float %131, %132
  %134 = fmul float %93, %24
  %135 = fadd float %133, %134
  %136 = fmul float %95, %25
  %137 = fadd float %135, %136
  %138 = fmul float %89, %26
  %139 = fmul float %91, %27
  %140 = fadd float %138, %139
  %141 = fmul float %93, %28
  %142 = fadd float %140, %141
  %143 = fmul float %95, %29
  %144 = fadd float %142, %143
  %145 = fmul float %89, %30
  %146 = fmul float %91, %31
  %147 = fadd float %145, %146
  %148 = fmul float %93, %32
  %149 = fadd float %147, %148
  %150 = fmul float %95, %33
  %151 = fadd float %149, %150
  %152 = fmul float %58, %35
  %153 = fmul float %59, %36
  %154 = fadd float %153, %152
  %155 = fmul float %60, %37
  %156 = fadd float %154, %155
  %157 = fmul float %58, %39
  %158 = fmul float %59, %40
  %159 = fadd float %158, %157
  %160 = fmul float %60, %41
  %161 = fadd float %159, %160
  %162 = fmul float %58, %43
  %163 = fmul float %59, %44
  %164 = fadd float %163, %162
  %165 = fmul float %60, %45
  %166 = fadd float %164, %165
  %167 = fmul float %79, %35
  %168 = fmul float %80, %36
  %169 = fadd float %168, %167
  %170 = fmul float %81, %37
  %171 = fadd float %169, %170
  %172 = fmul float %79, %39
  %173 = fmul float %80, %40
  %174 = fadd float %173, %172
  %175 = fmul float %81, %41
  %176 = fadd float %174, %175
  %177 = fmul float %79, %43
  %178 = fmul float %80, %44
  %179 = fadd float %178, %177
  %180 = fmul float %81, %45
  %181 = fadd float %179, %180
  %182 = fmul float %85, %35
  %183 = fmul float %86, %36
  %184 = fadd float %183, %182
  %185 = fmul float %87, %37
  %186 = fadd float %184, %185
  %187 = fadd float %74, %69
  %188 = fadd float %75, %70
  %189 = fmul float %85, %39
  %190 = fmul float %86, %40
  %191 = fadd float %190, %189
  %192 = fmul float %87, %41
  %193 = fadd float %191, %192
  %194 = fadd float %188, %75
  %195 = fadd float %187, %74
  %196 = fmul float %85, %43
  %197 = fmul float %86, %44
  %198 = fadd float %197, %196
  %199 = fmul float %87, %45
  %200 = fadd float %198, %199
  %201 = fadd float %195, %74
  %202 = fadd float %194, %75
  %203 = fmul float %34, %11
  %204 = fadd float %203, %12
  %205 = fmul float %34, %11
  %206 = fadd float %205, %12
  %207 = fmul float %34, %11
  %208 = fadd float %207, %12
  %209 = fmul float %34, %12
  %210 = fadd float %209, %11
  %211 = fsub float -0.000000e+00, %144
  %212 = fmul float %137, %13
  %213 = fadd float %212, %211
  %214 = fsub float -0.000000e+00, %130
  %215 = fmul float %47, %144
  %216 = fadd float %215, %123
  %217 = fmul float %48, %144
  %218 = fadd float %217, %214
  %219 = call float @llvm.AMDIL.clamp.(float %204, float 0.000000e+00, float 1.000000e+00)
  %220 = call float @llvm.AMDIL.clamp.(float %206, float 0.000000e+00, float 1.000000e+00)
  %221 = call float @llvm.AMDIL.clamp.(float %208, float 0.000000e+00, float 1.000000e+00)
  %222 = call float @llvm.AMDIL.clamp.(float %210, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %219, float %220, float %221, float %222)
  %223 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %224 = load <16 x i8> addrspace(2)* %223, !tbaa !0
  %225 = call float @llvm.SI.load.const(<16 x i8> %224, i32 0)
  %226 = fmul float %225, %123
  %227 = call float @llvm.SI.load.const(<16 x i8> %224, i32 4)
  %228 = fmul float %227, %130
  %229 = fadd float %226, %228
  %230 = call float @llvm.SI.load.const(<16 x i8> %224, i32 8)
  %231 = fmul float %230, %137
  %232 = fadd float %229, %231
  %233 = call float @llvm.SI.load.const(<16 x i8> %224, i32 12)
  %234 = fmul float %233, %144
  %235 = fadd float %232, %234
  %236 = call float @llvm.SI.load.const(<16 x i8> %224, i32 16)
  %237 = fmul float %236, %123
  %238 = call float @llvm.SI.load.const(<16 x i8> %224, i32 20)
  %239 = fmul float %238, %130
  %240 = fadd float %237, %239
  %241 = call float @llvm.SI.load.const(<16 x i8> %224, i32 24)
  %242 = fmul float %241, %137
  %243 = fadd float %240, %242
  %244 = call float @llvm.SI.load.const(<16 x i8> %224, i32 28)
  %245 = fmul float %244, %144
  %246 = fadd float %243, %245
  %247 = call float @llvm.SI.load.const(<16 x i8> %224, i32 32)
  %248 = fmul float %247, %123
  %249 = call float @llvm.SI.load.const(<16 x i8> %224, i32 36)
  %250 = fmul float %249, %130
  %251 = fadd float %248, %250
  %252 = call float @llvm.SI.load.const(<16 x i8> %224, i32 40)
  %253 = fmul float %252, %137
  %254 = fadd float %251, %253
  %255 = call float @llvm.SI.load.const(<16 x i8> %224, i32 44)
  %256 = fmul float %255, %144
  %257 = fadd float %254, %256
  %258 = call float @llvm.SI.load.const(<16 x i8> %224, i32 48)
  %259 = fmul float %258, %123
  %260 = call float @llvm.SI.load.const(<16 x i8> %224, i32 52)
  %261 = fmul float %260, %130
  %262 = fadd float %259, %261
  %263 = call float @llvm.SI.load.const(<16 x i8> %224, i32 56)
  %264 = fmul float %263, %137
  %265 = fadd float %262, %264
  %266 = call float @llvm.SI.load.const(<16 x i8> %224, i32 60)
  %267 = fmul float %266, %144
  %268 = fadd float %265, %267
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %235, float %246, float %257, float %268)
  %269 = call float @llvm.SI.load.const(<16 x i8> %224, i32 64)
  %270 = fmul float %269, %123
  %271 = call float @llvm.SI.load.const(<16 x i8> %224, i32 68)
  %272 = fmul float %271, %130
  %273 = fadd float %270, %272
  %274 = call float @llvm.SI.load.const(<16 x i8> %224, i32 72)
  %275 = fmul float %274, %137
  %276 = fadd float %273, %275
  %277 = call float @llvm.SI.load.const(<16 x i8> %224, i32 76)
  %278 = fmul float %277, %144
  %279 = fadd float %276, %278
  %280 = call float @llvm.SI.load.const(<16 x i8> %224, i32 80)
  %281 = fmul float %280, %123
  %282 = call float @llvm.SI.load.const(<16 x i8> %224, i32 84)
  %283 = fmul float %282, %130
  %284 = fadd float %281, %283
  %285 = call float @llvm.SI.load.const(<16 x i8> %224, i32 88)
  %286 = fmul float %285, %137
  %287 = fadd float %284, %286
  %288 = call float @llvm.SI.load.const(<16 x i8> %224, i32 92)
  %289 = fmul float %288, %144
  %290 = fadd float %287, %289
  %291 = call float @llvm.SI.load.const(<16 x i8> %224, i32 96)
  %292 = fmul float %291, %123
  %293 = call float @llvm.SI.load.const(<16 x i8> %224, i32 100)
  %294 = fmul float %293, %130
  %295 = fadd float %292, %294
  %296 = call float @llvm.SI.load.const(<16 x i8> %224, i32 104)
  %297 = fmul float %296, %137
  %298 = fadd float %295, %297
  %299 = call float @llvm.SI.load.const(<16 x i8> %224, i32 108)
  %300 = fmul float %299, %144
  %301 = fadd float %298, %300
  %302 = call float @llvm.SI.load.const(<16 x i8> %224, i32 112)
  %303 = fmul float %302, %123
  %304 = call float @llvm.SI.load.const(<16 x i8> %224, i32 116)
  %305 = fmul float %304, %130
  %306 = fadd float %303, %305
  %307 = call float @llvm.SI.load.const(<16 x i8> %224, i32 120)
  %308 = fmul float %307, %137
  %309 = fadd float %306, %308
  %310 = call float @llvm.SI.load.const(<16 x i8> %224, i32 124)
  %311 = fmul float %310, %144
  %312 = fadd float %309, %311
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %279, float %290, float %301, float %312)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %64, float %65, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %102, float %109, float %116, float %151)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %171, float %186, float %156, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %176, float %193, float %161, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %181, float %200, float %166, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %187, float %188, float %194, float %195)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %201, float %202, float %64, float %65)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %216, float %218, float %213, float %144)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 191
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR4, %VGPR1, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%49](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR3, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR9, %SGPR3, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR10, %SGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR3<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 19
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 23
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%223](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 27
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 30
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 31
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 19
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%61](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 15
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 51
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 201
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR0, %VGPR6, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 200
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR5, %SGPR1, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 202
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR7, %SGPR2, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 203
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR8, %SGPR3<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 127
	%VGPR16<def> = V_MUL_F32_e32 %SGPR3, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR5, %SGPR4, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 198
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR7, %SGPR5, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 199
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR8, %SGPR12<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR12, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR5<kill>, %SGPR14, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 194
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR7<kill>, %SGPR13, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 195
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR8<kill>, %SGPR15<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR5<kill>, %VGPR16<kill>, %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%55](tbaa=!"const")
	S_WAITCNT 15
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR14<def> = V_MUL_F32_e32 %SGPR14, %VGPR5, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR6, %SGPR12, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR7, %SGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 24; mem:LD16[%82](tbaa=!"const")
	S_WAITCNT 127
	%VGPR14_VGPR15_VGPR16_VGPR17<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %SGPR14, %VGPR14, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR15, %SGPR12, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR16, %SGPR13, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%76](tbaa=!"const")
	S_WAITCNT 127
	%VGPR18_VGPR19_VGPR20_VGPR21<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR24<def> = V_MUL_F32_e32 %SGPR14<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR19, %SGPR12<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR20, %SGPR13<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR24<kill>, %VGPR23<kill>, %VGPR22<kill>, %VGPR13, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR22<def> = V_MUL_F32_e32 %SGPR4, %VGPR5, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR6, %SGPR3, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR7, %SGPR5, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %SGPR4, %VGPR14, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR15, %SGPR3, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR16, %SGPR5, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR19, %SGPR3<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR20, %SGPR5<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 36, 0, 0, 0, %VGPR24<kill>, %VGPR23<kill>, %VGPR22<kill>, %VGPR13, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR22<def> = V_MUL_F32_e32 %SGPR1, %VGPR5, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR6, %SGPR0, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR7, %SGPR2, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR1, %VGPR14, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR15, %SGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR16, %SGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR19, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR20, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>
	EXP 15, 37, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%66](tbaa=!"const")
	S_WAITCNT 15
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 16; mem:LD16[%71](tbaa=!"const")
	S_WAITCNT 112
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR17<def> = V_ADD_F32_e32 %VGPR5, %VGPR13, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR17, %VGPR5, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e32 %VGPR6, %VGPR14, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR13, %VGPR6, %EXEC<imp-use>
	EXP 15, 38, 0, 0, 0, %VGPR17<kill>, %VGPR13<kill>, %VGPR14, %VGPR0, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR13<def> = V_ADD_F32_e32 %VGPR14<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR0<kill>, %VGPR5, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	EXP 15, 39, 0, 0, 0, %VGPR0<kill>, %VGPR13<kill>, %VGPR9, %VGPR10, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 204
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 205
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840100
bf8c007f
c20209bf
c2010900
bf8c007f
7e040202
c2018901
bf8c007f
7e020203
d2820003
040a0204
d2060803
02010103
d2820004
04060404
d2060804
02010104
f800020f
03040404
c0860700
bf8c000f
e00c2000
80030800
bf8c0770
d2820005
04080708
d2820006
04080709
c2020911
bf8c007f
10060c04
c2020910
bf8c007f
d2820003
040c0905
d2820007
0408070a
c2018912
bf8c007f
d2820002
040c0707
d2820008
04040508
c2010913
bf8c007f
d2820001
04080508
c2010915
bf8c007f
10040c02
c2010914
bf8c007f
d2820002
04080505
c2010916
bf8c007f
d2820002
04080507
c2010917
bf8c007f
d2820002
04080508
c0800104
bf8c007f
c202010d
bf8c007f
10060404
c202010c
bf8c007f
d2820004
040e0204
c2020919
bf8c007f
10060c04
c2020918
bf8c007f
d2820003
040c0905
c202091a
bf8c007f
d2820003
040c0907
c202091b
bf8c007f
d2820003
040c0908
c202010e
bf8c007f
d2820009
04120604
c202091d
bf8c007f
10080c04
c202091c
bf8c007f
d2820004
04100905
c202091e
bf8c007f
d2820004
04100907
c202091f
bf8c007f
d2820004
04100908
c202010f
bf8c007f
d2820009
04260804
c2020109
bf8c007f
10140404
c2020108
bf8c007f
d282000a
042a0204
c202010a
bf8c007f
d282000a
042a0604
c202010b
bf8c007f
d282000a
042a0804
c2020105
bf8c007f
10160404
c2020104
bf8c007f
d282000b
042e0204
c2020106
bf8c007f
d282000b
042e0604
c2020107
bf8c007f
d282000b
042e0804
c2020101
bf8c007f
10180404
c2020100
bf8c007f
d282000c
04320204
c2020102
bf8c007f
d282000c
04320604
c2020103
bf8c007f
d282000c
04320804
f80000ef
090a0b0c
c202011d
bf8c000f
10120404
c202011c
bf8c007f
d2820009
04260204
c202011e
bf8c007f
d2820009
04260604
c202011f
bf8c007f
d2820009
04260804
c2020119
bf8c007f
10140404
c2020118
bf8c007f
d282000a
042a0204
c202011a
bf8c007f
d282000a
042a0604
c202011b
bf8c007f
d282000a
042a0804
c2020115
bf8c007f
10160404
c2020114
bf8c007f
d282000b
042e0204
c2020116
bf8c007f
d282000b
042e0604
c2020117
bf8c007f
d282000b
042e0804
c2020111
bf8c007f
10180404
c2020110
bf8c007f
d282000c
04320204
c2020112
bf8c007f
d282000c
04320604
c2000113
bf8c007f
d282000c
04320800
f80000ff
090a0b0c
c0800708
bf8c000f
e00c2000
80000900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c2000931
bf8c000f
101c0c00
c2000930
bf8c007f
d282000e
04380105
c2000932
bf8c007f
d282000e
04380107
c2000933
bf8c007f
d282000e
04380108
c20009c9
bf8c007f
101e0c00
c20089c8
bf8c007f
d282000f
043c0305
c20109ca
bf8c007f
d282000f
043c0507
c20189cb
bf8c007f
d282000f
043c0708
c20189c5
bf8c007f
10200c03
c20209c4
bf8c007f
d2820010
04400905
c20289c6
bf8c007f
d2820010
04400b07
c20609c7
bf8c007f
d2820010
04401908
c20609c1
bf8c007f
100c0c0c
c20709c0
bf8c007f
d2820005
04181d05
c20689c2
bf8c007f
d2820005
04141b07
c20789c3
bf8c007f
d2820005
04141f08
f800022f
0e0f1005
c0880704
bf8c000f
e00c2000
80040500
bf8c0770
101c0a0e
d282000e
04381906
d2820016
04381b07
c0880718
bf8c007f
e00c2000
80040e00
bf8c0770
10241c0e
d2820012
0448190f
d2820017
04481b10
c0880714
bf8c007f
e00c2000
80041200
bf8c0770
1030240e
d2820018
04601913
d2820018
04601b14
f800023f
0d161718
bf8c070f
102c0a04
d2820016
04580706
d2820016
04580b07
102e1c04
d2820017
045c070f
d2820017
045c0b10
10302404
d2820018
04600713
d2820018
04600b14
f800024f
0d161718
bf8c070f
102c0a01
d2820016
04580106
d2820005
04580507
100c1c01
d2820006
0418010f
d2820006
04180510
100e2401
d2820007
041c0113
d2820007
041c0514
f800025f
0d050607
c080070c
bf8c000f
e00c2000
80000d00
c0800710
bf8c0070
e00c2000
80000500
bf8c0770
06221b05
06000b11
061a1d06
061c0d0d
f800026f
000e0d11
bf8c070f
061a0d0e
06000b00
f800027f
0a090d00
c20009cc
bf8c000f
d2820000
04060800
c2000902
bf8c007f
10020600
08020901
c20009cd
bf8c007f
10060800
08040503
f80008cf
04010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE
DCL IN[4], GENERIC[22], PERSPECTIVE
DCL IN[5], GENERIC[23], PERSPECTIVE
DCL IN[6], GENERIC[24], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..30]
DCL TEMP[0..5], LOCAL
DCL TEMP[6], ARRAY(1), LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: ADD TEMP[0].xyz, -IN[2].xyzz, CONST[10].xyzz
  1: MOV TEMP[1].x, IN[3].zzzz
  2: MOV TEMP[1].y, IN[4].zzzz
  3: MOV TEMP[1].z, IN[5].zzzz
  4: DP3 TEMP[2].x, TEMP[1].xyzz, TEMP[0].xyzz
  5: DP3 TEMP[3].x, TEMP[1].xyzz, TEMP[1].xyzz
  6: ADD TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
  7: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[3].xxxx
  8: MAD TEMP[1].xyz, TEMP[2].xxxx, TEMP[1].xyzz, -TEMP[0].xyzz
  9: MOV TEMP[2].xyz, TEMP[1].xyzz
 10: TEX TEMP[2].xyz, TEMP[2], SAMP[2], CUBE
 11: MOV TEMP[3].xy, IN[1].xyyy
 12: TEX TEMP[3], TEMP[3], SAMP[0], 2D
 13: MOV TEMP[4].xy, IN[6].xyyy
 14: TEX TEMP[4].xyz, TEMP[4], SAMP[1], 2D
 15: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[30].zzzz
 16: ADD TEMP[5].x, -TEMP[3].wwww, IMM[0].xxxx
 17: MUL TEMP[0].xyz, TEMP[3].xyzz, IN[0].xyzz
 18: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[5].xxxx
 19: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[0].xyzz
 20: MUL TEMP[1].xyz, TEMP[4].xyzz, CONST[12].xyzz
 21: MAD TEMP[3].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
 22: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[1].xyzz, TEMP[2].xyzz
 23: MIN TEMP[2].x, TEMP[3].xxxx, CONST[11].zzzz
 24: MOV_SAT TEMP[2].x, TEMP[2].xxxx
 25: MAD TEMP[0].xyz, TEMP[1].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 26: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
 27: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
 28: MAD TEMP[1].xyz, TEMP[1].xyzz, CONST[30].xxxx, TEMP[0].xyzz
 29: MUL TEMP[0].x, IN[2].wwww, CONST[29].wwww
 30: MOV TEMP[1].w, TEMP[0].xxxx
 31: MOV TEMP[6], TEMP[1]
 32: MOV OUT[0], TEMP[6]
 33: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 160)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 164)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 168)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 188)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 488)
  %40 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0
  %42 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
  %44 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %45 = load <32 x i8> addrspace(2)* %44, !tbaa !0
  %46 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0
  %48 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %49 = load <32 x i8> addrspace(2)* %48, !tbaa !0
  %50 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %53 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %54 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %55 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %56 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %57 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %59 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %60 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %61 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %62 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
  %63 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
  %64 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %6)
  %65 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %6)
  %66 = fsub float -0.000000e+00, %57
  %67 = fadd float %66, %25
  %68 = fsub float -0.000000e+00, %58
  %69 = fadd float %68, %26
  %70 = fsub float -0.000000e+00, %59
  %71 = fadd float %70, %27
  %72 = fmul float %61, %67
  %73 = fmul float %62, %69
  %74 = fadd float %73, %72
  %75 = fmul float %63, %71
  %76 = fadd float %74, %75
  %77 = fmul float %61, %61
  %78 = fmul float %62, %62
  %79 = fadd float %78, %77
  %80 = fmul float %63, %63
  %81 = fadd float %79, %80
  %82 = fadd float %76, %76
  %83 = fmul float %67, %81
  %84 = fmul float %69, %81
  %85 = fmul float %71, %81
  %86 = fsub float -0.000000e+00, %83
  %87 = fmul float %82, %61
  %88 = fadd float %87, %86
  %89 = fsub float -0.000000e+00, %84
  %90 = fmul float %82, %62
  %91 = fadd float %90, %89
  %92 = fsub float -0.000000e+00, %85
  %93 = fmul float %82, %63
  %94 = fadd float %93, %92
  %95 = insertelement <4 x float> undef, float %88, i32 0
  %96 = insertelement <4 x float> %95, float %91, i32 1
  %97 = insertelement <4 x float> %96, float %94, i32 2
  %98 = insertelement <4 x float> %97, float 0.000000e+00, i32 3
  %99 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %98)
  %100 = extractelement <4 x float> %99, i32 0
  %101 = extractelement <4 x float> %99, i32 1
  %102 = extractelement <4 x float> %99, i32 2
  %103 = extractelement <4 x float> %99, i32 3
  %104 = call float @fabs(float %102)
  %105 = fdiv float 1.000000e+00, %104
  %106 = fmul float %100, %105
  %107 = fadd float %106, 1.500000e+00
  %108 = fmul float %101, %105
  %109 = fadd float %108, 1.500000e+00
  %110 = bitcast float %109 to i32
  %111 = bitcast float %107 to i32
  %112 = bitcast float %103 to i32
  %113 = insertelement <4 x i32> undef, i32 %110, i32 0
  %114 = insertelement <4 x i32> %113, i32 %111, i32 1
  %115 = insertelement <4 x i32> %114, i32 %112, i32 2
  %116 = insertelement <4 x i32> %115, i32 undef, i32 3
  %117 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %116, <32 x i8> %49, <16 x i8> %51, i32 4)
  %118 = extractelement <4 x float> %117, i32 0
  %119 = extractelement <4 x float> %117, i32 1
  %120 = extractelement <4 x float> %117, i32 2
  %121 = bitcast float %55 to i32
  %122 = bitcast float %56 to i32
  %123 = insertelement <2 x i32> undef, i32 %121, i32 0
  %124 = insertelement <2 x i32> %123, i32 %122, i32 1
  %125 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %124, <32 x i8> %41, <16 x i8> %43, i32 2)
  %126 = extractelement <4 x float> %125, i32 0
  %127 = extractelement <4 x float> %125, i32 1
  %128 = extractelement <4 x float> %125, i32 2
  %129 = extractelement <4 x float> %125, i32 3
  %130 = bitcast float %64 to i32
  %131 = bitcast float %65 to i32
  %132 = insertelement <2 x i32> undef, i32 %130, i32 0
  %133 = insertelement <2 x i32> %132, i32 %131, i32 1
  %134 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %133, <32 x i8> %45, <16 x i8> %47, i32 2)
  %135 = extractelement <4 x float> %134, i32 0
  %136 = extractelement <4 x float> %134, i32 1
  %137 = extractelement <4 x float> %134, i32 2
  %138 = fmul float %118, %39
  %139 = fmul float %119, %39
  %140 = fmul float %120, %39
  %141 = fsub float -0.000000e+00, %129
  %142 = fadd float %141, 1.000000e+00
  %143 = fmul float %126, %52
  %144 = fmul float %127, %53
  %145 = fmul float %128, %54
  %146 = fmul float %138, %142
  %147 = fmul float %139, %142
  %148 = fmul float %140, %142
  %149 = fmul float %146, %22
  %150 = fmul float %147, %23
  %151 = fmul float %148, %24
  %152 = fmul float %135, %31
  %153 = fmul float %136, %32
  %154 = fmul float %137, %33
  %155 = fsub float -0.000000e+00, %28
  %156 = fmul float %60, %30
  %157 = fadd float %156, %155
  %158 = fmul float %143, %152
  %159 = fadd float %158, %149
  %160 = fmul float %144, %153
  %161 = fadd float %160, %150
  %162 = fmul float %145, %154
  %163 = fadd float %162, %151
  %164 = fcmp uge float %157, %29
  %165 = select i1 %164, float %29, float %157
  %166 = call float @llvm.AMDIL.clamp.(float %165, float 0.000000e+00, float 1.000000e+00)
  %167 = fsub float -0.000000e+00, %38
  %168 = fmul float %159, %167
  %169 = fadd float %168, %34
  %170 = fsub float -0.000000e+00, %38
  %171 = fmul float %161, %170
  %172 = fadd float %171, %35
  %173 = fsub float -0.000000e+00, %38
  %174 = fmul float %163, %173
  %175 = fadd float %174, %36
  %176 = fmul float %166, %166
  %177 = fmul float %169, %176
  %178 = fmul float %172, %176
  %179 = fmul float %175, %176
  %180 = fmul float %159, %38
  %181 = fadd float %180, %177
  %182 = fmul float %161, %38
  %183 = fadd float %182, %178
  %184 = fmul float %163, %38
  %185 = fadd float %184, %179
  %186 = fmul float %60, %37
  %187 = call i32 @llvm.SI.packf16(float %181, float %183)
  %188 = bitcast i32 %187 to float
  %189 = call i32 @llvm.SI.packf16(float %185, float %186)
  %190 = bitcast i32 %189 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %188, float %190, float %188, float %190)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR5, %VGPR5, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR4, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR6, %VGPR6, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 41
	S_WAITCNT 127
	%VGPR10<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR10, %VGPR7, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 40
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR5, %VGPR9, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR4, %VGPR10<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 42
	S_WAITCNT 127
	%VGPR10<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR6, %VGPR10, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e32 %VGPR11<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR11, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %VGPR4<kill>, %VGPR8<kill>, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-def>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR11, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-use,kill>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-def>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-use,kill>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-def>
	%VGPR15<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-use,kill>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-def>
	%VGPR5<def> = V_CUBESC_F32 %VGPR12, %VGPR13, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR4<def> = V_CUBETC_F32 %VGPR12, %VGPR13, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR6<def> = V_CUBEMA_F32 %VGPR12, %VGPR13, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR7<def> = V_CUBEID_F32 %VGPR12, %VGPR13, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR12<def> = V_ADD_F32_e64 %VGPR6, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_RCP_F32_e32 %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR4, %VGPR12, %VGPR13, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR5<def> = V_MAD_F32 %VGPR5, %VGPR12<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR8<def> = KILL %VGPR8<undef>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%50](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%48](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6_VGPR7_VGPR8, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 122
	S_WAITCNT 112
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0, %VGPR5, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%42](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%40](tbaa=!"const")
	S_WAITCNT 127
	%VGPR7_VGPR8_VGPR9_VGPR10<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR11<def> = V_SUB_F32_e32 1.000000e+00, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR11, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR2, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-def>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<tied0>, %VGPR3, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR2, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<tied0>, %VGPR3, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%46](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%44](tbaa=!"const")
	S_WAITCNT 127
	%VGPR12_VGPR13_VGPR14<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR12_VGPR13<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 112
	%VGPR2<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR8, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR3<kill>, %VGPR2<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 120
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR1, %VGPR15, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 117
	S_WAITCNT 127
	%VGPR16<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR17<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR15<kill>, %SGPR1, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %SGPR0, %VGPR4, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR11, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR16<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR17<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR18<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR18<def,tied1> = V_INTERP_P2_F32 %VGPR18<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR7, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR18<kill>, %VGPR17<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %SGPR1, %VGPR16, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 116
	S_WAITCNT 127
	%VGPR17<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR16<kill>, %SGPR1, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR16<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6<imp-use,kill>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR14, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14<imp-use,kill>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR9, %VGPR6<kill>, %EXEC<imp-use>, %VGPR7_VGPR8_VGPR9_VGPR10<imp-use,kill>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR1, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 118
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR1<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 119
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR15<kill>, %VGPR0<kill>, %VGPR15, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8101200
c8111201
c8140e00
c8150e01
100c0b05
d2820007
041a0904
c8181600
c8191601
d2820007
041e0d06
c8200900
c8210901
c0840100
bf8c007f
c2000929
bf8c007f
08141000
10100f0a
c8240800
c8250801
c2000928
bf8c007f
08121200
10161305
d282000b
042e1504
c8280a00
c8290a01
c200092a
bf8c007f
08141400
d282000b
042e1506
0616170b
1008090b
081a1104
10080f09
100a0b0b
08180905
10080f0a
100a0d0b
081c0905
7e1e0280
d28a0005
043a1b0c
d28c0004
043a1b0c
d28e0006
043a1b0c
d2880007
043a1b0c
d206010c
02010106
7e18550c
7e1a02ff
3fc00000
d2820006
04361904
d2820005
04361905
c0860308
c0c80510
bf8c007f
f0800700
00640405
c200097a
bf8c0070
10180a00
c8200500
c8210501
c81c0400
c81d0401
c0860300
c0c80500
bf8c007f
f0800f00
00640707
bf8c0770
081614f2
1018170c
c2008901
bf8c007f
101e1801
c8341902
c8351903
c8301802
c8311803
c0860304
c0c80508
bf8c007f
f0800700
00640c0c
c2008931
bf8c0070
10041a01
c80c0100
c80d0101
10060708
d282000f
043e0503
c2008978
bf8c007f
10041e01
c2010975
bf8c007f
08200402
c8080b00
c8090b01
c201092f
bf8c007f
10060402
c201092c
bf8c007f
0a060602
c201092e
bf8c007f
d00c0004
02000503
7e220202
d2000003
00122303
d2060803
02010103
10060703
10200710
d282000f
0440030f
10200800
10201710
c2010900
bf8c007f
10202002
c2010930
bf8c007f
10221802
c8480000
c8490001
10242507
d2820010
04422312
10222001
c2010974
bf8c007f
08222202
10220711
d2820010
04440310
5e1e1f10
10080c00
10081704
c2000902
bf8c007f
10080800
c2000932
bf8c007f
100a1c00
c8180200
c8190201
10000d09
d2820000
04120b00
10020001
c2000976
bf8c007f
08020200
10020701
d2820000
04040300
c2000977
bf8c007f
10020400
5e000300
f8001c0f
000f000f
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL OUT[7], GENERIC[23]
DCL OUT[8], GENERIC[24]
DCL CONST[0..51]
DCL TEMP[0..11], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[6]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: DP4 TEMP[5].x, TEMP[0], CONST[7]
 12: MOV TEMP[2].w, TEMP[5].xxxx
 13: DP4 TEMP[0].x, TEMP[0], CONST[12]
 14: DP3 TEMP[6].x, IN[1].xyzz, CONST[48].xyzz
 15: MOV TEMP[6].z, TEMP[6].xxxx
 16: DP3 TEMP[7].x, IN[1].xyzz, CONST[49].xyzz
 17: MOV TEMP[7].z, TEMP[7].xxxx
 18: DP3 TEMP[8].x, IN[1].xyzz, CONST[50].xyzz
 19: MOV TEMP[8].z, TEMP[8].xxxx
 20: DP3 TEMP[6].x, IN[4].xyzz, CONST[48].xyzz
 21: DP3 TEMP[7].x, IN[4].xyzz, CONST[49].xyzz
 22: DP3 TEMP[8].x, IN[4].xyzz, CONST[50].xyzz
 23: DP3 TEMP[9].x, IN[5].xyzz, CONST[48].xyzz
 24: MOV TEMP[6].y, TEMP[9].xxxx
 25: DP3 TEMP[9].x, IN[5].xyzz, CONST[49].xyzz
 26: MOV TEMP[7].y, TEMP[9].xxxx
 27: DP3 TEMP[9].x, IN[5].xyzz, CONST[50].xyzz
 28: MOV TEMP[8].y, TEMP[9].xxxx
 29: MOV TEMP[1].w, TEMP[0].xxxx
 30: MOV TEMP[0].xy, IN[2].xyxx
 31: MUL TEMP[9], IN[3].xyxx, CONST[0].yyxx
 32: MAD TEMP[10], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 33: MOV TEMP[11], TEMP[2]
 34: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[5].xxxx
 35: MOV TEMP[2].z, TEMP[4].xxxx
 36: MOV TEMP[2].y, -TEMP[3].xxxx
 37: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[5].xxxx, TEMP[2].xyyy
 38: MOV OUT[3], TEMP[0]
 39: MOV OUT[8], TEMP[9]
 40: MOV OUT[0], TEMP[2]
 41: MOV OUT[4], TEMP[1]
 42: MOV OUT[2], TEMP[11]
 43: MOV OUT[5], TEMP[6]
 44: MOV OUT[6], TEMP[7]
 45: MOV_SAT OUT[1], TEMP[10]
 46: MOV OUT[7], TEMP[8]
 47: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 764)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 776)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 792)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 800)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 804)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 808)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 812)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 816)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 820)
  %49 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0
  %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %5)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = extractelement <4 x float> %51, i32 1
  %54 = extractelement <4 x float> %51, i32 2
  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %5)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = extractelement <4 x float> %57, i32 2
  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
  %64 = extractelement <4 x float> %63, i32 0
  %65 = extractelement <4 x float> %63, i32 1
  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
  %69 = extractelement <4 x float> %68, i32 0
  %70 = extractelement <4 x float> %68, i32 1
  %71 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
  %73 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %72, i32 0, i32 %5)
  %74 = extractelement <4 x float> %73, i32 0
  %75 = extractelement <4 x float> %73, i32 1
  %76 = extractelement <4 x float> %73, i32 2
  %77 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
  %78 = load <16 x i8> addrspace(2)* %77, !tbaa !0
  %79 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %78, i32 0, i32 %5)
  %80 = extractelement <4 x float> %79, i32 0
  %81 = extractelement <4 x float> %79, i32 1
  %82 = extractelement <4 x float> %79, i32 2
  %83 = fmul float %52, %12
  %84 = fadd float %83, %11
  %85 = fmul float %53, %12
  %86 = fadd float %85, %11
  %87 = fmul float %54, %12
  %88 = fadd float %87, %11
  %89 = fmul float %52, %11
  %90 = fadd float %89, %12
  %91 = fmul float %84, %35
  %92 = fmul float %86, %36
  %93 = fadd float %91, %92
  %94 = fmul float %88, %37
  %95 = fadd float %93, %94
  %96 = fmul float %90, %38
  %97 = fadd float %95, %96
  %98 = fmul float %84, %39
  %99 = fmul float %86, %40
  %100 = fadd float %98, %99
  %101 = fmul float %88, %41
  %102 = fadd float %100, %101
  %103 = fmul float %90, %42
  %104 = fadd float %102, %103
  %105 = fmul float %84, %43
  %106 = fmul float %86, %44
  %107 = fadd float %105, %106
  %108 = fmul float %88, %45
  %109 = fadd float %107, %108
  %110 = fmul float %90, %46
  %111 = fadd float %109, %110
  %112 = fmul float %84, %14
  %113 = fmul float %86, %15
  %114 = fadd float %112, %113
  %115 = fmul float %88, %16
  %116 = fadd float %114, %115
  %117 = fmul float %90, %17
  %118 = fadd float %116, %117
  %119 = fmul float %84, %18
  %120 = fmul float %86, %19
  %121 = fadd float %119, %120
  %122 = fmul float %88, %20
  %123 = fadd float %121, %122
  %124 = fmul float %90, %21
  %125 = fadd float %123, %124
  %126 = fmul float %84, %22
  %127 = fmul float %86, %23
  %128 = fadd float %126, %127
  %129 = fmul float %88, %24
  %130 = fadd float %128, %129
  %131 = fmul float %90, %25
  %132 = fadd float %130, %131
  %133 = fmul float %84, %26
  %134 = fmul float %86, %27
  %135 = fadd float %133, %134
  %136 = fmul float %88, %28
  %137 = fadd float %135, %136
  %138 = fmul float %90, %29
  %139 = fadd float %137, %138
  %140 = fmul float %84, %30
  %141 = fmul float %86, %31
  %142 = fadd float %140, %141
  %143 = fmul float %88, %32
  %144 = fadd float %142, %143
  %145 = fmul float %90, %33
  %146 = fadd float %144, %145
  %147 = fmul float %58, %35
  %148 = fmul float %59, %36
  %149 = fadd float %148, %147
  %150 = fmul float %60, %37
  %151 = fadd float %149, %150
  %152 = fmul float %58, %39
  %153 = fmul float %59, %40
  %154 = fadd float %153, %152
  %155 = fmul float %60, %41
  %156 = fadd float %154, %155
  %157 = fmul float %58, %43
  %158 = fmul float %59, %44
  %159 = fadd float %158, %157
  %160 = fmul float %60, %45
  %161 = fadd float %159, %160
  %162 = fmul float %74, %35
  %163 = fmul float %75, %36
  %164 = fadd float %163, %162
  %165 = fmul float %76, %37
  %166 = fadd float %164, %165
  %167 = fmul float %74, %39
  %168 = fmul float %75, %40
  %169 = fadd float %168, %167
  %170 = fmul float %76, %41
  %171 = fadd float %169, %170
  %172 = fmul float %74, %43
  %173 = fmul float %75, %44
  %174 = fadd float %173, %172
  %175 = fmul float %76, %45
  %176 = fadd float %174, %175
  %177 = fmul float %80, %35
  %178 = fmul float %81, %36
  %179 = fadd float %178, %177
  %180 = fmul float %82, %37
  %181 = fadd float %179, %180
  %182 = fmul float %80, %39
  %183 = fmul float %81, %40
  %184 = fadd float %183, %182
  %185 = fmul float %82, %41
  %186 = fadd float %184, %185
  %187 = fmul float %80, %43
  %188 = fmul float %81, %44
  %189 = fadd float %188, %187
  %190 = fmul float %82, %45
  %191 = fadd float %189, %190
  %192 = fmul float %69, %12
  %193 = fmul float %70, %12
  %194 = fmul float %69, %11
  %195 = fmul float %69, %11
  %196 = fmul float %34, %11
  %197 = fadd float %196, %12
  %198 = fmul float %34, %11
  %199 = fadd float %198, %12
  %200 = fmul float %34, %11
  %201 = fadd float %200, %12
  %202 = fmul float %34, %12
  %203 = fadd float %202, %11
  %204 = fsub float -0.000000e+00, %139
  %205 = fmul float %132, %13
  %206 = fadd float %205, %204
  %207 = fsub float -0.000000e+00, %125
  %208 = fmul float %47, %139
  %209 = fadd float %208, %118
  %210 = fmul float %48, %139
  %211 = fadd float %210, %207
  %212 = call float @llvm.AMDIL.clamp.(float %197, float 0.000000e+00, float 1.000000e+00)
  %213 = call float @llvm.AMDIL.clamp.(float %199, float 0.000000e+00, float 1.000000e+00)
  %214 = call float @llvm.AMDIL.clamp.(float %201, float 0.000000e+00, float 1.000000e+00)
  %215 = call float @llvm.AMDIL.clamp.(float %203, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %212, float %213, float %214, float %215)
  %216 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %217 = load <16 x i8> addrspace(2)* %216, !tbaa !0
  %218 = call float @llvm.SI.load.const(<16 x i8> %217, i32 0)
  %219 = fmul float %218, %118
  %220 = call float @llvm.SI.load.const(<16 x i8> %217, i32 4)
  %221 = fmul float %220, %125
  %222 = fadd float %219, %221
  %223 = call float @llvm.SI.load.const(<16 x i8> %217, i32 8)
  %224 = fmul float %223, %132
  %225 = fadd float %222, %224
  %226 = call float @llvm.SI.load.const(<16 x i8> %217, i32 12)
  %227 = fmul float %226, %139
  %228 = fadd float %225, %227
  %229 = call float @llvm.SI.load.const(<16 x i8> %217, i32 16)
  %230 = fmul float %229, %118
  %231 = call float @llvm.SI.load.const(<16 x i8> %217, i32 20)
  %232 = fmul float %231, %125
  %233 = fadd float %230, %232
  %234 = call float @llvm.SI.load.const(<16 x i8> %217, i32 24)
  %235 = fmul float %234, %132
  %236 = fadd float %233, %235
  %237 = call float @llvm.SI.load.const(<16 x i8> %217, i32 28)
  %238 = fmul float %237, %139
  %239 = fadd float %236, %238
  %240 = call float @llvm.SI.load.const(<16 x i8> %217, i32 32)
  %241 = fmul float %240, %118
  %242 = call float @llvm.SI.load.const(<16 x i8> %217, i32 36)
  %243 = fmul float %242, %125
  %244 = fadd float %241, %243
  %245 = call float @llvm.SI.load.const(<16 x i8> %217, i32 40)
  %246 = fmul float %245, %132
  %247 = fadd float %244, %246
  %248 = call float @llvm.SI.load.const(<16 x i8> %217, i32 44)
  %249 = fmul float %248, %139
  %250 = fadd float %247, %249
  %251 = call float @llvm.SI.load.const(<16 x i8> %217, i32 48)
  %252 = fmul float %251, %118
  %253 = call float @llvm.SI.load.const(<16 x i8> %217, i32 52)
  %254 = fmul float %253, %125
  %255 = fadd float %252, %254
  %256 = call float @llvm.SI.load.const(<16 x i8> %217, i32 56)
  %257 = fmul float %256, %132
  %258 = fadd float %255, %257
  %259 = call float @llvm.SI.load.const(<16 x i8> %217, i32 60)
  %260 = fmul float %259, %139
  %261 = fadd float %258, %260
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %228, float %239, float %250, float %261)
  %262 = call float @llvm.SI.load.const(<16 x i8> %217, i32 64)
  %263 = fmul float %262, %118
  %264 = call float @llvm.SI.load.const(<16 x i8> %217, i32 68)
  %265 = fmul float %264, %125
  %266 = fadd float %263, %265
  %267 = call float @llvm.SI.load.const(<16 x i8> %217, i32 72)
  %268 = fmul float %267, %132
  %269 = fadd float %266, %268
  %270 = call float @llvm.SI.load.const(<16 x i8> %217, i32 76)
  %271 = fmul float %270, %139
  %272 = fadd float %269, %271
  %273 = call float @llvm.SI.load.const(<16 x i8> %217, i32 80)
  %274 = fmul float %273, %118
  %275 = call float @llvm.SI.load.const(<16 x i8> %217, i32 84)
  %276 = fmul float %275, %125
  %277 = fadd float %274, %276
  %278 = call float @llvm.SI.load.const(<16 x i8> %217, i32 88)
  %279 = fmul float %278, %132
  %280 = fadd float %277, %279
  %281 = call float @llvm.SI.load.const(<16 x i8> %217, i32 92)
  %282 = fmul float %281, %139
  %283 = fadd float %280, %282
  %284 = call float @llvm.SI.load.const(<16 x i8> %217, i32 96)
  %285 = fmul float %284, %118
  %286 = call float @llvm.SI.load.const(<16 x i8> %217, i32 100)
  %287 = fmul float %286, %125
  %288 = fadd float %285, %287
  %289 = call float @llvm.SI.load.const(<16 x i8> %217, i32 104)
  %290 = fmul float %289, %132
  %291 = fadd float %288, %290
  %292 = call float @llvm.SI.load.const(<16 x i8> %217, i32 108)
  %293 = fmul float %292, %139
  %294 = fadd float %291, %293
  %295 = call float @llvm.SI.load.const(<16 x i8> %217, i32 112)
  %296 = fmul float %295, %118
  %297 = call float @llvm.SI.load.const(<16 x i8> %217, i32 116)
  %298 = fmul float %297, %125
  %299 = fadd float %296, %298
  %300 = call float @llvm.SI.load.const(<16 x i8> %217, i32 120)
  %301 = fmul float %300, %132
  %302 = fadd float %299, %301
  %303 = call float @llvm.SI.load.const(<16 x i8> %217, i32 124)
  %304 = fmul float %303, %139
  %305 = fadd float %302, %304
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %272, float %283, float %294, float %305)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %64, float %65, float %88, float %90)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %97, float %104, float %111, float %146)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %166, float %181, float %151, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %171, float %186, float %156, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %176, float %191, float %161, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %192, float %193, float %194, float %195)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %209, float %211, float %206, float %139)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 191
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR4, %VGPR1, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%49](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR9, %SGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR10, %SGPR2, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8, %SGPR3, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 19
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 23
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%216](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 27
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 9
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 11
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 29
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 28
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 30
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 31
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 25
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 24
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 26
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 27
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 21
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 20
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 22
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 23
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 17
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 16
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 18
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 19
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%61](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR7, %VGPR8, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 51
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 201
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0, %VGPR6, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 200
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 202
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR7, %SGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 203
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR8, %SGPR5<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR5, %VGPR6, %EXEC<imp-use>
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR12, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 198
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR7, %SGPR13, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 199
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR8, %SGPR14<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR14, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR16<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR5<kill>, %SGPR16, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 194
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR7<kill>, %SGPR15, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 195
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR8<kill>, %SGPR17<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR5<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%55](tbaa=!"const")
	S_WAITCNT 15
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR20_SGPR21_SGPR22_SGPR23<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR9<def> = V_MUL_F32_e32 %SGPR16, %VGPR5, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR6, %SGPR14, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR7, %SGPR15, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%77](tbaa=!"const")
	S_WAITCNT 127
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR20_SGPR21_SGPR22_SGPR23<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR13<def> = V_MUL_F32_e32 %SGPR16, %VGPR9, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR10, %SGPR14, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR11, %SGPR15, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 16; mem:LD16[%71](tbaa=!"const")
	S_WAITCNT 127
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR20_SGPR21_SGPR22_SGPR23<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR17<def> = V_MUL_F32_e32 %SGPR16<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR14, %SGPR14<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR15, %SGPR15<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR20<kill>, %VGPR19<kill>, %VGPR18<kill>, %VGPR17, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR18<def> = V_MUL_F32_e32 %SGPR12, %VGPR5, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR6, %SGPR5, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR7, %SGPR13, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %SGPR12, %VGPR9, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR10, %SGPR5, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR11, %SGPR13, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %SGPR12<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR14, %SGPR5<kill>, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR15, %SGPR13<kill>, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 36, 0, 0, 0, %VGPR20<kill>, %VGPR19<kill>, %VGPR18<kill>, %VGPR17, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR18<def> = V_MUL_F32_e32 %SGPR1, %VGPR5, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR6, %SGPR0, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR7, %SGPR4, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR1, %VGPR9, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR10, %SGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR11, %SGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR14, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR15, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	EXP 15, 37, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR17<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 12; mem:LD16[%66](tbaa=!"const")
	S_WAITCNT 15
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR2, %VGPR6, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR5, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	EXP 15, 38, 0, 0, 0, %VGPR5<kill>, %VGPR9<kill>, %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 204
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 205
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840100
bf8c007f
c20209bf
c2018900
bf8c007f
7e040203
c2010901
bf8c007f
7e020202
d2820003
040a0204
d2060803
02010103
d2820004
04060404
d2060804
02010104
f800020f
03040404
c0860700
bf8c000f
e00c2000
80030800
bf8c0770
d2820005
04080508
d2820006
04080509
c2020911
bf8c007f
10060c04
c2020910
bf8c007f
d2820003
040c0905
d2820007
0408050a
c2020912
bf8c007f
d2820002
040c0907
d2820008
04040708
c2020913
bf8c007f
d2820001
04080908
c2020915
bf8c007f
10040c04
c2020914
bf8c007f
d2820002
04080905
c2020916
bf8c007f
d2820002
04080907
c2020917
bf8c007f
d2820002
04080908
c0860104
bf8c007f
c2000d0d
bf8c007f
10060400
c2000d0c
bf8c007f
d2820004
040e0200
c2000919
bf8c007f
10060c00
c2000918
bf8c007f
d2820003
040c0105
c200091a
bf8c007f
d2820003
040c0107
c200091b
bf8c007f
d2820003
040c0108
c2000d0e
bf8c007f
d2820009
04120600
c200091d
bf8c007f
10080c00
c200091c
bf8c007f
d2820004
04100105
c200091e
bf8c007f
d2820004
04100107
c200091f
bf8c007f
d2820004
04100108
c2000d0f
bf8c007f
d2820009
04260800
c2000d09
bf8c007f
10140400
c2000d08
bf8c007f
d282000a
042a0200
c2000d0a
bf8c007f
d282000a
042a0600
c2000d0b
bf8c007f
d282000a
042a0800
c2000d05
bf8c007f
10160400
c2000d04
bf8c007f
d282000b
042e0200
c2000d06
bf8c007f
d282000b
042e0600
c2000d07
bf8c007f
d282000b
042e0800
c2000d01
bf8c007f
10180400
c2000d00
bf8c007f
d282000c
04320200
c2000d02
bf8c007f
d282000c
04320600
c2000d03
bf8c007f
d282000c
04320800
f80000ef
090a0b0c
c2000d1d
bf8c000f
10120400
c2000d1c
bf8c007f
d2820009
04260200
c2000d1e
bf8c007f
d2820009
04260600
c2000d1f
bf8c007f
d2820009
04260800
c2000d19
bf8c007f
10140400
c2000d18
bf8c007f
d282000a
042a0200
c2000d1a
bf8c007f
d282000a
042a0600
c2000d1b
bf8c007f
d282000a
042a0800
c2000d15
bf8c007f
10160400
c2000d14
bf8c007f
d282000b
042e0200
c2000d16
bf8c007f
d282000b
042e0600
c2000d17
bf8c007f
d282000b
042e0800
c2000d11
bf8c007f
10180400
c2000d10
bf8c007f
d282000c
04320200
c2000d12
bf8c007f
d282000c
04320600
c2000d13
bf8c007f
d282000c
04320800
f80000ff
090a0b0c
c0860708
bf8c000f
e00c2000
80030900
bf8c0770
f800021f
08070a09
c2000931
bf8c000f
10120c00
c2000930
bf8c007f
d2820009
04240105
c2000932
bf8c007f
d2820009
04240107
c2000933
bf8c007f
d2820009
04240108
c20009c9
bf8c007f
10140c00
c20089c8
bf8c007f
d282000a
04280305
c20209ca
bf8c007f
d282000a
04280907
c20289cb
bf8c007f
d282000a
04280b08
c20289c5
bf8c007f
10160c05
c20609c4
bf8c007f
d282000b
042c1905
c20689c6
bf8c007f
d282000b
042c1b07
c20709c7
bf8c007f
d282000b
042c1d08
c20709c1
bf8c007f
100c0c0e
c20809c0
bf8c007f
d2820005
04182105
c20789c2
bf8c007f
d2820005
04141f07
c20889c3
bf8c007f
d2820005
04142308
f800022f
090a0b05
c08a0704
bf8c000f
e00c2000
80050500
bf8c0770
10120a10
d2820009
04241d06
d2820012
04241f07
c08a0714
bf8c007f
e00c2000
80050900
bf8c0770
101a1210
d282000d
04341d0a
d2820013
04341f0b
c08a0710
bf8c007f
e00c2000
80050d00
bf8c0770
10221a10
d2820011
04441d0e
d2820014
04441f0f
7e220280
f800023f
11121314
bf8c070f
10240a0c
d2820012
04480b06
d2820012
04481b07
1026120c
d2820013
044c0b0a
d2820013
044c1b0b
10281a0c
d2820014
04500b0e
d2820014
04501b0f
f800024f
11121314
bf8c070f
10240a01
d2820012
04480106
d2820005
04480907
100c1201
d2820006
0418010a
d2820006
0418090b
100e1a01
d2820007
041c010e
d2820007
041c090f
f800025f
11050607
c082070c
bf8c000f
e00c2000
80010500
bf8c0770
10000a03
10120c02
100a0a02
f800026f
00000905
c20009cc
bf8c000f
d2820000
04060800
c2000902
bf8c007f
10020600
08020901
c20009cd
bf8c007f
10060800
08040503
f80008cf
04010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..30]
DCL TEMP[0..3], LOCAL
DCL TEMP[4], ARRAY(1), LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MOV TEMP[1].xy, IN[3].xyyy
  3: TEX TEMP[2].xyz, TEMP[1], SAMP[1], 2D
  4: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[12].xyzz
  5: MAD TEMP[3].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
  6: MUL TEMP[1].xyz, TEMP[0].xyzz, IN[0].xyzz
  7: MIN TEMP[3].x, TEMP[3].xxxx, CONST[11].zzzz
  8: MOV_SAT TEMP[3].x, TEMP[3].xxxx
  9: MUL TEMP[1].xyz, TEMP[2].xyzz, TEMP[1].xyzz
 10: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[3].xxxx
 11: MAD TEMP[2].xyz, TEMP[1].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 12: MUL TEMP[2].xyz, TEMP[3].xxxx, TEMP[2].xyzz
 13: MUL TEMP[3].x, IN[0].wwww, CONST[12].wwww
 14: MAD TEMP[1].xyz, TEMP[1].xyzz, CONST[30].xxxx, TEMP[2].xyzz
 15: MUL TEMP[0].x, TEMP[0].wwww, TEMP[3].xxxx
 16: MOV TEMP[1].w, TEMP[0].xxxx
 17: MOV TEMP[4], TEMP[1]
 18: MOV OUT[0], TEMP[4]
 19: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 188)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 204)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %33 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0
  %35 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %43 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %44 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %45 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %46 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %47 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %48 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %6)
  %49 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %6)
  %50 = bitcast float %45 to i32
  %51 = bitcast float %46 to i32
  %52 = insertelement <2 x i32> undef, i32 %50, i32 0
  %53 = insertelement <2 x i32> %52, i32 %51, i32 1
  %54 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %53, <32 x i8> %34, <16 x i8> %36, i32 2)
  %55 = extractelement <4 x float> %54, i32 0
  %56 = extractelement <4 x float> %54, i32 1
  %57 = extractelement <4 x float> %54, i32 2
  %58 = extractelement <4 x float> %54, i32 3
  %59 = bitcast float %48 to i32
  %60 = bitcast float %49 to i32
  %61 = insertelement <2 x i32> undef, i32 %59, i32 0
  %62 = insertelement <2 x i32> %61, i32 %60, i32 1
  %63 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %62, <32 x i8> %38, <16 x i8> %40, i32 2)
  %64 = extractelement <4 x float> %63, i32 0
  %65 = extractelement <4 x float> %63, i32 1
  %66 = extractelement <4 x float> %63, i32 2
  %67 = fmul float %64, %25
  %68 = fmul float %65, %26
  %69 = fmul float %66, %27
  %70 = fsub float -0.000000e+00, %22
  %71 = fmul float %47, %24
  %72 = fadd float %71, %70
  %73 = fmul float %55, %41
  %74 = fmul float %56, %42
  %75 = fmul float %57, %43
  %76 = fcmp uge float %72, %23
  %77 = select i1 %76, float %23, float %72
  %78 = call float @llvm.AMDIL.clamp.(float %77, float 0.000000e+00, float 1.000000e+00)
  %79 = fmul float %67, %73
  %80 = fmul float %68, %74
  %81 = fmul float %69, %75
  %82 = fmul float %78, %78
  %83 = fsub float -0.000000e+00, %32
  %84 = fmul float %79, %83
  %85 = fadd float %84, %29
  %86 = fsub float -0.000000e+00, %32
  %87 = fmul float %80, %86
  %88 = fadd float %87, %30
  %89 = fsub float -0.000000e+00, %32
  %90 = fmul float %81, %89
  %91 = fadd float %90, %31
  %92 = fmul float %82, %85
  %93 = fmul float %82, %88
  %94 = fmul float %82, %91
  %95 = fmul float %44, %28
  %96 = fmul float %79, %32
  %97 = fadd float %96, %92
  %98 = fmul float %80, %32
  %99 = fadd float %98, %93
  %100 = fmul float %81, %32
  %101 = fadd float %100, %94
  %102 = fmul float %58, %95
  %103 = call i32 @llvm.SI.packf16(float %97, float %99)
  %104 = bitcast i32 %103 to float
  %105 = call i32 @llvm.SI.packf16(float %101, float %102)
  %106 = bitcast i32 %105 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %104, float %106, float %104, float %106)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%35](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%33](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6_VGPR7<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR11<def> = V_MUL_F32_e32 %VGPR5, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR2, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<tied0>, %VGPR3, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR2, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR3, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%39](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%37](tbaa=!"const")
	S_WAITCNT 127
	%VGPR8_VGPR9_VGPR10<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR8_VGPR9<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 49
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 120
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4, %VGPR3, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 117
	S_WAITCNT 127
	%VGPR11<def> = V_SUB_F32_e32 %SGPR5<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 47
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 44
	S_WAITCNT 127
	%VGPR2<def> = V_SUBREV_F32_e32 %SGPR5<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 46
	S_WAITCNT 127
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR12<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR2, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %SGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR4, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 48
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4, %VGPR11, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 116
	S_WAITCNT 127
	%VGPR12<def> = V_SUB_F32_e32 %SGPR5<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR2, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %SGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR11<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR6, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 50
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR10, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10<imp-use,kill>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4, %VGPR8, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 118
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e32 %SGPR5<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR8<kill>, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 51
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR7, %VGPR0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7<imp-use,kill>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR0<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR3<kill>, %VGPR0<kill>, %VGPR3, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140500
c8150501
c8100400
c8110401
c0840300
c0c60500
bf8c007f
f0800f00
00430404
c8200100
c8210101
bf8c0770
10161105
c8240d02
c8250d03
c8200c02
c8210c03
c0840304
c0c60508
bf8c007f
f0800700
00430808
c0800100
bf8c0070
c2020131
bf8c007f
10041204
10061702
c2020178
bf8c007f
10040604
c2028175
bf8c007f
08160405
c8080b00
c8090b01
c202812f
bf8c007f
10040405
c202812c
bf8c007f
0a040405
c202812e
bf8c007f
d00c0008
02000b02
7e180205
d2000002
00221902
d2060802
02010102
10040502
10161702
d2820003
042c0903
c82c0000
c82d0001
10161704
c2028130
bf8c007f
10181005
1016170c
10181604
c2028174
bf8c007f
08181805
10181902
d282000b
0430090b
5e06070b
c82c0200
c82d0201
10161706
c2028132
bf8c007f
10101405
10101708
10121004
c2028176
bf8c007f
08121205
10041302
d2820002
04080908
c8200300
c8210301
c2000133
bf8c007f
10001000
10000107
5e000102
f8001c0f
00030003
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL CONST[0..20]
DCL TEMP[0..7], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[17]
  2: DP4 TEMP[2].x, TEMP[0], CONST[18]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[19]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[12]
 10: DP4 TEMP[5].x, TEMP[0], CONST[6]
 11: MOV TEMP[2].z, TEMP[5].xxxx
 12: DP4 TEMP[0].x, TEMP[0], CONST[7]
 13: MOV TEMP[2].w, TEMP[0].xxxx
 14: MOV TEMP[1].w, TEMP[4].xxxx
 15: MOV TEMP[4].xy, IN[1].xyxx
 16: MUL TEMP[6], IN[2].xyxx, CONST[0].yyxx
 17: MOV TEMP[7], TEMP[2]
 18: MAD TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
 19: MOV TEMP[2].z, TEMP[5].xxxx
 20: MOV TEMP[2].y, -TEMP[3].xxxx
 21: MAD TEMP[2].xy, CONST[20].xyyy, TEMP[0].xxxx, TEMP[2].xyyy
 22: MOV OUT[3], TEMP[4]
 23: MOV OUT[5], TEMP[6]
 24: MOV OUT[0], TEMP[2]
 25: MOV OUT[4], TEMP[1]
 26: MOV OUT[2], TEMP[7]
 27: MOV_SAT OUT[1], IN[3]
 28: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 284)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 300)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 316)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
  %48 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %5)
  %51 = extractelement <4 x float> %50, i32 0
  %52 = extractelement <4 x float> %50, i32 1
  %53 = extractelement <4 x float> %50, i32 2
  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
  %57 = extractelement <4 x float> %56, i32 0
  %58 = extractelement <4 x float> %56, i32 1
  %59 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
  %61 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %60, i32 0, i32 %5)
  %62 = extractelement <4 x float> %61, i32 0
  %63 = extractelement <4 x float> %61, i32 1
  %64 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
  %66 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %65, i32 0, i32 %5)
  %67 = extractelement <4 x float> %66, i32 0
  %68 = extractelement <4 x float> %66, i32 1
  %69 = extractelement <4 x float> %66, i32 2
  %70 = extractelement <4 x float> %66, i32 3
  %71 = fmul float %51, %12
  %72 = fadd float %71, %11
  %73 = fmul float %52, %12
  %74 = fadd float %73, %11
  %75 = fmul float %53, %12
  %76 = fadd float %75, %11
  %77 = fmul float %51, %11
  %78 = fadd float %77, %12
  %79 = fmul float %72, %34
  %80 = fmul float %74, %35
  %81 = fadd float %79, %80
  %82 = fmul float %76, %36
  %83 = fadd float %81, %82
  %84 = fmul float %78, %37
  %85 = fadd float %83, %84
  %86 = fmul float %72, %38
  %87 = fmul float %74, %39
  %88 = fadd float %86, %87
  %89 = fmul float %76, %40
  %90 = fadd float %88, %89
  %91 = fmul float %78, %41
  %92 = fadd float %90, %91
  %93 = fmul float %72, %42
  %94 = fmul float %74, %43
  %95 = fadd float %93, %94
  %96 = fmul float %76, %44
  %97 = fadd float %95, %96
  %98 = fmul float %78, %45
  %99 = fadd float %97, %98
  %100 = fmul float %72, %14
  %101 = fmul float %74, %15
  %102 = fadd float %100, %101
  %103 = fmul float %76, %16
  %104 = fadd float %102, %103
  %105 = fmul float %78, %17
  %106 = fadd float %104, %105
  %107 = fmul float %72, %18
  %108 = fmul float %74, %19
  %109 = fadd float %107, %108
  %110 = fmul float %76, %20
  %111 = fadd float %109, %110
  %112 = fmul float %78, %21
  %113 = fadd float %111, %112
  %114 = fmul float %72, %30
  %115 = fmul float %74, %31
  %116 = fadd float %114, %115
  %117 = fmul float %76, %32
  %118 = fadd float %116, %117
  %119 = fmul float %78, %33
  %120 = fadd float %118, %119
  %121 = fmul float %72, %22
  %122 = fmul float %74, %23
  %123 = fadd float %121, %122
  %124 = fmul float %76, %24
  %125 = fadd float %123, %124
  %126 = fmul float %78, %25
  %127 = fadd float %125, %126
  %128 = fmul float %72, %26
  %129 = fmul float %74, %27
  %130 = fadd float %128, %129
  %131 = fmul float %76, %28
  %132 = fadd float %130, %131
  %133 = fmul float %78, %29
  %134 = fadd float %132, %133
  %135 = fmul float %62, %12
  %136 = fmul float %63, %12
  %137 = fmul float %62, %11
  %138 = fmul float %62, %11
  %139 = fsub float -0.000000e+00, %134
  %140 = fmul float %127, %13
  %141 = fadd float %140, %139
  %142 = fsub float -0.000000e+00, %113
  %143 = fmul float %46, %134
  %144 = fadd float %143, %106
  %145 = fmul float %47, %134
  %146 = fadd float %145, %142
  %147 = call float @llvm.AMDIL.clamp.(float %67, float 0.000000e+00, float 1.000000e+00)
  %148 = call float @llvm.AMDIL.clamp.(float %68, float 0.000000e+00, float 1.000000e+00)
  %149 = call float @llvm.AMDIL.clamp.(float %69, float 0.000000e+00, float 1.000000e+00)
  %150 = call float @llvm.AMDIL.clamp.(float %70, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %147, float %148, float %149, float %150)
  %151 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %152 = load <16 x i8> addrspace(2)* %151, !tbaa !0
  %153 = call float @llvm.SI.load.const(<16 x i8> %152, i32 0)
  %154 = fmul float %153, %106
  %155 = call float @llvm.SI.load.const(<16 x i8> %152, i32 4)
  %156 = fmul float %155, %113
  %157 = fadd float %154, %156
  %158 = call float @llvm.SI.load.const(<16 x i8> %152, i32 8)
  %159 = fmul float %158, %127
  %160 = fadd float %157, %159
  %161 = call float @llvm.SI.load.const(<16 x i8> %152, i32 12)
  %162 = fmul float %161, %134
  %163 = fadd float %160, %162
  %164 = call float @llvm.SI.load.const(<16 x i8> %152, i32 16)
  %165 = fmul float %164, %106
  %166 = call float @llvm.SI.load.const(<16 x i8> %152, i32 20)
  %167 = fmul float %166, %113
  %168 = fadd float %165, %167
  %169 = call float @llvm.SI.load.const(<16 x i8> %152, i32 24)
  %170 = fmul float %169, %127
  %171 = fadd float %168, %170
  %172 = call float @llvm.SI.load.const(<16 x i8> %152, i32 28)
  %173 = fmul float %172, %134
  %174 = fadd float %171, %173
  %175 = call float @llvm.SI.load.const(<16 x i8> %152, i32 32)
  %176 = fmul float %175, %106
  %177 = call float @llvm.SI.load.const(<16 x i8> %152, i32 36)
  %178 = fmul float %177, %113
  %179 = fadd float %176, %178
  %180 = call float @llvm.SI.load.const(<16 x i8> %152, i32 40)
  %181 = fmul float %180, %127
  %182 = fadd float %179, %181
  %183 = call float @llvm.SI.load.const(<16 x i8> %152, i32 44)
  %184 = fmul float %183, %134
  %185 = fadd float %182, %184
  %186 = call float @llvm.SI.load.const(<16 x i8> %152, i32 48)
  %187 = fmul float %186, %106
  %188 = call float @llvm.SI.load.const(<16 x i8> %152, i32 52)
  %189 = fmul float %188, %113
  %190 = fadd float %187, %189
  %191 = call float @llvm.SI.load.const(<16 x i8> %152, i32 56)
  %192 = fmul float %191, %127
  %193 = fadd float %190, %192
  %194 = call float @llvm.SI.load.const(<16 x i8> %152, i32 60)
  %195 = fmul float %194, %134
  %196 = fadd float %193, %195
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %163, float %174, float %185, float %196)
  %197 = call float @llvm.SI.load.const(<16 x i8> %152, i32 64)
  %198 = fmul float %197, %106
  %199 = call float @llvm.SI.load.const(<16 x i8> %152, i32 68)
  %200 = fmul float %199, %113
  %201 = fadd float %198, %200
  %202 = call float @llvm.SI.load.const(<16 x i8> %152, i32 72)
  %203 = fmul float %202, %127
  %204 = fadd float %201, %203
  %205 = call float @llvm.SI.load.const(<16 x i8> %152, i32 76)
  %206 = fmul float %205, %134
  %207 = fadd float %204, %206
  %208 = call float @llvm.SI.load.const(<16 x i8> %152, i32 80)
  %209 = fmul float %208, %106
  %210 = call float @llvm.SI.load.const(<16 x i8> %152, i32 84)
  %211 = fmul float %210, %113
  %212 = fadd float %209, %211
  %213 = call float @llvm.SI.load.const(<16 x i8> %152, i32 88)
  %214 = fmul float %213, %127
  %215 = fadd float %212, %214
  %216 = call float @llvm.SI.load.const(<16 x i8> %152, i32 92)
  %217 = fmul float %216, %134
  %218 = fadd float %215, %217
  %219 = call float @llvm.SI.load.const(<16 x i8> %152, i32 96)
  %220 = fmul float %219, %106
  %221 = call float @llvm.SI.load.const(<16 x i8> %152, i32 100)
  %222 = fmul float %221, %113
  %223 = fadd float %220, %222
  %224 = call float @llvm.SI.load.const(<16 x i8> %152, i32 104)
  %225 = fmul float %224, %127
  %226 = fadd float %223, %225
  %227 = call float @llvm.SI.load.const(<16 x i8> %152, i32 108)
  %228 = fmul float %227, %134
  %229 = fadd float %226, %228
  %230 = call float @llvm.SI.load.const(<16 x i8> %152, i32 112)
  %231 = fmul float %230, %106
  %232 = call float @llvm.SI.load.const(<16 x i8> %152, i32 116)
  %233 = fmul float %232, %113
  %234 = fadd float %231, %233
  %235 = call float @llvm.SI.load.const(<16 x i8> %152, i32 120)
  %236 = fmul float %235, %127
  %237 = fadd float %234, %236
  %238 = call float @llvm.SI.load.const(<16 x i8> %152, i32 124)
  %239 = fmul float %238, %134
  %240 = fadd float %237, %239
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %207, float %218, float %229, float %240)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %57, float %58, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %85, float %92, float %99, float %120)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %135, float %136, float %137, float %138)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %144, float %146, float %141, float %134)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%64](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_ADD_F32_e64 %VGPR4, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 %VGPR3, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR2, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 %VGPR1, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%48](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR2, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR2, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR2, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6, %SGPR3, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 19
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR2, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 23
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%151](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 27
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 9
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 11
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 29
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 28
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 30
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 31
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 25
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 24
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 26
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 27
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 21
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 20
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 22
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 23
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 17
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 16
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 18
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 19
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%54](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13<kill>, %VGPR13, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 49
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 51
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 77
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 76
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 78
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 79
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 73
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 72
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 74
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 75
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 69
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 68
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 70
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 71
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR2<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 8; mem:LD16[%59](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	EXP 15, 35, 0, 0, 0, %VGPR4<kill>, %VGPR2<kill>, %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 80
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 81
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c084070c
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0840700
bf8c000f
e00c2000
80020600
c0840100
bf8c0070
c2010901
c2018900
bf8c007f
7e020203
d2820002
04040506
d2820004
04040507
c2020911
bf8c007f
10060804
c2020910
bf8c007f
d2820003
040c0902
d2820005
04040508
c2020912
bf8c007f
d2820001
040c0905
7e060202
d2820006
040c0706
c2020913
bf8c007f
d2820001
04040906
c2020915
bf8c007f
10060804
c2020914
bf8c007f
d2820003
040c0902
c2020916
bf8c007f
d2820003
040c0905
c2020917
bf8c007f
d2820003
040c0906
c0860104
bf8c007f
c2000d0d
bf8c007f
100e0600
c2000d0c
bf8c007f
d2820008
041e0200
c2000919
bf8c007f
100e0800
c2000918
bf8c007f
d2820007
041c0102
c200091a
bf8c007f
d2820007
041c0105
c200091b
bf8c007f
d2820007
041c0106
c2000d0e
bf8c007f
d2820009
04220e00
c200091d
bf8c007f
10100800
c200091c
bf8c007f
d2820008
04200102
c200091e
bf8c007f
d2820008
04200105
c200091f
bf8c007f
d2820008
04200106
c2000d0f
bf8c007f
d2820009
04261000
c2000d09
bf8c007f
10140600
c2000d08
bf8c007f
d282000a
042a0200
c2000d0a
bf8c007f
d282000a
042a0e00
c2000d0b
bf8c007f
d282000a
042a1000
c2000d05
bf8c007f
10160600
c2000d04
bf8c007f
d282000b
042e0200
c2000d06
bf8c007f
d282000b
042e0e00
c2000d07
bf8c007f
d282000b
042e1000
c2000d01
bf8c007f
10180600
c2000d00
bf8c007f
d282000c
04320200
c2000d02
bf8c007f
d282000c
04320e00
c2000d03
bf8c007f
d282000c
04321000
f80000ef
090a0b0c
c2000d1d
bf8c000f
10120600
c2000d1c
bf8c007f
d2820009
04260200
c2000d1e
bf8c007f
d2820009
04260e00
c2000d1f
bf8c007f
d2820009
04261000
c2000d19
bf8c007f
10140600
c2000d18
bf8c007f
d282000a
042a0200
c2000d1a
bf8c007f
d282000a
042a0e00
c2000d1b
bf8c007f
d282000a
042a1000
c2000d15
bf8c007f
10160600
c2000d14
bf8c007f
d282000b
042e0200
c2000d16
bf8c007f
d282000b
042e0e00
c2000d17
bf8c007f
d282000b
042e1000
c2000d11
bf8c007f
10180600
c2000d10
bf8c007f
d282000c
04320200
c2000d12
bf8c007f
d282000c
04320e00
c2000d13
bf8c007f
d282000c
04321000
f80000ff
090a0b0c
c0860704
bf8c000f
e00c2000
80030900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c2000931
bf8c000f
10120800
c2000930
bf8c007f
d2820009
04240102
c2000932
bf8c007f
d2820009
04240105
c2000933
bf8c007f
d2820009
04240106
c200094d
bf8c007f
10140800
c200094c
bf8c007f
d282000a
04280102
c200094e
bf8c007f
d282000a
04280105
c200094f
bf8c007f
d282000a
04280106
c2000949
bf8c007f
10160800
c2000948
bf8c007f
d282000b
042c0102
c200094a
bf8c007f
d282000b
042c0105
c200094b
bf8c007f
d282000b
042c0106
c2000945
bf8c007f
10080800
c2000944
bf8c007f
d2820002
04100102
c2000946
bf8c007f
d2820002
04080105
c2000947
bf8c007f
d2820002
04080106
f800022f
090a0b02
c0820708
bf8c000f
e00c2000
80010900
bf8c0770
10001203
10041402
10081202
f800023f
00000204
c2000950
bf8c000f
d2820000
04061000
c2000902
bf8c007f
10020e00
08021101
c2000951
bf8c007f
10041000
08040702
f80008cf
08010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE, CENTROID
DCL IN[3], GENERIC[21], PERSPECTIVE, CENTROID
DCL IN[4], GENERIC[22], PERSPECTIVE, CENTROID
DCL IN[5], GENERIC[23], PERSPECTIVE, CENTROID
DCL IN[6], GENERIC[24], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..3]
DCL TEMP[0..4], LOCAL
DCL TEMP[5], ARRAY(1), LOCAL
IMM[0] FLT32 {    0.2000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[2].xyyy
  1: TEX TEMP[0].w, TEMP[0], SAMP[0], 2D
  2: MOV TEMP[1].xy, IN[4].xyyy
  3: TEX TEMP[1].w, TEMP[1], SAMP[0], 2D
  4: MOV TEMP[2].xy, IN[5].xyyy
  5: TEX TEMP[2].w, TEMP[2], SAMP[0], 2D
  6: MOV TEMP[3].xy, IN[6].xyyy
  7: TEX TEMP[3].w, TEMP[3], SAMP[0], 2D
  8: MOV TEMP[4].xy, IN[3].xyyy
  9: TEX TEMP[4].w, TEMP[4], SAMP[0], 2D
 10: ADD TEMP[4].x, TEMP[0].wwww, TEMP[4].wwww
 11: ADD TEMP[1].x, TEMP[1].wwww, TEMP[4].xxxx
 12: ADD TEMP[1].x, TEMP[2].wwww, TEMP[1].xxxx
 13: ADD TEMP[1].x, TEMP[3].wwww, TEMP[1].xxxx
 14: MAD TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx, -IN[0].wwww
 15: MOV_SAT TEMP[1].x, TEMP[1].xxxx
 16: MAD TEMP[2].x, IN[1].wwww, CONST[3].wwww, -CONST[3].xxxx
 17: MIN TEMP[2].x, TEMP[2].xxxx, CONST[3].zzzz
 18: MOV_SAT TEMP[2].x, TEMP[2].xxxx
 19: MAD TEMP[0].xyz, TEMP[1].xxxx, CONST[1].xyzz, -TEMP[1].xxxx
 20: ADD TEMP[1].x, -TEMP[2].xxxx, IMM[0].yyyy
 21: ADD TEMP[0].xyz, TEMP[0].xyzz, IMM[0].yyyy
 22: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 23: ADD TEMP[0].xyz, -TEMP[0].xyzz, IMM[0].yyyy
 24: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 25: MAD TEMP[0].xyz, TEMP[0].xyzz, -TEMP[1].xxxx, IMM[0].yyyy
 26: MOV TEMP[0].w, IMM[0].yyyy
 27: MOV TEMP[5], TEMP[0]
 28: MOV OUT[0], TEMP[5]
 29: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
  %28 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %29 = load <32 x i8> addrspace(2)* %28, !tbaa !0
  %30 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
  %32 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %33 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %34 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %6)
  %35 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %6)
  %36 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %6)
  %37 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %6)
  %38 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %6)
  %39 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %6)
  %40 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %6)
  %41 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %6)
  %42 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %6)
  %43 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %6)
  %44 = bitcast float %34 to i32
  %45 = bitcast float %35 to i32
  %46 = insertelement <2 x i32> undef, i32 %44, i32 0
  %47 = insertelement <2 x i32> %46, i32 %45, i32 1
  %48 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %47, <32 x i8> %29, <16 x i8> %31, i32 2)
  %49 = extractelement <4 x float> %48, i32 3
  %50 = bitcast float %38 to i32
  %51 = bitcast float %39 to i32
  %52 = insertelement <2 x i32> undef, i32 %50, i32 0
  %53 = insertelement <2 x i32> %52, i32 %51, i32 1
  %54 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %53, <32 x i8> %29, <16 x i8> %31, i32 2)
  %55 = extractelement <4 x float> %54, i32 3
  %56 = bitcast float %40 to i32
  %57 = bitcast float %41 to i32
  %58 = insertelement <2 x i32> undef, i32 %56, i32 0
  %59 = insertelement <2 x i32> %58, i32 %57, i32 1
  %60 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %59, <32 x i8> %29, <16 x i8> %31, i32 2)
  %61 = extractelement <4 x float> %60, i32 3
  %62 = bitcast float %42 to i32
  %63 = bitcast float %43 to i32
  %64 = insertelement <2 x i32> undef, i32 %62, i32 0
  %65 = insertelement <2 x i32> %64, i32 %63, i32 1
  %66 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %65, <32 x i8> %29, <16 x i8> %31, i32 2)
  %67 = extractelement <4 x float> %66, i32 3
  %68 = bitcast float %36 to i32
  %69 = bitcast float %37 to i32
  %70 = insertelement <2 x i32> undef, i32 %68, i32 0
  %71 = insertelement <2 x i32> %70, i32 %69, i32 1
  %72 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %71, <32 x i8> %29, <16 x i8> %31, i32 2)
  %73 = extractelement <4 x float> %72, i32 3
  %74 = fadd float %49, %73
  %75 = fadd float %55, %74
  %76 = fadd float %61, %75
  %77 = fadd float %67, %76
  %78 = fsub float -0.000000e+00, %32
  %79 = fmul float %77, 0x3FC99999A0000000
  %80 = fadd float %79, %78
  %81 = call float @llvm.AMDIL.clamp.(float %80, float 0.000000e+00, float 1.000000e+00)
  %82 = fsub float -0.000000e+00, %25
  %83 = fmul float %33, %27
  %84 = fadd float %83, %82
  %85 = fcmp uge float %84, %26
  %86 = select i1 %85, float %26, float %84
  %87 = call float @llvm.AMDIL.clamp.(float %86, float 0.000000e+00, float 1.000000e+00)
  %88 = fsub float -0.000000e+00, %81
  %89 = fmul float %81, %22
  %90 = fadd float %89, %88
  %91 = fsub float -0.000000e+00, %81
  %92 = fmul float %81, %23
  %93 = fadd float %92, %91
  %94 = fsub float -0.000000e+00, %81
  %95 = fmul float %81, %24
  %96 = fadd float %95, %94
  %97 = fsub float -0.000000e+00, %87
  %98 = fadd float %97, 1.000000e+00
  %99 = fadd float %90, 1.000000e+00
  %100 = fadd float %93, 1.000000e+00
  %101 = fadd float %96, 1.000000e+00
  %102 = fmul float %98, %98
  %103 = fsub float -0.000000e+00, %99
  %104 = fadd float %103, 1.000000e+00
  %105 = fsub float -0.000000e+00, %100
  %106 = fadd float %105, 1.000000e+00
  %107 = fsub float -0.000000e+00, %101
  %108 = fadd float %107, 1.000000e+00
  %109 = fmul float %102, %102
  %110 = fsub float -0.000000e+00, %109
  %111 = fmul float %104, %110
  %112 = fadd float %111, 1.000000e+00
  %113 = fsub float -0.000000e+00, %109
  %114 = fmul float %106, %113
  %115 = fadd float %114, 1.000000e+00
  %116 = fsub float -0.000000e+00, %109
  %117 = fmul float %108, %116
  %118 = fadd float %117, 1.000000e+00
  %119 = call i32 @llvm.SI.packf16(float %112, float %115)
  %120 = bitcast i32 %119 to float
  %121 = call i32 @llvm.SI.packf16(float %118, float 1.000000e+00)
  %122 = bitcast i32 %121 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %120, float %122, float %120, float %122)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR2, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR3, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR2, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR3, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%30](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%28](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR2, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR3, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR2, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR3, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_ADD_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR2, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR3, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR2, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR3, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_ADD_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR2, 1, 5, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR3, 1, 5, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR2, 0, 5, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR3, 0, 5, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_ADD_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR2, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR3, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR2, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR3, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR2<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_ADD_F32_e32 %VGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 2.000000e-01, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12
	S_WAITCNT 127
	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14
	S_WAITCNT 127
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR0, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_SUB_F32_e32 1.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 1.000000e+00, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 6
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e32 1.000000e+00, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 1.000000e+00, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_SUB_F32_e32 1.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 %VGPR0<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140d02
c8150d03
c8100c02
c8110c03
c0840300
c0c60500
bf8c007f
f0800800
00430404
c8180902
c8190903
c8140802
c8150803
f0800800
00430505
bf8c0770
06080905
c8181102
c8191103
c8141002
c8151003
f0800800
00430505
bf8c0770
06080905
c8181502
c8191503
c8141402
c8151403
f0800800
00430505
bf8c0770
06080905
c8181902
c8191903
c8141802
c8151803
f0800800
00430205
bf8c0770
06040902
100404ff
3e4ccccd
c80c0300
c80d0301
08040702
d2060802
02010102
c0800100
bf8c007f
c2020105
bf8c007f
10060404
08060503
060606f2
080606f2
c8100700
c8110701
c202010f
bf8c007f
10000804
c202010c
bf8c007f
0a000004
c202010e
bf8c007f
d00c0006
02000900
7e020204
d2000000
001a0300
d2060800
02010100
080000f2
10000100
10000100
10020103
080202f2
c2020104
bf8c007f
10060404
08060503
060606f2
080606f2
10060103
080606f2
5e020303
c2000106
bf8c007f
10060400
08040503
060404f2
080404f2
10000102
080000f2
d25e0000
0201e500
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL OUT[7], GENERIC[23]
DCL OUT[8], GENERIC[24]
DCL CONST[0..55]
DCL TEMP[0..10], LOCAL
  0: MOV TEMP[0].w, CONST[0].yyyy
  1: DP4 TEMP[0].x, IN[0], CONST[52]
  2: DP4 TEMP[1].x, IN[0], CONST[53]
  3: MOV TEMP[0].y, TEMP[1].xxxx
  4: DP4 TEMP[1].x, IN[0], CONST[54]
  5: MOV TEMP[0].z, TEMP[1].xxxx
  6: DP4 TEMP[1].x, TEMP[0], CONST[8]
  7: DP4 TEMP[2].x, TEMP[0], CONST[9]
  8: MOV TEMP[1].y, TEMP[2].xxxx
  9: DP4 TEMP[3].x, TEMP[0], CONST[10]
 10: MOV TEMP[1].z, TEMP[3].xxxx
 11: DP4 TEMP[4].x, TEMP[0], CONST[11]
 12: MOV TEMP[1].w, TEMP[4].xxxx
 13: DP4 TEMP[5].x, TEMP[0], CONST[13]
 14: DP4 TEMP[6].x, IN[2], CONST[48]
 15: DP4 TEMP[7].x, IN[2], CONST[49]
 16: MOV TEMP[6].y, TEMP[7].xxxx
 17: MOV TEMP[0].xyz, TEMP[0].xyzx
 18: ADD TEMP[7].xy, TEMP[6].xyyy, CONST[50].xyyy
 19: ADD TEMP[8].xy, TEMP[6].xyyy, -CONST[50].xyyy
 20: ADD TEMP[9].xy, TEMP[6].xyyy, CONST[51].xyyy
 21: ADD TEMP[10].xy, TEMP[6].xyyy, -CONST[51].xyyy
 22: MOV TEMP[6].xy, TEMP[6].xyxx
 23: MOV TEMP[0].w, TEMP[5].xxxx
 24: MOV TEMP[5], TEMP[1]
 25: MAD TEMP[3].x, TEMP[3].xxxx, CONST[0].zzzz, -TEMP[4].xxxx
 26: MOV TEMP[1].z, TEMP[3].xxxx
 27: MOV TEMP[1].y, -TEMP[2].xxxx
 28: MAD TEMP[1].xy, CONST[55].xyyy, TEMP[4].xxxx, TEMP[1].xyyy
 29: MOV OUT[4], TEMP[6]
 30: MOV OUT[5], TEMP[7]
 31: MOV OUT[6], TEMP[8]
 32: MOV OUT[7], TEMP[9]
 33: MOV OUT[0], TEMP[1]
 34: MOV OUT[8], TEMP[10]
 35: MOV OUT[2], TEMP[5]
 36: MOV OUT[3], TEMP[0]
 37: MOV_SAT OUT[1], IN[1]
 38: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 776)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 792)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 800)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 804)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 816)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 820)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 832)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 836)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 840)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 844)
  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 848)
  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 852)
  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 856)
  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 860)
  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 864)
  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 868)
  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 872)
  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 876)
  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 880)
  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 884)
  %59 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
  %61 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %60, i32 0, i32 %5)
  %62 = extractelement <4 x float> %61, i32 0
  %63 = extractelement <4 x float> %61, i32 1
  %64 = extractelement <4 x float> %61, i32 2
  %65 = extractelement <4 x float> %61, i32 3
  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
  %69 = extractelement <4 x float> %68, i32 0
  %70 = extractelement <4 x float> %68, i32 1
  %71 = extractelement <4 x float> %68, i32 2
  %72 = extractelement <4 x float> %68, i32 3
  %73 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %74 = load <16 x i8> addrspace(2)* %73, !tbaa !0
  %75 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %74, i32 0, i32 %5)
  %76 = extractelement <4 x float> %75, i32 0
  %77 = extractelement <4 x float> %75, i32 1
  %78 = extractelement <4 x float> %75, i32 2
  %79 = extractelement <4 x float> %75, i32 3
  %80 = fmul float %62, %45
  %81 = fmul float %63, %46
  %82 = fadd float %80, %81
  %83 = fmul float %64, %47
  %84 = fadd float %82, %83
  %85 = fmul float %65, %48
  %86 = fadd float %84, %85
  %87 = fmul float %62, %49
  %88 = fmul float %63, %50
  %89 = fadd float %87, %88
  %90 = fmul float %64, %51
  %91 = fadd float %89, %90
  %92 = fmul float %65, %52
  %93 = fadd float %91, %92
  %94 = fmul float %62, %53
  %95 = fmul float %63, %54
  %96 = fadd float %94, %95
  %97 = fmul float %64, %55
  %98 = fadd float %96, %97
  %99 = fmul float %65, %56
  %100 = fadd float %98, %99
  %101 = fmul float %86, %13
  %102 = fmul float %93, %14
  %103 = fadd float %101, %102
  %104 = fmul float %100, %15
  %105 = fadd float %103, %104
  %106 = fmul float %11, %16
  %107 = fadd float %105, %106
  %108 = fmul float %86, %17
  %109 = fmul float %93, %18
  %110 = fadd float %108, %109
  %111 = fmul float %100, %19
  %112 = fadd float %110, %111
  %113 = fmul float %11, %20
  %114 = fadd float %112, %113
  %115 = fmul float %86, %21
  %116 = fmul float %93, %22
  %117 = fadd float %115, %116
  %118 = fmul float %100, %23
  %119 = fadd float %117, %118
  %120 = fmul float %11, %24
  %121 = fadd float %119, %120
  %122 = fmul float %86, %25
  %123 = fmul float %93, %26
  %124 = fadd float %122, %123
  %125 = fmul float %100, %27
  %126 = fadd float %124, %125
  %127 = fmul float %11, %28
  %128 = fadd float %126, %127
  %129 = fmul float %86, %29
  %130 = fmul float %93, %30
  %131 = fadd float %129, %130
  %132 = fmul float %100, %31
  %133 = fadd float %131, %132
  %134 = fmul float %11, %32
  %135 = fadd float %133, %134
  %136 = fmul float %76, %33
  %137 = fmul float %77, %34
  %138 = fadd float %136, %137
  %139 = fmul float %78, %35
  %140 = fadd float %138, %139
  %141 = fmul float %79, %36
  %142 = fadd float %140, %141
  %143 = fmul float %76, %37
  %144 = fmul float %77, %38
  %145 = fadd float %143, %144
  %146 = fmul float %78, %39
  %147 = fadd float %145, %146
  %148 = fmul float %79, %40
  %149 = fadd float %147, %148
  %150 = fadd float %142, %41
  %151 = fadd float %149, %42
  %152 = fsub float -0.000000e+00, %41
  %153 = fadd float %142, %152
  %154 = fsub float -0.000000e+00, %42
  %155 = fadd float %149, %154
  %156 = fadd float %142, %43
  %157 = fadd float %149, %44
  %158 = fsub float -0.000000e+00, %43
  %159 = fadd float %142, %158
  %160 = fsub float -0.000000e+00, %44
  %161 = fadd float %149, %160
  %162 = fsub float -0.000000e+00, %128
  %163 = fmul float %121, %12
  %164 = fadd float %163, %162
  %165 = fsub float -0.000000e+00, %114
  %166 = fmul float %57, %128
  %167 = fadd float %166, %107
  %168 = fmul float %58, %128
  %169 = fadd float %168, %165
  %170 = call float @llvm.AMDIL.clamp.(float %69, float 0.000000e+00, float 1.000000e+00)
  %171 = call float @llvm.AMDIL.clamp.(float %70, float 0.000000e+00, float 1.000000e+00)
  %172 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00)
  %173 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %170, float %171, float %172, float %173)
  %174 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %175 = load <16 x i8> addrspace(2)* %174, !tbaa !0
  %176 = call float @llvm.SI.load.const(<16 x i8> %175, i32 0)
  %177 = fmul float %176, %107
  %178 = call float @llvm.SI.load.const(<16 x i8> %175, i32 4)
  %179 = fmul float %178, %114
  %180 = fadd float %177, %179
  %181 = call float @llvm.SI.load.const(<16 x i8> %175, i32 8)
  %182 = fmul float %181, %121
  %183 = fadd float %180, %182
  %184 = call float @llvm.SI.load.const(<16 x i8> %175, i32 12)
  %185 = fmul float %184, %128
  %186 = fadd float %183, %185
  %187 = call float @llvm.SI.load.const(<16 x i8> %175, i32 16)
  %188 = fmul float %187, %107
  %189 = call float @llvm.SI.load.const(<16 x i8> %175, i32 20)
  %190 = fmul float %189, %114
  %191 = fadd float %188, %190
  %192 = call float @llvm.SI.load.const(<16 x i8> %175, i32 24)
  %193 = fmul float %192, %121
  %194 = fadd float %191, %193
  %195 = call float @llvm.SI.load.const(<16 x i8> %175, i32 28)
  %196 = fmul float %195, %128
  %197 = fadd float %194, %196
  %198 = call float @llvm.SI.load.const(<16 x i8> %175, i32 32)
  %199 = fmul float %198, %107
  %200 = call float @llvm.SI.load.const(<16 x i8> %175, i32 36)
  %201 = fmul float %200, %114
  %202 = fadd float %199, %201
  %203 = call float @llvm.SI.load.const(<16 x i8> %175, i32 40)
  %204 = fmul float %203, %121
  %205 = fadd float %202, %204
  %206 = call float @llvm.SI.load.const(<16 x i8> %175, i32 44)
  %207 = fmul float %206, %128
  %208 = fadd float %205, %207
  %209 = call float @llvm.SI.load.const(<16 x i8> %175, i32 48)
  %210 = fmul float %209, %107
  %211 = call float @llvm.SI.load.const(<16 x i8> %175, i32 52)
  %212 = fmul float %211, %114
  %213 = fadd float %210, %212
  %214 = call float @llvm.SI.load.const(<16 x i8> %175, i32 56)
  %215 = fmul float %214, %121
  %216 = fadd float %213, %215
  %217 = call float @llvm.SI.load.const(<16 x i8> %175, i32 60)
  %218 = fmul float %217, %128
  %219 = fadd float %216, %218
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %186, float %197, float %208, float %219)
  %220 = call float @llvm.SI.load.const(<16 x i8> %175, i32 64)
  %221 = fmul float %220, %107
  %222 = call float @llvm.SI.load.const(<16 x i8> %175, i32 68)
  %223 = fmul float %222, %114
  %224 = fadd float %221, %223
  %225 = call float @llvm.SI.load.const(<16 x i8> %175, i32 72)
  %226 = fmul float %225, %121
  %227 = fadd float %224, %226
  %228 = call float @llvm.SI.load.const(<16 x i8> %175, i32 76)
  %229 = fmul float %228, %128
  %230 = fadd float %227, %229
  %231 = call float @llvm.SI.load.const(<16 x i8> %175, i32 80)
  %232 = fmul float %231, %107
  %233 = call float @llvm.SI.load.const(<16 x i8> %175, i32 84)
  %234 = fmul float %233, %114
  %235 = fadd float %232, %234
  %236 = call float @llvm.SI.load.const(<16 x i8> %175, i32 88)
  %237 = fmul float %236, %121
  %238 = fadd float %235, %237
  %239 = call float @llvm.SI.load.const(<16 x i8> %175, i32 92)
  %240 = fmul float %239, %128
  %241 = fadd float %238, %240
  %242 = call float @llvm.SI.load.const(<16 x i8> %175, i32 96)
  %243 = fmul float %242, %107
  %244 = call float @llvm.SI.load.const(<16 x i8> %175, i32 100)
  %245 = fmul float %244, %114
  %246 = fadd float %243, %245
  %247 = call float @llvm.SI.load.const(<16 x i8> %175, i32 104)
  %248 = fmul float %247, %121
  %249 = fadd float %246, %248
  %250 = call float @llvm.SI.load.const(<16 x i8> %175, i32 108)
  %251 = fmul float %250, %128
  %252 = fadd float %249, %251
  %253 = call float @llvm.SI.load.const(<16 x i8> %175, i32 112)
  %254 = fmul float %253, %107
  %255 = call float @llvm.SI.load.const(<16 x i8> %175, i32 116)
  %256 = fmul float %255, %114
  %257 = fadd float %254, %256
  %258 = call float @llvm.SI.load.const(<16 x i8> %175, i32 120)
  %259 = fmul float %258, %121
  %260 = fadd float %257, %259
  %261 = call float @llvm.SI.load.const(<16 x i8> %175, i32 124)
  %262 = fmul float %261, %128
  %263 = fadd float %260, %262
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %230, float %241, float %252, float %263)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %86, float %93, float %100, float %135)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %142, float %149, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %150, float %151, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %153, float %155, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %156, float %157, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %159, float %161, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %167, float %169, float %164, float %128)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%66](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_ADD_F32_e64 %VGPR4, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 %VGPR3, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR2, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 %VGPR1, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%59](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 209
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 208
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 210
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 211
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR9, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 213
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 212
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 214
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 215
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR9, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 217
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 216
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 218
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 219
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR9, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR7, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 35
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %SGPR2, %VGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 37
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 36
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR3, %SGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 38
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 39
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR2, %VGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%174](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 41
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 40
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 42
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 43
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR2, %VGPR8<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 45
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR2, %VGPR9<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 9
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 11
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 29
	S_WAITCNT 15
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 28
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 30
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 31
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 25
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 24
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 26
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 27
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 21
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 20
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 22
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 23
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 17
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 16
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 18
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 19
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 53
	S_WAITCNT 15
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 52
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 54
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 55
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %SGPR2<kill>, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR3<kill>, %VGPR5<kill>, %VGPR7<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 8; mem:LD16[%73](tbaa=!"const")
	S_WAITCNT 15
	%VGPR7_VGPR8_VGPR9_VGPR10<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 112
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 198
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR9, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 199
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 194
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR9, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 195
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8_VGPR9_VGPR10<imp-use,kill>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR3, %VGPR0, %VGPR5, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 201
	S_WAITCNT 15
	%VGPR7<def> = V_ADD_F32_e32 %SGPR0, %VGPR0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 200
	S_WAITCNT 127
	%VGPR8<def> = V_ADD_F32_e32 %SGPR1, %VGPR3, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR8<kill>, %VGPR7<kill>, %VGPR5, %VGPR5, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR7<def> = V_SUBREV_F32_e32 %SGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR8<def> = V_SUBREV_F32_e32 %SGPR1<kill>, %VGPR3, %EXEC<imp-use>
	EXP 15, 36, 0, 0, 0, %VGPR8<kill>, %VGPR7<kill>, %VGPR5, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 205
	S_WAITCNT 15
	%VGPR7<def> = V_ADD_F32_e32 %SGPR0, %VGPR0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 204
	S_WAITCNT 127
	%VGPR8<def> = V_ADD_F32_e32 %SGPR1, %VGPR3, %EXEC<imp-use>
	EXP 15, 37, 0, 0, 0, %VGPR8<kill>, %VGPR7<kill>, %VGPR5, %VGPR5, %EXEC<imp-use>
	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 38, 0, 0, 0, %VGPR3<kill>, %VGPR0<kill>, %VGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 220
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 221
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR6<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0840700
bf8c000f
e00c2000
80020600
c0840100
bf8c0070
c20109d1
bf8c007f
10020e02
c20109d0
bf8c007f
d2820001
04040506
c20109d2
bf8c007f
d2820001
04040508
c20109d3
bf8c007f
d2820003
04040509
c20109d5
bf8c007f
10020e02
c20109d4
bf8c007f
d2820001
04040506
c20109d6
bf8c007f
d2820001
04040508
c20109d7
bf8c007f
d2820005
04040509
c2010921
bf8c007f
10020a02
c2010920
bf8c007f
d2820001
04040503
c20109d9
bf8c007f
10040e02
c20109d8
bf8c007f
d2820002
04080506
c20109da
bf8c007f
d2820002
04080508
c20109db
bf8c007f
d2820007
04080509
c2010922
bf8c007f
d2820001
04040507
c2010901
c2018923
bf8c007f
7e040203
d2820001
04060402
c2018925
bf8c007f
10040a03
c2018924
bf8c007f
d2820002
04080703
c2018926
bf8c007f
d2820002
04080707
c2018927
bf8c007f
7e080203
d2820002
040a0802
c0860104
bf8c007f
c2000d0d
bf8c007f
10080400
c2000d0c
bf8c007f
d2820006
04120200
c2000929
bf8c007f
10080a00
c2000928
bf8c007f
d2820004
04100103
c200092a
bf8c007f
d2820004
04100107
c200092b
bf8c007f
7e100200
d2820004
04121002
c2000d0e
bf8c007f
d2820008
041a0800
c200092d
bf8c007f
100c0a00
c200092c
bf8c007f
d2820006
04180103
c200092e
bf8c007f
d2820006
04180107
c200092f
bf8c007f
7e120200
d2820006
041a1202
c2000d0f
bf8c007f
d2820008
04220c00
c2000d09
bf8c007f
10120400
c2000d08
bf8c007f
d2820009
04260200
c2000d0a
bf8c007f
d2820009
04260800
c2000d0b
bf8c007f
d2820009
04260c00
c2000d05
bf8c007f
10140400
c2000d04
bf8c007f
d282000a
042a0200
c2000d06
bf8c007f
d282000a
042a0800
c2000d07
bf8c007f
d282000a
042a0c00
c2000d01
bf8c007f
10160400
c2000d00
bf8c007f
d282000b
042e0200
c2000d02
bf8c007f
d282000b
042e0800
c2000d03
bf8c007f
d282000b
042e0c00
f80000ef
08090a0b
c2000d1d
bf8c000f
10100400
c2000d1c
bf8c007f
d2820008
04220200
c2000d1e
bf8c007f
d2820008
04220800
c2000d1f
bf8c007f
d2820008
04220c00
c2000d19
bf8c007f
10120400
c2000d18
bf8c007f
d2820009
04260200
c2000d1a
bf8c007f
d2820009
04260800
c2000d1b
bf8c007f
d2820009
04260c00
c2000d15
bf8c007f
10140400
c2000d14
bf8c007f
d282000a
042a0200
c2000d16
bf8c007f
d282000a
042a0800
c2000d17
bf8c007f
d282000a
042a0c00
c2000d11
bf8c007f
10160400
c2000d10
bf8c007f
d282000b
042e0200
c2000d12
bf8c007f
d282000b
042e0800
c2000d13
bf8c007f
d282000b
042e0c00
f80000ff
08090a0b
c2000935
bf8c000f
10100a00
c2000934
bf8c007f
d2820008
04200103
c2000936
bf8c007f
d2820008
04200107
c2000937
bf8c007f
7e120200
d2820008
04221202
f800021f
08070503
c0800708
bf8c000f
e00c2000
80000700
c20009c5
bf8c0070
10001000
c20009c4
bf8c007f
d2820000
04000107
c20009c6
bf8c007f
d2820000
04000109
c20009c7
bf8c007f
d2820000
0400010a
c20009c1
bf8c007f
10061000
c20009c0
bf8c007f
d2820003
040c0107
c20009c2
bf8c007f
d2820003
040c0109
c20009c3
bf8c007f
d2820003
040c010a
7e0a0280
f800022f
05050003
c20009c9
bf8c000f
060e0000
c20089c8
bf8c007f
06100601
f800023f
05050708
bf8c070f
0a0e0000
0a100601
f800024f
05050708
c20009cd
bf8c000f
060e0000
c20089cc
bf8c007f
06100601
f800025f
05050708
0a000000
0a060601
f800026f
05050003
c20009dc
bf8c000f
d2820000
04060c00
c2000902
bf8c007f
10020800
08020d01
c20009dd
bf8c007f
10060c00
08040503
f80008cf
06010200
bf810000
FRAG
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL IN[3], GENERIC[22], PERSPECTIVE
DCL IN[4], GENERIC[23], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..30]
DCL TEMP[0..11], LOCAL
DCL TEMP[12], ARRAY(1), LOCAL
IMM[0] FLT32 {    2.0000,    -1.0000,     0.0000,     1.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[1], 2D
  2: MOV TEMP[1].xy, IN[0].xyyy
  3: TEX TEMP[1], TEMP[1], SAMP[0], 2D
  4: MOV TEMP[2].xy, IN[0].xyyy
  5: TEX TEMP[3].xyz, TEMP[2], SAMP[2], 2D
  6: MAD TEMP[4].xyz, IMM[0].xxxx, TEMP[0].xyzz, IMM[0].yyyy
  7: ADD TEMP[0].xyz, -TEMP[4].xyzz, IMM[0].zzww
  8: MAD TEMP[0].xyz, CONST[27].xxxx, TEMP[0].xyzz, TEMP[4].xyzz
  9: MUL TEMP[4].xyz, TEMP[0].yyyy, IN[2].xyzz
 10: MAD TEMP[4].xyz, IN[1].xyzz, TEMP[0].xxxx, TEMP[4].xyzz
 11: MAD TEMP[0].xyz, IN[3].xyzz, TEMP[0].zzzz, TEMP[4].xyzz
 12: DP3 TEMP[5].x, TEMP[0].xyzz, TEMP[0].xyzz
 13: RSQ TEMP[5].x, TEMP[5].xxxx
 14: MUL TEMP[5].xyz, TEMP[0].xyzz, TEMP[5].xxxx
 15: MUL TEMP[6].xyz, TEMP[5].xyzz, TEMP[5].xyzz
 16: SGE TEMP[7].x, TEMP[5].xxxx, IMM[0].zzzz
 17: F2I TEMP[7].x, -TEMP[7]
 18: UIF TEMP[7].xxxx :0
 19:   MOV TEMP[7].x, IMM[0].zzzz
 20: ELSE :0
 21:   MOV TEMP[7].x, TEMP[6].xxxx
 22: ENDIF
 23: SGE TEMP[8].x, TEMP[5].yyyy, IMM[0].zzzz
 24: F2I TEMP[8].x, -TEMP[8]
 25: UIF TEMP[8].xxxx :0
 26:   MOV TEMP[8].x, IMM[0].zzzz
 27: ELSE :0
 28:   MOV TEMP[8].x, TEMP[6].yyyy
 29: ENDIF
 30: SGE TEMP[9].x, TEMP[5].zzzz, IMM[0].zzzz
 31: F2I TEMP[9].x, -TEMP[9]
 32: UIF TEMP[9].xxxx :0
 33:   MOV TEMP[9].x, IMM[0].zzzz
 34: ELSE :0
 35:   MOV TEMP[9].x, TEMP[6].zzzz
 36: ENDIF
 37: SGE TEMP[10].x, TEMP[5].xxxx, IMM[0].zzzz
 38: F2I TEMP[10].x, -TEMP[10]
 39: UIF TEMP[10].xxxx :0
 40:   MOV TEMP[10].x, TEMP[6].xxxx
 41: ELSE :0
 42:   MOV TEMP[10].x, IMM[0].zzzz
 43: ENDIF
 44: SGE TEMP[11].x, TEMP[5].yyyy, IMM[0].zzzz
 45: F2I TEMP[11].x, -TEMP[11]
 46: UIF TEMP[11].xxxx :0
 47:   MOV TEMP[11].x, TEMP[6].yyyy
 48: ELSE :0
 49:   MOV TEMP[11].x, IMM[0].zzzz
 50: ENDIF
 51: SGE TEMP[5].x, TEMP[5].zzzz, IMM[0].zzzz
 52: F2I TEMP[5].x, -TEMP[5]
 53: UIF TEMP[5].xxxx :0
 54:   MOV TEMP[5].x, TEMP[6].zzzz
 55: ELSE :0
 56:   MOV TEMP[5].x, IMM[0].zzzz
 57: ENDIF
 58: MUL TEMP[6].xyz, TEMP[7].xxxx, CONST[5].xyzz
 59: MAD TEMP[6].xyz, TEMP[10].xxxx, CONST[4].xyzz, TEMP[6].xyzz
 60: MAD TEMP[6].xyz, TEMP[11].xxxx, CONST[6].xyzz, TEMP[6].xyzz
 61: MAD TEMP[6].xyz, TEMP[8].xxxx, CONST[7].xyzz, TEMP[6].xyzz
 62: MAD TEMP[4].xyz, TEMP[5].xxxx, CONST[8].xyzz, TEMP[6].xyzz
 63: MAD TEMP[0].xyz, TEMP[9].xxxx, CONST[9].xyzz, TEMP[4].xyzz
 64: MUL TEMP[2].xyz, TEMP[1].xyzz, CONST[1].xyzz
 65: MUL TEMP[4].xyz, TEMP[0].xyzz, TEMP[2].xyzz
 66: MAD TEMP[2].xyz, CONST[0].xyzz, TEMP[2].xyzz, -TEMP[4].xyzz
 67: ADD TEMP[3].xyz, TEMP[3].xyzz, -TEMP[1].wwww
 68: MAD TEMP[0].xyz, CONST[10].wwww, TEMP[3].xyzz, TEMP[1].wwww
 69: MAD TEMP[2].xyz, TEMP[0].xyzz, TEMP[2].xyzz, TEMP[4].xyzz
 70: MAD TEMP[1].x, IN[4].zzzz, CONST[12].wwww, -CONST[12].xxxx
 71: MAX TEMP[3].xyz, TEMP[2].xyzz, IMM[0].zzzz
 72: MIN TEMP[1].x, TEMP[1].xxxx, CONST[12].zzzz
 73: MOV_SAT TEMP[1].x, TEMP[1].xxxx
 74: MAD TEMP[2].xyz, TEMP[3].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 75: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 76: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[1].xxxx
 77: MAD TEMP[0].xyz, TEMP[3].xyzz, CONST[30].xxxx, TEMP[2].xyzz
 78: MUL TEMP[1].x, IN[4].zzzz, CONST[29].wwww
 79: MOV TEMP[0].w, TEMP[1].xxxx
 80: MOV TEMP[12], TEMP[0]
 81: MOV OUT[0], TEMP[12]
 82: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 100)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 104)
  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 112)
  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 116)
  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 120)
  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
  %41 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
  %42 = call float @llvm.SI.load.const(<16 x i8> %21, i32 136)
  %43 = call float @llvm.SI.load.const(<16 x i8> %21, i32 144)
  %44 = call float @llvm.SI.load.const(<16 x i8> %21, i32 148)
  %45 = call float @llvm.SI.load.const(<16 x i8> %21, i32 152)
  %46 = call float @llvm.SI.load.const(<16 x i8> %21, i32 172)
  %47 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %48 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %49 = call float @llvm.SI.load.const(<16 x i8> %21, i32 204)
  %50 = call float @llvm.SI.load.const(<16 x i8> %21, i32 432)
  %51 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %52 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %53 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %54 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %55 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %56 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %57 = load <32 x i8> addrspace(2)* %56, !tbaa !0
  %58 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %59 = load <16 x i8> addrspace(2)* %58, !tbaa !0
  %60 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %61 = load <32 x i8> addrspace(2)* %60, !tbaa !0
  %62 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %63 = load <16 x i8> addrspace(2)* %62, !tbaa !0
  %64 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %65 = load <32 x i8> addrspace(2)* %64, !tbaa !0
  %66 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
  %68 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %69 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %70 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %71 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %72 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %73 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %74 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %75 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %76 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
  %77 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
  %78 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %79 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
  %80 = bitcast float %68 to i32
  %81 = bitcast float %69 to i32
  %82 = insertelement <2 x i32> undef, i32 %80, i32 0
  %83 = insertelement <2 x i32> %82, i32 %81, i32 1
  %84 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %83, <32 x i8> %61, <16 x i8> %63, i32 2)
  %85 = extractelement <4 x float> %84, i32 0
  %86 = extractelement <4 x float> %84, i32 1
  %87 = extractelement <4 x float> %84, i32 2
  %88 = bitcast float %68 to i32
  %89 = bitcast float %69 to i32
  %90 = insertelement <2 x i32> undef, i32 %88, i32 0
  %91 = insertelement <2 x i32> %90, i32 %89, i32 1
  %92 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %91, <32 x i8> %57, <16 x i8> %59, i32 2)
  %93 = extractelement <4 x float> %92, i32 0
  %94 = extractelement <4 x float> %92, i32 1
  %95 = extractelement <4 x float> %92, i32 2
  %96 = extractelement <4 x float> %92, i32 3
  %97 = bitcast float %68 to i32
  %98 = bitcast float %69 to i32
  %99 = insertelement <2 x i32> undef, i32 %97, i32 0
  %100 = insertelement <2 x i32> %99, i32 %98, i32 1
  %101 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %100, <32 x i8> %65, <16 x i8> %67, i32 2)
  %102 = extractelement <4 x float> %101, i32 0
  %103 = extractelement <4 x float> %101, i32 1
  %104 = extractelement <4 x float> %101, i32 2
  %105 = fmul float 2.000000e+00, %85
  %106 = fadd float %105, -1.000000e+00
  %107 = fmul float 2.000000e+00, %86
  %108 = fadd float %107, -1.000000e+00
  %109 = fmul float 2.000000e+00, %87
  %110 = fadd float %109, -1.000000e+00
  %111 = fsub float -0.000000e+00, %106
  %112 = fadd float %111, 0.000000e+00
  %113 = fsub float -0.000000e+00, %108
  %114 = fadd float %113, 0.000000e+00
  %115 = fsub float -0.000000e+00, %110
  %116 = fadd float %115, 1.000000e+00
  %117 = fmul float %50, %112
  %118 = fadd float %117, %106
  %119 = fmul float %50, %114
  %120 = fadd float %119, %108
  %121 = fmul float %50, %116
  %122 = fadd float %121, %110
  %123 = fmul float %120, %73
  %124 = fmul float %120, %74
  %125 = fmul float %120, %75
  %126 = fmul float %70, %118
  %127 = fadd float %126, %123
  %128 = fmul float %71, %118
  %129 = fadd float %128, %124
  %130 = fmul float %72, %118
  %131 = fadd float %130, %125
  %132 = fmul float %76, %122
  %133 = fadd float %132, %127
  %134 = fmul float %77, %122
  %135 = fadd float %134, %129
  %136 = fmul float %78, %122
  %137 = fadd float %136, %131
  %138 = fmul float %133, %133
  %139 = fmul float %135, %135
  %140 = fadd float %139, %138
  %141 = fmul float %137, %137
  %142 = fadd float %140, %141
  %143 = call float @fabs(float %142)
  %144 = call float @llvm.AMDGPU.rsq(float %143)
  %145 = fmul float %133, %144
  %146 = fmul float %135, %144
  %147 = fmul float %137, %144
  %148 = fmul float %145, %145
  %149 = fmul float %146, %146
  %150 = fmul float %147, %147
  %151 = fcmp uge float %145, 0.000000e+00
  %152 = select i1 %151, float 1.000000e+00, float 0.000000e+00
  %153 = fsub float -0.000000e+00, %152
  %154 = fptosi float %153 to i32
  %155 = bitcast i32 %154 to float
  %156 = bitcast float %155 to i32
  %157 = icmp ne i32 %156, 0
  %. = select i1 %157, float 0.000000e+00, float %148
  %158 = fcmp uge float %146, 0.000000e+00
  %159 = select i1 %158, float 1.000000e+00, float 0.000000e+00
  %160 = fsub float -0.000000e+00, %159
  %161 = fptosi float %160 to i32
  %162 = bitcast i32 %161 to float
  %163 = bitcast float %162 to i32
  %164 = icmp ne i32 %163, 0
  %temp32.0 = select i1 %164, float 0.000000e+00, float %149
  %165 = fcmp uge float %147, 0.000000e+00
  %166 = select i1 %165, float 1.000000e+00, float 0.000000e+00
  %167 = fsub float -0.000000e+00, %166
  %168 = fptosi float %167 to i32
  %169 = bitcast i32 %168 to float
  %170 = bitcast float %169 to i32
  %171 = icmp ne i32 %170, 0
  %.67 = select i1 %171, float 0.000000e+00, float %150
  %172 = fcmp uge float %145, 0.000000e+00
  %173 = select i1 %172, float 1.000000e+00, float 0.000000e+00
  %174 = fsub float -0.000000e+00, %173
  %175 = fptosi float %174 to i32
  %176 = bitcast i32 %175 to float
  %177 = bitcast float %176 to i32
  %178 = icmp ne i32 %177, 0
  %temp40.0 = select i1 %178, float %148, float 0.000000e+00
  %179 = fcmp uge float %146, 0.000000e+00
  %180 = select i1 %179, float 1.000000e+00, float 0.000000e+00
  %181 = fsub float -0.000000e+00, %180
  %182 = fptosi float %181 to i32
  %183 = bitcast i32 %182 to float
  %184 = bitcast float %183 to i32
  %185 = icmp ne i32 %184, 0
  %.68 = select i1 %185, float %149, float 0.000000e+00
  %186 = fcmp uge float %147, 0.000000e+00
  %187 = select i1 %186, float 1.000000e+00, float 0.000000e+00
  %188 = fsub float -0.000000e+00, %187
  %189 = fptosi float %188 to i32
  %190 = bitcast i32 %189 to float
  %191 = bitcast float %190 to i32
  %192 = icmp ne i32 %191, 0
  %temp20.0 = select i1 %192, float %150, float 0.000000e+00
  %193 = fmul float %., %31
  %194 = fmul float %., %32
  %195 = fmul float %., %33
  %196 = fmul float %temp40.0, %28
  %197 = fadd float %196, %193
  %198 = fmul float %temp40.0, %29
  %199 = fadd float %198, %194
  %200 = fmul float %temp40.0, %30
  %201 = fadd float %200, %195
  %202 = fmul float %.68, %34
  %203 = fadd float %202, %197
  %204 = fmul float %.68, %35
  %205 = fadd float %204, %199
  %206 = fmul float %.68, %36
  %207 = fadd float %206, %201
  %208 = fmul float %temp32.0, %37
  %209 = fadd float %208, %203
  %210 = fmul float %temp32.0, %38
  %211 = fadd float %210, %205
  %212 = fmul float %temp32.0, %39
  %213 = fadd float %212, %207
  %214 = fmul float %temp20.0, %40
  %215 = fadd float %214, %209
  %216 = fmul float %temp20.0, %41
  %217 = fadd float %216, %211
  %218 = fmul float %temp20.0, %42
  %219 = fadd float %218, %213
  %220 = fmul float %.67, %43
  %221 = fadd float %220, %215
  %222 = fmul float %.67, %44
  %223 = fadd float %222, %217
  %224 = fmul float %.67, %45
  %225 = fadd float %224, %219
  %226 = fmul float %93, %25
  %227 = fmul float %94, %26
  %228 = fmul float %95, %27
  %229 = fmul float %221, %226
  %230 = fmul float %223, %227
  %231 = fmul float %225, %228
  %232 = fsub float -0.000000e+00, %229
  %233 = fmul float %22, %226
  %234 = fadd float %233, %232
  %235 = fsub float -0.000000e+00, %230
  %236 = fmul float %23, %227
  %237 = fadd float %236, %235
  %238 = fsub float -0.000000e+00, %231
  %239 = fmul float %24, %228
  %240 = fadd float %239, %238
  %241 = fsub float -0.000000e+00, %96
  %242 = fadd float %102, %241
  %243 = fsub float -0.000000e+00, %96
  %244 = fadd float %103, %243
  %245 = fsub float -0.000000e+00, %96
  %246 = fadd float %104, %245
  %247 = fmul float %46, %242
  %248 = fadd float %247, %96
  %249 = fmul float %46, %244
  %250 = fadd float %249, %96
  %251 = fmul float %46, %246
  %252 = fadd float %251, %96
  %253 = fmul float %248, %234
  %254 = fadd float %253, %229
  %255 = fmul float %250, %237
  %256 = fadd float %255, %230
  %257 = fmul float %252, %240
  %258 = fadd float %257, %231
  %259 = fsub float -0.000000e+00, %47
  %260 = fmul float %79, %49
  %261 = fadd float %260, %259
  %262 = fcmp uge float %254, 0.000000e+00
  %263 = select i1 %262, float %254, float 0.000000e+00
  %264 = fcmp uge float %256, 0.000000e+00
  %265 = select i1 %264, float %256, float 0.000000e+00
  %266 = fcmp uge float %258, 0.000000e+00
  %267 = select i1 %266, float %258, float 0.000000e+00
  %268 = fcmp uge float %261, %48
  %269 = select i1 %268, float %48, float %261
  %270 = call float @llvm.AMDIL.clamp.(float %269, float 0.000000e+00, float 1.000000e+00)
  %271 = fsub float -0.000000e+00, %55
  %272 = fmul float %263, %271
  %273 = fadd float %272, %51
  %274 = fsub float -0.000000e+00, %55
  %275 = fmul float %265, %274
  %276 = fadd float %275, %52
  %277 = fsub float -0.000000e+00, %55
  %278 = fmul float %267, %277
  %279 = fadd float %278, %53
  %280 = fmul float %270, %270
  %281 = fmul float %273, %280
  %282 = fmul float %276, %280
  %283 = fmul float %279, %280
  %284 = fmul float %263, %55
  %285 = fadd float %284, %281
  %286 = fmul float %265, %55
  %287 = fadd float %286, %282
  %288 = fmul float %267, %55
  %289 = fadd float %288, %283
  %290 = fmul float %79, %54
  %291 = call i32 @llvm.SI.packf16(float %285, float %287)
  %292 = bitcast i32 %291 to float
  %293 = call i32 @llvm.SI.packf16(float %289, float %290)
  %294 = bitcast i32 %293 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %292, float %294, float %292, float %294)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #3

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%62](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%60](tbaa=!"const")
	S_WAITCNT 127
	%VGPR6_VGPR7_VGPR8<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_ADD_F32_e32 %VGPR6, %VGPR6, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_SUB_F32_e32 0.000000e+00, %VGPR4, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 108
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR0, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_F32_e32 %VGPR7, %VGPR7, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_SUB_F32_e32 0.000000e+00, %VGPR5, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %SGPR0, %VGPR9<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR5, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR10<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 %VGPR8, %VGPR8, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_SUB_F32_e32 1.000000e+00, %VGPR6, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR5, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR9<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR9<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR10, %VGPR10, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR6, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR8<kill>, %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR5<kill>, %VGPR7<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR8, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_RSQ_LEGACY_F32_e32 %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR4, %VGPR4, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR4<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR4<def> = V_CVT_I32_F32_e32 %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_NE_I32_e64 %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR5, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR5<kill>, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR4, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR6, %VGPR6, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR6<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 %VGPR6<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR6<def> = V_CVT_I32_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_NE_I32_e64 %VGPR6<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR10, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR6, %SGPR7<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR10<kill>, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR9, %VGPR9, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR9<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e64 %VGPR9<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR9<def> = V_CVT_I32_F32_e32 %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_NE_I32_e64 %VGPR9<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR8, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR12, %SGPR7<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 37
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR13, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%58](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%56](tbaa=!"const")
	S_WAITCNT 127
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 5
	S_WAITCNT 112
	%VGPR15<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR15, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %VGPR14<kill>, %VGPR17, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 8; mem:LD16[%66](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 16; mem:LD32[%64](tbaa=!"const")
	S_WAITCNT 127
	%VGPR14_VGPR15_VGPR16<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_SUB_F32_e32 %VGPR15, %VGPR11, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 43
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %SGPR1, %VGPR2<kill>, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %VGPR18<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR2, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR2<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 120
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0, %VGPR3, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 117
	S_WAITCNT 127
	%VGPR17<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 51
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR2<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR0, %SGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR3<kill>, %SGPR0, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR4, %SGPR2<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR2<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR2<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR12, %SGPR2<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 36
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR13, %SGPR2<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 4
	S_WAITCNT 127
	%VGPR17<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR17, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR17<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %VGPR17<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %VGPR14, %VGPR11, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %SGPR1, %VGPR18<kill>, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR18<kill>, %VGPR17<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR3, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR3<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %SGPR0, %VGPR3, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 116
	S_WAITCNT 127
	%VGPR17<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %SGPR0, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR4<kill>, %SGPR2<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6<kill>, %SGPR2<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7<kill>, %SGPR2<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR12<kill>, %SGPR2<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 38
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR13<kill>, %SGPR2<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 6
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR10, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_SUB_F32_e32 %VGPR4<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR5<def> = V_SUB_F32_e32 %VGPR16, %VGPR11, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16<imp-use,kill>
	%VGPR5<def> = V_MAD_F32 %SGPR1<kill>, %VGPR5<kill>, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%VGPR3<def> = V_MAD_F32 %VGPR5<kill>, %VGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR3, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR3<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0, %VGPR3, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 118
	S_WAITCNT 127
	%VGPR4<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3<kill>, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 119
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840304
c0c60508
bf8c007f
f0800700
00430602
bf8c0770
06080d06
060808f3
080a0880
c0840100
bf8c007f
c200096c
bf8c007f
d2820004
04120a00
060a0f07
060a0af3
08120a80
d2820005
04161200
c8240900
c8250901
10121305
c8280500
c8290501
d2820009
0426090a
060c1108
060c0cf3
080e0cf2
d2820007
041a0e00
c8180d00
c8190d01
d2820006
04260f06
c8200800
c8210801
10101105
c8240400
c8250401
d2820008
04220909
c8240c00
c8250c01
d282000a
04220f09
1010150a
d2820009
04220d06
c8200a00
c8210a01
100a1105
c8200600
c8210601
d2820004
04160908
c8140e00
c8150e01
d2820008
04120f05
d2820004
04261108
d2060104
02010104
7e125b04
1008130a
100a0904
d00c0000
02010104
d2000004
0001e480
d2060004
22010104
7e081104
d10a0000
02010104
d2000004
00020a80
d2000005
00010105
c2000915
bf8c007f
100e0a00
c2000911
bf8c007f
d2820007
041c0104
100c1306
10140d06
d00c0000
02010106
d2000006
0001e480
d2060006
22010106
7e0c1106
d10a0000
02010106
d2000006
00021480
c2038919
bf8c007f
d282000b
041c0f06
d2000007
0001010a
c200091d
bf8c007f
d282000a
042c0107
10121308
10101309
d00c0000
02010109
d2000009
0001e480
d2060009
22010109
7e121109
d10a0000
02010109
d200000c
00021080
c2038921
bf8c007f
d2820009
04280f0c
d200000d
00010108
c2000925
bf8c007f
d282000e
0424010d
c0860300
c0c80500
bf8c007f
f0800f00
00640802
c2000905
bf8c0070
101e1200
10221f0e
c2000901
bf8c007f
101c1e00
0824230e
c0800308
c0c60510
bf8c007f
f0800700
00030e02
bf8c0770
0804170f
c200892b
bf8c007f
d2820002
042e0401
d2820002
04462502
d00c0002
02010102
d2000003
000a0480
c2000978
bf8c007f
10040600
c2010975
bf8c007f
08220402
c8081200
c8091201
c2010933
bf8c007f
10000402
c2010930
bf8c007f
0a000002
c2010932
bf8c007f
d00c0004
02000500
7e020202
d2000000
00120300
d2060800
02010100
10000100
10020111
d2820001
04040103
c2010914
bf8c007f
10060a02
c2010910
bf8c007f
d2820003
040c0504
c2010918
bf8c007f
d2820003
040c0506
c201091c
bf8c007f
d2820003
040c0507
c2010920
bf8c007f
d2820003
040c050c
c2010924
bf8c007f
d2820003
040c050d
c2010904
bf8c007f
10221002
10062303
c2010900
bf8c007f
10222202
08220711
0824170e
d2820012
042e2401
d2820003
040e2312
d00c0002
02010103
d2000003
000a0680
10220600
c2010974
bf8c007f
08222202
10220111
d2820003
04440103
5e020303
c2010916
bf8c007f
10060a02
c2010912
bf8c007f
d2820003
040c0504
c201091a
bf8c007f
d2820003
040c0506
c201091e
bf8c007f
d2820003
040c0507
c2010922
bf8c007f
d2820003
040c050c
c2010926
bf8c007f
d2820003
040c050d
c2010906
bf8c007f
10081402
10060903
c2010902
bf8c007f
10080802
08080704
080a1710
d2820005
042e0a01
d2820003
040e0905
d00c0002
02010103
d2000003
000a0680
10080600
c2008976
bf8c007f
08080801
10000104
d2820000
04000103
c2000977
bf8c007f
10040400
5e000500
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL OUT[5], GENERIC[22]
DCL OUT[6], GENERIC[23]
DCL CONST[0..61]
DCL TEMP[0..10], LOCAL
IMM[0] FLT32 { -128.0000,     1.0000,   -64.0000,    -0.0159}
IMM[1] FLT32 {    0.0159,     0.0001,     0.0000,     0.0000}
  0: ADD TEMP[0], IN[1], IMM[0].xxxx
  1: SLT TEMP[1], TEMP[0], CONST[0].xxxx
  2: F2I TEMP[1], -TEMP[1]
  3: AND TEMP[1], TEMP[1], IMM[0].yyyy
  4: ABS TEMP[0], TEMP[0]
  5: ADD TEMP[0], TEMP[0], -TEMP[1]
  6: ADD TEMP[0], TEMP[0], IMM[0].zzzz
  7: SLT TEMP[2], TEMP[0], CONST[0].xxxx
  8: F2I TEMP[2], -TEMP[2]
  9: AND TEMP[2], TEMP[2], IMM[0].yyyy
 10: ABS TEMP[0], TEMP[0]
 11: ADD TEMP[0], TEMP[0], -TEMP[2]
 12: MAD TEMP[1].xyz, CONST[0].zzzz, -TEMP[1].xzww, CONST[0].yyyy
 13: MAD TEMP[3].xy, TEMP[0].xzzz, IMM[0].wwww, IMM[0].yyyy
 14: MAD TEMP[4].x, TEMP[0].yyyy, IMM[0].wwww, TEMP[3].xxxx
 15: MOV TEMP[3].z, TEMP[4].xxxx
 16: MUL TEMP[4], TEMP[0], IMM[1].xxxx
 17: MAD TEMP[5].x, TEMP[0].wwww, IMM[0].wwww, TEMP[3].yyyy
 18: MOV TEMP[0].z, TEMP[5].xxxx
 19: MOV TEMP[3].xy, TEMP[4].xyxx
 20: MAD TEMP[5], CONST[0].zzzz, -TEMP[2], CONST[0].yyyy
 21: DP3 TEMP[6].x, TEMP[3].xyzz, TEMP[3].xyzz
 22: RSQ TEMP[6].x, TEMP[6].xxxx
 23: MUL TEMP[6].xyz, TEMP[3].xyzz, TEMP[6].xxxx
 24: MUL TEMP[3].xy, TEMP[5].xyyy, TEMP[6].xyyy
 25: MUL TEMP[6].x, TEMP[1].xxxx, TEMP[6].zzzz
 26: MOV TEMP[3].z, TEMP[6].xxxx
 27: MAD TEMP[3].xyz, IN[4].xyzz, CONST[3].xxxx, TEMP[3].xyzz
 28: MOV TEMP[0].xy, TEMP[4].zwzz
 29: DP3 TEMP[4].x, TEMP[3].xyzz, CONST[56].xyzz
 30: MOV TEMP[2].z, TEMP[4].xxxx
 31: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz
 32: RSQ TEMP[4].x, TEMP[4].xxxx
 33: MUL TEMP[4].xyz, TEMP[0].xyzz, TEMP[4].xxxx
 34: MUL TEMP[5].xy, TEMP[5].zwww, TEMP[4].xyyy
 35: MUL TEMP[4].x, TEMP[1].yyyy, TEMP[4].zzzz
 36: MOV TEMP[5].z, TEMP[4].xxxx
 37: DP3 TEMP[2].x, TEMP[3].xyzz, CONST[54].xyzz
 38: DP3 TEMP[3].x, TEMP[3].xyzz, CONST[55].xyzz
 39: MOV TEMP[2].y, TEMP[3].xxxx
 40: MAD TEMP[0].xyz, IN[4].xyzz, CONST[3].xxxx, TEMP[5].xyzz
 41: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[2].xyzz
 42: DP3 TEMP[3].x, TEMP[0].xyzz, CONST[56].xyzz
 43: MOV TEMP[5].z, TEMP[3].xxxx
 44: RSQ TEMP[3].x, TEMP[5].xxxx
 45: DP3 TEMP[5].x, TEMP[0].xyzz, CONST[54].xyzz
 46: DP3 TEMP[4].x, TEMP[0].xyzz, CONST[55].xyzz
 47: MOV TEMP[5].y, TEMP[4].xxxx
 48: MUL TEMP[3].xyz, TEMP[2].xyzz, TEMP[3].xxxx
 49: DP3 TEMP[0].x, TEMP[5].xyzz, TEMP[5].xyzz
 50: RSQ TEMP[4].x, TEMP[0].xxxx
 51: MUL TEMP[0].xyz, TEMP[2].zxyy, TEMP[5].yzxx
 52: MUL TEMP[4].xyz, TEMP[5].xyzz, TEMP[4].xxxx
 53: MAD TEMP[5].xyz, TEMP[2].yzxx, TEMP[5].zxyy, -TEMP[0].xyzz
 54: MOV TEMP[5].w, IN[0].wwww
 55: MUL TEMP[2].xyz, TEMP[1].zzzz, TEMP[5].xyzz
 56: MAD TEMP[5].xyz, IN[3].xyzz, CONST[3].xxxx, IN[0].xyzz
 57: DP3 TEMP[0].x, TEMP[2].xyzz, TEMP[2].xyzz
 58: DP4 TEMP[1].x, TEMP[5], CONST[56]
 59: MOV TEMP[0].z, TEMP[1].xxxx
 60: RSQ TEMP[1].x, TEMP[0].xxxx
 61: DP4 TEMP[0].x, TEMP[5], CONST[54]
 62: DP4 TEMP[6].x, TEMP[5], CONST[55]
 63: MOV TEMP[0].y, TEMP[6].xxxx
 64: MUL TEMP[1].xyz, TEMP[2].xyzz, TEMP[1].xxxx
 65: UIF CONST[58].xxxx :0
 66: ENDIF
 67: UIF CONST[59].xxxx :0
 68: ENDIF
 69: UIF CONST[60].xxxx :0
 70: ENDIF
 71: UIF CONST[61].xxxx :0
 72: ELSE :0
 73: ENDIF
 74: MOV TEMP[0].w, CONST[0].yyyy
 75: DP4 TEMP[6].x, TEMP[0], CONST[13]
 76: MOV TEMP[2].z, TEMP[6].xxxx
 77: MUL TEMP[6].x, IN[3].wwww, CONST[3].yyyy
 78: MOV TEMP[2].w, TEMP[6].xxxx
 79: MOV TEMP[2].zw, TEMP[2].wwzw
 80: DP4 TEMP[5].x, TEMP[0], CONST[8]
 81: DP4 TEMP[6].x, TEMP[0], CONST[9]
 82: MOV TEMP[5].y, TEMP[6].xxxx
 83: MOV TEMP[2].xy, TEMP[5].xyxx
 84: DP4 TEMP[7].x, TEMP[0], CONST[10]
 85: MOV TEMP[5].z, TEMP[7].xxxx
 86: DP4 TEMP[0].x, TEMP[0], CONST[11]
 87: MOV TEMP[5].w, TEMP[0].xxxx
 88: MOV TEMP[8].xw, TEMP[5].xxxw
 89: DP4 TEMP[9].x, IN[2], CONST[48]
 90: DP4 TEMP[10].x, IN[2], CONST[49]
 91: MOV TEMP[9].y, TEMP[10].xxxx
 92: DP4 TEMP[10].x, IN[2], CONST[52]
 93: MOV TEMP[9].z, TEMP[10].xxxx
 94: DP4 TEMP[10].x, IN[2], CONST[53]
 95: MOV TEMP[9].w, TEMP[10].xxxx
 96: MAD TEMP[7].x, TEMP[7].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
 97: MOV TEMP[8].z, TEMP[7].xxxx
 98: MOV TEMP[8].y, -TEMP[6].xxxx
 99: MAD TEMP[8].xy, CONST[57].xyyy, TEMP[0].xxxx, TEMP[8].xyyy
100: MOV OUT[2], TEMP[9]
101: MOV OUT[3], TEMP[4]
102: MOV OUT[0], TEMP[8]
103: MOV OUT[4], TEMP[1]
104: MOV OUT[1], TEMP[5]
105: MOV OUT[5], TEMP[3]
106: MOV OUT[6], TEMP[2]
107: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 776)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 792)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 832)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 836)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 840)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 844)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 848)
  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 852)
  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 856)
  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 860)
  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 864)
  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 868)
  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 872)
  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 876)
  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 880)
  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 884)
  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 888)
  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 892)
  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 896)
  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 900)
  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 904)
  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 908)
  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 912)
  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 916)
  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 944)
  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 960)
  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 976)
  %69 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %70 = load <16 x i8> addrspace(2)* %69, !tbaa !0
  %71 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %70, i32 0, i32 %5)
  %72 = extractelement <4 x float> %71, i32 0
  %73 = extractelement <4 x float> %71, i32 1
  %74 = extractelement <4 x float> %71, i32 2
  %75 = extractelement <4 x float> %71, i32 3
  %76 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %77 = load <16 x i8> addrspace(2)* %76, !tbaa !0
  %78 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %77, i32 0, i32 %5)
  %79 = extractelement <4 x float> %78, i32 0
  %80 = extractelement <4 x float> %78, i32 1
  %81 = extractelement <4 x float> %78, i32 2
  %82 = extractelement <4 x float> %78, i32 3
  %83 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %84 = load <16 x i8> addrspace(2)* %83, !tbaa !0
  %85 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %84, i32 0, i32 %5)
  %86 = extractelement <4 x float> %85, i32 0
  %87 = extractelement <4 x float> %85, i32 1
  %88 = extractelement <4 x float> %85, i32 2
  %89 = extractelement <4 x float> %85, i32 3
  %90 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
  %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %5)
  %93 = extractelement <4 x float> %92, i32 0
  %94 = extractelement <4 x float> %92, i32 1
  %95 = extractelement <4 x float> %92, i32 2
  %96 = extractelement <4 x float> %92, i32 3
  %97 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %98 = load <16 x i8> addrspace(2)* %97, !tbaa !0
  %99 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %98, i32 0, i32 %5)
  %100 = extractelement <4 x float> %99, i32 0
  %101 = extractelement <4 x float> %99, i32 1
  %102 = extractelement <4 x float> %99, i32 2
  %103 = fadd float %79, -1.280000e+02
  %104 = fadd float %80, -1.280000e+02
  %105 = fadd float %81, -1.280000e+02
  %106 = fadd float %82, -1.280000e+02
  %107 = fcmp ult float %103, %11
  %108 = select i1 %107, float 1.000000e+00, float 0.000000e+00
  %109 = fcmp ult float %104, %11
  %110 = select i1 %109, float 1.000000e+00, float 0.000000e+00
  %111 = fcmp ult float %105, %11
  %112 = select i1 %111, float 1.000000e+00, float 0.000000e+00
  %113 = fcmp ult float %106, %11
  %114 = select i1 %113, float 1.000000e+00, float 0.000000e+00
  %115 = fsub float -0.000000e+00, %108
  %116 = fptosi float %115 to i32
  %117 = fsub float -0.000000e+00, %110
  %118 = fptosi float %117 to i32
  %119 = fsub float -0.000000e+00, %112
  %120 = fptosi float %119 to i32
  %121 = fsub float -0.000000e+00, %114
  %122 = fptosi float %121 to i32
  %123 = bitcast i32 %116 to float
  %124 = bitcast i32 %118 to float
  %125 = bitcast i32 %120 to float
  %126 = bitcast i32 %122 to float
  %127 = bitcast float %123 to i32
  %128 = and i32 %127, 1065353216
  %129 = bitcast float %124 to i32
  %130 = and i32 %129, 1065353216
  %131 = bitcast float %125 to i32
  %132 = and i32 %131, 1065353216
  %133 = bitcast float %126 to i32
  %134 = and i32 %133, 1065353216
  %135 = bitcast i32 %128 to float
  %136 = bitcast i32 %130 to float
  %137 = bitcast i32 %132 to float
  %138 = bitcast i32 %134 to float
  %139 = call float @fabs(float %103)
  %140 = call float @fabs(float %104)
  %141 = call float @fabs(float %105)
  %142 = call float @fabs(float %106)
  %143 = fsub float -0.000000e+00, %135
  %144 = fadd float %139, %143
  %145 = fsub float -0.000000e+00, %136
  %146 = fadd float %140, %145
  %147 = fsub float -0.000000e+00, %137
  %148 = fadd float %141, %147
  %149 = fsub float -0.000000e+00, %138
  %150 = fadd float %142, %149
  %151 = fadd float %144, -6.400000e+01
  %152 = fadd float %146, -6.400000e+01
  %153 = fadd float %148, -6.400000e+01
  %154 = fadd float %150, -6.400000e+01
  %155 = fcmp ult float %151, %11
  %156 = select i1 %155, float 1.000000e+00, float 0.000000e+00
  %157 = fcmp ult float %152, %11
  %158 = select i1 %157, float 1.000000e+00, float 0.000000e+00
  %159 = fcmp ult float %153, %11
  %160 = select i1 %159, float 1.000000e+00, float 0.000000e+00
  %161 = fcmp ult float %154, %11
  %162 = select i1 %161, float 1.000000e+00, float 0.000000e+00
  %163 = fsub float -0.000000e+00, %156
  %164 = fptosi float %163 to i32
  %165 = fsub float -0.000000e+00, %158
  %166 = fptosi float %165 to i32
  %167 = fsub float -0.000000e+00, %160
  %168 = fptosi float %167 to i32
  %169 = fsub float -0.000000e+00, %162
  %170 = fptosi float %169 to i32
  %171 = bitcast i32 %164 to float
  %172 = bitcast i32 %166 to float
  %173 = bitcast i32 %168 to float
  %174 = bitcast i32 %170 to float
  %175 = bitcast float %171 to i32
  %176 = and i32 %175, 1065353216
  %177 = bitcast float %172 to i32
  %178 = and i32 %177, 1065353216
  %179 = bitcast float %173 to i32
  %180 = and i32 %179, 1065353216
  %181 = bitcast float %174 to i32
  %182 = and i32 %181, 1065353216
  %183 = bitcast i32 %176 to float
  %184 = bitcast i32 %178 to float
  %185 = bitcast i32 %180 to float
  %186 = bitcast i32 %182 to float
  %187 = call float @fabs(float %151)
  %188 = call float @fabs(float %152)
  %189 = call float @fabs(float %153)
  %190 = call float @fabs(float %154)
  %191 = fsub float -0.000000e+00, %183
  %192 = fadd float %187, %191
  %193 = fsub float -0.000000e+00, %184
  %194 = fadd float %188, %193
  %195 = fsub float -0.000000e+00, %185
  %196 = fadd float %189, %195
  %197 = fsub float -0.000000e+00, %186
  %198 = fadd float %190, %197
  %199 = fsub float -0.000000e+00, %135
  %200 = fmul float %13, %199
  %201 = fadd float %200, %12
  %202 = fsub float -0.000000e+00, %137
  %203 = fmul float %13, %202
  %204 = fadd float %203, %12
  %205 = fsub float -0.000000e+00, %138
  %206 = fmul float %13, %205
  %207 = fadd float %206, %12
  %208 = fmul float %192, 0xBF90410420000000
  %209 = fadd float %208, 1.000000e+00
  %210 = fmul float %196, 0xBF90410420000000
  %211 = fadd float %210, 1.000000e+00
  %212 = fmul float %194, 0xBF90410420000000
  %213 = fadd float %212, %209
  %214 = fmul float %192, 0x3F90410420000000
  %215 = fmul float %194, 0x3F90410420000000
  %216 = fmul float %196, 0x3F90410420000000
  %217 = fmul float %198, 0x3F90410420000000
  %218 = fmul float %198, 0xBF90410420000000
  %219 = fadd float %218, %211
  %220 = fsub float -0.000000e+00, %183
  %221 = fmul float %13, %220
  %222 = fadd float %221, %12
  %223 = fsub float -0.000000e+00, %184
  %224 = fmul float %13, %223
  %225 = fadd float %224, %12
  %226 = fsub float -0.000000e+00, %185
  %227 = fmul float %13, %226
  %228 = fadd float %227, %12
  %229 = fsub float -0.000000e+00, %186
  %230 = fmul float %13, %229
  %231 = fadd float %230, %12
  %232 = fmul float %214, %214
  %233 = fmul float %215, %215
  %234 = fadd float %233, %232
  %235 = fmul float %213, %213
  %236 = fadd float %234, %235
  %237 = call float @fabs(float %236)
  %238 = call float @llvm.AMDGPU.rsq(float %237)
  %239 = fmul float %214, %238
  %240 = fmul float %215, %238
  %241 = fmul float %213, %238
  %242 = fmul float %222, %239
  %243 = fmul float %225, %240
  %244 = fmul float %201, %241
  %245 = fmul float %100, %14
  %246 = fadd float %245, %242
  %247 = fmul float %101, %14
  %248 = fadd float %247, %243
  %249 = fmul float %102, %14
  %250 = fadd float %249, %244
  %251 = fmul float %246, %60
  %252 = fmul float %248, %61
  %253 = fadd float %252, %251
  %254 = fmul float %250, %62
  %255 = fadd float %253, %254
  %256 = fmul float %216, %216
  %257 = fmul float %217, %217
  %258 = fadd float %257, %256
  %259 = fmul float %219, %219
  %260 = fadd float %258, %259
  %261 = call float @fabs(float %260)
  %262 = call float @llvm.AMDGPU.rsq(float %261)
  %263 = fmul float %216, %262
  %264 = fmul float %217, %262
  %265 = fmul float %219, %262
  %266 = fmul float %228, %263
  %267 = fmul float %231, %264
  %268 = fmul float %204, %265
  %269 = fmul float %246, %52
  %270 = fmul float %248, %53
  %271 = fadd float %270, %269
  %272 = fmul float %250, %54
  %273 = fadd float %271, %272
  %274 = fmul float %246, %56
  %275 = fmul float %248, %57
  %276 = fadd float %275, %274
  %277 = fmul float %250, %58
  %278 = fadd float %276, %277
  %279 = fmul float %100, %14
  %280 = fadd float %279, %266
  %281 = fmul float %101, %14
  %282 = fadd float %281, %267
  %283 = fmul float %102, %14
  %284 = fadd float %283, %268
  %285 = fmul float %273, %273
  %286 = fmul float %278, %278
  %287 = fadd float %286, %285
  %288 = fmul float %255, %255
  %289 = fadd float %287, %288
  %290 = fmul float %280, %60
  %291 = fmul float %282, %61
  %292 = fadd float %291, %290
  %293 = fmul float %284, %62
  %294 = fadd float %292, %293
  %295 = call float @fabs(float %289)
  %296 = call float @llvm.AMDGPU.rsq(float %295)
  %297 = fmul float %280, %52
  %298 = fmul float %282, %53
  %299 = fadd float %298, %297
  %300 = fmul float %284, %54
  %301 = fadd float %299, %300
  %302 = fmul float %280, %56
  %303 = fmul float %282, %57
  %304 = fadd float %303, %302
  %305 = fmul float %284, %58
  %306 = fadd float %304, %305
  %307 = fmul float %273, %296
  %308 = fmul float %278, %296
  %309 = fmul float %255, %296
  %310 = fmul float %301, %301
  %311 = fmul float %306, %306
  %312 = fadd float %311, %310
  %313 = fmul float %294, %294
  %314 = fadd float %312, %313
  %315 = call float @fabs(float %314)
  %316 = call float @llvm.AMDGPU.rsq(float %315)
  %317 = fmul float %255, %306
  %318 = fmul float %273, %294
  %319 = fmul float %278, %301
  %320 = fmul float %301, %316
  %321 = fmul float %306, %316
  %322 = fmul float %294, %316
  %323 = fsub float -0.000000e+00, %317
  %324 = fmul float %278, %294
  %325 = fadd float %324, %323
  %326 = fsub float -0.000000e+00, %318
  %327 = fmul float %255, %301
  %328 = fadd float %327, %326
  %329 = fsub float -0.000000e+00, %319
  %330 = fmul float %273, %306
  %331 = fadd float %330, %329
  %332 = fmul float %207, %325
  %333 = fmul float %207, %328
  %334 = fmul float %207, %331
  %335 = fmul float %93, %14
  %336 = fadd float %335, %72
  %337 = fmul float %94, %14
  %338 = fadd float %337, %73
  %339 = fmul float %95, %14
  %340 = fadd float %339, %74
  %341 = fmul float %332, %332
  %342 = fmul float %333, %333
  %343 = fadd float %342, %341
  %344 = fmul float %334, %334
  %345 = fadd float %343, %344
  %346 = fmul float %336, %60
  %347 = fmul float %338, %61
  %348 = fadd float %346, %347
  %349 = fmul float %340, %62
  %350 = fadd float %348, %349
  %351 = fmul float %75, %63
  %352 = fadd float %350, %351
  %353 = call float @fabs(float %345)
  %354 = call float @llvm.AMDGPU.rsq(float %353)
  %355 = fmul float %336, %52
  %356 = fmul float %338, %53
  %357 = fadd float %355, %356
  %358 = fmul float %340, %54
  %359 = fadd float %357, %358
  %360 = fmul float %75, %55
  %361 = fadd float %359, %360
  %362 = fmul float %336, %56
  %363 = fmul float %338, %57
  %364 = fadd float %362, %363
  %365 = fmul float %340, %58
  %366 = fadd float %364, %365
  %367 = fmul float %75, %59
  %368 = fadd float %366, %367
  %369 = fmul float %332, %354
  %370 = fmul float %333, %354
  %371 = fmul float %334, %354
  %372 = bitcast float %66 to i32
  %373 = icmp ne i32 %372, 0
  %374 = bitcast float %67 to i32
  %375 = icmp ne i32 %374, 0
  %376 = bitcast float %68 to i32
  %377 = icmp ne i32 %376, 0
  %378 = fmul float %361, %32
  %379 = fmul float %368, %33
  %380 = fadd float %378, %379
  %381 = fmul float %352, %34
  %382 = fadd float %380, %381
  %383 = fmul float %12, %35
  %384 = fadd float %382, %383
  %385 = fmul float %96, %15
  %386 = fmul float %361, %16
  %387 = fmul float %368, %17
  %388 = fadd float %386, %387
  %389 = fmul float %352, %18
  %390 = fadd float %388, %389
  %391 = fmul float %12, %19
  %392 = fadd float %390, %391
  %393 = fmul float %361, %20
  %394 = fmul float %368, %21
  %395 = fadd float %393, %394
  %396 = fmul float %352, %22
  %397 = fadd float %395, %396
  %398 = fmul float %12, %23
  %399 = fadd float %397, %398
  %400 = fmul float %361, %24
  %401 = fmul float %368, %25
  %402 = fadd float %400, %401
  %403 = fmul float %352, %26
  %404 = fadd float %402, %403
  %405 = fmul float %12, %27
  %406 = fadd float %404, %405
  %407 = fmul float %361, %28
  %408 = fmul float %368, %29
  %409 = fadd float %407, %408
  %410 = fmul float %352, %30
  %411 = fadd float %409, %410
  %412 = fmul float %12, %31
  %413 = fadd float %411, %412
  %414 = fmul float %86, %36
  %415 = fmul float %87, %37
  %416 = fadd float %414, %415
  %417 = fmul float %88, %38
  %418 = fadd float %416, %417
  %419 = fmul float %89, %39
  %420 = fadd float %418, %419
  %421 = fmul float %86, %40
  %422 = fmul float %87, %41
  %423 = fadd float %421, %422
  %424 = fmul float %88, %42
  %425 = fadd float %423, %424
  %426 = fmul float %89, %43
  %427 = fadd float %425, %426
  %428 = fmul float %86, %44
  %429 = fmul float %87, %45
  %430 = fadd float %428, %429
  %431 = fmul float %88, %46
  %432 = fadd float %430, %431
  %433 = fmul float %89, %47
  %434 = fadd float %432, %433
  %435 = fmul float %86, %48
  %436 = fmul float %87, %49
  %437 = fadd float %435, %436
  %438 = fmul float %88, %50
  %439 = fadd float %437, %438
  %440 = fmul float %89, %51
  %441 = fadd float %439, %440
  %442 = fsub float -0.000000e+00, %413
  %443 = fmul float %406, %13
  %444 = fadd float %443, %442
  %445 = fsub float -0.000000e+00, %399
  %446 = fmul float %64, %413
  %447 = fadd float %446, %392
  %448 = fmul float %65, %413
  %449 = fadd float %448, %445
  %450 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %451 = load <16 x i8> addrspace(2)* %450, !tbaa !0
  %452 = call float @llvm.SI.load.const(<16 x i8> %451, i32 0)
  %453 = fmul float %452, %392
  %454 = call float @llvm.SI.load.const(<16 x i8> %451, i32 4)
  %455 = fmul float %454, %399
  %456 = fadd float %453, %455
  %457 = call float @llvm.SI.load.const(<16 x i8> %451, i32 8)
  %458 = fmul float %457, %406
  %459 = fadd float %456, %458
  %460 = call float @llvm.SI.load.const(<16 x i8> %451, i32 12)
  %461 = fmul float %460, %413
  %462 = fadd float %459, %461
  %463 = call float @llvm.SI.load.const(<16 x i8> %451, i32 16)
  %464 = fmul float %463, %392
  %465 = call float @llvm.SI.load.const(<16 x i8> %451, i32 20)
  %466 = fmul float %465, %399
  %467 = fadd float %464, %466
  %468 = call float @llvm.SI.load.const(<16 x i8> %451, i32 24)
  %469 = fmul float %468, %406
  %470 = fadd float %467, %469
  %471 = call float @llvm.SI.load.const(<16 x i8> %451, i32 28)
  %472 = fmul float %471, %413
  %473 = fadd float %470, %472
  %474 = call float @llvm.SI.load.const(<16 x i8> %451, i32 32)
  %475 = fmul float %474, %392
  %476 = call float @llvm.SI.load.const(<16 x i8> %451, i32 36)
  %477 = fmul float %476, %399
  %478 = fadd float %475, %477
  %479 = call float @llvm.SI.load.const(<16 x i8> %451, i32 40)
  %480 = fmul float %479, %406
  %481 = fadd float %478, %480
  %482 = call float @llvm.SI.load.const(<16 x i8> %451, i32 44)
  %483 = fmul float %482, %413
  %484 = fadd float %481, %483
  %485 = call float @llvm.SI.load.const(<16 x i8> %451, i32 48)
  %486 = fmul float %485, %392
  %487 = call float @llvm.SI.load.const(<16 x i8> %451, i32 52)
  %488 = fmul float %487, %399
  %489 = fadd float %486, %488
  %490 = call float @llvm.SI.load.const(<16 x i8> %451, i32 56)
  %491 = fmul float %490, %406
  %492 = fadd float %489, %491
  %493 = call float @llvm.SI.load.const(<16 x i8> %451, i32 60)
  %494 = fmul float %493, %413
  %495 = fadd float %492, %494
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %462, float %473, float %484, float %495)
  %496 = call float @llvm.SI.load.const(<16 x i8> %451, i32 64)
  %497 = fmul float %496, %392
  %498 = call float @llvm.SI.load.const(<16 x i8> %451, i32 68)
  %499 = fmul float %498, %399
  %500 = fadd float %497, %499
  %501 = call float @llvm.SI.load.const(<16 x i8> %451, i32 72)
  %502 = fmul float %501, %406
  %503 = fadd float %500, %502
  %504 = call float @llvm.SI.load.const(<16 x i8> %451, i32 76)
  %505 = fmul float %504, %413
  %506 = fadd float %503, %505
  %507 = call float @llvm.SI.load.const(<16 x i8> %451, i32 80)
  %508 = fmul float %507, %392
  %509 = call float @llvm.SI.load.const(<16 x i8> %451, i32 84)
  %510 = fmul float %509, %399
  %511 = fadd float %508, %510
  %512 = call float @llvm.SI.load.const(<16 x i8> %451, i32 88)
  %513 = fmul float %512, %406
  %514 = fadd float %511, %513
  %515 = call float @llvm.SI.load.const(<16 x i8> %451, i32 92)
  %516 = fmul float %515, %413
  %517 = fadd float %514, %516
  %518 = call float @llvm.SI.load.const(<16 x i8> %451, i32 96)
  %519 = fmul float %518, %392
  %520 = call float @llvm.SI.load.const(<16 x i8> %451, i32 100)
  %521 = fmul float %520, %399
  %522 = fadd float %519, %521
  %523 = call float @llvm.SI.load.const(<16 x i8> %451, i32 104)
  %524 = fmul float %523, %406
  %525 = fadd float %522, %524
  %526 = call float @llvm.SI.load.const(<16 x i8> %451, i32 108)
  %527 = fmul float %526, %413
  %528 = fadd float %525, %527
  %529 = call float @llvm.SI.load.const(<16 x i8> %451, i32 112)
  %530 = fmul float %529, %392
  %531 = call float @llvm.SI.load.const(<16 x i8> %451, i32 116)
  %532 = fmul float %531, %399
  %533 = fadd float %530, %532
  %534 = call float @llvm.SI.load.const(<16 x i8> %451, i32 120)
  %535 = fmul float %534, %406
  %536 = fadd float %533, %535
  %537 = call float @llvm.SI.load.const(<16 x i8> %451, i32 124)
  %538 = fmul float %537, %413
  %539 = fadd float %536, %538
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %506, float %517, float %528, float %539)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %420, float %427, float %434, float %441)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %320, float %321, float %322, float %217)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %369, float %370, float %371, float %138)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %307, float %308, float %309, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %392, float %399, float %384, float %385)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %447, float %449, float %444, float %413)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #3

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%69](tbaa=!"const")
	S_WAITCNT 127
	%VGPR7_VGPR8_VGPR9_VGPR10<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%90](tbaa=!"const")
	S_WAITCNT 112
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 12
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR1, %SGPR3, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 217
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR13, %VGPR12, %EXEC<imp-use>
	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 216
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR11, %SGPR15, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR3, %SGPR3, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 218
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR13, %SGPR14, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 219
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR10, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 221
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4, %VGPR12, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 220
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR11, %SGPR5, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 222
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR13, %SGPR12, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 223
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR10, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR5, %SGPR2<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 225
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR16, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR17<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 224
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %SGPR17, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR18<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 226
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR13<kill>, %SGPR18, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 227
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR10, %SGPR2<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8_VGPR9_VGPR10<imp-use,kill>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR8, %SGPR2<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 35
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR19<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %SGPR2, %VGPR9<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 37
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR19<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 36
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR19<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 38
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR8, %SGPR19<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 39
	S_WAITCNT 127
	%VGPR10<def> = V_MOV_B32_e32 %SGPR19<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %SGPR2, %VGPR10<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 4; mem:LD16[%447](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 13
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 12
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 41
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 40
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 42
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 43
	S_WAITCNT 127
	%VGPR12<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %SGPR2, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 14
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR10, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 45
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 44
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 46
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR13<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %SGPR2, %VGPR13<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 15
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR11, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 9
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 8
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 10
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %SGPR0<kill>, %VGPR10, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 11
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %SGPR0<kill>, %VGPR11, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 5
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 4
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 6
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %SGPR0<kill>, %VGPR10, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 7
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %SGPR0<kill>, %VGPR11, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 1
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 0
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 2
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %SGPR0<kill>, %VGPR10, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 3
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %SGPR0<kill>, %VGPR11, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR15<kill>, %VGPR14<kill>, %VGPR13<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 29
	S_WAITCNT 15
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 28
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 30
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR10, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 31
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR11, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 25
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 24
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 26
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %SGPR0<kill>, %VGPR10, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 27
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %SGPR0<kill>, %VGPR11, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 21
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 20
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 22
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %SGPR0<kill>, %VGPR10, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 23
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %SGPR0<kill>, %VGPR11, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 17
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 16
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 18
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %SGPR0<kill>, %VGPR10, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23<kill>, 19
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %SGPR0<kill>, %VGPR11, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR15<kill>, %VGPR14<kill>, %VGPR13<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%83](tbaa=!"const")
	S_WAITCNT 15
	%VGPR12_VGPR13_VGPR14_VGPR15<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR20_SGPR21_SGPR22_SGPR23<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 213
	S_WAITCNT 112
	%VGPR16<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 212
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR12, %SGPR0<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 214
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR14, %SGPR0<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 215
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR15, %SGPR0<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 209
	S_WAITCNT 127
	%VGPR17<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 208
	S_WAITCNT 127
	%VGPR17<def> = V_MAD_F32 %VGPR12, %SGPR0<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 210
	S_WAITCNT 127
	%VGPR17<def> = V_MAD_F32 %VGPR14, %SGPR0<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 211
	S_WAITCNT 127
	%VGPR17<def> = V_MAD_F32 %VGPR15, %SGPR0<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 197
	S_WAITCNT 127
	%VGPR18<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 196
	S_WAITCNT 127
	%VGPR18<def> = V_MAD_F32 %VGPR12, %SGPR0<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 198
	S_WAITCNT 127
	%VGPR18<def> = V_MAD_F32 %VGPR14, %SGPR0<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 199
	S_WAITCNT 127
	%VGPR18<def> = V_MAD_F32 %VGPR15, %SGPR0<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 193
	S_WAITCNT 127
	%VGPR19<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 192
	S_WAITCNT 127
	%VGPR19<def> = V_MAD_F32 %VGPR12, %SGPR0<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 194
	S_WAITCNT 127
	%VGPR19<def> = V_MAD_F32 %VGPR14, %SGPR0<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 195
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR15, %SGPR0<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR12<kill>, %VGPR18<kill>, %VGPR17<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%76](tbaa=!"const")
	S_WAITCNT 15
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR20_SGPR21_SGPR22_SGPR23<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR12<def> = V_ADD_F32_e32 -1.280000e+02, %VGPR16, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e64 %VGPR12, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%SGPR20_SGPR21<def> = V_CMP_LT_F32_e64 %VGPR12<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_F32_e64 %VGPR12<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR12<def> = V_CVT_I32_F32_e32 %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %VGPR17<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e32 -6.400000e+01, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e64 %VGPR17, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_LT_F32_e64 %VGPR17<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e64 %VGPR17<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR17<def> = V_CVT_I32_F32_e32 %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_AND_B32_e32 1065353216, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %VGPR18<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e32 -1.280000e+02, %VGPR15, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e64 %VGPR20, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_LT_F32_e64 %VGPR20<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e64 %VGPR20<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR20<def> = V_CVT_I32_F32_e32 %VGPR20<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_AND_B32_e32 1065353216, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 %VGPR19<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e32 -6.400000e+01, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e64 %VGPR20, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_LT_F32_e64 %VGPR20<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e64 %VGPR20<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR20<def> = V_CVT_I32_F32_e32 %VGPR20<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_AND_B32_e32 1065353216, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 %VGPR19<kill>, %VGPR25, %EXEC<imp-use>
	%VGPR22<def> = V_MOV_B32_e32 -1.587302e-02, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR19, %VGPR22, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR18, %VGPR22, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 1.587302e-02, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 1.587302e-02, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR28, %VGPR28, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR24, %VGPR24, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR23, %VGPR23, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e64 %VGPR18<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_RSQ_LEGACY_F32_e32 %VGPR18<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR24, %VGPR27, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR17<def> = V_MUL_F32_e32 %SGPR0, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %SGPR2, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR18<kill>, %EXEC<imp-use>
	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 16; mem:LD16[%97](tbaa=!"const")
	S_WAITCNT 127
	%VGPR17_VGPR18_VGPR19_VGPR20<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR20_SGPR21_SGPR22_SGPR23<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR26<def> = V_MAD_F32 %VGPR18, %SGPR3, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR27, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %SGPR0, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_SUB_F32_e32 %SGPR2, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR17, %SGPR3, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %SGPR5, %VGPR25, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR26, %SGPR4, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR23<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %SGPR0, %VGPR21<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_SUB_F32_e32 %SGPR2, %VGPR21<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR21<kill>, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR19, %SGPR3, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR23, %SGPR12, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %SGPR15, %VGPR25, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR26, %SGPR13, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR23, %SGPR14, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR21, %VGPR21, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR0, %VGPR0, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %SGPR17, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR26<kill>, %SGPR16, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR23<kill>, %SGPR18, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR23, %VGPR23, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR25<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_RSQ_LEGACY_F32_e32 %VGPR25<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR23, %VGPR25, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR0, %VGPR25, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR21, %VGPR25<kill>, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR25<kill>, %VGPR27<kill>, %VGPR26<kill>, %VGPR24<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR25<def> = V_ADD_F32_e32 -1.280000e+02, %VGPR14, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 %VGPR25, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_F32_e64 %VGPR25<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR25<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR25<def> = V_CVT_I32_F32_e32 %VGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_AND_B32_e32 1065353216, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_SUB_F32_e32 %VGPR24<kill>, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e32 -6.400000e+01, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR24, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_F32_e64 %VGPR24<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 %VGPR24<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR24<def> = V_CVT_I32_F32_e32 %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_AND_B32_e32 1065353216, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_SUB_F32_e32 %VGPR25<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e32 -1.280000e+02, %VGPR13, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%VGPR14<def> = V_ADD_F32_e64 %VGPR13, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_F32_e64 %VGPR13<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e64 %VGPR13<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR13<def> = V_CVT_I32_F32_e32 %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_AND_B32_e32 1065353216, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR14<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e32 -6.400000e+01, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e64 %VGPR15, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_F32_e64 %VGPR15<kill>, %SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e64 %VGPR15<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR15<def> = V_CVT_I32_F32_e32 %VGPR15<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_AND_B32_e32 1065353216, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_SUB_F32_e32 %VGPR14<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR26, %VGPR22, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR25, %VGPR22<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 1.587302e-02, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 1.587302e-02, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR25, %VGPR25, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR15, %VGPR15, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR14, %VGPR14, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_ADD_F32_e64 %VGPR22<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_RSQ_LEGACY_F32_e32 %VGPR22<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR22, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR0, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_SUB_F32_e32 %SGPR2, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR18, %SGPR3, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR22, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %SGPR0, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_SUB_F32_e32 %SGPR2, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR17, %SGPR3, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR15<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR15, %SGPR13<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %SGPR2, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR19, %SGPR3<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>
	%VGPR13<def> = V_MAD_F32 %VGPR18, %SGPR14<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR13, %VGPR23, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %SGPR17<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR15, %SGPR16<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR18, %SGPR18<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR14, %VGPR21, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %VGPR19<kill>, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %SGPR0, %VGPR12, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 %SGPR2, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR19, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR14, %VGPR0, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR15<kill>, %SGPR4<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR18<kill>, %SGPR12<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR15, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_SUB_F32_e32 %VGPR16<kill>, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR19, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR16, %VGPR16, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR17, %VGPR17, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR15, %VGPR21<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR13, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_SUB_F32_e32 %VGPR0<kill>, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR19<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR0, %VGPR0, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e64 %VGPR18<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_RSQ_LEGACY_F32_e32 %VGPR18<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR18<kill>, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR16<kill>, %VGPR17<kill>, %VGPR0<kill>, %VGPR12<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_MUL_F32_e32 %VGPR13, %VGPR13, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR15, %VGPR15, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR14, %VGPR14, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_RSQ_LEGACY_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR12<kill>, %VGPR14<kill>, %VGPR0<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 53
	S_WAITCNT 15
	%VGPR0<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 52
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR5<kill>, %SGPR1<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 54
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR8<kill>, %SGPR1<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 55
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %SGPR2<kill>, %VGPR5<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 13
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 36, 0, 0, 0, %VGPR7, %VGPR9, %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 228
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR1<kill>, %VGPR11, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR11, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 229
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR9<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR11<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840700
bf8c007f
e00c2000
80020700
c084070c
bf8c0070
e00c2000
80020100
c0840100
bf8c0070
c201890c
bf8c007f
d282000b
041c0701
d282000c
04200702
c20689d9
bf8c007f
100a180d
c20789d8
bf8c007f
d2820005
04141f0b
d282000d
04240703
c20709da
bf8c007f
d2820005
04141d0d
c20109db
bf8c007f
d2820005
0414050a
c20209dd
bf8c007f
100c1804
c20289dc
bf8c007f
d2820006
04180b0b
c20609de
bf8c007f
d2820006
0418190d
c20109df
bf8c007f
d2820006
0418050a
c2010921
bf8c007f
101c0c02
c2010920
bf8c007f
d282000e
04380505
c20809e1
bf8c007f
10181810
c20889e0
bf8c007f
d282000b
0430230b
c20909e2
bf8c007f
d282000b
042c250d
c20109e3
bf8c007f
d2820008
042c050a
c2010922
bf8c007f
d2820007
04380508
c2010901
c2098923
bf8c007f
7e120213
d2820007
041e1202
c2098925
bf8c007f
10120c13
c2098924
bf8c007f
d2820009
04242705
c2098926
bf8c007f
d2820009
04242708
c2098927
bf8c007f
7e140213
d2820009
04261402
c08a0104
bf8c007f
c200150d
bf8c007f
10141200
c200150c
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d282000b
042a0e00
c2000929
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10140c00
c2000928
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d282000a
04280105
c200092a
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d282000a
04280108
c200092b
bf8c007f
7e180200
d282000a
042a1802
c200150e
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d282000c
042e1400
c200092d
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10160c00
c200092c
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d282000b
042c0105
c200092e
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d282000b
042c0108
c200092f
bf8c007f
7e1a0200
d282000b
042e1a02
c200150f
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d282000c
04321600
c2001509
bf8c007f
101a1200
c2001508
bf8c007f
d282000d
04360e00
c200150a
bf8c007f
d282000d
04361400
c200150b
bf8c007f
d282000d
04361600
c2001505
bf8c007f
101c1200
c2001504
bf8c007f
d282000e
043a0e00
c2001506
bf8c007f
d282000e
043a1400
c2001507
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d282000e
043a1600
c2001501
bf8c007f
101e1200
c2001500
bf8c007f
d282000f
043e0e00
c2001502
bf8c007f
d282000f
043e1400
c2001503
bf8c007f
d282000f
043e1600
f80000ef
0c0d0e0f
c200151d
bf8c000f
10181200
c200151c
bf8c007f
d282000c
04320e00
c200151e
bf8c007f
d282000c
04321400
c200151f
bf8c007f
d282000c
04321600
c2001519
bf8c007f
101a1200
c2001518
bf8c007f
d282000d
04360e00
c200151a
bf8c007f
d282000d
04361400
c200151b
bf8c007f
d282000d
04361600
c2001515
bf8c007f
101c1200
c2001514
bf8c007f
d282000e
043a0e00
c2001516
bf8c007f
d282000e
043a1400
c2001517
bf8c007f
d282000e
043a1600
c2001511
bf8c007f
101e1200
c2001510
bf8c007f
d282000f
043e0e00
c2001512
bf8c007f
d282000f
043e1400
c2001513
bf8c007f
d282000f
043e1600
f80000ff
0c0d0e0f
c08a0708
bf8c000f
e00c2000
80050c00
c20009d5
bf8c0070
10201a00
c20009d4
bf8c007f
d2820010
0440010c
c20009d6
bf8c007f
d2820010
0440010e
c20009d7
bf8c007f
d2820010
0440010f
c20009d1
bf8c007f
10221a00
c20009d0
bf8c007f
d2820011
0444010c
c20009d2
bf8c007f
d2820011
0444010e
c20009d3
bf8c007f
d2820011
0444010f
c20009c5
bf8c007f
10241a00
c20009c4
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d2820012
0448010c
c20009c6
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d2820012
0448010e
c20009c7
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d2820012
0448010f
c20009c1
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10261a00
c20009c0
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d2820013
044c010c
c20009c2
bf8c007f
d2820013
044c010e
c20009c3
bf8c007f
d282000c
044c010f
f800020f
1011120c
c08a0704
bf8c000f
e00c2000
80050d00
bf8c0770
061820ff
c3000000
d2060111
0201010c
c2008900
bf8c007f
d0020014
0200030c
d200000c
0051e480
d206000c
2201010c
7e18110c
361818f2
08221911
062222ff
c2800000
d2060112
02010111
d0020014
02000311
d2000011
0051e480
d2060011
22010111
7e221111
362222f2
08242312
06281eff
c3000000
d2060113
02010114
d0020014
02000314
d2000014
0051e480
d2060014
22010114
7e281114
362a28f2
08262b13
062826ff
c2800000
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02010114
d0020014
02000314
d2000014
0051e480
d2060014
22010114
7e281114
363228f2
08263313
7e2c02ff
bc820821
d2820014
03ca2d13
d2820017
04522d12
103024ff
3c820821
103826ff
3c820821
1024391c
d2820012
044a3118
d2820012
044a2f17
d2060112
02010112
7e365b12
10243718
c2000902
bf8c007f
10222200
08222202
10342511
c08a0710
bf8c007f
e00c2000
80051100
bf8c0770
d282001a
04680712
1000371c
10323200
08323202
10000119
d2820019
04000711
10003205
d2820000
0400091a
102e3717
102a2a00
082a2a02
102a2f15
d2820017
04540713
d2820000
04001917
102a320f
d2820015
04541b1a
d2820015
04541d17
10362b15
d282001b
046e0100
10323211
d2820019
0464211a
d2820017
04642517
d2820019
046e2f17
d2060119
02010119
7e325b19
10343317
10363300
10323315
f800021f
181a1b19
bf8c070f
06321cff
c3000000
d2060118
02010119
d0020006
02000319
d2000019
0019e480
d2060019
22010119
7e321119
363232f2
08303318
063030ff
c2800000
d2060119
02010118
d0020006
02000318
d2000018
0019e480
d2060018
22010118
7e301118
363030f2
08323119
061a1aff
c3000000
d206010e
0201010d
d0020006
0200030d
d200000d
0019e480
d206000d
2201010d
7e1a110d
361a1af2
081c1b0e
061e1cff
c2800000
d206010e
0201010f
d0020006
0200030f
d200000f
0019e480
d206000f
2201010f
7e1e110f
36201ef2
0834210e
d282000e
03ca2d1a
d282000e
043a2d19
101e32ff
3c820821
103234ff
3c820821
102c3319
d2820016
045a1f0f
d2820016
045a1d0e
d2060116
02010116
7e2c5b16
101e2d0f
10303000
08303002
101e1f18
d282000f
043c0712
10302d19
10202000
08202002
10203110
d2820010
04400711
1030200f
d2820018
04601b0f
101c2d0e
101a1a00
081a1a02
101a1d0d
d2820012
04340713
d282000d
04601d12
10222f0d
101c2011
d282000e
0438210f
d282000e
04382512
10262b0e
08222313
10261800
08262602
10222313
1028010e
10202005
d282000f
0440090f
d282000f
043c1912
10202f0f
08202910
10202113
10242110
d2820012
044a2311
10282b0f
1000010d
08002900
10000113
d2820012
044a0100
d2060112
02010112
7e245b12
10002500
10222511
10202510
f800022f
0c001110
bf8c070f
10001b0d
d2820000
04021f0f
d2820000
04021d0e
d2060100
02010100
7e185b00
1000190e
101c190f
1018190d
7e1a0280
f800023f
0d000e0c
c2008935
bf8c000f
10000c01
c2008934
bf8c007f
d2820000
04000305
c2008936
bf8c007f
d2820000
04000308
c2008937
bf8c007f
7e0a0201
d2820000
04020a02
c200890d
bf8c007f
10020801
f800024f
01000907
c20089e4
bf8c000f
d2820000
041e1601
10021400
08021701
c20009e5
bf8c007f
10041600
08041302
f80008cf
0b010200
bf810000
FRAG
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL IN[3], GENERIC[22], PERSPECTIVE
DCL IN[4], GENERIC[23], PERSPECTIVE
DCL IN[5], GENERIC[24], PERSPECTIVE
DCL IN[6], GENERIC[25], PERSPECTIVE
DCL IN[7], GENERIC[26], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..30]
DCL TEMP[0..22], LOCAL
DCL TEMP[23], ARRAY(1), LOCAL
IMM[0] FLT32 {    2.0000,    -1.0000,     0.0000,     1.0000}
IMM[1] FLT32 {  149.0000,    -0.5000,     0.5000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[1], 2D
  2: MOV TEMP[1].xy, IN[0].xyyy
  3: TEX TEMP[2].xy, TEMP[1], SAMP[2], 2D
  4: MOV TEMP[3].xy, IN[0].xyyy
  5: TEX TEMP[4], TEMP[3], SAMP[0], 2D
  6: MOV TEMP[5].xy, IN[0].xyyy
  7: TEX TEMP[5].xyz, TEMP[5], SAMP[3], 2D
  8: ADD TEMP[6].xyz, -IN[6].xyzz, CONST[23].xyzz
  9: DP3 TEMP[7].x, IN[2].xyzz, IN[2].xyzz
 10: DP3 TEMP[8].x, TEMP[6].xyzz, TEMP[6].xyzz
 11: RSQ TEMP[8].x, TEMP[8].xxxx
 12: MUL TEMP[8].xyz, TEMP[6].xyzz, TEMP[8].xxxx
 13: RSQ TEMP[9].x, TEMP[7].xxxx
 14: MUL TEMP[6].xyz, TEMP[9].xxxx, IN[2].xyzz
 15: MAD TEMP[7].xyz, IMM[0].xxxx, TEMP[0].xyzz, IMM[0].yyyy
 16: ADD TEMP[1].xyz, -TEMP[7].xyzz, IMM[0].zzww
 17: MAD TEMP[1].xyz, CONST[27].xxxx, TEMP[1].xyzz, TEMP[7].xyzz
 18: MUL TEMP[7].xyz, TEMP[1].yyyy, IN[4].xyzz
 19: MAD TEMP[7].xyz, IN[3].xyzz, TEMP[1].xxxx, TEMP[7].xyzz
 20: MAD TEMP[1].xyz, IN[5].xyzz, TEMP[1].zzzz, TEMP[7].xyzz
 21: DP3 TEMP[10].x, TEMP[1].xyzz, TEMP[1].xyzz
 22: RSQ TEMP[10].x, TEMP[10].xxxx
 23: MUL TEMP[10].xyz, TEMP[1].xyzz, TEMP[10].xxxx
 24: DP3 TEMP[11].x, TEMP[10].xyzz, TEMP[6].xyzz
 25: MUL TEMP[1].xyz, TEMP[10].xyzz, TEMP[11].xxxx
 26: ADD TEMP[1].xyz, TEMP[1].xyzz, TEMP[1].xyzz
 27: MAD TEMP[6].xyz, IN[2].xyzz, -TEMP[9].xxxx, TEMP[1].xyzz
 28: MAD TEMP[12].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[0].wwww
 29: DP3 TEMP[1].x, TEMP[6].xyzz, TEMP[8].xyzz
 30: MOV_SAT TEMP[1].x, TEMP[1].xxxx
 31: SGE TEMP[13].x, CONST[11].wwww, IMM[0].zzzz
 32: F2I TEMP[13].x, -TEMP[13]
 33: UIF TEMP[13].xxxx :0
 34:   MOV TEMP[13].x, CONST[11].wwww
 35: ELSE :0
 36:   MOV TEMP[13].x, TEMP[12].xxxx
 37: ENDIF
 38: DP3 TEMP[12].x, TEMP[10].xyzz, TEMP[8].xyzz
 39: POW TEMP[14].x, TEMP[1].xxxx, TEMP[13].xxxx
 40: MOV_SAT TEMP[15].x, TEMP[12].xxxx
 41: MUL TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx
 42: MUL TEMP[7].xyz, IN[1].yyyy, CONST[22].xyzz
 43: MUL TEMP[1].xyz, TEMP[14].xxxx, TEMP[7].xyzz
 44: ADD TEMP[14].xyz, -IN[6].xyzz, CONST[21].xyzz
 45: DP3 TEMP[15].x, TEMP[14].xyzz, TEMP[14].xyzz
 46: RSQ TEMP[15].x, TEMP[15].xxxx
 47: MUL TEMP[8].xyz, TEMP[14].xyzz, TEMP[15].xxxx
 48: DP3 TEMP[15].x, TEMP[6].xyzz, TEMP[8].xyzz
 49: MOV_SAT TEMP[15].x, TEMP[15].xxxx
 50: DP3 TEMP[16].x, TEMP[10].xyzz, TEMP[8].xyzz
 51: MUL TEMP[14].xyz, IN[1].xxxx, CONST[20].xyzz
 52: ADD TEMP[17].xyz, -IN[6].xyzz, CONST[25].xyzz
 53: DP3 TEMP[18].x, TEMP[17].xyzz, TEMP[17].xyzz
 54: RSQ TEMP[18].x, TEMP[18].xxxx
 55: MUL TEMP[8].xyz, TEMP[17].xyzz, TEMP[18].xxxx
 56: DP3 TEMP[3].x, TEMP[6].xyzz, TEMP[8].xyzz
 57: MOV_SAT TEMP[3].x, TEMP[3].xxxx
 58: ADD TEMP[11].x, -TEMP[11].xxxx, IMM[0].wwww
 59: MOV_SAT TEMP[11].x, TEMP[11].xxxx
 60: DP3 TEMP[18].x, TEMP[10].xyzz, TEMP[8].xyzz
 61: MOV TEMP[8].x, CONST[23].wwww
 62: MOV_SAT TEMP[19].x, TEMP[16].xxxx
 63: MOV TEMP[8].y, CONST[24].wwww
 64: POW TEMP[20].x, TEMP[15].xxxx, TEMP[13].xxxx
 65: MUL TEMP[19].x, TEMP[20].xxxx, TEMP[19].xxxx
 66: MOV TEMP[8].z, CONST[25].wwww
 67: ADD TEMP[17].xyz, TEMP[8].xyzz, -IN[6].xyzz
 68: DP3 TEMP[20].x, TEMP[17].xyzz, TEMP[17].xyzz
 69: RSQ TEMP[20].x, TEMP[20].xxxx
 70: MUL TEMP[8].xyz, TEMP[17].xyzz, TEMP[20].xxxx
 71: POW TEMP[20].x, TEMP[3].xxxx, TEMP[13].xxxx
 72: MOV_SAT TEMP[21].x, TEMP[18].xxxx
 73: MUL TEMP[20].x, TEMP[20].xxxx, TEMP[21].xxxx
 74: DP3 TEMP[6].x, TEMP[6].xyzz, TEMP[8].xyzz
 75: MOV_SAT TEMP[6].x, TEMP[6].xxxx
 76: DP3 TEMP[21].x, TEMP[10].xyzz, TEMP[8].xyzz
 77: POW TEMP[13].x, TEMP[6].xxxx, TEMP[13].xxxx
 78: MAD TEMP[1].xyz, TEMP[19].xxxx, TEMP[14].xyzz, TEMP[1].xyzz
 79: MOV_SAT TEMP[19].x, TEMP[21].xxxx
 80: MUL TEMP[6].xyz, IN[1].zzzz, CONST[24].xyzz
 81: MUL TEMP[13].x, TEMP[13].xxxx, TEMP[19].xxxx
 82: MAD TEMP[1].xyz, TEMP[20].xxxx, TEMP[6].xyzz, TEMP[1].xyzz
 83: MAD TEMP[11].x, TEMP[11].xxxx, TEMP[11].xxxx, IMM[1].yyyy
 84: MOV TEMP[8].x, CONST[20].wwww
 85: SGE TEMP[19].x, TEMP[11].xxxx, IMM[0].zzzz
 86: F2I TEMP[19].x, -TEMP[19]
 87: UIF TEMP[19].xxxx :0
 88:   MOV TEMP[19].x, CONST[19].zzzz
 89: ELSE :0
 90:   MOV TEMP[19].x, CONST[19].xxxx
 91: ENDIF
 92: MOV TEMP[8].y, CONST[21].wwww
 93: MAD TEMP[11].x, TEMP[19].xxxx, TEMP[11].xxxx, CONST[19].yyyy
 94: MOV TEMP[8].z, CONST[22].wwww
 95: ADD TEMP[19].x, TEMP[4].wwww, -TEMP[0].wwww
 96: MAD TEMP[19].x, CONST[27].xxxx, TEMP[19].xxxx, TEMP[0].wwww
 97: MUL TEMP[8].xyz, TEMP[8].xyzz, IN[6].wwww
 98: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[19].xxxx
 99: MAD TEMP[1].xyz, TEMP[13].xxxx, TEMP[8].xyzz, TEMP[1].xyzz
100: MUL TEMP[11].x, TEMP[11].xxxx, CONST[19].wwww
101: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[11].xxxx
102: MUL TEMP[15].xyz, TEMP[10].xyzz, TEMP[10].xyzz
103: SGE TEMP[11].x, TEMP[10].xxxx, IMM[0].zzzz
104: F2I TEMP[11].x, -TEMP[11]
105: UIF TEMP[11].xxxx :0
106:   MOV TEMP[11].x, IMM[0].zzzz
107: ELSE :0
108:   MOV TEMP[11].x, TEMP[15].xxxx
109: ENDIF
110: SGE TEMP[13].x, TEMP[10].yyyy, IMM[0].zzzz
111: F2I TEMP[13].x, -TEMP[13]
112: UIF TEMP[13].xxxx :0
113:   MOV TEMP[13].x, IMM[0].zzzz
114: ELSE :0
115:   MOV TEMP[13].x, TEMP[15].yyyy
116: ENDIF
117: SGE TEMP[19].x, TEMP[10].zzzz, IMM[0].zzzz
118: F2I TEMP[19].x, -TEMP[19]
119: UIF TEMP[19].xxxx :0
120:   MOV TEMP[19].x, IMM[0].zzzz
121: ELSE :0
122:   MOV TEMP[19].x, TEMP[15].zzzz
123: ENDIF
124: SGE TEMP[20].x, TEMP[10].xxxx, IMM[0].zzzz
125: F2I TEMP[20].x, -TEMP[20]
126: UIF TEMP[20].xxxx :0
127:   MOV TEMP[20].x, TEMP[15].xxxx
128: ELSE :0
129:   MOV TEMP[20].x, IMM[0].zzzz
130: ENDIF
131: SGE TEMP[22].x, TEMP[10].yyyy, IMM[0].zzzz
132: F2I TEMP[22].x, -TEMP[22]
133: UIF TEMP[22].xxxx :0
134:   MOV TEMP[22].x, TEMP[15].yyyy
135: ELSE :0
136:   MOV TEMP[22].x, IMM[0].zzzz
137: ENDIF
138: SGE TEMP[10].x, TEMP[10].zzzz, IMM[0].zzzz
139: F2I TEMP[10].x, -TEMP[10]
140: UIF TEMP[10].xxxx :0
141:   MOV TEMP[10].x, TEMP[15].zzzz
142: ELSE :0
143:   MOV TEMP[10].x, IMM[0].zzzz
144: ENDIF
145: MUL TEMP[15].xyz, TEMP[11].xxxx, CONST[5].xyzz
146: MAD TEMP[11].x, TEMP[12].xxxx, IMM[1].zzzz, IMM[1].zzzz
147: MOV_SAT TEMP[11].x, TEMP[11].xxxx
148: MAD TEMP[15].xyz, TEMP[20].xxxx, CONST[4].xyzz, TEMP[15].xyzz
149: MAD TEMP[12].x, TEMP[16].xxxx, IMM[1].zzzz, IMM[1].zzzz
150: MOV_SAT TEMP[12].x, TEMP[12].xxxx
151: MAD TEMP[15].xyz, TEMP[22].xxxx, CONST[6].xyzz, TEMP[15].xyzz
152: MAD TEMP[16].x, TEMP[18].xxxx, IMM[1].zzzz, IMM[1].zzzz
153: MOV_SAT TEMP[16].x, TEMP[16].xxxx
154: MAD TEMP[15].xyz, TEMP[13].xxxx, CONST[7].xyzz, TEMP[15].xyzz
155: MAD TEMP[13].x, TEMP[21].xxxx, IMM[1].zzzz, IMM[1].zzzz
156: MOV_SAT TEMP[13].x, TEMP[13].xxxx
157: MAD TEMP[9].xyz, TEMP[10].xxxx, CONST[8].xyzz, TEMP[15].xyzz
158: MAD TEMP[17].xyz, TEMP[19].xxxx, CONST[9].xyzz, TEMP[9].xyzz
159: MUL TEMP[9].x, TEMP[12].xxxx, TEMP[12].xxxx
160: MAD TEMP[14].xyz, TEMP[14].xyzz, TEMP[9].xxxx, TEMP[17].xyzz
161: MUL TEMP[9].x, TEMP[11].xxxx, TEMP[11].xxxx
162: MAD TEMP[7].xyz, TEMP[7].xyzz, TEMP[9].xxxx, TEMP[14].xyzz
163: MUL TEMP[9].x, TEMP[16].xxxx, TEMP[16].xxxx
164: MAD TEMP[6].xyz, TEMP[6].xyzz, TEMP[9].xxxx, TEMP[7].xyzz
165: MUL TEMP[9].x, TEMP[13].xxxx, TEMP[13].xxxx
166: MAD TEMP[6].xyz, TEMP[8].xyzz, TEMP[9].xxxx, TEMP[6].xyzz
167: MUL TEMP[8].xyz, TEMP[4].xyzz, CONST[1].xyzz
168: MUL TEMP[7].xyz, TEMP[6].xyzz, TEMP[8].xyzz
169: MAD TEMP[6].xyz, CONST[0].xyzz, TEMP[8].xyzz, -TEMP[7].xyzz
170: ADD TEMP[5].xyz, TEMP[5].xyzz, -TEMP[4].wwww
171: MAD TEMP[8].xyz, CONST[10].wwww, TEMP[5].xyzz, TEMP[4].wwww
172: ADD TEMP[4].xyz, TEMP[4].xyzz, IMM[0].yyyy
173: MAD TEMP[8].xyz, TEMP[8].xyzz, TEMP[6].xyzz, TEMP[7].xyzz
174: MAX TEMP[5].xyz, TEMP[8].xyzz, IMM[0].zzzz
175: MAD TEMP[3].xyz, TEMP[2].yyyy, TEMP[4].xyzz, IMM[0].wwww
176: SGE TEMP[2].x, CONST[26].xxxx, IMM[0].zzzz
177: F2I TEMP[2].x, -TEMP[2]
178: UIF TEMP[2].xxxx :0
179:   MOV TEMP[2].x, CONST[26].xxxx
180: ELSE :0
181:   MOV TEMP[2].x, TEMP[3].xxxx
182: ENDIF
183: MOV TEMP[3].x, TEMP[2].xxxx
184: SGE TEMP[2].x, CONST[26].xxxx, IMM[0].zzzz
185: F2I TEMP[2].x, -TEMP[2]
186: UIF TEMP[2].xxxx :0
187:   MOV TEMP[2].x, CONST[26].yyyy
188: ELSE :0
189:   MOV TEMP[2].x, TEMP[3].yyyy
190: ENDIF
191: MOV TEMP[3].y, TEMP[2].xxxx
192: SGE TEMP[2].x, CONST[26].xxxx, IMM[0].zzzz
193: F2I TEMP[2].x, -TEMP[2]
194: UIF TEMP[2].xxxx :0
195:   MOV TEMP[2].x, CONST[26].zzzz
196: ELSE :0
197:   MOV TEMP[2].x, TEMP[3].zzzz
198: ENDIF
199: MOV TEMP[3].z, TEMP[2].xxxx
200: MAD TEMP[2].x, IN[7].zzzz, CONST[12].wwww, -CONST[12].xxxx
201: MAD TEMP[3].xyz, TEMP[1].xyzz, TEMP[3].xyzz, TEMP[5].xyzz
202: MIN TEMP[1].x, TEMP[2].xxxx, CONST[12].zzzz
203: MOV_SAT TEMP[1].x, TEMP[1].xxxx
204: MAD TEMP[0].xyz, TEMP[3].xyzz, -CONST[30].xxxx, CONST[29].xyzz
205: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
206: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx
207: MAD TEMP[3].xyz, TEMP[3].xyzz, CONST[30].xxxx, TEMP[0].xyzz
208: MUL TEMP[0].x, IN[7].zzzz, CONST[29].wwww
209: MOV TEMP[3].w, TEMP[0].xxxx
210: MOV TEMP[23], TEMP[3]
211: MOV OUT[0], TEMP[23]
212: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 100)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 104)
  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 112)
  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 116)
  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 120)
  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
  %41 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
  %42 = call float @llvm.SI.load.const(<16 x i8> %21, i32 136)
  %43 = call float @llvm.SI.load.const(<16 x i8> %21, i32 144)
  %44 = call float @llvm.SI.load.const(<16 x i8> %21, i32 148)
  %45 = call float @llvm.SI.load.const(<16 x i8> %21, i32 152)
  %46 = call float @llvm.SI.load.const(<16 x i8> %21, i32 172)
  %47 = call float @llvm.SI.load.const(<16 x i8> %21, i32 188)
  %48 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
  %49 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
  %50 = call float @llvm.SI.load.const(<16 x i8> %21, i32 204)
  %51 = call float @llvm.SI.load.const(<16 x i8> %21, i32 304)
  %52 = call float @llvm.SI.load.const(<16 x i8> %21, i32 308)
  %53 = call float @llvm.SI.load.const(<16 x i8> %21, i32 312)
  %54 = call float @llvm.SI.load.const(<16 x i8> %21, i32 316)
  %55 = call float @llvm.SI.load.const(<16 x i8> %21, i32 320)
  %56 = call float @llvm.SI.load.const(<16 x i8> %21, i32 324)
  %57 = call float @llvm.SI.load.const(<16 x i8> %21, i32 328)
  %58 = call float @llvm.SI.load.const(<16 x i8> %21, i32 332)
  %59 = call float @llvm.SI.load.const(<16 x i8> %21, i32 336)
  %60 = call float @llvm.SI.load.const(<16 x i8> %21, i32 340)
  %61 = call float @llvm.SI.load.const(<16 x i8> %21, i32 344)
  %62 = call float @llvm.SI.load.const(<16 x i8> %21, i32 348)
  %63 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %64 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %65 = call float @llvm.SI.load.const(<16 x i8> %21, i32 360)
  %66 = call float @llvm.SI.load.const(<16 x i8> %21, i32 364)
  %67 = call float @llvm.SI.load.const(<16 x i8> %21, i32 368)
  %68 = call float @llvm.SI.load.const(<16 x i8> %21, i32 372)
  %69 = call float @llvm.SI.load.const(<16 x i8> %21, i32 376)
  %70 = call float @llvm.SI.load.const(<16 x i8> %21, i32 380)
  %71 = call float @llvm.SI.load.const(<16 x i8> %21, i32 384)
  %72 = call float @llvm.SI.load.const(<16 x i8> %21, i32 388)
  %73 = call float @llvm.SI.load.const(<16 x i8> %21, i32 392)
  %74 = call float @llvm.SI.load.const(<16 x i8> %21, i32 396)
  %75 = call float @llvm.SI.load.const(<16 x i8> %21, i32 400)
  %76 = call float @llvm.SI.load.const(<16 x i8> %21, i32 404)
  %77 = call float @llvm.SI.load.const(<16 x i8> %21, i32 408)
  %78 = call float @llvm.SI.load.const(<16 x i8> %21, i32 412)
  %79 = call float @llvm.SI.load.const(<16 x i8> %21, i32 416)
  %80 = call float @llvm.SI.load.const(<16 x i8> %21, i32 420)
  %81 = call float @llvm.SI.load.const(<16 x i8> %21, i32 424)
  %82 = call float @llvm.SI.load.const(<16 x i8> %21, i32 432)
  %83 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %84 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %85 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %86 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %87 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %88 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %89 = load <32 x i8> addrspace(2)* %88, !tbaa !0
  %90 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %91 = load <16 x i8> addrspace(2)* %90, !tbaa !0
  %92 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %93 = load <32 x i8> addrspace(2)* %92, !tbaa !0
  %94 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %95 = load <16 x i8> addrspace(2)* %94, !tbaa !0
  %96 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %97 = load <32 x i8> addrspace(2)* %96, !tbaa !0
  %98 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %99 = load <16 x i8> addrspace(2)* %98, !tbaa !0
  %100 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %101 = load <32 x i8> addrspace(2)* %100, !tbaa !0
  %102 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %103 = load <16 x i8> addrspace(2)* %102, !tbaa !0
  %104 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %105 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %106 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %107 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %108 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %109 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %110 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %111 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %112 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
  %113 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
  %114 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %115 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
  %116 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
  %117 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
  %118 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
  %119 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
  %120 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
  %121 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %5)
  %122 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %5)
  %123 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %3, <2 x i32> %5)
  %124 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %3, <2 x i32> %5)
  %125 = call float @llvm.SI.fs.interp(i32 2, i32 7, i32 %3, <2 x i32> %5)
  %126 = bitcast float %104 to i32
  %127 = bitcast float %105 to i32
  %128 = insertelement <2 x i32> undef, i32 %126, i32 0
  %129 = insertelement <2 x i32> %128, i32 %127, i32 1
  %130 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %129, <32 x i8> %93, <16 x i8> %95, i32 2)
  %131 = extractelement <4 x float> %130, i32 0
  %132 = extractelement <4 x float> %130, i32 1
  %133 = extractelement <4 x float> %130, i32 2
  %134 = extractelement <4 x float> %130, i32 3
  %135 = bitcast float %104 to i32
  %136 = bitcast float %105 to i32
  %137 = insertelement <2 x i32> undef, i32 %135, i32 0
  %138 = insertelement <2 x i32> %137, i32 %136, i32 1
  %139 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %138, <32 x i8> %97, <16 x i8> %99, i32 2)
  %140 = extractelement <4 x float> %139, i32 0
  %141 = extractelement <4 x float> %139, i32 1
  %142 = bitcast float %104 to i32
  %143 = bitcast float %105 to i32
  %144 = insertelement <2 x i32> undef, i32 %142, i32 0
  %145 = insertelement <2 x i32> %144, i32 %143, i32 1
  %146 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %145, <32 x i8> %89, <16 x i8> %91, i32 2)
  %147 = extractelement <4 x float> %146, i32 0
  %148 = extractelement <4 x float> %146, i32 1
  %149 = extractelement <4 x float> %146, i32 2
  %150 = extractelement <4 x float> %146, i32 3
  %151 = bitcast float %104 to i32
  %152 = bitcast float %105 to i32
  %153 = insertelement <2 x i32> undef, i32 %151, i32 0
  %154 = insertelement <2 x i32> %153, i32 %152, i32 1
  %155 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %154, <32 x i8> %101, <16 x i8> %103, i32 2)
  %156 = extractelement <4 x float> %155, i32 0
  %157 = extractelement <4 x float> %155, i32 1
  %158 = extractelement <4 x float> %155, i32 2
  %159 = fsub float -0.000000e+00, %121
  %160 = fadd float %159, %67
  %161 = fsub float -0.000000e+00, %122
  %162 = fadd float %161, %68
  %163 = fsub float -0.000000e+00, %123
  %164 = fadd float %163, %69
  %165 = fmul float %109, %109
  %166 = fmul float %110, %110
  %167 = fadd float %166, %165
  %168 = fmul float %111, %111
  %169 = fadd float %167, %168
  %170 = fmul float %160, %160
  %171 = fmul float %162, %162
  %172 = fadd float %171, %170
  %173 = fmul float %164, %164
  %174 = fadd float %172, %173
  %175 = call float @fabs(float %174)
  %176 = call float @llvm.AMDGPU.rsq(float %175)
  %177 = fmul float %160, %176
  %178 = fmul float %162, %176
  %179 = fmul float %164, %176
  %180 = call float @fabs(float %169)
  %181 = call float @llvm.AMDGPU.rsq(float %180)
  %182 = fmul float %181, %109
  %183 = fmul float %181, %110
  %184 = fmul float %181, %111
  %185 = fmul float 2.000000e+00, %131
  %186 = fadd float %185, -1.000000e+00
  %187 = fmul float 2.000000e+00, %132
  %188 = fadd float %187, -1.000000e+00
  %189 = fmul float 2.000000e+00, %133
  %190 = fadd float %189, -1.000000e+00
  %191 = fsub float -0.000000e+00, %186
  %192 = fadd float %191, 0.000000e+00
  %193 = fsub float -0.000000e+00, %188
  %194 = fadd float %193, 0.000000e+00
  %195 = fsub float -0.000000e+00, %190
  %196 = fadd float %195, 1.000000e+00
  %197 = fmul float %82, %192
  %198 = fadd float %197, %186
  %199 = fmul float %82, %194
  %200 = fadd float %199, %188
  %201 = fmul float %82, %196
  %202 = fadd float %201, %190
  %203 = fmul float %200, %115
  %204 = fmul float %200, %116
  %205 = fmul float %200, %117
  %206 = fmul float %112, %198
  %207 = fadd float %206, %203
  %208 = fmul float %113, %198
  %209 = fadd float %208, %204
  %210 = fmul float %114, %198
  %211 = fadd float %210, %205
  %212 = fmul float %118, %202
  %213 = fadd float %212, %207
  %214 = fmul float %119, %202
  %215 = fadd float %214, %209
  %216 = fmul float %120, %202
  %217 = fadd float %216, %211
  %218 = fmul float %213, %213
  %219 = fmul float %215, %215
  %220 = fadd float %219, %218
  %221 = fmul float %217, %217
  %222 = fadd float %220, %221
  %223 = call float @fabs(float %222)
  %224 = call float @llvm.AMDGPU.rsq(float %223)
  %225 = fmul float %213, %224
  %226 = fmul float %215, %224
  %227 = fmul float %217, %224
  %228 = fmul float %225, %182
  %229 = fmul float %226, %183
  %230 = fadd float %229, %228
  %231 = fmul float %227, %184
  %232 = fadd float %230, %231
  %233 = fmul float %225, %232
  %234 = fmul float %226, %232
  %235 = fmul float %227, %232
  %236 = fadd float %233, %233
  %237 = fadd float %234, %234
  %238 = fadd float %235, %235
  %239 = fsub float -0.000000e+00, %181
  %240 = fmul float %109, %239
  %241 = fadd float %240, %236
  %242 = fsub float -0.000000e+00, %181
  %243 = fmul float %110, %242
  %244 = fadd float %243, %237
  %245 = fsub float -0.000000e+00, %181
  %246 = fmul float %111, %245
  %247 = fadd float %246, %238
  %248 = fmul float %140, 1.490000e+02
  %249 = fadd float %248, 1.000000e+00
  %250 = fmul float %241, %177
  %251 = fmul float %244, %178
  %252 = fadd float %251, %250
  %253 = fmul float %247, %179
  %254 = fadd float %252, %253
  %255 = call float @llvm.AMDIL.clamp.(float %254, float 0.000000e+00, float 1.000000e+00)
  %256 = fcmp uge float %47, 0.000000e+00
  %257 = select i1 %256, float 1.000000e+00, float 0.000000e+00
  %258 = fsub float -0.000000e+00, %257
  %259 = fptosi float %258 to i32
  %260 = bitcast i32 %259 to float
  %261 = bitcast float %260 to i32
  %262 = icmp ne i32 %261, 0
  %. = select i1 %262, float %47, float %249
  %263 = fmul float %225, %177
  %264 = fmul float %226, %178
  %265 = fadd float %264, %263
  %266 = fmul float %227, %179
  %267 = fadd float %265, %266
  %268 = call float @llvm.pow.f32(float %255, float %.)
  %269 = call float @llvm.AMDIL.clamp.(float %267, float 0.000000e+00, float 1.000000e+00)
  %270 = fmul float %268, %269
  %271 = fmul float %107, %63
  %272 = fmul float %107, %64
  %273 = fmul float %107, %65
  %274 = fmul float %270, %271
  %275 = fmul float %270, %272
  %276 = fmul float %270, %273
  %277 = fsub float -0.000000e+00, %121
  %278 = fadd float %277, %59
  %279 = fsub float -0.000000e+00, %122
  %280 = fadd float %279, %60
  %281 = fsub float -0.000000e+00, %123
  %282 = fadd float %281, %61
  %283 = fmul float %278, %278
  %284 = fmul float %280, %280
  %285 = fadd float %284, %283
  %286 = fmul float %282, %282
  %287 = fadd float %285, %286
  %288 = call float @fabs(float %287)
  %289 = call float @llvm.AMDGPU.rsq(float %288)
  %290 = fmul float %278, %289
  %291 = fmul float %280, %289
  %292 = fmul float %282, %289
  %293 = fmul float %241, %290
  %294 = fmul float %244, %291
  %295 = fadd float %294, %293
  %296 = fmul float %247, %292
  %297 = fadd float %295, %296
  %298 = call float @llvm.AMDIL.clamp.(float %297, float 0.000000e+00, float 1.000000e+00)
  %299 = fmul float %225, %290
  %300 = fmul float %226, %291
  %301 = fadd float %300, %299
  %302 = fmul float %227, %292
  %303 = fadd float %301, %302
  %304 = fmul float %106, %55
  %305 = fmul float %106, %56
  %306 = fmul float %106, %57
  %307 = fsub float -0.000000e+00, %121
  %308 = fadd float %307, %75
  %309 = fsub float -0.000000e+00, %122
  %310 = fadd float %309, %76
  %311 = fsub float -0.000000e+00, %123
  %312 = fadd float %311, %77
  %313 = fmul float %308, %308
  %314 = fmul float %310, %310
  %315 = fadd float %314, %313
  %316 = fmul float %312, %312
  %317 = fadd float %315, %316
  %318 = call float @fabs(float %317)
  %319 = call float @llvm.AMDGPU.rsq(float %318)
  %320 = fmul float %308, %319
  %321 = fmul float %310, %319
  %322 = fmul float %312, %319
  %323 = fmul float %241, %320
  %324 = fmul float %244, %321
  %325 = fadd float %324, %323
  %326 = fmul float %247, %322
  %327 = fadd float %325, %326
  %328 = call float @llvm.AMDIL.clamp.(float %327, float 0.000000e+00, float 1.000000e+00)
  %329 = fsub float -0.000000e+00, %232
  %330 = fadd float %329, 1.000000e+00
  %331 = call float @llvm.AMDIL.clamp.(float %330, float 0.000000e+00, float 1.000000e+00)
  %332 = fmul float %225, %320
  %333 = fmul float %226, %321
  %334 = fadd float %333, %332
  %335 = fmul float %227, %322
  %336 = fadd float %334, %335
  %337 = call float @llvm.AMDIL.clamp.(float %303, float 0.000000e+00, float 1.000000e+00)
  %338 = call float @llvm.pow.f32(float %298, float %.)
  %339 = fmul float %338, %337
  %340 = fsub float -0.000000e+00, %121
  %341 = fadd float %70, %340
  %342 = fsub float -0.000000e+00, %122
  %343 = fadd float %74, %342
  %344 = fsub float -0.000000e+00, %123
  %345 = fadd float %78, %344
  %346 = fmul float %341, %341
  %347 = fmul float %343, %343
  %348 = fadd float %347, %346
  %349 = fmul float %345, %345
  %350 = fadd float %348, %349
  %351 = call float @fabs(float %350)
  %352 = call float @llvm.AMDGPU.rsq(float %351)
  %353 = fmul float %341, %352
  %354 = fmul float %343, %352
  %355 = fmul float %345, %352
  %356 = call float @llvm.pow.f32(float %328, float %.)
  %357 = call float @llvm.AMDIL.clamp.(float %336, float 0.000000e+00, float 1.000000e+00)
  %358 = fmul float %356, %357
  %359 = fmul float %241, %353
  %360 = fmul float %244, %354
  %361 = fadd float %360, %359
  %362 = fmul float %247, %355
  %363 = fadd float %361, %362
  %364 = call float @llvm.AMDIL.clamp.(float %363, float 0.000000e+00, float 1.000000e+00)
  %365 = fmul float %225, %353
  %366 = fmul float %226, %354
  %367 = fadd float %366, %365
  %368 = fmul float %227, %355
  %369 = fadd float %367, %368
  %370 = call float @llvm.pow.f32(float %364, float %.)
  %371 = fmul float %339, %304
  %372 = fadd float %371, %274
  %373 = fmul float %339, %305
  %374 = fadd float %373, %275
  %375 = fmul float %339, %306
  %376 = fadd float %375, %276
  %377 = call float @llvm.AMDIL.clamp.(float %369, float 0.000000e+00, float 1.000000e+00)
  %378 = fmul float %108, %71
  %379 = fmul float %108, %72
  %380 = fmul float %108, %73
  %381 = fmul float %370, %377
  %382 = fmul float %358, %378
  %383 = fadd float %382, %372
  %384 = fmul float %358, %379
  %385 = fadd float %384, %374
  %386 = fmul float %358, %380
  %387 = fadd float %386, %376
  %388 = fmul float %331, %331
  %389 = fadd float %388, -5.000000e-01
  %390 = fcmp uge float %389, 0.000000e+00
  %391 = select i1 %390, float 1.000000e+00, float 0.000000e+00
  %392 = fsub float -0.000000e+00, %391
  %393 = fptosi float %392 to i32
  %394 = bitcast i32 %393 to float
  %395 = bitcast float %394 to i32
  %396 = icmp ne i32 %395, 0
  %temp76.0 = select i1 %396, float %53, float %51
  %397 = fmul float %temp76.0, %389
  %398 = fadd float %397, %52
  %399 = fsub float -0.000000e+00, %134
  %400 = fadd float %150, %399
  %401 = fmul float %82, %400
  %402 = fadd float %401, %134
  %403 = fmul float %58, %124
  %404 = fmul float %62, %124
  %405 = fmul float %66, %124
  %406 = fmul float %398, %402
  %407 = fmul float %381, %403
  %408 = fadd float %407, %383
  %409 = fmul float %381, %404
  %410 = fadd float %409, %385
  %411 = fmul float %381, %405
  %412 = fadd float %411, %387
  %413 = fmul float %406, %54
  %414 = fmul float %408, %413
  %415 = fmul float %410, %413
  %416 = fmul float %412, %413
  %417 = fmul float %225, %225
  %418 = fmul float %226, %226
  %419 = fmul float %227, %227
  %420 = fcmp uge float %225, 0.000000e+00
  %421 = select i1 %420, float 1.000000e+00, float 0.000000e+00
  %422 = fsub float -0.000000e+00, %421
  %423 = fptosi float %422 to i32
  %424 = bitcast i32 %423 to float
  %425 = bitcast float %424 to i32
  %426 = icmp ne i32 %425, 0
  %.126 = select i1 %426, float 0.000000e+00, float %417
  %427 = fcmp uge float %226, 0.000000e+00
  %428 = select i1 %427, float 1.000000e+00, float 0.000000e+00
  %429 = fsub float -0.000000e+00, %428
  %430 = fptosi float %429 to i32
  %431 = bitcast i32 %430 to float
  %432 = bitcast float %431 to i32
  %433 = icmp ne i32 %432, 0
  %temp52.1 = select i1 %433, float 0.000000e+00, float %418
  %434 = fcmp uge float %227, 0.000000e+00
  %435 = select i1 %434, float 1.000000e+00, float 0.000000e+00
  %436 = fsub float -0.000000e+00, %435
  %437 = fptosi float %436 to i32
  %438 = bitcast i32 %437 to float
  %439 = bitcast float %438 to i32
  %440 = icmp ne i32 %439, 0
  %.127 = select i1 %440, float 0.000000e+00, float %419
  %441 = fcmp uge float %225, 0.000000e+00
  %442 = select i1 %441, float 1.000000e+00, float 0.000000e+00
  %443 = fsub float -0.000000e+00, %442
  %444 = fptosi float %443 to i32
  %445 = bitcast i32 %444 to float
  %446 = bitcast float %445 to i32
  %447 = icmp ne i32 %446, 0
  %temp80.0 = select i1 %447, float %417, float 0.000000e+00
  %448 = fcmp uge float %226, 0.000000e+00
  %449 = select i1 %448, float 1.000000e+00, float 0.000000e+00
  %450 = fsub float -0.000000e+00, %449
  %451 = fptosi float %450 to i32
  %452 = bitcast i32 %451 to float
  %453 = bitcast float %452 to i32
  %454 = icmp ne i32 %453, 0
  %.128 = select i1 %454, float %418, float 0.000000e+00
  %455 = fcmp uge float %227, 0.000000e+00
  %456 = select i1 %455, float 1.000000e+00, float 0.000000e+00
  %457 = fsub float -0.000000e+00, %456
  %458 = fptosi float %457 to i32
  %459 = bitcast i32 %458 to float
  %460 = bitcast float %459 to i32
  %461 = icmp ne i32 %460, 0
  %temp40.0 = select i1 %461, float %419, float 0.000000e+00
  %462 = fmul float %.126, %31
  %463 = fmul float %.126, %32
  %464 = fmul float %.126, %33
  %465 = fmul float %267, 5.000000e-01
  %466 = fadd float %465, 5.000000e-01
  %467 = call float @llvm.AMDIL.clamp.(float %466, float 0.000000e+00, float 1.000000e+00)
  %468 = fmul float %temp80.0, %28
  %469 = fadd float %468, %462
  %470 = fmul float %temp80.0, %29
  %471 = fadd float %470, %463
  %472 = fmul float %temp80.0, %30
  %473 = fadd float %472, %464
  %474 = fmul float %303, 5.000000e-01
  %475 = fadd float %474, 5.000000e-01
  %476 = call float @llvm.AMDIL.clamp.(float %475, float 0.000000e+00, float 1.000000e+00)
  %477 = fmul float %.128, %34
  %478 = fadd float %477, %469
  %479 = fmul float %.128, %35
  %480 = fadd float %479, %471
  %481 = fmul float %.128, %36
  %482 = fadd float %481, %473
  %483 = fmul float %336, 5.000000e-01
  %484 = fadd float %483, 5.000000e-01
  %485 = call float @llvm.AMDIL.clamp.(float %484, float 0.000000e+00, float 1.000000e+00)
  %486 = fmul float %temp52.1, %37
  %487 = fadd float %486, %478
  %488 = fmul float %temp52.1, %38
  %489 = fadd float %488, %480
  %490 = fmul float %temp52.1, %39
  %491 = fadd float %490, %482
  %492 = fmul float %369, 5.000000e-01
  %493 = fadd float %492, 5.000000e-01
  %494 = call float @llvm.AMDIL.clamp.(float %493, float 0.000000e+00, float 1.000000e+00)
  %495 = fmul float %temp40.0, %40
  %496 = fadd float %495, %487
  %497 = fmul float %temp40.0, %41
  %498 = fadd float %497, %489
  %499 = fmul float %temp40.0, %42
  %500 = fadd float %499, %491
  %501 = fmul float %.127, %43
  %502 = fadd float %501, %496
  %503 = fmul float %.127, %44
  %504 = fadd float %503, %498
  %505 = fmul float %.127, %45
  %506 = fadd float %505, %500
  %507 = fmul float %476, %476
  %508 = fmul float %304, %507
  %509 = fadd float %508, %502
  %510 = fmul float %305, %507
  %511 = fadd float %510, %504
  %512 = fmul float %306, %507
  %513 = fadd float %512, %506
  %514 = fmul float %467, %467
  %515 = fmul float %271, %514
  %516 = fadd float %515, %509
  %517 = fmul float %272, %514
  %518 = fadd float %517, %511
  %519 = fmul float %273, %514
  %520 = fadd float %519, %513
  %521 = fmul float %485, %485
  %522 = fmul float %378, %521
  %523 = fadd float %522, %516
  %524 = fmul float %379, %521
  %525 = fadd float %524, %518
  %526 = fmul float %380, %521
  %527 = fadd float %526, %520
  %528 = fmul float %494, %494
  %529 = fmul float %403, %528
  %530 = fadd float %529, %523
  %531 = fmul float %404, %528
  %532 = fadd float %531, %525
  %533 = fmul float %405, %528
  %534 = fadd float %533, %527
  %535 = fmul float %147, %25
  %536 = fmul float %148, %26
  %537 = fmul float %149, %27
  %538 = fmul float %530, %535
  %539 = fmul float %532, %536
  %540 = fmul float %534, %537
  %541 = fsub float -0.000000e+00, %538
  %542 = fmul float %22, %535
  %543 = fadd float %542, %541
  %544 = fsub float -0.000000e+00, %539
  %545 = fmul float %23, %536
  %546 = fadd float %545, %544
  %547 = fsub float -0.000000e+00, %540
  %548 = fmul float %24, %537
  %549 = fadd float %548, %547
  %550 = fsub float -0.000000e+00, %150
  %551 = fadd float %156, %550
  %552 = fsub float -0.000000e+00, %150
  %553 = fadd float %157, %552
  %554 = fsub float -0.000000e+00, %150
  %555 = fadd float %158, %554
  %556 = fmul float %46, %551
  %557 = fadd float %556, %150
  %558 = fmul float %46, %553
  %559 = fadd float %558, %150
  %560 = fmul float %46, %555
  %561 = fadd float %560, %150
  %562 = fadd float %147, -1.000000e+00
  %563 = fadd float %148, -1.000000e+00
  %564 = fadd float %149, -1.000000e+00
  %565 = fmul float %557, %543
  %566 = fadd float %565, %538
  %567 = fmul float %559, %546
  %568 = fadd float %567, %539
  %569 = fmul float %561, %549
  %570 = fadd float %569, %540
  %571 = fcmp uge float %566, 0.000000e+00
  %572 = select i1 %571, float %566, float 0.000000e+00
  %573 = fcmp uge float %568, 0.000000e+00
  %574 = select i1 %573, float %568, float 0.000000e+00
  %575 = fcmp uge float %570, 0.000000e+00
  %576 = select i1 %575, float %570, float 0.000000e+00
  %577 = fmul float %141, %562
  %578 = fadd float %577, 1.000000e+00
  %579 = fmul float %141, %563
  %580 = fadd float %579, 1.000000e+00
  %581 = fmul float %141, %564
  %582 = fadd float %581, 1.000000e+00
  %583 = fcmp uge float %79, 0.000000e+00
  %584 = select i1 %583, float 1.000000e+00, float 0.000000e+00
  %585 = fsub float -0.000000e+00, %584
  %586 = fptosi float %585 to i32
  %587 = bitcast i32 %586 to float
  %588 = bitcast float %587 to i32
  %589 = icmp ne i32 %588, 0
  %.129 = select i1 %589, float %79, float %578
  %590 = fcmp uge float %79, 0.000000e+00
  %591 = select i1 %590, float 1.000000e+00, float 0.000000e+00
  %592 = fsub float -0.000000e+00, %591
  %593 = fptosi float %592 to i32
  %594 = bitcast i32 %593 to float
  %595 = bitcast float %594 to i32
  %596 = icmp ne i32 %595, 0
  %temp8.1 = select i1 %596, float %80, float %580
  %597 = fcmp uge float %79, 0.000000e+00
  %598 = select i1 %597, float 1.000000e+00, float 0.000000e+00
  %599 = fsub float -0.000000e+00, %598
  %600 = fptosi float %599 to i32
  %601 = bitcast i32 %600 to float
  %602 = bitcast float %601 to i32
  %603 = icmp ne i32 %602, 0
  %.130 = select i1 %603, float %81, float %582
  %604 = fsub float -0.000000e+00, %48
  %605 = fmul float %125, %50
  %606 = fadd float %605, %604
  %607 = fmul float %414, %.129
  %608 = fadd float %607, %572
  %609 = fmul float %415, %temp8.1
  %610 = fadd float %609, %574
  %611 = fmul float %416, %.130
  %612 = fadd float %611, %576
  %613 = fcmp uge float %606, %49
  %614 = select i1 %613, float %49, float %606
  %615 = call float @llvm.AMDIL.clamp.(float %614, float 0.000000e+00, float 1.000000e+00)
  %616 = fsub float -0.000000e+00, %87
  %617 = fmul float %608, %616
  %618 = fadd float %617, %83
  %619 = fsub float -0.000000e+00, %87
  %620 = fmul float %610, %619
  %621 = fadd float %620, %84
  %622 = fsub float -0.000000e+00, %87
  %623 = fmul float %612, %622
  %624 = fadd float %623, %85
  %625 = fmul float %615, %615
  %626 = fmul float %618, %625
  %627 = fmul float %621, %625
  %628 = fmul float %624, %625
  %629 = fmul float %608, %87
  %630 = fadd float %629, %626
  %631 = fmul float %610, %87
  %632 = fadd float %631, %627
  %633 = fmul float %612, %87
  %634 = fadd float %633, %628
  %635 = fmul float %125, %86
  %636 = call i32 @llvm.SI.packf16(float %630, float %632)
  %637 = bitcast i32 %636 to float
  %638 = call i32 @llvm.SI.packf16(float %634, float %635)
  %639 = bitcast i32 %638 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %637, float %639, float %637, float %639)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #3

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #3

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #4

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { readnone }
attributes #4 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%94](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%92](tbaa=!"const")
	S_WAITCNT 127
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_ADD_F32_e32 %VGPR6, %VGPR6, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_SUB_F32_e32 0.000000e+00, %VGPR4, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 108
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR0, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_F32_e32 %VGPR7, %VGPR7, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_SUB_F32_e32 0.000000e+00, %VGPR5, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %SGPR0, %VGPR10<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR5, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e32 %VGPR8, %VGPR8, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 1.000000e+00, %VGPR10, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %SGPR0, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR5, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR13<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR13<kill>, %VGPR10, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR12, %VGPR12, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR14<kill>, %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR5<kill>, %VGPR10<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR4, %VGPR4, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_F32_e64 %VGPR5<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_RSQ_LEGACY_F32_e32 %VGPR5<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR11, %VGPR11, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR10, %VGPR10, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR12, %VGPR12, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e64 %VGPR13<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_RSQ_LEGACY_F32_e32 %VGPR13<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR17, %VGPR11, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR14, %VGPR10, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR18, %VGPR4, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR14, %VGPR19, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR14, %VGPR19, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR17, %VGPR19, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR17, %VGPR19, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_INTERP_P1_F32 %VGPR0, 1, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR22<def,tied1> = V_INTERP_P2_F32 %VGPR22<kill,tied0>, %VGPR1, 1, 6, %M0<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 85
	S_WAITCNT 127
	%VGPR5<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR22, %EXEC<imp-use>
	%VGPR23<def> = V_INTERP_P1_F32 %VGPR0, 0, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR23<def,tied1> = V_INTERP_P2_F32 %VGPR23<kill,tied0>, %VGPR1, 0, 6, %M0<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 84
	S_WAITCNT 127
	%VGPR10<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR10, %VGPR10, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR5, %VGPR5, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_INTERP_P1_F32 %VGPR0, 2, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR24<def,tied1> = V_INTERP_P2_F32 %VGPR24<kill,tied0>, %VGPR1, 2, 6, %M0<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 86
	S_WAITCNT 127
	%VGPR12<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR12, %VGPR12, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_RSQ_LEGACY_F32_e32 %VGPR11<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR21, %VGPR10, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR20, %VGPR11, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR18, %VGPR19, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR18, %VGPR19, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR29, %VGPR12, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_LOG_F32_e32 %VGPR4<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%98](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%96](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5<def> = IMAGE_SAMPLE 3, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 1.490000e+02, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MAD_F32 %VGPR4, %VGPR15<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 47
	S_WAITCNT 127
	%VGPR16<def> = V_MOV_B32_e32 %SGPR1, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = V_CMP_GE_F32_e64 %SGPR1<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR12_SGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR25<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR25<def> = V_CVT_I32_F32_e32 %VGPR25<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = V_CMP_NE_I32_e64 %VGPR25<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_CNDMASK_B32_e64 %VGPR15<kill>, %VGPR16<kill>, %SGPR12_SGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_LEGACY_F32_e32 %VGPR32, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_EXP_F32_e32 %VGPR13<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR17, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR14, %VGPR11<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR18, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e64 %VGPR25, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 93
	S_WAITCNT 127
	%VGPR11<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR22, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 92
	S_WAITCNT 127
	%VGPR12<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR12, %VGPR12, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 94
	S_WAITCNT 127
	%VGPR13<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR13, %VGPR13, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e64 %VGPR15<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_RSQ_LEGACY_F32_e32 %VGPR15<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR15, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR21, %VGPR12, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR15, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR20, %VGPR11, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR29, %VGPR13, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e64 %VGPR15<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_LOG_F32_e32 %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_LEGACY_F32_e32 %VGPR32, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_EXP_F32_e32 %VGPR15<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR17, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR14, %VGPR11<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR18, %VGPR13<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e64 %VGPR26, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 89
	S_WAITCNT 127
	%VGPR27<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR11, %VGPR27, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 81
	S_WAITCNT 127
	%VGPR28<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR10, %VGPR28, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 101
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR22, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 100
	S_WAITCNT 127
	%VGPR16<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR16, %VGPR16, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR15, %VGPR15, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 102
	S_WAITCNT 127
	%VGPR30<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR30, %VGPR30, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_ADD_F32_e64 %VGPR31<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_RSQ_LEGACY_F32_e32 %VGPR31<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR31, %EXEC<imp-use>
	%VGPR34<def> = V_MUL_F32_e32 %VGPR21, %VGPR16, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR31, %EXEC<imp-use>
	%VGPR34<def> = V_MAD_F32 %VGPR20, %VGPR15, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR29, %VGPR30, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_ADD_F32_e64 %VGPR31<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_LOG_F32_e32 %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_LEGACY_F32_e32 %VGPR32, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_EXP_F32_e32 %VGPR31<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR17, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR14, %VGPR15<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_MAD_F32 %VGPR18, %VGPR30<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e64 %VGPR30, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR0, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<kill,tied0>, %VGPR1, 2, 1, %M0<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 97
	S_WAITCNT 127
	%VGPR31<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR34<def> = V_MAD_F32 %VGPR15, %VGPR31, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 99
	S_WAITCNT 127
	%VGPR22<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR22<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 95
	S_WAITCNT 127
	%VGPR23<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %VGPR23, %VGPR23, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR22, %VGPR22, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 103
	S_WAITCNT 127
	%VGPR24<def> = V_SUB_F32_e32 %SGPR1<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR24, %VGPR24, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_F32_e64 %VGPR33<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_RSQ_LEGACY_F32_e32 %VGPR33<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR23<kill>, %VGPR33, %EXEC<imp-use>
	%VGPR35<def> = V_MUL_F32_e32 %VGPR21<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR22<kill>, %VGPR33, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR20<kill>, %VGPR21, %VGPR35<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR33<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR29<kill>, %VGPR20, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_ADD_F32_e64 %VGPR22<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_LOG_F32_e32 %VGPR22<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_LEGACY_F32_e32 %VGPR32<kill>, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_EXP_F32_e32 %VGPR22<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR17, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR14, %VGPR21<kill>, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR18, %VGPR20<kill>, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e64 %VGPR29, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR22<kill>, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_INTERP_P1_F32 %VGPR0, 3, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR24<def,tied1> = V_INTERP_P2_F32 %VGPR24<kill,tied0>, %VGPR1, 3, 6, %M0<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 87
	S_WAITCNT 127
	%VGPR33<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR23, %VGPR33, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 1.000000e+00, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e64 %VGPR19<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR19<kill>, %VGPR19, -5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = V_CMP_GE_F32_e64 %VGPR19, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR12_SGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e64 %VGPR20<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR20<def> = V_CVT_I32_F32_e32 %VGPR20<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = V_CMP_NE_I32_e64 %VGPR20<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 78
	S_WAITCNT 127
	%VGPR20<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 76
	S_WAITCNT 127
	%VGPR21<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_CNDMASK_B32_e64 %VGPR21<kill>, %VGPR20<kill>, %SGPR12_SGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 77
	S_WAITCNT 127
	%VGPR34<def> = V_MAD_F32 %VGPR20<kill>, %VGPR19<kill>, %SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%90](tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%88](tbaa=!"const")
	S_WAITCNT 127
	%VGPR19_VGPR20_VGPR21_VGPR22<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR35<def> = V_SUB_F32_e32 %VGPR22, %VGPR9, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR0<kill>, %VGPR35<kill>, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR34<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 79
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR17, %VGPR17, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR17<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR7<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR7<def> = V_CVT_I32_F32_e32 %VGPR7<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_NE_I32_e64 %VGPR7<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR8, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17
	S_WAITCNT 127
	%VGPR17<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_MUL_F32_e32 %VGPR14, %VGPR14, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR14<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e64 %VGPR9<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR9<def> = V_CVT_I32_F32_e32 %VGPR9<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_NE_I32_e64 %VGPR9<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR34, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25
	S_WAITCNT 127
	%VGPR17<def> = V_MAD_F32 %VGPR9, %SGPR7<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_CNDMASK_B32_e64 %VGPR34<kill>, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29
	S_WAITCNT 127
	%VGPR34<def> = V_MAD_F32 %VGPR14, %SGPR0<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR35<def> = V_MUL_F32_e32 %VGPR18, %VGPR18, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR18<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e64 %VGPR17<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR17<def> = V_CVT_I32_F32_e32 %VGPR17<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_NE_I32_e64 %VGPR17<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR35, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33
	S_WAITCNT 127
	%VGPR34<def> = V_MAD_F32 %VGPR17, %SGPR7<kill>, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_CNDMASK_B32_e64 %VGPR35<kill>, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 37
	S_WAITCNT 127
	%VGPR34<def> = V_MAD_F32 %VGPR18, %SGPR0<kill>, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR25<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR25<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR25, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, %VGPR25, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_ADD_F32_e64 %VGPR26<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR26, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR27<kill>, %VGPR26, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR30<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_ADD_F32_e64 %VGPR27<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR27, %EXEC<imp-use>
	%VGPR30<def> = V_MAD_F32 %VGPR31<kill>, %VGPR27, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR29<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_ADD_F32_e64 %VGPR28<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR28, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR33<kill>, %VGPR28, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 5
	S_WAITCNT 127
	%VGPR30<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR20, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR30, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1
	S_WAITCNT 127
	%VGPR29<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR34<def> = V_SUB_F32_e32 %VGPR29<kill>, %VGPR33, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 12; mem:LD16[%102](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 24; mem:LD32[%100](tbaa=!"const")
	S_WAITCNT 127
	%VGPR29_VGPR30_VGPR31<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_SUB_F32_e32 %VGPR30, %VGPR22, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 43
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %SGPR0, %VGPR2<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %VGPR34<kill>, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR2, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR2<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR20, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR5, %VGPR3<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 105
	S_WAITCNT 127
	%VGPR33<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 104
	S_WAITCNT 127
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %SGPR4, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_ADD_F32_e64 %VGPR34<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR34<def> = V_CVT_I32_F32_e32 %VGPR34<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR34<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR33<kill>, %SGPR2_SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR32<kill>, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 120
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR1, %VGPR3, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 117
	S_WAITCNT 127
	%VGPR32<def> = V_SUB_F32_e32 %SGPR5<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 2, 7, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 2, 7, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 51
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 48
	S_WAITCNT 127
	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR5<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 50
	S_WAITCNT 127
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR0, %SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR3<kill>, %SGPR1, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 88
	S_WAITCNT 127
	%VGPR32<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR11, %VGPR32, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 80
	S_WAITCNT 127
	%VGPR33<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR10, %VGPR33, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 96
	S_WAITCNT 127
	%VGPR34<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR15, %VGPR34, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 83
	S_WAITCNT 127
	%VGPR35<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR23, %VGPR35, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20
	S_WAITCNT 127
	%VGPR36<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16
	S_WAITCNT 127
	%VGPR36<def> = V_MAD_F32 %VGPR7, %SGPR5<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24
	S_WAITCNT 127
	%VGPR36<def> = V_MAD_F32 %VGPR9, %SGPR5<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28
	S_WAITCNT 127
	%VGPR36<def> = V_MAD_F32 %VGPR14, %SGPR5<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32
	S_WAITCNT 127
	%VGPR36<def> = V_MAD_F32 %VGPR17, %SGPR5<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 36
	S_WAITCNT 127
	%VGPR36<def> = V_MAD_F32 %VGPR18, %SGPR5<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR33<kill>, %VGPR25, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR32<kill>, %VGPR26, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR34<kill>, %VGPR27, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR35<kill>, %VGPR28, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 4
	S_WAITCNT 127
	%VGPR33<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR19, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR33, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0
	S_WAITCNT 127
	%VGPR33<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR33<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_SUB_F32_e32 %VGPR33<kill>, %VGPR32, %EXEC<imp-use>
	%VGPR34<def> = V_SUB_F32_e32 %VGPR29, %VGPR22, %EXEC<imp-use>
	%VGPR34<def> = V_MAD_F32 %SGPR0, %VGPR34<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR34<kill>, %VGPR33<kill>, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR32, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR32<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR19, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR5, %VGPR33<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_CNDMASK_B32_e64 %VGPR33<kill>, %VGPR34<kill>, %SGPR2_SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %VGPR33<kill>, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %SGPR1, %VGPR3, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 116
	S_WAITCNT 127
	%VGPR32<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR32<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %SGPR1, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 90
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR12, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 82
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR10<kill>, %VGPR11, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 98
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR15<kill>, %VGPR10, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 91
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR23<kill>, %VGPR13, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR7<kill>, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR9<kill>, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR14<kill>, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR17<kill>, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 38
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR18<kill>, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR11<kill>, %VGPR25<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR12<kill>, %VGPR26<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR10<kill>, %VGPR27<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR13<kill>, %VGPR28<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 6
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_SUB_F32_e32 %VGPR7<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR8<def> = V_SUB_F32_e32 %VGPR31, %VGPR22, %EXEC<imp-use>, %VGPR29_VGPR30_VGPR31<imp-use,kill>
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR8<kill>, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR6, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR6<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR21, %EXEC<imp-use>, %VGPR19_VGPR20_VGPR21_VGPR22<imp-use,kill>
	%VGPR4<def> = V_MAD_F32 %VGPR5, %VGPR7<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 106
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_CNDMASK_B32_e64 %VGPR4<kill>, %VGPR5<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %VGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR1, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 118
	S_WAITCNT 127
	%VGPR4<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3<kill>, %SGPR1<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 119
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840304
c0c60508
bf8c007f
f0800f00
00430602
bf8c0770
06080d06
060808f3
080a0880
c0840100
bf8c007f
c200096c
bf8c007f
d2820004
04120a00
060a0f07
060a0af3
08140a80
d2820005
04161400
c8281100
c8291101
10141505
c82c0d00
c82d0d01
d282000b
042a090b
06141108
061414f3
081814f2
d282000a
042a1800
c8301500
c8311501
d282000b
042e150c
c8301000
c8311001
10181905
c8340c00
c8350c01
d282000c
0432090d
c8341400
c8351401
d282000c
0432150d
101a190c
d282000d
0436170b
c8381200
c8391201
100a1d05
c8380e00
c8390e01
d2820004
0416090e
c8141600
c8151601
d2820004
04121505
d2820005
04360904
d2060105
02010105
7e0a5b05
101c0b0b
10220b0c
c8280900
c8290901
c82c0800
c82d0801
1018170b
d282000d
0432150a
c8300a00
c8310a01
d282000d
0436190c
d206010d
0201010d
7e1a5b0d
10161b0b
101e1711
10141b0a
d282000f
043e150e
10240b04
10081b0c
d2820013
043e0912
100a270e
d2820005
0416270e
08281505
100a2711
d2820005
04162711
082a1705
c8581900
c8591901
c2008955
bf8c007f
080a2c01
c85c1800
c85d1801
c2008954
bf8c007f
08142e01
1016150a
d282000b
042e0b05
c8601a00
c8611a01
c2008956
bf8c007f
08183001
d282000b
042e190c
d206010b
0201010b
7e1a5b0b
10141b0a
101e1515
10161b05
d2820005
043e1714
101e2712
d282000f
043e2712
083a090f
10181b0c
d2820004
0416191d
d2060804
02010104
7e1a4f04
c0860308
c0c80510
bf8c007f
f0800300
00640402
7e1e02ff
43150000
bf8c0770
d282000f
03ca1f04
c200892f
bf8c007f
7e200201
d00c000c
02010001
d2000019
0031e480
d2060019
22010119
7e321119
d10a000c
02010119
d2000020
0032210f
0e1a1b20
7e1a4b0d
10141511
d282000a
042a170e
d2820019
042a1912
d206080a
02010119
1014150d
c200895d
bf8c007f
08162c01
c200895c
bf8c007f
08182e01
101a190c
d282000f
0436170b
c200895e
bf8c007f
081a3001
d282000f
043e1b0d
d206010f
0201010f
7e1e5b0f
10181f0c
10201915
10161f0b
d2820010
04421714
101a1f0d
d282000f
04421b1d
d206080f
0201010f
7e1e4f0f
0e1e1f20
7e1e4b0f
10181911
d282000b
0432170e
d282001a
042e1b12
d206080b
0201011a
1016170f
c8300500
c8310501
c2008959
bf8c007f
10361801
101e370b
c8340400
c8350401
c2008951
bf8c007f
10381a01
d2820021
043e390a
c2008965
bf8c007f
081e2c01
c2008964
bf8c007f
08202e01
103c2110
d282001f
047a1f0f
c2008966
bf8c007f
083c3001
d282001f
047e3d1e
d206011f
0201011f
7e3e5b1f
10203f10
10442115
101e3f0f
d2820022
048a1f14
103c3f1e
d282001f
048a3d1d
d206081f
0201011f
7e3e4f1f
0e3e3f20
7e3e4b1f
10202111
d282000f
04421f0e
d282001e
043e3d12
d206080f
0201011e
101e1f1f
c8400600
c8410601
c2008961
bf8c007f
103e2001
d2820022
04863f0f
c2008963
bf8c007f
082c2c01
c200895f
bf8c007f
082e2e01
10422f17
d2820021
04862d16
c2008967
bf8c007f
08303001
d2820021
04863118
d2060121
02010121
7e425b21
102e4317
10462f15
102a4316
d2820016
048e2b14
10284318
d2820016
045a291d
d2060816
02010116
7e2c4f16
0e2c2d20
7e2c4b16
102e2f11
d2820015
045e2b0e
d282001d
04562912
d2060814
0201011d
102e2916
c8601b00
c8611b01
c2008957
bf8c007f
10423001
d2820020
048a4317
082626f2
d2060813
02010113
d2820013
03c62713
d00c000c
02010113
d2000014
0031e480
d2060014
22010114
7e281114
d10a000c
02010114
c200894e
bf8c007f
7e280201
c200894c
bf8c007f
7e2a0201
d2000014
00322915
c200894d
bf8c007f
d2820022
00062714
c0860300
c0c80500
bf8c007f
f0800f00
00641302
bf8c0770
08461316
d2820006
04264600
100c0d22
c200094f
bf8c007f
100c0c00
10400d20
10102311
d00c0000
02010111
d2000007
0001e480
d2060007
22010107
7e0e1107
d10a0000
02010107
d2000007
00021080
d2000008
00010108
c2000915
bf8c007f
10121000
c2000911
bf8c007f
d2820011
04240107
10441d0e
d00c0000
0201010e
d2000009
0001e480
d2060009
22010109
7e121109
d10a0000
02010109
d2000009
00024480
c2038919
bf8c007f
d2820011
04440f09
d200000e
00010122
c200091d
bf8c007f
d2820022
0444010e
10462512
d00c0000
02010112
d2000011
0001e480
d2060011
22010111
7e221111
d10a0000
02010111
d2000011
00024680
c2038921
bf8c007f
d2820022
04880f11
d2000012
00010123
c2000925
bf8c007f
d2820022
04880112
d2820019
03c1e119
d2060819
02010119
10323319
d282001c
048a331c
d282001a
03c1e11a
d206081a
0201011a
1034351a
d282001c
0472351b
d282001b
03c1e11e
d206081b
0201011b
1036371b
d282001e
0472371f
d282001c
03c1e11d
d206081c
0201011c
1038391c
d282001d
047a3921
c2000905
bf8c007f
103c2800
10423d1d
c2000901
bf8c007f
103a3c00
0844431d
c080030c
c0c60518
bf8c007f
f0800700
00031d02
bf8c0770
08042d1e
c200092b
bf8c007f
d2820002
045a0400
d2820002
04864502
d00c0002
02010102
d2000002
000a0480
060628f3
d2820003
03ca0705
c2008969
bf8c007f
7e420201
c2020968
bf8c007f
d00c0002
02010004
d2000022
0009e480
d2060022
22010122
7e441122
d10a0002
02010122
d2000003
000a4303
d2820003
040a0720
c2008978
bf8c007f
10040601
c2028975
bf8c007f
08400405
c8081e00
c8091e01
c2028933
bf8c007f
10000405
c2028930
bf8c007f
0a000005
c2028932
bf8c007f
d00c0006
02000b00
7e020205
d2000000
001a0300
d2060800
02010100
10000100
10020120
d2820001
04040303
c2028958
bf8c007f
10401805
1006410b
c2028950
bf8c007f
10421a05
d2820003
040e430a
c2028960
bf8c007f
10442005
d2820003
040e450f
c2028953
bf8c007f
10463005
d2820003
040e4717
10060d03
c2028914
bf8c007f
10481005
c2028910
bf8c007f
d2820024
04900b07
c2028918
bf8c007f
d2820024
04900b09
c202891c
bf8c007f
d2820024
04900b0e
c2028920
bf8c007f
d2820024
04900b11
c2028924
bf8c007f
d2820024
04900b12
d2820021
04923321
d2820020
04863520
d2820020
04823722
d2820020
04823923
c2028904
bf8c007f
10422605
10404320
c2028900
bf8c007f
10424205
08424121
08442d1d
d2820022
045a4400
d2820020
04824322
d00c0006
02010120
d2000020
001a4080
064226f3
d2820021
03ca4305
7e440204
d2000021
000a4521
d2820003
04824303
10400601
c2020974
bf8c007f
08404004
10400120
d2820003
04800303
5e020303
c202095a
bf8c007f
10181804
1006190b
c2020952
bf8c007f
10161a04
d2820003
040e170a
c2020962
bf8c007f
10142004
d2820003
040e150f
c202095b
bf8c007f
101a3004
d2820003
040e1b17
10060d03
c2020916
bf8c007f
100c1004
c2020912
bf8c007f
d2820006
04180907
c202091a
bf8c007f
d2820006
04180909
c202091e
bf8c007f
d2820006
0418090e
c2020922
bf8c007f
d2820006
04180911
c2020926
bf8c007f
d2820006
04180912
d2820006
041a330b
d2820006
041a350c
d2820006
041a370a
d2820006
041a390d
c2020906
bf8c007f
100e2a04
100c0f06
c2020902
bf8c007f
100e0e04
080e0d07
08102d1f
d2820008
045a1000
d2820006
041a0f08
d00c0004
02010106
d2000006
00120c80
060e2af3
d2820004
03ca0f05
c200096a
bf8c007f
7e0a0200
d2000004
000a0b04
d2820003
041a0903
10080601
c2000976
bf8c007f
08080800
10000104
d2820000
04000303
c2000977
bf8c007f
10040400
5e000500
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL OUT[5], GENERIC[22]
DCL OUT[6], GENERIC[23]
DCL OUT[7], GENERIC[24]
DCL OUT[8], GENERIC[25]
DCL OUT[9], GENERIC[26]
DCL CONST[0..61]
DCL TEMP[0..13], LOCAL
IMM[0] FLT32 { -128.0000,     1.0000,   -64.0000,    -0.0159}
IMM[1] FLT32 {    0.0159,     0.0001,     0.0000,     0.0000}
  0: ADD TEMP[0], IN[1], IMM[0].xxxx
  1: SLT TEMP[1], TEMP[0], CONST[0].xxxx
  2: F2I TEMP[1], -TEMP[1]
  3: AND TEMP[1], TEMP[1], IMM[0].yyyy
  4: ABS TEMP[0], TEMP[0]
  5: ADD TEMP[0], TEMP[0], -TEMP[1]
  6: ADD TEMP[0], TEMP[0], IMM[0].zzzz
  7: SLT TEMP[2], TEMP[0], CONST[0].xxxx
  8: F2I TEMP[2], -TEMP[2]
  9: AND TEMP[2], TEMP[2], IMM[0].yyyy
 10: ABS TEMP[0], TEMP[0]
 11: ADD TEMP[0], TEMP[0], -TEMP[2]
 12: MAD TEMP[1].xyz, CONST[0].zzzz, -TEMP[1].xzww, CONST[0].yyyy
 13: MAD TEMP[3].xy, TEMP[0].xzzz, IMM[0].wwww, IMM[0].yyyy
 14: MAD TEMP[4].x, TEMP[0].yyyy, IMM[0].wwww, TEMP[3].xxxx
 15: MOV TEMP[3].z, TEMP[4].xxxx
 16: MUL TEMP[4], TEMP[0], IMM[1].xxxx
 17: MAD TEMP[5].x, TEMP[0].wwww, IMM[0].wwww, TEMP[3].yyyy
 18: MOV TEMP[0].z, TEMP[5].xxxx
 19: MOV TEMP[3].xy, TEMP[4].xyxx
 20: MAD TEMP[5], CONST[0].zzzz, -TEMP[2], CONST[0].yyyy
 21: DP3 TEMP[6].x, TEMP[3].xyzz, TEMP[3].xyzz
 22: RSQ TEMP[6].x, TEMP[6].xxxx
 23: MUL TEMP[6].xyz, TEMP[3].xyzz, TEMP[6].xxxx
 24: MUL TEMP[3].xy, TEMP[5].xyyy, TEMP[6].xyyy
 25: MUL TEMP[6].x, TEMP[1].xxxx, TEMP[6].zzzz
 26: MOV TEMP[3].z, TEMP[6].xxxx
 27: MAD TEMP[3].xyz, IN[4].xyzz, CONST[3].xxxx, TEMP[3].xyzz
 28: MOV TEMP[0].xy, TEMP[4].zwzz
 29: DP3 TEMP[4].x, TEMP[3].xyzz, CONST[56].xyzz
 30: MOV TEMP[2].z, TEMP[4].xxxx
 31: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz
 32: RSQ TEMP[4].x, TEMP[4].xxxx
 33: MUL TEMP[4].xyz, TEMP[0].xyzz, TEMP[4].xxxx
 34: MUL TEMP[5].xy, TEMP[5].zwww, TEMP[4].xyyy
 35: MUL TEMP[4].x, TEMP[1].yyyy, TEMP[4].zzzz
 36: MOV TEMP[5].z, TEMP[4].xxxx
 37: DP3 TEMP[2].x, TEMP[3].xyzz, CONST[54].xyzz
 38: DP3 TEMP[4].x, TEMP[3].xyzz, CONST[55].xyzz
 39: MOV TEMP[2].y, TEMP[4].xxxx
 40: MAD TEMP[0].xyz, IN[4].xyzz, CONST[3].xxxx, TEMP[5].xyzz
 41: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[2].xyzz
 42: DP3 TEMP[4].x, TEMP[0].xyzz, CONST[56].xyzz
 43: MOV TEMP[5].z, TEMP[4].xxxx
 44: RSQ TEMP[4].x, TEMP[5].xxxx
 45: DP3 TEMP[5].x, TEMP[0].xyzz, CONST[54].xyzz
 46: DP3 TEMP[6].x, TEMP[0].xyzz, CONST[55].xyzz
 47: MOV TEMP[5].y, TEMP[6].xxxx
 48: MUL TEMP[4].xyz, TEMP[2].xyzz, TEMP[4].xxxx
 49: DP3 TEMP[0].x, TEMP[5].xyzz, TEMP[5].xyzz
 50: RSQ TEMP[6].x, TEMP[0].xxxx
 51: MUL TEMP[0].xyz, TEMP[2].zxyy, TEMP[5].yzxx
 52: MUL TEMP[6].xyz, TEMP[5].xyzz, TEMP[6].xxxx
 53: MAD TEMP[5].xyz, TEMP[2].yzxx, TEMP[5].zxyy, -TEMP[0].xyzz
 54: MOV TEMP[5].w, IN[0].wwww
 55: MUL TEMP[2].xyz, TEMP[1].zzzz, TEMP[5].xyzz
 56: MAD TEMP[5].xyz, IN[3].xyzz, CONST[3].xxxx, IN[0].xyzz
 57: DP3 TEMP[0].x, TEMP[2].xyzz, TEMP[2].xyzz
 58: DP4 TEMP[1].x, TEMP[5], CONST[56]
 59: MOV TEMP[0].z, TEMP[1].xxxx
 60: RSQ TEMP[1].x, TEMP[0].xxxx
 61: DP4 TEMP[0].x, TEMP[5], CONST[54]
 62: DP4 TEMP[7].x, TEMP[5], CONST[55]
 63: MOV TEMP[0].y, TEMP[7].xxxx
 64: MUL TEMP[1].xyz, TEMP[2].xyzz, TEMP[1].xxxx
 65: ADD TEMP[7].xyz, -TEMP[0].xyzz, CONST[2].xyzz
 66: UIF CONST[58].xxxx :0
 67:   ADD TEMP[2].xyz, -TEMP[0].xyzz, CONST[29].xyzz
 68:   DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
 69:   RSQ TEMP[8].x, TEMP[3].xxxx
 70:   MOV TEMP[5].y, TEMP[8].xxxx
 71:   MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[8].xxxx
 72:   MOV TEMP[3].y, CONST[0].yyyy
 73:   DP3 TEMP[8].x, CONST[28].xyzz, -TEMP[2].xyzz
 74:   ADD TEMP[8].x, TEMP[8].xxxx, -CONST[30].zzzz
 75:   MOV TEMP[5].xz, CONST[0].yyyy
 76:   MUL TEMP[8].x, TEMP[8].xxxx, CONST[30].wwww
 77:   MUL TEMP[5].xyz, TEMP[3].yxxx, TEMP[5].xyzz
 78:   MAX TEMP[8].x, TEMP[8].xxxx, IMM[1].yyyy
 79:   DP3 TEMP[9].x, CONST[31].xyzz, TEMP[5].xyzz
 80:   MOV TEMP[5].x, TEMP[9].xxxx
 81:   POW TEMP[8].x, TEMP[8].xxxx, CONST[30].xxxx
 82:   RCP TEMP[9].x, TEMP[9].xxxx
 83:   MIN TEMP[8].x, TEMP[8].xxxx, CONST[0].yyyy
 84:   MAD TEMP[8].x, TEMP[9].xxxx, TEMP[8].xxxx, -TEMP[9].xxxx
 85:   MAD TEMP[8].x, CONST[28].wwww, TEMP[8].xxxx, TEMP[9].xxxx
 86:   ADD TEMP[9].x, -TEMP[8].xxxx, CONST[0].yyyy
 87:   MAD TEMP[8].x, CONST[27].wwww, TEMP[9].xxxx, TEMP[8].xxxx
 88: ELSE :0
 89:   MOV TEMP[8].x, CONST[0].xxxx
 90: ENDIF
 91: UIF CONST[59].xxxx :0
 92:   ADD TEMP[2].xyz, -TEMP[0].xyzz, CONST[34].xyzz
 93:   DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
 94:   RSQ TEMP[9].x, TEMP[3].xxxx
 95:   MOV TEMP[5].y, TEMP[9].xxxx
 96:   MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[9].xxxx
 97:   MOV TEMP[3].y, CONST[0].yyyy
 98:   DP3 TEMP[9].x, CONST[33].xyzz, -TEMP[2].xyzz
 99:   ADD TEMP[9].x, TEMP[9].xxxx, -CONST[35].zzzz
100:   MOV TEMP[5].xz, CONST[0].yyyy
101:   MUL TEMP[9].x, TEMP[9].xxxx, CONST[35].wwww
102:   MUL TEMP[5].xyz, TEMP[3].yxxx, TEMP[5].xyzz
103:   MAX TEMP[9].x, TEMP[9].xxxx, IMM[1].yyyy
104:   DP3 TEMP[10].x, CONST[36].xyzz, TEMP[5].xyzz
105:   MOV TEMP[5].x, TEMP[10].xxxx
106:   POW TEMP[9].x, TEMP[9].xxxx, CONST[35].xxxx
107:   RCP TEMP[10].x, TEMP[10].xxxx
108:   MIN TEMP[9].x, TEMP[9].xxxx, CONST[0].yyyy
109:   MAD TEMP[9].x, TEMP[10].xxxx, TEMP[9].xxxx, -TEMP[10].xxxx
110:   MAD TEMP[9].x, CONST[33].wwww, TEMP[9].xxxx, TEMP[10].xxxx
111:   ADD TEMP[10].x, -TEMP[9].xxxx, CONST[0].yyyy
112:   MAD TEMP[9].x, CONST[32].wwww, TEMP[10].xxxx, TEMP[9].xxxx
113:   MOV TEMP[8].y, TEMP[9].xxxx
114: ELSE :0
115:   MOV TEMP[8].y, CONST[0].xxxx
116: ENDIF
117: UIF CONST[60].xxxx :0
118:   ADD TEMP[2].xyz, -TEMP[0].xyzz, CONST[39].xyzz
119:   DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
120:   RSQ TEMP[9].x, TEMP[3].xxxx
121:   MOV TEMP[5].y, TEMP[9].xxxx
122:   MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[9].xxxx
123:   MOV TEMP[3].y, CONST[0].yyyy
124:   DP3 TEMP[9].x, CONST[38].xyzz, -TEMP[2].xyzz
125:   ADD TEMP[9].x, TEMP[9].xxxx, -CONST[40].zzzz
126:   MOV TEMP[5].xz, CONST[0].yyyy
127:   MUL TEMP[9].x, TEMP[9].xxxx, CONST[40].wwww
128:   MUL TEMP[5].xyz, TEMP[3].yxxx, TEMP[5].xyzz
129:   MAX TEMP[9].x, TEMP[9].xxxx, IMM[1].yyyy
130:   DP3 TEMP[10].x, CONST[41].xyzz, TEMP[5].xyzz
131:   MOV TEMP[5].x, TEMP[10].xxxx
132:   POW TEMP[9].x, TEMP[9].xxxx, CONST[40].xxxx
133:   RCP TEMP[10].x, TEMP[10].xxxx
134:   MIN TEMP[9].x, TEMP[9].xxxx, CONST[0].yyyy
135:   MAD TEMP[9].x, TEMP[10].xxxx, TEMP[9].xxxx, -TEMP[10].xxxx
136:   MAD TEMP[9].x, CONST[38].wwww, TEMP[9].xxxx, TEMP[10].xxxx
137:   ADD TEMP[10].x, -TEMP[9].xxxx, CONST[0].yyyy
138:   MAD TEMP[9].x, CONST[37].wwww, TEMP[10].xxxx, TEMP[9].xxxx
139:   MOV TEMP[8].z, TEMP[9].xxxx
140: ELSE :0
141:   MOV TEMP[8].z, CONST[0].xxxx
142: ENDIF
143: UIF CONST[61].xxxx :0
144:   ADD TEMP[2].xyz, -TEMP[0].xyzz, CONST[44].xyzz
145:   DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
146:   RSQ TEMP[9].x, TEMP[3].xxxx
147:   MOV TEMP[5].y, TEMP[9].xxxx
148:   MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[9].xxxx
149:   MOV TEMP[3].y, CONST[0].yyyy
150:   DP3 TEMP[9].x, CONST[43].xyzz, -TEMP[2].xyzz
151:   ADD TEMP[9].x, TEMP[9].xxxx, -CONST[45].zzzz
152:   MOV TEMP[5].xz, CONST[0].yyyy
153:   MUL TEMP[9].x, TEMP[9].xxxx, CONST[45].wwww
154:   MUL TEMP[5].xyz, TEMP[3].yxxx, TEMP[5].xyzz
155:   MAX TEMP[3].x, TEMP[9].xxxx, IMM[1].yyyy
156:   DP3 TEMP[9].x, CONST[46].xyzz, TEMP[5].xyzz
157:   POW TEMP[3].x, TEMP[3].xxxx, CONST[45].xxxx
158:   RCP TEMP[9].x, TEMP[9].xxxx
159:   MIN TEMP[3].x, TEMP[3].xxxx, CONST[0].yyyy
160:   MAD TEMP[3].x, TEMP[9].xxxx, TEMP[3].xxxx, -TEMP[9].xxxx
161:   MAD TEMP[3].x, CONST[43].wwww, TEMP[3].xxxx, TEMP[9].xxxx
162:   ADD TEMP[9].x, -TEMP[3].xxxx, CONST[0].yyyy
163:   MAD TEMP[5].x, CONST[42].wwww, TEMP[9].xxxx, TEMP[3].xxxx
164: ELSE :0
165:   MOV TEMP[5].x, CONST[0].xxxx
166: ENDIF
167: MOV TEMP[5].yzw, TEMP[0].yxyz
168: MOV TEMP[0].w, CONST[0].yyyy
169: DP4 TEMP[3].x, TEMP[0], CONST[13]
170: MOV TEMP[2].z, TEMP[3].xxxx
171: MUL TEMP[3].x, IN[3].wwww, CONST[3].yyyy
172: MOV TEMP[2].w, TEMP[3].xxxx
173: MOV TEMP[3], TEMP[5].yzwx
174: MOV TEMP[2].zw, TEMP[2].wwzw
175: DP4 TEMP[5].x, TEMP[0], CONST[8]
176: DP4 TEMP[9].x, TEMP[0], CONST[9]
177: MOV TEMP[5].y, TEMP[9].xxxx
178: MOV TEMP[2].xy, TEMP[5].xyxx
179: DP4 TEMP[10].x, TEMP[0], CONST[10]
180: MOV TEMP[5].z, TEMP[10].xxxx
181: DP4 TEMP[0].x, TEMP[0], CONST[11]
182: MOV TEMP[5].w, TEMP[0].xxxx
183: MOV TEMP[11].xw, TEMP[5].xxxw
184: DP4 TEMP[12].x, IN[2], CONST[48]
185: DP4 TEMP[13].x, IN[2], CONST[49]
186: MOV TEMP[12].y, TEMP[13].xxxx
187: DP4 TEMP[13].x, IN[2], CONST[52]
188: MOV TEMP[12].z, TEMP[13].xxxx
189: DP4 TEMP[13].x, IN[2], CONST[53]
190: MOV TEMP[12].w, TEMP[13].xxxx
191: MAD TEMP[10].x, TEMP[10].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
192: MOV TEMP[11].z, TEMP[10].xxxx
193: MOV TEMP[11].y, -TEMP[9].xxxx
194: MAD TEMP[11].xy, CONST[57].xyyy, TEMP[0].xxxx, TEMP[11].xyyy
195: MOV OUT[2], TEMP[12]
196: MOV OUT[3], TEMP[8]
197: MOV OUT[4], TEMP[7]
198: MOV OUT[5], TEMP[6]
199: MOV OUT[0], TEMP[11]
200: MOV OUT[6], TEMP[1]
201: MOV OUT[1], TEMP[5]
202: MOV OUT[7], TEMP[4]
203: MOV OUT[8], TEMP[3]
204: MOV OUT[9], TEMP[2]
205: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 444)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 460)
  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 492)
  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 524)
  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 528)
  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 532)
  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 536)
  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 540)
  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 544)
  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 548)
  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 552)
  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 560)
  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 568)
  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 572)
  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 576)
  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 580)
  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 584)
  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 604)
  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 608)
  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 612)
  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 616)
  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 620)
  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 624)
  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 628)
  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 632)
  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 640)
  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 648)
  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 652)
  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 656)
  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 660)
  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 664)
  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 684)
  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 688)
  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 692)
  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 696)
  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 700)
  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 704)
  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 708)
  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 712)
  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 720)
  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 728)
  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 732)
  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 736)
  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 740)
  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 744)
  %95 = call float @llvm.SI.load.const(<16 x i8> %10, i32 768)
  %96 = call float @llvm.SI.load.const(<16 x i8> %10, i32 772)
  %97 = call float @llvm.SI.load.const(<16 x i8> %10, i32 776)
  %98 = call float @llvm.SI.load.const(<16 x i8> %10, i32 780)
  %99 = call float @llvm.SI.load.const(<16 x i8> %10, i32 784)
  %100 = call float @llvm.SI.load.const(<16 x i8> %10, i32 788)
  %101 = call float @llvm.SI.load.const(<16 x i8> %10, i32 792)
  %102 = call float @llvm.SI.load.const(<16 x i8> %10, i32 796)
  %103 = call float @llvm.SI.load.const(<16 x i8> %10, i32 832)
  %104 = call float @llvm.SI.load.const(<16 x i8> %10, i32 836)
  %105 = call float @llvm.SI.load.const(<16 x i8> %10, i32 840)
  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 844)
  %107 = call float @llvm.SI.load.const(<16 x i8> %10, i32 848)
  %108 = call float @llvm.SI.load.const(<16 x i8> %10, i32 852)
  %109 = call float @llvm.SI.load.const(<16 x i8> %10, i32 856)
  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 860)
  %111 = call float @llvm.SI.load.const(<16 x i8> %10, i32 864)
  %112 = call float @llvm.SI.load.const(<16 x i8> %10, i32 868)
  %113 = call float @llvm.SI.load.const(<16 x i8> %10, i32 872)
  %114 = call float @llvm.SI.load.const(<16 x i8> %10, i32 876)
  %115 = call float @llvm.SI.load.const(<16 x i8> %10, i32 880)
  %116 = call float @llvm.SI.load.const(<16 x i8> %10, i32 884)
  %117 = call float @llvm.SI.load.const(<16 x i8> %10, i32 888)
  %118 = call float @llvm.SI.load.const(<16 x i8> %10, i32 892)
  %119 = call float @llvm.SI.load.const(<16 x i8> %10, i32 896)
  %120 = call float @llvm.SI.load.const(<16 x i8> %10, i32 900)
  %121 = call float @llvm.SI.load.const(<16 x i8> %10, i32 904)
  %122 = call float @llvm.SI.load.const(<16 x i8> %10, i32 908)
  %123 = call float @llvm.SI.load.const(<16 x i8> %10, i32 912)
  %124 = call float @llvm.SI.load.const(<16 x i8> %10, i32 916)
  %125 = call float @llvm.SI.load.const(<16 x i8> %10, i32 928)
  %126 = call float @llvm.SI.load.const(<16 x i8> %10, i32 944)
  %127 = call float @llvm.SI.load.const(<16 x i8> %10, i32 960)
  %128 = call float @llvm.SI.load.const(<16 x i8> %10, i32 976)
  %129 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %130 = load <16 x i8> addrspace(2)* %129, !tbaa !0
  %131 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %130, i32 0, i32 %5)
  %132 = extractelement <4 x float> %131, i32 0
  %133 = extractelement <4 x float> %131, i32 1
  %134 = extractelement <4 x float> %131, i32 2
  %135 = extractelement <4 x float> %131, i32 3
  %136 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %137 = load <16 x i8> addrspace(2)* %136, !tbaa !0
  %138 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %137, i32 0, i32 %5)
  %139 = extractelement <4 x float> %138, i32 0
  %140 = extractelement <4 x float> %138, i32 1
  %141 = extractelement <4 x float> %138, i32 2
  %142 = extractelement <4 x float> %138, i32 3
  %143 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %144 = load <16 x i8> addrspace(2)* %143, !tbaa !0
  %145 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %144, i32 0, i32 %5)
  %146 = extractelement <4 x float> %145, i32 0
  %147 = extractelement <4 x float> %145, i32 1
  %148 = extractelement <4 x float> %145, i32 2
  %149 = extractelement <4 x float> %145, i32 3
  %150 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %151 = load <16 x i8> addrspace(2)* %150, !tbaa !0
  %152 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %151, i32 0, i32 %5)
  %153 = extractelement <4 x float> %152, i32 0
  %154 = extractelement <4 x float> %152, i32 1
  %155 = extractelement <4 x float> %152, i32 2
  %156 = extractelement <4 x float> %152, i32 3
  %157 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %158 = load <16 x i8> addrspace(2)* %157, !tbaa !0
  %159 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %158, i32 0, i32 %5)
  %160 = extractelement <4 x float> %159, i32 0
  %161 = extractelement <4 x float> %159, i32 1
  %162 = extractelement <4 x float> %159, i32 2
  %163 = fadd float %139, -1.280000e+02
  %164 = fadd float %140, -1.280000e+02
  %165 = fadd float %141, -1.280000e+02
  %166 = fadd float %142, -1.280000e+02
  %167 = fcmp ult float %163, %11
  %168 = select i1 %167, float 1.000000e+00, float 0.000000e+00
  %169 = fcmp ult float %164, %11
  %170 = select i1 %169, float 1.000000e+00, float 0.000000e+00
  %171 = fcmp ult float %165, %11
  %172 = select i1 %171, float 1.000000e+00, float 0.000000e+00
  %173 = fcmp ult float %166, %11
  %174 = select i1 %173, float 1.000000e+00, float 0.000000e+00
  %175 = fsub float -0.000000e+00, %168
  %176 = fptosi float %175 to i32
  %177 = fsub float -0.000000e+00, %170
  %178 = fptosi float %177 to i32
  %179 = fsub float -0.000000e+00, %172
  %180 = fptosi float %179 to i32
  %181 = fsub float -0.000000e+00, %174
  %182 = fptosi float %181 to i32
  %183 = bitcast i32 %176 to float
  %184 = bitcast i32 %178 to float
  %185 = bitcast i32 %180 to float
  %186 = bitcast i32 %182 to float
  %187 = bitcast float %183 to i32
  %188 = and i32 %187, 1065353216
  %189 = bitcast float %184 to i32
  %190 = and i32 %189, 1065353216
  %191 = bitcast float %185 to i32
  %192 = and i32 %191, 1065353216
  %193 = bitcast float %186 to i32
  %194 = and i32 %193, 1065353216
  %195 = bitcast i32 %188 to float
  %196 = bitcast i32 %190 to float
  %197 = bitcast i32 %192 to float
  %198 = bitcast i32 %194 to float
  %199 = call float @fabs(float %163)
  %200 = call float @fabs(float %164)
  %201 = call float @fabs(float %165)
  %202 = call float @fabs(float %166)
  %203 = fsub float -0.000000e+00, %195
  %204 = fadd float %199, %203
  %205 = fsub float -0.000000e+00, %196
  %206 = fadd float %200, %205
  %207 = fsub float -0.000000e+00, %197
  %208 = fadd float %201, %207
  %209 = fsub float -0.000000e+00, %198
  %210 = fadd float %202, %209
  %211 = fadd float %204, -6.400000e+01
  %212 = fadd float %206, -6.400000e+01
  %213 = fadd float %208, -6.400000e+01
  %214 = fadd float %210, -6.400000e+01
  %215 = fcmp ult float %211, %11
  %216 = select i1 %215, float 1.000000e+00, float 0.000000e+00
  %217 = fcmp ult float %212, %11
  %218 = select i1 %217, float 1.000000e+00, float 0.000000e+00
  %219 = fcmp ult float %213, %11
  %220 = select i1 %219, float 1.000000e+00, float 0.000000e+00
  %221 = fcmp ult float %214, %11
  %222 = select i1 %221, float 1.000000e+00, float 0.000000e+00
  %223 = fsub float -0.000000e+00, %216
  %224 = fptosi float %223 to i32
  %225 = fsub float -0.000000e+00, %218
  %226 = fptosi float %225 to i32
  %227 = fsub float -0.000000e+00, %220
  %228 = fptosi float %227 to i32
  %229 = fsub float -0.000000e+00, %222
  %230 = fptosi float %229 to i32
  %231 = bitcast i32 %224 to float
  %232 = bitcast i32 %226 to float
  %233 = bitcast i32 %228 to float
  %234 = bitcast i32 %230 to float
  %235 = bitcast float %231 to i32
  %236 = and i32 %235, 1065353216
  %237 = bitcast float %232 to i32
  %238 = and i32 %237, 1065353216
  %239 = bitcast float %233 to i32
  %240 = and i32 %239, 1065353216
  %241 = bitcast float %234 to i32
  %242 = and i32 %241, 1065353216
  %243 = bitcast i32 %236 to float
  %244 = bitcast i32 %238 to float
  %245 = bitcast i32 %240 to float
  %246 = bitcast i32 %242 to float
  %247 = call float @fabs(float %211)
  %248 = call float @fabs(float %212)
  %249 = call float @fabs(float %213)
  %250 = call float @fabs(float %214)
  %251 = fsub float -0.000000e+00, %243
  %252 = fadd float %247, %251
  %253 = fsub float -0.000000e+00, %244
  %254 = fadd float %248, %253
  %255 = fsub float -0.000000e+00, %245
  %256 = fadd float %249, %255
  %257 = fsub float -0.000000e+00, %246
  %258 = fadd float %250, %257
  %259 = fsub float -0.000000e+00, %195
  %260 = fmul float %13, %259
  %261 = fadd float %260, %12
  %262 = fsub float -0.000000e+00, %197
  %263 = fmul float %13, %262
  %264 = fadd float %263, %12
  %265 = fsub float -0.000000e+00, %198
  %266 = fmul float %13, %265
  %267 = fadd float %266, %12
  %268 = fmul float %252, 0xBF90410420000000
  %269 = fadd float %268, 1.000000e+00
  %270 = fmul float %256, 0xBF90410420000000
  %271 = fadd float %270, 1.000000e+00
  %272 = fmul float %254, 0xBF90410420000000
  %273 = fadd float %272, %269
  %274 = fmul float %252, 0x3F90410420000000
  %275 = fmul float %254, 0x3F90410420000000
  %276 = fmul float %256, 0x3F90410420000000
  %277 = fmul float %258, 0x3F90410420000000
  %278 = fmul float %258, 0xBF90410420000000
  %279 = fadd float %278, %271
  %280 = fsub float -0.000000e+00, %243
  %281 = fmul float %13, %280
  %282 = fadd float %281, %12
  %283 = fsub float -0.000000e+00, %244
  %284 = fmul float %13, %283
  %285 = fadd float %284, %12
  %286 = fsub float -0.000000e+00, %245
  %287 = fmul float %13, %286
  %288 = fadd float %287, %12
  %289 = fsub float -0.000000e+00, %246
  %290 = fmul float %13, %289
  %291 = fadd float %290, %12
  %292 = fmul float %274, %274
  %293 = fmul float %275, %275
  %294 = fadd float %293, %292
  %295 = fmul float %273, %273
  %296 = fadd float %294, %295
  %297 = call float @fabs(float %296)
  %298 = call float @llvm.AMDGPU.rsq(float %297)
  %299 = fmul float %274, %298
  %300 = fmul float %275, %298
  %301 = fmul float %273, %298
  %302 = fmul float %282, %299
  %303 = fmul float %285, %300
  %304 = fmul float %261, %301
  %305 = fmul float %160, %17
  %306 = fadd float %305, %302
  %307 = fmul float %161, %17
  %308 = fadd float %307, %303
  %309 = fmul float %162, %17
  %310 = fadd float %309, %304
  %311 = fmul float %306, %119
  %312 = fmul float %308, %120
  %313 = fadd float %312, %311
  %314 = fmul float %310, %121
  %315 = fadd float %313, %314
  %316 = fmul float %276, %276
  %317 = fmul float %277, %277
  %318 = fadd float %317, %316
  %319 = fmul float %279, %279
  %320 = fadd float %318, %319
  %321 = call float @fabs(float %320)
  %322 = call float @llvm.AMDGPU.rsq(float %321)
  %323 = fmul float %276, %322
  %324 = fmul float %277, %322
  %325 = fmul float %279, %322
  %326 = fmul float %288, %323
  %327 = fmul float %291, %324
  %328 = fmul float %264, %325
  %329 = fmul float %306, %111
  %330 = fmul float %308, %112
  %331 = fadd float %330, %329
  %332 = fmul float %310, %113
  %333 = fadd float %331, %332
  %334 = fmul float %306, %115
  %335 = fmul float %308, %116
  %336 = fadd float %335, %334
  %337 = fmul float %310, %117
  %338 = fadd float %336, %337
  %339 = fmul float %160, %17
  %340 = fadd float %339, %326
  %341 = fmul float %161, %17
  %342 = fadd float %341, %327
  %343 = fmul float %162, %17
  %344 = fadd float %343, %328
  %345 = fmul float %333, %333
  %346 = fmul float %338, %338
  %347 = fadd float %346, %345
  %348 = fmul float %315, %315
  %349 = fadd float %347, %348
  %350 = fmul float %340, %119
  %351 = fmul float %342, %120
  %352 = fadd float %351, %350
  %353 = fmul float %344, %121
  %354 = fadd float %352, %353
  %355 = call float @fabs(float %349)
  %356 = call float @llvm.AMDGPU.rsq(float %355)
  %357 = fmul float %340, %111
  %358 = fmul float %342, %112
  %359 = fadd float %358, %357
  %360 = fmul float %344, %113
  %361 = fadd float %359, %360
  %362 = fmul float %340, %115
  %363 = fmul float %342, %116
  %364 = fadd float %363, %362
  %365 = fmul float %344, %117
  %366 = fadd float %364, %365
  %367 = fmul float %333, %356
  %368 = fmul float %338, %356
  %369 = fmul float %315, %356
  %370 = fmul float %361, %361
  %371 = fmul float %366, %366
  %372 = fadd float %371, %370
  %373 = fmul float %354, %354
  %374 = fadd float %372, %373
  %375 = call float @fabs(float %374)
  %376 = call float @llvm.AMDGPU.rsq(float %375)
  %377 = fmul float %315, %366
  %378 = fmul float %333, %354
  %379 = fmul float %338, %361
  %380 = fmul float %361, %376
  %381 = fmul float %366, %376
  %382 = fmul float %354, %376
  %383 = fsub float -0.000000e+00, %377
  %384 = fmul float %338, %354
  %385 = fadd float %384, %383
  %386 = fsub float -0.000000e+00, %378
  %387 = fmul float %315, %361
  %388 = fadd float %387, %386
  %389 = fsub float -0.000000e+00, %379
  %390 = fmul float %333, %366
  %391 = fadd float %390, %389
  %392 = fmul float %267, %385
  %393 = fmul float %267, %388
  %394 = fmul float %267, %391
  %395 = fmul float %153, %17
  %396 = fadd float %395, %132
  %397 = fmul float %154, %17
  %398 = fadd float %397, %133
  %399 = fmul float %155, %17
  %400 = fadd float %399, %134
  %401 = fmul float %392, %392
  %402 = fmul float %393, %393
  %403 = fadd float %402, %401
  %404 = fmul float %394, %394
  %405 = fadd float %403, %404
  %406 = fmul float %396, %119
  %407 = fmul float %398, %120
  %408 = fadd float %406, %407
  %409 = fmul float %400, %121
  %410 = fadd float %408, %409
  %411 = fmul float %135, %122
  %412 = fadd float %410, %411
  %413 = call float @fabs(float %405)
  %414 = call float @llvm.AMDGPU.rsq(float %413)
  %415 = fmul float %396, %111
  %416 = fmul float %398, %112
  %417 = fadd float %415, %416
  %418 = fmul float %400, %113
  %419 = fadd float %417, %418
  %420 = fmul float %135, %114
  %421 = fadd float %419, %420
  %422 = fmul float %396, %115
  %423 = fmul float %398, %116
  %424 = fadd float %422, %423
  %425 = fmul float %400, %117
  %426 = fadd float %424, %425
  %427 = fmul float %135, %118
  %428 = fadd float %426, %427
  %429 = fmul float %392, %414
  %430 = fmul float %393, %414
  %431 = fmul float %394, %414
  %432 = fsub float -0.000000e+00, %421
  %433 = fadd float %432, %14
  %434 = fsub float -0.000000e+00, %428
  %435 = fadd float %434, %15
  %436 = fsub float -0.000000e+00, %412
  %437 = fadd float %436, %16
  %438 = bitcast float %125 to i32
  %439 = icmp ne i32 %438, 0
  br i1 %439, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %440 = fadd float %432, %44
  %441 = fsub float -0.000000e+00, %428
  %442 = fadd float %441, %45
  %443 = fsub float -0.000000e+00, %412
  %444 = fadd float %443, %46
  %445 = fmul float %440, %440
  %446 = fmul float %442, %442
  %447 = fadd float %446, %445
  %448 = fmul float %444, %444
  %449 = fadd float %447, %448
  %450 = call float @fabs(float %449)
  %451 = call float @llvm.AMDGPU.rsq(float %450)
  %452 = fmul float %440, %451
  %453 = fmul float %442, %451
  %454 = fmul float %444, %451
  %455 = fsub float -0.000000e+00, %452
  %456 = fsub float -0.000000e+00, %453
  %457 = fsub float -0.000000e+00, %454
  %458 = fmul float %40, %455
  %459 = fmul float %41, %456
  %460 = fadd float %459, %458
  %461 = fmul float %42, %457
  %462 = fadd float %460, %461
  %463 = fsub float -0.000000e+00, %48
  %464 = fadd float %462, %463
  %465 = fmul float %464, %49
  %466 = fmul float %12, %12
  %467 = fmul float %449, %451
  %468 = fmul float %449, %12
  %469 = fcmp uge float %465, 0x3F1A36E2E0000000
  %470 = select i1 %469, float %465, float 0x3F1A36E2E0000000
  %471 = fmul float %50, %466
  %472 = fmul float %51, %467
  %473 = fadd float %472, %471
  %474 = fmul float %52, %468
  %475 = fadd float %473, %474
  %476 = call float @llvm.pow.f32(float %470, float %47)
  %477 = fdiv float 1.000000e+00, %475
  %478 = fcmp uge float %476, %12
  %479 = select i1 %478, float %12, float %476
  %480 = fsub float -0.000000e+00, %477
  %481 = fmul float %477, %479
  %482 = fadd float %481, %480
  %483 = fmul float %43, %482
  %484 = fadd float %483, %477
  %485 = fsub float -0.000000e+00, %484
  %486 = fadd float %485, %12
  %487 = fmul float %39, %486
  %488 = fadd float %487, %484
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp32.0 = phi float [ %488, %IF ], [ %11, %main_body ]
  %489 = bitcast float %126 to i32
  %490 = icmp ne i32 %489, 0
  br i1 %490, label %IF57, label %ENDIF56

IF57:                                             ; preds = %ENDIF
  %491 = fsub float -0.000000e+00, %421
  %492 = fadd float %491, %58
  %493 = fsub float -0.000000e+00, %428
  %494 = fadd float %493, %59
  %495 = fsub float -0.000000e+00, %412
  %496 = fadd float %495, %60
  %497 = fmul float %492, %492
  %498 = fmul float %494, %494
  %499 = fadd float %498, %497
  %500 = fmul float %496, %496
  %501 = fadd float %499, %500
  %502 = call float @fabs(float %501)
  %503 = call float @llvm.AMDGPU.rsq(float %502)
  %504 = fmul float %492, %503
  %505 = fmul float %494, %503
  %506 = fmul float %496, %503
  %507 = fsub float -0.000000e+00, %504
  %508 = fsub float -0.000000e+00, %505
  %509 = fsub float -0.000000e+00, %506
  %510 = fmul float %54, %507
  %511 = fmul float %55, %508
  %512 = fadd float %511, %510
  %513 = fmul float %56, %509
  %514 = fadd float %512, %513
  %515 = fsub float -0.000000e+00, %62
  %516 = fadd float %514, %515
  %517 = fmul float %516, %63
  %518 = fmul float %12, %12
  %519 = fmul float %501, %503
  %520 = fmul float %501, %12
  %521 = fcmp uge float %517, 0x3F1A36E2E0000000
  %522 = select i1 %521, float %517, float 0x3F1A36E2E0000000
  %523 = fmul float %64, %518
  %524 = fmul float %65, %519
  %525 = fadd float %524, %523
  %526 = fmul float %66, %520
  %527 = fadd float %525, %526
  %528 = call float @llvm.pow.f32(float %522, float %61)
  %529 = fdiv float 1.000000e+00, %527
  %530 = fcmp uge float %528, %12
  %531 = select i1 %530, float %12, float %528
  %532 = fsub float -0.000000e+00, %529
  %533 = fmul float %529, %531
  %534 = fadd float %533, %532
  %535 = fmul float %57, %534
  %536 = fadd float %535, %529
  %537 = fsub float -0.000000e+00, %536
  %538 = fadd float %537, %12
  %539 = fmul float %53, %538
  %540 = fadd float %539, %536
  br label %ENDIF56

ENDIF56:                                          ; preds = %ENDIF, %IF57
  %temp33.0 = phi float [ %540, %IF57 ], [ %11, %ENDIF ]
  %541 = bitcast float %127 to i32
  %542 = icmp ne i32 %541, 0
  br i1 %542, label %IF60, label %ENDIF59

IF60:                                             ; preds = %ENDIF56
  %543 = fsub float -0.000000e+00, %421
  %544 = fadd float %543, %72
  %545 = fsub float -0.000000e+00, %428
  %546 = fadd float %545, %73
  %547 = fsub float -0.000000e+00, %412
  %548 = fadd float %547, %74
  %549 = fmul float %544, %544
  %550 = fmul float %546, %546
  %551 = fadd float %550, %549
  %552 = fmul float %548, %548
  %553 = fadd float %551, %552
  %554 = call float @fabs(float %553)
  %555 = call float @llvm.AMDGPU.rsq(float %554)
  %556 = fmul float %544, %555
  %557 = fmul float %546, %555
  %558 = fmul float %548, %555
  %559 = fsub float -0.000000e+00, %556
  %560 = fsub float -0.000000e+00, %557
  %561 = fsub float -0.000000e+00, %558
  %562 = fmul float %68, %559
  %563 = fmul float %69, %560
  %564 = fadd float %563, %562
  %565 = fmul float %70, %561
  %566 = fadd float %564, %565
  %567 = fsub float -0.000000e+00, %76
  %568 = fadd float %566, %567
  %569 = fmul float %568, %77
  %570 = fmul float %12, %12
  %571 = fmul float %553, %555
  %572 = fmul float %553, %12
  %573 = fcmp uge float %569, 0x3F1A36E2E0000000
  %574 = select i1 %573, float %569, float 0x3F1A36E2E0000000
  %575 = fmul float %78, %570
  %576 = fmul float %79, %571
  %577 = fadd float %576, %575
  %578 = fmul float %80, %572
  %579 = fadd float %577, %578
  %580 = call float @llvm.pow.f32(float %574, float %75)
  %581 = fdiv float 1.000000e+00, %579
  %582 = fcmp uge float %580, %12
  %583 = select i1 %582, float %12, float %580
  %584 = fsub float -0.000000e+00, %581
  %585 = fmul float %581, %583
  %586 = fadd float %585, %584
  %587 = fmul float %71, %586
  %588 = fadd float %587, %581
  %589 = fsub float -0.000000e+00, %588
  %590 = fadd float %589, %12
  %591 = fmul float %67, %590
  %592 = fadd float %591, %588
  br label %ENDIF59

ENDIF59:                                          ; preds = %ENDIF56, %IF60
  %temp34.0 = phi float [ %592, %IF60 ], [ %11, %ENDIF56 ]
  %593 = bitcast float %128 to i32
  %594 = icmp ne i32 %593, 0
  br i1 %594, label %IF63, label %ENDIF62

IF63:                                             ; preds = %ENDIF59
  %595 = fsub float -0.000000e+00, %421
  %596 = fadd float %595, %86
  %597 = fsub float -0.000000e+00, %428
  %598 = fadd float %597, %87
  %599 = fsub float -0.000000e+00, %412
  %600 = fadd float %599, %88
  %601 = fmul float %596, %596
  %602 = fmul float %598, %598
  %603 = fadd float %602, %601
  %604 = fmul float %600, %600
  %605 = fadd float %603, %604
  %606 = call float @fabs(float %605)
  %607 = call float @llvm.AMDGPU.rsq(float %606)
  %608 = fmul float %596, %607
  %609 = fmul float %598, %607
  %610 = fmul float %600, %607
  %611 = fsub float -0.000000e+00, %608
  %612 = fsub float -0.000000e+00, %609
  %613 = fsub float -0.000000e+00, %610
  %614 = fmul float %82, %611
  %615 = fmul float %83, %612
  %616 = fadd float %615, %614
  %617 = fmul float %84, %613
  %618 = fadd float %616, %617
  %619 = fsub float -0.000000e+00, %90
  %620 = fadd float %618, %619
  %621 = fmul float %620, %91
  %622 = fmul float %12, %12
  %623 = fmul float %605, %607
  %624 = fmul float %605, %12
  %625 = fcmp uge float %621, 0x3F1A36E2E0000000
  %626 = select i1 %625, float %621, float 0x3F1A36E2E0000000
  %627 = fmul float %92, %622
  %628 = fmul float %93, %623
  %629 = fadd float %628, %627
  %630 = fmul float %94, %624
  %631 = fadd float %629, %630
  %632 = call float @llvm.pow.f32(float %626, float %89)
  %633 = fdiv float 1.000000e+00, %631
  %634 = fcmp uge float %632, %12
  %635 = select i1 %634, float %12, float %632
  %636 = fsub float -0.000000e+00, %633
  %637 = fmul float %633, %635
  %638 = fadd float %637, %636
  %639 = fmul float %85, %638
  %640 = fadd float %639, %633
  %641 = fsub float -0.000000e+00, %640
  %642 = fadd float %641, %12
  %643 = fmul float %81, %642
  %644 = fadd float %643, %640
  br label %ENDIF62

ENDIF62:                                          ; preds = %ENDIF59, %IF63
  %temp20.0 = phi float [ %644, %IF63 ], [ %11, %ENDIF59 ]
  %645 = fmul float %421, %35
  %646 = fmul float %428, %36
  %647 = fadd float %645, %646
  %648 = fmul float %412, %37
  %649 = fadd float %647, %648
  %650 = fmul float %12, %38
  %651 = fadd float %649, %650
  %652 = fmul float %156, %18
  %653 = fmul float %421, %19
  %654 = fmul float %428, %20
  %655 = fadd float %653, %654
  %656 = fmul float %412, %21
  %657 = fadd float %655, %656
  %658 = fmul float %12, %22
  %659 = fadd float %657, %658
  %660 = fmul float %421, %23
  %661 = fmul float %428, %24
  %662 = fadd float %660, %661
  %663 = fmul float %412, %25
  %664 = fadd float %662, %663
  %665 = fmul float %12, %26
  %666 = fadd float %664, %665
  %667 = fmul float %421, %27
  %668 = fmul float %428, %28
  %669 = fadd float %667, %668
  %670 = fmul float %412, %29
  %671 = fadd float %669, %670
  %672 = fmul float %12, %30
  %673 = fadd float %671, %672
  %674 = fmul float %421, %31
  %675 = fmul float %428, %32
  %676 = fadd float %674, %675
  %677 = fmul float %412, %33
  %678 = fadd float %676, %677
  %679 = fmul float %12, %34
  %680 = fadd float %678, %679
  %681 = fmul float %146, %95
  %682 = fmul float %147, %96
  %683 = fadd float %681, %682
  %684 = fmul float %148, %97
  %685 = fadd float %683, %684
  %686 = fmul float %149, %98
  %687 = fadd float %685, %686
  %688 = fmul float %146, %99
  %689 = fmul float %147, %100
  %690 = fadd float %688, %689
  %691 = fmul float %148, %101
  %692 = fadd float %690, %691
  %693 = fmul float %149, %102
  %694 = fadd float %692, %693
  %695 = fmul float %146, %103
  %696 = fmul float %147, %104
  %697 = fadd float %695, %696
  %698 = fmul float %148, %105
  %699 = fadd float %697, %698
  %700 = fmul float %149, %106
  %701 = fadd float %699, %700
  %702 = fmul float %146, %107
  %703 = fmul float %147, %108
  %704 = fadd float %702, %703
  %705 = fmul float %148, %109
  %706 = fadd float %704, %705
  %707 = fmul float %149, %110
  %708 = fadd float %706, %707
  %709 = fsub float -0.000000e+00, %680
  %710 = fmul float %673, %13
  %711 = fadd float %710, %709
  %712 = fsub float -0.000000e+00, %666
  %713 = fmul float %123, %680
  %714 = fadd float %713, %659
  %715 = fmul float %124, %680
  %716 = fadd float %715, %712
  %717 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
  %718 = load <16 x i8> addrspace(2)* %717, !tbaa !0
  %719 = call float @llvm.SI.load.const(<16 x i8> %718, i32 0)
  %720 = fmul float %719, %659
  %721 = call float @llvm.SI.load.const(<16 x i8> %718, i32 4)
  %722 = fmul float %721, %666
  %723 = fadd float %720, %722
  %724 = call float @llvm.SI.load.const(<16 x i8> %718, i32 8)
  %725 = fmul float %724, %673
  %726 = fadd float %723, %725
  %727 = call float @llvm.SI.load.const(<16 x i8> %718, i32 12)
  %728 = fmul float %727, %680
  %729 = fadd float %726, %728
  %730 = call float @llvm.SI.load.const(<16 x i8> %718, i32 16)
  %731 = fmul float %730, %659
  %732 = call float @llvm.SI.load.const(<16 x i8> %718, i32 20)
  %733 = fmul float %732, %666
  %734 = fadd float %731, %733
  %735 = call float @llvm.SI.load.const(<16 x i8> %718, i32 24)
  %736 = fmul float %735, %673
  %737 = fadd float %734, %736
  %738 = call float @llvm.SI.load.const(<16 x i8> %718, i32 28)
  %739 = fmul float %738, %680
  %740 = fadd float %737, %739
  %741 = call float @llvm.SI.load.const(<16 x i8> %718, i32 32)
  %742 = fmul float %741, %659
  %743 = call float @llvm.SI.load.const(<16 x i8> %718, i32 36)
  %744 = fmul float %743, %666
  %745 = fadd float %742, %744
  %746 = call float @llvm.SI.load.const(<16 x i8> %718, i32 40)
  %747 = fmul float %746, %673
  %748 = fadd float %745, %747
  %749 = call float @llvm.SI.load.const(<16 x i8> %718, i32 44)
  %750 = fmul float %749, %680
  %751 = fadd float %748, %750
  %752 = call float @llvm.SI.load.const(<16 x i8> %718, i32 48)
  %753 = fmul float %752, %659
  %754 = call float @llvm.SI.load.const(<16 x i8> %718, i32 52)
  %755 = fmul float %754, %666
  %756 = fadd float %753, %755
  %757 = call float @llvm.SI.load.const(<16 x i8> %718, i32 56)
  %758 = fmul float %757, %673
  %759 = fadd float %756, %758
  %760 = call float @llvm.SI.load.const(<16 x i8> %718, i32 60)
  %761 = fmul float %760, %680
  %762 = fadd float %759, %761
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %729, float %740, float %751, float %762)
  %763 = call float @llvm.SI.load.const(<16 x i8> %718, i32 64)
  %764 = fmul float %763, %659
  %765 = call float @llvm.SI.load.const(<16 x i8> %718, i32 68)
  %766 = fmul float %765, %666
  %767 = fadd float %764, %766
  %768 = call float @llvm.SI.load.const(<16 x i8> %718, i32 72)
  %769 = fmul float %768, %673
  %770 = fadd float %767, %769
  %771 = call float @llvm.SI.load.const(<16 x i8> %718, i32 76)
  %772 = fmul float %771, %680
  %773 = fadd float %770, %772
  %774 = call float @llvm.SI.load.const(<16 x i8> %718, i32 80)
  %775 = fmul float %774, %659
  %776 = call float @llvm.SI.load.const(<16 x i8> %718, i32 84)
  %777 = fmul float %776, %666
  %778 = fadd float %775, %777
  %779 = call float @llvm.SI.load.const(<16 x i8> %718, i32 88)
  %780 = fmul float %779, %673
  %781 = fadd float %778, %780
  %782 = call float @llvm.SI.load.const(<16 x i8> %718, i32 92)
  %783 = fmul float %782, %680
  %784 = fadd float %781, %783
  %785 = call float @llvm.SI.load.const(<16 x i8> %718, i32 96)
  %786 = fmul float %785, %659
  %787 = call float @llvm.SI.load.const(<16 x i8> %718, i32 100)
  %788 = fmul float %787, %666
  %789 = fadd float %786, %788
  %790 = call float @llvm.SI.load.const(<16 x i8> %718, i32 104)
  %791 = fmul float %790, %673
  %792 = fadd float %789, %791
  %793 = call float @llvm.SI.load.const(<16 x i8> %718, i32 108)
  %794 = fmul float %793, %680
  %795 = fadd float %792, %794
  %796 = call float @llvm.SI.load.const(<16 x i8> %718, i32 112)
  %797 = fmul float %796, %659
  %798 = call float @llvm.SI.load.const(<16 x i8> %718, i32 116)
  %799 = fmul float %798, %666
  %800 = fadd float %797, %799
  %801 = call float @llvm.SI.load.const(<16 x i8> %718, i32 120)
  %802 = fmul float %801, %673
  %803 = fadd float %800, %802
  %804 = call float @llvm.SI.load.const(<16 x i8> %718, i32 124)
  %805 = fmul float %804, %680
  %806 = fadd float %803, %805
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %773, float %784, float %795, float %806)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %687, float %694, float %701, float %708)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %temp32.0, float %temp33.0, float %temp34.0, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %433, float %435, float %437, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %380, float %381, float %382, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %429, float %430, float %431, float %198)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %367, float %368, float %369, float %277)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %421, float %428, float %412, float %temp20.0)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %659, float %666, float %651, float %652)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %714, float %716, float %711, float %680)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #3

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #4

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { readnone }
attributes #4 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
hl2_linux: AMDGPUInstrInfo.cpp:109: virtual void llvm::AMDGPUInstrInfo::storeRegToStackSlot(llvm::MachineBasicBlock&, llvm::MachineBasicBlock::iterator, unsigned int, bool, int, const llvm::TargetRegisterClass*, const llvm::TargetRegisterInfo*) const: Assertion `!"Not Implemented"' failed.
ALSA lib pcm.c:7339:(snd_pcm_recover) underrun occurred
Uploading dump (out-of-process) [proxy '']
/tmp/dumps/assert_20130711115051_1.dmp
Finished uploading minidump (out-of-process): success = yes
response: CrashID=bp-3eb4d3d0-1349-46c2-952e-308202130711