FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%16](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%16](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%16](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
SDL video target is 'x11'
SDL video target is 'x11'
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%16](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
SDL failed to create GL compatibility profile (whichProfile=0)!
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %21 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %22 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %23 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	EXP 15, 0, 0, 1, 1, %VGPR5<kill>, %VGPR4<kill>, %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8080300
c8090301
c80c0200
c80d0201
c8100100
c8110101
c8140000
c8150001
f800180f
02030405
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 3
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 4
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 5
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 6
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 7
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 8
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 9
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 10
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 11
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 12
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 13
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 14
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 15
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
  %53 = extractelement <4 x float> %52, i32 0
  %54 = extractelement <4 x float> %52, i32 1
  %55 = extractelement <4 x float> %52, i32 2
  %56 = extractelement <4 x float> %52, i32 3
  %57 = fmul float %46, %12
  %58 = fmul float %46, %14
  %59 = fmul float %46, %16
  %60 = fmul float %46, %18
  %61 = fmul float %47, %20
  %62 = fadd float %61, %57
  %63 = fmul float %47, %22
  %64 = fadd float %63, %58
  %65 = fmul float %47, %24
  %66 = fadd float %65, %59
  %67 = fmul float %47, %26
  %68 = fadd float %67, %60
  %69 = fmul float %48, %28
  %70 = fadd float %69, %62
  %71 = fmul float %48, %30
  %72 = fadd float %71, %64
  %73 = fmul float %48, %32
  %74 = fadd float %73, %66
  %75 = fmul float %48, %34
  %76 = fadd float %75, %68
  %77 = fmul float %49, %36
  %78 = fadd float %77, %70
  %79 = fmul float %49, %38
  %80 = fadd float %79, %72
  %81 = fmul float %49, %40
  %82 = fadd float %81, %74
  %83 = fmul float %49, %42
  %84 = fadd float %83, %76
  %85 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00)
  %86 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
  %87 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
  %88 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %85, float %86, float %87, float %88)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %78, float %80, float %82, float %84)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%50](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_ADD_F32_e64 %VGPR4, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 %VGPR3, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR2, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 %VGPR1, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%43](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 12; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0820700
bf8c000f
e00c2000
80010000
c0400100
bf8c0070
c0010103
bf8c007f
10080002
c0010107
bf8c007f
d2820004
04100501
c001010b
bf8c007f
d2820004
04100502
c001010f
bf8c007f
d2820004
04100503
c0010102
bf8c007f
100a0002
c0010106
bf8c007f
d2820005
04140501
c001010a
bf8c007f
d2820005
04140502
c001010e
bf8c007f
d2820005
04140503
c0010101
bf8c007f
100c0002
c0010105
bf8c007f
d2820006
04180501
c0010109
bf8c007f
d2820006
04180502
c001010d
bf8c007f
d2820006
04180503
c0010100
bf8c007f
100e0002
c0010104
bf8c007f
d2820007
041c0501
c0010108
bf8c007f
d2820007
041c0502
c000010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
  %25 = bitcast i32 %24 to float
  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
  %27 = bitcast i32 %26 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
5e000101
c8060102
c80a0002
5e020302
f8001c0f
00010001
bf810000
Using breakpad crash handler
Setting breakpad minidump AppID = 400
Forcing breakpad minidump interfaces to load
Looking up breakpad interfaces from steamclient
Calling BreakpadMiniDumpSystemInit
Looking up breakpad interfaces from steamclient
Calling BreakpadMiniDumpSystemInit
Steam_SetMinidumpSteamID:  Caching Steam ID:  76561197992653503 [API loaded yes]
Steam_SetMinidumpSteamID:  Setting Steam ID:  76561197992653503
Did not detect any valid joysticks.
[0720/085109:ERROR:resource_bundle.cc(411)] Failed to load /home/lordh/.local/share/Steam/SteamApps/common/Portal/cef_gtk.pak
Some features may not be available.
[0720/085109:WARNING:proxy_service.cc(646)] PAC support disabled because there is no system implementation
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
  %36 = bitcast i32 %35 to float
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
  %36 = bitcast i32 %35 to float
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MOV OUT[0], TEMP[0]
  3: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
  %36 = bitcast i32 %35 to float
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..3]
DCL TEMP[0], LOCAL
IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
  0: MUL TEMP[0], CONST[0], IN[0].xxxx
  1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0]
  2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0]
  3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0]
  4: MOV OUT[1], IMM[0].xxxx
  5: MOV OUT[0], TEMP[0]
  6: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 3
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 4
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 5
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 6
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 7
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 8
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 9
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 10
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 11
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 12
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 13
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 14
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 15
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = fmul float %12, %46
  %51 = fmul float %14, %46
  %52 = fmul float %16, %46
  %53 = fmul float %18, %46
  %54 = fmul float %20, %47
  %55 = fadd float %54, %50
  %56 = fmul float %22, %47
  %57 = fadd float %56, %51
  %58 = fmul float %24, %47
  %59 = fadd float %58, %52
  %60 = fmul float %26, %47
  %61 = fadd float %60, %53
  %62 = fmul float %28, %48
  %63 = fadd float %62, %55
  %64 = fmul float %30, %48
  %65 = fadd float %64, %57
  %66 = fmul float %32, %48
  %67 = fadd float %66, %59
  %68 = fmul float %34, %48
  %69 = fadd float %68, %61
  %70 = fmul float %36, %49
  %71 = fadd float %70, %63
  %72 = fmul float %38, %49
  %73 = fadd float %72, %65
  %74 = fmul float %40, %49
  %75 = fadd float %74, %67
  %76 = fmul float %42, %49
  %77 = fadd float %76, %69
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %71, float %73, float %75, float %77)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%VGPR1<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR1, %VGPR1, %VGPR1, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%43](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR2<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR2<kill>, %VGPR2, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR2<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR2<kill>, %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR2<kill>, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR2<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR2<kill>, %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR2<kill>, %VGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR2<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR2<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR2<kill>, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 12; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e020280
f800020f
01010101
c0820700
bf8c000f
e00c2000
80010000
c0400100
bf8c0070
c0010103
bf8c007f
10080002
c0010107
bf8c007f
d2820004
04120202
c001010b
bf8c007f
d2820004
04120402
c001010f
bf8c007f
d2820004
04120602
c0010102
bf8c007f
100a0002
c0010106
bf8c007f
d2820005
04160202
c001010a
bf8c007f
d2820005
04160402
c001010e
bf8c007f
d2820005
04160602
c0010101
bf8c007f
100c0002
c0010105
bf8c007f
d2820006
041a0202
c0010109
bf8c007f
d2820006
041a0402
c001010d
bf8c007f
d2820006
041a0602
c0010100
bf8c007f
100e0002
c0010104
bf8c007f
d2820007
041e0202
c0010108
bf8c007f
d2820007
041e0402
c000010c
bf8c007f
d2820000
041e0600
f80008cf
04050600
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], CUBE
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %9)
  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %9)
  %28 = insertelement <4 x float> undef, float %24, i32 0
  %29 = insertelement <4 x float> %28, float %25, i32 1
  %30 = insertelement <4 x float> %29, float %26, i32 2
  %31 = insertelement <4 x float> %30, float %27, i32 3
  %32 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %31)
  %33 = extractelement <4 x float> %32, i32 0
  %34 = extractelement <4 x float> %32, i32 1
  %35 = extractelement <4 x float> %32, i32 2
  %36 = extractelement <4 x float> %32, i32 3
  %37 = call float @fabs(float %35)
  %38 = fdiv float 1.000000e+00, %37
  %39 = fmul float %33, %38
  %40 = fadd float %39, 1.500000e+00
  %41 = fmul float %34, %38
  %42 = fadd float %41, 1.500000e+00
  %43 = bitcast float %42 to i32
  %44 = bitcast float %40 to i32
  %45 = bitcast float %36 to i32
  %46 = insertelement <4 x i32> undef, i32 %43, i32 0
  %47 = insertelement <4 x i32> %46, i32 %44, i32 1
  %48 = insertelement <4 x i32> %47, i32 %45, i32 2
  %49 = insertelement <4 x i32> %48, i32 undef, i32 3
  %50 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %49, <32 x i8> %21, <16 x i8> %23, i32 4)
  %51 = extractelement <4 x float> %50, i32 0
  %52 = extractelement <4 x float> %50, i32 1
  %53 = extractelement <4 x float> %50, i32 2
  %54 = extractelement <4 x float> %50, i32 3
  %55 = call i32 @llvm.SI.packf16(float %51, float %52)
  %56 = bitcast i32 %55 to float
  %57 = call i32 @llvm.SI.packf16(float %53, float %54)
  %58 = bitcast i32 %57 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %56, float %58, float %56, float %58)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR7<def> = V_CUBESC_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR6<def> = V_CUBETC_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR8<def> = V_CUBEMA_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR9<def> = V_CUBEID_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR8, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_RCP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR6, %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR7<def> = V_MAD_F32 %VGPR7, %VGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR10<def> = KILL %VGPR10<undef>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8_VGPR9_VGPR10, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c8100200
c8110201
c8140300
c8150301
d28a0007
04120702
d28c0006
04120702
d28e0008
04120702
d2880009
04120702
d2060100
02010108
7e005500
7e0202ff
3fc00000
d2820008
04060106
d2820007
04060107
c0800300
c0c20500
bf8c007f
f0800f00
00010007
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], CUBE
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %9)
  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %9)
  %28 = insertelement <4 x float> undef, float %24, i32 0
  %29 = insertelement <4 x float> %28, float %25, i32 1
  %30 = insertelement <4 x float> %29, float %26, i32 2
  %31 = insertelement <4 x float> %30, float %27, i32 3
  %32 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %31)
  %33 = extractelement <4 x float> %32, i32 0
  %34 = extractelement <4 x float> %32, i32 1
  %35 = extractelement <4 x float> %32, i32 2
  %36 = extractelement <4 x float> %32, i32 3
  %37 = call float @fabs(float %35)
  %38 = fdiv float 1.000000e+00, %37
  %39 = fmul float %33, %38
  %40 = fadd float %39, 1.500000e+00
  %41 = fmul float %34, %38
  %42 = fadd float %41, 1.500000e+00
  %43 = bitcast float %42 to i32
  %44 = bitcast float %40 to i32
  %45 = bitcast float %36 to i32
  %46 = insertelement <4 x i32> undef, i32 %43, i32 0
  %47 = insertelement <4 x i32> %46, i32 %44, i32 1
  %48 = insertelement <4 x i32> %47, i32 %45, i32 2
  %49 = insertelement <4 x i32> %48, i32 undef, i32 3
  %50 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %49, <32 x i8> %21, <16 x i8> %23, i32 4)
  %51 = extractelement <4 x float> %50, i32 0
  %52 = extractelement <4 x float> %50, i32 1
  %53 = extractelement <4 x float> %50, i32 2
  %54 = extractelement <4 x float> %50, i32 3
  %55 = call i32 @llvm.SI.packf16(float %51, float %52)
  %56 = bitcast i32 %55 to float
  %57 = call i32 @llvm.SI.packf16(float %53, float %54)
  %58 = bitcast i32 %57 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %56, float %58, float %56, float %58)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR7<def> = V_CUBESC_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR6<def> = V_CUBETC_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR8<def> = V_CUBEMA_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR9<def> = V_CUBEID_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR8, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_RCP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR6, %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR7<def> = V_MAD_F32 %VGPR7, %VGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR10<def> = KILL %VGPR10<undef>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8_VGPR9_VGPR10, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c8100200
c8110201
c8140300
c8150301
d28a0007
04120702
d28c0006
04120702
d28e0008
04120702
d2880009
04120702
d2060100
02010108
7e005500
7e0202ff
3fc00000
d2820008
04060106
d2820007
04060107
c0800300
c0c20500
bf8c007f
f0800f00
00010007
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xyz, IN[0].xyzz
  1: TEX TEMP[0], TEMP[0], SAMP[0], CUBE
  2: MOV OUT[0], TEMP[0]
  3: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %27 = insertelement <4 x float> undef, float %24, i32 0
  %28 = insertelement <4 x float> %27, float %25, i32 1
  %29 = insertelement <4 x float> %28, float %26, i32 2
  %30 = insertelement <4 x float> %29, float 0.000000e+00, i32 3
  %31 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %30)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = extractelement <4 x float> %31, i32 3
  %36 = call float @fabs(float %34)
  %37 = fdiv float 1.000000e+00, %36
  %38 = fmul float %32, %37
  %39 = fadd float %38, 1.500000e+00
  %40 = fmul float %33, %37
  %41 = fadd float %40, 1.500000e+00
  %42 = bitcast float %41 to i32
  %43 = bitcast float %39 to i32
  %44 = bitcast float %35 to i32
  %45 = insertelement <4 x i32> undef, i32 %42, i32 0
  %46 = insertelement <4 x i32> %45, i32 %43, i32 1
  %47 = insertelement <4 x i32> %46, i32 %44, i32 2
  %48 = insertelement <4 x i32> %47, i32 undef, i32 3
  %49 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %48, <32 x i8> %21, <16 x i8> %23, i32 4)
  %50 = extractelement <4 x float> %49, i32 0
  %51 = extractelement <4 x float> %49, i32 1
  %52 = extractelement <4 x float> %49, i32 2
  %53 = extractelement <4 x float> %49, i32 3
  %54 = call i32 @llvm.SI.packf16(float %50, float %51)
  %55 = bitcast i32 %54 to float
  %56 = call i32 @llvm.SI.packf16(float %52, float %53)
  %57 = bitcast i32 %56 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %55, float %57, float %55, float %57)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR7<def> = V_CUBESC_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR6<def> = V_CUBETC_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR8<def> = V_CUBEMA_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR9<def> = V_CUBEID_F32 %VGPR2, %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR8, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_RCP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR6, %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR7<def> = V_MAD_F32 %VGPR7, %VGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%VGPR10<def> = KILL %VGPR10<undef>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8_VGPR9_VGPR10, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c8100200
c8110201
7e0a0280
d28a0007
04120702
d28c0006
04120702
d28e0008
04120702
d2880009
04120702
d2060100
02010108
7e005500
7e0202ff
3fc00000
d2820008
04060106
d2820007
04060107
c0800300
c0c20500
bf8c007f
f0800f00
00010007
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..3]
DCL TEMP[0], LOCAL
IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
  0: MUL TEMP[0], CONST[0], IN[0].xxxx
  1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0]
  2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0]
  3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0]
  4: MOV OUT[1], IMM[0].xxxx
  5: MOV OUT[0], TEMP[0]
  6: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 3
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 4
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 5
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 6
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 7
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 8
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 9
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 10
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 11
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 12
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 13
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 14
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 15
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = fmul float %12, %46
  %51 = fmul float %14, %46
  %52 = fmul float %16, %46
  %53 = fmul float %18, %46
  %54 = fmul float %20, %47
  %55 = fadd float %54, %50
  %56 = fmul float %22, %47
  %57 = fadd float %56, %51
  %58 = fmul float %24, %47
  %59 = fadd float %58, %52
  %60 = fmul float %26, %47
  %61 = fadd float %60, %53
  %62 = fmul float %28, %48
  %63 = fadd float %62, %55
  %64 = fmul float %30, %48
  %65 = fadd float %64, %57
  %66 = fmul float %32, %48
  %67 = fadd float %66, %59
  %68 = fmul float %34, %48
  %69 = fadd float %68, %61
  %70 = fmul float %36, %49
  %71 = fadd float %70, %63
  %72 = fmul float %38, %49
  %73 = fadd float %72, %65
  %74 = fmul float %40, %49
  %75 = fadd float %74, %67
  %76 = fmul float %42, %49
  %77 = fadd float %76, %69
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %71, float %73, float %75, float %77)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%VGPR1<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR1, %VGPR1, %VGPR1, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%43](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR2<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR2<kill>, %VGPR2, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR2<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR2<kill>, %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR2<kill>, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR2<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR2<kill>, %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR2<kill>, %VGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR2<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR2<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR2<kill>, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 12; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e020280
f800020f
01010101
c0820700
bf8c000f
e00c2000
80010000
c0400100
bf8c0070
c0010103
bf8c007f
10080002
c0010107
bf8c007f
d2820004
04120202
c001010b
bf8c007f
d2820004
04120402
c001010f
bf8c007f
d2820004
04120602
c0010102
bf8c007f
100a0002
c0010106
bf8c007f
d2820005
04160202
c001010a
bf8c007f
d2820005
04160402
c001010e
bf8c007f
d2820005
04160602
c0010101
bf8c007f
100c0002
c0010105
bf8c007f
d2820006
041a0202
c0010109
bf8c007f
d2820006
041a0402
c001010d
bf8c007f
d2820006
041a0602
c0010100
bf8c007f
100e0002
c0010104
bf8c007f
d2820007
041e0202
c0010108
bf8c007f
d2820007
041e0402
c000010c
bf8c007f
d2820000
041e0600
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL OUT[0], COLOR
DCL CONST[0..3]
  0: MOV OUT[0], CONST[3]
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 12
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 13
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 14
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 15
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = call i32 @llvm.SI.packf16(float %23, float %25)
  %31 = bitcast i32 %30 to float
  %32 = call i32 @llvm.SI.packf16(float %27, float %29)
  %33 = bitcast i32 %32 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %31, float %33, float %31, float %33)
  ret void
}

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%26]
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR0<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 %SGPR2<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%22]
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 13; mem:LD4[%24]
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0400100
bf8c007f
c001010e
c001810f
bf8c007f
7e000203
d25e0000
02020002
c001010c
c000010d
bf8c007f
7e020200
d25e0001
02020202
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 3
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 4
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 5
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 6
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 7
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 8
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 9
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 10
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 11
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 12
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 13
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 14
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 15
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = fmul float %46, %12
  %51 = fmul float %46, %14
  %52 = fmul float %46, %16
  %53 = fmul float %46, %18
  %54 = fmul float %47, %20
  %55 = fadd float %54, %50
  %56 = fmul float %47, %22
  %57 = fadd float %56, %51
  %58 = fmul float %47, %24
  %59 = fadd float %58, %52
  %60 = fmul float %47, %26
  %61 = fadd float %60, %53
  %62 = fmul float %48, %28
  %63 = fadd float %62, %55
  %64 = fmul float %48, %30
  %65 = fadd float %64, %57
  %66 = fmul float %48, %32
  %67 = fadd float %66, %59
  %68 = fmul float %48, %34
  %69 = fadd float %68, %61
  %70 = fmul float %49, %36
  %71 = fadd float %70, %63
  %72 = fmul float %49, %38
  %73 = fadd float %72, %65
  %74 = fmul float %49, %40
  %75 = fadd float %74, %67
  %76 = fmul float %49, %42
  %77 = fadd float %76, %69
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %71, float %73, float %75, float %77)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%43](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 12; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0820700
bf8c007f
e00c2000
80010000
c0400100
bf8c0070
c0010103
bf8c007f
10080002
c0010107
bf8c007f
d2820004
04100501
c001010b
bf8c007f
d2820004
04100502
c001010f
bf8c007f
d2820004
04100503
c0010102
bf8c007f
100a0002
c0010106
bf8c007f
d2820005
04140501
c001010a
bf8c007f
d2820005
04140502
c001010e
bf8c007f
d2820005
04140503
c0010101
bf8c007f
100c0002
c0010105
bf8c007f
d2820006
04180501
c0010109
bf8c007f
d2820006
04180502
c001010d
bf8c007f
d2820006
04180503
c0010100
bf8c007f
100e0002
c0010104
bf8c007f
d2820007
041c0501
c0010108
bf8c007f
d2820007
041c0502
c000010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..29]
DCL TEMP[0..3], LOCAL
DCL TEMP[4], ARRAY(1), LOCAL
IMM[0] FLT32 {    1.0000,     1.1641,     0.0000,     2.0178}
IMM[1] FLT32 {    1.1641,     1.5958,     0.0000,    -0.8707}
IMM[2] FLT32 {    1.1641,    -0.8135,    -0.3914,     0.5297}
IMM[3] FLT32 {    1.1641,     0.0000,     2.0178,    -1.0817}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0].x, TEMP[0], SAMP[0], 2D
  2: MOV TEMP[0].x, TEMP[0].xxxx
  3: MOV TEMP[1].xy, IN[0].xyyy
  4: TEX TEMP[1].x, TEMP[1], SAMP[1], 2D
  5: MOV TEMP[2].xy, IN[0].xyyy
  6: TEX TEMP[2].x, TEMP[2], SAMP[2], 2D
  7: MOV TEMP[0].y, TEMP[1].xxxx
  8: MOV TEMP[0].z, TEMP[2].xxxx
  9: MOV TEMP[0].w, IMM[0].xxxx
 10: MAD TEMP[2].x, IN[1].wwww, CONST[12].wwww, -CONST[12].xxxx
 11: DP4 TEMP[1].x, TEMP[0], IMM[1]
 12: MIN TEMP[2].x, TEMP[2].xxxx, CONST[12].zzzz
 13: MOV_SAT TEMP[2].x, TEMP[2].xxxx
 14: DP4 TEMP[3].x, TEMP[0], IMM[2]
 15: MOV TEMP[1].y, TEMP[3].xxxx
 16: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
 17: DP4 TEMP[3].x, TEMP[0], IMM[3]
 18: MOV TEMP[1].z, TEMP[3].xxxx
 19: ADD TEMP[3].xyz, CONST[29].xyzz, -TEMP[1].xyzz
 20: MAD TEMP[0].xyz, TEMP[2].xxxx, TEMP[3].xyzz, TEMP[1].xyzz
 21: MOV TEMP[0].w, IMM[0].xxxx
 22: MOV TEMP[4], TEMP[0]
 23: MOV OUT[0], TEMP[4]
 24: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 48
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 50
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 51
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 116
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 117
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 118
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %35 = load <32 x i8> addrspace(2)* %34, !tbaa !0
  %36 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
  %38 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %39 = load <32 x i8> addrspace(2)* %38, !tbaa !0
  %40 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %41 = load <16 x i8> addrspace(2)* %40, !tbaa !0
  %42 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %43 = load <32 x i8> addrspace(2)* %42, !tbaa !0
  %44 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %45 = load <16 x i8> addrspace(2)* %44, !tbaa !0
  %46 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %47 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %48 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %49 = bitcast float %46 to i32
  %50 = bitcast float %47 to i32
  %51 = insertelement <2 x i32> undef, i32 %49, i32 0
  %52 = insertelement <2 x i32> %51, i32 %50, i32 1
  %53 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %52, <32 x i8> %35, <16 x i8> %37, i32 2)
  %54 = extractelement <4 x float> %53, i32 0
  %55 = bitcast float %46 to i32
  %56 = bitcast float %47 to i32
  %57 = insertelement <2 x i32> undef, i32 %55, i32 0
  %58 = insertelement <2 x i32> %57, i32 %56, i32 1
  %59 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %58, <32 x i8> %39, <16 x i8> %41, i32 2)
  %60 = extractelement <4 x float> %59, i32 0
  %61 = bitcast float %46 to i32
  %62 = bitcast float %47 to i32
  %63 = insertelement <2 x i32> undef, i32 %61, i32 0
  %64 = insertelement <2 x i32> %63, i32 %62, i32 1
  %65 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %64, <32 x i8> %43, <16 x i8> %45, i32 2)
  %66 = extractelement <4 x float> %65, i32 0
  %67 = fsub float -0.000000e+00, %23
  %68 = fmul float %48, %27
  %69 = fadd float %68, %67
  %70 = fmul float %54, 0x3FF2A04000000000
  %71 = fmul float %60, 0x3FF9886000000000
  %72 = fadd float %70, %71
  %73 = fmul float %66, 0.000000e+00
  %74 = fadd float %72, %73
  %75 = fmul float 1.000000e+00, 0xBFEBDC6800000000
  %76 = fadd float %74, %75
  %77 = fcmp uge float %69, %25
  %78 = select i1 %77, float %25, float %69
  %79 = call float @llvm.AMDIL.clamp.(float %78, float 0.000000e+00, float 1.000000e+00)
  %80 = fmul float %54, 0x3FF2A04000000000
  %81 = fmul float %60, 0xBFEA080000000000
  %82 = fadd float %80, %81
  %83 = fmul float %66, 0xBFD90D8000000000
  %84 = fadd float %82, %83
  %85 = fmul float 1.000000e+00, 0x3FE0F35800000000
  %86 = fadd float %84, %85
  %87 = fmul float %79, %79
  %88 = fmul float %54, 0x3FF2A04000000000
  %89 = fmul float %60, 0.000000e+00
  %90 = fadd float %88, %89
  %91 = fmul float %66, 0x4000248000000000
  %92 = fadd float %90, %91
  %93 = fmul float 1.000000e+00, 0xBFF14E8400000000
  %94 = fadd float %92, %93
  %95 = fsub float -0.000000e+00, %76
  %96 = fadd float %29, %95
  %97 = fsub float -0.000000e+00, %86
  %98 = fadd float %31, %97
  %99 = fsub float -0.000000e+00, %94
  %100 = fadd float %33, %99
  %101 = fmul float %87, %96
  %102 = fadd float %101, %76
  %103 = fmul float %87, %98
  %104 = fadd float %103, %86
  %105 = fmul float %87, %100
  %106 = fadd float %105, %94
  %107 = call i32 @llvm.SI.packf16(float %102, float %104)
  %108 = bitcast i32 %107 to float
  %109 = call i32 @llvm.SI.packf16(float %106, float 1.000000e+00)
  %110 = bitcast i32 %109 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %108, float %110, float %108, float %110)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%36](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%34](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2<def> = IMAGE_SAMPLE 1, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%40](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%38](tbaa=!"const")
	S_WAITCNT 112
	%VGPR3<def> = IMAGE_SAMPLE 1, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR7<def> = V_MUL_F32_e32 -8.134766e-01, %VGPR3, %EXEC<imp-use>
	%VGPR4<def> = V_MOV_B32_e32 1.164124e+00, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 8; mem:LD16[%44](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 16; mem:LD32[%42](tbaa=!"const")
	S_WAITCNT 127
	%VGPR5<def> = IMAGE_SAMPLE 1, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 -3.914490e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_MAD_F32 %VGPR5, %VGPR6<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 5.297050e-01, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%30]
	S_WAITCNT 127
	%VGPR7<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 51; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR2<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%24]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR0, %SGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR0, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 1.595795e+00, %VGPR3, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR5, 0.000000e+00, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 -8.706551e-01, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 116; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR7<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR0, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR6<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 0.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %VGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 2.017822e+00, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR5<kill>, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e32 -1.081669e+00, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 118; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR3<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 %VGPR0<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8180100
c8190101
c8140000
c8150001
c0840300
c0c60500
bf8c007f
f0800100
00430205
c0840304
c0c60508
bf8c0070
f0800100
00430305
bf8c0770
100e06ff
bf504000
7e0802ff
3f950200
d2820007
041e0902
c0840308
c0c60510
bf8c007f
f0800100
00430505
7e0c02ff
bec86c00
bf8c0770
d2820006
041e0d05
060c0cff
3f079ac0
c0400100
bf8c007f
c0010175
bf8c007f
080e0c02
c8200700
c8210701
c0010133
bf8c007f
10001002
c0010130
bf8c007f
0a000002
c0010132
bf8c007f
d00c0004
02000500
7e020202
d2000000
00120300
d2060800
02010100
10000100
d2820001
041a0f00
100c06ff
3fcc4300
d2820006
041a0902
d2820006
04190105
060c0cff
bf5ee340
c0010174
bf8c007f
080e0c02
d2820006
041a0f00
5e020306
10060680
d2820002
040e0902
7e0602ff
40012400
d2820002
040a0705
060404ff
bf8a7420
c0000176
bf8c007f
08060400
d2820000
040a0700
d25e0000
0201e500
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL CONST[0..20]
DCL TEMP[0..6], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[4]
  2: DP4 TEMP[2].x, TEMP[0], CONST[5]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[3].x, TEMP[0], CONST[17]
  5: DP4 TEMP[4].x, TEMP[0], CONST[18]
  6: MOV TEMP[3].y, TEMP[4].xxxx
  7: DP4 TEMP[4].x, TEMP[0], CONST[19]
  8: MOV TEMP[3].z, TEMP[4].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[7]
 10: MOV TEMP[5].w, TEMP[4].xxxx
 11: DP4 TEMP[0].x, TEMP[0], CONST[6]
 12: MOV TEMP[5].z, TEMP[0].xxxx
 13: MOV TEMP[1].zw, TEMP[5].wwzw
 14: MOV TEMP[3].w, TEMP[0].xxxx
 15: MOV TEMP[5].xy, IN[1].xyxx
 16: MOV TEMP[6], TEMP[1]
 17: MAD TEMP[0].x, TEMP[0].xxxx, CONST[0].zzzz, -TEMP[4].xxxx
 18: MOV TEMP[1].z, TEMP[0].xxxx
 19: MOV TEMP[1].y, -TEMP[2].xxxx
 20: MAD TEMP[1].xy, CONST[20].xyyy, TEMP[4].xxxx, TEMP[1].xyyy
 21: MOV OUT[2], TEMP[5]
 22: MOV OUT[3], TEMP[3]
 23: MOV OUT[0], TEMP[1]
 24: MOV OUT[1], TEMP[6]
 25: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 16
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 17
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 18
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 19
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 20
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 21
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 22
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 23
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 24
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 25
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 26
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 27
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 28
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 29
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 30
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 31
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 68
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 69
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 70
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 71
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 72
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 73
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 74
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 75
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 76
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 77
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 78
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 79
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 80
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 81
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %78 = load <16 x i8> addrspace(2)* %77, !tbaa !0
  %79 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %78, i32 0, i32 %5)
  %80 = extractelement <4 x float> %79, i32 0
  %81 = extractelement <4 x float> %79, i32 1
  %82 = extractelement <4 x float> %79, i32 2
  %83 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %84 = load <16 x i8> addrspace(2)* %83, !tbaa !0
  %85 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %84, i32 0, i32 %5)
  %86 = extractelement <4 x float> %85, i32 0
  %87 = extractelement <4 x float> %85, i32 1
  %88 = fmul float %80, %14
  %89 = fadd float %88, %12
  %90 = fmul float %81, %14
  %91 = fadd float %90, %12
  %92 = fmul float %82, %14
  %93 = fadd float %92, %12
  %94 = fmul float %80, %12
  %95 = fadd float %94, %14
  %96 = fmul float %89, %18
  %97 = fmul float %91, %20
  %98 = fadd float %96, %97
  %99 = fmul float %93, %22
  %100 = fadd float %98, %99
  %101 = fmul float %95, %24
  %102 = fadd float %100, %101
  %103 = fmul float %89, %26
  %104 = fmul float %91, %28
  %105 = fadd float %103, %104
  %106 = fmul float %93, %30
  %107 = fadd float %105, %106
  %108 = fmul float %95, %32
  %109 = fadd float %107, %108
  %110 = fmul float %89, %50
  %111 = fmul float %91, %52
  %112 = fadd float %110, %111
  %113 = fmul float %93, %54
  %114 = fadd float %112, %113
  %115 = fmul float %95, %56
  %116 = fadd float %114, %115
  %117 = fmul float %89, %58
  %118 = fmul float %91, %60
  %119 = fadd float %117, %118
  %120 = fmul float %93, %62
  %121 = fadd float %119, %120
  %122 = fmul float %95, %64
  %123 = fadd float %121, %122
  %124 = fmul float %89, %66
  %125 = fmul float %91, %68
  %126 = fadd float %124, %125
  %127 = fmul float %93, %70
  %128 = fadd float %126, %127
  %129 = fmul float %95, %72
  %130 = fadd float %128, %129
  %131 = fmul float %89, %42
  %132 = fmul float %91, %44
  %133 = fadd float %131, %132
  %134 = fmul float %93, %46
  %135 = fadd float %133, %134
  %136 = fmul float %95, %48
  %137 = fadd float %135, %136
  %138 = fmul float %89, %34
  %139 = fmul float %91, %36
  %140 = fadd float %138, %139
  %141 = fmul float %93, %38
  %142 = fadd float %140, %141
  %143 = fmul float %95, %40
  %144 = fadd float %142, %143
  %145 = fsub float -0.000000e+00, %137
  %146 = fmul float %144, %16
  %147 = fadd float %146, %145
  %148 = fsub float -0.000000e+00, %109
  %149 = fmul float %74, %137
  %150 = fadd float %149, %102
  %151 = fmul float %76, %137
  %152 = fadd float %151, %148
  %153 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %154 = load float addrspace(2)* addrspace(2)* %153, !tbaa !0
  %155 = getelementptr float addrspace(2)* %154, i32 0
  %156 = load float addrspace(2)* %155, !tbaa !0
  %157 = fmul float %156, %102
  %158 = getelementptr float addrspace(2)* %154, i32 1
  %159 = load float addrspace(2)* %158, !tbaa !0
  %160 = fmul float %159, %109
  %161 = fadd float %157, %160
  %162 = getelementptr float addrspace(2)* %154, i32 2
  %163 = load float addrspace(2)* %162, !tbaa !0
  %164 = fmul float %163, %144
  %165 = fadd float %161, %164
  %166 = getelementptr float addrspace(2)* %154, i32 3
  %167 = load float addrspace(2)* %166, !tbaa !0
  %168 = fmul float %167, %137
  %169 = fadd float %165, %168
  %170 = getelementptr float addrspace(2)* %154, i32 4
  %171 = load float addrspace(2)* %170, !tbaa !0
  %172 = fmul float %171, %102
  %173 = getelementptr float addrspace(2)* %154, i32 5
  %174 = load float addrspace(2)* %173, !tbaa !0
  %175 = fmul float %174, %109
  %176 = fadd float %172, %175
  %177 = getelementptr float addrspace(2)* %154, i32 6
  %178 = load float addrspace(2)* %177, !tbaa !0
  %179 = fmul float %178, %144
  %180 = fadd float %176, %179
  %181 = getelementptr float addrspace(2)* %154, i32 7
  %182 = load float addrspace(2)* %181, !tbaa !0
  %183 = fmul float %182, %137
  %184 = fadd float %180, %183
  %185 = getelementptr float addrspace(2)* %154, i32 8
  %186 = load float addrspace(2)* %185, !tbaa !0
  %187 = fmul float %186, %102
  %188 = getelementptr float addrspace(2)* %154, i32 9
  %189 = load float addrspace(2)* %188, !tbaa !0
  %190 = fmul float %189, %109
  %191 = fadd float %187, %190
  %192 = getelementptr float addrspace(2)* %154, i32 10
  %193 = load float addrspace(2)* %192, !tbaa !0
  %194 = fmul float %193, %144
  %195 = fadd float %191, %194
  %196 = getelementptr float addrspace(2)* %154, i32 11
  %197 = load float addrspace(2)* %196, !tbaa !0
  %198 = fmul float %197, %137
  %199 = fadd float %195, %198
  %200 = getelementptr float addrspace(2)* %154, i32 12
  %201 = load float addrspace(2)* %200, !tbaa !0
  %202 = fmul float %201, %102
  %203 = getelementptr float addrspace(2)* %154, i32 13
  %204 = load float addrspace(2)* %203, !tbaa !0
  %205 = fmul float %204, %109
  %206 = fadd float %202, %205
  %207 = getelementptr float addrspace(2)* %154, i32 14
  %208 = load float addrspace(2)* %207, !tbaa !0
  %209 = fmul float %208, %144
  %210 = fadd float %206, %209
  %211 = getelementptr float addrspace(2)* %154, i32 15
  %212 = load float addrspace(2)* %211, !tbaa !0
  %213 = fmul float %212, %137
  %214 = fadd float %210, %213
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %169, float %184, float %199, float %214)
  %215 = getelementptr float addrspace(2)* %154, i32 16
  %216 = load float addrspace(2)* %215, !tbaa !0
  %217 = fmul float %216, %102
  %218 = getelementptr float addrspace(2)* %154, i32 17
  %219 = load float addrspace(2)* %218, !tbaa !0
  %220 = fmul float %219, %109
  %221 = fadd float %217, %220
  %222 = getelementptr float addrspace(2)* %154, i32 18
  %223 = load float addrspace(2)* %222, !tbaa !0
  %224 = fmul float %223, %144
  %225 = fadd float %221, %224
  %226 = getelementptr float addrspace(2)* %154, i32 19
  %227 = load float addrspace(2)* %226, !tbaa !0
  %228 = fmul float %227, %137
  %229 = fadd float %225, %228
  %230 = getelementptr float addrspace(2)* %154, i32 20
  %231 = load float addrspace(2)* %230, !tbaa !0
  %232 = fmul float %231, %102
  %233 = getelementptr float addrspace(2)* %154, i32 21
  %234 = load float addrspace(2)* %233, !tbaa !0
  %235 = fmul float %234, %109
  %236 = fadd float %232, %235
  %237 = getelementptr float addrspace(2)* %154, i32 22
  %238 = load float addrspace(2)* %237, !tbaa !0
  %239 = fmul float %238, %144
  %240 = fadd float %236, %239
  %241 = getelementptr float addrspace(2)* %154, i32 23
  %242 = load float addrspace(2)* %241, !tbaa !0
  %243 = fmul float %242, %137
  %244 = fadd float %240, %243
  %245 = getelementptr float addrspace(2)* %154, i32 24
  %246 = load float addrspace(2)* %245, !tbaa !0
  %247 = fmul float %246, %102
  %248 = getelementptr float addrspace(2)* %154, i32 25
  %249 = load float addrspace(2)* %248, !tbaa !0
  %250 = fmul float %249, %109
  %251 = fadd float %247, %250
  %252 = getelementptr float addrspace(2)* %154, i32 26
  %253 = load float addrspace(2)* %252, !tbaa !0
  %254 = fmul float %253, %144
  %255 = fadd float %251, %254
  %256 = getelementptr float addrspace(2)* %154, i32 27
  %257 = load float addrspace(2)* %256, !tbaa !0
  %258 = fmul float %257, %137
  %259 = fadd float %255, %258
  %260 = getelementptr float addrspace(2)* %154, i32 28
  %261 = load float addrspace(2)* %260, !tbaa !0
  %262 = fmul float %261, %102
  %263 = getelementptr float addrspace(2)* %154, i32 29
  %264 = load float addrspace(2)* %263, !tbaa !0
  %265 = fmul float %264, %109
  %266 = fadd float %262, %265
  %267 = getelementptr float addrspace(2)* %154, i32 30
  %268 = load float addrspace(2)* %267, !tbaa !0
  %269 = fmul float %268, %144
  %270 = fadd float %266, %269
  %271 = getelementptr float addrspace(2)* %154, i32 31
  %272 = load float addrspace(2)* %271, !tbaa !0
  %273 = fmul float %272, %137
  %274 = fadd float %270, %273
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %229, float %244, float %259, float %274)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %86, float %87, float %144, float %137)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %116, float %123, float %130, float %144)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %150, float %152, float %147, float %137)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%77](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6_VGPR7<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%13]
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR4, %SGPR4, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR5, %SGPR4, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 17; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 16; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR1, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR4, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 18; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR3, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR4, %SGPR5<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7<imp-use,kill>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 19; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 21; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 20; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 22; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 23; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%153](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%203]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%200]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 25; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 24; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 26; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 27; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%207]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 29; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 28; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 30; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 31; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%211]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%188]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%185]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%192]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%196]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%173]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%170]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%177]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%181]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%158]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%155]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%162]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%166]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%263]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%260]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%267]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%271]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%248]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%245]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%252]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%256]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%233]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%230]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%237]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%241]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%218]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%215]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%222]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%226]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 4; mem:LD16[%83](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR9, %VGPR10, %VGPR7, %VGPR8, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 77; mem:LD4[%67]
	S_WAITCNT 15
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 76; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR1, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 78; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 79; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 73; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 72; mem:LD4[%57]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR1, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 74; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 75; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 69; mem:LD4[%51]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 68; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR1<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 70; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR3<kill>, %SGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 71; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR5<kill>, %SGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR1<kill>, %VGPR9<kill>, %VGPR0<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 80; mem:LD4[%73]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 81; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR6<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840700
bf8c007f
e00c2000
80020400
c0410100
bf8c0070
c0020301
c0028300
bf8c007f
7e060205
d2820001
040c0904
d2820002
040c0905
c0040311
bf8c007f
10100408
c0040310
bf8c007f
d2820008
04201101
d2820003
040c0906
c0040312
bf8c007f
d2820008
04201103
7e120204
d2820005
04240b04
c0020313
bf8c007f
d2820004
04200905
c0020315
bf8c007f
100c0404
c0020314
bf8c007f
d2820006
04180901
c0020316
bf8c007f
d2820006
04180903
c0020317
bf8c007f
d2820006
04180905
c0400102
bf8c007f
c002010d
bf8c007f
100e0c04
c002010c
bf8c007f
d2820008
041e0804
c0020319
bf8c007f
100e0404
c0020318
bf8c007f
d2820007
041c0901
c002031a
bf8c007f
d2820007
041c0903
c002031b
bf8c007f
d2820007
041c0905
c002010e
bf8c007f
d2820009
04220e04
c002031d
bf8c007f
10100404
c002031c
bf8c007f
d2820008
04200901
c002031e
bf8c007f
d2820008
04200903
c002031f
bf8c007f
d2820008
04200905
c002010f
bf8c007f
d2820009
04261004
c0020109
bf8c007f
10140c04
c0020108
bf8c007f
d282000a
042a0804
c002010a
bf8c007f
d282000a
042a0e04
c002010b
bf8c007f
d282000a
042a1004
c0020105
bf8c007f
10160c04
c0020104
bf8c007f
d282000b
042e0804
c0020106
bf8c007f
d282000b
042e0e04
c0020107
bf8c007f
d282000b
042e1004
c0020101
bf8c007f
10180c04
c0020100
bf8c007f
d282000c
04320804
c0020102
bf8c007f
d282000c
04320e04
c0020103
bf8c007f
d282000c
04321004
f80000ef
090a0b0c
c002011d
bf8c000f
10120c04
c002011c
bf8c007f
d2820009
04260804
c002011e
bf8c007f
d2820009
04260e04
c002011f
bf8c007f
d2820009
04261004
c0020119
bf8c007f
10140c04
c0020118
bf8c007f
d282000a
042a0804
c002011a
bf8c007f
d282000a
042a0e04
c002011b
bf8c007f
d282000a
042a1004
c0020115
bf8c007f
10160c04
c0020114
bf8c007f
d282000b
042e0804
c0020116
bf8c007f
d282000b
042e0e04
c0020117
bf8c007f
d282000b
042e1004
c0020111
bf8c007f
10180c04
c0020110
bf8c007f
d282000c
04320804
c0020112
bf8c007f
d282000c
04320e04
c0000113
bf8c007f
d282000c
04321000
f80000ff
090a0b0c
c0820704
bf8c000f
e00c2000
80010900
bf8c0770
f800020f
08070a09
c000034d
bf8c000f
10000400
c000034c
bf8c007f
d2820000
04000101
c000034e
bf8c007f
d2820000
04000103
c000034f
bf8c007f
d2820000
04000105
c0000349
bf8c007f
10120400
c0000348
bf8c007f
d2820009
04240101
c000034a
bf8c007f
d2820009
04240103
c000034b
bf8c007f
d2820009
04240105
c0000345
bf8c007f
10040400
c0000344
bf8c007f
d2820001
04080101
c0000346
bf8c007f
d2820001
04040103
c0000347
bf8c007f
d2820001
04040105
f800021f
07000901
c0000350
bf8c000f
d2820000
04121000
c0000302
bf8c007f
10020e00
08021101
c0000351
bf8c007f
10041000
08040d02
f80008cf
08010200
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 3
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 4
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 5
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 6
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 7
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 8
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 9
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 10
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 11
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 12
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 13
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 14
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 15
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = fmul float %46, %12
  %51 = fmul float %46, %14
  %52 = fmul float %46, %16
  %53 = fmul float %46, %18
  %54 = fmul float %47, %20
  %55 = fadd float %54, %50
  %56 = fmul float %47, %22
  %57 = fadd float %56, %51
  %58 = fmul float %47, %24
  %59 = fadd float %58, %52
  %60 = fmul float %47, %26
  %61 = fadd float %60, %53
  %62 = fmul float %48, %28
  %63 = fadd float %62, %55
  %64 = fmul float %48, %30
  %65 = fadd float %64, %57
  %66 = fmul float %48, %32
  %67 = fadd float %66, %59
  %68 = fmul float %48, %34
  %69 = fadd float %68, %61
  %70 = fmul float %49, %36
  %71 = fadd float %70, %63
  %72 = fmul float %49, %38
  %73 = fadd float %72, %65
  %74 = fmul float %49, %40
  %75 = fadd float %74, %67
  %76 = fmul float %49, %42
  %77 = fadd float %76, %69
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %71, float %73, float %75, float %77)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%43](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 12; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0820700
bf8c007f
e00c2000
80010000
c0400100
bf8c0070
c0010103
bf8c007f
10080002
c0010107
bf8c007f
d2820004
04100501
c001010b
bf8c007f
d2820004
04100502
c001010f
bf8c007f
d2820004
04100503
c0010102
bf8c007f
100a0002
c0010106
bf8c007f
d2820005
04140501
c001010a
bf8c007f
d2820005
04140502
c001010e
bf8c007f
d2820005
04140503
c0010101
bf8c007f
100c0002
c0010105
bf8c007f
d2820006
04180501
c0010109
bf8c007f
d2820006
04180502
c001010d
bf8c007f
d2820006
04180503
c0010100
bf8c007f
100e0002
c0010104
bf8c007f
d2820007
041c0501
c0010108
bf8c007f
d2820007
041c0502
c000010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %32, float %33, float %34)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 0, 0, 1, 1, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
f800180f
03020100
bf810000
FRAG
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL IN[3], GENERIC[22], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..30]
DCL TEMP[0..5], LOCAL
DCL TEMP[6], ARRAY(1), LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MAD TEMP[1].x, CONST[12].xxxx, CONST[21].yyyy, -IN[3].zzzz
  3: MAD TEMP[2].x, CONST[12].xxxx, CONST[20].zzzz, -IN[3].zzzz
  4: RCP TEMP[3].x, TEMP[2].xxxx
  5: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
  6: MUL TEMP[3].x, TEMP[1].xxxx, TEMP[3].xxxx
  7: MOV_SAT TEMP[3].x, TEMP[3].xxxx
  8: SGE TEMP[2].x, -TEMP[2].xxxx, IMM[0].xxxx
  9: F2I TEMP[2].x, -TEMP[2]
 10: UIF TEMP[2].xxxx :0
 11:   MOV TEMP[2].x, IMM[0].yyyy
 12: ELSE :0
 13:   MOV TEMP[2].x, TEMP[3].xxxx
 14: ENDIF
 15: MUL TEMP[3].x, IN[2].zzzz, CONST[21].wwww
 16: MAD TEMP[2].x, TEMP[3].xxxx, TEMP[2].xxxx, -CONST[21].xxxx
 17: MIN TEMP[2].x, TEMP[2].xxxx, CONST[21].zzzz
 18: MOV_SAT TEMP[2].x, TEMP[2].xxxx
 19: MAD TEMP[3].x, TEMP[2].xxxx, -TEMP[2].xxxx, TEMP[2].xxxx
 20: MUL TEMP[3].x, TEMP[3].xxxx, CONST[12].xxxx
 21: MAD TEMP[3].x, TEMP[2].xxxx, TEMP[2].xxxx, TEMP[3].xxxx
 22: MUL TEMP[4].x, TEMP[0].wwww, CONST[1].wwww
 23: MAD TEMP[5].x, TEMP[4].xxxx, IN[1].wwww, -TEMP[4].xxxx
 24: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[1].xyzz
 25: MAD TEMP[4].x, CONST[12].wwww, TEMP[5].xxxx, TEMP[4].xxxx
 26: MAD TEMP[1].xyz, TEMP[0].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 27: ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[4].xxxx
 28: MAD TEMP[2].x, CONST[12].zzzz, TEMP[2].xxxx, TEMP[4].xxxx
 29: MUL TEMP[1].xyz, TEMP[3].xxxx, TEMP[1].xyzz
 30: MAD TEMP[3].x, IN[2].zzzz, CONST[29].wwww, -TEMP[2].xxxx
 31: MAD TEMP[0].xyz, TEMP[0].xyzz, CONST[30].xxxx, TEMP[1].xyzz
 32: MAD TEMP[1].x, CONST[12].yyyy, TEMP[3].xxxx, TEMP[2].xxxx
 33: MOV TEMP[0].w, TEMP[1].xxxx
 34: MOV TEMP[6], TEMP[0]
 35: MOV OUT[0], TEMP[6]
 36: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 4
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 5
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 6
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 7
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 48
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 49
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 50
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 51
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 82
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 84
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 85
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr float addrspace(2)* %21, i32 86
  %45 = load float addrspace(2)* %44, !tbaa !0
  %46 = getelementptr float addrspace(2)* %21, i32 87
  %47 = load float addrspace(2)* %46, !tbaa !0
  %48 = getelementptr float addrspace(2)* %21, i32 116
  %49 = load float addrspace(2)* %48, !tbaa !0
  %50 = getelementptr float addrspace(2)* %21, i32 117
  %51 = load float addrspace(2)* %50, !tbaa !0
  %52 = getelementptr float addrspace(2)* %21, i32 118
  %53 = load float addrspace(2)* %52, !tbaa !0
  %54 = getelementptr float addrspace(2)* %21, i32 119
  %55 = load float addrspace(2)* %54, !tbaa !0
  %56 = getelementptr float addrspace(2)* %21, i32 120
  %57 = load float addrspace(2)* %56, !tbaa !0
  %58 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %59 = load <32 x i8> addrspace(2)* %58, !tbaa !0
  %60 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
  %62 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %63 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %64 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %65 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %66 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %67 = bitcast float %62 to i32
  %68 = bitcast float %63 to i32
  %69 = insertelement <2 x i32> undef, i32 %67, i32 0
  %70 = insertelement <2 x i32> %69, i32 %68, i32 1
  %71 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %70, <32 x i8> %59, <16 x i8> %61, i32 2)
  %72 = extractelement <4 x float> %71, i32 0
  %73 = extractelement <4 x float> %71, i32 1
  %74 = extractelement <4 x float> %71, i32 2
  %75 = extractelement <4 x float> %71, i32 3
  %76 = fsub float -0.000000e+00, %66
  %77 = fmul float %31, %43
  %78 = fadd float %77, %76
  %79 = fsub float -0.000000e+00, %66
  %80 = fmul float %31, %39
  %81 = fadd float %80, %79
  %82 = fdiv float 1.000000e+00, %81
  %83 = fmul float %81, %81
  %84 = fmul float %78, %82
  %85 = call float @llvm.AMDIL.clamp.(float %84, float 0.000000e+00, float 1.000000e+00)
  %86 = fsub float -0.000000e+00, %83
  %87 = fcmp uge float %86, 0.000000e+00
  %88 = select i1 %87, float 1.000000e+00, float 0.000000e+00
  %89 = fsub float -0.000000e+00, %88
  %90 = fptosi float %89 to i32
  %91 = bitcast i32 %90 to float
  %92 = bitcast float %91 to i32
  %93 = icmp ne i32 %92, 0
  %. = select i1 %93, float 1.000000e+00, float %85
  %94 = fmul float %65, %47
  %95 = fsub float -0.000000e+00, %41
  %96 = fmul float %94, %.
  %97 = fadd float %96, %95
  %98 = fcmp uge float %97, %45
  %99 = select i1 %98, float %45, float %97
  %100 = call float @llvm.AMDIL.clamp.(float %99, float 0.000000e+00, float 1.000000e+00)
  %101 = fsub float -0.000000e+00, %100
  %102 = fmul float %100, %101
  %103 = fadd float %102, %100
  %104 = fmul float %103, %31
  %105 = fmul float %100, %100
  %106 = fadd float %105, %104
  %107 = fmul float %75, %29
  %108 = fsub float -0.000000e+00, %107
  %109 = fmul float %107, %64
  %110 = fadd float %109, %108
  %111 = fmul float %72, %23
  %112 = fmul float %73, %25
  %113 = fmul float %74, %27
  %114 = fmul float %37, %110
  %115 = fadd float %114, %107
  %116 = fsub float -0.000000e+00, %57
  %117 = fmul float %111, %116
  %118 = fadd float %117, %49
  %119 = fsub float -0.000000e+00, %57
  %120 = fmul float %112, %119
  %121 = fadd float %120, %51
  %122 = fsub float -0.000000e+00, %57
  %123 = fmul float %113, %122
  %124 = fadd float %123, %53
  %125 = fsub float -0.000000e+00, %115
  %126 = fadd float %100, %125
  %127 = fmul float %35, %126
  %128 = fadd float %127, %115
  %129 = fmul float %106, %118
  %130 = fmul float %106, %121
  %131 = fmul float %106, %124
  %132 = fsub float -0.000000e+00, %128
  %133 = fmul float %65, %55
  %134 = fadd float %133, %132
  %135 = fmul float %111, %57
  %136 = fadd float %135, %129
  %137 = fmul float %112, %57
  %138 = fadd float %137, %130
  %139 = fmul float %113, %57
  %140 = fadd float %139, %131
  %141 = fmul float %33, %134
  %142 = fadd float %141, %128
  %143 = call i32 @llvm.SI.packf16(float %136, float %138)
  %144 = bitcast i32 %143 to float
  %145 = call i32 @llvm.SI.packf16(float %140, float %142)
  %146 = bitcast i32 %145 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %144, float %146, float %144, float %146)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%60](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%58](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR6, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_SUB_F32_e32 %VGPR7<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 51; mem:LD4[%36]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR2<kill>, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%30]
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 85; mem:LD4[%42]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e64 %SGPR2, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 82; mem:LD4[%38]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e64 %SGPR2, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_SUB_F32_e32 %VGPR9<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_RCP_F32_e32 %VGPR9, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR7<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR8<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR8<def> = V_CVT_I32_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR7<kill>, 1.000000e+00, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 87; mem:LD4[%46]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 84; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR3<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 86; mem:LD4[%44]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR0, %SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR0, %VGPR6, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %SGPR3<kill>, %VGPR1<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 119; mem:LD4[%54]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_SUB_F32_e32 %VGPR6<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 49; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %SGPR3<kill>, %VGPR6<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR0, %VGPR0, %EXEC<imp-use>
	%VGPR6<def> = V_SUB_F32_e32 %VGPR0, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%56]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2, %VGPR6, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 118; mem:LD4[%52]
	S_WAITCNT 127
	%VGPR7<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR0, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6<kill>, %SGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR6<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%24]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2, %VGPR6, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%50]
	S_WAITCNT 127
	%VGPR7<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR0, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6<kill>, %SGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR2, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	%VGPR3<def> = V_MUL_F32_e32 %SGPR2, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 116; mem:LD4[%48]
	S_WAITCNT 127
	%VGPR3<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR2<kill>, %SGPR2<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR1<kill>, %VGPR0, %VGPR1, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430202
c0400100
bf8c0070
c0010107
bf8c007f
100c0a02
c81c0700
c81d0701
100e0f06
080e0d07
c0010133
bf8c007f
d2820006
041a0e02
c81c0e00
c81d0e01
c0010130
c0018155
bf8c007f
7e100203
d2100008
02021002
08100f08
c0018152
bf8c007f
7e120203
d2100009
02021202
08120f09
7e0e5509
100e0f08
d2060807
02010107
10101309
d2060008
22010108
d00c0004
02010108
d2000008
0011e480
d2060008
22010108
7e101108
d10a0004
02010108
d2000008
0011e507
c81c0a00
c81d0a01
c0018157
bf8c007f
10000e03
10001100
c0018154
bf8c007f
0a000003
c0018156
bf8c007f
d00c0004
02000700
7e020203
d2000000
00120300
d2060800
02010100
08020d00
c0018132
bf8c007f
d2820001
041a0203
c0018177
bf8c007f
100c0e03
080c0306
c0018131
bf8c007f
d2820001
04060c03
100c0100
080c0d00
100c0c02
d2820000
041a0100
c0010106
bf8c007f
100c0802
c0010178
bf8c007f
100e0c02
c0018176
bf8c007f
080e0e03
100e0f00
d2820006
041c0506
5e020306
c0018105
bf8c007f
100c0603
100e0c02
c0018175
bf8c007f
080e0e03
100e0f00
d2820006
041c0506
c0018104
bf8c007f
10040403
10060402
c0000174
bf8c007f
08060600
10000700
d2820000
04000502
5e000d00
f8001c0f
01000100
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL OUT[5], GENERIC[22]
DCL CONST[0..57]
DCL TEMP[0..6], LOCAL
  0: DP4 TEMP[0].x, IN[1], CONST[48]
  1: DP4 TEMP[1].x, IN[1], CONST[49]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: MAD TEMP[2].xyz, IN[2].xyzz, CONST[3].xxxx, IN[0].xyzz
  4: MOV TEMP[2].w, IN[0].wwww
  5: DP4 TEMP[1].x, TEMP[2], CONST[54]
  6: DP4 TEMP[3].x, TEMP[2], CONST[55]
  7: MOV TEMP[1].y, TEMP[3].xxxx
  8: DP4 TEMP[3].x, TEMP[2], CONST[56]
  9: MOV TEMP[1].z, TEMP[3].xxxx
 10: MOV TEMP[1].w, CONST[0].yyyy
 11: DP4 TEMP[3].x, TEMP[1], CONST[10]
 12: MOV TEMP[2].z, TEMP[3].xxxx
 13: DP4 TEMP[2].x, TEMP[1], CONST[8]
 14: DP4 TEMP[3].x, TEMP[1], CONST[9]
 15: MOV TEMP[2].y, TEMP[3].xxxx
 16: DP4 TEMP[3].x, TEMP[1], CONST[11]
 17: MOV TEMP[2].w, TEMP[3].xxxx
 18: DP4 TEMP[3].x, TEMP[1], CONST[13]
 19: MOV TEMP[4].z, TEMP[3].xxxx
 20: MOV TEMP[1].xyz, TEMP[1].xyzx
 21: MOV TEMP[5], TEMP[2]
 22: MOV TEMP[6].xy, TEMP[2].xyxx
 23: MOV TEMP[6].zw, TEMP[4].wwzw
 24: MOV TEMP[1].w, TEMP[3].xxxx
 25: MOV TEMP[3], TEMP[5]
 26: MAD TEMP[4].x, TEMP[2].zzzz, CONST[0].zzzz, -TEMP[2].wwww
 27: MOV TEMP[5].z, TEMP[4].xxxx
 28: MOV TEMP[5].y, -TEMP[2].yyyy
 29: MAD TEMP[5].xy, CONST[57].xyyy, TEMP[2].wwww, TEMP[5].xyyy
 30: MOV OUT[2], TEMP[0]
 31: MOV OUT[3], CONST[0].xxxx
 32: MOV OUT[0], TEMP[5]
 33: MOV OUT[1], TEMP[3]
 34: MOV OUT[4], TEMP[6]
 35: MOV OUT[5], TEMP[1]
 36: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 12
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 32
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 33
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 34
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 35
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 36
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 37
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 38
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 39
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 40
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 41
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 42
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 43
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 44
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 45
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 46
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 47
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 52
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 53
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 54
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 55
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 192
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 193
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 194
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 195
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 196
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 197
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 198
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 199
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 216
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 217
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 218
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 219
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 220
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 221
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr float addrspace(2)* %10, i32 222
  %88 = load float addrspace(2)* %87, !tbaa !0
  %89 = getelementptr float addrspace(2)* %10, i32 223
  %90 = load float addrspace(2)* %89, !tbaa !0
  %91 = getelementptr float addrspace(2)* %10, i32 224
  %92 = load float addrspace(2)* %91, !tbaa !0
  %93 = getelementptr float addrspace(2)* %10, i32 225
  %94 = load float addrspace(2)* %93, !tbaa !0
  %95 = getelementptr float addrspace(2)* %10, i32 226
  %96 = load float addrspace(2)* %95, !tbaa !0
  %97 = getelementptr float addrspace(2)* %10, i32 227
  %98 = load float addrspace(2)* %97, !tbaa !0
  %99 = getelementptr float addrspace(2)* %10, i32 228
  %100 = load float addrspace(2)* %99, !tbaa !0
  %101 = getelementptr float addrspace(2)* %10, i32 229
  %102 = load float addrspace(2)* %101, !tbaa !0
  %103 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %104 = load <16 x i8> addrspace(2)* %103, !tbaa !0
  %105 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %104, i32 0, i32 %5)
  %106 = extractelement <4 x float> %105, i32 0
  %107 = extractelement <4 x float> %105, i32 1
  %108 = extractelement <4 x float> %105, i32 2
  %109 = extractelement <4 x float> %105, i32 3
  %110 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %111 = load <16 x i8> addrspace(2)* %110, !tbaa !0
  %112 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %111, i32 0, i32 %5)
  %113 = extractelement <4 x float> %112, i32 0
  %114 = extractelement <4 x float> %112, i32 1
  %115 = extractelement <4 x float> %112, i32 2
  %116 = extractelement <4 x float> %112, i32 3
  %117 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %118 = load <16 x i8> addrspace(2)* %117, !tbaa !0
  %119 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %118, i32 0, i32 %5)
  %120 = extractelement <4 x float> %119, i32 0
  %121 = extractelement <4 x float> %119, i32 1
  %122 = extractelement <4 x float> %119, i32 2
  %123 = fmul float %113, %60
  %124 = fmul float %114, %62
  %125 = fadd float %123, %124
  %126 = fmul float %115, %64
  %127 = fadd float %125, %126
  %128 = fmul float %116, %66
  %129 = fadd float %127, %128
  %130 = fmul float %113, %68
  %131 = fmul float %114, %70
  %132 = fadd float %130, %131
  %133 = fmul float %115, %72
  %134 = fadd float %132, %133
  %135 = fmul float %116, %74
  %136 = fadd float %134, %135
  %137 = fmul float %120, %18
  %138 = fadd float %137, %106
  %139 = fmul float %121, %18
  %140 = fadd float %139, %107
  %141 = fmul float %122, %18
  %142 = fadd float %141, %108
  %143 = fmul float %138, %76
  %144 = fmul float %140, %78
  %145 = fadd float %143, %144
  %146 = fmul float %142, %80
  %147 = fadd float %145, %146
  %148 = fmul float %109, %82
  %149 = fadd float %147, %148
  %150 = fmul float %138, %84
  %151 = fmul float %140, %86
  %152 = fadd float %150, %151
  %153 = fmul float %142, %88
  %154 = fadd float %152, %153
  %155 = fmul float %109, %90
  %156 = fadd float %154, %155
  %157 = fmul float %138, %92
  %158 = fmul float %140, %94
  %159 = fadd float %157, %158
  %160 = fmul float %142, %96
  %161 = fadd float %159, %160
  %162 = fmul float %109, %98
  %163 = fadd float %161, %162
  %164 = fmul float %149, %36
  %165 = fmul float %156, %38
  %166 = fadd float %164, %165
  %167 = fmul float %163, %40
  %168 = fadd float %166, %167
  %169 = fmul float %14, %42
  %170 = fadd float %168, %169
  %171 = fmul float %149, %20
  %172 = fmul float %156, %22
  %173 = fadd float %171, %172
  %174 = fmul float %163, %24
  %175 = fadd float %173, %174
  %176 = fmul float %14, %26
  %177 = fadd float %175, %176
  %178 = fmul float %149, %28
  %179 = fmul float %156, %30
  %180 = fadd float %178, %179
  %181 = fmul float %163, %32
  %182 = fadd float %180, %181
  %183 = fmul float %14, %34
  %184 = fadd float %182, %183
  %185 = fmul float %149, %44
  %186 = fmul float %156, %46
  %187 = fadd float %185, %186
  %188 = fmul float %163, %48
  %189 = fadd float %187, %188
  %190 = fmul float %14, %50
  %191 = fadd float %189, %190
  %192 = fmul float %149, %52
  %193 = fmul float %156, %54
  %194 = fadd float %192, %193
  %195 = fmul float %163, %56
  %196 = fadd float %194, %195
  %197 = fmul float %14, %58
  %198 = fadd float %196, %197
  %199 = fsub float -0.000000e+00, %191
  %200 = fmul float %170, %16
  %201 = fadd float %200, %199
  %202 = fsub float -0.000000e+00, %184
  %203 = fmul float %100, %191
  %204 = fadd float %203, %177
  %205 = fmul float %102, %191
  %206 = fadd float %205, %202
  %207 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %208 = load float addrspace(2)* addrspace(2)* %207, !tbaa !0
  %209 = getelementptr float addrspace(2)* %208, i32 0
  %210 = load float addrspace(2)* %209, !tbaa !0
  %211 = fmul float %210, %177
  %212 = getelementptr float addrspace(2)* %208, i32 1
  %213 = load float addrspace(2)* %212, !tbaa !0
  %214 = fmul float %213, %184
  %215 = fadd float %211, %214
  %216 = getelementptr float addrspace(2)* %208, i32 2
  %217 = load float addrspace(2)* %216, !tbaa !0
  %218 = fmul float %217, %170
  %219 = fadd float %215, %218
  %220 = getelementptr float addrspace(2)* %208, i32 3
  %221 = load float addrspace(2)* %220, !tbaa !0
  %222 = fmul float %221, %191
  %223 = fadd float %219, %222
  %224 = getelementptr float addrspace(2)* %208, i32 4
  %225 = load float addrspace(2)* %224, !tbaa !0
  %226 = fmul float %225, %177
  %227 = getelementptr float addrspace(2)* %208, i32 5
  %228 = load float addrspace(2)* %227, !tbaa !0
  %229 = fmul float %228, %184
  %230 = fadd float %226, %229
  %231 = getelementptr float addrspace(2)* %208, i32 6
  %232 = load float addrspace(2)* %231, !tbaa !0
  %233 = fmul float %232, %170
  %234 = fadd float %230, %233
  %235 = getelementptr float addrspace(2)* %208, i32 7
  %236 = load float addrspace(2)* %235, !tbaa !0
  %237 = fmul float %236, %191
  %238 = fadd float %234, %237
  %239 = getelementptr float addrspace(2)* %208, i32 8
  %240 = load float addrspace(2)* %239, !tbaa !0
  %241 = fmul float %240, %177
  %242 = getelementptr float addrspace(2)* %208, i32 9
  %243 = load float addrspace(2)* %242, !tbaa !0
  %244 = fmul float %243, %184
  %245 = fadd float %241, %244
  %246 = getelementptr float addrspace(2)* %208, i32 10
  %247 = load float addrspace(2)* %246, !tbaa !0
  %248 = fmul float %247, %170
  %249 = fadd float %245, %248
  %250 = getelementptr float addrspace(2)* %208, i32 11
  %251 = load float addrspace(2)* %250, !tbaa !0
  %252 = fmul float %251, %191
  %253 = fadd float %249, %252
  %254 = getelementptr float addrspace(2)* %208, i32 12
  %255 = load float addrspace(2)* %254, !tbaa !0
  %256 = fmul float %255, %177
  %257 = getelementptr float addrspace(2)* %208, i32 13
  %258 = load float addrspace(2)* %257, !tbaa !0
  %259 = fmul float %258, %184
  %260 = fadd float %256, %259
  %261 = getelementptr float addrspace(2)* %208, i32 14
  %262 = load float addrspace(2)* %261, !tbaa !0
  %263 = fmul float %262, %170
  %264 = fadd float %260, %263
  %265 = getelementptr float addrspace(2)* %208, i32 15
  %266 = load float addrspace(2)* %265, !tbaa !0
  %267 = fmul float %266, %191
  %268 = fadd float %264, %267
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %223, float %238, float %253, float %268)
  %269 = getelementptr float addrspace(2)* %208, i32 16
  %270 = load float addrspace(2)* %269, !tbaa !0
  %271 = fmul float %270, %177
  %272 = getelementptr float addrspace(2)* %208, i32 17
  %273 = load float addrspace(2)* %272, !tbaa !0
  %274 = fmul float %273, %184
  %275 = fadd float %271, %274
  %276 = getelementptr float addrspace(2)* %208, i32 18
  %277 = load float addrspace(2)* %276, !tbaa !0
  %278 = fmul float %277, %170
  %279 = fadd float %275, %278
  %280 = getelementptr float addrspace(2)* %208, i32 19
  %281 = load float addrspace(2)* %280, !tbaa !0
  %282 = fmul float %281, %191
  %283 = fadd float %279, %282
  %284 = getelementptr float addrspace(2)* %208, i32 20
  %285 = load float addrspace(2)* %284, !tbaa !0
  %286 = fmul float %285, %177
  %287 = getelementptr float addrspace(2)* %208, i32 21
  %288 = load float addrspace(2)* %287, !tbaa !0
  %289 = fmul float %288, %184
  %290 = fadd float %286, %289
  %291 = getelementptr float addrspace(2)* %208, i32 22
  %292 = load float addrspace(2)* %291, !tbaa !0
  %293 = fmul float %292, %170
  %294 = fadd float %290, %293
  %295 = getelementptr float addrspace(2)* %208, i32 23
  %296 = load float addrspace(2)* %295, !tbaa !0
  %297 = fmul float %296, %191
  %298 = fadd float %294, %297
  %299 = getelementptr float addrspace(2)* %208, i32 24
  %300 = load float addrspace(2)* %299, !tbaa !0
  %301 = fmul float %300, %177
  %302 = getelementptr float addrspace(2)* %208, i32 25
  %303 = load float addrspace(2)* %302, !tbaa !0
  %304 = fmul float %303, %184
  %305 = fadd float %301, %304
  %306 = getelementptr float addrspace(2)* %208, i32 26
  %307 = load float addrspace(2)* %306, !tbaa !0
  %308 = fmul float %307, %170
  %309 = fadd float %305, %308
  %310 = getelementptr float addrspace(2)* %208, i32 27
  %311 = load float addrspace(2)* %310, !tbaa !0
  %312 = fmul float %311, %191
  %313 = fadd float %309, %312
  %314 = getelementptr float addrspace(2)* %208, i32 28
  %315 = load float addrspace(2)* %314, !tbaa !0
  %316 = fmul float %315, %177
  %317 = getelementptr float addrspace(2)* %208, i32 29
  %318 = load float addrspace(2)* %317, !tbaa !0
  %319 = fmul float %318, %184
  %320 = fadd float %316, %319
  %321 = getelementptr float addrspace(2)* %208, i32 30
  %322 = load float addrspace(2)* %321, !tbaa !0
  %323 = fmul float %322, %170
  %324 = fadd float %320, %323
  %325 = getelementptr float addrspace(2)* %208, i32 31
  %326 = load float addrspace(2)* %325, !tbaa !0
  %327 = fmul float %326, %191
  %328 = fadd float %324, %327
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %283, float %298, float %313, float %328)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %129, float %136, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %12, float %12, float %12, float %12)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %177, float %184, float %198, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %149, float %156, float %163, float %198)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %204, float %206, float %201, float %191)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%103](tbaa=!"const")
	S_WAITCNT 127
	%VGPR3_VGPR4_VGPR5_VGPR6<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%117](tbaa=!"const")
	S_WAITCNT 112
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 12; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR9, %SGPR4, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 217; mem:LD4[%77]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 216; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR7, %SGPR5<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR11, %SGPR4<kill>, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 218; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR9, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 219; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 221; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 220; mem:LD4[%83]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 222; mem:LD4[%87]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR9, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 223; mem:LD4[%89]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 33; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 32; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 225; mem:LD4[%93]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 224; mem:LD4[%91]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR7<kill>, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 226; mem:LD4[%95]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR9<kill>, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 227; mem:LD4[%97]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-use,kill>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 34; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%13]
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 35; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 37; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 36; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR5<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 38; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR5<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 39; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %SGPR4, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%207](tbaa=!"const")
	S_WAITCNT 127
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%257]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%254]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 41; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 40; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR5<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 42; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR5<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 43; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR4, %VGPR8<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%261]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 45; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 44; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR5<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 46; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR3, %SGPR5<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 47; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %SGPR4, %VGPR9<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%265]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%242]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%239]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%246]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%250]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%227]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%224]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%231]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%235]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%212]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%209]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%216]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%220]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%317]
	S_WAITCNT 15
	%VGPR8<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%314]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%321]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%325]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%302]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%299]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%306]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%310]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%287]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%284]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%291]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%295]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%272]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%269]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%276]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%280]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 4; mem:LD16[%110](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%69]
	S_WAITCNT 112
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 198; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 199; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR11, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 194; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 195; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR11, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%VGPR0<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR8<kill>, %VGPR12<kill>, %VGPR0, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 0; mem:LD4[%11]
	S_WAITCNT 15
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 %SGPR0, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %SGPR0, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR8<kill>, %VGPR9<kill>, %VGPR10<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 53; mem:LD4[%53]
	S_WAITCNT 15
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 52; mem:LD4[%51]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR1, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 54; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 55; mem:LD4[%57]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR4, %VGPR5, %VGPR8, %VGPR0<kill>, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR1<kill>, %VGPR2<kill>, %VGPR3<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 228; mem:LD4[%99]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 229; mem:LD4[%101]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR5<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR7<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840700
bf8c007f
e00c2000
80020300
c0840708
bf8c0070
e00c2000
80020900
c0410100
bf8c0070
c002030c
bf8c007f
d2820007
040c0909
d2820008
0410090a
c00283d9
bf8c007f
10021005
c00283d8
bf8c007f
d2820001
04040b07
d2820009
0414090b
c00203da
bf8c007f
d2820001
04040909
c00203db
bf8c007f
d2820001
04040906
c00203dd
bf8c007f
10041004
c00203dc
bf8c007f
d2820002
04080907
c00203de
bf8c007f
d2820002
04080909
c00203df
bf8c007f
d2820002
04080906
c0020321
bf8c007f
10140404
c0020320
bf8c007f
d282000a
04280901
c00203e1
bf8c007f
10101004
c00203e0
bf8c007f
d2820007
04200907
c00203e2
bf8c007f
d2820007
041c0909
c00203e3
bf8c007f
d2820003
041c0906
c0020322
bf8c007f
d2820004
04280903
c0020301
c0028323
bf8c007f
7e0a0205
d2820004
04120a04
c0028325
bf8c007f
100a0405
c0028324
bf8c007f
d2820005
04140b01
c0028326
bf8c007f
d2820005
04140b03
c0028327
bf8c007f
7e0c0205
d2820005
04160c04
c0400102
bf8c007f
c002810d
bf8c007f
100c0a05
c002810c
bf8c007f
d2820007
041a0805
c0028329
bf8c007f
100c0405
c0028328
bf8c007f
d2820006
04180b01
c002832a
bf8c007f
d2820006
04180b03
c002832b
bf8c007f
7e100205
d2820006
041a1004
c002810e
bf8c007f
d2820008
041e0c05
c002832d
bf8c007f
100e0405
c002832c
bf8c007f
d2820007
041c0b01
c002832e
bf8c007f
d2820007
041c0b03
c002832f
bf8c007f
7e120205
d2820007
041e1204
c002810f
bf8c007f
d2820008
04220e05
c0028109
bf8c007f
10120a05
c0028108
bf8c007f
d2820009
04260805
c002810a
bf8c007f
d2820009
04260c05
c002810b
bf8c007f
d2820009
04260e05
c0028105
bf8c007f
10140a05
c0028104
bf8c007f
d282000a
042a0805
c0028106
bf8c007f
d282000a
042a0c05
c0028107
bf8c007f
d282000a
042a0e05
c0028101
bf8c007f
10160a05
c0028100
bf8c007f
d282000b
042e0805
c0028102
bf8c007f
d282000b
042e0c05
c0028103
bf8c007f
d282000b
042e0e05
f80000ef
08090a0b
c002811d
bf8c000f
10100a05
c002811c
bf8c007f
d2820008
04220805
c002811e
bf8c007f
d2820008
04220c05
c002811f
bf8c007f
d2820008
04220e05
c0028119
bf8c007f
10120a05
c0028118
bf8c007f
d2820009
04260805
c002811a
bf8c007f
d2820009
04260c05
c002811b
bf8c007f
d2820009
04260e05
c0028115
bf8c007f
10140a05
c0028114
bf8c007f
d282000a
042a0805
c0028116
bf8c007f
d282000a
042a0c05
c0028117
bf8c007f
d282000a
042a0e05
c0028111
bf8c007f
10160a05
c0028110
bf8c007f
d282000b
042e0805
c0028112
bf8c007f
d282000b
042e0c05
c0000113
bf8c007f
d282000b
042e0e00
f80000ff
08090a0b
c0840704
bf8c000f
e00c2000
80020800
c00003c5
bf8c0070
10001200
c00003c4
bf8c007f
d2820000
04000108
c00003c6
bf8c007f
d2820000
0400010a
c00003c7
bf8c007f
d282000c
0400010b
c00003c1
bf8c007f
10001200
c00003c0
bf8c007f
d2820000
04000108
c00003c2
bf8c007f
d2820000
0400010a
c00003c3
bf8c007f
d2820008
0400010b
7e000280
f800020f
00000c08
c0000300
bf8c000f
7e100200
7e120200
7e140200
7e160200
f800021f
0b0a0908
c0000335
bf8c000f
10100400
c0000334
bf8c007f
d2820008
04200101
c0000336
bf8c007f
d2820008
04200103
c0000337
bf8c007f
7e120200
d2820008
04221204
f800022f
00080504
f800023f
08030201
c00003e4
bf8c000f
d2820000
04120e00
c0000302
bf8c007f
10020c00
08020f01
c00003e5
bf8c007f
10040e00
08040b02
f80008cf
07010200
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[1..4]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: MOV TEMP[0].w, IN[0].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], CONST[4]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 16
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 17
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 18
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 19
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %31 = load <32 x i8> addrspace(2)* %30, !tbaa !0
  %32 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0
  %34 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %35 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %36 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %37 = fdiv float %34, %36
  %38 = fdiv float %35, %36
  %39 = bitcast float %37 to i32
  %40 = bitcast float %38 to i32
  %41 = insertelement <2 x i32> undef, i32 %39, i32 0
  %42 = insertelement <2 x i32> %41, i32 %40, i32 1
  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %42, <32 x i8> %31, <16 x i8> %33, i32 2)
  %44 = extractelement <4 x float> %43, i32 0
  %45 = extractelement <4 x float> %43, i32 1
  %46 = extractelement <4 x float> %43, i32 2
  %47 = extractelement <4 x float> %43, i32 3
  %48 = fmul float %44, %23
  %49 = fmul float %45, %25
  %50 = fmul float %46, %27
  %51 = fmul float %47, %29
  %52 = call i32 @llvm.SI.packf16(float %48, float %49)
  %53 = bitcast i32 %52 to float
  %54 = call i32 @llvm.SI.packf16(float %50, float %51)
  %55 = bitcast i32 %54 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %53, float %55, float %53, float %55)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_RCP_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR4, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%32](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%30](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%24]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 16; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR5<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8080100
c8090101
c80c0300
c80d0301
7e085503
10060902
c8140000
c8150001
10040905
c0840300
c0c60500
bf8c007f
f0800f00
00430002
c0400100
bf8c0070
c0010113
bf8c007f
10080602
c0010112
bf8c007f
100a0402
5e080905
c0010111
bf8c007f
100a0202
c0000110
bf8c007f
10000000
5e000b00
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
DCL CONST[0..7]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MUL TEMP[0], IN[1].xxxx, CONST[4]
  5: MAD TEMP[0], IN[1].yyyy, CONST[5], TEMP[0]
  6: MAD TEMP[0], IN[1].zzzz, CONST[6], TEMP[0]
  7: MAD OUT[1], IN[1].wwww, CONST[7], TEMP[0]
  8: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 3
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 4
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 5
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 6
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 7
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 8
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 9
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 10
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 11
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 12
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 13
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 14
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 15
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 16
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 17
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 18
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 19
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 20
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 21
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 22
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 23
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 24
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 25
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 26
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 27
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 28
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 29
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 30
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 31
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0
  %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %76, i32 0, i32 %5)
  %78 = extractelement <4 x float> %77, i32 0
  %79 = extractelement <4 x float> %77, i32 1
  %80 = extractelement <4 x float> %77, i32 2
  %81 = extractelement <4 x float> %77, i32 3
  %82 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %83 = load <16 x i8> addrspace(2)* %82, !tbaa !0
  %84 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %83, i32 0, i32 %5)
  %85 = extractelement <4 x float> %84, i32 0
  %86 = extractelement <4 x float> %84, i32 1
  %87 = extractelement <4 x float> %84, i32 2
  %88 = extractelement <4 x float> %84, i32 3
  %89 = fmul float %78, %12
  %90 = fmul float %78, %14
  %91 = fmul float %78, %16
  %92 = fmul float %78, %18
  %93 = fmul float %79, %20
  %94 = fadd float %93, %89
  %95 = fmul float %79, %22
  %96 = fadd float %95, %90
  %97 = fmul float %79, %24
  %98 = fadd float %97, %91
  %99 = fmul float %79, %26
  %100 = fadd float %99, %92
  %101 = fmul float %80, %28
  %102 = fadd float %101, %94
  %103 = fmul float %80, %30
  %104 = fadd float %103, %96
  %105 = fmul float %80, %32
  %106 = fadd float %105, %98
  %107 = fmul float %80, %34
  %108 = fadd float %107, %100
  %109 = fmul float %81, %36
  %110 = fadd float %109, %102
  %111 = fmul float %81, %38
  %112 = fadd float %111, %104
  %113 = fmul float %81, %40
  %114 = fadd float %113, %106
  %115 = fmul float %81, %42
  %116 = fadd float %115, %108
  %117 = fmul float %85, %44
  %118 = fmul float %85, %46
  %119 = fmul float %85, %48
  %120 = fmul float %85, %50
  %121 = fmul float %86, %52
  %122 = fadd float %121, %117
  %123 = fmul float %86, %54
  %124 = fadd float %123, %118
  %125 = fmul float %86, %56
  %126 = fadd float %125, %119
  %127 = fmul float %86, %58
  %128 = fadd float %127, %120
  %129 = fmul float %87, %60
  %130 = fadd float %129, %122
  %131 = fmul float %87, %62
  %132 = fadd float %131, %124
  %133 = fmul float %87, %64
  %134 = fadd float %133, %126
  %135 = fmul float %87, %66
  %136 = fadd float %135, %128
  %137 = fmul float %88, %68
  %138 = fadd float %137, %130
  %139 = fmul float %88, %70
  %140 = fadd float %139, %132
  %141 = fmul float %88, %72
  %142 = fadd float %141, %134
  %143 = fmul float %88, %74
  %144 = fadd float %143, %136
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %138, float %140, float %142, float %144)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %110, float %112, float %114, float %116)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%82](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%57]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR4, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR4, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR4, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%51]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR4, %SGPR2<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%75](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%17]
	S_WAITCNT 112
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 12; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0400100
bf8c0070
c0010113
bf8c007f
100a0202
c0010117
bf8c007f
d2820005
04140502
c001011b
bf8c007f
d2820005
04140503
c001011f
bf8c007f
d2820005
04140504
c0010112
bf8c007f
100c0202
c0010116
bf8c007f
d2820006
04180502
c001011a
bf8c007f
d2820006
04180503
c001011e
bf8c007f
d2820006
04180504
c0010111
bf8c007f
100e0202
c0010115
bf8c007f
d2820007
041c0502
c0010119
bf8c007f
d2820007
041c0503
c001011d
bf8c007f
d2820007
041c0504
c0010110
bf8c007f
10100202
c0010114
bf8c007f
d2820008
04200502
c0010118
bf8c007f
d2820008
04200503
c001011c
bf8c007f
d2820001
04200504
f800020f
05060701
c0820700
bf8c000f
e00c2000
80010000
c0010103
bf8c0070
10080002
c0010107
bf8c007f
d2820004
04100501
c001010b
bf8c007f
d2820004
04100502
c001010f
bf8c007f
d2820004
04100503
c0010102
bf8c007f
100a0002
c0010106
bf8c007f
d2820005
04140501
c001010a
bf8c007f
d2820005
04140502
c001010e
bf8c007f
d2820005
04140503
c0010101
bf8c007f
100c0002
c0010105
bf8c007f
d2820006
04180501
c0010109
bf8c007f
d2820006
04180502
c001010d
bf8c007f
d2820006
04180503
c0010100
bf8c007f
100e0002
c0010104
bf8c007f
d2820007
041c0501
c0010108
bf8c007f
d2820007
041c0502
c000010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: MOV TEMP[0].w, IN[1].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], IN[0]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %31 = fdiv float %28, %30
  %32 = fdiv float %29, %30
  %33 = bitcast float %31 to i32
  %34 = bitcast float %32 to i32
  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %38, %24
  %43 = fmul float %39, %25
  %44 = fmul float %40, %26
  %45 = fmul float %41, %27
  %46 = call i32 @llvm.SI.packf16(float %42, float %43)
  %47 = bitcast i32 %46 to float
  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
  %49 = bitcast i32 %48 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %47, float %49, float %47, float %49)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_RCP_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR4, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_MUL_F32_e32 %VGPR5, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR4, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR7<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR3, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR8<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR6<kill>, %VGPR0, %VGPR6, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8080500
c8090501
c80c0700
c80d0701
7e085503
10060902
c8140400
c8150401
10040905
c0800300
c0c40500
bf8c007f
f0800f00
00020202
c8180300
c8190301
bf8c0770
100c0d05
c81c0200
c81d0201
100e0f04
5e0c0d07
c81c0100
c81d0101
100e0f03
c8200000
c8210001
10001102
5e000f00
f8001c0f
06000600
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], GENERIC[0]
DCL CONST[0..7]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
  9: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 3
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 4
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 5
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 6
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 7
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 8
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 9
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 10
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 11
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 12
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 13
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 14
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 15
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 16
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 17
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 18
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 19
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 20
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 21
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 22
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 23
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 24
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 25
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 26
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 27
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 28
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 29
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 30
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 31
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0
  %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %76, i32 0, i32 %5)
  %78 = extractelement <4 x float> %77, i32 0
  %79 = extractelement <4 x float> %77, i32 1
  %80 = extractelement <4 x float> %77, i32 2
  %81 = extractelement <4 x float> %77, i32 3
  %82 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %83 = load <16 x i8> addrspace(2)* %82, !tbaa !0
  %84 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %83, i32 0, i32 %5)
  %85 = extractelement <4 x float> %84, i32 0
  %86 = extractelement <4 x float> %84, i32 1
  %87 = extractelement <4 x float> %84, i32 2
  %88 = extractelement <4 x float> %84, i32 3
  %89 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %90 = load <16 x i8> addrspace(2)* %89, !tbaa !0
  %91 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %90, i32 0, i32 %5)
  %92 = extractelement <4 x float> %91, i32 0
  %93 = extractelement <4 x float> %91, i32 1
  %94 = extractelement <4 x float> %91, i32 2
  %95 = extractelement <4 x float> %91, i32 3
  %96 = fmul float %78, %12
  %97 = fmul float %78, %14
  %98 = fmul float %78, %16
  %99 = fmul float %78, %18
  %100 = fmul float %79, %20
  %101 = fadd float %100, %96
  %102 = fmul float %79, %22
  %103 = fadd float %102, %97
  %104 = fmul float %79, %24
  %105 = fadd float %104, %98
  %106 = fmul float %79, %26
  %107 = fadd float %106, %99
  %108 = fmul float %80, %28
  %109 = fadd float %108, %101
  %110 = fmul float %80, %30
  %111 = fadd float %110, %103
  %112 = fmul float %80, %32
  %113 = fadd float %112, %105
  %114 = fmul float %80, %34
  %115 = fadd float %114, %107
  %116 = fmul float %81, %36
  %117 = fadd float %116, %109
  %118 = fmul float %81, %38
  %119 = fadd float %118, %111
  %120 = fmul float %81, %40
  %121 = fadd float %120, %113
  %122 = fmul float %81, %42
  %123 = fadd float %122, %115
  %124 = call float @llvm.AMDIL.clamp.(float %85, float 0.000000e+00, float 1.000000e+00)
  %125 = call float @llvm.AMDIL.clamp.(float %86, float 0.000000e+00, float 1.000000e+00)
  %126 = call float @llvm.AMDIL.clamp.(float %87, float 0.000000e+00, float 1.000000e+00)
  %127 = call float @llvm.AMDIL.clamp.(float %88, float 0.000000e+00, float 1.000000e+00)
  %128 = fmul float %92, %44
  %129 = fmul float %92, %46
  %130 = fmul float %92, %48
  %131 = fmul float %92, %50
  %132 = fmul float %93, %52
  %133 = fadd float %132, %128
  %134 = fmul float %93, %54
  %135 = fadd float %134, %129
  %136 = fmul float %93, %56
  %137 = fadd float %136, %130
  %138 = fmul float %93, %58
  %139 = fadd float %138, %131
  %140 = fmul float %94, %60
  %141 = fadd float %140, %133
  %142 = fmul float %94, %62
  %143 = fadd float %142, %135
  %144 = fmul float %94, %64
  %145 = fadd float %144, %137
  %146 = fmul float %94, %66
  %147 = fadd float %146, %139
  %148 = fmul float %95, %68
  %149 = fadd float %148, %141
  %150 = fmul float %95, %70
  %151 = fadd float %150, %143
  %152 = fmul float %95, %72
  %153 = fadd float %152, %145
  %154 = fmul float %95, %74
  %155 = fadd float %154, %147
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %124, float %125, float %126, float %127)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %149, float %151, float %153, float %155)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %117, float %119, float %121, float %123)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%82](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_ADD_F32_e64 %VGPR4, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 %VGPR3, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR2, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 %VGPR1, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%89](tbaa=!"const")
	S_WAITCNT 15
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%57]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR4, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR4, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR4, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%51]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR4, %SGPR2<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 33, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%75](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%17]
	S_WAITCNT 112
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 12; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0840708
bf8c000f
e00c2000
80020100
c0400100
bf8c0070
c0010113
bf8c007f
100a0202
c0010117
bf8c007f
d2820005
04140502
c001011b
bf8c007f
d2820005
04140503
c001011f
bf8c007f
d2820005
04140504
c0010112
bf8c007f
100c0202
c0010116
bf8c007f
d2820006
04180502
c001011a
bf8c007f
d2820006
04180503
c001011e
bf8c007f
d2820006
04180504
c0010111
bf8c007f
100e0202
c0010115
bf8c007f
d2820007
041c0502
c0010119
bf8c007f
d2820007
041c0503
c001011d
bf8c007f
d2820007
041c0504
c0010110
bf8c007f
10100202
c0010114
bf8c007f
d2820008
04200502
c0010118
bf8c007f
d2820008
04200503
c001011c
bf8c007f
d2820001
04200504
f800021f
05060701
c0820700
bf8c000f
e00c2000
80010000
c0010103
bf8c0070
10080002
c0010107
bf8c007f
d2820004
04100501
c001010b
bf8c007f
d2820004
04100502
c001010f
bf8c007f
d2820004
04100503
c0010102
bf8c007f
100a0002
c0010106
bf8c007f
d2820005
04140501
c001010a
bf8c007f
d2820005
04140502
c001010e
bf8c007f
d2820005
04140503
c0010101
bf8c007f
100c0002
c0010105
bf8c007f
d2820006
04180501
c0010109
bf8c007f
d2820006
04180502
c001010d
bf8c007f
d2820006
04180503
c0010100
bf8c007f
100e0002
c0010104
bf8c007f
d2820007
041c0501
c0010108
bf8c007f
d2820007
041c0502
c000010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
Could not load program cache file glbaseshaders.cfg
Could not find base GL shader cache file
CGLMShaderPair::SetProgramPair: Centroid masks differ at link time of vertex shader lightmappedgeneric_vs20 and pixel shader decalbasetimeslightmapalphablendselfillum2_ps20b!
Loaded program cache file "glshaders.cfg", total keyvalues: 189, total successfully linked: 189
Precache: Took 7557 ms, Vertex 486, Pixel 906
ConVarRef mat_dxlevel doesn't point to an existing ConVar
Game.so loaded for "Half-Life 2"
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 3
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 4
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 5
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 6
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 7
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 8
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 9
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 10
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 11
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 12
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 13
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 14
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 15
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = fmul float %46, %12
  %51 = fmul float %46, %14
  %52 = fmul float %46, %16
  %53 = fmul float %46, %18
  %54 = fmul float %47, %20
  %55 = fadd float %54, %50
  %56 = fmul float %47, %22
  %57 = fadd float %56, %51
  %58 = fmul float %47, %24
  %59 = fadd float %58, %52
  %60 = fmul float %47, %26
  %61 = fadd float %60, %53
  %62 = fmul float %48, %28
  %63 = fadd float %62, %55
  %64 = fmul float %48, %30
  %65 = fadd float %64, %57
  %66 = fmul float %48, %32
  %67 = fadd float %66, %59
  %68 = fmul float %48, %34
  %69 = fadd float %68, %61
  %70 = fmul float %49, %36
  %71 = fadd float %70, %63
  %72 = fmul float %49, %38
  %73 = fadd float %72, %65
  %74 = fmul float %49, %40
  %75 = fadd float %74, %67
  %76 = fmul float %49, %42
  %77 = fadd float %76, %69
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %71, float %73, float %75, float %77)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%43](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 12; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0820700
bf8c007f
e00c2000
80010000
c0400100
bf8c0070
c0010103
bf8c007f
10080002
c0010107
bf8c007f
d2820004
04100501
c001010b
bf8c007f
d2820004
04100502
c001010f
bf8c007f
d2820004
04100503
c0010102
bf8c007f
100a0002
c0010106
bf8c007f
d2820005
04140501
c001010a
bf8c007f
d2820005
04140502
c001010e
bf8c007f
d2820005
04140503
c0010101
bf8c007f
100c0002
c0010105
bf8c007f
d2820006
04180501
c0010109
bf8c007f
d2820006
04180502
c001010d
bf8c007f
d2820006
04180503
c0010100
bf8c007f
100e0002
c0010104
bf8c007f
d2820007
041c0501
c0010108
bf8c007f
d2820007
041c0502
c000010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 3D
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %9)
  %27 = bitcast float %24 to i32
  %28 = bitcast float %25 to i32
  %29 = bitcast float %26 to i32
  %30 = insertelement <4 x i32> undef, i32 %27, i32 0
  %31 = insertelement <4 x i32> %30, i32 %28, i32 1
  %32 = insertelement <4 x i32> %31, i32 %29, i32 2
  %33 = insertelement <4 x i32> %32, i32 undef, i32 3
  %34 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %33, <32 x i8> %21, <16 x i8> %23, i32 3)
  %35 = extractelement <4 x float> %34, i32 0
  %36 = extractelement <4 x float> %34, i32 1
  %37 = extractelement <4 x float> %34, i32 2
  %38 = extractelement <4 x float> %34, i32 3
  %39 = call i32 @llvm.SI.packf16(float %35, float %36)
  %40 = bitcast i32 %39 to float
  %41 = call i32 @llvm.SI.packf16(float %37, float %38)
  %42 = bitcast i32 %41 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def> = KILL %VGPR5<undef>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3_VGPR4_VGPR5<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c8100200
c8110201
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 3D
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %9)
  %27 = bitcast float %24 to i32
  %28 = bitcast float %25 to i32
  %29 = bitcast float %26 to i32
  %30 = insertelement <4 x i32> undef, i32 %27, i32 0
  %31 = insertelement <4 x i32> %30, i32 %28, i32 1
  %32 = insertelement <4 x i32> %31, i32 %29, i32 2
  %33 = insertelement <4 x i32> %32, i32 undef, i32 3
  %34 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %33, <32 x i8> %21, <16 x i8> %23, i32 3)
  %35 = extractelement <4 x float> %34, i32 0
  %36 = extractelement <4 x float> %34, i32 1
  %37 = extractelement <4 x float> %34, i32 2
  %38 = extractelement <4 x float> %34, i32 3
  %39 = call i32 @llvm.SI.packf16(float %35, float %36)
  %40 = bitcast i32 %39 to float
  %41 = call i32 @llvm.SI.packf16(float %37, float %38)
  %42 = bitcast i32 %41 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def> = KILL %VGPR5<undef>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3_VGPR4_VGPR5<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c8100200
c8110201
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xyz, IN[0].xyzz
  1: TEX TEMP[0], TEMP[0], SAMP[0], 3D
  2: MOV OUT[0], TEMP[0]
  3: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %27 = bitcast float %24 to i32
  %28 = bitcast float %25 to i32
  %29 = bitcast float %26 to i32
  %30 = insertelement <4 x i32> undef, i32 %27, i32 0
  %31 = insertelement <4 x i32> %30, i32 %28, i32 1
  %32 = insertelement <4 x i32> %31, i32 %29, i32 2
  %33 = insertelement <4 x i32> %32, i32 undef, i32 3
  %34 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %33, <32 x i8> %21, <16 x i8> %23, i32 3)
  %35 = extractelement <4 x float> %34, i32 0
  %36 = extractelement <4 x float> %34, i32 1
  %37 = extractelement <4 x float> %34, i32 2
  %38 = extractelement <4 x float> %34, i32 3
  %39 = call i32 @llvm.SI.packf16(float %35, float %36)
  %40 = bitcast i32 %39 to float
  %41 = call i32 @llvm.SI.packf16(float %37, float %38)
  %42 = bitcast i32 %41 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR5<def> = KILL %VGPR5<undef>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3_VGPR4_VGPR5<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c8100200
c8110201
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..3]
DCL TEMP[0], LOCAL
IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
  0: MUL TEMP[0], CONST[0], IN[0].xxxx
  1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0]
  2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0]
  3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0]
  4: MOV OUT[1], IMM[0].xxxx
  5: MOV OUT[0], TEMP[0]
  6: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 3
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 4
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 5
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 6
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 7
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 8
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 9
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 10
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 11
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 12
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 13
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 14
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 15
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = fmul float %12, %46
  %51 = fmul float %14, %46
  %52 = fmul float %16, %46
  %53 = fmul float %18, %46
  %54 = fmul float %20, %47
  %55 = fadd float %54, %50
  %56 = fmul float %22, %47
  %57 = fadd float %56, %51
  %58 = fmul float %24, %47
  %59 = fadd float %58, %52
  %60 = fmul float %26, %47
  %61 = fadd float %60, %53
  %62 = fmul float %28, %48
  %63 = fadd float %62, %55
  %64 = fmul float %30, %48
  %65 = fadd float %64, %57
  %66 = fmul float %32, %48
  %67 = fadd float %66, %59
  %68 = fmul float %34, %48
  %69 = fadd float %68, %61
  %70 = fmul float %36, %49
  %71 = fadd float %70, %63
  %72 = fmul float %38, %49
  %73 = fadd float %72, %65
  %74 = fmul float %40, %49
  %75 = fadd float %74, %67
  %76 = fmul float %42, %49
  %77 = fadd float %76, %69
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %71, float %73, float %75, float %77)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%VGPR1<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR1, %VGPR1, %VGPR1, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%43](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR2<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR2<kill>, %VGPR2, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR2<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR2<kill>, %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR2<kill>, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR2<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR2<kill>, %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR2<kill>, %VGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR2<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR2<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR2<kill>, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 12; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e020280
f800020f
01010101
c0820700
bf8c000f
e00c2000
80010000
c0400100
bf8c0070
c0010103
bf8c007f
10080002
c0010107
bf8c007f
d2820004
04120202
c001010b
bf8c007f
d2820004
04120402
c001010f
bf8c007f
d2820004
04120602
c0010102
bf8c007f
100a0002
c0010106
bf8c007f
d2820005
04160202
c001010a
bf8c007f
d2820005
04160402
c001010e
bf8c007f
d2820005
04160602
c0010101
bf8c007f
100c0002
c0010105
bf8c007f
d2820006
041a0202
c0010109
bf8c007f
d2820006
041a0402
c001010d
bf8c007f
d2820006
041a0602
c0010100
bf8c007f
100e0002
c0010104
bf8c007f
d2820007
041e0202
c0010108
bf8c007f
d2820007
041e0402
c000010c
bf8c007f
d2820000
041e0600
f80008cf
04050600
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL OUT[1], POSITION
DCL SAMP[0]
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV OUT[0], IMM[0].xxxy
  1: TEX OUT[1].z, IN[0], SAMP[0], 2D
  2: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 2
  %32 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
  %33 = bitcast i32 %32 to float
  %34 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 1.000000e+00)
  %35 = bitcast i32 %34 to float
  call void @llvm.SI.export(i32 1, i32 0, i32 0, i32 8, i32 0, float %31, float %31, float %31, float %31)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %33, float %35, float %33, float %35)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0<def> = IMAGE_SAMPLE 4, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 1, 8, 0, 0, 0, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800400
00010002
bf8c0770
f8000081
00000000
bf8c070f
d25e0000
0201e480
d25e0001
02010080
f8001c0f
00010001
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL OUT[1], POSITION
DCL SAMP[0]
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV OUT[0], IMM[0].xxxy
  1: TEX OUT[1].z, IN[0], SAMP[0], 2D
  2: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 2
  call void @llvm.SI.export(i32 1, i32 0, i32 0, i32 8, i32 0, float %31, float %31, float %31, float %31)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0<def> = IMAGE_SAMPLE 4, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 1, 8, 0, 0, 0, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR1<kill>, %VGPR1, %VGPR1, %VGPR0<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800400
00010002
bf8c0770
f8000081
00000000
bf8c070f
7e0002f2
7e020280
f800180f
00010101
bf810000
FRAG
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL IN[3], GENERIC[22], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..30]
DCL TEMP[0..5], LOCAL
DCL TEMP[6], ARRAY(1), LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MAD TEMP[1].x, CONST[12].xxxx, CONST[21].yyyy, -IN[3].zzzz
  3: MAD TEMP[2].x, CONST[12].xxxx, CONST[20].zzzz, -IN[3].zzzz
  4: RCP TEMP[3].x, TEMP[2].xxxx
  5: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
  6: MUL TEMP[3].x, TEMP[1].xxxx, TEMP[3].xxxx
  7: MOV_SAT TEMP[3].x, TEMP[3].xxxx
  8: SGE TEMP[2].x, -TEMP[2].xxxx, IMM[0].xxxx
  9: F2I TEMP[2].x, -TEMP[2]
 10: UIF TEMP[2].xxxx :0
 11:   MOV TEMP[2].x, IMM[0].yyyy
 12: ELSE :0
 13:   MOV TEMP[2].x, TEMP[3].xxxx
 14: ENDIF
 15: MUL TEMP[3].x, IN[2].zzzz, CONST[21].wwww
 16: MAD TEMP[2].x, TEMP[3].xxxx, TEMP[2].xxxx, -CONST[21].xxxx
 17: MIN TEMP[2].x, TEMP[2].xxxx, CONST[21].zzzz
 18: MOV_SAT TEMP[2].x, TEMP[2].xxxx
 19: MAD TEMP[3].x, TEMP[2].xxxx, -TEMP[2].xxxx, TEMP[2].xxxx
 20: MUL TEMP[3].x, TEMP[3].xxxx, CONST[12].xxxx
 21: MAD TEMP[3].x, TEMP[2].xxxx, TEMP[2].xxxx, TEMP[3].xxxx
 22: MUL TEMP[4].x, TEMP[0].wwww, CONST[1].wwww
 23: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[1].xyzz
 24: MAD TEMP[5].x, TEMP[4].xxxx, IN[1].wwww, -TEMP[4].xxxx
 25: MUL TEMP[0].xyz, TEMP[0].xyzz, IN[1].xyzz
 26: MAD TEMP[4].x, CONST[12].wwww, TEMP[5].xxxx, TEMP[4].xxxx
 27: MAD TEMP[1].xyz, TEMP[0].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 28: ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[4].xxxx
 29: MAD TEMP[2].x, CONST[12].zzzz, TEMP[2].xxxx, TEMP[4].xxxx
 30: MUL TEMP[1].xyz, TEMP[3].xxxx, TEMP[1].xyzz
 31: MAD TEMP[3].x, IN[2].zzzz, CONST[29].wwww, -TEMP[2].xxxx
 32: MAD TEMP[0].xyz, TEMP[0].xyzz, CONST[30].xxxx, TEMP[1].xyzz
 33: MAD TEMP[1].x, CONST[12].yyyy, TEMP[3].xxxx, TEMP[2].xxxx
 34: MOV TEMP[0].w, TEMP[1].xxxx
 35: MOV TEMP[6], TEMP[0]
 36: MOV OUT[0], TEMP[6]
 37: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 4
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 5
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 6
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 7
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 48
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 49
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 50
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 51
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 82
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 84
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 85
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr float addrspace(2)* %21, i32 86
  %45 = load float addrspace(2)* %44, !tbaa !0
  %46 = getelementptr float addrspace(2)* %21, i32 87
  %47 = load float addrspace(2)* %46, !tbaa !0
  %48 = getelementptr float addrspace(2)* %21, i32 116
  %49 = load float addrspace(2)* %48, !tbaa !0
  %50 = getelementptr float addrspace(2)* %21, i32 117
  %51 = load float addrspace(2)* %50, !tbaa !0
  %52 = getelementptr float addrspace(2)* %21, i32 118
  %53 = load float addrspace(2)* %52, !tbaa !0
  %54 = getelementptr float addrspace(2)* %21, i32 119
  %55 = load float addrspace(2)* %54, !tbaa !0
  %56 = getelementptr float addrspace(2)* %21, i32 120
  %57 = load float addrspace(2)* %56, !tbaa !0
  %58 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %59 = load <32 x i8> addrspace(2)* %58, !tbaa !0
  %60 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
  %62 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %63 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %64 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %65 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %66 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %67 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %68 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %69 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %70 = bitcast float %62 to i32
  %71 = bitcast float %63 to i32
  %72 = insertelement <2 x i32> undef, i32 %70, i32 0
  %73 = insertelement <2 x i32> %72, i32 %71, i32 1
  %74 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %73, <32 x i8> %59, <16 x i8> %61, i32 2)
  %75 = extractelement <4 x float> %74, i32 0
  %76 = extractelement <4 x float> %74, i32 1
  %77 = extractelement <4 x float> %74, i32 2
  %78 = extractelement <4 x float> %74, i32 3
  %79 = fsub float -0.000000e+00, %69
  %80 = fmul float %31, %43
  %81 = fadd float %80, %79
  %82 = fsub float -0.000000e+00, %69
  %83 = fmul float %31, %39
  %84 = fadd float %83, %82
  %85 = fdiv float 1.000000e+00, %84
  %86 = fmul float %84, %84
  %87 = fmul float %81, %85
  %88 = call float @llvm.AMDIL.clamp.(float %87, float 0.000000e+00, float 1.000000e+00)
  %89 = fsub float -0.000000e+00, %86
  %90 = fcmp uge float %89, 0.000000e+00
  %91 = select i1 %90, float 1.000000e+00, float 0.000000e+00
  %92 = fsub float -0.000000e+00, %91
  %93 = fptosi float %92 to i32
  %94 = bitcast i32 %93 to float
  %95 = bitcast float %94 to i32
  %96 = icmp ne i32 %95, 0
  %. = select i1 %96, float 1.000000e+00, float %88
  %97 = fmul float %68, %47
  %98 = fsub float -0.000000e+00, %41
  %99 = fmul float %97, %.
  %100 = fadd float %99, %98
  %101 = fcmp uge float %100, %45
  %102 = select i1 %101, float %45, float %100
  %103 = call float @llvm.AMDIL.clamp.(float %102, float 0.000000e+00, float 1.000000e+00)
  %104 = fsub float -0.000000e+00, %103
  %105 = fmul float %103, %104
  %106 = fadd float %105, %103
  %107 = fmul float %106, %31
  %108 = fmul float %103, %103
  %109 = fadd float %108, %107
  %110 = fmul float %78, %29
  %111 = fmul float %75, %23
  %112 = fmul float %76, %25
  %113 = fmul float %77, %27
  %114 = fsub float -0.000000e+00, %110
  %115 = fmul float %110, %67
  %116 = fadd float %115, %114
  %117 = fmul float %111, %64
  %118 = fmul float %112, %65
  %119 = fmul float %113, %66
  %120 = fmul float %37, %116
  %121 = fadd float %120, %110
  %122 = fsub float -0.000000e+00, %57
  %123 = fmul float %117, %122
  %124 = fadd float %123, %49
  %125 = fsub float -0.000000e+00, %57
  %126 = fmul float %118, %125
  %127 = fadd float %126, %51
  %128 = fsub float -0.000000e+00, %57
  %129 = fmul float %119, %128
  %130 = fadd float %129, %53
  %131 = fsub float -0.000000e+00, %121
  %132 = fadd float %103, %131
  %133 = fmul float %35, %132
  %134 = fadd float %133, %121
  %135 = fmul float %109, %124
  %136 = fmul float %109, %127
  %137 = fmul float %109, %130
  %138 = fsub float -0.000000e+00, %134
  %139 = fmul float %68, %55
  %140 = fadd float %139, %138
  %141 = fmul float %117, %57
  %142 = fadd float %141, %135
  %143 = fmul float %118, %57
  %144 = fadd float %143, %136
  %145 = fmul float %119, %57
  %146 = fadd float %145, %137
  %147 = fmul float %33, %140
  %148 = fadd float %147, %134
  %149 = call i32 @llvm.SI.packf16(float %142, float %144)
  %150 = bitcast i32 %149 to float
  %151 = call i32 @llvm.SI.packf16(float %146, float %148)
  %152 = bitcast i32 %151 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %150, float %152, float %150, float %152)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%60](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%58](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR6, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_SUB_F32_e32 %VGPR7<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 51; mem:LD4[%36]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR2<kill>, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%30]
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 85; mem:LD4[%42]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e64 %SGPR2, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 82; mem:LD4[%38]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e64 %SGPR2, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_SUB_F32_e32 %VGPR9<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_RCP_F32_e32 %VGPR9, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR7<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR8<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR8<def> = V_CVT_I32_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR7<kill>, 1.000000e+00, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 87; mem:LD4[%46]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 84; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR8<def> = V_SUBREV_F32_e32 %SGPR3<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 86; mem:LD4[%44]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR8, %SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR9<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_SUB_F32_e32 %VGPR8, %VGPR6, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR3<kill>, %VGPR9<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 119; mem:LD4[%54]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_SUB_F32_e32 %VGPR7<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 49; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR3<kill>, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR8, %VGPR8, %EXEC<imp-use>
	%VGPR6<def> = V_SUB_F32_e32 %VGPR8, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR8<kill>, %VGPR8, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%56]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 118; mem:LD4[%52]
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR6, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8<kill>, %SGPR2, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%24]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%50]
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR6, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8<kill>, %SGPR2, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR2, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 116; mem:LD4[%48]
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR7<kill>, %VGPR0, %VGPR7, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430202
c0400100
bf8c0070
c0010107
bf8c007f
100c0a02
c81c0700
c81d0701
100e0f06
080e0d07
c0010133
bf8c007f
d2820006
041a0e02
c81c0e00
c81d0e01
c0010130
c0018155
bf8c007f
7e100203
d2100008
02021002
08100f08
c0018152
bf8c007f
7e120203
d2100009
02021202
08120f09
7e0e5509
100e0f08
d2060807
02010107
10101309
d2060008
22010108
d00c0004
02010108
d2000008
0011e480
d2060008
22010108
7e101108
d10a0004
02010108
d2000008
0011e507
c81c0a00
c81d0a01
c0018157
bf8c007f
10120e03
10101109
c0018154
bf8c007f
0a101003
c0018156
bf8c007f
d00c0004
02000708
7e120203
d2000008
00121308
d2060808
02010108
08120d08
c0018132
bf8c007f
d2820006
041a1203
c0018177
bf8c007f
100e0e03
080e0d07
c0018131
bf8c007f
d2820007
041a0e03
100c1108
080c0d08
100c0c02
d2820006
041a1108
c0010106
bf8c007f
10100802
c8240600
c8250601
10101308
c0010178
bf8c007f
10121002
c0018176
bf8c007f
08121203
10121306
d2820008
04240508
5e0e0f08
c0018105
bf8c007f
10100603
c8240500
c8250501
10101308
10121002
c0018175
bf8c007f
08121203
10121306
d2820008
04240508
c0018104
bf8c007f
10040403
c80c0400
c80d0401
10000702
10020002
c0000174
bf8c007f
08020200
10020306
d2820000
04040500
5e001100
f8001c0f
07000700
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL OUT[5], GENERIC[22]
DCL CONST[0..57]
DCL TEMP[0..7], LOCAL
IMM[0] FLT32 {    2.2000,     0.0000,     0.0000,     0.0000}
  0: LG2 TEMP[0].x, IN[1].xxxx
  1: LG2 TEMP[1].x, IN[1].yyyy
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: LG2 TEMP[1].x, IN[1].zzzz
  4: MOV TEMP[0].z, TEMP[1].xxxx
  5: MUL TEMP[0].xyz, TEMP[0].xyzz, IMM[0].xxxx
  6: EX2 TEMP[1].x, TEMP[0].xxxx
  7: EX2 TEMP[2].x, TEMP[0].yyyy
  8: MOV TEMP[1].y, TEMP[2].xxxx
  9: EX2 TEMP[2].x, TEMP[0].zzzz
 10: MOV TEMP[1].z, TEMP[2].xxxx
 11: DP4 TEMP[2].x, IN[2], CONST[48]
 12: DP4 TEMP[3].x, IN[2], CONST[49]
 13: MOV TEMP[2].y, TEMP[3].xxxx
 14: MAD TEMP[0].xyz, IN[3].xyzz, CONST[3].xxxx, IN[0].xyzz
 15: MOV TEMP[0].w, IN[0].wwww
 16: DP4 TEMP[3].x, TEMP[0], CONST[54]
 17: DP4 TEMP[4].x, TEMP[0], CONST[55]
 18: MOV TEMP[3].y, TEMP[4].xxxx
 19: DP4 TEMP[4].x, TEMP[0], CONST[56]
 20: MOV TEMP[3].z, TEMP[4].xxxx
 21: MOV TEMP[3].w, CONST[0].yyyy
 22: DP4 TEMP[4].x, TEMP[3], CONST[10]
 23: MOV TEMP[0].z, TEMP[4].xxxx
 24: DP4 TEMP[0].x, TEMP[3], CONST[8]
 25: DP4 TEMP[4].x, TEMP[3], CONST[9]
 26: MOV TEMP[0].y, TEMP[4].xxxx
 27: DP4 TEMP[4].x, TEMP[3], CONST[11]
 28: MOV TEMP[0].w, TEMP[4].xxxx
 29: DP4 TEMP[4].x, TEMP[3], CONST[13]
 30: MOV TEMP[5].z, TEMP[4].xxxx
 31: MOV TEMP[3].xyz, TEMP[3].xyzx
 32: MOV TEMP[6], TEMP[0]
 33: MOV TEMP[7].xy, TEMP[0].xyxx
 34: MOV TEMP[1].w, IN[1].wwww
 35: MOV TEMP[7].zw, TEMP[5].wwzw
 36: MOV TEMP[3].w, TEMP[4].xxxx
 37: MOV TEMP[4], TEMP[6]
 38: MAD TEMP[5].x, TEMP[0].zzzz, CONST[0].zzzz, -TEMP[0].wwww
 39: MOV TEMP[6].z, TEMP[5].xxxx
 40: MOV TEMP[6].y, -TEMP[0].yyyy
 41: MAD TEMP[6].xy, CONST[57].xyyy, TEMP[0].wwww, TEMP[6].xyyy
 42: MOV OUT[2], TEMP[2]
 43: MOV OUT[3], TEMP[1]
 44: MOV OUT[0], TEMP[6]
 45: MOV OUT[1], TEMP[4]
 46: MOV OUT[4], TEMP[7]
 47: MOV OUT[5], TEMP[3]
 48: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 1
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 2
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 12
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 32
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 33
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 34
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 35
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 36
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 37
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 38
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 39
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 40
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 41
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 42
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 43
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 44
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 45
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 46
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 47
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 52
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 53
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 54
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 55
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 192
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 193
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 194
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 195
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 196
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 197
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 198
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 199
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 216
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 217
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 218
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 219
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 220
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 221
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 222
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr float addrspace(2)* %10, i32 223
  %88 = load float addrspace(2)* %87, !tbaa !0
  %89 = getelementptr float addrspace(2)* %10, i32 224
  %90 = load float addrspace(2)* %89, !tbaa !0
  %91 = getelementptr float addrspace(2)* %10, i32 225
  %92 = load float addrspace(2)* %91, !tbaa !0
  %93 = getelementptr float addrspace(2)* %10, i32 226
  %94 = load float addrspace(2)* %93, !tbaa !0
  %95 = getelementptr float addrspace(2)* %10, i32 227
  %96 = load float addrspace(2)* %95, !tbaa !0
  %97 = getelementptr float addrspace(2)* %10, i32 228
  %98 = load float addrspace(2)* %97, !tbaa !0
  %99 = getelementptr float addrspace(2)* %10, i32 229
  %100 = load float addrspace(2)* %99, !tbaa !0
  %101 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %102 = load <16 x i8> addrspace(2)* %101, !tbaa !0
  %103 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %102, i32 0, i32 %5)
  %104 = extractelement <4 x float> %103, i32 0
  %105 = extractelement <4 x float> %103, i32 1
  %106 = extractelement <4 x float> %103, i32 2
  %107 = extractelement <4 x float> %103, i32 3
  %108 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %109 = load <16 x i8> addrspace(2)* %108, !tbaa !0
  %110 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %109, i32 0, i32 %5)
  %111 = extractelement <4 x float> %110, i32 0
  %112 = extractelement <4 x float> %110, i32 1
  %113 = extractelement <4 x float> %110, i32 2
  %114 = extractelement <4 x float> %110, i32 3
  %115 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %116 = load <16 x i8> addrspace(2)* %115, !tbaa !0
  %117 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %116, i32 0, i32 %5)
  %118 = extractelement <4 x float> %117, i32 0
  %119 = extractelement <4 x float> %117, i32 1
  %120 = extractelement <4 x float> %117, i32 2
  %121 = extractelement <4 x float> %117, i32 3
  %122 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
  %124 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %123, i32 0, i32 %5)
  %125 = extractelement <4 x float> %124, i32 0
  %126 = extractelement <4 x float> %124, i32 1
  %127 = extractelement <4 x float> %124, i32 2
  %128 = call float @llvm.log2.f32(float %111)
  %129 = call float @llvm.log2.f32(float %112)
  %130 = call float @llvm.log2.f32(float %113)
  %131 = fmul float %128, 0x40019999A0000000
  %132 = fmul float %129, 0x40019999A0000000
  %133 = fmul float %130, 0x40019999A0000000
  %134 = call float @llvm.AMDIL.exp.(float %131)
  %135 = call float @llvm.AMDIL.exp.(float %132)
  %136 = call float @llvm.AMDIL.exp.(float %133)
  %137 = fmul float %118, %58
  %138 = fmul float %119, %60
  %139 = fadd float %137, %138
  %140 = fmul float %120, %62
  %141 = fadd float %139, %140
  %142 = fmul float %121, %64
  %143 = fadd float %141, %142
  %144 = fmul float %118, %66
  %145 = fmul float %119, %68
  %146 = fadd float %144, %145
  %147 = fmul float %120, %70
  %148 = fadd float %146, %147
  %149 = fmul float %121, %72
  %150 = fadd float %148, %149
  %151 = fmul float %125, %16
  %152 = fadd float %151, %104
  %153 = fmul float %126, %16
  %154 = fadd float %153, %105
  %155 = fmul float %127, %16
  %156 = fadd float %155, %106
  %157 = fmul float %152, %74
  %158 = fmul float %154, %76
  %159 = fadd float %157, %158
  %160 = fmul float %156, %78
  %161 = fadd float %159, %160
  %162 = fmul float %107, %80
  %163 = fadd float %161, %162
  %164 = fmul float %152, %82
  %165 = fmul float %154, %84
  %166 = fadd float %164, %165
  %167 = fmul float %156, %86
  %168 = fadd float %166, %167
  %169 = fmul float %107, %88
  %170 = fadd float %168, %169
  %171 = fmul float %152, %90
  %172 = fmul float %154, %92
  %173 = fadd float %171, %172
  %174 = fmul float %156, %94
  %175 = fadd float %173, %174
  %176 = fmul float %107, %96
  %177 = fadd float %175, %176
  %178 = fmul float %163, %34
  %179 = fmul float %170, %36
  %180 = fadd float %178, %179
  %181 = fmul float %177, %38
  %182 = fadd float %180, %181
  %183 = fmul float %12, %40
  %184 = fadd float %182, %183
  %185 = fmul float %163, %18
  %186 = fmul float %170, %20
  %187 = fadd float %185, %186
  %188 = fmul float %177, %22
  %189 = fadd float %187, %188
  %190 = fmul float %12, %24
  %191 = fadd float %189, %190
  %192 = fmul float %163, %26
  %193 = fmul float %170, %28
  %194 = fadd float %192, %193
  %195 = fmul float %177, %30
  %196 = fadd float %194, %195
  %197 = fmul float %12, %32
  %198 = fadd float %196, %197
  %199 = fmul float %163, %42
  %200 = fmul float %170, %44
  %201 = fadd float %199, %200
  %202 = fmul float %177, %46
  %203 = fadd float %201, %202
  %204 = fmul float %12, %48
  %205 = fadd float %203, %204
  %206 = fmul float %163, %50
  %207 = fmul float %170, %52
  %208 = fadd float %206, %207
  %209 = fmul float %177, %54
  %210 = fadd float %208, %209
  %211 = fmul float %12, %56
  %212 = fadd float %210, %211
  %213 = fsub float -0.000000e+00, %205
  %214 = fmul float %184, %14
  %215 = fadd float %214, %213
  %216 = fsub float -0.000000e+00, %198
  %217 = fmul float %98, %205
  %218 = fadd float %217, %191
  %219 = fmul float %100, %205
  %220 = fadd float %219, %216
  %221 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %222 = load float addrspace(2)* addrspace(2)* %221, !tbaa !0
  %223 = getelementptr float addrspace(2)* %222, i32 0
  %224 = load float addrspace(2)* %223, !tbaa !0
  %225 = fmul float %224, %191
  %226 = getelementptr float addrspace(2)* %222, i32 1
  %227 = load float addrspace(2)* %226, !tbaa !0
  %228 = fmul float %227, %198
  %229 = fadd float %225, %228
  %230 = getelementptr float addrspace(2)* %222, i32 2
  %231 = load float addrspace(2)* %230, !tbaa !0
  %232 = fmul float %231, %184
  %233 = fadd float %229, %232
  %234 = getelementptr float addrspace(2)* %222, i32 3
  %235 = load float addrspace(2)* %234, !tbaa !0
  %236 = fmul float %235, %205
  %237 = fadd float %233, %236
  %238 = getelementptr float addrspace(2)* %222, i32 4
  %239 = load float addrspace(2)* %238, !tbaa !0
  %240 = fmul float %239, %191
  %241 = getelementptr float addrspace(2)* %222, i32 5
  %242 = load float addrspace(2)* %241, !tbaa !0
  %243 = fmul float %242, %198
  %244 = fadd float %240, %243
  %245 = getelementptr float addrspace(2)* %222, i32 6
  %246 = load float addrspace(2)* %245, !tbaa !0
  %247 = fmul float %246, %184
  %248 = fadd float %244, %247
  %249 = getelementptr float addrspace(2)* %222, i32 7
  %250 = load float addrspace(2)* %249, !tbaa !0
  %251 = fmul float %250, %205
  %252 = fadd float %248, %251
  %253 = getelementptr float addrspace(2)* %222, i32 8
  %254 = load float addrspace(2)* %253, !tbaa !0
  %255 = fmul float %254, %191
  %256 = getelementptr float addrspace(2)* %222, i32 9
  %257 = load float addrspace(2)* %256, !tbaa !0
  %258 = fmul float %257, %198
  %259 = fadd float %255, %258
  %260 = getelementptr float addrspace(2)* %222, i32 10
  %261 = load float addrspace(2)* %260, !tbaa !0
  %262 = fmul float %261, %184
  %263 = fadd float %259, %262
  %264 = getelementptr float addrspace(2)* %222, i32 11
  %265 = load float addrspace(2)* %264, !tbaa !0
  %266 = fmul float %265, %205
  %267 = fadd float %263, %266
  %268 = getelementptr float addrspace(2)* %222, i32 12
  %269 = load float addrspace(2)* %268, !tbaa !0
  %270 = fmul float %269, %191
  %271 = getelementptr float addrspace(2)* %222, i32 13
  %272 = load float addrspace(2)* %271, !tbaa !0
  %273 = fmul float %272, %198
  %274 = fadd float %270, %273
  %275 = getelementptr float addrspace(2)* %222, i32 14
  %276 = load float addrspace(2)* %275, !tbaa !0
  %277 = fmul float %276, %184
  %278 = fadd float %274, %277
  %279 = getelementptr float addrspace(2)* %222, i32 15
  %280 = load float addrspace(2)* %279, !tbaa !0
  %281 = fmul float %280, %205
  %282 = fadd float %278, %281
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %237, float %252, float %267, float %282)
  %283 = getelementptr float addrspace(2)* %222, i32 16
  %284 = load float addrspace(2)* %283, !tbaa !0
  %285 = fmul float %284, %191
  %286 = getelementptr float addrspace(2)* %222, i32 17
  %287 = load float addrspace(2)* %286, !tbaa !0
  %288 = fmul float %287, %198
  %289 = fadd float %285, %288
  %290 = getelementptr float addrspace(2)* %222, i32 18
  %291 = load float addrspace(2)* %290, !tbaa !0
  %292 = fmul float %291, %184
  %293 = fadd float %289, %292
  %294 = getelementptr float addrspace(2)* %222, i32 19
  %295 = load float addrspace(2)* %294, !tbaa !0
  %296 = fmul float %295, %205
  %297 = fadd float %293, %296
  %298 = getelementptr float addrspace(2)* %222, i32 20
  %299 = load float addrspace(2)* %298, !tbaa !0
  %300 = fmul float %299, %191
  %301 = getelementptr float addrspace(2)* %222, i32 21
  %302 = load float addrspace(2)* %301, !tbaa !0
  %303 = fmul float %302, %198
  %304 = fadd float %300, %303
  %305 = getelementptr float addrspace(2)* %222, i32 22
  %306 = load float addrspace(2)* %305, !tbaa !0
  %307 = fmul float %306, %184
  %308 = fadd float %304, %307
  %309 = getelementptr float addrspace(2)* %222, i32 23
  %310 = load float addrspace(2)* %309, !tbaa !0
  %311 = fmul float %310, %205
  %312 = fadd float %308, %311
  %313 = getelementptr float addrspace(2)* %222, i32 24
  %314 = load float addrspace(2)* %313, !tbaa !0
  %315 = fmul float %314, %191
  %316 = getelementptr float addrspace(2)* %222, i32 25
  %317 = load float addrspace(2)* %316, !tbaa !0
  %318 = fmul float %317, %198
  %319 = fadd float %315, %318
  %320 = getelementptr float addrspace(2)* %222, i32 26
  %321 = load float addrspace(2)* %320, !tbaa !0
  %322 = fmul float %321, %184
  %323 = fadd float %319, %322
  %324 = getelementptr float addrspace(2)* %222, i32 27
  %325 = load float addrspace(2)* %324, !tbaa !0
  %326 = fmul float %325, %205
  %327 = fadd float %323, %326
  %328 = getelementptr float addrspace(2)* %222, i32 28
  %329 = load float addrspace(2)* %328, !tbaa !0
  %330 = fmul float %329, %191
  %331 = getelementptr float addrspace(2)* %222, i32 29
  %332 = load float addrspace(2)* %331, !tbaa !0
  %333 = fmul float %332, %198
  %334 = fadd float %330, %333
  %335 = getelementptr float addrspace(2)* %222, i32 30
  %336 = load float addrspace(2)* %335, !tbaa !0
  %337 = fmul float %336, %184
  %338 = fadd float %334, %337
  %339 = getelementptr float addrspace(2)* %222, i32 31
  %340 = load float addrspace(2)* %339, !tbaa !0
  %341 = fmul float %340, %205
  %342 = fadd float %338, %341
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %297, float %312, float %327, float %342)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %143, float %150, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %134, float %135, float %136, float %114)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %191, float %198, float %212, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %163, float %170, float %177, float %212)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %218, float %220, float %215, float %205)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: nounwind readonly
declare float @llvm.log2.f32(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.exp.(float) #3

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%101](tbaa=!"const")
	S_WAITCNT 127
	%VGPR3_VGPR4_VGPR5_VGPR6<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%122](tbaa=!"const")
	S_WAITCNT 112
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 12; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR9, %SGPR4, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 217; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 216; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR7, %SGPR5<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR11, %SGPR4<kill>, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 218; mem:LD4[%77]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR9, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 219; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 221; mem:LD4[%83]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 220; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 222; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR9, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 223; mem:LD4[%87]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 33; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 32; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR1, %SGPR4<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 225; mem:LD4[%91]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 224; mem:LD4[%89]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR7<kill>, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 226; mem:LD4[%93]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR9<kill>, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 227; mem:LD4[%95]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-use,kill>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 34; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%11]
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 35; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 37; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 36; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR5<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 38; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR5<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 39; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %SGPR4, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%221](tbaa=!"const")
	S_WAITCNT 127
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%271]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%268]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 41; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 40; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR5<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 42; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR5<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 43; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR4, %VGPR8<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%275]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 45; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 44; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR5<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 46; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR3, %SGPR5<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 47; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %SGPR4, %VGPR9<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%279]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%256]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%253]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%260]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%264]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%241]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%238]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%245]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%249]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%226]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%223]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%230]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%234]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%331]
	S_WAITCNT 15
	%VGPR8<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%328]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%335]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%339]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%316]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%313]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%320]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%324]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%301]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%298]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%305]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%309]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%286]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%283]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%290]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%294]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%115](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%67]
	S_WAITCNT 112
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 198; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 199; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR11, %SGPR0<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%57]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 194; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 195; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR11, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%VGPR8<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR9<kill>, %VGPR12<kill>, %VGPR8, %VGPR8, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 4; mem:LD16[%108](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_LOG_F32_e32 %VGPR11, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 2.200000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_EXP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_LOG_F32_e32 %VGPR10, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 2.200000e+00, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_EXP_F32_e32 %VGPR13<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_LOG_F32_e32 %VGPR9, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 2.200000e+00, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_EXP_F32_e32 %VGPR14<kill>, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR14<kill>, %VGPR13<kill>, %VGPR0<kill>, %VGPR12, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 53; mem:LD4[%51]
	S_WAITCNT 15
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 52; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR1, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 54; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 55; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %SGPR4<kill>, %VGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR4, %VGPR5, %VGPR0, %VGPR8<kill>, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR1<kill>, %VGPR2<kill>, %VGPR3<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 228; mem:LD4[%97]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR7, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 229; mem:LD4[%99]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR5<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR7<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840700
bf8c007f
e00c2000
80020300
c084070c
bf8c0070
e00c2000
80020900
c0410100
bf8c0070
c002030c
bf8c007f
d2820007
040c0909
d2820008
0410090a
c00283d9
bf8c007f
10021005
c00283d8
bf8c007f
d2820001
04040b07
d2820009
0414090b
c00203da
bf8c007f
d2820001
04040909
c00203db
bf8c007f
d2820001
04040906
c00203dd
bf8c007f
10041004
c00203dc
bf8c007f
d2820002
04080907
c00203de
bf8c007f
d2820002
04080909
c00203df
bf8c007f
d2820002
04080906
c0020321
bf8c007f
10140404
c0020320
bf8c007f
d282000a
04280901
c00203e1
bf8c007f
10101004
c00203e0
bf8c007f
d2820007
04200907
c00203e2
bf8c007f
d2820007
041c0909
c00203e3
bf8c007f
d2820003
041c0906
c0020322
bf8c007f
d2820004
04280903
c0020301
c0028323
bf8c007f
7e0a0205
d2820004
04120a04
c0028325
bf8c007f
100a0405
c0028324
bf8c007f
d2820005
04140b01
c0028326
bf8c007f
d2820005
04140b03
c0028327
bf8c007f
7e0c0205
d2820005
04160c04
c0400102
bf8c007f
c002810d
bf8c007f
100c0a05
c002810c
bf8c007f
d2820007
041a0805
c0028329
bf8c007f
100c0405
c0028328
bf8c007f
d2820006
04180b01
c002832a
bf8c007f
d2820006
04180b03
c002832b
bf8c007f
7e100205
d2820006
041a1004
c002810e
bf8c007f
d2820008
041e0c05
c002832d
bf8c007f
100e0405
c002832c
bf8c007f
d2820007
041c0b01
c002832e
bf8c007f
d2820007
041c0b03
c002832f
bf8c007f
7e120205
d2820007
041e1204
c002810f
bf8c007f
d2820008
04220e05
c0028109
bf8c007f
10120a05
c0028108
bf8c007f
d2820009
04260805
c002810a
bf8c007f
d2820009
04260c05
c002810b
bf8c007f
d2820009
04260e05
c0028105
bf8c007f
10140a05
c0028104
bf8c007f
d282000a
042a0805
c0028106
bf8c007f
d282000a
042a0c05
c0028107
bf8c007f
d282000a
042a0e05
c0028101
bf8c007f
10160a05
c0028100
bf8c007f
d282000b
042e0805
c0028102
bf8c007f
d282000b
042e0c05
c0028103
bf8c007f
d282000b
042e0e05
f80000ef
08090a0b
c002811d
bf8c000f
10100a05
c002811c
bf8c007f
d2820008
04220805
c002811e
bf8c007f
d2820008
04220c05
c002811f
bf8c007f
d2820008
04220e05
c0028119
bf8c007f
10120a05
c0028118
bf8c007f
d2820009
04260805
c002811a
bf8c007f
d2820009
04260c05
c002811b
bf8c007f
d2820009
04260e05
c0028115
bf8c007f
10140a05
c0028114
bf8c007f
d282000a
042a0805
c0028116
bf8c007f
d282000a
042a0c05
c0028117
bf8c007f
d282000a
042a0e05
c0028111
bf8c007f
10160a05
c0028110
bf8c007f
d282000b
042e0805
c0028112
bf8c007f
d282000b
042e0c05
c0000113
bf8c007f
d282000b
042e0e00
f80000ff
08090a0b
c0840708
bf8c000f
e00c2000
80020800
c00003c5
bf8c0070
10181200
c00003c4
bf8c007f
d282000c
04300108
c00003c6
bf8c007f
d282000c
0430010a
c00003c7
bf8c007f
d282000c
0430010b
c00003c1
bf8c007f
101a1200
c00003c0
bf8c007f
d282000d
04340108
c00003c2
bf8c007f
d282000d
0434010a
c00003c3
bf8c007f
d2820009
0434010b
7e100280
f800020f
08080c09
c0840704
bf8c000f
e00c2000
80020900
bf8c0770
7e004f0b
100000ff
400ccccd
7e004b00
7e1a4f0a
101a1aff
400ccccd
7e1a4b0d
7e1c4f09
101c1cff
400ccccd
7e1c4b0e
f800021f
0c000d0e
c0000335
bf8c000f
10000400
c0000334
bf8c007f
d2820000
04000101
c0000336
bf8c007f
d2820000
04000103
c0000337
bf8c007f
7e120200
d2820000
04021204
f800022f
08000504
f800023f
00030201
c00003e4
bf8c000f
d2820000
04120e00
c0000302
bf8c007f
10020c00
08020f01
c00003e5
bf8c007f
10040e00
08040b02
f80008cf
07010200
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 3
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 4
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 5
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 6
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 7
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 8
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 9
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 10
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 11
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 12
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 13
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 14
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 15
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = fmul float %46, %12
  %51 = fmul float %46, %14
  %52 = fmul float %46, %16
  %53 = fmul float %46, %18
  %54 = fmul float %47, %20
  %55 = fadd float %54, %50
  %56 = fmul float %47, %22
  %57 = fadd float %56, %51
  %58 = fmul float %47, %24
  %59 = fadd float %58, %52
  %60 = fmul float %47, %26
  %61 = fadd float %60, %53
  %62 = fmul float %48, %28
  %63 = fadd float %62, %55
  %64 = fmul float %48, %30
  %65 = fadd float %64, %57
  %66 = fmul float %48, %32
  %67 = fadd float %66, %59
  %68 = fmul float %48, %34
  %69 = fadd float %68, %61
  %70 = fmul float %49, %36
  %71 = fadd float %70, %63
  %72 = fmul float %49, %38
  %73 = fadd float %72, %65
  %74 = fmul float %49, %40
  %75 = fadd float %74, %67
  %76 = fmul float %49, %42
  %77 = fadd float %76, %69
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %71, float %73, float %75, float %77)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%43](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 12; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0820700
bf8c007f
e00c2000
80010000
c0400100
bf8c0070
c0010103
bf8c007f
10080002
c0010107
bf8c007f
d2820004
04100501
c001010b
bf8c007f
d2820004
04100502
c001010f
bf8c007f
d2820004
04100503
c0010102
bf8c007f
100a0002
c0010106
bf8c007f
d2820005
04140501
c001010a
bf8c007f
d2820005
04140502
c001010e
bf8c007f
d2820005
04140503
c0010101
bf8c007f
100c0002
c0010105
bf8c007f
d2820006
04180501
c0010109
bf8c007f
d2820006
04180502
c001010d
bf8c007f
d2820006
04180503
c0010100
bf8c007f
100e0002
c0010104
bf8c007f
d2820007
041c0501
c0010108
bf8c007f
d2820007
041c0502
c000010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
  %25 = bitcast i32 %24 to float
  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
  %27 = bitcast i32 %26 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6 in %vreg3

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8020302
c8060202
5e000101
c8060102
c80a0002
5e020302
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%16](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%9](tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use,kill>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
DCL TEMP[1], ARRAY(1), LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0].w, TEMP[0], SAMP[0], 2D
  2: MUL TEMP[0].x, TEMP[0].wwww, IN[0].wwww
  3: MOV TEMP[0].w, TEMP[0].xxxx
  4: MOV TEMP[0].xyz, IMM[0].xxxx
  5: MOV TEMP[1], TEMP[0]
  6: MOV OUT[0], TEMP[1]
  7: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %27 = bitcast float %25 to i32
  %28 = bitcast float %26 to i32
  %29 = insertelement <2 x i32> undef, i32 %27, i32 0
  %30 = insertelement <2 x i32> %29, i32 %28, i32 1
  %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %21, <16 x i8> %23, i32 2)
  %32 = extractelement <4 x float> %31, i32 3
  %33 = fmul float %32, %24
  %34 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 1.000000e+00)
  %35 = bitcast i32 %34 to float
  %36 = call i32 @llvm.SI.packf16(float 1.000000e+00, float %33)
  %37 = bitcast i32 %36 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %35, float %37, float %35, float %37)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 1.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 1.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0500
c80d0501
c8080400
c8090401
c0800300
c0c40500
bf8c007f
f0800800
00020202
c80c0300
c80d0301
bf8c0770
10000702
5e0000f2
d25e0001
0201e4f2
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL CONST[0..57]
DCL TEMP[0..5], LOCAL
  0: MOV TEMP[0].w, CONST[0].yyyy
  1: DP4 TEMP[0].x, IN[0], CONST[54]
  2: DP4 TEMP[1].x, IN[0], CONST[55]
  3: MOV TEMP[0].y, TEMP[1].xxxx
  4: DP4 TEMP[1].x, IN[0], CONST[56]
  5: MOV TEMP[0].z, TEMP[1].xxxx
  6: DP4 TEMP[1].x, TEMP[0], CONST[8]
  7: DP4 TEMP[2].x, TEMP[0], CONST[9]
  8: MOV TEMP[1].y, TEMP[2].xxxx
  9: DP4 TEMP[3].x, TEMP[0], CONST[10]
 10: MOV TEMP[1].z, TEMP[3].xxxx
 11: DP4 TEMP[0].x, TEMP[0], CONST[11]
 12: MOV TEMP[1].w, TEMP[0].xxxx
 13: MUL TEMP[4].xy, IN[1].yyyy, CONST[49].xyyy
 14: MAD TEMP[4].xy, IN[1].xxxx, CONST[48].xyyy, TEMP[4].xyyy
 15: MOV TEMP[5], TEMP[1]
 16: MAD TEMP[3].x, TEMP[3].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
 17: MOV TEMP[1].z, TEMP[3].xxxx
 18: MOV TEMP[1].y, -TEMP[2].xxxx
 19: MAD TEMP[1].xy, CONST[57].xyyy, TEMP[0].xxxx, TEMP[1].xyyy
 20: MOV OUT[3], TEMP[4]
 21: MOV OUT[0], TEMP[1]
 22: MOV OUT[2], TEMP[5]
 23: MOV_SAT OUT[1], CONST[47]
 24: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 1
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 2
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 32
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 33
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 34
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 35
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 36
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 37
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 38
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 39
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 40
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 41
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 42
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 43
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 44
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 45
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 46
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 47
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 188
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 189
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 190
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 191
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 192
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 193
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 196
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 197
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 216
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 217
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 218
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 219
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 220
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 221
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 222
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 223
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 224
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 225
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 226
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 227
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr float addrspace(2)* %10, i32 228
  %88 = load float addrspace(2)* %87, !tbaa !0
  %89 = getelementptr float addrspace(2)* %10, i32 229
  %90 = load float addrspace(2)* %89, !tbaa !0
  %91 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %92 = load <16 x i8> addrspace(2)* %91, !tbaa !0
  %93 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %92, i32 0, i32 %5)
  %94 = extractelement <4 x float> %93, i32 0
  %95 = extractelement <4 x float> %93, i32 1
  %96 = extractelement <4 x float> %93, i32 2
  %97 = extractelement <4 x float> %93, i32 3
  %98 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %99 = load <16 x i8> addrspace(2)* %98, !tbaa !0
  %100 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %99, i32 0, i32 %5)
  %101 = extractelement <4 x float> %100, i32 0
  %102 = extractelement <4 x float> %100, i32 1
  %103 = fmul float %94, %64
  %104 = fmul float %95, %66
  %105 = fadd float %103, %104
  %106 = fmul float %96, %68
  %107 = fadd float %105, %106
  %108 = fmul float %97, %70
  %109 = fadd float %107, %108
  %110 = fmul float %94, %72
  %111 = fmul float %95, %74
  %112 = fadd float %110, %111
  %113 = fmul float %96, %76
  %114 = fadd float %112, %113
  %115 = fmul float %97, %78
  %116 = fadd float %114, %115
  %117 = fmul float %94, %80
  %118 = fmul float %95, %82
  %119 = fadd float %117, %118
  %120 = fmul float %96, %84
  %121 = fadd float %119, %120
  %122 = fmul float %97, %86
  %123 = fadd float %121, %122
  %124 = fmul float %109, %16
  %125 = fmul float %116, %18
  %126 = fadd float %124, %125
  %127 = fmul float %123, %20
  %128 = fadd float %126, %127
  %129 = fmul float %12, %22
  %130 = fadd float %128, %129
  %131 = fmul float %109, %24
  %132 = fmul float %116, %26
  %133 = fadd float %131, %132
  %134 = fmul float %123, %28
  %135 = fadd float %133, %134
  %136 = fmul float %12, %30
  %137 = fadd float %135, %136
  %138 = fmul float %109, %32
  %139 = fmul float %116, %34
  %140 = fadd float %138, %139
  %141 = fmul float %123, %36
  %142 = fadd float %140, %141
  %143 = fmul float %12, %38
  %144 = fadd float %142, %143
  %145 = fmul float %109, %40
  %146 = fmul float %116, %42
  %147 = fadd float %145, %146
  %148 = fmul float %123, %44
  %149 = fadd float %147, %148
  %150 = fmul float %12, %46
  %151 = fadd float %149, %150
  %152 = fmul float %102, %60
  %153 = fmul float %102, %62
  %154 = fmul float %101, %56
  %155 = fadd float %154, %152
  %156 = fmul float %101, %58
  %157 = fadd float %156, %153
  %158 = fsub float -0.000000e+00, %151
  %159 = fmul float %144, %14
  %160 = fadd float %159, %158
  %161 = fsub float -0.000000e+00, %137
  %162 = fmul float %88, %151
  %163 = fadd float %162, %130
  %164 = fmul float %90, %151
  %165 = fadd float %164, %161
  %166 = call float @llvm.AMDIL.clamp.(float %48, float 0.000000e+00, float 1.000000e+00)
  %167 = call float @llvm.AMDIL.clamp.(float %50, float 0.000000e+00, float 1.000000e+00)
  %168 = call float @llvm.AMDIL.clamp.(float %52, float 0.000000e+00, float 1.000000e+00)
  %169 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %166, float %167, float %168, float %169)
  %170 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %171 = load float addrspace(2)* addrspace(2)* %170, !tbaa !0
  %172 = getelementptr float addrspace(2)* %171, i32 0
  %173 = load float addrspace(2)* %172, !tbaa !0
  %174 = fmul float %173, %130
  %175 = getelementptr float addrspace(2)* %171, i32 1
  %176 = load float addrspace(2)* %175, !tbaa !0
  %177 = fmul float %176, %137
  %178 = fadd float %174, %177
  %179 = getelementptr float addrspace(2)* %171, i32 2
  %180 = load float addrspace(2)* %179, !tbaa !0
  %181 = fmul float %180, %144
  %182 = fadd float %178, %181
  %183 = getelementptr float addrspace(2)* %171, i32 3
  %184 = load float addrspace(2)* %183, !tbaa !0
  %185 = fmul float %184, %151
  %186 = fadd float %182, %185
  %187 = getelementptr float addrspace(2)* %171, i32 4
  %188 = load float addrspace(2)* %187, !tbaa !0
  %189 = fmul float %188, %130
  %190 = getelementptr float addrspace(2)* %171, i32 5
  %191 = load float addrspace(2)* %190, !tbaa !0
  %192 = fmul float %191, %137
  %193 = fadd float %189, %192
  %194 = getelementptr float addrspace(2)* %171, i32 6
  %195 = load float addrspace(2)* %194, !tbaa !0
  %196 = fmul float %195, %144
  %197 = fadd float %193, %196
  %198 = getelementptr float addrspace(2)* %171, i32 7
  %199 = load float addrspace(2)* %198, !tbaa !0
  %200 = fmul float %199, %151
  %201 = fadd float %197, %200
  %202 = getelementptr float addrspace(2)* %171, i32 8
  %203 = load float addrspace(2)* %202, !tbaa !0
  %204 = fmul float %203, %130
  %205 = getelementptr float addrspace(2)* %171, i32 9
  %206 = load float addrspace(2)* %205, !tbaa !0
  %207 = fmul float %206, %137
  %208 = fadd float %204, %207
  %209 = getelementptr float addrspace(2)* %171, i32 10
  %210 = load float addrspace(2)* %209, !tbaa !0
  %211 = fmul float %210, %144
  %212 = fadd float %208, %211
  %213 = getelementptr float addrspace(2)* %171, i32 11
  %214 = load float addrspace(2)* %213, !tbaa !0
  %215 = fmul float %214, %151
  %216 = fadd float %212, %215
  %217 = getelementptr float addrspace(2)* %171, i32 12
  %218 = load float addrspace(2)* %217, !tbaa !0
  %219 = fmul float %218, %130
  %220 = getelementptr float addrspace(2)* %171, i32 13
  %221 = load float addrspace(2)* %220, !tbaa !0
  %222 = fmul float %221, %137
  %223 = fadd float %219, %222
  %224 = getelementptr float addrspace(2)* %171, i32 14
  %225 = load float addrspace(2)* %224, !tbaa !0
  %226 = fmul float %225, %144
  %227 = fadd float %223, %226
  %228 = getelementptr float addrspace(2)* %171, i32 15
  %229 = load float addrspace(2)* %228, !tbaa !0
  %230 = fmul float %229, %151
  %231 = fadd float %227, %230
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %186, float %201, float %216, float %231)
  %232 = getelementptr float addrspace(2)* %171, i32 16
  %233 = load float addrspace(2)* %232, !tbaa !0
  %234 = fmul float %233, %130
  %235 = getelementptr float addrspace(2)* %171, i32 17
  %236 = load float addrspace(2)* %235, !tbaa !0
  %237 = fmul float %236, %137
  %238 = fadd float %234, %237
  %239 = getelementptr float addrspace(2)* %171, i32 18
  %240 = load float addrspace(2)* %239, !tbaa !0
  %241 = fmul float %240, %144
  %242 = fadd float %238, %241
  %243 = getelementptr float addrspace(2)* %171, i32 19
  %244 = load float addrspace(2)* %243, !tbaa !0
  %245 = fmul float %244, %151
  %246 = fadd float %242, %245
  %247 = getelementptr float addrspace(2)* %171, i32 20
  %248 = load float addrspace(2)* %247, !tbaa !0
  %249 = fmul float %248, %130
  %250 = getelementptr float addrspace(2)* %171, i32 21
  %251 = load float addrspace(2)* %250, !tbaa !0
  %252 = fmul float %251, %137
  %253 = fadd float %249, %252
  %254 = getelementptr float addrspace(2)* %171, i32 22
  %255 = load float addrspace(2)* %254, !tbaa !0
  %256 = fmul float %255, %144
  %257 = fadd float %253, %256
  %258 = getelementptr float addrspace(2)* %171, i32 23
  %259 = load float addrspace(2)* %258, !tbaa !0
  %260 = fmul float %259, %151
  %261 = fadd float %257, %260
  %262 = getelementptr float addrspace(2)* %171, i32 24
  %263 = load float addrspace(2)* %262, !tbaa !0
  %264 = fmul float %263, %130
  %265 = getelementptr float addrspace(2)* %171, i32 25
  %266 = load float addrspace(2)* %265, !tbaa !0
  %267 = fmul float %266, %137
  %268 = fadd float %264, %267
  %269 = getelementptr float addrspace(2)* %171, i32 26
  %270 = load float addrspace(2)* %269, !tbaa !0
  %271 = fmul float %270, %144
  %272 = fadd float %268, %271
  %273 = getelementptr float addrspace(2)* %171, i32 27
  %274 = load float addrspace(2)* %273, !tbaa !0
  %275 = fmul float %274, %151
  %276 = fadd float %272, %275
  %277 = getelementptr float addrspace(2)* %171, i32 28
  %278 = load float addrspace(2)* %277, !tbaa !0
  %279 = fmul float %278, %130
  %280 = getelementptr float addrspace(2)* %171, i32 29
  %281 = load float addrspace(2)* %280, !tbaa !0
  %282 = fmul float %281, %137
  %283 = fadd float %279, %282
  %284 = getelementptr float addrspace(2)* %171, i32 30
  %285 = load float addrspace(2)* %284, !tbaa !0
  %286 = fmul float %285, %144
  %287 = fadd float %283, %286
  %288 = getelementptr float addrspace(2)* %171, i32 31
  %289 = load float addrspace(2)* %288, !tbaa !0
  %290 = fmul float %289, %151
  %291 = fadd float %287, %290
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %246, float %261, float %276, float %291)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %155, float %157, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %163, float %165, float %160, float %151)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 191; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR1<def> = V_ADD_F32_e64 %SGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 190; mem:LD4[%51]
	S_WAITCNT 127
	%VGPR2<def> = V_ADD_F32_e64 %SGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 189; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR3<def> = V_ADD_F32_e64 %SGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 188; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR4<def> = V_ADD_F32_e64 %SGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%91](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 217; mem:LD4[%65]
	S_WAITCNT 112
	%VGPR1<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 216; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 218; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 219; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR9, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 221; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 220; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 222; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 223; mem:LD4[%77]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR9, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 33; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 32; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 225; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 224; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 226; mem:LD4[%83]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 227; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR9, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 34; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%11]
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 35; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %SGPR4, %VGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 37; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 36; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR4, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 38; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 39; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR4, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%170](tbaa=!"const")
	S_WAITCNT 127
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%220]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%217]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 41; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 40; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR4, %SGPR5<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 42; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR5<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 43; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR4, %VGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%224]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR5<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 45; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 44; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR4<kill>, %SGPR5<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 46; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %SGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 47; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%228]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%205]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%202]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%209]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%213]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%190]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%187]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%194]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%198]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%175]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%172]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%179]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%183]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR8<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%280]
	S_WAITCNT 15
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%277]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%284]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%288]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%265]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%262]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%269]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%273]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%250]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%247]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%254]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%258]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%235]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%232]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%239]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%243]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR8<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 4; mem:LD16[%98](tbaa=!"const")
	S_WAITCNT 15
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%61]
	S_WAITCNT 112
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%57]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR5<kill>, %VGPR0<kill>, %VGPR6<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 228; mem:LD4[%87]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 229; mem:LD4[%89]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0410100
bf8c007f
c00203bf
bf8c007f
d2060801
02010004
c00203be
bf8c007f
d2060802
02010004
c00203bd
bf8c007f
d2060803
02010004
c00203bc
bf8c007f
d2060804
02010004
f800020f
01020304
c0840700
bf8c000f
e00c2000
80020600
c00203d9
bf8c0070
10020e04
c00203d8
bf8c007f
d2820001
04040906
c00203da
bf8c007f
d2820001
04040908
c00203db
bf8c007f
d2820004
04040909
c00203dd
bf8c007f
10020e04
c00203dc
bf8c007f
d2820001
04040906
c00203de
bf8c007f
d2820001
04040908
c00203df
bf8c007f
d2820005
04040909
c0020321
bf8c007f
10020a04
c0020320
bf8c007f
d2820001
04040904
c00203e1
bf8c007f
10040e04
c00203e0
bf8c007f
d2820002
04080906
c00203e2
bf8c007f
d2820002
04080908
c00203e3
bf8c007f
d2820006
04080909
c0020322
bf8c007f
d2820001
04040906
c0020301
c0028323
bf8c007f
7e040205
d2820001
04060404
c0028325
bf8c007f
10040a05
c0028324
bf8c007f
d2820002
04080b04
c0028326
bf8c007f
d2820002
04080b06
c0028327
bf8c007f
7e060205
d2820002
040a0604
c0400102
bf8c007f
c002810d
bf8c007f
10060405
c002810c
bf8c007f
d2820007
040e0205
c0028329
bf8c007f
10060a05
c0028328
bf8c007f
d2820003
040c0b04
c002832a
bf8c007f
d2820003
040c0b06
c002832b
bf8c007f
7e100205
d2820003
040e1004
c002810e
bf8c007f
d2820007
041e0605
c002832d
bf8c007f
100a0a05
c002832c
bf8c007f
d2820004
04140b04
c002832e
bf8c007f
d2820004
04100b06
c002832f
bf8c007f
7e0a0205
d2820004
04120a04
c002010f
bf8c007f
d2820005
041e0804
c0020109
bf8c007f
100c0404
c0020108
bf8c007f
d2820006
041a0204
c002010a
bf8c007f
d2820006
041a0604
c002010b
bf8c007f
d2820006
041a0804
c0020105
bf8c007f
100e0404
c0020104
bf8c007f
d2820007
041e0204
c0020106
bf8c007f
d2820007
041e0604
c0020107
bf8c007f
d2820007
041e0804
c0020101
bf8c007f
10100404
c0020100
bf8c007f
d2820008
04220204
c0020102
bf8c007f
d2820008
04220604
c0020103
bf8c007f
d2820008
04220804
f80000ef
05060708
c002011d
bf8c000f
100a0404
c002011c
bf8c007f
d2820005
04160204
c002011e
bf8c007f
d2820005
04160604
c002011f
bf8c007f
d2820005
04160804
c0020119
bf8c007f
100c0404
c0020118
bf8c007f
d2820006
041a0204
c002011a
bf8c007f
d2820006
041a0604
c002011b
bf8c007f
d2820006
041a0804
c0020115
bf8c007f
100e0404
c0020114
bf8c007f
d2820007
041e0204
c0020116
bf8c007f
d2820007
041e0604
c0020117
bf8c007f
d2820007
041e0804
c0020111
bf8c007f
10100404
c0020110
bf8c007f
d2820008
04220204
c0020112
bf8c007f
d2820008
04220604
c0000113
bf8c007f
d2820008
04220800
f80000ff
05060708
c0820704
bf8c000f
e00c2000
80010500
c00003c5
bf8c0070
10000c00
c00003c1
bf8c007f
d2820000
04000105
c00003c4
bf8c007f
10120c00
c00003c0
bf8c007f
d2820005
04240105
7e0c0280
f800021f
06060005
c00003e4
bf8c000f
d2820000
04060800
c0000302
bf8c007f
10020600
08020901
c00003e5
bf8c007f
10060800
08040503
f80008cf
04010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
DCL TEMP[1], ARRAY(1), LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0].w, TEMP[0], SAMP[0], 2D
  2: MUL TEMP[0].x, TEMP[0].wwww, IN[0].wwww
  3: MOV TEMP[0].w, TEMP[0].xxxx
  4: MOV TEMP[0].xyz, IMM[0].xxxx
  5: MOV TEMP[1], TEMP[0]
  6: MOV OUT[0], TEMP[1]
  7: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %27 = bitcast float %25 to i32
  %28 = bitcast float %26 to i32
  %29 = insertelement <2 x i32> undef, i32 %27, i32 0
  %30 = insertelement <2 x i32> %29, i32 %28, i32 1
  %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %21, <16 x i8> %23, i32 2)
  %32 = extractelement <4 x float> %31, i32 3
  %33 = fmul float %32, %24
  %34 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 1.000000e+00)
  %35 = bitcast i32 %34 to float
  %36 = call i32 @llvm.SI.packf16(float 1.000000e+00, float %33)
  %37 = bitcast i32 %36 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %35, float %37, float %35, float %37)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%22](tbaa=!"const")
	%SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%20](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 1.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 1.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0500
c80d0501
c8080400
c8090401
c0800300
c0c40500
bf8c007f
f0800800
00020202
c80c0300
c80d0301
bf8c0770
10000702
5e0000f2
d25e0001
0201e4f2
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL CONST[0..215]
DCL TEMP[0..7], LOCAL
DCL ADDR[0]
IMM[0] FLT32 {  765.0059,     0.0000,     0.0000,     0.0000}
IMM[1] INT32 {2, 1, 0, 0}
  0: ADD TEMP[0].xy, IN[1].xyyy, CONST[0].yyyy
  1: MUL TEMP[1].xyz, IN[2].zyxx, IMM[0].xxxx
  2: MUL TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy
  3: MOV TEMP[3].x, TEMP[1].xyzx
  4: ADD TEMP[4].x, TEMP[2].yyyy, TEMP[2].xxxx
  5: F2I TEMP[5].x, TEMP[1].yyyy
  6: UARL ADDR[0].x, TEMP[5].xxxx
  7: UARL ADDR[0].x, TEMP[5].xxxx
  8: MUL TEMP[5], TEMP[2].yyyy, CONST[ADDR[0].x+54]
  9: ADD TEMP[4].x, -TEMP[4].xxxx, CONST[0].yyyy
 10: F2I TEMP[6].x, TEMP[1].zzzz
 11: F2I TEMP[7].x, TEMP[1].xxxx
 12: UARL ADDR[0].x, TEMP[7].xxxx
 13: MAD TEMP[5], CONST[ADDR[0].x+54], TEMP[2].xxxx, TEMP[5]
 14: UARL ADDR[0].x, TEMP[6].xxxx
 15: MAD TEMP[5], CONST[ADDR[0].x+54], TEMP[4].xxxx, TEMP[5]
 16: DP4 TEMP[1].x, IN[0], TEMP[5]
 17: F2I TEMP[5].x, TEMP[1].yyyy
 18: UADD TEMP[5].x, TEMP[5].xxxx, IMM[1].xxxx
 19: F2I TEMP[6].x, TEMP[3].xxxx
 20: UADD TEMP[6].x, TEMP[6].xxxx, IMM[1].xxxx
 21: UARL ADDR[0].x, TEMP[6].xxxx
 22: MUL TEMP[6], CONST[ADDR[0].x+54], TEMP[2].xxxx
 23: UARL ADDR[0].x, TEMP[5].xxxx
 24: UARL ADDR[0].x, TEMP[5].xxxx
 25: MAD TEMP[0], TEMP[2].yyyy, CONST[ADDR[0].x+54], TEMP[6]
 26: F2I TEMP[5].x, TEMP[1].zzzz
 27: UADD TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
 28: F2I TEMP[6].x, TEMP[1].yyyy
 29: UADD TEMP[6].x, TEMP[6].xxxx, IMM[1].yyyy
 30: F2I TEMP[3].x, TEMP[3].xxxx
 31: UADD TEMP[3].x, TEMP[3].xxxx, IMM[1].yyyy
 32: UARL ADDR[0].x, TEMP[3].xxxx
 33: MUL TEMP[3], CONST[ADDR[0].x+54], TEMP[2].xxxx
 34: UARL ADDR[0].x, TEMP[6].xxxx
 35: MAD TEMP[2], TEMP[2].yyyy, CONST[ADDR[0].x+54], TEMP[3]
 36: UARL ADDR[0].x, TEMP[5].xxxx
 37: MAD TEMP[2], CONST[ADDR[0].x+54], TEMP[4].xxxx, TEMP[2]
 38: DP4 TEMP[2].x, IN[0], TEMP[2]
 39: MOV TEMP[1].y, TEMP[2].xxxx
 40: F2I TEMP[2].x, TEMP[1].zzzz
 41: UADD TEMP[2].x, TEMP[2].xxxx, IMM[1].xxxx
 42: UARL ADDR[0].x, TEMP[2].xxxx
 43: UARL ADDR[0].x, TEMP[2].xxxx
 44: MAD TEMP[2], CONST[ADDR[0].x+54], TEMP[4].xxxx, TEMP[0]
 45: DP4 TEMP[2].x, IN[0], TEMP[2]
 46: MOV TEMP[1].z, TEMP[2].xxxx
 47: MOV TEMP[1].w, CONST[0].yyyy
 48: DP4 TEMP[2].x, TEMP[1], CONST[8]
 49: DP4 TEMP[3].x, TEMP[1], CONST[9]
 50: MOV TEMP[2].y, TEMP[3].xxxx
 51: DP4 TEMP[4].x, TEMP[1], CONST[10]
 52: MOV TEMP[2].z, TEMP[4].xxxx
 53: DP4 TEMP[1].x, TEMP[1], CONST[11]
 54: MOV TEMP[2].w, TEMP[1].xxxx
 55: MUL TEMP[0].xy, IN[3].yyyy, CONST[49].xyyy
 56: MAD TEMP[0].xy, IN[3].xxxx, CONST[48].xyyy, TEMP[0].xyyy
 57: MOV TEMP[5], TEMP[2]
 58: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[1].xxxx
 59: MOV TEMP[2].z, TEMP[4].xxxx
 60: MOV TEMP[2].y, -TEMP[3].xxxx
 61: MAD TEMP[2].xy, CONST[215].xyyy, TEMP[1].xxxx, TEMP[2].xyyy
 62: MOV OUT[3], TEMP[0]
 63: MOV OUT[0], TEMP[2]
 64: MOV OUT[2], TEMP[5]
 65: MOV_SAT OUT[1], CONST[47]
 66: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 1
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 2
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 32
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 33
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 34
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 35
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 36
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 37
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 38
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 39
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 40
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 41
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 42
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 43
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 44
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 45
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 46
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 47
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 188
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 189
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 190
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 191
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 192
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 193
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 196
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 197
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 860
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 861
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
  %69 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %5)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = extractelement <4 x float> %69, i32 2
  %73 = extractelement <4 x float> %69, i32 3
  %74 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %75 = load <16 x i8> addrspace(2)* %74, !tbaa !0
  %76 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %75, i32 0, i32 %5)
  %77 = extractelement <4 x float> %76, i32 0
  %78 = extractelement <4 x float> %76, i32 1
  %79 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %80 = load <16 x i8> addrspace(2)* %79, !tbaa !0
  %81 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %80, i32 0, i32 %5)
  %82 = extractelement <4 x float> %81, i32 0
  %83 = extractelement <4 x float> %81, i32 1
  %84 = extractelement <4 x float> %81, i32 2
  %85 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %86 = load <16 x i8> addrspace(2)* %85, !tbaa !0
  %87 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %86, i32 0, i32 %5)
  %88 = extractelement <4 x float> %87, i32 0
  %89 = extractelement <4 x float> %87, i32 1
  %90 = fadd float %77, %12
  %91 = fadd float %78, %12
  %92 = fmul float %84, 0x4087E80C00000000
  %93 = fmul float %83, 0x4087E80C00000000
  %94 = fmul float %82, 0x4087E80C00000000
  %95 = fmul float %90, 0x3F00000000000000
  %96 = fmul float %91, 0x3F00000000000000
  %97 = fadd float %96, %95
  %98 = fptosi float %93 to i32
  %99 = bitcast i32 %98 to float
  %100 = bitcast float %99 to i32
  %101 = shl i32 %100, 4
  %102 = add i32 %101, 864
  %103 = udiv i32 %102, 4
  %104 = getelementptr float addrspace(2)* %10, i32 %103
  %105 = load float addrspace(2)* %104, !tbaa !0
  %106 = fmul float %96, %105
  %107 = shl i32 %100, 4
  %108 = add i32 %107, 868
  %109 = udiv i32 %108, 4
  %110 = getelementptr float addrspace(2)* %10, i32 %109
  %111 = load float addrspace(2)* %110, !tbaa !0
  %112 = fmul float %96, %111
  %113 = shl i32 %100, 4
  %114 = add i32 %113, 872
  %115 = udiv i32 %114, 4
  %116 = getelementptr float addrspace(2)* %10, i32 %115
  %117 = load float addrspace(2)* %116, !tbaa !0
  %118 = fmul float %96, %117
  %119 = shl i32 %100, 4
  %120 = add i32 %119, 876
  %121 = udiv i32 %120, 4
  %122 = getelementptr float addrspace(2)* %10, i32 %121
  %123 = load float addrspace(2)* %122, !tbaa !0
  %124 = fmul float %96, %123
  %125 = fsub float -0.000000e+00, %97
  %126 = fadd float %125, %12
  %127 = fptosi float %94 to i32
  %128 = bitcast i32 %127 to float
  %129 = fptosi float %92 to i32
  %130 = bitcast i32 %129 to float
  %131 = bitcast float %130 to i32
  %132 = shl i32 %131, 4
  %133 = add i32 %132, 864
  %134 = udiv i32 %133, 4
  %135 = getelementptr float addrspace(2)* %10, i32 %134
  %136 = load float addrspace(2)* %135, !tbaa !0
  %137 = fmul float %136, %95
  %138 = fadd float %137, %106
  %139 = shl i32 %131, 4
  %140 = add i32 %139, 868
  %141 = udiv i32 %140, 4
  %142 = getelementptr float addrspace(2)* %10, i32 %141
  %143 = load float addrspace(2)* %142, !tbaa !0
  %144 = fmul float %143, %95
  %145 = fadd float %144, %112
  %146 = shl i32 %131, 4
  %147 = add i32 %146, 872
  %148 = udiv i32 %147, 4
  %149 = getelementptr float addrspace(2)* %10, i32 %148
  %150 = load float addrspace(2)* %149, !tbaa !0
  %151 = fmul float %150, %95
  %152 = fadd float %151, %118
  %153 = shl i32 %131, 4
  %154 = add i32 %153, 876
  %155 = udiv i32 %154, 4
  %156 = getelementptr float addrspace(2)* %10, i32 %155
  %157 = load float addrspace(2)* %156, !tbaa !0
  %158 = fmul float %157, %95
  %159 = fadd float %158, %124
  %160 = bitcast float %128 to i32
  %161 = shl i32 %160, 4
  %162 = add i32 %161, 864
  %163 = udiv i32 %162, 4
  %164 = getelementptr float addrspace(2)* %10, i32 %163
  %165 = load float addrspace(2)* %164, !tbaa !0
  %166 = fmul float %165, %126
  %167 = fadd float %166, %138
  %168 = shl i32 %160, 4
  %169 = add i32 %168, 868
  %170 = udiv i32 %169, 4
  %171 = getelementptr float addrspace(2)* %10, i32 %170
  %172 = load float addrspace(2)* %171, !tbaa !0
  %173 = fmul float %172, %126
  %174 = fadd float %173, %145
  %175 = shl i32 %160, 4
  %176 = add i32 %175, 872
  %177 = udiv i32 %176, 4
  %178 = getelementptr float addrspace(2)* %10, i32 %177
  %179 = load float addrspace(2)* %178, !tbaa !0
  %180 = fmul float %179, %126
  %181 = fadd float %180, %152
  %182 = shl i32 %160, 4
  %183 = add i32 %182, 876
  %184 = udiv i32 %183, 4
  %185 = getelementptr float addrspace(2)* %10, i32 %184
  %186 = load float addrspace(2)* %185, !tbaa !0
  %187 = fmul float %186, %126
  %188 = fadd float %187, %159
  %189 = fmul float %70, %167
  %190 = fmul float %71, %174
  %191 = fadd float %189, %190
  %192 = fmul float %72, %181
  %193 = fadd float %191, %192
  %194 = fmul float %73, %188
  %195 = fadd float %193, %194
  %196 = fptosi float %93 to i32
  %197 = bitcast i32 %196 to float
  %198 = bitcast float %197 to i32
  %199 = add i32 %198, 2
  %200 = bitcast i32 %199 to float
  %201 = fptosi float %92 to i32
  %202 = bitcast i32 %201 to float
  %203 = bitcast float %202 to i32
  %204 = add i32 %203, 2
  %205 = bitcast i32 %204 to float
  %206 = bitcast float %205 to i32
  %207 = shl i32 %206, 4
  %208 = add i32 %207, 864
  %209 = udiv i32 %208, 4
  %210 = getelementptr float addrspace(2)* %10, i32 %209
  %211 = load float addrspace(2)* %210, !tbaa !0
  %212 = fmul float %211, %95
  %213 = shl i32 %206, 4
  %214 = add i32 %213, 868
  %215 = udiv i32 %214, 4
  %216 = getelementptr float addrspace(2)* %10, i32 %215
  %217 = load float addrspace(2)* %216, !tbaa !0
  %218 = fmul float %217, %95
  %219 = shl i32 %206, 4
  %220 = add i32 %219, 872
  %221 = udiv i32 %220, 4
  %222 = getelementptr float addrspace(2)* %10, i32 %221
  %223 = load float addrspace(2)* %222, !tbaa !0
  %224 = fmul float %223, %95
  %225 = shl i32 %206, 4
  %226 = add i32 %225, 876
  %227 = udiv i32 %226, 4
  %228 = getelementptr float addrspace(2)* %10, i32 %227
  %229 = load float addrspace(2)* %228, !tbaa !0
  %230 = fmul float %229, %95
  %231 = bitcast float %200 to i32
  %232 = shl i32 %231, 4
  %233 = add i32 %232, 864
  %234 = udiv i32 %233, 4
  %235 = getelementptr float addrspace(2)* %10, i32 %234
  %236 = load float addrspace(2)* %235, !tbaa !0
  %237 = fmul float %96, %236
  %238 = fadd float %237, %212
  %239 = shl i32 %231, 4
  %240 = add i32 %239, 868
  %241 = udiv i32 %240, 4
  %242 = getelementptr float addrspace(2)* %10, i32 %241
  %243 = load float addrspace(2)* %242, !tbaa !0
  %244 = fmul float %96, %243
  %245 = fadd float %244, %218
  %246 = shl i32 %231, 4
  %247 = add i32 %246, 872
  %248 = udiv i32 %247, 4
  %249 = getelementptr float addrspace(2)* %10, i32 %248
  %250 = load float addrspace(2)* %249, !tbaa !0
  %251 = fmul float %96, %250
  %252 = fadd float %251, %224
  %253 = shl i32 %231, 4
  %254 = add i32 %253, 876
  %255 = udiv i32 %254, 4
  %256 = getelementptr float addrspace(2)* %10, i32 %255
  %257 = load float addrspace(2)* %256, !tbaa !0
  %258 = fmul float %96, %257
  %259 = fadd float %258, %230
  %260 = fptosi float %94 to i32
  %261 = bitcast i32 %260 to float
  %262 = bitcast float %261 to i32
  %263 = add i32 %262, 1
  %264 = bitcast i32 %263 to float
  %265 = fptosi float %93 to i32
  %266 = bitcast i32 %265 to float
  %267 = bitcast float %266 to i32
  %268 = add i32 %267, 1
  %269 = bitcast i32 %268 to float
  %270 = fptosi float %92 to i32
  %271 = bitcast i32 %270 to float
  %272 = bitcast float %271 to i32
  %273 = add i32 %272, 1
  %274 = bitcast i32 %273 to float
  %275 = bitcast float %274 to i32
  %276 = shl i32 %275, 4
  %277 = add i32 %276, 864
  %278 = udiv i32 %277, 4
  %279 = getelementptr float addrspace(2)* %10, i32 %278
  %280 = load float addrspace(2)* %279, !tbaa !0
  %281 = fmul float %280, %95
  %282 = shl i32 %275, 4
  %283 = add i32 %282, 868
  %284 = udiv i32 %283, 4
  %285 = getelementptr float addrspace(2)* %10, i32 %284
  %286 = load float addrspace(2)* %285, !tbaa !0
  %287 = fmul float %286, %95
  %288 = shl i32 %275, 4
  %289 = add i32 %288, 872
  %290 = udiv i32 %289, 4
  %291 = getelementptr float addrspace(2)* %10, i32 %290
  %292 = load float addrspace(2)* %291, !tbaa !0
  %293 = fmul float %292, %95
  %294 = shl i32 %275, 4
  %295 = add i32 %294, 876
  %296 = udiv i32 %295, 4
  %297 = getelementptr float addrspace(2)* %10, i32 %296
  %298 = load float addrspace(2)* %297, !tbaa !0
  %299 = fmul float %298, %95
  %300 = bitcast float %269 to i32
  %301 = shl i32 %300, 4
  %302 = add i32 %301, 864
  %303 = udiv i32 %302, 4
  %304 = getelementptr float addrspace(2)* %10, i32 %303
  %305 = load float addrspace(2)* %304, !tbaa !0
  %306 = fmul float %96, %305
  %307 = fadd float %306, %281
  %308 = shl i32 %300, 4
  %309 = add i32 %308, 868
  %310 = udiv i32 %309, 4
  %311 = getelementptr float addrspace(2)* %10, i32 %310
  %312 = load float addrspace(2)* %311, !tbaa !0
  %313 = fmul float %96, %312
  %314 = fadd float %313, %287
  %315 = shl i32 %300, 4
  %316 = add i32 %315, 872
  %317 = udiv i32 %316, 4
  %318 = getelementptr float addrspace(2)* %10, i32 %317
  %319 = load float addrspace(2)* %318, !tbaa !0
  %320 = fmul float %96, %319
  %321 = fadd float %320, %293
  %322 = shl i32 %300, 4
  %323 = add i32 %322, 876
  %324 = udiv i32 %323, 4
  %325 = getelementptr float addrspace(2)* %10, i32 %324
  %326 = load float addrspace(2)* %325, !tbaa !0
  %327 = fmul float %96, %326
  %328 = fadd float %327, %299
  %329 = bitcast float %264 to i32
  %330 = shl i32 %329, 4
  %331 = add i32 %330, 864
  %332 = udiv i32 %331, 4
  %333 = getelementptr float addrspace(2)* %10, i32 %332
  %334 = load float addrspace(2)* %333, !tbaa !0
  %335 = fmul float %334, %126
  %336 = fadd float %335, %307
  %337 = shl i32 %329, 4
  %338 = add i32 %337, 868
  %339 = udiv i32 %338, 4
  %340 = getelementptr float addrspace(2)* %10, i32 %339
  %341 = load float addrspace(2)* %340, !tbaa !0
  %342 = fmul float %341, %126
  %343 = fadd float %342, %314
  %344 = shl i32 %329, 4
  %345 = add i32 %344, 872
  %346 = udiv i32 %345, 4
  %347 = getelementptr float addrspace(2)* %10, i32 %346
  %348 = load float addrspace(2)* %347, !tbaa !0
  %349 = fmul float %348, %126
  %350 = fadd float %349, %321
  %351 = shl i32 %329, 4
  %352 = add i32 %351, 876
  %353 = udiv i32 %352, 4
  %354 = getelementptr float addrspace(2)* %10, i32 %353
  %355 = load float addrspace(2)* %354, !tbaa !0
  %356 = fmul float %355, %126
  %357 = fadd float %356, %328
  %358 = fmul float %70, %336
  %359 = fmul float %71, %343
  %360 = fadd float %358, %359
  %361 = fmul float %72, %350
  %362 = fadd float %360, %361
  %363 = fmul float %73, %357
  %364 = fadd float %362, %363
  %365 = fptosi float %94 to i32
  %366 = bitcast i32 %365 to float
  %367 = bitcast float %366 to i32
  %368 = add i32 %367, 2
  %369 = bitcast i32 %368 to float
  %370 = bitcast float %369 to i32
  %371 = shl i32 %370, 4
  %372 = add i32 %371, 864
  %373 = udiv i32 %372, 4
  %374 = getelementptr float addrspace(2)* %10, i32 %373
  %375 = load float addrspace(2)* %374, !tbaa !0
  %376 = fmul float %375, %126
  %377 = fadd float %376, %238
  %378 = shl i32 %370, 4
  %379 = add i32 %378, 868
  %380 = udiv i32 %379, 4
  %381 = getelementptr float addrspace(2)* %10, i32 %380
  %382 = load float addrspace(2)* %381, !tbaa !0
  %383 = fmul float %382, %126
  %384 = fadd float %383, %245
  %385 = shl i32 %370, 4
  %386 = add i32 %385, 872
  %387 = udiv i32 %386, 4
  %388 = getelementptr float addrspace(2)* %10, i32 %387
  %389 = load float addrspace(2)* %388, !tbaa !0
  %390 = fmul float %389, %126
  %391 = fadd float %390, %252
  %392 = shl i32 %370, 4
  %393 = add i32 %392, 876
  %394 = udiv i32 %393, 4
  %395 = getelementptr float addrspace(2)* %10, i32 %394
  %396 = load float addrspace(2)* %395, !tbaa !0
  %397 = fmul float %396, %126
  %398 = fadd float %397, %259
  %399 = fmul float %70, %377
  %400 = fmul float %71, %384
  %401 = fadd float %399, %400
  %402 = fmul float %72, %391
  %403 = fadd float %401, %402
  %404 = fmul float %73, %398
  %405 = fadd float %403, %404
  %406 = fmul float %195, %16
  %407 = fmul float %364, %18
  %408 = fadd float %406, %407
  %409 = fmul float %405, %20
  %410 = fadd float %408, %409
  %411 = fmul float %12, %22
  %412 = fadd float %410, %411
  %413 = fmul float %195, %24
  %414 = fmul float %364, %26
  %415 = fadd float %413, %414
  %416 = fmul float %405, %28
  %417 = fadd float %415, %416
  %418 = fmul float %12, %30
  %419 = fadd float %417, %418
  %420 = fmul float %195, %32
  %421 = fmul float %364, %34
  %422 = fadd float %420, %421
  %423 = fmul float %405, %36
  %424 = fadd float %422, %423
  %425 = fmul float %12, %38
  %426 = fadd float %424, %425
  %427 = fmul float %195, %40
  %428 = fmul float %364, %42
  %429 = fadd float %427, %428
  %430 = fmul float %405, %44
  %431 = fadd float %429, %430
  %432 = fmul float %12, %46
  %433 = fadd float %431, %432
  %434 = fmul float %89, %60
  %435 = fmul float %89, %62
  %436 = fmul float %88, %56
  %437 = fadd float %436, %434
  %438 = fmul float %88, %58
  %439 = fadd float %438, %435
  %440 = fsub float -0.000000e+00, %433
  %441 = fmul float %426, %14
  %442 = fadd float %441, %440
  %443 = fsub float -0.000000e+00, %419
  %444 = fmul float %64, %433
  %445 = fadd float %444, %412
  %446 = fmul float %66, %433
  %447 = fadd float %446, %443
  %448 = call float @llvm.AMDIL.clamp.(float %48, float 0.000000e+00, float 1.000000e+00)
  %449 = call float @llvm.AMDIL.clamp.(float %50, float 0.000000e+00, float 1.000000e+00)
  %450 = call float @llvm.AMDIL.clamp.(float %52, float 0.000000e+00, float 1.000000e+00)
  %451 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %448, float %449, float %450, float %451)
  %452 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %453 = load float addrspace(2)* addrspace(2)* %452, !tbaa !0
  %454 = getelementptr float addrspace(2)* %453, i32 0
  %455 = load float addrspace(2)* %454, !tbaa !0
  %456 = fmul float %455, %412
  %457 = getelementptr float addrspace(2)* %453, i32 1
  %458 = load float addrspace(2)* %457, !tbaa !0
  %459 = fmul float %458, %419
  %460 = fadd float %456, %459
  %461 = getelementptr float addrspace(2)* %453, i32 2
  %462 = load float addrspace(2)* %461, !tbaa !0
  %463 = fmul float %462, %426
  %464 = fadd float %460, %463
  %465 = getelementptr float addrspace(2)* %453, i32 3
  %466 = load float addrspace(2)* %465, !tbaa !0
  %467 = fmul float %466, %433
  %468 = fadd float %464, %467
  %469 = getelementptr float addrspace(2)* %453, i32 4
  %470 = load float addrspace(2)* %469, !tbaa !0
  %471 = fmul float %470, %412
  %472 = getelementptr float addrspace(2)* %453, i32 5
  %473 = load float addrspace(2)* %472, !tbaa !0
  %474 = fmul float %473, %419
  %475 = fadd float %471, %474
  %476 = getelementptr float addrspace(2)* %453, i32 6
  %477 = load float addrspace(2)* %476, !tbaa !0
  %478 = fmul float %477, %426
  %479 = fadd float %475, %478
  %480 = getelementptr float addrspace(2)* %453, i32 7
  %481 = load float addrspace(2)* %480, !tbaa !0
  %482 = fmul float %481, %433
  %483 = fadd float %479, %482
  %484 = getelementptr float addrspace(2)* %453, i32 8
  %485 = load float addrspace(2)* %484, !tbaa !0
  %486 = fmul float %485, %412
  %487 = getelementptr float addrspace(2)* %453, i32 9
  %488 = load float addrspace(2)* %487, !tbaa !0
  %489 = fmul float %488, %419
  %490 = fadd float %486, %489
  %491 = getelementptr float addrspace(2)* %453, i32 10
  %492 = load float addrspace(2)* %491, !tbaa !0
  %493 = fmul float %492, %426
  %494 = fadd float %490, %493
  %495 = getelementptr float addrspace(2)* %453, i32 11
  %496 = load float addrspace(2)* %495, !tbaa !0
  %497 = fmul float %496, %433
  %498 = fadd float %494, %497
  %499 = getelementptr float addrspace(2)* %453, i32 12
  %500 = load float addrspace(2)* %499, !tbaa !0
  %501 = fmul float %500, %412
  %502 = getelementptr float addrspace(2)* %453, i32 13
  %503 = load float addrspace(2)* %502, !tbaa !0
  %504 = fmul float %503, %419
  %505 = fadd float %501, %504
  %506 = getelementptr float addrspace(2)* %453, i32 14
  %507 = load float addrspace(2)* %506, !tbaa !0
  %508 = fmul float %507, %426
  %509 = fadd float %505, %508
  %510 = getelementptr float addrspace(2)* %453, i32 15
  %511 = load float addrspace(2)* %510, !tbaa !0
  %512 = fmul float %511, %433
  %513 = fadd float %509, %512
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %468, float %483, float %498, float %513)
  %514 = getelementptr float addrspace(2)* %453, i32 16
  %515 = load float addrspace(2)* %514, !tbaa !0
  %516 = fmul float %515, %412
  %517 = getelementptr float addrspace(2)* %453, i32 17
  %518 = load float addrspace(2)* %517, !tbaa !0
  %519 = fmul float %518, %419
  %520 = fadd float %516, %519
  %521 = getelementptr float addrspace(2)* %453, i32 18
  %522 = load float addrspace(2)* %521, !tbaa !0
  %523 = fmul float %522, %426
  %524 = fadd float %520, %523
  %525 = getelementptr float addrspace(2)* %453, i32 19
  %526 = load float addrspace(2)* %525, !tbaa !0
  %527 = fmul float %526, %433
  %528 = fadd float %524, %527
  %529 = getelementptr float addrspace(2)* %453, i32 20
  %530 = load float addrspace(2)* %529, !tbaa !0
  %531 = fmul float %530, %412
  %532 = getelementptr float addrspace(2)* %453, i32 21
  %533 = load float addrspace(2)* %532, !tbaa !0
  %534 = fmul float %533, %419
  %535 = fadd float %531, %534
  %536 = getelementptr float addrspace(2)* %453, i32 22
  %537 = load float addrspace(2)* %536, !tbaa !0
  %538 = fmul float %537, %426
  %539 = fadd float %535, %538
  %540 = getelementptr float addrspace(2)* %453, i32 23
  %541 = load float addrspace(2)* %540, !tbaa !0
  %542 = fmul float %541, %433
  %543 = fadd float %539, %542
  %544 = getelementptr float addrspace(2)* %453, i32 24
  %545 = load float addrspace(2)* %544, !tbaa !0
  %546 = fmul float %545, %412
  %547 = getelementptr float addrspace(2)* %453, i32 25
  %548 = load float addrspace(2)* %547, !tbaa !0
  %549 = fmul float %548, %419
  %550 = fadd float %546, %549
  %551 = getelementptr float addrspace(2)* %453, i32 26
  %552 = load float addrspace(2)* %551, !tbaa !0
  %553 = fmul float %552, %426
  %554 = fadd float %550, %553
  %555 = getelementptr float addrspace(2)* %453, i32 27
  %556 = load float addrspace(2)* %555, !tbaa !0
  %557 = fmul float %556, %433
  %558 = fadd float %554, %557
  %559 = getelementptr float addrspace(2)* %453, i32 28
  %560 = load float addrspace(2)* %559, !tbaa !0
  %561 = fmul float %560, %412
  %562 = getelementptr float addrspace(2)* %453, i32 29
  %563 = load float addrspace(2)* %562, !tbaa !0
  %564 = fmul float %563, %419
  %565 = fadd float %561, %564
  %566 = getelementptr float addrspace(2)* %453, i32 30
  %567 = load float addrspace(2)* %566, !tbaa !0
  %568 = fmul float %567, %426
  %569 = fadd float %565, %568
  %570 = getelementptr float addrspace(2)* %453, i32 31
  %571 = load float addrspace(2)* %570, !tbaa !0
  %572 = fmul float %571, %433
  %573 = fadd float %569, %572
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %528, float %543, float %558, float %573)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %437, float %439, float %252, float %259)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %445, float %447, float %442, float %433)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 191; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR1<def> = V_ADD_F32_e64 %SGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 190; mem:LD4[%51]
	S_WAITCNT 127
	%VGPR2<def> = V_ADD_F32_e64 %SGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 189; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR3<def> = V_ADD_F32_e64 %SGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 188; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR4<def> = V_ADD_F32_e64 %SGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%79](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR1<def> = V_MUL_F32_e32 7.650059e+02, %VGPR7, %EXEC<imp-use>
	%VGPR10<def> = V_CVT_I32_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_LSHLREV_B32_e32 4, %VGPR10, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_I32_e32 864, %VGPR11, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR1<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-def>
	%VGPR2<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR3_VGPR4<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = S_MOV_B64 %SGPR2_SGPR3, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR10<def> = S_MOV_B32 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR11<def> = S_MOV_B32 61440, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%VGPR5<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR3_VGPR4<kill>, 0, %EXEC<imp-use>; mem:LD4[%104]
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%74](tbaa=!"const")
	S_WAITCNT 112
	%VGPR15_VGPR16_VGPR17_VGPR18<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%11]
	S_WAITCNT 112
	%VGPR4<def> = V_ADD_F32_e32 %SGPR4, %VGPR16, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 3.051758e-05, %VGPR4, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR3, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 7.650059e+02, %VGPR8, %EXEC<imp-use>
	%VGPR13<def> = V_CVT_I32_F32_e32 %VGPR5<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_LSHLREV_B32_e32 4, %VGPR13, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 864, %VGPR14, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR5<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR19_VGPR20<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR19<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR19_VGPR20<kill>, 0, %EXEC<imp-use>; mem:LD4[%135]
	%VGPR5<def> = V_ADD_F32_e32 %SGPR4, %VGPR15, %EXEC<imp-use>, %VGPR15_VGPR16_VGPR17_VGPR18<imp-use,kill>
	%VGPR5<def> = V_MUL_F32_e32 3.051758e-05, %VGPR5<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR16<def> = V_MAD_F32 %VGPR19<kill>, %VGPR5, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 3.051758e-05, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR4<kill>, %VGPR12<kill>, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_SUB_F32_e32 %SGPR4, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 7.650059e+02, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%VGPR12<def> = V_CVT_I32_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_LSHLREV_B32_e32 4, %VGPR12, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_I32_e32 864, %VGPR15, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR6<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR6_VGPR7<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR6<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR6_VGPR7<kill>, 0, %EXEC<imp-use>; mem:LD4[%164]
	S_WAITCNT 1904
	%VGPR16<def> = V_MAD_F32 %VGPR6<kill>, %VGPR4, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_I32_e32 868, %VGPR11, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR6<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR6_VGPR7<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR6<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR6_VGPR7<kill>, 0, %EXEC<imp-use>; mem:LD4[%110]
	S_WAITCNT 1904
	%VGPR6<def> = V_MUL_F32_e32 %VGPR3, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_I32_e32 868, %VGPR14, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR7<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR7_VGPR8<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR7<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR7_VGPR8<kill>, 0, %EXEC<imp-use>; mem:LD4[%142]
	S_WAITCNT 1904
	%VGPR6<def> = V_MAD_F32 %VGPR7<kill>, %VGPR5, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_I32_e32 868, %VGPR15, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR7<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR7_VGPR8<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR7<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR7_VGPR8<kill>, 0, %EXEC<imp-use>; mem:LD4[%171]
	S_WAITCNT 1904
	%VGPR17<def> = V_MAD_F32 %VGPR7<kill>, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%67](tbaa=!"const")
	S_WAITCNT 127
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR17<def> = V_MUL_F32_e32 %VGPR7, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR6, %VGPR16<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_I32_e32 872, %VGPR11, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR17<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR17_VGPR18<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR17<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR17_VGPR18<kill>, 0, %EXEC<imp-use>; mem:LD4[%116]
	S_WAITCNT 1904
	%VGPR17<def> = V_MUL_F32_e32 %VGPR3, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_I32_e32 872, %VGPR14, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR18<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR18<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%149]
	S_WAITCNT 1904
	%VGPR17<def> = V_MAD_F32 %VGPR18<kill>, %VGPR5, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_I32_e32 872, %VGPR15, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR18<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR18<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%178]
	S_WAITCNT 1904
	%VGPR17<def> = V_MAD_F32 %VGPR18<kill>, %VGPR4, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR8, %VGPR17<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_I32_e32 876, %VGPR11<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR11<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR17_VGPR18<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR11<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR17_VGPR18<kill>, 0, %EXEC<imp-use>; mem:LD4[%122]
	S_WAITCNT 1904
	%VGPR11<def> = V_MUL_F32_e32 %VGPR3, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_I32_e32 876, %VGPR14<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR14<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR17_VGPR18<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR17_VGPR18<kill>, 0, %EXEC<imp-use>; mem:LD4[%156]
	S_WAITCNT 1904
	%VGPR11<def> = V_MAD_F32 %VGPR14<kill>, %VGPR5, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_I32_e32 876, %VGPR15<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR14<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR14_VGPR15<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR14_VGPR15<kill>, 0, %EXEC<imp-use>; mem:LD4[%185]
	S_WAITCNT 1904
	%VGPR11<def> = V_MAD_F32 %VGPR14<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR9, %VGPR11<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_I32_e32 1, %VGPR13, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR14<def> = V_LSHLREV_B32_e32 4, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_I32_e32 864, %VGPR14, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR15<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR15_VGPR16<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR15_VGPR16<kill>, 0, %EXEC<imp-use>; mem:LD4[%279]
	S_WAITCNT 1904
	%VGPR16<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_I32_e32 1, %VGPR10, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR15<def> = V_LSHLREV_B32_e32 4, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_I32_e32 864, %VGPR15, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR17<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR17_VGPR18<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR17<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR17_VGPR18<kill>, 0, %EXEC<imp-use>; mem:LD4[%304]
	S_WAITCNT 1904
	%VGPR17<def> = V_MAD_F32 %VGPR3, %VGPR17<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_I32_e32 1, %VGPR12, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR16<def> = V_LSHLREV_B32_e32 4, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_I32_e32 864, %VGPR16, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR18<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR18<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%333]
	S_WAITCNT 1904
	%VGPR17<def> = V_MAD_F32 %VGPR18<kill>, %VGPR4, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_I32_e32 868, %VGPR14, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR18<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR18<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%285]
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %VGPR18<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_I32_e32 868, %VGPR15, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR19<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR19_VGPR20<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR19<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR19_VGPR20<kill>, 0, %EXEC<imp-use>; mem:LD4[%311]
	S_WAITCNT 1904
	%VGPR18<def> = V_MAD_F32 %VGPR3, %VGPR19<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_I32_e32 868, %VGPR16, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR19<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR19_VGPR20<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR19<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR19_VGPR20<kill>, 0, %EXEC<imp-use>; mem:LD4[%340]
	S_WAITCNT 1904
	%VGPR18<def> = V_MAD_F32 %VGPR19<kill>, %VGPR4, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR7, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR6, %VGPR17<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_I32_e32 872, %VGPR14, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR18<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR18<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%291]
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %VGPR18<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_I32_e32 872, %VGPR15, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR19<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR19_VGPR20<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR19<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR19_VGPR20<kill>, 0, %EXEC<imp-use>; mem:LD4[%318]
	S_WAITCNT 1904
	%VGPR18<def> = V_MAD_F32 %VGPR3, %VGPR19<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_I32_e32 872, %VGPR16, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR19<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR19_VGPR20<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR19<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR19_VGPR20<kill>, 0, %EXEC<imp-use>; mem:LD4[%347]
	S_WAITCNT 1904
	%VGPR18<def> = V_MAD_F32 %VGPR19<kill>, %VGPR4, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR8, %VGPR18<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_I32_e32 876, %VGPR14<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR14<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%297]
	S_WAITCNT 1904
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_I32_e32 876, %VGPR15<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR15<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%325]
	S_WAITCNT 1904
	%VGPR14<def> = V_MAD_F32 %VGPR3, %VGPR15<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_I32_e32 876, %VGPR16<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR15<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR15_VGPR16<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR15_VGPR16<kill>, 0, %EXEC<imp-use>; mem:LD4[%354]
	S_WAITCNT 1904
	%VGPR14<def> = V_MAD_F32 %VGPR15<kill>, %VGPR4, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR9, %VGPR14<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 33; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR14, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 32; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR11, %SGPR5<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 2, %VGPR13<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR13<def> = V_LSHLREV_B32_e32 4, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_I32_e32 864, %VGPR13, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR16<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR16_VGPR17<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR16<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR16_VGPR17<kill>, 0, %EXEC<imp-use>; mem:LD4[%210]
	S_WAITCNT 1904
	%VGPR17<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_I32_e32 2, %VGPR10<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR16<def> = V_LSHLREV_B32_e32 4, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_I32_e32 864, %VGPR16, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR10<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR10<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%235]
	S_WAITCNT 1904
	%VGPR10<def> = V_MAD_F32 %VGPR3, %VGPR10<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_I32_e32 2, %VGPR12<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR12<def> = V_LSHLREV_B32_e32 4, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_I32_e32 864, %VGPR12, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR17<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR17_VGPR18<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR17<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR17_VGPR18<kill>, 0, %EXEC<imp-use>; mem:LD4[%374]
	S_WAITCNT 1904
	%VGPR10<def> = V_MAD_F32 %VGPR17<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_I32_e32 868, %VGPR13, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR17<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR17_VGPR18<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR17<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR17_VGPR18<kill>, 0, %EXEC<imp-use>; mem:LD4[%216]
	S_WAITCNT 1904
	%VGPR17<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_I32_e32 868, %VGPR16, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR18<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR18<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%242]
	S_WAITCNT 1904
	%VGPR17<def> = V_MAD_F32 %VGPR3, %VGPR18<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_I32_e32 868, %VGPR12, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR18<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR18<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%381]
	S_WAITCNT 1904
	%VGPR17<def> = V_MAD_F32 %VGPR18<kill>, %VGPR4, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR7, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR6, %VGPR10<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_I32_e32 872, %VGPR13, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR10<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR10<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%222]
	S_WAITCNT 1904
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_I32_e32 872, %VGPR16, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR18<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR18<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%249]
	S_WAITCNT 1904
	%VGPR10<def> = V_MAD_F32 %VGPR3, %VGPR18<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_I32_e32 872, %VGPR12, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR18<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR18<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%388]
	S_WAITCNT 1904
	%VGPR18<def> = V_MAD_F32 %VGPR18<kill>, %VGPR4, %VGPR10, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR8, %VGPR18<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 876, %VGPR13<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR13<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR13<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%228]
	S_WAITCNT 1904
	%VGPR5<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 876, %VGPR16<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR13<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR18_VGPR19<def> = V_LSHL_B64 %VGPR1_VGPR2, 2, %EXEC<imp-use>
	%VGPR13<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR18_VGPR19<kill>, 0, %EXEC<imp-use>; mem:LD4[%256]
	S_WAITCNT 1904
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %VGPR13<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 876, %VGPR12<kill>, %VCC<imp-def,dead>, %EXEC<imp-use>
	%VGPR1<def> = V_LSHRREV_B32_e32 2, %VGPR5<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR1_VGPR2<def> = V_LSHL_B64 %VGPR1_VGPR2<kill>, 2, %EXEC<imp-use>
	%VGPR1<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR1_VGPR2<kill>, 0, %EXEC<imp-use>; mem:LD4[%395]
	S_WAITCNT 1904
	%VGPR1<def> = V_MAD_F32 %VGPR1<kill>, %VGPR4<kill>, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR9, %VGPR1<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 34; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR5, %SGPR5<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 35; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %SGPR4, %VGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 37; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR14, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 36; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR11, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 38; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 39; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR4, %VGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%452](tbaa=!"const")
	S_WAITCNT 127
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%502]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%499]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 41; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR14, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 40; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR11, %SGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 42; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR5, %SGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 43; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4, %VGPR7<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%506]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 45; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 44; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR11<kill>, %SGPR5<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 46; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR5<kill>, %SGPR5<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 47; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR7<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%510]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%487]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%484]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%491]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%495]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%472]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%469]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%476]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%480]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%457]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%454]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%461]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%465]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR9<kill>, %VGPR8<kill>, %VGPR7<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%562]
	S_WAITCNT 15
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%559]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%566]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%570]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%547]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%544]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%551]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%555]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%532]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%529]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%536]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%540]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%517]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%514]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%521]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%525]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR9<kill>, %VGPR8<kill>, %VGPR7<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 12; mem:LD16[%85](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%61]
	S_WAITCNT 112
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%57]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	EXP 15, 33, 0, 0, 0, %VGPR6<kill>, %VGPR0<kill>, %VGPR10<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_MOV_B32 3440
	%SGPR0<def> = S_LOAD_DWORD_SGPR %SGPR2_SGPR3, %SGPR0<kill>; mem:LD4[%63]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_MOV_B32 3444
	%SGPR0<def> = S_LOAD_DWORD_SGPR %SGPR2_SGPR3<kill>, %SGPR0<kill>; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR5<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0410100
bf8c007f
c00203bf
bf8c007f
d2060801
02010004
c00203be
bf8c007f
d2060802
02010004
c00203bd
bf8c007f
d2060803
02010004
c00203bc
bf8c007f
d2060804
02010004
f800020f
01020304
c0840708
bf8c000f
e00c2000
80020600
bf8c0770
10020eff
443f4060
7e141101
34161484
4a0216ff
00000360
2c020282
7e040280
d2c20003
02010501
be880402
be8a0380
be8b03ff
0000f000
e0308000
80020503
c0860704
bf8c0070
e00c2000
80030f00
c0020301
bf8c0070
06082004
100608ff
38000000
10180b03
100a10ff
443f4060
7e1a1105
341c1a84
4a0a1cff
00000360
2c020a82
d2c20013
02010501
e0308000
80021313
060a1e04
100a0aff
38000000
bf8c0770
d2820010
04320b13
7e1802ff
38000000
d2820004
04161904
08080804
100c0cff
443f4060
7e181106
341e1884
4a0c1eff
00000360
2c020c82
d2c20006
02010501
e0308000
80020606
bf8c0770
d2820010
04420906
4a0c16ff
00000364
2c020c82
d2c20006
02010501
e0308000
80020606
bf8c0770
100c0d03
4a0e1cff
00000364
2c020e82
d2c20007
02010501
e0308000
80020707
bf8c0770
d2820006
041a0b07
4a0e1eff
00000364
2c020e82
d2c20007
02010501
e0308000
80020707
bf8c0770
d2820011
041a0907
c0860700
bf8c007f
e00c2000
80030600
bf8c0770
10222307
d2820010
04462106
4a2216ff
00000368
2c022282
d2c20011
02010501
e0308000
80021111
bf8c0770
10222303
4a241cff
00000368
2c022482
d2c20012
02010501
e0308000
80021212
bf8c0770
d2820011
04460b12
4a241eff
00000368
2c022482
d2c20012
02010501
e0308000
80021212
bf8c0770
d2820011
04460912
d2820010
04422308
4a1616ff
0000036c
2c021682
d2c20011
02010501
e0308000
80020b11
bf8c0770
10161703
4a1c1cff
0000036c
2c021c82
d2c20011
02010501
e0308000
80020e11
bf8c0770
d282000b
042e0b0e
4a1c1eff
0000036c
2c021c82
d2c2000e
02010501
e0308000
80020e0e
bf8c0770
d282000b
042e090e
d282000b
04421709
4a1c1a81
341c1c84
4a1e1cff
00000360
2c021e82
d2c2000f
02010501
e0308000
80020f0f
bf8c0770
10200b0f
4a1e1481
341e1e84
4a221eff
00000360
2c022282
d2c20011
02010501
e0308000
80021111
bf8c0770
d2820011
04422303
4a201881
34202084
4a2420ff
00000360
2c022482
d2c20012
02010501
e0308000
80021212
bf8c0770
d2820011
04460912
4a241cff
00000364
2c022482
d2c20012
02010501
e0308000
80021212
bf8c0770
10240b12
4a261eff
00000364
2c022682
d2c20013
02010501
e0308000
80021313
bf8c0770
d2820012
044a2703
4a2620ff
00000364
2c022682
d2c20013
02010501
e0308000
80021313
bf8c0770
d2820012
044a0913
10242507
d2820011
044a2306
4a241cff
00000368
2c022482
d2c20012
02010501
e0308000
80021212
bf8c0770
10240b12
4a261eff
00000368
2c022682
d2c20013
02010501
e0308000
80021313
bf8c0770
d2820012
044a2703
4a2620ff
00000368
2c022682
d2c20013
02010501
e0308000
80021313
bf8c0770
d2820012
044a0913
d2820011
04462508
4a1c1cff
0000036c
2c021c82
d2c20012
02010501
e0308000
80020e12
bf8c0770
101c0b0e
4a1e1eff
0000036c
2c021e82
d2c20012
02010501
e0308000
80020f12
bf8c0770
d282000e
043a1f03
4a1e20ff
0000036c
2c021e82
d2c2000f
02010501
e0308000
80020f0f
bf8c0770
d282000e
043a090f
d282000e
04461d09
c0028321
bf8c007f
101e1c05
c0028320
bf8c007f
d282000f
043c0b0b
4a1a1a82
341a1a84
4a201aff
00000360
2c022082
d2c20010
02010501
e0308000
80021010
bf8c0770
10220b10
4a141482
34201484
4a1420ff
00000360
2c021482
d2c20012
02010501
e0308000
80020a12
bf8c0770
d282000a
04461503
4a181882
34181884
4a2218ff
00000360
2c022282
d2c20011
02010501
e0308000
80021111
bf8c0770
d282000a
042a0911
4a221aff
00000364
2c022282
d2c20011
02010501
e0308000
80021111
bf8c0770
10220b11
4a2420ff
00000364
2c022482
d2c20012
02010501
e0308000
80021212
bf8c0770
d2820011
04462503
4a2418ff
00000364
2c022482
d2c20012
02010501
e0308000
80021212
bf8c0770
d2820011
04460912
10222307
d2820011
04461506
4a141aff
00000368
2c021482
d2c20012
02010501
e0308000
80020a12
bf8c0770
10140b0a
4a2420ff
00000368
2c022482
d2c20012
02010501
e0308000
80021212
bf8c0770
d282000a
042a2503
4a2418ff
00000368
2c022482
d2c20012
02010501
e0308000
80021212
bf8c0770
d2820012
042a0912
d2820011
04462508
4a1a1aff
0000036c
2c021a82
d2c20012
02010501
e0308000
80020d12
bf8c0770
100a0b0d
4a1a20ff
0000036c
2c021a82
d2c20012
02010501
e0308000
80020d12
bf8c0770
d2820003
04161b03
4a0a18ff
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2c020a82
d2c20001
02010501
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80020101
bf8c0770
d2820001
040e0901
d2820005
04460309
c0028322
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043c0b05
c0028323
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7e040205
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04060404
c0028325
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10041c05
c0028324
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d2820002
04080b0b
c0028326
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04080b05
c0028327
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7e080205
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040a0804
c0400102
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c002810d
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10080405
c002810c
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d2820006
04120205
c0028329
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10081c05
c0028328
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d2820004
04100b0b
c002832a
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7e0e0205
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04120e04
c002810e
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041a0805
c002832d
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100e1c05
c002832c
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d2820007
041c0b0b
c002832e
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d2820005
041c0b05
c002832f
bf8c007f
7e0e0205
d2820005
04160e04
c002010f
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d2820006
041a0a04
c0020109
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100e0404
c0020108
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d2820007
041e0204
c002010a
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041e0804
c002010b
bf8c007f
d2820007
041e0a04
c0020105
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10100404
c0020104
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d2820008
04220204
c0020106
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d2820008
04220804
c0020107
bf8c007f
d2820008
04220a04
c0020101
bf8c007f
10120404
c0020100
bf8c007f
d2820009
04260204
c0020102
bf8c007f
d2820009
04260804
c0020103
bf8c007f
d2820009
04260a04
f80000ef
06070809
c002011d
bf8c000f
100c0404
c002011c
bf8c007f
d2820006
041a0204
c002011e
bf8c007f
d2820006
041a0804
c002011f
bf8c007f
d2820006
041a0a04
c0020119
bf8c007f
100e0404
c0020118
bf8c007f
d2820007
041e0204
c002011a
bf8c007f
d2820007
041e0804
c002011b
bf8c007f
d2820007
041e0a04
c0020115
bf8c007f
10100404
c0020114
bf8c007f
d2820008
04220204
c0020116
bf8c007f
d2820008
04220804
c0020117
bf8c007f
d2820008
04220a04
c0020111
bf8c007f
10120404
c0020110
bf8c007f
d2820009
04260204
c0020112
bf8c007f
d2820009
04260804
c0000113
bf8c007f
d2820009
04260a00
f80000ff
06070809
c082070c
bf8c000f
e00c2000
80010600
c00003c5
bf8c0070
10000e00
c00003c1
bf8c007f
d2820000
04000106
c00003c4
bf8c007f
10160e00
c00003c0
bf8c007f
d2820006
042c0106
f800021f
030a0006
be8003ff
00000d70
c0000200
bf8c000f
d2820000
04060a00
c0000302
bf8c007f
10020800
08020b01
be8003ff
00000d74
c0000200
bf8c007f
10060a00
08040503
f80008cf
05010200
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 3
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 4
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 5
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 6
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 7
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 8
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 9
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 10
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 11
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 12
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 13
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 14
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 15
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = fmul float %46, %12
  %51 = fmul float %46, %14
  %52 = fmul float %46, %16
  %53 = fmul float %46, %18
  %54 = fmul float %47, %20
  %55 = fadd float %54, %50
  %56 = fmul float %47, %22
  %57 = fadd float %56, %51
  %58 = fmul float %47, %24
  %59 = fadd float %58, %52
  %60 = fmul float %47, %26
  %61 = fadd float %60, %53
  %62 = fmul float %48, %28
  %63 = fadd float %62, %55
  %64 = fmul float %48, %30
  %65 = fadd float %64, %57
  %66 = fmul float %48, %32
  %67 = fadd float %66, %59
  %68 = fmul float %48, %34
  %69 = fadd float %68, %61
  %70 = fmul float %49, %36
  %71 = fadd float %70, %63
  %72 = fmul float %49, %38
  %73 = fadd float %72, %65
  %74 = fmul float %49, %40
  %75 = fadd float %74, %67
  %76 = fmul float %49, %42
  %77 = fadd float %76, %69
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %71, float %73, float %75, float %77)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%43](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR2<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR1, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR2<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 12; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0820700
bf8c007f
e00c2000
80010000
c0400100
bf8c0070
c0010103
bf8c007f
10080002
c0010107
bf8c007f
d2820004
04100501
c001010b
bf8c007f
d2820004
04100502
c001010f
bf8c007f
d2820004
04100503
c0010102
bf8c007f
100a0002
c0010106
bf8c007f
d2820005
04140501
c001010a
bf8c007f
d2820005
04140502
c001010e
bf8c007f
d2820005
04140503
c0010101
bf8c007f
100c0002
c0010105
bf8c007f
d2820006
04180501
c0010109
bf8c007f
d2820006
04180502
c001010d
bf8c007f
d2820006
04180503
c0010100
bf8c007f
100e0002
c0010104
bf8c007f
d2820007
041c0501
c0010108
bf8c007f
d2820007
041c0502
c000010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE
DCL IN[4], GENERIC[22], PERSPECTIVE
DCL IN[5], GENERIC[23], PERSPECTIVE
DCL IN[6], GENERIC[24], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..30]
DCL TEMP[0..5], LOCAL
DCL TEMP[6], ARRAY(1), LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: ADD TEMP[0].xyz, -IN[2].xyzz, CONST[10].xyzz
  1: MOV TEMP[1].x, IN[3].zzzz
  2: MOV TEMP[1].y, IN[4].zzzz
  3: MOV TEMP[1].z, IN[5].zzzz
  4: DP3 TEMP[2].x, TEMP[1].xyzz, TEMP[0].xyzz
  5: DP3 TEMP[3].x, TEMP[1].xyzz, TEMP[1].xyzz
  6: ADD TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
  7: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[3].xxxx
  8: MAD TEMP[1].xyz, TEMP[2].xxxx, TEMP[1].xyzz, -TEMP[0].xyzz
  9: MOV TEMP[2].xyz, TEMP[1].xyzz
 10: TEX TEMP[2].xyz, TEMP[2], SAMP[2], CUBE
 11: MOV TEMP[3].xy, IN[1].xyyy
 12: TEX TEMP[3], TEMP[3], SAMP[0], 2D
 13: MOV TEMP[4].xy, IN[6].xyyy
 14: TEX TEMP[4].xyz, TEMP[4], SAMP[1], 2D
 15: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[30].zzzz
 16: ADD TEMP[5].x, -TEMP[3].wwww, IMM[0].xxxx
 17: MUL TEMP[0].xyz, TEMP[3].xyzz, IN[0].xyzz
 18: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[5].xxxx
 19: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[0].xyzz
 20: MUL TEMP[1].xyz, TEMP[4].xyzz, CONST[12].xyzz
 21: MAD TEMP[3].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
 22: MAD TEMP[1].xyz, TEMP[0].xyzz, TEMP[1].xyzz, TEMP[2].xyzz
 23: MIN TEMP[2].x, TEMP[3].xxxx, CONST[11].zzzz
 24: MOV_SAT TEMP[2].x, TEMP[2].xxxx
 25: MAD TEMP[0].xyz, TEMP[1].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 26: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
 27: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
 28: MAD TEMP[1].xyz, TEMP[1].xyzz, CONST[30].xxxx, TEMP[0].xyzz
 29: MUL TEMP[0].x, IN[2].wwww, CONST[29].wwww
 30: MOV TEMP[1].w, TEMP[0].xxxx
 31: MOV TEMP[6], TEMP[1]
 32: MOV OUT[0], TEMP[6]
 33: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 0
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 1
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 2
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 40
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 41
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 42
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 44
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 46
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 47
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 48
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 49
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr float addrspace(2)* %21, i32 50
  %45 = load float addrspace(2)* %44, !tbaa !0
  %46 = getelementptr float addrspace(2)* %21, i32 116
  %47 = load float addrspace(2)* %46, !tbaa !0
  %48 = getelementptr float addrspace(2)* %21, i32 117
  %49 = load float addrspace(2)* %48, !tbaa !0
  %50 = getelementptr float addrspace(2)* %21, i32 118
  %51 = load float addrspace(2)* %50, !tbaa !0
  %52 = getelementptr float addrspace(2)* %21, i32 119
  %53 = load float addrspace(2)* %52, !tbaa !0
  %54 = getelementptr float addrspace(2)* %21, i32 120
  %55 = load float addrspace(2)* %54, !tbaa !0
  %56 = getelementptr float addrspace(2)* %21, i32 122
  %57 = load float addrspace(2)* %56, !tbaa !0
  %58 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %59 = load <32 x i8> addrspace(2)* %58, !tbaa !0
  %60 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
  %62 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %63 = load <32 x i8> addrspace(2)* %62, !tbaa !0
  %64 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
  %66 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %67 = load <32 x i8> addrspace(2)* %66, !tbaa !0
  %68 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
  %70 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %71 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %72 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %73 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %74 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %75 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %76 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %77 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %78 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %79 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %80 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
  %81 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
  %82 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %6)
  %83 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %6)
  %84 = fsub float -0.000000e+00, %75
  %85 = fadd float %84, %29
  %86 = fsub float -0.000000e+00, %76
  %87 = fadd float %86, %31
  %88 = fsub float -0.000000e+00, %77
  %89 = fadd float %88, %33
  %90 = fmul float %79, %85
  %91 = fmul float %80, %87
  %92 = fadd float %91, %90
  %93 = fmul float %81, %89
  %94 = fadd float %92, %93
  %95 = fmul float %79, %79
  %96 = fmul float %80, %80
  %97 = fadd float %96, %95
  %98 = fmul float %81, %81
  %99 = fadd float %97, %98
  %100 = fadd float %94, %94
  %101 = fmul float %85, %99
  %102 = fmul float %87, %99
  %103 = fmul float %89, %99
  %104 = fsub float -0.000000e+00, %101
  %105 = fmul float %100, %79
  %106 = fadd float %105, %104
  %107 = fsub float -0.000000e+00, %102
  %108 = fmul float %100, %80
  %109 = fadd float %108, %107
  %110 = fsub float -0.000000e+00, %103
  %111 = fmul float %100, %81
  %112 = fadd float %111, %110
  %113 = insertelement <4 x float> undef, float %106, i32 0
  %114 = insertelement <4 x float> %113, float %109, i32 1
  %115 = insertelement <4 x float> %114, float %112, i32 2
  %116 = insertelement <4 x float> %115, float 0.000000e+00, i32 3
  %117 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %116)
  %118 = extractelement <4 x float> %117, i32 0
  %119 = extractelement <4 x float> %117, i32 1
  %120 = extractelement <4 x float> %117, i32 2
  %121 = extractelement <4 x float> %117, i32 3
  %122 = call float @fabs(float %120)
  %123 = fdiv float 1.000000e+00, %122
  %124 = fmul float %118, %123
  %125 = fadd float %124, 1.500000e+00
  %126 = fmul float %119, %123
  %127 = fadd float %126, 1.500000e+00
  %128 = bitcast float %127 to i32
  %129 = bitcast float %125 to i32
  %130 = bitcast float %121 to i32
  %131 = insertelement <4 x i32> undef, i32 %128, i32 0
  %132 = insertelement <4 x i32> %131, i32 %129, i32 1
  %133 = insertelement <4 x i32> %132, i32 %130, i32 2
  %134 = insertelement <4 x i32> %133, i32 undef, i32 3
  %135 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %134, <32 x i8> %67, <16 x i8> %69, i32 4)
  %136 = extractelement <4 x float> %135, i32 0
  %137 = extractelement <4 x float> %135, i32 1
  %138 = extractelement <4 x float> %135, i32 2
  %139 = bitcast float %73 to i32
  %140 = bitcast float %74 to i32
  %141 = insertelement <2 x i32> undef, i32 %139, i32 0
  %142 = insertelement <2 x i32> %141, i32 %140, i32 1
  %143 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %142, <32 x i8> %59, <16 x i8> %61, i32 2)
  %144 = extractelement <4 x float> %143, i32 0
  %145 = extractelement <4 x float> %143, i32 1
  %146 = extractelement <4 x float> %143, i32 2
  %147 = extractelement <4 x float> %143, i32 3
  %148 = bitcast float %82 to i32
  %149 = bitcast float %83 to i32
  %150 = insertelement <2 x i32> undef, i32 %148, i32 0
  %151 = insertelement <2 x i32> %150, i32 %149, i32 1
  %152 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %151, <32 x i8> %63, <16 x i8> %65, i32 2)
  %153 = extractelement <4 x float> %152, i32 0
  %154 = extractelement <4 x float> %152, i32 1
  %155 = extractelement <4 x float> %152, i32 2
  %156 = fmul float %136, %57
  %157 = fmul float %137, %57
  %158 = fmul float %138, %57
  %159 = fsub float -0.000000e+00, %147
  %160 = fadd float %159, 1.000000e+00
  %161 = fmul float %144, %70
  %162 = fmul float %145, %71
  %163 = fmul float %146, %72
  %164 = fmul float %156, %160
  %165 = fmul float %157, %160
  %166 = fmul float %158, %160
  %167 = fmul float %164, %23
  %168 = fmul float %165, %25
  %169 = fmul float %166, %27
  %170 = fmul float %153, %41
  %171 = fmul float %154, %43
  %172 = fmul float %155, %45
  %173 = fsub float -0.000000e+00, %35
  %174 = fmul float %78, %39
  %175 = fadd float %174, %173
  %176 = fmul float %161, %170
  %177 = fadd float %176, %167
  %178 = fmul float %162, %171
  %179 = fadd float %178, %168
  %180 = fmul float %163, %172
  %181 = fadd float %180, %169
  %182 = fcmp uge float %175, %37
  %183 = select i1 %182, float %37, float %175
  %184 = call float @llvm.AMDIL.clamp.(float %183, float 0.000000e+00, float 1.000000e+00)
  %185 = fsub float -0.000000e+00, %55
  %186 = fmul float %177, %185
  %187 = fadd float %186, %47
  %188 = fsub float -0.000000e+00, %55
  %189 = fmul float %179, %188
  %190 = fadd float %189, %49
  %191 = fsub float -0.000000e+00, %55
  %192 = fmul float %181, %191
  %193 = fadd float %192, %51
  %194 = fmul float %184, %184
  %195 = fmul float %187, %194
  %196 = fmul float %190, %194
  %197 = fmul float %193, %194
  %198 = fmul float %177, %55
  %199 = fadd float %198, %195
  %200 = fmul float %179, %55
  %201 = fadd float %200, %196
  %202 = fmul float %181, %55
  %203 = fadd float %202, %197
  %204 = fmul float %78, %53
  %205 = call i32 @llvm.SI.packf16(float %199, float %201)
  %206 = bitcast i32 %205 to float
  %207 = call i32 @llvm.SI.packf16(float %203, float %204)
  %208 = bitcast i32 %207 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %206, float %208, float %206, float %208)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR5, %VGPR5, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR4, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR6, %VGPR6, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 41; mem:LD4[%30]
	S_WAITCNT 127
	%VGPR10<def> = V_SUB_F32_e32 %SGPR7<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR10, %VGPR7, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 40; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e32 %SGPR7<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR5, %VGPR9, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR4, %VGPR10<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 42; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR10<def> = V_SUB_F32_e32 %SGPR7<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR6, %VGPR10, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e32 %VGPR11<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR11, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %VGPR4<kill>, %VGPR8<kill>, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-def>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR11, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-use,kill>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-def>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-use,kill>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-def>
	%VGPR15<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-use,kill>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-def>
	%VGPR5<def> = V_CUBESC_F32 %VGPR12, %VGPR13, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR4<def> = V_CUBETC_F32 %VGPR12, %VGPR13, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR6<def> = V_CUBEMA_F32 %VGPR12, %VGPR13, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR7<def> = V_CUBEID_F32 %VGPR12, %VGPR13, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR12<def> = V_ADD_F32_e64 %VGPR6, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_RCP_F32_e32 %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR4, %VGPR12, %VGPR13, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR5<def> = V_MAD_F32 %VGPR5, %VGPR12<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR8<def> = KILL %VGPR8<undef>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%68](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%66](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6_VGPR7_VGPR8, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 122; mem:LD4[%56]
	S_WAITCNT 112
	%VGPR12<def> = V_MUL_F32_e32 %SGPR7, %VGPR5, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%60](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%58](tbaa=!"const")
	S_WAITCNT 127
	%VGPR7_VGPR8_VGPR9_VGPR10<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR11<def> = V_SUB_F32_e32 1.000000e+00, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR11, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%24]
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR2, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-def>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<tied0>, %VGPR3, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR2, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<tied0>, %VGPR3, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%64](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%62](tbaa=!"const")
	S_WAITCNT 127
	%VGPR12_VGPR13_VGPR14<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR12_VGPR13<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 49; mem:LD4[%42]
	S_WAITCNT 112
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR8, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR3<kill>, %VGPR2<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%54]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR15, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%48]
	S_WAITCNT 127
	%VGPR16<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 47; mem:LD4[%38]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 44; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR3<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 46; mem:LD4[%36]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR17<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR15<kill>, %SGPR2, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %SGPR7, %VGPR4, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR11, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR16<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR17<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR18<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR18<def,tied1> = V_INTERP_P2_F32 %VGPR18<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR7, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR18<kill>, %VGPR17<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %SGPR2, %VGPR16, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 116; mem:LD4[%46]
	S_WAITCNT 127
	%VGPR17<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR16<kill>, %SGPR2, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR16<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR6, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6<imp-use,kill>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%44]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR14, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14<imp-use,kill>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR9, %VGPR6<kill>, %EXEC<imp-use>, %VGPR7_VGPR8_VGPR9_VGPR10<imp-use,kill>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2, %VGPR0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 118; mem:LD4[%50]
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 119; mem:LD4[%52]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR15<kill>, %VGPR0<kill>, %VGPR15, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8101200
c8111201
c8140e00
c8150e01
100c0b05
d2820007
041a0904
c8181600
c8191601
d2820007
041e0d06
c8200900
c8210901
c0400100
bf8c007f
c0038129
bf8c007f
08141007
10100f0a
c8240800
c8250801
c0038128
bf8c007f
08121207
10161305
d282000b
042e1504
c8280a00
c8290a01
c003812a
bf8c007f
08141407
d282000b
042e1506
0616170b
1008090b
081a1104
10080f09
100a0b0b
08180905
10080f0a
100a0d0b
081c0905
7e1e0280
d28a0005
043a1b0c
d28c0004
043a1b0c
d28e0006
043a1b0c
d2880007
043a1b0c
d206010c
02010106
7e18550c
7e1a02ff
3fc00000
d2820006
04361904
d2820005
04361905
c0840308
c0c60510
bf8c007f
f0800700
00430405
c003817a
bf8c0070
10180a07
c8200500
c8210501
c81c0400
c81d0401
c0840300
c0c60500
bf8c007f
f0800f00
00430707
bf8c0770
081614f2
1018170c
c0040101
bf8c007f
101e1808
c8341902
c8351903
c8301802
c8311803
c0840304
c0c60508
bf8c007f
f0800700
00430c0c
c0010131
bf8c0070
10041a02
c80c0100
c80d0101
10060708
d282000f
043e0503
c0010178
bf8c007f
10041e02
c0018175
bf8c007f
08200403
c8080b00
c8090b01
c001812f
bf8c007f
10060403
c001812c
bf8c007f
0a060603
c001812e
bf8c007f
d00c0004
02000703
7e220203
d2000003
00122303
d2060803
02010103
10060703
10200710
d282000f
0440050f
10200807
10201710
c0018100
bf8c007f
10202003
c0018130
bf8c007f
10221803
c8480000
c8490001
10242507
d2820010
04422312
10222002
c0018174
bf8c007f
08222203
10220711
d2820010
04440510
5e1e1f10
10080c07
10081704
c0018102
bf8c007f
10080803
c0018132
bf8c007f
100a1c03
c8180200
c8190201
10000d09
d2820000
04120b00
10020002
c0018176
bf8c007f
08020203
10020701
d2820000
04040500
c0000177
bf8c007f
10020400
5e000300
f8001c0f
000f000f
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL OUT[7], GENERIC[23]
DCL OUT[8], GENERIC[24]
DCL CONST[0..51]
DCL TEMP[0..11], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[6]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: DP4 TEMP[5].x, TEMP[0], CONST[7]
 12: MOV TEMP[2].w, TEMP[5].xxxx
 13: DP4 TEMP[0].x, TEMP[0], CONST[12]
 14: DP3 TEMP[6].x, IN[1].xyzz, CONST[48].xyzz
 15: MOV TEMP[6].z, TEMP[6].xxxx
 16: DP3 TEMP[7].x, IN[1].xyzz, CONST[49].xyzz
 17: MOV TEMP[7].z, TEMP[7].xxxx
 18: DP3 TEMP[8].x, IN[1].xyzz, CONST[50].xyzz
 19: MOV TEMP[8].z, TEMP[8].xxxx
 20: DP3 TEMP[6].x, IN[4].xyzz, CONST[48].xyzz
 21: DP3 TEMP[7].x, IN[4].xyzz, CONST[49].xyzz
 22: DP3 TEMP[8].x, IN[4].xyzz, CONST[50].xyzz
 23: DP3 TEMP[9].x, IN[5].xyzz, CONST[48].xyzz
 24: MOV TEMP[6].y, TEMP[9].xxxx
 25: DP3 TEMP[9].x, IN[5].xyzz, CONST[49].xyzz
 26: MOV TEMP[7].y, TEMP[9].xxxx
 27: DP3 TEMP[9].x, IN[5].xyzz, CONST[50].xyzz
 28: MOV TEMP[8].y, TEMP[9].xxxx
 29: MOV TEMP[1].w, TEMP[0].xxxx
 30: MOV TEMP[0].xy, IN[2].xyxx
 31: MUL TEMP[9], IN[3].xyxx, CONST[0].yyxx
 32: MAD TEMP[10], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 33: MOV TEMP[11], TEMP[2]
 34: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[5].xxxx
 35: MOV TEMP[2].z, TEMP[4].xxxx
 36: MOV TEMP[2].y, -TEMP[3].xxxx
 37: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[5].xxxx, TEMP[2].xyyy
 38: MOV OUT[3], TEMP[0]
 39: MOV OUT[8], TEMP[9]
 40: MOV OUT[0], TEMP[2]
 41: MOV OUT[4], TEMP[1]
 42: MOV OUT[2], TEMP[11]
 43: MOV OUT[5], TEMP[6]
 44: MOV OUT[6], TEMP[7]
 45: MOV_SAT OUT[1], TEMP[10]
 46: MOV OUT[7], TEMP[8]
 47: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 16
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 17
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 18
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 19
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 20
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 21
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 22
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 23
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 24
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 25
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 26
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 27
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 28
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 29
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 30
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 31
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 48
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 49
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 50
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 51
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 191
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 192
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 193
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 194
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 195
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 196
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 197
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 198
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 199
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 200
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 201
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 202
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 203
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 204
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 205
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %5)
  %90 = extractelement <4 x float> %89, i32 0
  %91 = extractelement <4 x float> %89, i32 1
  %92 = extractelement <4 x float> %89, i32 2
  %93 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %94 = load <16 x i8> addrspace(2)* %93, !tbaa !0
  %95 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %94, i32 0, i32 %5)
  %96 = extractelement <4 x float> %95, i32 0
  %97 = extractelement <4 x float> %95, i32 1
  %98 = extractelement <4 x float> %95, i32 2
  %99 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %100 = load <16 x i8> addrspace(2)* %99, !tbaa !0
  %101 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %100, i32 0, i32 %5)
  %102 = extractelement <4 x float> %101, i32 0
  %103 = extractelement <4 x float> %101, i32 1
  %104 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %105 = load <16 x i8> addrspace(2)* %104, !tbaa !0
  %106 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %105, i32 0, i32 %5)
  %107 = extractelement <4 x float> %106, i32 0
  %108 = extractelement <4 x float> %106, i32 1
  %109 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %110 = load <16 x i8> addrspace(2)* %109, !tbaa !0
  %111 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %110, i32 0, i32 %5)
  %112 = extractelement <4 x float> %111, i32 0
  %113 = extractelement <4 x float> %111, i32 1
  %114 = extractelement <4 x float> %111, i32 2
  %115 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
  %116 = load <16 x i8> addrspace(2)* %115, !tbaa !0
  %117 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %116, i32 0, i32 %5)
  %118 = extractelement <4 x float> %117, i32 0
  %119 = extractelement <4 x float> %117, i32 1
  %120 = extractelement <4 x float> %117, i32 2
  %121 = fmul float %90, %14
  %122 = fadd float %121, %12
  %123 = fmul float %91, %14
  %124 = fadd float %123, %12
  %125 = fmul float %92, %14
  %126 = fadd float %125, %12
  %127 = fmul float %90, %12
  %128 = fadd float %127, %14
  %129 = fmul float %122, %60
  %130 = fmul float %124, %62
  %131 = fadd float %129, %130
  %132 = fmul float %126, %64
  %133 = fadd float %131, %132
  %134 = fmul float %128, %66
  %135 = fadd float %133, %134
  %136 = fmul float %122, %68
  %137 = fmul float %124, %70
  %138 = fadd float %136, %137
  %139 = fmul float %126, %72
  %140 = fadd float %138, %139
  %141 = fmul float %128, %74
  %142 = fadd float %140, %141
  %143 = fmul float %122, %76
  %144 = fmul float %124, %78
  %145 = fadd float %143, %144
  %146 = fmul float %126, %80
  %147 = fadd float %145, %146
  %148 = fmul float %128, %82
  %149 = fadd float %147, %148
  %150 = fmul float %122, %18
  %151 = fmul float %124, %20
  %152 = fadd float %150, %151
  %153 = fmul float %126, %22
  %154 = fadd float %152, %153
  %155 = fmul float %128, %24
  %156 = fadd float %154, %155
  %157 = fmul float %122, %26
  %158 = fmul float %124, %28
  %159 = fadd float %157, %158
  %160 = fmul float %126, %30
  %161 = fadd float %159, %160
  %162 = fmul float %128, %32
  %163 = fadd float %161, %162
  %164 = fmul float %122, %34
  %165 = fmul float %124, %36
  %166 = fadd float %164, %165
  %167 = fmul float %126, %38
  %168 = fadd float %166, %167
  %169 = fmul float %128, %40
  %170 = fadd float %168, %169
  %171 = fmul float %122, %42
  %172 = fmul float %124, %44
  %173 = fadd float %171, %172
  %174 = fmul float %126, %46
  %175 = fadd float %173, %174
  %176 = fmul float %128, %48
  %177 = fadd float %175, %176
  %178 = fmul float %122, %50
  %179 = fmul float %124, %52
  %180 = fadd float %178, %179
  %181 = fmul float %126, %54
  %182 = fadd float %180, %181
  %183 = fmul float %128, %56
  %184 = fadd float %182, %183
  %185 = fmul float %96, %60
  %186 = fmul float %97, %62
  %187 = fadd float %186, %185
  %188 = fmul float %98, %64
  %189 = fadd float %187, %188
  %190 = fmul float %96, %68
  %191 = fmul float %97, %70
  %192 = fadd float %191, %190
  %193 = fmul float %98, %72
  %194 = fadd float %192, %193
  %195 = fmul float %96, %76
  %196 = fmul float %97, %78
  %197 = fadd float %196, %195
  %198 = fmul float %98, %80
  %199 = fadd float %197, %198
  %200 = fmul float %112, %60
  %201 = fmul float %113, %62
  %202 = fadd float %201, %200
  %203 = fmul float %114, %64
  %204 = fadd float %202, %203
  %205 = fmul float %112, %68
  %206 = fmul float %113, %70
  %207 = fadd float %206, %205
  %208 = fmul float %114, %72
  %209 = fadd float %207, %208
  %210 = fmul float %112, %76
  %211 = fmul float %113, %78
  %212 = fadd float %211, %210
  %213 = fmul float %114, %80
  %214 = fadd float %212, %213
  %215 = fmul float %118, %60
  %216 = fmul float %119, %62
  %217 = fadd float %216, %215
  %218 = fmul float %120, %64
  %219 = fadd float %217, %218
  %220 = fmul float %118, %68
  %221 = fmul float %119, %70
  %222 = fadd float %221, %220
  %223 = fmul float %120, %72
  %224 = fadd float %222, %223
  %225 = fmul float %118, %76
  %226 = fmul float %119, %78
  %227 = fadd float %226, %225
  %228 = fmul float %120, %80
  %229 = fadd float %227, %228
  %230 = fmul float %107, %14
  %231 = fmul float %108, %14
  %232 = fmul float %107, %12
  %233 = fmul float %107, %12
  %234 = fmul float %58, %12
  %235 = fadd float %234, %14
  %236 = fmul float %58, %12
  %237 = fadd float %236, %14
  %238 = fmul float %58, %12
  %239 = fadd float %238, %14
  %240 = fmul float %58, %14
  %241 = fadd float %240, %12
  %242 = fsub float -0.000000e+00, %177
  %243 = fmul float %170, %16
  %244 = fadd float %243, %242
  %245 = fsub float -0.000000e+00, %163
  %246 = fmul float %84, %177
  %247 = fadd float %246, %156
  %248 = fmul float %86, %177
  %249 = fadd float %248, %245
  %250 = call float @llvm.AMDIL.clamp.(float %235, float 0.000000e+00, float 1.000000e+00)
  %251 = call float @llvm.AMDIL.clamp.(float %237, float 0.000000e+00, float 1.000000e+00)
  %252 = call float @llvm.AMDIL.clamp.(float %239, float 0.000000e+00, float 1.000000e+00)
  %253 = call float @llvm.AMDIL.clamp.(float %241, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %250, float %251, float %252, float %253)
  %254 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %255 = load float addrspace(2)* addrspace(2)* %254, !tbaa !0
  %256 = getelementptr float addrspace(2)* %255, i32 0
  %257 = load float addrspace(2)* %256, !tbaa !0
  %258 = fmul float %257, %156
  %259 = getelementptr float addrspace(2)* %255, i32 1
  %260 = load float addrspace(2)* %259, !tbaa !0
  %261 = fmul float %260, %163
  %262 = fadd float %258, %261
  %263 = getelementptr float addrspace(2)* %255, i32 2
  %264 = load float addrspace(2)* %263, !tbaa !0
  %265 = fmul float %264, %170
  %266 = fadd float %262, %265
  %267 = getelementptr float addrspace(2)* %255, i32 3
  %268 = load float addrspace(2)* %267, !tbaa !0
  %269 = fmul float %268, %177
  %270 = fadd float %266, %269
  %271 = getelementptr float addrspace(2)* %255, i32 4
  %272 = load float addrspace(2)* %271, !tbaa !0
  %273 = fmul float %272, %156
  %274 = getelementptr float addrspace(2)* %255, i32 5
  %275 = load float addrspace(2)* %274, !tbaa !0
  %276 = fmul float %275, %163
  %277 = fadd float %273, %276
  %278 = getelementptr float addrspace(2)* %255, i32 6
  %279 = load float addrspace(2)* %278, !tbaa !0
  %280 = fmul float %279, %170
  %281 = fadd float %277, %280
  %282 = getelementptr float addrspace(2)* %255, i32 7
  %283 = load float addrspace(2)* %282, !tbaa !0
  %284 = fmul float %283, %177
  %285 = fadd float %281, %284
  %286 = getelementptr float addrspace(2)* %255, i32 8
  %287 = load float addrspace(2)* %286, !tbaa !0
  %288 = fmul float %287, %156
  %289 = getelementptr float addrspace(2)* %255, i32 9
  %290 = load float addrspace(2)* %289, !tbaa !0
  %291 = fmul float %290, %163
  %292 = fadd float %288, %291
  %293 = getelementptr float addrspace(2)* %255, i32 10
  %294 = load float addrspace(2)* %293, !tbaa !0
  %295 = fmul float %294, %170
  %296 = fadd float %292, %295
  %297 = getelementptr float addrspace(2)* %255, i32 11
  %298 = load float addrspace(2)* %297, !tbaa !0
  %299 = fmul float %298, %177
  %300 = fadd float %296, %299
  %301 = getelementptr float addrspace(2)* %255, i32 12
  %302 = load float addrspace(2)* %301, !tbaa !0
  %303 = fmul float %302, %156
  %304 = getelementptr float addrspace(2)* %255, i32 13
  %305 = load float addrspace(2)* %304, !tbaa !0
  %306 = fmul float %305, %163
  %307 = fadd float %303, %306
  %308 = getelementptr float addrspace(2)* %255, i32 14
  %309 = load float addrspace(2)* %308, !tbaa !0
  %310 = fmul float %309, %170
  %311 = fadd float %307, %310
  %312 = getelementptr float addrspace(2)* %255, i32 15
  %313 = load float addrspace(2)* %312, !tbaa !0
  %314 = fmul float %313, %177
  %315 = fadd float %311, %314
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %270, float %285, float %300, float %315)
  %316 = getelementptr float addrspace(2)* %255, i32 16
  %317 = load float addrspace(2)* %316, !tbaa !0
  %318 = fmul float %317, %156
  %319 = getelementptr float addrspace(2)* %255, i32 17
  %320 = load float addrspace(2)* %319, !tbaa !0
  %321 = fmul float %320, %163
  %322 = fadd float %318, %321
  %323 = getelementptr float addrspace(2)* %255, i32 18
  %324 = load float addrspace(2)* %323, !tbaa !0
  %325 = fmul float %324, %170
  %326 = fadd float %322, %325
  %327 = getelementptr float addrspace(2)* %255, i32 19
  %328 = load float addrspace(2)* %327, !tbaa !0
  %329 = fmul float %328, %177
  %330 = fadd float %326, %329
  %331 = getelementptr float addrspace(2)* %255, i32 20
  %332 = load float addrspace(2)* %331, !tbaa !0
  %333 = fmul float %332, %156
  %334 = getelementptr float addrspace(2)* %255, i32 21
  %335 = load float addrspace(2)* %334, !tbaa !0
  %336 = fmul float %335, %163
  %337 = fadd float %333, %336
  %338 = getelementptr float addrspace(2)* %255, i32 22
  %339 = load float addrspace(2)* %338, !tbaa !0
  %340 = fmul float %339, %170
  %341 = fadd float %337, %340
  %342 = getelementptr float addrspace(2)* %255, i32 23
  %343 = load float addrspace(2)* %342, !tbaa !0
  %344 = fmul float %343, %177
  %345 = fadd float %341, %344
  %346 = getelementptr float addrspace(2)* %255, i32 24
  %347 = load float addrspace(2)* %346, !tbaa !0
  %348 = fmul float %347, %156
  %349 = getelementptr float addrspace(2)* %255, i32 25
  %350 = load float addrspace(2)* %349, !tbaa !0
  %351 = fmul float %350, %163
  %352 = fadd float %348, %351
  %353 = getelementptr float addrspace(2)* %255, i32 26
  %354 = load float addrspace(2)* %353, !tbaa !0
  %355 = fmul float %354, %170
  %356 = fadd float %352, %355
  %357 = getelementptr float addrspace(2)* %255, i32 27
  %358 = load float addrspace(2)* %357, !tbaa !0
  %359 = fmul float %358, %177
  %360 = fadd float %356, %359
  %361 = getelementptr float addrspace(2)* %255, i32 28
  %362 = load float addrspace(2)* %361, !tbaa !0
  %363 = fmul float %362, %156
  %364 = getelementptr float addrspace(2)* %255, i32 29
  %365 = load float addrspace(2)* %364, !tbaa !0
  %366 = fmul float %365, %163
  %367 = fadd float %363, %366
  %368 = getelementptr float addrspace(2)* %255, i32 30
  %369 = load float addrspace(2)* %368, !tbaa !0
  %370 = fmul float %369, %170
  %371 = fadd float %367, %370
  %372 = getelementptr float addrspace(2)* %255, i32 31
  %373 = load float addrspace(2)* %372, !tbaa !0
  %374 = fmul float %373, %177
  %375 = fadd float %371, %374
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %330, float %345, float %360, float %375)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %102, float %103, float %126, float %128)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %135, float %142, float %149, float %184)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %204, float %219, float %189, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %209, float %224, float %194, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %214, float %229, float %199, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %230, float %231, float %232, float %233)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %247, float %249, float %244, float %177)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 191; mem:LD4[%57]
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR8, %VGPR1, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR2, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%87](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR4, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR9, %SGPR4, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 17; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 16; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 18; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8, %SGPR5, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 19; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR8<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 21; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 20; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 22; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR8<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 23; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR8<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%254](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%304]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%301]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 25; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 24; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 26; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 27; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR8, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%308]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 29; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 28; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 30; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR8<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 31; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR8, %SGPR8<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%312]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%289]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%286]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%293]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%297]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%274]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%271]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%278]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%282]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%259]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%256]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%263]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%267]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%364]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%361]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%368]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%372]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%349]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%346]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%353]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%357]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%334]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%331]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%338]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%342]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%319]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%316]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%323]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%327]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%99](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR7, %VGPR8, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 49; mem:LD4[%51]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 48; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 50; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 51; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 201; mem:LD4[%77]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0, %VGPR6, %EXEC<imp-use>
	%SGPR1<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 200; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 202; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR7, %SGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 203; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR8, %SGPR9<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR9, %VGPR6, %EXEC<imp-use>
	%SGPR10<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR10, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR11<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 198; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR7, %SGPR11, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 199; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR8, %SGPR12<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR12, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR14<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR5<kill>, %SGPR14, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR13<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 194; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR7<kill>, %SGPR13, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR15<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 195; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR8<kill>, %SGPR15<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR5<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%93](tbaa=!"const")
	S_WAITCNT 15
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR9<def> = V_MUL_F32_e32 %SGPR14, %VGPR5, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR6, %SGPR12, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR7, %SGPR13, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%115](tbaa=!"const")
	S_WAITCNT 127
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR13<def> = V_MUL_F32_e32 %SGPR14, %VGPR9, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR10, %SGPR12, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR11, %SGPR13, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 16; mem:LD16[%109](tbaa=!"const")
	S_WAITCNT 127
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR17<def> = V_MUL_F32_e32 %SGPR14<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR14, %SGPR12<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR15, %SGPR13<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR20<kill>, %VGPR19<kill>, %VGPR18<kill>, %VGPR17, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR18<def> = V_MUL_F32_e32 %SGPR10, %VGPR5, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR6, %SGPR9, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR7, %SGPR11, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %SGPR10, %VGPR9, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR10, %SGPR9, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR11, %SGPR11, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %SGPR10<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR14, %SGPR9<kill>, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR15, %SGPR11<kill>, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 36, 0, 0, 0, %VGPR20<kill>, %VGPR19<kill>, %VGPR18<kill>, %VGPR17, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR18<def> = V_MUL_F32_e32 %SGPR1, %VGPR5, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR6, %SGPR0, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR7, %SGPR8, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR1, %VGPR9, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR10, %SGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR11, %SGPR8, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR14, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR15, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	EXP 15, 37, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR17<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 12; mem:LD16[%104](tbaa=!"const")
	S_WAITCNT 15
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4, %VGPR6, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	EXP 15, 38, 0, 0, 0, %VGPR5<kill>, %VGPR9<kill>, %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 204; mem:LD4[%83]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 205; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0410100
bf8c007f
c00403bf
c0028300
bf8c007f
7e040205
c0020301
bf8c007f
7e020204
d2820003
040a0208
d2060803
02010103
d2820004
04060408
d2060804
02010104
f800020f
03040404
c0840700
bf8c000f
e00c2000
80020800
bf8c0770
d2820005
04080908
d2820006
04080909
c0040311
bf8c007f
10060c08
c0040310
bf8c007f
d2820003
040c1105
d2820007
0408090a
c0040312
bf8c007f
d2820002
040c1107
d2820008
04040b08
c0040313
bf8c007f
d2820001
04081108
c0040315
bf8c007f
10040c08
c0040314
bf8c007f
d2820002
04081105
c0040316
bf8c007f
d2820002
04081107
c0040317
bf8c007f
d2820002
04081108
c0400102
bf8c007f
c004010d
bf8c007f
10060408
c004010c
bf8c007f
d2820004
040e0208
c0040319
bf8c007f
10060c08
c0040318
bf8c007f
d2820003
040c1105
c004031a
bf8c007f
d2820003
040c1107
c004031b
bf8c007f
d2820003
040c1108
c004010e
bf8c007f
d2820009
04120608
c004031d
bf8c007f
10080c08
c004031c
bf8c007f
d2820004
04101105
c004031e
bf8c007f
d2820004
04101107
c004031f
bf8c007f
d2820004
04101108
c004010f
bf8c007f
d2820009
04260808
c0040109
bf8c007f
10140408
c0040108
bf8c007f
d282000a
042a0208
c004010a
bf8c007f
d282000a
042a0608
c004010b
bf8c007f
d282000a
042a0808
c0040105
bf8c007f
10160408
c0040104
bf8c007f
d282000b
042e0208
c0040106
bf8c007f
d282000b
042e0608
c0040107
bf8c007f
d282000b
042e0808
c0040101
bf8c007f
10180408
c0040100
bf8c007f
d282000c
04320208
c0040102
bf8c007f
d282000c
04320608
c0040103
bf8c007f
d282000c
04320808
f80000ef
090a0b0c
c004011d
bf8c000f
10120408
c004011c
bf8c007f
d2820009
04260208
c004011e
bf8c007f
d2820009
04260608
c004011f
bf8c007f
d2820009
04260808
c0040119
bf8c007f
10140408
c0040118
bf8c007f
d282000a
042a0208
c004011a
bf8c007f
d282000a
042a0608
c004011b
bf8c007f
d282000a
042a0808
c0040115
bf8c007f
10160408
c0040114
bf8c007f
d282000b
042e0208
c0040116
bf8c007f
d282000b
042e0608
c0040117
bf8c007f
d282000b
042e0808
c0040111
bf8c007f
10180408
c0040110
bf8c007f
d282000c
04320208
c0040112
bf8c007f
d282000c
04320608
c0000113
bf8c007f
d282000c
04320800
f80000ff
090a0b0c
c0840708
bf8c000f
e00c2000
80020900
bf8c0770
f800021f
08070a09
c0000331
bf8c000f
10120c00
c0000330
bf8c007f
d2820009
04240105
c0000332
bf8c007f
d2820009
04240107
c0000333
bf8c007f
d2820009
04240108
c00003c9
bf8c007f
10140c00
c00083c8
bf8c007f
d282000a
04280305
c00403ca
bf8c007f
d282000a
04281107
c00483cb
bf8c007f
d282000a
04281308
c00483c5
bf8c007f
10160c09
c00503c4
bf8c007f
d282000b
042c1505
c00583c6
bf8c007f
d282000b
042c1707
c00603c7
bf8c007f
d282000b
042c1908
c00603c1
bf8c007f
100c0c0c
c00703c0
bf8c007f
d2820005
04181d05
c00683c2
bf8c007f
d2820005
04141b07
c00783c3
bf8c007f
d2820005
04141f08
f800022f
090a0b05
c0880704
bf8c000f
e00c2000
80040500
bf8c0770
10120a0e
d2820009
04241906
d2820012
04241b07
c0880714
bf8c007f
e00c2000
80040900
bf8c0770
101a120e
d282000d
0434190a
d2820013
04341b0b
c0880710
bf8c007f
e00c2000
80040d00
bf8c0770
10221a0e
d2820011
0444190e
d2820014
04441b0f
7e220280
f800023f
11121314
bf8c070f
10240a0a
d2820012
04481306
d2820012
04481707
1026120a
d2820013
044c130a
d2820013
044c170b
10281a0a
d2820014
0450130e
d2820014
0450170f
f800024f
11121314
bf8c070f
10240a01
d2820012
04480106
d2820005
04481107
100c1201
d2820006
0418010a
d2820006
0418110b
100e1a01
d2820007
041c010e
d2820007
041c110f
f800025f
11050607
c084070c
bf8c000f
e00c2000
80020500
bf8c0770
10000a05
10120c04
100a0a04
f800026f
00000905
c00003cc
bf8c000f
d2820000
04060800
c0000302
bf8c007f
10020600
08020901
c00003cd
bf8c007f
10060800
08040503
f80008cf
04010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE
DCL IN[4], GENERIC[22], PERSPECTIVE, CENTROID
DCL IN[5], GENERIC[23], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..30]
DCL TEMP[0..5], LOCAL
DCL TEMP[6], ARRAY(1), LOCAL
IMM[0] FLT32 {    2.0000,    -1.0000,     1.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[4].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[1], 2D
  2: MOV TEMP[1].xy, IN[4].wzzz
  3: TEX TEMP[1].xyz, TEMP[1], SAMP[1], 2D
  4: MOV TEMP[2].xy, IN[1].xyyy
  5: TEX TEMP[2].xyz, TEMP[2], SAMP[2], 2D
  6: MOV TEMP[3].xy, IN[5].xyyy
  7: TEX TEMP[3].xyz, TEMP[3], SAMP[1], 2D
  8: MOV TEMP[4].xy, IN[2].xyyy
  9: TEX TEMP[4].xyz, TEMP[4], SAMP[3], 2D
 10: MOV TEMP[5].xy, IN[1].xyyy
 11: TEX TEMP[5].xyz, TEMP[5], SAMP[0], 2D
 12: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].yyyy
 13: MAD TEMP[0].xyz, TEMP[2].xxxx, TEMP[0].xyzz, TEMP[1].xyzz
 14: MAD TEMP[0].xyz, TEMP[2].zzzz, TEMP[3].xyzz, TEMP[0].xyzz
 15: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[12].xyzz
 16: MUL TEMP[1].xyz, TEMP[4].xyzz, CONST[8].xyzz
 17: MAD TEMP[1].xyz, IMM[0].xxxx, TEMP[1].xyzz, IMM[0].yyyy
 18: MAD TEMP[1].xyz, CONST[8].wwww, TEMP[1].xyzz, IMM[0].zzzz
 19: MUL TEMP[2].xyz, TEMP[5].xyzz, TEMP[1].xyzz
 20: MUL TEMP[2].xyz, TEMP[2].xyzz, IN[0].xyzz
 21: MAD TEMP[3].x, IN[3].wwww, CONST[11].wwww, -CONST[11].xxxx
 22: MUL TEMP[2].xyz, TEMP[0].xyzz, TEMP[2].xyzz
 23: MIN TEMP[0].x, TEMP[3].xxxx, CONST[11].zzzz
 24: MOV_SAT TEMP[0].x, TEMP[0].xxxx
 25: MAD TEMP[1].xyz, TEMP[2].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 26: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx
 27: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[0].xxxx
 28: MAD TEMP[2].xyz, TEMP[2].xyzz, CONST[30].xxxx, TEMP[1].xyzz
 29: MUL TEMP[0].x, IN[3].wwww, CONST[29].wwww
 30: MOV TEMP[2].w, TEMP[0].xxxx
 31: MOV TEMP[6], TEMP[2]
 32: MOV OUT[0], TEMP[6]
 33: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 32
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 33
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 34
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 35
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 44
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 46
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 47
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 48
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 49
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 50
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 116
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr float addrspace(2)* %21, i32 117
  %45 = load float addrspace(2)* %44, !tbaa !0
  %46 = getelementptr float addrspace(2)* %21, i32 118
  %47 = load float addrspace(2)* %46, !tbaa !0
  %48 = getelementptr float addrspace(2)* %21, i32 119
  %49 = load float addrspace(2)* %48, !tbaa !0
  %50 = getelementptr float addrspace(2)* %21, i32 120
  %51 = load float addrspace(2)* %50, !tbaa !0
  %52 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %53 = load <32 x i8> addrspace(2)* %52, !tbaa !0
  %54 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
  %56 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %57 = load <32 x i8> addrspace(2)* %56, !tbaa !0
  %58 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %59 = load <16 x i8> addrspace(2)* %58, !tbaa !0
  %60 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %61 = load <32 x i8> addrspace(2)* %60, !tbaa !0
  %62 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %63 = load <16 x i8> addrspace(2)* %62, !tbaa !0
  %64 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %65 = load <32 x i8> addrspace(2)* %64, !tbaa !0
  %66 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
  %68 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %69 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %70 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %71 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %72 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %73 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %74 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %75 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
  %76 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %6)
  %77 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %6)
  %78 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %6)
  %79 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %6)
  %80 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %6)
  %81 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %6)
  %82 = bitcast float %76 to i32
  %83 = bitcast float %77 to i32
  %84 = insertelement <2 x i32> undef, i32 %82, i32 0
  %85 = insertelement <2 x i32> %84, i32 %83, i32 1
  %86 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %85, <32 x i8> %57, <16 x i8> %59, i32 2)
  %87 = extractelement <4 x float> %86, i32 0
  %88 = extractelement <4 x float> %86, i32 1
  %89 = extractelement <4 x float> %86, i32 2
  %90 = bitcast float %79 to i32
  %91 = bitcast float %78 to i32
  %92 = insertelement <2 x i32> undef, i32 %90, i32 0
  %93 = insertelement <2 x i32> %92, i32 %91, i32 1
  %94 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %93, <32 x i8> %57, <16 x i8> %59, i32 2)
  %95 = extractelement <4 x float> %94, i32 0
  %96 = extractelement <4 x float> %94, i32 1
  %97 = extractelement <4 x float> %94, i32 2
  %98 = bitcast float %71 to i32
  %99 = bitcast float %72 to i32
  %100 = insertelement <2 x i32> undef, i32 %98, i32 0
  %101 = insertelement <2 x i32> %100, i32 %99, i32 1
  %102 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %101, <32 x i8> %61, <16 x i8> %63, i32 2)
  %103 = extractelement <4 x float> %102, i32 0
  %104 = extractelement <4 x float> %102, i32 1
  %105 = extractelement <4 x float> %102, i32 2
  %106 = bitcast float %80 to i32
  %107 = bitcast float %81 to i32
  %108 = insertelement <2 x i32> undef, i32 %106, i32 0
  %109 = insertelement <2 x i32> %108, i32 %107, i32 1
  %110 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %109, <32 x i8> %57, <16 x i8> %59, i32 2)
  %111 = extractelement <4 x float> %110, i32 0
  %112 = extractelement <4 x float> %110, i32 1
  %113 = extractelement <4 x float> %110, i32 2
  %114 = bitcast float %73 to i32
  %115 = bitcast float %74 to i32
  %116 = insertelement <2 x i32> undef, i32 %114, i32 0
  %117 = insertelement <2 x i32> %116, i32 %115, i32 1
  %118 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %117, <32 x i8> %65, <16 x i8> %67, i32 2)
  %119 = extractelement <4 x float> %118, i32 0
  %120 = extractelement <4 x float> %118, i32 1
  %121 = extractelement <4 x float> %118, i32 2
  %122 = bitcast float %71 to i32
  %123 = bitcast float %72 to i32
  %124 = insertelement <2 x i32> undef, i32 %122, i32 0
  %125 = insertelement <2 x i32> %124, i32 %123, i32 1
  %126 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %125, <32 x i8> %53, <16 x i8> %55, i32 2)
  %127 = extractelement <4 x float> %126, i32 0
  %128 = extractelement <4 x float> %126, i32 1
  %129 = extractelement <4 x float> %126, i32 2
  %130 = fmul float %95, %104
  %131 = fmul float %96, %104
  %132 = fmul float %97, %104
  %133 = fmul float %103, %87
  %134 = fadd float %133, %130
  %135 = fmul float %103, %88
  %136 = fadd float %135, %131
  %137 = fmul float %103, %89
  %138 = fadd float %137, %132
  %139 = fmul float %105, %111
  %140 = fadd float %139, %134
  %141 = fmul float %105, %112
  %142 = fadd float %141, %136
  %143 = fmul float %105, %113
  %144 = fadd float %143, %138
  %145 = fmul float %140, %37
  %146 = fmul float %142, %39
  %147 = fmul float %144, %41
  %148 = fmul float %119, %23
  %149 = fmul float %120, %25
  %150 = fmul float %121, %27
  %151 = fmul float 2.000000e+00, %148
  %152 = fadd float %151, -1.000000e+00
  %153 = fmul float 2.000000e+00, %149
  %154 = fadd float %153, -1.000000e+00
  %155 = fmul float 2.000000e+00, %150
  %156 = fadd float %155, -1.000000e+00
  %157 = fmul float %29, %152
  %158 = fadd float %157, 1.000000e+00
  %159 = fmul float %29, %154
  %160 = fadd float %159, 1.000000e+00
  %161 = fmul float %29, %156
  %162 = fadd float %161, 1.000000e+00
  %163 = fmul float %127, %158
  %164 = fmul float %128, %160
  %165 = fmul float %129, %162
  %166 = fmul float %163, %68
  %167 = fmul float %164, %69
  %168 = fmul float %165, %70
  %169 = fsub float -0.000000e+00, %31
  %170 = fmul float %75, %35
  %171 = fadd float %170, %169
  %172 = fmul float %145, %166
  %173 = fmul float %146, %167
  %174 = fmul float %147, %168
  %175 = fcmp uge float %171, %33
  %176 = select i1 %175, float %33, float %171
  %177 = call float @llvm.AMDIL.clamp.(float %176, float 0.000000e+00, float 1.000000e+00)
  %178 = fsub float -0.000000e+00, %51
  %179 = fmul float %172, %178
  %180 = fadd float %179, %43
  %181 = fsub float -0.000000e+00, %51
  %182 = fmul float %173, %181
  %183 = fadd float %182, %45
  %184 = fsub float -0.000000e+00, %51
  %185 = fmul float %174, %184
  %186 = fadd float %185, %47
  %187 = fmul float %177, %177
  %188 = fmul float %180, %187
  %189 = fmul float %183, %187
  %190 = fmul float %186, %187
  %191 = fmul float %172, %51
  %192 = fadd float %191, %188
  %193 = fmul float %173, %51
  %194 = fadd float %193, %189
  %195 = fmul float %174, %51
  %196 = fadd float %195, %190
  %197 = fmul float %75, %49
  %198 = call i32 @llvm.SI.packf16(float %192, float %194)
  %199 = bitcast i32 %198 to float
  %200 = call i32 @llvm.SI.packf16(float %196, float %197)
  %201 = bitcast i32 %200 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %199, float %201, float %199, float %201)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%62](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%60](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR2, 2, 4, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR3, 2, 4, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR2, 3, 4, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<tied0>, %VGPR3, 3, 4, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%58](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%56](tbaa=!"const")
	S_WAITCNT 112
	%VGPR7_VGPR8_VGPR9<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MUL_F32_e32 %VGPR8, %VGPR5, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR2, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<tied0>, %VGPR3, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR2, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<tied0>, %VGPR3, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10_VGPR11_VGPR12<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR10_VGPR11<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MAD_F32 %VGPR4, %VGPR11, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR2, 1, 5, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-def>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<tied0>, %VGPR3, 1, 5, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR2, 0, 5, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<tied0>, %VGPR3, 0, 5, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR15_VGPR16_VGPR17<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR15_VGPR16<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %VGPR16, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 49; mem:LD4[%38]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR18_VGPR19<imp-def>
	%VGPR19<def,tied1> = V_INTERP_P2_F32 %VGPR19<tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR18_VGPR19<imp-use,kill>, %VGPR18_VGPR19<imp-def>
	%VGPR18<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR18_VGPR19<imp-use,kill>, %VGPR18_VGPR19<imp-def>
	%VGPR18<def,tied1> = V_INTERP_P2_F32 %VGPR18<tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR18_VGPR19<imp-use,kill>, %VGPR18_VGPR19<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 12; mem:LD16[%66](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 24; mem:LD32[%64](tbaa=!"const")
	S_WAITCNT 127
	%VGPR18_VGPR19_VGPR20<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR18_VGPR19<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 33; mem:LD4[%24]
	S_WAITCNT 112
	%VGPR3<def> = V_MUL_F32_e32 %SGPR7, %VGPR19, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR19, %SGPR7<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 35; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %SGPR7, %VGPR3<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%54](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%52](tbaa=!"const")
	S_WAITCNT 127
	%VGPR21_VGPR22_VGPR23<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR3<def> = V_MUL_F32_e32 %VGPR22, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%50]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR13, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%44]
	S_WAITCNT 127
	%VGPR14<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 3, %M0<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 47; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 44; mem:LD4[%30]
	S_WAITCNT 127
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR3<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 46; mem:LD4[%32]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR24<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR13<kill>, %SGPR2, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR7, %VGPR5, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR4, %VGPR10, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR6, %VGPR15, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%36]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 32; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR24<def> = V_MUL_F32_e32 %SGPR3, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR18, %SGPR3<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %SGPR7, %VGPR24<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR21, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR25<def,tied1> = V_INTERP_P2_F32 %VGPR25<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR2, %VGPR14, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 116; mem:LD4[%42]
	S_WAITCNT 127
	%VGPR24<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR14<kill>, %SGPR2, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR14<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR9, %VGPR5, %EXEC<imp-use>, %VGPR7_VGPR8_VGPR9<imp-use,kill>
	%VGPR7<def> = V_MAD_F32 %VGPR4, %VGPR12, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12<imp-use,kill>
	%VGPR4<def> = V_MAD_F32 %VGPR6, %VGPR17, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR4_VGPR5_VGPR6<imp-use,kill>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 34; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR3, %VGPR20, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR20, %SGPR3<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20<imp-use,kill>
	%VGPR5<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %SGPR7<kill>, %VGPR5<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR23, %VGPR5<kill>, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23<imp-use,kill>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2, %VGPR0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 118; mem:LD4[%46]
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 119; mem:LD4[%48]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR13<kill>, %VGPR0<kill>, %VGPR13, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8380500
c8390501
c8340400
c8350401
c0840308
c0c60510
bf8c007f
f0800700
0043040d
c8201202
c8211203
c81c1302
c81d1303
c0840304
c0c60508
bf8c0070
f0800700
00430707
bf8c0770
101e0b08
c82c1102
c82d1103
c8281002
c8291003
f0800700
00430a0a
bf8c0770
d2820012
043e1704
c8401502
c8411503
c83c1402
c83d1403
f0800700
00430f0f
bf8c0770
d2820002
044a2106
c0400100
bf8c007f
c0038131
bf8c007f
10040407
c84c0900
c84d0901
c8480800
c8490801
c084030c
c0c60518
bf8c007f
f0800700
00431212
c0038121
bf8c0070
10062607
d2820003
040c0f13
060606f3
c0038123
bf8c007f
d2820003
03ca0607
c0840300
c0c60500
bf8c007f
f0800700
0043150d
bf8c0770
10060716
c8340100
c8350101
10061b03
101a0702
c0010178
bf8c007f
10041a02
c0018175
bf8c007f
081c0403
c8080f00
c8090f01
c001812f
bf8c007f
10060403
c001812c
bf8c007f
0a060603
c001812e
bf8c007f
d00c0004
02000703
7e300203
d2000003
00123103
d2060803
02010103
10060703
101c070e
d282000d
0438050d
101c0b07
d282000e
043a1504
d282000e
043a1f06
c0018130
bf8c007f
101c1c03
c0018120
bf8c007f
10302403
d2820018
04600712
063030f3
d2820018
03ca3007
10303115
c8640000
c8650001
10303318
101c310e
10301c02
c0018174
bf8c007f
08303003
10300718
d282000e
0460050e
5e1a1b0e
100e0b09
d2820007
041e1904
d2820004
041e2306
c0018132
bf8c007f
10080803
c0018122
bf8c007f
100a2803
d2820005
04140714
060a0af3
d2820005
03ca0a07
100a0b17
c8180200
c8190201
10000d05
10000104
10020002
c0018176
bf8c007f
08020203
10020701
d2820000
04040500
c0000177
bf8c007f
10020400
5e000300
f8001c0f
000d000d
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL OUT[7], GENERIC[23]
DCL CONST[0..55]
DCL TEMP[0..11], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[52]
  2: DP4 TEMP[2].x, TEMP[0], CONST[53]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[54]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[6]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: MUL TEMP[5].xy, IN[1].xyyy, CONST[48].xyyy
 12: DP4 TEMP[6].x, TEMP[0], CONST[7]
 13: MOV TEMP[2].w, TEMP[6].xxxx
 14: ADD TEMP[7].x, TEMP[5].yyyy, TEMP[5].xxxx
 15: DP4 TEMP[8].x, TEMP[0], CONST[12]
 16: ADD TEMP[7].x, TEMP[7].xxxx, CONST[48].wwww
 17: MUL TEMP[5].xy, IN[1].xyyy, CONST[49].xyyy
 18: MUL TEMP[0].xy, IN[1].xyyy, CONST[50].xyyy
 19: ADD TEMP[9].x, TEMP[5].yyyy, TEMP[5].xxxx
 20: ADD TEMP[10].x, TEMP[0].yyyy, TEMP[0].xxxx
 21: ADD TEMP[9].x, TEMP[9].xxxx, CONST[49].wwww
 22: MOV TEMP[7].y, TEMP[9].xxxx
 23: ADD TEMP[9].x, TEMP[10].xxxx, CONST[50].wwww
 24: MUL TEMP[5].xy, IN[1].xyyy, CONST[51].xyyy
 25: MUL TEMP[0].xy, IN[1].xyyy, CONST[14].xyyy
 26: ADD TEMP[10].x, TEMP[5].yyyy, TEMP[5].xxxx
 27: ADD TEMP[11].x, TEMP[0].yyyy, TEMP[0].xxxx
 28: ADD TEMP[10].x, TEMP[10].xxxx, CONST[51].wwww
 29: MOV TEMP[9].y, TEMP[10].xxxx
 30: ADD TEMP[10].x, TEMP[11].xxxx, CONST[14].wwww
 31: MOV TEMP[10].z, TEMP[10].xxxx
 32: MUL TEMP[5].xy, IN[1].xyyy, CONST[15].xyyy
 33: ADD TEMP[0].xy, IN[3].xyyy, IN[2].xyyy
 34: ADD TEMP[5].x, TEMP[5].yyyy, TEMP[5].xxxx
 35: ADD TEMP[11].xy, TEMP[0].yxxx, IN[3].yxxx
 36: MOV TEMP[0].zw, TEMP[11].yyxy
 37: ADD TEMP[5].x, TEMP[5].xxxx, CONST[15].wwww
 38: MOV TEMP[10].w, TEMP[5].xxxx
 39: MOV TEMP[0], TEMP[0]
 40: ADD TEMP[10].xy, TEMP[11].yxxx, IN[3].xyyy
 41: MOV TEMP[1].w, TEMP[8].xxxx
 42: MOV TEMP[9].zw, CONST[0].xxxx
 43: MAD TEMP[5], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 44: MOV TEMP[8], TEMP[2]
 45: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[6].xxxx
 46: MOV TEMP[2].z, TEMP[4].xxxx
 47: MOV TEMP[2].y, -TEMP[3].xxxx
 48: MAD TEMP[2].xy, CONST[55].xyyy, TEMP[6].xxxx, TEMP[2].xyyy
 49: MOV OUT[3], TEMP[7]
 50: MOV OUT[4], TEMP[9]
 51: MOV OUT[6], TEMP[0]
 52: MOV OUT[7], TEMP[10]
 53: MOV OUT[0], TEMP[2]
 54: MOV OUT[5], TEMP[1]
 55: MOV OUT[2], TEMP[8]
 56: MOV_SAT OUT[1], TEMP[5]
 57: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 16
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 17
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 18
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 19
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 20
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 21
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 22
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 23
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 24
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 25
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 26
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 27
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 28
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 29
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 30
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 31
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 48
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 49
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 50
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 51
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 56
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 57
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 59
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 60
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 61
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 63
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 191
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 192
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 193
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 195
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 196
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 197
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 199
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 200
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 201
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr float addrspace(2)* %10, i32 203
  %88 = load float addrspace(2)* %87, !tbaa !0
  %89 = getelementptr float addrspace(2)* %10, i32 204
  %90 = load float addrspace(2)* %89, !tbaa !0
  %91 = getelementptr float addrspace(2)* %10, i32 205
  %92 = load float addrspace(2)* %91, !tbaa !0
  %93 = getelementptr float addrspace(2)* %10, i32 207
  %94 = load float addrspace(2)* %93, !tbaa !0
  %95 = getelementptr float addrspace(2)* %10, i32 208
  %96 = load float addrspace(2)* %95, !tbaa !0
  %97 = getelementptr float addrspace(2)* %10, i32 209
  %98 = load float addrspace(2)* %97, !tbaa !0
  %99 = getelementptr float addrspace(2)* %10, i32 210
  %100 = load float addrspace(2)* %99, !tbaa !0
  %101 = getelementptr float addrspace(2)* %10, i32 211
  %102 = load float addrspace(2)* %101, !tbaa !0
  %103 = getelementptr float addrspace(2)* %10, i32 212
  %104 = load float addrspace(2)* %103, !tbaa !0
  %105 = getelementptr float addrspace(2)* %10, i32 213
  %106 = load float addrspace(2)* %105, !tbaa !0
  %107 = getelementptr float addrspace(2)* %10, i32 214
  %108 = load float addrspace(2)* %107, !tbaa !0
  %109 = getelementptr float addrspace(2)* %10, i32 215
  %110 = load float addrspace(2)* %109, !tbaa !0
  %111 = getelementptr float addrspace(2)* %10, i32 216
  %112 = load float addrspace(2)* %111, !tbaa !0
  %113 = getelementptr float addrspace(2)* %10, i32 217
  %114 = load float addrspace(2)* %113, !tbaa !0
  %115 = getelementptr float addrspace(2)* %10, i32 218
  %116 = load float addrspace(2)* %115, !tbaa !0
  %117 = getelementptr float addrspace(2)* %10, i32 219
  %118 = load float addrspace(2)* %117, !tbaa !0
  %119 = getelementptr float addrspace(2)* %10, i32 220
  %120 = load float addrspace(2)* %119, !tbaa !0
  %121 = getelementptr float addrspace(2)* %10, i32 221
  %122 = load float addrspace(2)* %121, !tbaa !0
  %123 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %124 = load <16 x i8> addrspace(2)* %123, !tbaa !0
  %125 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %124, i32 0, i32 %5)
  %126 = extractelement <4 x float> %125, i32 0
  %127 = extractelement <4 x float> %125, i32 1
  %128 = extractelement <4 x float> %125, i32 2
  %129 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %130 = load <16 x i8> addrspace(2)* %129, !tbaa !0
  %131 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %130, i32 0, i32 %5)
  %132 = extractelement <4 x float> %131, i32 0
  %133 = extractelement <4 x float> %131, i32 1
  %134 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %135 = load <16 x i8> addrspace(2)* %134, !tbaa !0
  %136 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %135, i32 0, i32 %5)
  %137 = extractelement <4 x float> %136, i32 0
  %138 = extractelement <4 x float> %136, i32 1
  %139 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %140 = load <16 x i8> addrspace(2)* %139, !tbaa !0
  %141 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %140, i32 0, i32 %5)
  %142 = extractelement <4 x float> %141, i32 0
  %143 = extractelement <4 x float> %141, i32 1
  %144 = fmul float %126, %14
  %145 = fadd float %144, %12
  %146 = fmul float %127, %14
  %147 = fadd float %146, %12
  %148 = fmul float %128, %14
  %149 = fadd float %148, %12
  %150 = fmul float %126, %12
  %151 = fadd float %150, %14
  %152 = fmul float %145, %96
  %153 = fmul float %147, %98
  %154 = fadd float %152, %153
  %155 = fmul float %149, %100
  %156 = fadd float %154, %155
  %157 = fmul float %151, %102
  %158 = fadd float %156, %157
  %159 = fmul float %145, %104
  %160 = fmul float %147, %106
  %161 = fadd float %159, %160
  %162 = fmul float %149, %108
  %163 = fadd float %161, %162
  %164 = fmul float %151, %110
  %165 = fadd float %163, %164
  %166 = fmul float %145, %112
  %167 = fmul float %147, %114
  %168 = fadd float %166, %167
  %169 = fmul float %149, %116
  %170 = fadd float %168, %169
  %171 = fmul float %151, %118
  %172 = fadd float %170, %171
  %173 = fmul float %145, %18
  %174 = fmul float %147, %20
  %175 = fadd float %173, %174
  %176 = fmul float %149, %22
  %177 = fadd float %175, %176
  %178 = fmul float %151, %24
  %179 = fadd float %177, %178
  %180 = fmul float %145, %26
  %181 = fmul float %147, %28
  %182 = fadd float %180, %181
  %183 = fmul float %149, %30
  %184 = fadd float %182, %183
  %185 = fmul float %151, %32
  %186 = fadd float %184, %185
  %187 = fmul float %145, %34
  %188 = fmul float %147, %36
  %189 = fadd float %187, %188
  %190 = fmul float %149, %38
  %191 = fadd float %189, %190
  %192 = fmul float %151, %40
  %193 = fadd float %191, %192
  %194 = fmul float %132, %72
  %195 = fmul float %133, %74
  %196 = fmul float %145, %42
  %197 = fmul float %147, %44
  %198 = fadd float %196, %197
  %199 = fmul float %149, %46
  %200 = fadd float %198, %199
  %201 = fmul float %151, %48
  %202 = fadd float %200, %201
  %203 = fadd float %195, %194
  %204 = fmul float %145, %50
  %205 = fmul float %147, %52
  %206 = fadd float %204, %205
  %207 = fmul float %149, %54
  %208 = fadd float %206, %207
  %209 = fmul float %151, %56
  %210 = fadd float %208, %209
  %211 = fadd float %203, %76
  %212 = fmul float %132, %78
  %213 = fmul float %133, %80
  %214 = fmul float %132, %84
  %215 = fmul float %133, %86
  %216 = fadd float %213, %212
  %217 = fadd float %215, %214
  %218 = fadd float %216, %82
  %219 = fadd float %217, %88
  %220 = fmul float %132, %90
  %221 = fmul float %133, %92
  %222 = fmul float %132, %58
  %223 = fmul float %133, %60
  %224 = fadd float %221, %220
  %225 = fadd float %223, %222
  %226 = fadd float %224, %94
  %227 = fadd float %225, %62
  %228 = fmul float %132, %64
  %229 = fmul float %133, %66
  %230 = fadd float %142, %137
  %231 = fadd float %143, %138
  %232 = fadd float %229, %228
  %233 = fadd float %231, %143
  %234 = fadd float %230, %142
  %235 = fadd float %232, %68
  %236 = fadd float %234, %142
  %237 = fadd float %233, %143
  %238 = fmul float %70, %12
  %239 = fadd float %238, %14
  %240 = fmul float %70, %12
  %241 = fadd float %240, %14
  %242 = fmul float %70, %12
  %243 = fadd float %242, %14
  %244 = fmul float %70, %14
  %245 = fadd float %244, %12
  %246 = fsub float -0.000000e+00, %202
  %247 = fmul float %193, %16
  %248 = fadd float %247, %246
  %249 = fsub float -0.000000e+00, %186
  %250 = fmul float %120, %202
  %251 = fadd float %250, %179
  %252 = fmul float %122, %202
  %253 = fadd float %252, %249
  %254 = call float @llvm.AMDIL.clamp.(float %239, float 0.000000e+00, float 1.000000e+00)
  %255 = call float @llvm.AMDIL.clamp.(float %241, float 0.000000e+00, float 1.000000e+00)
  %256 = call float @llvm.AMDIL.clamp.(float %243, float 0.000000e+00, float 1.000000e+00)
  %257 = call float @llvm.AMDIL.clamp.(float %245, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %254, float %255, float %256, float %257)
  %258 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %259 = load float addrspace(2)* addrspace(2)* %258, !tbaa !0
  %260 = getelementptr float addrspace(2)* %259, i32 0
  %261 = load float addrspace(2)* %260, !tbaa !0
  %262 = fmul float %261, %179
  %263 = getelementptr float addrspace(2)* %259, i32 1
  %264 = load float addrspace(2)* %263, !tbaa !0
  %265 = fmul float %264, %186
  %266 = fadd float %262, %265
  %267 = getelementptr float addrspace(2)* %259, i32 2
  %268 = load float addrspace(2)* %267, !tbaa !0
  %269 = fmul float %268, %193
  %270 = fadd float %266, %269
  %271 = getelementptr float addrspace(2)* %259, i32 3
  %272 = load float addrspace(2)* %271, !tbaa !0
  %273 = fmul float %272, %202
  %274 = fadd float %270, %273
  %275 = getelementptr float addrspace(2)* %259, i32 4
  %276 = load float addrspace(2)* %275, !tbaa !0
  %277 = fmul float %276, %179
  %278 = getelementptr float addrspace(2)* %259, i32 5
  %279 = load float addrspace(2)* %278, !tbaa !0
  %280 = fmul float %279, %186
  %281 = fadd float %277, %280
  %282 = getelementptr float addrspace(2)* %259, i32 6
  %283 = load float addrspace(2)* %282, !tbaa !0
  %284 = fmul float %283, %193
  %285 = fadd float %281, %284
  %286 = getelementptr float addrspace(2)* %259, i32 7
  %287 = load float addrspace(2)* %286, !tbaa !0
  %288 = fmul float %287, %202
  %289 = fadd float %285, %288
  %290 = getelementptr float addrspace(2)* %259, i32 8
  %291 = load float addrspace(2)* %290, !tbaa !0
  %292 = fmul float %291, %179
  %293 = getelementptr float addrspace(2)* %259, i32 9
  %294 = load float addrspace(2)* %293, !tbaa !0
  %295 = fmul float %294, %186
  %296 = fadd float %292, %295
  %297 = getelementptr float addrspace(2)* %259, i32 10
  %298 = load float addrspace(2)* %297, !tbaa !0
  %299 = fmul float %298, %193
  %300 = fadd float %296, %299
  %301 = getelementptr float addrspace(2)* %259, i32 11
  %302 = load float addrspace(2)* %301, !tbaa !0
  %303 = fmul float %302, %202
  %304 = fadd float %300, %303
  %305 = getelementptr float addrspace(2)* %259, i32 12
  %306 = load float addrspace(2)* %305, !tbaa !0
  %307 = fmul float %306, %179
  %308 = getelementptr float addrspace(2)* %259, i32 13
  %309 = load float addrspace(2)* %308, !tbaa !0
  %310 = fmul float %309, %186
  %311 = fadd float %307, %310
  %312 = getelementptr float addrspace(2)* %259, i32 14
  %313 = load float addrspace(2)* %312, !tbaa !0
  %314 = fmul float %313, %193
  %315 = fadd float %311, %314
  %316 = getelementptr float addrspace(2)* %259, i32 15
  %317 = load float addrspace(2)* %316, !tbaa !0
  %318 = fmul float %317, %202
  %319 = fadd float %315, %318
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %274, float %289, float %304, float %319)
  %320 = getelementptr float addrspace(2)* %259, i32 16
  %321 = load float addrspace(2)* %320, !tbaa !0
  %322 = fmul float %321, %179
  %323 = getelementptr float addrspace(2)* %259, i32 17
  %324 = load float addrspace(2)* %323, !tbaa !0
  %325 = fmul float %324, %186
  %326 = fadd float %322, %325
  %327 = getelementptr float addrspace(2)* %259, i32 18
  %328 = load float addrspace(2)* %327, !tbaa !0
  %329 = fmul float %328, %193
  %330 = fadd float %326, %329
  %331 = getelementptr float addrspace(2)* %259, i32 19
  %332 = load float addrspace(2)* %331, !tbaa !0
  %333 = fmul float %332, %202
  %334 = fadd float %330, %333
  %335 = getelementptr float addrspace(2)* %259, i32 20
  %336 = load float addrspace(2)* %335, !tbaa !0
  %337 = fmul float %336, %179
  %338 = getelementptr float addrspace(2)* %259, i32 21
  %339 = load float addrspace(2)* %338, !tbaa !0
  %340 = fmul float %339, %186
  %341 = fadd float %337, %340
  %342 = getelementptr float addrspace(2)* %259, i32 22
  %343 = load float addrspace(2)* %342, !tbaa !0
  %344 = fmul float %343, %193
  %345 = fadd float %341, %344
  %346 = getelementptr float addrspace(2)* %259, i32 23
  %347 = load float addrspace(2)* %346, !tbaa !0
  %348 = fmul float %347, %202
  %349 = fadd float %345, %348
  %350 = getelementptr float addrspace(2)* %259, i32 24
  %351 = load float addrspace(2)* %350, !tbaa !0
  %352 = fmul float %351, %179
  %353 = getelementptr float addrspace(2)* %259, i32 25
  %354 = load float addrspace(2)* %353, !tbaa !0
  %355 = fmul float %354, %186
  %356 = fadd float %352, %355
  %357 = getelementptr float addrspace(2)* %259, i32 26
  %358 = load float addrspace(2)* %357, !tbaa !0
  %359 = fmul float %358, %193
  %360 = fadd float %356, %359
  %361 = getelementptr float addrspace(2)* %259, i32 27
  %362 = load float addrspace(2)* %361, !tbaa !0
  %363 = fmul float %362, %202
  %364 = fadd float %360, %363
  %365 = getelementptr float addrspace(2)* %259, i32 28
  %366 = load float addrspace(2)* %365, !tbaa !0
  %367 = fmul float %366, %179
  %368 = getelementptr float addrspace(2)* %259, i32 29
  %369 = load float addrspace(2)* %368, !tbaa !0
  %370 = fmul float %369, %186
  %371 = fadd float %367, %370
  %372 = getelementptr float addrspace(2)* %259, i32 30
  %373 = load float addrspace(2)* %372, !tbaa !0
  %374 = fmul float %373, %193
  %375 = fadd float %371, %374
  %376 = getelementptr float addrspace(2)* %259, i32 31
  %377 = load float addrspace(2)* %376, !tbaa !0
  %378 = fmul float %377, %202
  %379 = fadd float %375, %378
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %334, float %349, float %364, float %379)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %211, float %218, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %219, float %226, float %12, float %12)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %158, float %165, float %172, float %210)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %230, float %231, float %233, float %234)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %236, float %237, float %227, float %235)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %251, float %253, float %248, float %202)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 191; mem:LD4[%69]
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR8, %VGPR1, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR2, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%123](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_MAD_F32 %VGPR8, %SGPR5, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR9, %SGPR5, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 17; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 16; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR4, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR10, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 18; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR5<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8, %SGPR4, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 19; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 21; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 20; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR4, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 22; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 23; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%258](tbaa=!"const")
	S_WAITCNT 127
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%308]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%305]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 25; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 24; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR4, %SGPR5<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 26; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR5<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 27; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR8, %SGPR5<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%312]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 29; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 28; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR4, %SGPR5<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 30; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR7, %SGPR5<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 31; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR5<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%316]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR5, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%293]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%290]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%297]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%301]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR5, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%278]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%275]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%282]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%286]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR5, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%263]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%260]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%267]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR5<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%271]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR5<kill>, %VGPR5, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%368]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%365]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%372]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR3, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%376]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR5, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%353]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%350]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%357]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%361]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR5, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%338]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%335]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%342]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%346]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR5, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%323]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%320]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%327]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR5<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%331]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%129](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%77]
	S_WAITCNT 112
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 199; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR13<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 195; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR14<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR14<kill>, %VGPR13<kill>, %VGPR15<kill>, %VGPR15, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 204; mem:LD4[%89]
	S_WAITCNT 15
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 205; mem:LD4[%91]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 207; mem:LD4[%93]
	S_WAITCNT 127
	%VGPR13<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 200; mem:LD4[%83]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 201; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 203; mem:LD4[%87]
	S_WAITCNT 127
	%VGPR14<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%VGPR16<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR14<kill>, %VGPR13<kill>, %VGPR15<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 49; mem:LD4[%51]
	S_WAITCNT 15
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 48; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR4, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 50; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 51; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 217; mem:LD4[%113]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 216; mem:LD4[%111]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR4, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 218; mem:LD4[%115]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 219; mem:LD4[%117]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 213; mem:LD4[%105]
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 212; mem:LD4[%103]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR4, %SGPR0<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 214; mem:LD4[%107]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 215; mem:LD4[%109]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 209; mem:LD4[%97]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 208; mem:LD4[%95]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR4<kill>, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 210; mem:LD4[%99]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR7<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 211; mem:LD4[%101]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR8<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR4<kill>, %VGPR15<kill>, %VGPR14<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%134](tbaa=!"const")
	S_WAITCNT 15
	%VGPR17_VGPR18_VGPR19_VGPR20<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 12; mem:LD16[%139](tbaa=!"const")
	S_WAITCNT 112
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_ADD_F32_e32 %VGPR13, %VGPR17, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR6, %VGPR13, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e32 %VGPR14, %VGPR18, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR7, %VGPR14, %EXEC<imp-use>
	EXP 15, 36, 0, 0, 0, %VGPR6<kill>, %VGPR7<kill>, %VGPR4, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 60; mem:LD4[%63]
	S_WAITCNT 15
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 61; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 63; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR6<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 56; mem:LD4[%57]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 57; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 59; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR7<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR14, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR0<kill>, %VGPR13, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	EXP 15, 37, 0, 0, 0, %VGPR0<kill>, %VGPR4<kill>, %VGPR7<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 220; mem:LD4[%119]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR5, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 221; mem:LD4[%121]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR5<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0410100
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c00403bf
c0020300
bf8c007f
7e040204
c0028301
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7e020205
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10040c05
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c0400102
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040e0205
c0028319
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10060c05
c0028318
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d2820003
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c002831a
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10140405
c0028108
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c0028106
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10120405
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061c1c00
7e1e0280
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0f0f0d0e
c00003cc
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101a1200
c00003cd
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d282000d
0434010a
c00003cf
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061a1a00
c00003c8
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101c1200
c00003c9
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c00003cb
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101a0c00
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c00003d2
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c00003d3
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f800023f
0d0e0f04
c0840708
bf8c000f
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80021100
c082070c
bf8c0070
e00c2000
80010d00
bf8c0770
060c230d
06001b06
060e250e
06081d07
f800024f
00040706
c000033c
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100c1200
c000033d
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d2820006
0418010a
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060c0c00
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100e1200
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d2820007
041c010a
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060e0e00
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f800025f
06070400
c00003dc
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d2820000
04060a00
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10020600
08020b01
c00003dd
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FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..30]
DCL TEMP[0..2], LOCAL
DCL TEMP[3], ARRAY(1), LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
  2: MUL TEMP[0].xyz, TEMP[0].xyzz, IN[0].xyzz
  3: MAD TEMP[1].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
  4: MOV TEMP[2].xy, IN[3].xyyy
  5: TEX TEMP[2].xyz, TEMP[2], SAMP[1], 2D
  6: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[12].xyzz
  7: MIN TEMP[1].x, TEMP[1].xxxx, CONST[11].zzzz
  8: MOV_SAT TEMP[1].x, TEMP[1].xxxx
  9: MUL TEMP[2].xyz, TEMP[0].xyzz, TEMP[2].xyzz
 10: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 11: MAD TEMP[0].xyz, TEMP[2].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 12: MUL TEMP[0].xyz, TEMP[1].xxxx, TEMP[0].xyzz
 13: MAD TEMP[2].xyz, TEMP[2].xyzz, CONST[30].xxxx, TEMP[0].xyzz
 14: MUL TEMP[0].x, IN[2].wwww, CONST[29].wwww
 15: MOV TEMP[2].w, TEMP[0].xxxx
 16: MOV TEMP[3], TEMP[2]
 17: MOV OUT[0], TEMP[3]
 18: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 44
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 46
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 47
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 48
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 49
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 50
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 116
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 117
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 118
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 119
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 120
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %45 = load <32 x i8> addrspace(2)* %44, !tbaa !0
  %46 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0
  %48 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %49 = load <32 x i8> addrspace(2)* %48, !tbaa !0
  %50 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %53 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %54 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %55 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %56 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %57 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %6)
  %59 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %6)
  %60 = bitcast float %55 to i32
  %61 = bitcast float %56 to i32
  %62 = insertelement <2 x i32> undef, i32 %60, i32 0
  %63 = insertelement <2 x i32> %62, i32 %61, i32 1
  %64 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %63, <32 x i8> %45, <16 x i8> %47, i32 2)
  %65 = extractelement <4 x float> %64, i32 0
  %66 = extractelement <4 x float> %64, i32 1
  %67 = extractelement <4 x float> %64, i32 2
  %68 = fmul float %65, %52
  %69 = fmul float %66, %53
  %70 = fmul float %67, %54
  %71 = fsub float -0.000000e+00, %23
  %72 = fmul float %57, %27
  %73 = fadd float %72, %71
  %74 = bitcast float %58 to i32
  %75 = bitcast float %59 to i32
  %76 = insertelement <2 x i32> undef, i32 %74, i32 0
  %77 = insertelement <2 x i32> %76, i32 %75, i32 1
  %78 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %77, <32 x i8> %49, <16 x i8> %51, i32 2)
  %79 = extractelement <4 x float> %78, i32 0
  %80 = extractelement <4 x float> %78, i32 1
  %81 = extractelement <4 x float> %78, i32 2
  %82 = fmul float %79, %29
  %83 = fmul float %80, %31
  %84 = fmul float %81, %33
  %85 = fcmp uge float %73, %25
  %86 = select i1 %85, float %25, float %73
  %87 = call float @llvm.AMDIL.clamp.(float %86, float 0.000000e+00, float 1.000000e+00)
  %88 = fmul float %68, %82
  %89 = fmul float %69, %83
  %90 = fmul float %70, %84
  %91 = fmul float %87, %87
  %92 = fsub float -0.000000e+00, %43
  %93 = fmul float %88, %92
  %94 = fadd float %93, %35
  %95 = fsub float -0.000000e+00, %43
  %96 = fmul float %89, %95
  %97 = fadd float %96, %37
  %98 = fsub float -0.000000e+00, %43
  %99 = fmul float %90, %98
  %100 = fadd float %99, %39
  %101 = fmul float %91, %94
  %102 = fmul float %91, %97
  %103 = fmul float %91, %100
  %104 = fmul float %88, %43
  %105 = fadd float %104, %101
  %106 = fmul float %89, %43
  %107 = fadd float %106, %102
  %108 = fmul float %90, %43
  %109 = fadd float %108, %103
  %110 = fmul float %57, %41
  %111 = call i32 @llvm.SI.packf16(float %105, float %107)
  %112 = bitcast i32 %111 to float
  %113 = call i32 @llvm.SI.packf16(float %109, float %110)
  %114 = bitcast i32 %113 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %112, float %114, float %112, float %114)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR2, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR3, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR2, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR3, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%50](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%48](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 49; mem:LD4[%30]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%46](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%44](tbaa=!"const")
	S_WAITCNT 127
	%VGPR5_VGPR6_VGPR7<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR9<def> = V_MUL_F32_e32 %VGPR6, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%42]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%36]
	S_WAITCNT 127
	%VGPR11<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 47; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 44; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR9<def> = V_SUBREV_F32_e32 %SGPR3<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 46; mem:LD4[%24]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR9, %SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 %VGPR9<kill>, %VGPR12<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e64 %VGPR9<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR9, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR10<kill>, %SGPR2, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR5, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %SGPR2, %VGPR11, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 116; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR12<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR9, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %SGPR2, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR11<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR4, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4<imp-use,kill>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR7, %VGPR3<kill>, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2, %VGPR0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 118; mem:LD4[%38]
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 119; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR10<kill>, %VGPR0<kill>, %VGPR10, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140d02
c8150d03
c8100c02
c8110c03
c0840304
c0c60508
bf8c007f
f0800700
00430204
c0400100
bf8c0070
c0038131
bf8c007f
10100607
c8180500
c8190501
c8140400
c8150401
c0840300
c0c60500
bf8c007f
f0800700
00430505
c8240100
c8250101
bf8c0770
10121306
10141109
c0010178
bf8c007f
10101402
c0018175
bf8c007f
08161003
c8200b00
c8210b01
c001812f
bf8c007f
10121003
c001812c
bf8c007f
0a121203
c001812e
bf8c007f
d00c0004
02000709
7e180203
d2000009
00121909
d2060809
02010109
10121309
10161709
d282000a
042c050a
c0018130
bf8c007f
10160403
c8300000
c8310001
10181905
1016170c
10181602
c0018174
bf8c007f
08181803
10181909
d282000b
0430050b
5e14150b
c0018132
bf8c007f
10040803
c80c0200
c80d0201
10000707
10000500
10020002
c0018176
bf8c007f
08020203
10020309
d2820000
04040500
c0000177
bf8c007f
10021000
5e000300
f8001c0f
000a000a
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL CONST[0..51]
DCL TEMP[0..8], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[12]
 10: DP4 TEMP[5].x, TEMP[0], CONST[6]
 11: MOV TEMP[2].z, TEMP[5].xxxx
 12: DP4 TEMP[0].x, TEMP[0], CONST[7]
 13: MOV TEMP[2].w, TEMP[0].xxxx
 14: MOV TEMP[1].w, TEMP[4].xxxx
 15: MOV TEMP[4].xy, IN[1].xyxx
 16: MUL TEMP[6], IN[2].xyxx, CONST[0].yyxx
 17: MAD TEMP[7], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 18: MOV TEMP[8], TEMP[2]
 19: MAD TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
 20: MOV TEMP[2].z, TEMP[5].xxxx
 21: MOV TEMP[2].y, -TEMP[3].xxxx
 22: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[0].xxxx, TEMP[2].xyyy
 23: MOV OUT[3], TEMP[4]
 24: MOV OUT[5], TEMP[6]
 25: MOV OUT[0], TEMP[2]
 26: MOV OUT[4], TEMP[1]
 27: MOV OUT[2], TEMP[8]
 28: MOV_SAT OUT[1], TEMP[7]
 29: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 16
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 17
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 18
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 19
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 20
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 21
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 22
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 23
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 24
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 25
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 26
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 27
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 28
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 29
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 30
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 31
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 48
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 49
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 50
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 51
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 191
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 192
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 193
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 194
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 195
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 196
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 197
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 198
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 199
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 200
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 201
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 202
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 203
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 204
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 205
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %5)
  %90 = extractelement <4 x float> %89, i32 0
  %91 = extractelement <4 x float> %89, i32 1
  %92 = extractelement <4 x float> %89, i32 2
  %93 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %94 = load <16 x i8> addrspace(2)* %93, !tbaa !0
  %95 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %94, i32 0, i32 %5)
  %96 = extractelement <4 x float> %95, i32 0
  %97 = extractelement <4 x float> %95, i32 1
  %98 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %99 = load <16 x i8> addrspace(2)* %98, !tbaa !0
  %100 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %99, i32 0, i32 %5)
  %101 = extractelement <4 x float> %100, i32 0
  %102 = extractelement <4 x float> %100, i32 1
  %103 = fmul float %90, %14
  %104 = fadd float %103, %12
  %105 = fmul float %91, %14
  %106 = fadd float %105, %12
  %107 = fmul float %92, %14
  %108 = fadd float %107, %12
  %109 = fmul float %90, %12
  %110 = fadd float %109, %14
  %111 = fmul float %104, %60
  %112 = fmul float %106, %62
  %113 = fadd float %111, %112
  %114 = fmul float %108, %64
  %115 = fadd float %113, %114
  %116 = fmul float %110, %66
  %117 = fadd float %115, %116
  %118 = fmul float %104, %68
  %119 = fmul float %106, %70
  %120 = fadd float %118, %119
  %121 = fmul float %108, %72
  %122 = fadd float %120, %121
  %123 = fmul float %110, %74
  %124 = fadd float %122, %123
  %125 = fmul float %104, %76
  %126 = fmul float %106, %78
  %127 = fadd float %125, %126
  %128 = fmul float %108, %80
  %129 = fadd float %127, %128
  %130 = fmul float %110, %82
  %131 = fadd float %129, %130
  %132 = fmul float %104, %18
  %133 = fmul float %106, %20
  %134 = fadd float %132, %133
  %135 = fmul float %108, %22
  %136 = fadd float %134, %135
  %137 = fmul float %110, %24
  %138 = fadd float %136, %137
  %139 = fmul float %104, %26
  %140 = fmul float %106, %28
  %141 = fadd float %139, %140
  %142 = fmul float %108, %30
  %143 = fadd float %141, %142
  %144 = fmul float %110, %32
  %145 = fadd float %143, %144
  %146 = fmul float %104, %50
  %147 = fmul float %106, %52
  %148 = fadd float %146, %147
  %149 = fmul float %108, %54
  %150 = fadd float %148, %149
  %151 = fmul float %110, %56
  %152 = fadd float %150, %151
  %153 = fmul float %104, %34
  %154 = fmul float %106, %36
  %155 = fadd float %153, %154
  %156 = fmul float %108, %38
  %157 = fadd float %155, %156
  %158 = fmul float %110, %40
  %159 = fadd float %157, %158
  %160 = fmul float %104, %42
  %161 = fmul float %106, %44
  %162 = fadd float %160, %161
  %163 = fmul float %108, %46
  %164 = fadd float %162, %163
  %165 = fmul float %110, %48
  %166 = fadd float %164, %165
  %167 = fmul float %101, %14
  %168 = fmul float %102, %14
  %169 = fmul float %101, %12
  %170 = fmul float %101, %12
  %171 = fmul float %58, %12
  %172 = fadd float %171, %14
  %173 = fmul float %58, %12
  %174 = fadd float %173, %14
  %175 = fmul float %58, %12
  %176 = fadd float %175, %14
  %177 = fmul float %58, %14
  %178 = fadd float %177, %12
  %179 = fsub float -0.000000e+00, %166
  %180 = fmul float %159, %16
  %181 = fadd float %180, %179
  %182 = fsub float -0.000000e+00, %145
  %183 = fmul float %84, %166
  %184 = fadd float %183, %138
  %185 = fmul float %86, %166
  %186 = fadd float %185, %182
  %187 = call float @llvm.AMDIL.clamp.(float %172, float 0.000000e+00, float 1.000000e+00)
  %188 = call float @llvm.AMDIL.clamp.(float %174, float 0.000000e+00, float 1.000000e+00)
  %189 = call float @llvm.AMDIL.clamp.(float %176, float 0.000000e+00, float 1.000000e+00)
  %190 = call float @llvm.AMDIL.clamp.(float %178, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %187, float %188, float %189, float %190)
  %191 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %192 = load float addrspace(2)* addrspace(2)* %191, !tbaa !0
  %193 = getelementptr float addrspace(2)* %192, i32 0
  %194 = load float addrspace(2)* %193, !tbaa !0
  %195 = fmul float %194, %138
  %196 = getelementptr float addrspace(2)* %192, i32 1
  %197 = load float addrspace(2)* %196, !tbaa !0
  %198 = fmul float %197, %145
  %199 = fadd float %195, %198
  %200 = getelementptr float addrspace(2)* %192, i32 2
  %201 = load float addrspace(2)* %200, !tbaa !0
  %202 = fmul float %201, %159
  %203 = fadd float %199, %202
  %204 = getelementptr float addrspace(2)* %192, i32 3
  %205 = load float addrspace(2)* %204, !tbaa !0
  %206 = fmul float %205, %166
  %207 = fadd float %203, %206
  %208 = getelementptr float addrspace(2)* %192, i32 4
  %209 = load float addrspace(2)* %208, !tbaa !0
  %210 = fmul float %209, %138
  %211 = getelementptr float addrspace(2)* %192, i32 5
  %212 = load float addrspace(2)* %211, !tbaa !0
  %213 = fmul float %212, %145
  %214 = fadd float %210, %213
  %215 = getelementptr float addrspace(2)* %192, i32 6
  %216 = load float addrspace(2)* %215, !tbaa !0
  %217 = fmul float %216, %159
  %218 = fadd float %214, %217
  %219 = getelementptr float addrspace(2)* %192, i32 7
  %220 = load float addrspace(2)* %219, !tbaa !0
  %221 = fmul float %220, %166
  %222 = fadd float %218, %221
  %223 = getelementptr float addrspace(2)* %192, i32 8
  %224 = load float addrspace(2)* %223, !tbaa !0
  %225 = fmul float %224, %138
  %226 = getelementptr float addrspace(2)* %192, i32 9
  %227 = load float addrspace(2)* %226, !tbaa !0
  %228 = fmul float %227, %145
  %229 = fadd float %225, %228
  %230 = getelementptr float addrspace(2)* %192, i32 10
  %231 = load float addrspace(2)* %230, !tbaa !0
  %232 = fmul float %231, %159
  %233 = fadd float %229, %232
  %234 = getelementptr float addrspace(2)* %192, i32 11
  %235 = load float addrspace(2)* %234, !tbaa !0
  %236 = fmul float %235, %166
  %237 = fadd float %233, %236
  %238 = getelementptr float addrspace(2)* %192, i32 12
  %239 = load float addrspace(2)* %238, !tbaa !0
  %240 = fmul float %239, %138
  %241 = getelementptr float addrspace(2)* %192, i32 13
  %242 = load float addrspace(2)* %241, !tbaa !0
  %243 = fmul float %242, %145
  %244 = fadd float %240, %243
  %245 = getelementptr float addrspace(2)* %192, i32 14
  %246 = load float addrspace(2)* %245, !tbaa !0
  %247 = fmul float %246, %159
  %248 = fadd float %244, %247
  %249 = getelementptr float addrspace(2)* %192, i32 15
  %250 = load float addrspace(2)* %249, !tbaa !0
  %251 = fmul float %250, %166
  %252 = fadd float %248, %251
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %207, float %222, float %237, float %252)
  %253 = getelementptr float addrspace(2)* %192, i32 16
  %254 = load float addrspace(2)* %253, !tbaa !0
  %255 = fmul float %254, %138
  %256 = getelementptr float addrspace(2)* %192, i32 17
  %257 = load float addrspace(2)* %256, !tbaa !0
  %258 = fmul float %257, %145
  %259 = fadd float %255, %258
  %260 = getelementptr float addrspace(2)* %192, i32 18
  %261 = load float addrspace(2)* %260, !tbaa !0
  %262 = fmul float %261, %159
  %263 = fadd float %259, %262
  %264 = getelementptr float addrspace(2)* %192, i32 19
  %265 = load float addrspace(2)* %264, !tbaa !0
  %266 = fmul float %265, %166
  %267 = fadd float %263, %266
  %268 = getelementptr float addrspace(2)* %192, i32 20
  %269 = load float addrspace(2)* %268, !tbaa !0
  %270 = fmul float %269, %138
  %271 = getelementptr float addrspace(2)* %192, i32 21
  %272 = load float addrspace(2)* %271, !tbaa !0
  %273 = fmul float %272, %145
  %274 = fadd float %270, %273
  %275 = getelementptr float addrspace(2)* %192, i32 22
  %276 = load float addrspace(2)* %275, !tbaa !0
  %277 = fmul float %276, %159
  %278 = fadd float %274, %277
  %279 = getelementptr float addrspace(2)* %192, i32 23
  %280 = load float addrspace(2)* %279, !tbaa !0
  %281 = fmul float %280, %166
  %282 = fadd float %278, %281
  %283 = getelementptr float addrspace(2)* %192, i32 24
  %284 = load float addrspace(2)* %283, !tbaa !0
  %285 = fmul float %284, %138
  %286 = getelementptr float addrspace(2)* %192, i32 25
  %287 = load float addrspace(2)* %286, !tbaa !0
  %288 = fmul float %287, %145
  %289 = fadd float %285, %288
  %290 = getelementptr float addrspace(2)* %192, i32 26
  %291 = load float addrspace(2)* %290, !tbaa !0
  %292 = fmul float %291, %159
  %293 = fadd float %289, %292
  %294 = getelementptr float addrspace(2)* %192, i32 27
  %295 = load float addrspace(2)* %294, !tbaa !0
  %296 = fmul float %295, %166
  %297 = fadd float %293, %296
  %298 = getelementptr float addrspace(2)* %192, i32 28
  %299 = load float addrspace(2)* %298, !tbaa !0
  %300 = fmul float %299, %138
  %301 = getelementptr float addrspace(2)* %192, i32 29
  %302 = load float addrspace(2)* %301, !tbaa !0
  %303 = fmul float %302, %145
  %304 = fadd float %300, %303
  %305 = getelementptr float addrspace(2)* %192, i32 30
  %306 = load float addrspace(2)* %305, !tbaa !0
  %307 = fmul float %306, %159
  %308 = fadd float %304, %307
  %309 = getelementptr float addrspace(2)* %192, i32 31
  %310 = load float addrspace(2)* %309, !tbaa !0
  %311 = fmul float %310, %166
  %312 = fadd float %308, %311
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %267, float %282, float %297, float %312)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %96, float %97, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %117, float %124, float %131, float %152)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %167, float %168, float %169, float %170)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %184, float %186, float %181, float %166)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 191; mem:LD4[%57]
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR8, %VGPR1, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%87](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR4, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR4, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 17; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 16; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR4, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 18; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6, %SGPR5, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 19; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 21; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 20; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 22; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 23; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%191](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%241]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%238]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 25; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 24; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 26; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 27; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%245]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 29; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 28; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 30; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 31; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%249]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%226]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%223]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%230]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%234]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%211]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%208]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%215]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%219]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%196]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%193]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%200]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%204]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%301]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%298]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%305]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%309]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%286]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%283]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%290]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%294]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%271]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%268]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%275]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%279]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%256]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%253]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%260]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%264]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%93](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13<kill>, %VGPR13, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 49; mem:LD4[%51]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 48; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 50; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 51; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 201; mem:LD4[%77]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 200; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 202; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 203; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 198; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 199; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 194; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 195; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR2<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 8; mem:LD16[%98](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4, %VGPR10, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	EXP 15, 35, 0, 0, 0, %VGPR4<kill>, %VGPR2<kill>, %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 204; mem:LD4[%83]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 205; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0410100
bf8c007f
c00403bf
c0028300
bf8c007f
7e060205
c0020301
bf8c007f
7e020204
d2820002
040e0208
d2060802
02010102
d2820004
04060608
d2060804
02010104
f800020f
02040404
c0840700
bf8c000f
e00c2000
80020600
bf8c0770
d2820002
040c0906
d2820004
040c0907
c0040311
bf8c007f
100a0808
c0040310
bf8c007f
d282000a
04141102
d2820005
040c0908
c0040312
bf8c007f
d2820003
04281105
d2820006
04040b06
c0040313
bf8c007f
d2820001
040c1106
c0040315
bf8c007f
10060808
c0040314
bf8c007f
d2820003
040c1102
c0040316
bf8c007f
d2820003
040c1105
c0040317
bf8c007f
d2820003
040c1106
c0400102
bf8c007f
c004010d
bf8c007f
100e0608
c004010c
bf8c007f
d2820008
041e0208
c0040319
bf8c007f
100e0808
c0040318
bf8c007f
d2820007
041c1102
c004031a
bf8c007f
d2820007
041c1105
c004031b
bf8c007f
d2820007
041c1106
c004010e
bf8c007f
d2820009
04220e08
c004031d
bf8c007f
10100808
c004031c
bf8c007f
d2820008
04201102
c004031e
bf8c007f
d2820008
04201105
c004031f
bf8c007f
d2820008
04201106
c004010f
bf8c007f
d2820009
04261008
c0040109
bf8c007f
10140608
c0040108
bf8c007f
d282000a
042a0208
c004010a
bf8c007f
d282000a
042a0e08
c004010b
bf8c007f
d282000a
042a1008
c0040105
bf8c007f
10160608
c0040104
bf8c007f
d282000b
042e0208
c0040106
bf8c007f
d282000b
042e0e08
c0040107
bf8c007f
d282000b
042e1008
c0040101
bf8c007f
10180608
c0040100
bf8c007f
d282000c
04320208
c0040102
bf8c007f
d282000c
04320e08
c0040103
bf8c007f
d282000c
04321008
f80000ef
090a0b0c
c004011d
bf8c000f
10120608
c004011c
bf8c007f
d2820009
04260208
c004011e
bf8c007f
d2820009
04260e08
c004011f
bf8c007f
d2820009
04261008
c0040119
bf8c007f
10140608
c0040118
bf8c007f
d282000a
042a0208
c004011a
bf8c007f
d282000a
042a0e08
c004011b
bf8c007f
d282000a
042a1008
c0040115
bf8c007f
10160608
c0040114
bf8c007f
d282000b
042e0208
c0040116
bf8c007f
d282000b
042e0e08
c0040117
bf8c007f
d282000b
042e1008
c0040111
bf8c007f
10180608
c0040110
bf8c007f
d282000c
04320208
c0040112
bf8c007f
d282000c
04320e08
c0000113
bf8c007f
d282000c
04321000
f80000ff
090a0b0c
c0840704
bf8c000f
e00c2000
80020900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c0000331
bf8c000f
10120800
c0000330
bf8c007f
d2820009
04240102
c0000332
bf8c007f
d2820009
04240105
c0000333
bf8c007f
d2820009
04240106
c00003c9
bf8c007f
10140800
c00003c8
bf8c007f
d282000a
04280102
c00003ca
bf8c007f
d282000a
04280105
c00003cb
bf8c007f
d282000a
04280106
c00003c5
bf8c007f
10160800
c00003c4
bf8c007f
d282000b
042c0102
c00003c6
bf8c007f
d282000b
042c0105
c00003c7
bf8c007f
d282000b
042c0106
c00003c1
bf8c007f
10080800
c00003c0
bf8c007f
d2820002
04100102
c00003c2
bf8c007f
d2820002
04080105
c00003c3
bf8c007f
d2820002
04080106
f800022f
090a0b02
c0840708
bf8c000f
e00c2000
80020900
bf8c0770
10001205
10041404
10081204
f800023f
00000204
c00003cc
bf8c000f
d2820000
04061000
c0000302
bf8c007f
10020e00
08021101
c00003cd
bf8c007f
10041000
08040702
f80008cf
08010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..30]
DCL TEMP[0..3], LOCAL
DCL TEMP[4], ARRAY(1), LOCAL
  0: MOV TEMP[0].xy, IN[3].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[1], 2D
  2: MOV TEMP[1].xy, IN[1].xyyy
  3: TEX TEMP[1], TEMP[1], SAMP[0], 2D
  4: MUL TEMP[2].xyz, TEMP[0].xyzz, CONST[12].xyzz
  5: MUL TEMP[0].xyz, TEMP[1].xyzz, IN[0].xyzz
  6: MUL TEMP[0].xyz, TEMP[2].xyzz, TEMP[0].xyzz
  7: MAD TEMP[2].xyz, TEMP[1].xyzz, IN[0].xyzz, -TEMP[0].xyzz
  8: MAD TEMP[3].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
  9: MAD TEMP[2].xyz, TEMP[1].wwww, TEMP[2].xyzz, TEMP[0].xyzz
 10: MIN TEMP[1].x, TEMP[3].xxxx, CONST[11].zzzz
 11: MOV_SAT TEMP[1].x, TEMP[1].xxxx
 12: MAD TEMP[0].xyz, TEMP[2].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 13: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 14: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx
 15: MAD TEMP[2].xyz, TEMP[2].xyzz, CONST[30].xxxx, TEMP[0].xyzz
 16: MUL TEMP[0].x, IN[2].wwww, CONST[29].wwww
 17: MOV TEMP[2].w, TEMP[0].xxxx
 18: MOV TEMP[4], TEMP[2]
 19: MOV OUT[0], TEMP[4]
 20: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 44
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 46
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 47
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 48
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 49
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 50
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 116
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 117
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 118
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 119
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 120
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %45 = load <32 x i8> addrspace(2)* %44, !tbaa !0
  %46 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0
  %48 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %49 = load <32 x i8> addrspace(2)* %48, !tbaa !0
  %50 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %53 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %54 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %55 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %56 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %57 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %6)
  %59 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %6)
  %60 = bitcast float %58 to i32
  %61 = bitcast float %59 to i32
  %62 = insertelement <2 x i32> undef, i32 %60, i32 0
  %63 = insertelement <2 x i32> %62, i32 %61, i32 1
  %64 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %63, <32 x i8> %49, <16 x i8> %51, i32 2)
  %65 = extractelement <4 x float> %64, i32 0
  %66 = extractelement <4 x float> %64, i32 1
  %67 = extractelement <4 x float> %64, i32 2
  %68 = bitcast float %55 to i32
  %69 = bitcast float %56 to i32
  %70 = insertelement <2 x i32> undef, i32 %68, i32 0
  %71 = insertelement <2 x i32> %70, i32 %69, i32 1
  %72 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %71, <32 x i8> %45, <16 x i8> %47, i32 2)
  %73 = extractelement <4 x float> %72, i32 0
  %74 = extractelement <4 x float> %72, i32 1
  %75 = extractelement <4 x float> %72, i32 2
  %76 = extractelement <4 x float> %72, i32 3
  %77 = fmul float %65, %29
  %78 = fmul float %66, %31
  %79 = fmul float %67, %33
  %80 = fmul float %73, %52
  %81 = fmul float %74, %53
  %82 = fmul float %75, %54
  %83 = fmul float %77, %80
  %84 = fmul float %78, %81
  %85 = fmul float %79, %82
  %86 = fsub float -0.000000e+00, %83
  %87 = fmul float %73, %52
  %88 = fadd float %87, %86
  %89 = fsub float -0.000000e+00, %84
  %90 = fmul float %74, %53
  %91 = fadd float %90, %89
  %92 = fsub float -0.000000e+00, %85
  %93 = fmul float %75, %54
  %94 = fadd float %93, %92
  %95 = fsub float -0.000000e+00, %23
  %96 = fmul float %57, %27
  %97 = fadd float %96, %95
  %98 = fmul float %76, %88
  %99 = fadd float %98, %83
  %100 = fmul float %76, %91
  %101 = fadd float %100, %84
  %102 = fmul float %76, %94
  %103 = fadd float %102, %85
  %104 = fcmp uge float %97, %25
  %105 = select i1 %104, float %25, float %97
  %106 = call float @llvm.AMDIL.clamp.(float %105, float 0.000000e+00, float 1.000000e+00)
  %107 = fsub float -0.000000e+00, %43
  %108 = fmul float %99, %107
  %109 = fadd float %108, %35
  %110 = fsub float -0.000000e+00, %43
  %111 = fmul float %101, %110
  %112 = fadd float %111, %37
  %113 = fsub float -0.000000e+00, %43
  %114 = fmul float %103, %113
  %115 = fadd float %114, %39
  %116 = fmul float %106, %106
  %117 = fmul float %109, %116
  %118 = fmul float %112, %116
  %119 = fmul float %115, %116
  %120 = fmul float %99, %43
  %121 = fadd float %120, %117
  %122 = fmul float %101, %43
  %123 = fadd float %122, %118
  %124 = fmul float %103, %43
  %125 = fadd float %124, %119
  %126 = fmul float %57, %41
  %127 = call i32 @llvm.SI.packf16(float %121, float %123)
  %128 = bitcast i32 %127 to float
  %129 = call i32 @llvm.SI.packf16(float %125, float %126)
  %130 = bitcast i32 %129 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %128, float %130, float %128, float %130)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%46](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%44](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6_VGPR7<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR11<def> = V_MUL_F32_e32 %VGPR5, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR2, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<tied0>, %VGPR3, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR2, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR3, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%50](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%48](tbaa=!"const")
	S_WAITCNT 127
	%VGPR8_VGPR9_VGPR10<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR8_VGPR9<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 49; mem:LD4[%30]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR7, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%42]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR11, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%36]
	S_WAITCNT 127
	%VGPR12<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 47; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 44; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR3<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 46; mem:LD4[%24]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR13<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %SGPR2, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR4, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR12<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR7, %VGPR12<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %SGPR2, %VGPR12, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 116; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR13<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %SGPR2, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR12<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR6, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR10, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10<imp-use,kill>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR0<def> = V_SUB_F32_e32 %VGPR0<kill>, %VGPR1, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR7, %VGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7<imp-use,kill>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2, %VGPR0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 118; mem:LD4[%38]
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 119; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR11<kill>, %VGPR0<kill>, %VGPR11, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140500
c8150501
c8100400
c8110401
c0840300
c0c60500
bf8c007f
f0800f00
00430404
c8200100
c8210101
bf8c0770
10161105
c8240d02
c8250d03
c8200c02
c8210c03
c0840304
c0c60508
bf8c007f
f0800700
00430808
c0400100
bf8c0070
c0010131
bf8c007f
10041202
10041702
0806050b
d282000b
040a0707
c0010178
bf8c007f
10041602
c0018175
bf8c007f
08180403
c8080b00
c8090b01
c001812f
bf8c007f
10060403
c001812c
bf8c007f
0a060603
c001812e
bf8c007f
d00c0004
02000703
7e1a0203
d2000003
00121b03
d2060803
02010103
10060703
1018070c
d282000b
0430050b
c8300000
c8310001
10181904
c0018130
bf8c007f
101a1003
101a190d
08181b0c
d282000c
04361907
101a1802
c0018174
bf8c007f
081a1a03
101a070d
d282000c
0434050c
5e16170c
c8300200
c8310201
10001906
c0018132
bf8c007f
10021403
10020101
08000300
d2820000
04060107
10020002
c0018176
bf8c007f
08020203
10020701
d2820000
04040500
c0000177
bf8c007f
10020400
5e000300
f8001c0f
000b000b
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL CONST[0..51]
DCL TEMP[0..8], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[12]
 10: DP4 TEMP[5].x, TEMP[0], CONST[6]
 11: MOV TEMP[2].z, TEMP[5].xxxx
 12: DP4 TEMP[0].x, TEMP[0], CONST[7]
 13: MOV TEMP[2].w, TEMP[0].xxxx
 14: MOV TEMP[1].w, TEMP[4].xxxx
 15: MOV TEMP[4].xy, IN[1].xyxx
 16: MUL TEMP[6], IN[2].xyxx, CONST[0].yyxx
 17: MAD TEMP[7], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 18: MOV TEMP[8], TEMP[2]
 19: MAD TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
 20: MOV TEMP[2].z, TEMP[5].xxxx
 21: MOV TEMP[2].y, -TEMP[3].xxxx
 22: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[0].xxxx, TEMP[2].xyyy
 23: MOV OUT[3], TEMP[4]
 24: MOV OUT[5], TEMP[6]
 25: MOV OUT[0], TEMP[2]
 26: MOV OUT[4], TEMP[1]
 27: MOV OUT[2], TEMP[8]
 28: MOV_SAT OUT[1], TEMP[7]
 29: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 16
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 17
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 18
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 19
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 20
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 21
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 22
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 23
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 24
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 25
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 26
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 27
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 28
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 29
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 30
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 31
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 48
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 49
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 50
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 51
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 191
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 192
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 193
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 194
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 195
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 196
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 197
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 198
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 199
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 200
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 201
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 202
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 203
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 204
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 205
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %5)
  %90 = extractelement <4 x float> %89, i32 0
  %91 = extractelement <4 x float> %89, i32 1
  %92 = extractelement <4 x float> %89, i32 2
  %93 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %94 = load <16 x i8> addrspace(2)* %93, !tbaa !0
  %95 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %94, i32 0, i32 %5)
  %96 = extractelement <4 x float> %95, i32 0
  %97 = extractelement <4 x float> %95, i32 1
  %98 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %99 = load <16 x i8> addrspace(2)* %98, !tbaa !0
  %100 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %99, i32 0, i32 %5)
  %101 = extractelement <4 x float> %100, i32 0
  %102 = extractelement <4 x float> %100, i32 1
  %103 = fmul float %90, %14
  %104 = fadd float %103, %12
  %105 = fmul float %91, %14
  %106 = fadd float %105, %12
  %107 = fmul float %92, %14
  %108 = fadd float %107, %12
  %109 = fmul float %90, %12
  %110 = fadd float %109, %14
  %111 = fmul float %104, %60
  %112 = fmul float %106, %62
  %113 = fadd float %111, %112
  %114 = fmul float %108, %64
  %115 = fadd float %113, %114
  %116 = fmul float %110, %66
  %117 = fadd float %115, %116
  %118 = fmul float %104, %68
  %119 = fmul float %106, %70
  %120 = fadd float %118, %119
  %121 = fmul float %108, %72
  %122 = fadd float %120, %121
  %123 = fmul float %110, %74
  %124 = fadd float %122, %123
  %125 = fmul float %104, %76
  %126 = fmul float %106, %78
  %127 = fadd float %125, %126
  %128 = fmul float %108, %80
  %129 = fadd float %127, %128
  %130 = fmul float %110, %82
  %131 = fadd float %129, %130
  %132 = fmul float %104, %18
  %133 = fmul float %106, %20
  %134 = fadd float %132, %133
  %135 = fmul float %108, %22
  %136 = fadd float %134, %135
  %137 = fmul float %110, %24
  %138 = fadd float %136, %137
  %139 = fmul float %104, %26
  %140 = fmul float %106, %28
  %141 = fadd float %139, %140
  %142 = fmul float %108, %30
  %143 = fadd float %141, %142
  %144 = fmul float %110, %32
  %145 = fadd float %143, %144
  %146 = fmul float %104, %50
  %147 = fmul float %106, %52
  %148 = fadd float %146, %147
  %149 = fmul float %108, %54
  %150 = fadd float %148, %149
  %151 = fmul float %110, %56
  %152 = fadd float %150, %151
  %153 = fmul float %104, %34
  %154 = fmul float %106, %36
  %155 = fadd float %153, %154
  %156 = fmul float %108, %38
  %157 = fadd float %155, %156
  %158 = fmul float %110, %40
  %159 = fadd float %157, %158
  %160 = fmul float %104, %42
  %161 = fmul float %106, %44
  %162 = fadd float %160, %161
  %163 = fmul float %108, %46
  %164 = fadd float %162, %163
  %165 = fmul float %110, %48
  %166 = fadd float %164, %165
  %167 = fmul float %101, %14
  %168 = fmul float %102, %14
  %169 = fmul float %101, %12
  %170 = fmul float %101, %12
  %171 = fmul float %58, %12
  %172 = fadd float %171, %14
  %173 = fmul float %58, %12
  %174 = fadd float %173, %14
  %175 = fmul float %58, %12
  %176 = fadd float %175, %14
  %177 = fmul float %58, %14
  %178 = fadd float %177, %12
  %179 = fsub float -0.000000e+00, %166
  %180 = fmul float %159, %16
  %181 = fadd float %180, %179
  %182 = fsub float -0.000000e+00, %145
  %183 = fmul float %84, %166
  %184 = fadd float %183, %138
  %185 = fmul float %86, %166
  %186 = fadd float %185, %182
  %187 = call float @llvm.AMDIL.clamp.(float %172, float 0.000000e+00, float 1.000000e+00)
  %188 = call float @llvm.AMDIL.clamp.(float %174, float 0.000000e+00, float 1.000000e+00)
  %189 = call float @llvm.AMDIL.clamp.(float %176, float 0.000000e+00, float 1.000000e+00)
  %190 = call float @llvm.AMDIL.clamp.(float %178, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %187, float %188, float %189, float %190)
  %191 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %192 = load float addrspace(2)* addrspace(2)* %191, !tbaa !0
  %193 = getelementptr float addrspace(2)* %192, i32 0
  %194 = load float addrspace(2)* %193, !tbaa !0
  %195 = fmul float %194, %138
  %196 = getelementptr float addrspace(2)* %192, i32 1
  %197 = load float addrspace(2)* %196, !tbaa !0
  %198 = fmul float %197, %145
  %199 = fadd float %195, %198
  %200 = getelementptr float addrspace(2)* %192, i32 2
  %201 = load float addrspace(2)* %200, !tbaa !0
  %202 = fmul float %201, %159
  %203 = fadd float %199, %202
  %204 = getelementptr float addrspace(2)* %192, i32 3
  %205 = load float addrspace(2)* %204, !tbaa !0
  %206 = fmul float %205, %166
  %207 = fadd float %203, %206
  %208 = getelementptr float addrspace(2)* %192, i32 4
  %209 = load float addrspace(2)* %208, !tbaa !0
  %210 = fmul float %209, %138
  %211 = getelementptr float addrspace(2)* %192, i32 5
  %212 = load float addrspace(2)* %211, !tbaa !0
  %213 = fmul float %212, %145
  %214 = fadd float %210, %213
  %215 = getelementptr float addrspace(2)* %192, i32 6
  %216 = load float addrspace(2)* %215, !tbaa !0
  %217 = fmul float %216, %159
  %218 = fadd float %214, %217
  %219 = getelementptr float addrspace(2)* %192, i32 7
  %220 = load float addrspace(2)* %219, !tbaa !0
  %221 = fmul float %220, %166
  %222 = fadd float %218, %221
  %223 = getelementptr float addrspace(2)* %192, i32 8
  %224 = load float addrspace(2)* %223, !tbaa !0
  %225 = fmul float %224, %138
  %226 = getelementptr float addrspace(2)* %192, i32 9
  %227 = load float addrspace(2)* %226, !tbaa !0
  %228 = fmul float %227, %145
  %229 = fadd float %225, %228
  %230 = getelementptr float addrspace(2)* %192, i32 10
  %231 = load float addrspace(2)* %230, !tbaa !0
  %232 = fmul float %231, %159
  %233 = fadd float %229, %232
  %234 = getelementptr float addrspace(2)* %192, i32 11
  %235 = load float addrspace(2)* %234, !tbaa !0
  %236 = fmul float %235, %166
  %237 = fadd float %233, %236
  %238 = getelementptr float addrspace(2)* %192, i32 12
  %239 = load float addrspace(2)* %238, !tbaa !0
  %240 = fmul float %239, %138
  %241 = getelementptr float addrspace(2)* %192, i32 13
  %242 = load float addrspace(2)* %241, !tbaa !0
  %243 = fmul float %242, %145
  %244 = fadd float %240, %243
  %245 = getelementptr float addrspace(2)* %192, i32 14
  %246 = load float addrspace(2)* %245, !tbaa !0
  %247 = fmul float %246, %159
  %248 = fadd float %244, %247
  %249 = getelementptr float addrspace(2)* %192, i32 15
  %250 = load float addrspace(2)* %249, !tbaa !0
  %251 = fmul float %250, %166
  %252 = fadd float %248, %251
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %207, float %222, float %237, float %252)
  %253 = getelementptr float addrspace(2)* %192, i32 16
  %254 = load float addrspace(2)* %253, !tbaa !0
  %255 = fmul float %254, %138
  %256 = getelementptr float addrspace(2)* %192, i32 17
  %257 = load float addrspace(2)* %256, !tbaa !0
  %258 = fmul float %257, %145
  %259 = fadd float %255, %258
  %260 = getelementptr float addrspace(2)* %192, i32 18
  %261 = load float addrspace(2)* %260, !tbaa !0
  %262 = fmul float %261, %159
  %263 = fadd float %259, %262
  %264 = getelementptr float addrspace(2)* %192, i32 19
  %265 = load float addrspace(2)* %264, !tbaa !0
  %266 = fmul float %265, %166
  %267 = fadd float %263, %266
  %268 = getelementptr float addrspace(2)* %192, i32 20
  %269 = load float addrspace(2)* %268, !tbaa !0
  %270 = fmul float %269, %138
  %271 = getelementptr float addrspace(2)* %192, i32 21
  %272 = load float addrspace(2)* %271, !tbaa !0
  %273 = fmul float %272, %145
  %274 = fadd float %270, %273
  %275 = getelementptr float addrspace(2)* %192, i32 22
  %276 = load float addrspace(2)* %275, !tbaa !0
  %277 = fmul float %276, %159
  %278 = fadd float %274, %277
  %279 = getelementptr float addrspace(2)* %192, i32 23
  %280 = load float addrspace(2)* %279, !tbaa !0
  %281 = fmul float %280, %166
  %282 = fadd float %278, %281
  %283 = getelementptr float addrspace(2)* %192, i32 24
  %284 = load float addrspace(2)* %283, !tbaa !0
  %285 = fmul float %284, %138
  %286 = getelementptr float addrspace(2)* %192, i32 25
  %287 = load float addrspace(2)* %286, !tbaa !0
  %288 = fmul float %287, %145
  %289 = fadd float %285, %288
  %290 = getelementptr float addrspace(2)* %192, i32 26
  %291 = load float addrspace(2)* %290, !tbaa !0
  %292 = fmul float %291, %159
  %293 = fadd float %289, %292
  %294 = getelementptr float addrspace(2)* %192, i32 27
  %295 = load float addrspace(2)* %294, !tbaa !0
  %296 = fmul float %295, %166
  %297 = fadd float %293, %296
  %298 = getelementptr float addrspace(2)* %192, i32 28
  %299 = load float addrspace(2)* %298, !tbaa !0
  %300 = fmul float %299, %138
  %301 = getelementptr float addrspace(2)* %192, i32 29
  %302 = load float addrspace(2)* %301, !tbaa !0
  %303 = fmul float %302, %145
  %304 = fadd float %300, %303
  %305 = getelementptr float addrspace(2)* %192, i32 30
  %306 = load float addrspace(2)* %305, !tbaa !0
  %307 = fmul float %306, %159
  %308 = fadd float %304, %307
  %309 = getelementptr float addrspace(2)* %192, i32 31
  %310 = load float addrspace(2)* %309, !tbaa !0
  %311 = fmul float %310, %166
  %312 = fadd float %308, %311
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %267, float %282, float %297, float %312)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %96, float %97, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %117, float %124, float %131, float %152)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %167, float %168, float %169, float %170)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %184, float %186, float %181, float %166)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 191; mem:LD4[%57]
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR8, %VGPR1, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%87](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR4, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR4, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 17; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 16; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR4, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 18; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6, %SGPR5, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 19; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 21; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 20; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 22; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 23; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%191](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%241]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%238]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 25; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 24; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 26; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 27; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%245]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 29; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 28; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 30; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 31; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%249]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%226]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%223]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%230]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%234]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%211]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%208]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%215]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%219]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%196]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%193]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%200]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%204]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%301]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%298]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%305]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%309]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%286]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%283]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%290]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%294]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%271]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%268]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%275]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%279]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%256]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%253]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%260]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%264]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%93](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13<kill>, %VGPR13, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 49; mem:LD4[%51]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 48; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 50; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 51; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 201; mem:LD4[%77]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 200; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 202; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 203; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 198; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 199; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 194; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 195; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR2<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 8; mem:LD16[%98](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4, %VGPR10, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	EXP 15, 35, 0, 0, 0, %VGPR4<kill>, %VGPR2<kill>, %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 204; mem:LD4[%83]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 205; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0410100
bf8c007f
c00403bf
c0028300
bf8c007f
7e060205
c0020301
bf8c007f
7e020204
d2820002
040e0208
d2060802
02010102
d2820004
04060608
d2060804
02010104
f800020f
02040404
c0840700
bf8c000f
e00c2000
80020600
bf8c0770
d2820002
040c0906
d2820004
040c0907
c0040311
bf8c007f
100a0808
c0040310
bf8c007f
d282000a
04141102
d2820005
040c0908
c0040312
bf8c007f
d2820003
04281105
d2820006
04040b06
c0040313
bf8c007f
d2820001
040c1106
c0040315
bf8c007f
10060808
c0040314
bf8c007f
d2820003
040c1102
c0040316
bf8c007f
d2820003
040c1105
c0040317
bf8c007f
d2820003
040c1106
c0400102
bf8c007f
c004010d
bf8c007f
100e0608
c004010c
bf8c007f
d2820008
041e0208
c0040319
bf8c007f
100e0808
c0040318
bf8c007f
d2820007
041c1102
c004031a
bf8c007f
d2820007
041c1105
c004031b
bf8c007f
d2820007
041c1106
c004010e
bf8c007f
d2820009
04220e08
c004031d
bf8c007f
10100808
c004031c
bf8c007f
d2820008
04201102
c004031e
bf8c007f
d2820008
04201105
c004031f
bf8c007f
d2820008
04201106
c004010f
bf8c007f
d2820009
04261008
c0040109
bf8c007f
10140608
c0040108
bf8c007f
d282000a
042a0208
c004010a
bf8c007f
d282000a
042a0e08
c004010b
bf8c007f
d282000a
042a1008
c0040105
bf8c007f
10160608
c0040104
bf8c007f
d282000b
042e0208
c0040106
bf8c007f
d282000b
042e0e08
c0040107
bf8c007f
d282000b
042e1008
c0040101
bf8c007f
10180608
c0040100
bf8c007f
d282000c
04320208
c0040102
bf8c007f
d282000c
04320e08
c0040103
bf8c007f
d282000c
04321008
f80000ef
090a0b0c
c004011d
bf8c000f
10120608
c004011c
bf8c007f
d2820009
04260208
c004011e
bf8c007f
d2820009
04260e08
c004011f
bf8c007f
d2820009
04261008
c0040119
bf8c007f
10140608
c0040118
bf8c007f
d282000a
042a0208
c004011a
bf8c007f
d282000a
042a0e08
c004011b
bf8c007f
d282000a
042a1008
c0040115
bf8c007f
10160608
c0040114
bf8c007f
d282000b
042e0208
c0040116
bf8c007f
d282000b
042e0e08
c0040117
bf8c007f
d282000b
042e1008
c0040111
bf8c007f
10180608
c0040110
bf8c007f
d282000c
04320208
c0040112
bf8c007f
d282000c
04320e08
c0000113
bf8c007f
d282000c
04321000
f80000ff
090a0b0c
c0840704
bf8c000f
e00c2000
80020900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c0000331
bf8c000f
10120800
c0000330
bf8c007f
d2820009
04240102
c0000332
bf8c007f
d2820009
04240105
c0000333
bf8c007f
d2820009
04240106
c00003c9
bf8c007f
10140800
c00003c8
bf8c007f
d282000a
04280102
c00003ca
bf8c007f
d282000a
04280105
c00003cb
bf8c007f
d282000a
04280106
c00003c5
bf8c007f
10160800
c00003c4
bf8c007f
d282000b
042c0102
c00003c6
bf8c007f
d282000b
042c0105
c00003c7
bf8c007f
d282000b
042c0106
c00003c1
bf8c007f
10080800
c00003c0
bf8c007f
d2820002
04100102
c00003c2
bf8c007f
d2820002
04080105
c00003c3
bf8c007f
d2820002
04080106
f800022f
090a0b02
c0840708
bf8c000f
e00c2000
80020900
bf8c0770
10001205
10041404
10081204
f800023f
00000204
c00003cc
bf8c000f
d2820000
04061000
c0000302
bf8c007f
10020e00
08021101
c00003cd
bf8c007f
10041000
08040702
f80008cf
08010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..30]
DCL TEMP[0..3], LOCAL
DCL TEMP[4], ARRAY(1), LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MOV TEMP[1].xy, IN[3].xyyy
  3: TEX TEMP[2].xyz, TEMP[1], SAMP[1], 2D
  4: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[12].xyzz
  5: MAD TEMP[3].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
  6: MUL TEMP[1].xyz, TEMP[0].xyzz, IN[0].xyzz
  7: MIN TEMP[3].x, TEMP[3].xxxx, CONST[11].zzzz
  8: MOV_SAT TEMP[3].x, TEMP[3].xxxx
  9: MUL TEMP[1].xyz, TEMP[2].xyzz, TEMP[1].xyzz
 10: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[3].xxxx
 11: MAD TEMP[2].xyz, TEMP[1].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 12: MUL TEMP[2].xyz, TEMP[3].xxxx, TEMP[2].xyzz
 13: MUL TEMP[3].x, IN[0].wwww, CONST[12].wwww
 14: MAD TEMP[1].xyz, TEMP[1].xyzz, CONST[30].xxxx, TEMP[2].xyzz
 15: MUL TEMP[0].x, TEMP[0].wwww, TEMP[3].xxxx
 16: MOV TEMP[1].w, TEMP[0].xxxx
 17: MOV TEMP[4], TEMP[1]
 18: MOV OUT[0], TEMP[4]
 19: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 44
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 46
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 47
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 48
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 49
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 50
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 51
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 116
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 117
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 118
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 120
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %45 = load <32 x i8> addrspace(2)* %44, !tbaa !0
  %46 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0
  %48 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %49 = load <32 x i8> addrspace(2)* %48, !tbaa !0
  %50 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %53 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %54 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %55 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %56 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %57 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %59 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %6)
  %60 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %6)
  %61 = bitcast float %56 to i32
  %62 = bitcast float %57 to i32
  %63 = insertelement <2 x i32> undef, i32 %61, i32 0
  %64 = insertelement <2 x i32> %63, i32 %62, i32 1
  %65 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %64, <32 x i8> %45, <16 x i8> %47, i32 2)
  %66 = extractelement <4 x float> %65, i32 0
  %67 = extractelement <4 x float> %65, i32 1
  %68 = extractelement <4 x float> %65, i32 2
  %69 = extractelement <4 x float> %65, i32 3
  %70 = bitcast float %59 to i32
  %71 = bitcast float %60 to i32
  %72 = insertelement <2 x i32> undef, i32 %70, i32 0
  %73 = insertelement <2 x i32> %72, i32 %71, i32 1
  %74 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %73, <32 x i8> %49, <16 x i8> %51, i32 2)
  %75 = extractelement <4 x float> %74, i32 0
  %76 = extractelement <4 x float> %74, i32 1
  %77 = extractelement <4 x float> %74, i32 2
  %78 = fmul float %75, %29
  %79 = fmul float %76, %31
  %80 = fmul float %77, %33
  %81 = fsub float -0.000000e+00, %23
  %82 = fmul float %58, %27
  %83 = fadd float %82, %81
  %84 = fmul float %66, %52
  %85 = fmul float %67, %53
  %86 = fmul float %68, %54
  %87 = fcmp uge float %83, %25
  %88 = select i1 %87, float %25, float %83
  %89 = call float @llvm.AMDIL.clamp.(float %88, float 0.000000e+00, float 1.000000e+00)
  %90 = fmul float %78, %84
  %91 = fmul float %79, %85
  %92 = fmul float %80, %86
  %93 = fmul float %89, %89
  %94 = fsub float -0.000000e+00, %43
  %95 = fmul float %90, %94
  %96 = fadd float %95, %37
  %97 = fsub float -0.000000e+00, %43
  %98 = fmul float %91, %97
  %99 = fadd float %98, %39
  %100 = fsub float -0.000000e+00, %43
  %101 = fmul float %92, %100
  %102 = fadd float %101, %41
  %103 = fmul float %93, %96
  %104 = fmul float %93, %99
  %105 = fmul float %93, %102
  %106 = fmul float %55, %35
  %107 = fmul float %90, %43
  %108 = fadd float %107, %103
  %109 = fmul float %91, %43
  %110 = fadd float %109, %104
  %111 = fmul float %92, %43
  %112 = fadd float %111, %105
  %113 = fmul float %69, %106
  %114 = fcmp uge float %113, 0x3FD3131320000000
  %115 = sext i1 %114 to i32
  %116 = trunc i32 %115 to i1
  %117 = select i1 %116, float 1.000000e+00, float -1.000000e+00
  call void @llvm.AMDGPU.kill(float %117)
  %118 = call i32 @llvm.SI.packf16(float %108, float %110)
  %119 = bitcast i32 %118 to float
  %120 = call i32 @llvm.SI.packf16(float %112, float %113)
  %121 = bitcast i32 %120 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %119, float %121, float %119, float %121)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.AMDGPU.kill(float)

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%46](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%44](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6_VGPR7<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 51; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR7, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 2.980392e-01, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 -1.000000e+00, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VCC<def> = V_CMPX_LE_F32_e32 0, %VGPR9<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR5, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR2, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<tied0>, %VGPR3, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR2, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<tied0>, %VGPR3, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%50](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%48](tbaa=!"const")
	S_WAITCNT 127
	%VGPR9_VGPR10_VGPR11<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR9_VGPR10<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 49; mem:LD4[%30]
	S_WAITCNT 112
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR10, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%42]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%38]
	S_WAITCNT 127
	%VGPR12<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 47; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 44; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR2<def> = V_SUBREV_F32_e32 %SGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 46; mem:LD4[%24]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR13<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR2, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %SGPR2, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR4, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %SGPR2, %VGPR12, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 116; mem:LD4[%36]
	S_WAITCNT 127
	%VGPR13<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR2, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %SGPR2, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR12<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR6, %VGPR12<kill>, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7<imp-use,kill>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR11, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 118; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR3<kill>, %VGPR0<kill>, %VGPR3, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140500
c8150501
c8100400
c8110401
c0840300
c0c60500
bf8c007f
f0800f00
00430404
c8200300
c8210301
c0400100
bf8c0070
c0038133
bf8c007f
10101007
10101107
7e1202ff
3e989899
d00c0008
02021308
d2000009
0021e4f3
7c261280
c8240100
c8250101
10181305
c8280d02
c8290d03
c8240c02
c8250c03
c0840304
c0c60508
bf8c007f
f0800700
00430909
c0010131
bf8c0070
10041402
10061902
c0010178
bf8c007f
10040602
c0018175
bf8c007f
08180403
c8080b00
c8090b01
c001812f
bf8c007f
10040403
c001812c
bf8c007f
0a040403
c001812e
bf8c007f
d00c0004
02000702
7e1a0203
d2000002
00121b02
d2060802
02010102
10040502
10181902
d2820003
04300503
c8300000
c8310001
10181904
c0018130
bf8c007f
101a1203
1018190d
101a1802
c0018174
bf8c007f
081a1a03
101a1b02
d282000c
0434050c
5e06070c
c8300200
c8310201
10001906
c0018132
bf8c007f
10021603
10000101
10020002
c0000176
bf8c007f
08020200
10020302
d2820000
04040500
5e001100
f8001c0f
00030003
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL CONST[0..51]
DCL TEMP[0..8], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[12]
 10: DP4 TEMP[5].x, TEMP[0], CONST[6]
 11: MOV TEMP[2].z, TEMP[5].xxxx
 12: DP4 TEMP[0].x, TEMP[0], CONST[7]
 13: MOV TEMP[2].w, TEMP[0].xxxx
 14: MOV TEMP[1].w, TEMP[4].xxxx
 15: MOV TEMP[4].xy, IN[1].xyxx
 16: MUL TEMP[6], IN[2].xyxx, CONST[0].yyxx
 17: MAD TEMP[7], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 18: MOV TEMP[8], TEMP[2]
 19: MAD TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
 20: MOV TEMP[2].z, TEMP[5].xxxx
 21: MOV TEMP[2].y, -TEMP[3].xxxx
 22: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[0].xxxx, TEMP[2].xyyy
 23: MOV OUT[3], TEMP[4]
 24: MOV OUT[5], TEMP[6]
 25: MOV OUT[0], TEMP[2]
 26: MOV OUT[4], TEMP[1]
 27: MOV OUT[2], TEMP[8]
 28: MOV_SAT OUT[1], TEMP[7]
 29: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 16
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 17
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 18
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 19
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 20
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 21
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 22
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 23
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 24
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 25
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 26
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 27
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 28
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 29
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 30
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 31
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 48
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 49
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 50
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 51
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 191
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 192
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 193
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 194
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 195
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 196
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 197
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 198
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 199
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 200
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 201
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 202
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 203
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 204
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 205
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %5)
  %90 = extractelement <4 x float> %89, i32 0
  %91 = extractelement <4 x float> %89, i32 1
  %92 = extractelement <4 x float> %89, i32 2
  %93 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %94 = load <16 x i8> addrspace(2)* %93, !tbaa !0
  %95 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %94, i32 0, i32 %5)
  %96 = extractelement <4 x float> %95, i32 0
  %97 = extractelement <4 x float> %95, i32 1
  %98 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %99 = load <16 x i8> addrspace(2)* %98, !tbaa !0
  %100 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %99, i32 0, i32 %5)
  %101 = extractelement <4 x float> %100, i32 0
  %102 = extractelement <4 x float> %100, i32 1
  %103 = fmul float %90, %14
  %104 = fadd float %103, %12
  %105 = fmul float %91, %14
  %106 = fadd float %105, %12
  %107 = fmul float %92, %14
  %108 = fadd float %107, %12
  %109 = fmul float %90, %12
  %110 = fadd float %109, %14
  %111 = fmul float %104, %60
  %112 = fmul float %106, %62
  %113 = fadd float %111, %112
  %114 = fmul float %108, %64
  %115 = fadd float %113, %114
  %116 = fmul float %110, %66
  %117 = fadd float %115, %116
  %118 = fmul float %104, %68
  %119 = fmul float %106, %70
  %120 = fadd float %118, %119
  %121 = fmul float %108, %72
  %122 = fadd float %120, %121
  %123 = fmul float %110, %74
  %124 = fadd float %122, %123
  %125 = fmul float %104, %76
  %126 = fmul float %106, %78
  %127 = fadd float %125, %126
  %128 = fmul float %108, %80
  %129 = fadd float %127, %128
  %130 = fmul float %110, %82
  %131 = fadd float %129, %130
  %132 = fmul float %104, %18
  %133 = fmul float %106, %20
  %134 = fadd float %132, %133
  %135 = fmul float %108, %22
  %136 = fadd float %134, %135
  %137 = fmul float %110, %24
  %138 = fadd float %136, %137
  %139 = fmul float %104, %26
  %140 = fmul float %106, %28
  %141 = fadd float %139, %140
  %142 = fmul float %108, %30
  %143 = fadd float %141, %142
  %144 = fmul float %110, %32
  %145 = fadd float %143, %144
  %146 = fmul float %104, %50
  %147 = fmul float %106, %52
  %148 = fadd float %146, %147
  %149 = fmul float %108, %54
  %150 = fadd float %148, %149
  %151 = fmul float %110, %56
  %152 = fadd float %150, %151
  %153 = fmul float %104, %34
  %154 = fmul float %106, %36
  %155 = fadd float %153, %154
  %156 = fmul float %108, %38
  %157 = fadd float %155, %156
  %158 = fmul float %110, %40
  %159 = fadd float %157, %158
  %160 = fmul float %104, %42
  %161 = fmul float %106, %44
  %162 = fadd float %160, %161
  %163 = fmul float %108, %46
  %164 = fadd float %162, %163
  %165 = fmul float %110, %48
  %166 = fadd float %164, %165
  %167 = fmul float %101, %14
  %168 = fmul float %102, %14
  %169 = fmul float %101, %12
  %170 = fmul float %101, %12
  %171 = fmul float %58, %12
  %172 = fadd float %171, %14
  %173 = fmul float %58, %12
  %174 = fadd float %173, %14
  %175 = fmul float %58, %12
  %176 = fadd float %175, %14
  %177 = fmul float %58, %14
  %178 = fadd float %177, %12
  %179 = fsub float -0.000000e+00, %166
  %180 = fmul float %159, %16
  %181 = fadd float %180, %179
  %182 = fsub float -0.000000e+00, %145
  %183 = fmul float %84, %166
  %184 = fadd float %183, %138
  %185 = fmul float %86, %166
  %186 = fadd float %185, %182
  %187 = call float @llvm.AMDIL.clamp.(float %172, float 0.000000e+00, float 1.000000e+00)
  %188 = call float @llvm.AMDIL.clamp.(float %174, float 0.000000e+00, float 1.000000e+00)
  %189 = call float @llvm.AMDIL.clamp.(float %176, float 0.000000e+00, float 1.000000e+00)
  %190 = call float @llvm.AMDIL.clamp.(float %178, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %187, float %188, float %189, float %190)
  %191 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %192 = load float addrspace(2)* addrspace(2)* %191, !tbaa !0
  %193 = getelementptr float addrspace(2)* %192, i32 0
  %194 = load float addrspace(2)* %193, !tbaa !0
  %195 = fmul float %194, %138
  %196 = getelementptr float addrspace(2)* %192, i32 1
  %197 = load float addrspace(2)* %196, !tbaa !0
  %198 = fmul float %197, %145
  %199 = fadd float %195, %198
  %200 = getelementptr float addrspace(2)* %192, i32 2
  %201 = load float addrspace(2)* %200, !tbaa !0
  %202 = fmul float %201, %159
  %203 = fadd float %199, %202
  %204 = getelementptr float addrspace(2)* %192, i32 3
  %205 = load float addrspace(2)* %204, !tbaa !0
  %206 = fmul float %205, %166
  %207 = fadd float %203, %206
  %208 = getelementptr float addrspace(2)* %192, i32 4
  %209 = load float addrspace(2)* %208, !tbaa !0
  %210 = fmul float %209, %138
  %211 = getelementptr float addrspace(2)* %192, i32 5
  %212 = load float addrspace(2)* %211, !tbaa !0
  %213 = fmul float %212, %145
  %214 = fadd float %210, %213
  %215 = getelementptr float addrspace(2)* %192, i32 6
  %216 = load float addrspace(2)* %215, !tbaa !0
  %217 = fmul float %216, %159
  %218 = fadd float %214, %217
  %219 = getelementptr float addrspace(2)* %192, i32 7
  %220 = load float addrspace(2)* %219, !tbaa !0
  %221 = fmul float %220, %166
  %222 = fadd float %218, %221
  %223 = getelementptr float addrspace(2)* %192, i32 8
  %224 = load float addrspace(2)* %223, !tbaa !0
  %225 = fmul float %224, %138
  %226 = getelementptr float addrspace(2)* %192, i32 9
  %227 = load float addrspace(2)* %226, !tbaa !0
  %228 = fmul float %227, %145
  %229 = fadd float %225, %228
  %230 = getelementptr float addrspace(2)* %192, i32 10
  %231 = load float addrspace(2)* %230, !tbaa !0
  %232 = fmul float %231, %159
  %233 = fadd float %229, %232
  %234 = getelementptr float addrspace(2)* %192, i32 11
  %235 = load float addrspace(2)* %234, !tbaa !0
  %236 = fmul float %235, %166
  %237 = fadd float %233, %236
  %238 = getelementptr float addrspace(2)* %192, i32 12
  %239 = load float addrspace(2)* %238, !tbaa !0
  %240 = fmul float %239, %138
  %241 = getelementptr float addrspace(2)* %192, i32 13
  %242 = load float addrspace(2)* %241, !tbaa !0
  %243 = fmul float %242, %145
  %244 = fadd float %240, %243
  %245 = getelementptr float addrspace(2)* %192, i32 14
  %246 = load float addrspace(2)* %245, !tbaa !0
  %247 = fmul float %246, %159
  %248 = fadd float %244, %247
  %249 = getelementptr float addrspace(2)* %192, i32 15
  %250 = load float addrspace(2)* %249, !tbaa !0
  %251 = fmul float %250, %166
  %252 = fadd float %248, %251
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %207, float %222, float %237, float %252)
  %253 = getelementptr float addrspace(2)* %192, i32 16
  %254 = load float addrspace(2)* %253, !tbaa !0
  %255 = fmul float %254, %138
  %256 = getelementptr float addrspace(2)* %192, i32 17
  %257 = load float addrspace(2)* %256, !tbaa !0
  %258 = fmul float %257, %145
  %259 = fadd float %255, %258
  %260 = getelementptr float addrspace(2)* %192, i32 18
  %261 = load float addrspace(2)* %260, !tbaa !0
  %262 = fmul float %261, %159
  %263 = fadd float %259, %262
  %264 = getelementptr float addrspace(2)* %192, i32 19
  %265 = load float addrspace(2)* %264, !tbaa !0
  %266 = fmul float %265, %166
  %267 = fadd float %263, %266
  %268 = getelementptr float addrspace(2)* %192, i32 20
  %269 = load float addrspace(2)* %268, !tbaa !0
  %270 = fmul float %269, %138
  %271 = getelementptr float addrspace(2)* %192, i32 21
  %272 = load float addrspace(2)* %271, !tbaa !0
  %273 = fmul float %272, %145
  %274 = fadd float %270, %273
  %275 = getelementptr float addrspace(2)* %192, i32 22
  %276 = load float addrspace(2)* %275, !tbaa !0
  %277 = fmul float %276, %159
  %278 = fadd float %274, %277
  %279 = getelementptr float addrspace(2)* %192, i32 23
  %280 = load float addrspace(2)* %279, !tbaa !0
  %281 = fmul float %280, %166
  %282 = fadd float %278, %281
  %283 = getelementptr float addrspace(2)* %192, i32 24
  %284 = load float addrspace(2)* %283, !tbaa !0
  %285 = fmul float %284, %138
  %286 = getelementptr float addrspace(2)* %192, i32 25
  %287 = load float addrspace(2)* %286, !tbaa !0
  %288 = fmul float %287, %145
  %289 = fadd float %285, %288
  %290 = getelementptr float addrspace(2)* %192, i32 26
  %291 = load float addrspace(2)* %290, !tbaa !0
  %292 = fmul float %291, %159
  %293 = fadd float %289, %292
  %294 = getelementptr float addrspace(2)* %192, i32 27
  %295 = load float addrspace(2)* %294, !tbaa !0
  %296 = fmul float %295, %166
  %297 = fadd float %293, %296
  %298 = getelementptr float addrspace(2)* %192, i32 28
  %299 = load float addrspace(2)* %298, !tbaa !0
  %300 = fmul float %299, %138
  %301 = getelementptr float addrspace(2)* %192, i32 29
  %302 = load float addrspace(2)* %301, !tbaa !0
  %303 = fmul float %302, %145
  %304 = fadd float %300, %303
  %305 = getelementptr float addrspace(2)* %192, i32 30
  %306 = load float addrspace(2)* %305, !tbaa !0
  %307 = fmul float %306, %159
  %308 = fadd float %304, %307
  %309 = getelementptr float addrspace(2)* %192, i32 31
  %310 = load float addrspace(2)* %309, !tbaa !0
  %311 = fmul float %310, %166
  %312 = fadd float %308, %311
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %267, float %282, float %297, float %312)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %96, float %97, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %117, float %124, float %131, float %152)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %167, float %168, float %169, float %170)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %184, float %186, float %181, float %166)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 191; mem:LD4[%57]
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR8, %VGPR1, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%87](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR4, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR4, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 17; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 16; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR4, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 18; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6, %SGPR5, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 19; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 21; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 20; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 22; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 23; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%191](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%241]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%238]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 25; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 24; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 26; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 27; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%245]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 29; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 28; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 30; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 31; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%249]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%226]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%223]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%230]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%234]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%211]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%208]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%215]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%219]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%196]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%193]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%200]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%204]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%301]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%298]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%305]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%309]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%286]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%283]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%290]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%294]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%271]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%268]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%275]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%279]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%256]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%253]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%260]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%264]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%93](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13<kill>, %VGPR13, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 49; mem:LD4[%51]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 48; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 50; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 51; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 201; mem:LD4[%77]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 200; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 202; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 203; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 198; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 199; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 194; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 195; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR2<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 8; mem:LD16[%98](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4, %VGPR10, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	EXP 15, 35, 0, 0, 0, %VGPR4<kill>, %VGPR2<kill>, %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 204; mem:LD4[%83]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 205; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0410100
bf8c007f
c00403bf
c0028300
bf8c007f
7e060205
c0020301
bf8c007f
7e020204
d2820002
040e0208
d2060802
02010102
d2820004
04060608
d2060804
02010104
f800020f
02040404
c0840700
bf8c000f
e00c2000
80020600
bf8c0770
d2820002
040c0906
d2820004
040c0907
c0040311
bf8c007f
100a0808
c0040310
bf8c007f
d282000a
04141102
d2820005
040c0908
c0040312
bf8c007f
d2820003
04281105
d2820006
04040b06
c0040313
bf8c007f
d2820001
040c1106
c0040315
bf8c007f
10060808
c0040314
bf8c007f
d2820003
040c1102
c0040316
bf8c007f
d2820003
040c1105
c0040317
bf8c007f
d2820003
040c1106
c0400102
bf8c007f
c004010d
bf8c007f
100e0608
c004010c
bf8c007f
d2820008
041e0208
c0040319
bf8c007f
100e0808
c0040318
bf8c007f
d2820007
041c1102
c004031a
bf8c007f
d2820007
041c1105
c004031b
bf8c007f
d2820007
041c1106
c004010e
bf8c007f
d2820009
04220e08
c004031d
bf8c007f
10100808
c004031c
bf8c007f
d2820008
04201102
c004031e
bf8c007f
d2820008
04201105
c004031f
bf8c007f
d2820008
04201106
c004010f
bf8c007f
d2820009
04261008
c0040109
bf8c007f
10140608
c0040108
bf8c007f
d282000a
042a0208
c004010a
bf8c007f
d282000a
042a0e08
c004010b
bf8c007f
d282000a
042a1008
c0040105
bf8c007f
10160608
c0040104
bf8c007f
d282000b
042e0208
c0040106
bf8c007f
d282000b
042e0e08
c0040107
bf8c007f
d282000b
042e1008
c0040101
bf8c007f
10180608
c0040100
bf8c007f
d282000c
04320208
c0040102
bf8c007f
d282000c
04320e08
c0040103
bf8c007f
d282000c
04321008
f80000ef
090a0b0c
c004011d
bf8c000f
10120608
c004011c
bf8c007f
d2820009
04260208
c004011e
bf8c007f
d2820009
04260e08
c004011f
bf8c007f
d2820009
04261008
c0040119
bf8c007f
10140608
c0040118
bf8c007f
d282000a
042a0208
c004011a
bf8c007f
d282000a
042a0e08
c004011b
bf8c007f
d282000a
042a1008
c0040115
bf8c007f
10160608
c0040114
bf8c007f
d282000b
042e0208
c0040116
bf8c007f
d282000b
042e0e08
c0040117
bf8c007f
d282000b
042e1008
c0040111
bf8c007f
10180608
c0040110
bf8c007f
d282000c
04320208
c0040112
bf8c007f
d282000c
04320e08
c0000113
bf8c007f
d282000c
04321000
f80000ff
090a0b0c
c0840704
bf8c000f
e00c2000
80020900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c0000331
bf8c000f
10120800
c0000330
bf8c007f
d2820009
04240102
c0000332
bf8c007f
d2820009
04240105
c0000333
bf8c007f
d2820009
04240106
c00003c9
bf8c007f
10140800
c00003c8
bf8c007f
d282000a
04280102
c00003ca
bf8c007f
d282000a
04280105
c00003cb
bf8c007f
d282000a
04280106
c00003c5
bf8c007f
10160800
c00003c4
bf8c007f
d282000b
042c0102
c00003c6
bf8c007f
d282000b
042c0105
c00003c7
bf8c007f
d282000b
042c0106
c00003c1
bf8c007f
10080800
c00003c0
bf8c007f
d2820002
04100102
c00003c2
bf8c007f
d2820002
04080105
c00003c3
bf8c007f
d2820002
04080106
f800022f
090a0b02
c0840708
bf8c000f
e00c2000
80020900
bf8c0770
10001205
10041404
10081204
f800023f
00000204
c00003cc
bf8c000f
d2820000
04061000
c0000302
bf8c007f
10020e00
08021101
c00003cd
bf8c007f
10041000
08040702
f80008cf
08010200
bf810000
FRAG
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL CONST[0..29]
DCL TEMP[0], LOCAL
DCL TEMP[1], ARRAY(1), LOCAL
IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
  0: MUL TEMP[0].x, IN[0].xxxx, CONST[29].wwww
  1: MOV TEMP[0].w, TEMP[0].xxxx
  2: MOV TEMP[0].xyz, IMM[0].xxxx
  3: MOV TEMP[1], TEMP[0]
  4: MOV OUT[0], TEMP[1]
  5: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 119
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = fmul float %24, %23
  %26 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
  %27 = bitcast i32 %26 to float
  %28 = call i32 @llvm.SI.packf16(float 0.000000e+00, float %25)
  %29 = bitcast i32 %28 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 119; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 0.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8080000
c8090001
c0400100
bf8c007f
c0000177
bf8c007f
10000400
5e000080
d25e0001
02010080
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL CONST[0..8]
DCL TEMP[0..5], LOCAL
  0: DP4 TEMP[0].x, IN[0], CONST[4]
  1: DP4 TEMP[1].x, IN[0], CONST[5]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: DP4 TEMP[2].x, IN[0], CONST[7]
  4: MOV TEMP[3].w, TEMP[2].xxxx
  5: DP4 TEMP[4].x, IN[0], CONST[6]
  6: MOV TEMP[3].z, TEMP[4].xxxx
  7: MOV TEMP[0].zw, TEMP[3].wwzw
  8: MOV TEMP[3].x, TEMP[4].xxxx
  9: MOV TEMP[5], TEMP[0]
 10: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[2].xxxx
 11: MOV TEMP[0].z, TEMP[4].xxxx
 12: MOV TEMP[0].y, -TEMP[1].xxxx
 13: MAD TEMP[0].xy, CONST[8].xyyy, TEMP[2].xxxx, TEMP[0].xyyy
 14: MOV OUT[2], TEMP[3]
 15: MOV OUT[0], TEMP[0]
 16: MOV OUT[1], TEMP[5]
 17: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 2
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 16
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 17
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 18
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 19
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 20
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 21
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 22
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 23
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 24
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 25
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 26
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 27
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 28
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 29
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 30
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 31
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 32
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 33
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0
  %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %5)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = extractelement <4 x float> %51, i32 1
  %54 = extractelement <4 x float> %51, i32 2
  %55 = extractelement <4 x float> %51, i32 3
  %56 = fmul float %52, %14
  %57 = fmul float %53, %16
  %58 = fadd float %56, %57
  %59 = fmul float %54, %18
  %60 = fadd float %58, %59
  %61 = fmul float %55, %20
  %62 = fadd float %60, %61
  %63 = fmul float %52, %22
  %64 = fmul float %53, %24
  %65 = fadd float %63, %64
  %66 = fmul float %54, %26
  %67 = fadd float %65, %66
  %68 = fmul float %55, %28
  %69 = fadd float %67, %68
  %70 = fmul float %52, %38
  %71 = fmul float %53, %40
  %72 = fadd float %70, %71
  %73 = fmul float %54, %42
  %74 = fadd float %72, %73
  %75 = fmul float %55, %44
  %76 = fadd float %74, %75
  %77 = fmul float %52, %30
  %78 = fmul float %53, %32
  %79 = fadd float %77, %78
  %80 = fmul float %54, %34
  %81 = fadd float %79, %80
  %82 = fmul float %55, %36
  %83 = fadd float %81, %82
  %84 = fsub float -0.000000e+00, %76
  %85 = fmul float %83, %12
  %86 = fadd float %85, %84
  %87 = fsub float -0.000000e+00, %69
  %88 = fmul float %46, %76
  %89 = fadd float %88, %62
  %90 = fmul float %48, %76
  %91 = fadd float %90, %87
  %92 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %93 = load float addrspace(2)* addrspace(2)* %92, !tbaa !0
  %94 = getelementptr float addrspace(2)* %93, i32 0
  %95 = load float addrspace(2)* %94, !tbaa !0
  %96 = fmul float %95, %62
  %97 = getelementptr float addrspace(2)* %93, i32 1
  %98 = load float addrspace(2)* %97, !tbaa !0
  %99 = fmul float %98, %69
  %100 = fadd float %96, %99
  %101 = getelementptr float addrspace(2)* %93, i32 2
  %102 = load float addrspace(2)* %101, !tbaa !0
  %103 = fmul float %102, %83
  %104 = fadd float %100, %103
  %105 = getelementptr float addrspace(2)* %93, i32 3
  %106 = load float addrspace(2)* %105, !tbaa !0
  %107 = fmul float %106, %76
  %108 = fadd float %104, %107
  %109 = getelementptr float addrspace(2)* %93, i32 4
  %110 = load float addrspace(2)* %109, !tbaa !0
  %111 = fmul float %110, %62
  %112 = getelementptr float addrspace(2)* %93, i32 5
  %113 = load float addrspace(2)* %112, !tbaa !0
  %114 = fmul float %113, %69
  %115 = fadd float %111, %114
  %116 = getelementptr float addrspace(2)* %93, i32 6
  %117 = load float addrspace(2)* %116, !tbaa !0
  %118 = fmul float %117, %83
  %119 = fadd float %115, %118
  %120 = getelementptr float addrspace(2)* %93, i32 7
  %121 = load float addrspace(2)* %120, !tbaa !0
  %122 = fmul float %121, %76
  %123 = fadd float %119, %122
  %124 = getelementptr float addrspace(2)* %93, i32 8
  %125 = load float addrspace(2)* %124, !tbaa !0
  %126 = fmul float %125, %62
  %127 = getelementptr float addrspace(2)* %93, i32 9
  %128 = load float addrspace(2)* %127, !tbaa !0
  %129 = fmul float %128, %69
  %130 = fadd float %126, %129
  %131 = getelementptr float addrspace(2)* %93, i32 10
  %132 = load float addrspace(2)* %131, !tbaa !0
  %133 = fmul float %132, %83
  %134 = fadd float %130, %133
  %135 = getelementptr float addrspace(2)* %93, i32 11
  %136 = load float addrspace(2)* %135, !tbaa !0
  %137 = fmul float %136, %76
  %138 = fadd float %134, %137
  %139 = getelementptr float addrspace(2)* %93, i32 12
  %140 = load float addrspace(2)* %139, !tbaa !0
  %141 = fmul float %140, %62
  %142 = getelementptr float addrspace(2)* %93, i32 13
  %143 = load float addrspace(2)* %142, !tbaa !0
  %144 = fmul float %143, %69
  %145 = fadd float %141, %144
  %146 = getelementptr float addrspace(2)* %93, i32 14
  %147 = load float addrspace(2)* %146, !tbaa !0
  %148 = fmul float %147, %83
  %149 = fadd float %145, %148
  %150 = getelementptr float addrspace(2)* %93, i32 15
  %151 = load float addrspace(2)* %150, !tbaa !0
  %152 = fmul float %151, %76
  %153 = fadd float %149, %152
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %108, float %123, float %138, float %153)
  %154 = getelementptr float addrspace(2)* %93, i32 16
  %155 = load float addrspace(2)* %154, !tbaa !0
  %156 = fmul float %155, %62
  %157 = getelementptr float addrspace(2)* %93, i32 17
  %158 = load float addrspace(2)* %157, !tbaa !0
  %159 = fmul float %158, %69
  %160 = fadd float %156, %159
  %161 = getelementptr float addrspace(2)* %93, i32 18
  %162 = load float addrspace(2)* %161, !tbaa !0
  %163 = fmul float %162, %83
  %164 = fadd float %160, %163
  %165 = getelementptr float addrspace(2)* %93, i32 19
  %166 = load float addrspace(2)* %165, !tbaa !0
  %167 = fmul float %166, %76
  %168 = fadd float %164, %167
  %169 = getelementptr float addrspace(2)* %93, i32 20
  %170 = load float addrspace(2)* %169, !tbaa !0
  %171 = fmul float %170, %62
  %172 = getelementptr float addrspace(2)* %93, i32 21
  %173 = load float addrspace(2)* %172, !tbaa !0
  %174 = fmul float %173, %69
  %175 = fadd float %171, %174
  %176 = getelementptr float addrspace(2)* %93, i32 22
  %177 = load float addrspace(2)* %176, !tbaa !0
  %178 = fmul float %177, %83
  %179 = fadd float %175, %178
  %180 = getelementptr float addrspace(2)* %93, i32 23
  %181 = load float addrspace(2)* %180, !tbaa !0
  %182 = fmul float %181, %76
  %183 = fadd float %179, %182
  %184 = getelementptr float addrspace(2)* %93, i32 24
  %185 = load float addrspace(2)* %184, !tbaa !0
  %186 = fmul float %185, %62
  %187 = getelementptr float addrspace(2)* %93, i32 25
  %188 = load float addrspace(2)* %187, !tbaa !0
  %189 = fmul float %188, %69
  %190 = fadd float %186, %189
  %191 = getelementptr float addrspace(2)* %93, i32 26
  %192 = load float addrspace(2)* %191, !tbaa !0
  %193 = fmul float %192, %83
  %194 = fadd float %190, %193
  %195 = getelementptr float addrspace(2)* %93, i32 27
  %196 = load float addrspace(2)* %195, !tbaa !0
  %197 = fmul float %196, %76
  %198 = fadd float %194, %197
  %199 = getelementptr float addrspace(2)* %93, i32 28
  %200 = load float addrspace(2)* %199, !tbaa !0
  %201 = fmul float %200, %62
  %202 = getelementptr float addrspace(2)* %93, i32 29
  %203 = load float addrspace(2)* %202, !tbaa !0
  %204 = fmul float %203, %69
  %205 = fadd float %201, %204
  %206 = getelementptr float addrspace(2)* %93, i32 30
  %207 = load float addrspace(2)* %206, !tbaa !0
  %208 = fmul float %207, %83
  %209 = fadd float %205, %208
  %210 = getelementptr float addrspace(2)* %93, i32 31
  %211 = load float addrspace(2)* %210, !tbaa !0
  %212 = fmul float %211, %76
  %213 = fadd float %209, %212
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %168, float %183, float %198, float %213)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %83, float 0.000000e+00, float %83, float %76)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %89, float %91, float %86, float %76)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%49](tbaa=!"const")
	S_WAITCNT 127
	%VGPR3_VGPR4_VGPR5_VGPR6<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 17; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 16; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 18; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 19; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 21; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 20; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 22; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 23; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%92](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%142]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%139]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 25; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 24; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 26; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 27; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%146]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 29; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 28; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 30; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 31; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-use,kill>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%150]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%127]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%124]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%131]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%135]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%112]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%109]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%116]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%120]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%97]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%94]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%101]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%105]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%202]
	S_WAITCNT 15
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%199]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%206]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%210]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%187]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%184]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%191]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%195]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%172]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%169]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%176]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%180]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%157]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%154]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%161]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR4<kill>, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%165]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR2, %VGPR4<kill>, %VGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 32; mem:LD4[%45]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR3, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 33; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR4<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR1<kill>, %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0820700
bf8c007f
e00c2000
80010300
c0410100
bf8c0070
c0020311
bf8c007f
10000804
c0020310
bf8c007f
d2820000
04000903
c0020312
bf8c007f
d2820000
04000905
c0020313
bf8c007f
d2820000
04000906
c0020315
bf8c007f
10020804
c0020314
bf8c007f
d2820001
04040903
c0020316
bf8c007f
d2820001
04040905
c0020317
bf8c007f
d2820001
04040906
c0400102
bf8c007f
c002010d
bf8c007f
10040204
c002010c
bf8c007f
d2820007
040a0004
c0020319
bf8c007f
10040804
c0020318
bf8c007f
d2820002
04080903
c002031a
bf8c007f
d2820002
04080905
c002031b
bf8c007f
d2820002
04080906
c002010e
bf8c007f
d2820007
041e0404
c002031d
bf8c007f
10100804
c002031c
bf8c007f
d2820008
04200903
c002031e
bf8c007f
d2820008
04200905
c002031f
bf8c007f
d2820003
04200906
c002010f
bf8c007f
d2820004
041e0604
c0020109
bf8c007f
100a0204
c0020108
bf8c007f
d2820005
04160004
c002010a
bf8c007f
d2820005
04160404
c002010b
bf8c007f
d2820005
04160604
c0020105
bf8c007f
100c0204
c0020104
bf8c007f
d2820006
041a0004
c0020106
bf8c007f
d2820006
041a0404
c0020107
bf8c007f
d2820006
041a0604
c0020101
bf8c007f
100e0204
c0020100
bf8c007f
d2820007
041e0004
c0020102
bf8c007f
d2820007
041e0404
c0020103
bf8c007f
d2820007
041e0604
f80000ef
04050607
c002011d
bf8c000f
10080204
c002011c
bf8c007f
d2820004
04120004
c002011e
bf8c007f
d2820004
04120404
c002011f
bf8c007f
d2820004
04120604
c0020119
bf8c007f
100a0204
c0020118
bf8c007f
d2820005
04160004
c002011a
bf8c007f
d2820005
04160404
c002011b
bf8c007f
d2820005
04160604
c0020115
bf8c007f
100c0204
c0020114
bf8c007f
d2820006
041a0004
c0020116
bf8c007f
d2820006
041a0404
c0020117
bf8c007f
d2820006
041a0604
c0020111
bf8c007f
100e0204
c0020110
bf8c007f
d2820007
041e0004
c0020112
bf8c007f
d2820007
041e0404
c0000113
bf8c007f
d2820007
041e0600
f80000ff
04050607
bf8c070f
7e080280
f800020f
03020402
c0000320
bf8c000f
d2820000
04020600
c0000302
bf8c007f
10040400
08040702
c0000321
bf8c007f
10080600
08020304
f80008cf
03020100
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE
DCL IN[4], GENERIC[22], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..30]
DCL TEMP[0..2], LOCAL
DCL TEMP[3], ARRAY(1), LOCAL
IMM[0] FLT32 {    2.0000,    -1.0000,     1.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[2].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[2], 2D
  2: MOV TEMP[1].xy, IN[1].xyyy
  3: TEX TEMP[1].xyz, TEMP[1], SAMP[0], 2D
  4: MOV TEMP[2].xy, IN[4].xyyy
  5: TEX TEMP[2].xyz, TEMP[2], SAMP[1], 2D
  6: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[8].xyzz
  7: MAD TEMP[0].xyz, IMM[0].xxxx, TEMP[0].xyzz, IMM[0].yyyy
  8: MAD TEMP[0].xyz, CONST[8].wwww, TEMP[0].xyzz, IMM[0].zzzz
  9: MUL TEMP[0].xyz, TEMP[1].xyzz, TEMP[0].xyzz
 10: MUL TEMP[0].xyz, TEMP[0].xyzz, IN[0].xyzz
 11: MUL TEMP[1].xyz, TEMP[2].xyzz, CONST[12].xyzz
 12: MAD TEMP[2].x, IN[3].wwww, CONST[11].wwww, -CONST[11].xxxx
 13: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[1].xyzz
 14: MIN TEMP[2].x, TEMP[2].xxxx, CONST[11].zzzz
 15: MOV_SAT TEMP[2].x, TEMP[2].xxxx
 16: MAD TEMP[0].xyz, TEMP[1].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 17: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
 18: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
 19: MAD TEMP[1].xyz, TEMP[1].xyzz, CONST[30].xxxx, TEMP[0].xyzz
 20: MUL TEMP[0].x, IN[3].wwww, CONST[29].wwww
 21: MOV TEMP[1].w, TEMP[0].xxxx
 22: MOV TEMP[3], TEMP[1]
 23: MOV OUT[0], TEMP[3]
 24: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 32
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 33
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 34
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 35
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 44
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 46
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 47
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 48
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 49
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 50
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 116
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr float addrspace(2)* %21, i32 117
  %45 = load float addrspace(2)* %44, !tbaa !0
  %46 = getelementptr float addrspace(2)* %21, i32 118
  %47 = load float addrspace(2)* %46, !tbaa !0
  %48 = getelementptr float addrspace(2)* %21, i32 119
  %49 = load float addrspace(2)* %48, !tbaa !0
  %50 = getelementptr float addrspace(2)* %21, i32 120
  %51 = load float addrspace(2)* %50, !tbaa !0
  %52 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %53 = load <32 x i8> addrspace(2)* %52, !tbaa !0
  %54 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
  %56 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %57 = load <32 x i8> addrspace(2)* %56, !tbaa !0
  %58 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %59 = load <16 x i8> addrspace(2)* %58, !tbaa !0
  %60 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %61 = load <32 x i8> addrspace(2)* %60, !tbaa !0
  %62 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %63 = load <16 x i8> addrspace(2)* %62, !tbaa !0
  %64 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %65 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %66 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %67 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %68 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %69 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %70 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %71 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
  %72 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %6)
  %73 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %6)
  %74 = bitcast float %69 to i32
  %75 = bitcast float %70 to i32
  %76 = insertelement <2 x i32> undef, i32 %74, i32 0
  %77 = insertelement <2 x i32> %76, i32 %75, i32 1
  %78 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %77, <32 x i8> %61, <16 x i8> %63, i32 2)
  %79 = extractelement <4 x float> %78, i32 0
  %80 = extractelement <4 x float> %78, i32 1
  %81 = extractelement <4 x float> %78, i32 2
  %82 = bitcast float %67 to i32
  %83 = bitcast float %68 to i32
  %84 = insertelement <2 x i32> undef, i32 %82, i32 0
  %85 = insertelement <2 x i32> %84, i32 %83, i32 1
  %86 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %85, <32 x i8> %53, <16 x i8> %55, i32 2)
  %87 = extractelement <4 x float> %86, i32 0
  %88 = extractelement <4 x float> %86, i32 1
  %89 = extractelement <4 x float> %86, i32 2
  %90 = bitcast float %72 to i32
  %91 = bitcast float %73 to i32
  %92 = insertelement <2 x i32> undef, i32 %90, i32 0
  %93 = insertelement <2 x i32> %92, i32 %91, i32 1
  %94 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %93, <32 x i8> %57, <16 x i8> %59, i32 2)
  %95 = extractelement <4 x float> %94, i32 0
  %96 = extractelement <4 x float> %94, i32 1
  %97 = extractelement <4 x float> %94, i32 2
  %98 = fmul float %79, %23
  %99 = fmul float %80, %25
  %100 = fmul float %81, %27
  %101 = fmul float 2.000000e+00, %98
  %102 = fadd float %101, -1.000000e+00
  %103 = fmul float 2.000000e+00, %99
  %104 = fadd float %103, -1.000000e+00
  %105 = fmul float 2.000000e+00, %100
  %106 = fadd float %105, -1.000000e+00
  %107 = fmul float %29, %102
  %108 = fadd float %107, 1.000000e+00
  %109 = fmul float %29, %104
  %110 = fadd float %109, 1.000000e+00
  %111 = fmul float %29, %106
  %112 = fadd float %111, 1.000000e+00
  %113 = fmul float %87, %108
  %114 = fmul float %88, %110
  %115 = fmul float %89, %112
  %116 = fmul float %113, %64
  %117 = fmul float %114, %65
  %118 = fmul float %115, %66
  %119 = fmul float %95, %37
  %120 = fmul float %96, %39
  %121 = fmul float %97, %41
  %122 = fsub float -0.000000e+00, %31
  %123 = fmul float %71, %35
  %124 = fadd float %123, %122
  %125 = fmul float %116, %119
  %126 = fmul float %117, %120
  %127 = fmul float %118, %121
  %128 = fcmp uge float %124, %33
  %129 = select i1 %128, float %33, float %124
  %130 = call float @llvm.AMDIL.clamp.(float %129, float 0.000000e+00, float 1.000000e+00)
  %131 = fsub float -0.000000e+00, %51
  %132 = fmul float %125, %131
  %133 = fadd float %132, %43
  %134 = fsub float -0.000000e+00, %51
  %135 = fmul float %126, %134
  %136 = fadd float %135, %45
  %137 = fsub float -0.000000e+00, %51
  %138 = fmul float %127, %137
  %139 = fadd float %138, %47
  %140 = fmul float %130, %130
  %141 = fmul float %133, %140
  %142 = fmul float %136, %140
  %143 = fmul float %139, %140
  %144 = fmul float %125, %51
  %145 = fadd float %144, %141
  %146 = fmul float %126, %51
  %147 = fadd float %146, %142
  %148 = fmul float %127, %51
  %149 = fadd float %148, %143
  %150 = fmul float %71, %49
  %151 = call i32 @llvm.SI.packf16(float %145, float %147)
  %152 = bitcast i32 %151 to float
  %153 = call i32 @llvm.SI.packf16(float %149, float %150)
  %154 = bitcast i32 %153 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %152, float %154, float %152, float %154)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%62](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%60](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 33; mem:LD4[%24]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR7, %VGPR5, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR7<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR7<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 35; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR7, %VGPR7<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%54](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%52](tbaa=!"const")
	S_WAITCNT 127
	%VGPR7_VGPR8_VGPR9<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR10<def> = V_MUL_F32_e32 %VGPR8, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR2, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<tied0>, %VGPR3, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR2, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<tied0>, %VGPR3, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%58](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%56](tbaa=!"const")
	S_WAITCNT 127
	%VGPR10_VGPR11_VGPR12<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR10_VGPR11<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 49; mem:LD4[%38]
	S_WAITCNT 112
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%50]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR13, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%44]
	S_WAITCNT 127
	%VGPR14<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 3, %M0<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 47; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 44; mem:LD4[%30]
	S_WAITCNT 127
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR3<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 46; mem:LD4[%32]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR15<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR13<kill>, %SGPR2, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 32; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR3, %VGPR4, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR4, %SGPR3<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %SGPR7, %VGPR14<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR7, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%36]
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR10, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %SGPR2, %VGPR14, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 116; mem:LD4[%42]
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR14<kill>, %SGPR2, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR14<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 34; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR3, %VGPR6, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6, %SGPR3<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR7<kill>, %VGPR4<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR9, %VGPR4<kill>, %EXEC<imp-use>, %VGPR7_VGPR8_VGPR9<imp-use,kill>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR12, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2, %VGPR0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 118; mem:LD4[%46]
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 119; mem:LD4[%48]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR13<kill>, %VGPR0<kill>, %VGPR13, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140900
c8150901
c8100800
c8110801
c0840308
c0c60510
bf8c007f
f0800700
00430404
c0400100
bf8c0070
c0038121
bf8c007f
100e0a07
d2820007
041c0f05
060e0ef3
c0038123
bf8c007f
d282000a
03ca0e07
c8200500
c8210501
c81c0400
c81d0401
c0840300
c0c60500
bf8c007f
f0800700
00430707
bf8c0770
10141508
c82c0100
c82d0101
101a170a
c82c1102
c82d1103
c8281002
c8291003
c0840304
c0c60508
bf8c007f
f0800700
00430a0a
c0010131
bf8c0070
10041602
101a050d
c0010178
bf8c007f
10041a02
c0018175
bf8c007f
081c0403
c8080f00
c8090f01
c001812f
bf8c007f
10060403
c001812c
bf8c007f
0a060603
c001812e
bf8c007f
d00c0004
02000703
7e1e0203
d2000003
00121f03
d2060803
02010103
10060703
101c070e
d282000d
0438050d
c0018120
bf8c007f
101c0803
d282000e
04380704
061c1cf3
d282000e
03ca1c07
101c1d07
c83c0000
c83d0001
101c1f0e
c0018130
bf8c007f
101e1403
101c1f0e
101e1c02
c0018174
bf8c007f
081e1e03
101e070f
d282000e
043c050e
5e1a1b0e
c0018122
bf8c007f
101c0c03
d2820004
04380706
060808f3
d2820004
03ca0807
10080909
c8140200
c8150201
10000b04
c0018132
bf8c007f
10021803
10000300
10020002
c0018176
bf8c007f
08020203
10020701
d2820000
04040500
c0000177
bf8c007f
10020400
5e000300
f8001c0f
000d000d
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL CONST[0..55]
DCL TEMP[0..9], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[52]
  2: DP4 TEMP[2].x, TEMP[0], CONST[53]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[54]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[6]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: DP4 TEMP[5].x, TEMP[0], CONST[7]
 12: MOV TEMP[2].w, TEMP[5].xxxx
 13: DP4 TEMP[6].x, TEMP[0], CONST[12]
 14: MUL TEMP[0].xy, IN[1].xyyy, CONST[48].xyyy
 15: ADD TEMP[7].x, TEMP[0].yyyy, TEMP[0].xxxx
 16: MUL TEMP[0].xy, IN[1].xyyy, CONST[49].xyyy
 17: ADD TEMP[7].x, TEMP[7].xxxx, CONST[48].wwww
 18: ADD TEMP[8].x, TEMP[0].yyyy, TEMP[0].xxxx
 19: ADD TEMP[8].x, TEMP[8].xxxx, CONST[49].wwww
 20: MOV TEMP[7].y, TEMP[8].xxxx
 21: MUL TEMP[0].xy, IN[1].xyyy, CONST[50].xyyy
 22: ADD TEMP[8].x, TEMP[0].yyyy, TEMP[0].xxxx
 23: MUL TEMP[0].xy, IN[1].xyyy, CONST[51].xyyy
 24: ADD TEMP[8].x, TEMP[8].xxxx, CONST[50].wwww
 25: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx
 26: ADD TEMP[0].x, TEMP[0].xxxx, CONST[51].wwww
 27: MOV TEMP[8].y, TEMP[0].xxxx
 28: MOV TEMP[1].w, TEMP[6].xxxx
 29: MOV TEMP[8].zw, CONST[0].xxxx
 30: MUL TEMP[0], IN[2].xyxx, CONST[0].yyxx
 31: MAD TEMP[6], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 32: MOV TEMP[9], TEMP[2]
 33: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[5].xxxx
 34: MOV TEMP[2].z, TEMP[4].xxxx
 35: MOV TEMP[2].y, -TEMP[3].xxxx
 36: MAD TEMP[2].xy, CONST[55].xyyy, TEMP[5].xxxx, TEMP[2].xyyy
 37: MOV OUT[3], TEMP[7]
 38: MOV OUT[4], TEMP[8]
 39: MOV OUT[6], TEMP[0]
 40: MOV OUT[0], TEMP[2]
 41: MOV OUT[5], TEMP[1]
 42: MOV OUT[2], TEMP[9]
 43: MOV_SAT OUT[1], TEMP[6]
 44: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 16
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 17
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 18
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 19
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 20
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 21
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 22
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 23
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 24
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 25
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 26
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 27
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 28
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 29
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 30
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 31
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 48
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 49
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 50
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 51
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 191
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 192
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 193
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 195
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 196
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 197
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 199
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 200
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 201
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 203
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 204
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 205
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 207
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 208
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 209
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr float addrspace(2)* %10, i32 210
  %88 = load float addrspace(2)* %87, !tbaa !0
  %89 = getelementptr float addrspace(2)* %10, i32 211
  %90 = load float addrspace(2)* %89, !tbaa !0
  %91 = getelementptr float addrspace(2)* %10, i32 212
  %92 = load float addrspace(2)* %91, !tbaa !0
  %93 = getelementptr float addrspace(2)* %10, i32 213
  %94 = load float addrspace(2)* %93, !tbaa !0
  %95 = getelementptr float addrspace(2)* %10, i32 214
  %96 = load float addrspace(2)* %95, !tbaa !0
  %97 = getelementptr float addrspace(2)* %10, i32 215
  %98 = load float addrspace(2)* %97, !tbaa !0
  %99 = getelementptr float addrspace(2)* %10, i32 216
  %100 = load float addrspace(2)* %99, !tbaa !0
  %101 = getelementptr float addrspace(2)* %10, i32 217
  %102 = load float addrspace(2)* %101, !tbaa !0
  %103 = getelementptr float addrspace(2)* %10, i32 218
  %104 = load float addrspace(2)* %103, !tbaa !0
  %105 = getelementptr float addrspace(2)* %10, i32 219
  %106 = load float addrspace(2)* %105, !tbaa !0
  %107 = getelementptr float addrspace(2)* %10, i32 220
  %108 = load float addrspace(2)* %107, !tbaa !0
  %109 = getelementptr float addrspace(2)* %10, i32 221
  %110 = load float addrspace(2)* %109, !tbaa !0
  %111 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %112 = load <16 x i8> addrspace(2)* %111, !tbaa !0
  %113 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %112, i32 0, i32 %5)
  %114 = extractelement <4 x float> %113, i32 0
  %115 = extractelement <4 x float> %113, i32 1
  %116 = extractelement <4 x float> %113, i32 2
  %117 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %118 = load <16 x i8> addrspace(2)* %117, !tbaa !0
  %119 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %118, i32 0, i32 %5)
  %120 = extractelement <4 x float> %119, i32 0
  %121 = extractelement <4 x float> %119, i32 1
  %122 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
  %124 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %123, i32 0, i32 %5)
  %125 = extractelement <4 x float> %124, i32 0
  %126 = extractelement <4 x float> %124, i32 1
  %127 = fmul float %114, %14
  %128 = fadd float %127, %12
  %129 = fmul float %115, %14
  %130 = fadd float %129, %12
  %131 = fmul float %116, %14
  %132 = fadd float %131, %12
  %133 = fmul float %114, %12
  %134 = fadd float %133, %14
  %135 = fmul float %128, %84
  %136 = fmul float %130, %86
  %137 = fadd float %135, %136
  %138 = fmul float %132, %88
  %139 = fadd float %137, %138
  %140 = fmul float %134, %90
  %141 = fadd float %139, %140
  %142 = fmul float %128, %92
  %143 = fmul float %130, %94
  %144 = fadd float %142, %143
  %145 = fmul float %132, %96
  %146 = fadd float %144, %145
  %147 = fmul float %134, %98
  %148 = fadd float %146, %147
  %149 = fmul float %128, %100
  %150 = fmul float %130, %102
  %151 = fadd float %149, %150
  %152 = fmul float %132, %104
  %153 = fadd float %151, %152
  %154 = fmul float %134, %106
  %155 = fadd float %153, %154
  %156 = fmul float %128, %18
  %157 = fmul float %130, %20
  %158 = fadd float %156, %157
  %159 = fmul float %132, %22
  %160 = fadd float %158, %159
  %161 = fmul float %134, %24
  %162 = fadd float %160, %161
  %163 = fmul float %128, %26
  %164 = fmul float %130, %28
  %165 = fadd float %163, %164
  %166 = fmul float %132, %30
  %167 = fadd float %165, %166
  %168 = fmul float %134, %32
  %169 = fadd float %167, %168
  %170 = fmul float %128, %34
  %171 = fmul float %130, %36
  %172 = fadd float %170, %171
  %173 = fmul float %132, %38
  %174 = fadd float %172, %173
  %175 = fmul float %134, %40
  %176 = fadd float %174, %175
  %177 = fmul float %128, %42
  %178 = fmul float %130, %44
  %179 = fadd float %177, %178
  %180 = fmul float %132, %46
  %181 = fadd float %179, %180
  %182 = fmul float %134, %48
  %183 = fadd float %181, %182
  %184 = fmul float %128, %50
  %185 = fmul float %130, %52
  %186 = fadd float %184, %185
  %187 = fmul float %132, %54
  %188 = fadd float %186, %187
  %189 = fmul float %134, %56
  %190 = fadd float %188, %189
  %191 = fmul float %120, %60
  %192 = fmul float %121, %62
  %193 = fadd float %192, %191
  %194 = fmul float %120, %66
  %195 = fmul float %121, %68
  %196 = fadd float %193, %64
  %197 = fadd float %195, %194
  %198 = fadd float %197, %70
  %199 = fmul float %120, %72
  %200 = fmul float %121, %74
  %201 = fadd float %200, %199
  %202 = fmul float %120, %78
  %203 = fmul float %121, %80
  %204 = fadd float %201, %76
  %205 = fadd float %203, %202
  %206 = fadd float %205, %82
  %207 = fmul float %125, %14
  %208 = fmul float %126, %14
  %209 = fmul float %125, %12
  %210 = fmul float %125, %12
  %211 = fmul float %58, %12
  %212 = fadd float %211, %14
  %213 = fmul float %58, %12
  %214 = fadd float %213, %14
  %215 = fmul float %58, %12
  %216 = fadd float %215, %14
  %217 = fmul float %58, %14
  %218 = fadd float %217, %12
  %219 = fsub float -0.000000e+00, %183
  %220 = fmul float %176, %16
  %221 = fadd float %220, %219
  %222 = fsub float -0.000000e+00, %169
  %223 = fmul float %108, %183
  %224 = fadd float %223, %162
  %225 = fmul float %110, %183
  %226 = fadd float %225, %222
  %227 = call float @llvm.AMDIL.clamp.(float %212, float 0.000000e+00, float 1.000000e+00)
  %228 = call float @llvm.AMDIL.clamp.(float %214, float 0.000000e+00, float 1.000000e+00)
  %229 = call float @llvm.AMDIL.clamp.(float %216, float 0.000000e+00, float 1.000000e+00)
  %230 = call float @llvm.AMDIL.clamp.(float %218, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %227, float %228, float %229, float %230)
  %231 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %232 = load float addrspace(2)* addrspace(2)* %231, !tbaa !0
  %233 = getelementptr float addrspace(2)* %232, i32 0
  %234 = load float addrspace(2)* %233, !tbaa !0
  %235 = fmul float %234, %162
  %236 = getelementptr float addrspace(2)* %232, i32 1
  %237 = load float addrspace(2)* %236, !tbaa !0
  %238 = fmul float %237, %169
  %239 = fadd float %235, %238
  %240 = getelementptr float addrspace(2)* %232, i32 2
  %241 = load float addrspace(2)* %240, !tbaa !0
  %242 = fmul float %241, %176
  %243 = fadd float %239, %242
  %244 = getelementptr float addrspace(2)* %232, i32 3
  %245 = load float addrspace(2)* %244, !tbaa !0
  %246 = fmul float %245, %183
  %247 = fadd float %243, %246
  %248 = getelementptr float addrspace(2)* %232, i32 4
  %249 = load float addrspace(2)* %248, !tbaa !0
  %250 = fmul float %249, %162
  %251 = getelementptr float addrspace(2)* %232, i32 5
  %252 = load float addrspace(2)* %251, !tbaa !0
  %253 = fmul float %252, %169
  %254 = fadd float %250, %253
  %255 = getelementptr float addrspace(2)* %232, i32 6
  %256 = load float addrspace(2)* %255, !tbaa !0
  %257 = fmul float %256, %176
  %258 = fadd float %254, %257
  %259 = getelementptr float addrspace(2)* %232, i32 7
  %260 = load float addrspace(2)* %259, !tbaa !0
  %261 = fmul float %260, %183
  %262 = fadd float %258, %261
  %263 = getelementptr float addrspace(2)* %232, i32 8
  %264 = load float addrspace(2)* %263, !tbaa !0
  %265 = fmul float %264, %162
  %266 = getelementptr float addrspace(2)* %232, i32 9
  %267 = load float addrspace(2)* %266, !tbaa !0
  %268 = fmul float %267, %169
  %269 = fadd float %265, %268
  %270 = getelementptr float addrspace(2)* %232, i32 10
  %271 = load float addrspace(2)* %270, !tbaa !0
  %272 = fmul float %271, %176
  %273 = fadd float %269, %272
  %274 = getelementptr float addrspace(2)* %232, i32 11
  %275 = load float addrspace(2)* %274, !tbaa !0
  %276 = fmul float %275, %183
  %277 = fadd float %273, %276
  %278 = getelementptr float addrspace(2)* %232, i32 12
  %279 = load float addrspace(2)* %278, !tbaa !0
  %280 = fmul float %279, %162
  %281 = getelementptr float addrspace(2)* %232, i32 13
  %282 = load float addrspace(2)* %281, !tbaa !0
  %283 = fmul float %282, %169
  %284 = fadd float %280, %283
  %285 = getelementptr float addrspace(2)* %232, i32 14
  %286 = load float addrspace(2)* %285, !tbaa !0
  %287 = fmul float %286, %176
  %288 = fadd float %284, %287
  %289 = getelementptr float addrspace(2)* %232, i32 15
  %290 = load float addrspace(2)* %289, !tbaa !0
  %291 = fmul float %290, %183
  %292 = fadd float %288, %291
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %247, float %262, float %277, float %292)
  %293 = getelementptr float addrspace(2)* %232, i32 16
  %294 = load float addrspace(2)* %293, !tbaa !0
  %295 = fmul float %294, %162
  %296 = getelementptr float addrspace(2)* %232, i32 17
  %297 = load float addrspace(2)* %296, !tbaa !0
  %298 = fmul float %297, %169
  %299 = fadd float %295, %298
  %300 = getelementptr float addrspace(2)* %232, i32 18
  %301 = load float addrspace(2)* %300, !tbaa !0
  %302 = fmul float %301, %176
  %303 = fadd float %299, %302
  %304 = getelementptr float addrspace(2)* %232, i32 19
  %305 = load float addrspace(2)* %304, !tbaa !0
  %306 = fmul float %305, %183
  %307 = fadd float %303, %306
  %308 = getelementptr float addrspace(2)* %232, i32 20
  %309 = load float addrspace(2)* %308, !tbaa !0
  %310 = fmul float %309, %162
  %311 = getelementptr float addrspace(2)* %232, i32 21
  %312 = load float addrspace(2)* %311, !tbaa !0
  %313 = fmul float %312, %169
  %314 = fadd float %310, %313
  %315 = getelementptr float addrspace(2)* %232, i32 22
  %316 = load float addrspace(2)* %315, !tbaa !0
  %317 = fmul float %316, %176
  %318 = fadd float %314, %317
  %319 = getelementptr float addrspace(2)* %232, i32 23
  %320 = load float addrspace(2)* %319, !tbaa !0
  %321 = fmul float %320, %183
  %322 = fadd float %318, %321
  %323 = getelementptr float addrspace(2)* %232, i32 24
  %324 = load float addrspace(2)* %323, !tbaa !0
  %325 = fmul float %324, %162
  %326 = getelementptr float addrspace(2)* %232, i32 25
  %327 = load float addrspace(2)* %326, !tbaa !0
  %328 = fmul float %327, %169
  %329 = fadd float %325, %328
  %330 = getelementptr float addrspace(2)* %232, i32 26
  %331 = load float addrspace(2)* %330, !tbaa !0
  %332 = fmul float %331, %176
  %333 = fadd float %329, %332
  %334 = getelementptr float addrspace(2)* %232, i32 27
  %335 = load float addrspace(2)* %334, !tbaa !0
  %336 = fmul float %335, %183
  %337 = fadd float %333, %336
  %338 = getelementptr float addrspace(2)* %232, i32 28
  %339 = load float addrspace(2)* %338, !tbaa !0
  %340 = fmul float %339, %162
  %341 = getelementptr float addrspace(2)* %232, i32 29
  %342 = load float addrspace(2)* %341, !tbaa !0
  %343 = fmul float %342, %169
  %344 = fadd float %340, %343
  %345 = getelementptr float addrspace(2)* %232, i32 30
  %346 = load float addrspace(2)* %345, !tbaa !0
  %347 = fmul float %346, %176
  %348 = fadd float %344, %347
  %349 = getelementptr float addrspace(2)* %232, i32 31
  %350 = load float addrspace(2)* %349, !tbaa !0
  %351 = fmul float %350, %183
  %352 = fadd float %348, %351
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %307, float %322, float %337, float %352)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %196, float %198, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %204, float %206, float %12, float %12)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %141, float %148, float %155, float %190)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %207, float %208, float %209, float %210)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %224, float %226, float %221, float %183)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 191; mem:LD4[%57]
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR8, %VGPR1, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR3, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%111](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR4, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR4, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 17; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 16; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR4, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 18; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6, %SGPR5, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 19; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 21; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 20; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 22; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 23; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%231](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%281]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%278]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 25; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 24; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 26; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 27; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%285]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 29; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 28; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 30; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 31; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%289]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%266]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%263]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%270]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%274]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%251]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%248]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%255]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%259]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%236]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%233]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%240]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%244]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%341]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%338]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%345]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%349]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%326]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%323]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%330]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%334]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%311]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%308]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%315]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%319]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%296]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%293]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%300]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%304]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%117](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%65]
	S_WAITCNT 112
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 199; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR13<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 195; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR14<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR14<kill>, %VGPR13<kill>, %VGPR15<kill>, %VGPR15, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 204; mem:LD4[%77]
	S_WAITCNT 15
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 205; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 207; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR13<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 200; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 201; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 203; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR9<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR9<kill>, %VGPR13<kill>, %VGPR10<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 49; mem:LD4[%51]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 48; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 50; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 51; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 217; mem:LD4[%101]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 216; mem:LD4[%99]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 218; mem:LD4[%103]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 219; mem:LD4[%105]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 213; mem:LD4[%93]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 212; mem:LD4[%91]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 214; mem:LD4[%95]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 215; mem:LD4[%97]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 209; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 208; mem:LD4[%83]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 210; mem:LD4[%87]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 211; mem:LD4[%89]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR2<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 8; mem:LD16[%122](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4, %VGPR10, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	EXP 15, 36, 0, 0, 0, %VGPR4<kill>, %VGPR2<kill>, %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 220; mem:LD4[%107]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 221; mem:LD4[%109]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0410100
bf8c007f
c00403bf
c0028300
bf8c007f
7e060205
c0020301
bf8c007f
7e020204
d2820002
040e0208
d2060802
02010102
d2820004
04060608
d2060804
02010104
f800020f
02040404
c0840700
bf8c000f
e00c2000
80020600
bf8c0770
d2820002
040c0906
d2820004
040c0907
c0040311
bf8c007f
100a0808
c0040310
bf8c007f
d282000a
04141102
d2820005
040c0908
c0040312
bf8c007f
d2820003
04281105
d2820006
04040b06
c0040313
bf8c007f
d2820001
040c1106
c0040315
bf8c007f
10060808
c0040314
bf8c007f
d2820003
040c1102
c0040316
bf8c007f
d2820003
040c1105
c0040317
bf8c007f
d2820003
040c1106
c0400102
bf8c007f
c004010d
bf8c007f
100e0608
c004010c
bf8c007f
d2820008
041e0208
c0040319
bf8c007f
100e0808
c0040318
bf8c007f
d2820007
041c1102
c004031a
bf8c007f
d2820007
041c1105
c004031b
bf8c007f
d2820007
041c1106
c004010e
bf8c007f
d2820009
04220e08
c004031d
bf8c007f
10100808
c004031c
bf8c007f
d2820008
04201102
c004031e
bf8c007f
d2820008
04201105
c004031f
bf8c007f
d2820008
04201106
c004010f
bf8c007f
d2820009
04261008
c0040109
bf8c007f
10140608
c0040108
bf8c007f
d282000a
042a0208
c004010a
bf8c007f
d282000a
042a0e08
c004010b
bf8c007f
d282000a
042a1008
c0040105
bf8c007f
10160608
c0040104
bf8c007f
d282000b
042e0208
c0040106
bf8c007f
d282000b
042e0e08
c0040107
bf8c007f
d282000b
042e1008
c0040101
bf8c007f
10180608
c0040100
bf8c007f
d282000c
04320208
c0040102
bf8c007f
d282000c
04320e08
c0040103
bf8c007f
d282000c
04321008
f80000ef
090a0b0c
c004011d
bf8c000f
10120608
c004011c
bf8c007f
d2820009
04260208
c004011e
bf8c007f
d2820009
04260e08
c004011f
bf8c007f
d2820009
04261008
c0040119
bf8c007f
10140608
c0040118
bf8c007f
d282000a
042a0208
c004011a
bf8c007f
d282000a
042a0e08
c004011b
bf8c007f
d282000a
042a1008
c0040115
bf8c007f
10160608
c0040114
bf8c007f
d282000b
042e0208
c0040116
bf8c007f
d282000b
042e0e08
c0040117
bf8c007f
d282000b
042e1008
c0040111
bf8c007f
10180608
c0040110
bf8c007f
d282000c
04320208
c0040112
bf8c007f
d282000c
04320e08
c0000113
bf8c007f
d282000c
04321000
f80000ff
090a0b0c
c0840704
bf8c000f
e00c2000
80020900
c00003c4
bf8c0070
101a1200
c00003c5
bf8c007f
d282000d
0434010a
c00003c7
bf8c007f
061a1a00
c00003c0
bf8c007f
101c1200
c00003c1
bf8c007f
d282000e
0438010a
c00003c3
bf8c007f
061c1c00
7e1e0280
f800021f
0f0f0d0e
c00003cc
bf8c000f
101a1200
c00003cd
bf8c007f
d282000d
0434010a
c00003cf
bf8c007f
061a1a00
c00003c8
bf8c007f
101c1200
c00003c9
bf8c007f
d2820009
0438010a
c00003cb
bf8c007f
06121200
7e140205
7e160205
f800022f
0b0a0d09
c0000331
bf8c000f
10120800
c0000330
bf8c007f
d2820009
04240102
c0000332
bf8c007f
d2820009
04240105
c0000333
bf8c007f
d2820009
04240106
c00003d9
bf8c007f
10140800
c00003d8
bf8c007f
d282000a
04280102
c00003da
bf8c007f
d282000a
04280105
c00003db
bf8c007f
d282000a
04280106
c00003d5
bf8c007f
10160800
c00003d4
bf8c007f
d282000b
042c0102
c00003d6
bf8c007f
d282000b
042c0105
c00003d7
bf8c007f
d282000b
042c0106
c00003d1
bf8c007f
10080800
c00003d0
bf8c007f
d2820002
04100102
c00003d2
bf8c007f
d2820002
04080105
c00003d3
bf8c007f
d2820002
04080106
f800023f
090a0b02
c0840708
bf8c000f
e00c2000
80020900
bf8c0770
10001205
10041404
10081204
f800024f
00000204
c00003dc
bf8c000f
d2820000
04061000
c0000302
bf8c007f
10020e00
08021101
c00003dd
bf8c007f
10041000
08040702
f80008cf
08010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE
DCL IN[4], GENERIC[22], PERSPECTIVE
DCL IN[5], GENERIC[23], PERSPECTIVE
DCL IN[6], GENERIC[24], PERSPECTIVE, CENTROID
DCL IN[7], GENERIC[25], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..30]
DCL TEMP[0..8], LOCAL
DCL TEMP[9], ARRAY(1), LOCAL
IMM[0] FLT32 {   -0.4082,     0.7071,     0.5774,    -0.4082}
IMM[1] FLT32 {    0.8165,     0.0000,     0.5774,    -0.4082}
IMM[2] FLT32 {   -0.4082,    -0.7071,     0.5774,     0.0000}
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[3], 2D
  2: ADD TEMP[1].xyz, -IN[2].xyzz, CONST[10].xyzz
  3: MUL TEMP[2].xyz, TEMP[0].yyyy, IMM[0].xyzz
  4: MAD TEMP[2].xyz, TEMP[0].xxxx, IMM[1].xyzz, TEMP[2].xyzz
  5: MAD TEMP[2].xyz, TEMP[0].zzzz, IMM[2].xyzz, TEMP[2].xyzz
  6: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
  7: RSQ TEMP[3].x, TEMP[3].xxxx
  8: MUL TEMP[3].xyz, TEMP[2].xyzz, TEMP[3].xxxx
  9: DP3 TEMP[2].x, TEMP[3].xyzz, IN[3].xyzz
 10: DP3 TEMP[4].x, TEMP[3].xyzz, IN[4].xyzz
 11: MOV TEMP[2].y, TEMP[4].xxxx
 12: DP3 TEMP[4].x, TEMP[3].xyzz, IN[5].xyzz
 13: MOV TEMP[2].z, TEMP[4].xxxx
 14: DP3 TEMP[4].x, TEMP[2].xyzz, TEMP[1].xyzz
 15: ADD TEMP[4].x, TEMP[4].xxxx, TEMP[4].xxxx
 16: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[2].xyzz
 17: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[5].xxxx
 18: MAD TEMP[2].xyz, TEMP[4].xxxx, TEMP[2].xyzz, -TEMP[1].xyzz
 19: MOV TEMP[4].xyz, TEMP[2].xyzz
 20: TEX TEMP[4].xyz, TEMP[4], SAMP[2], CUBE
 21: MOV TEMP[5].xy, IN[1].xyyy
 22: TEX TEMP[5].xyz, TEMP[5], SAMP[0], 2D
 23: MOV TEMP[6].xy, IN[6].wzzz
 24: TEX TEMP[6].xyz, TEMP[6], SAMP[1], 2D
 25: MOV TEMP[7].xy, IN[6].xyyy
 26: TEX TEMP[7].xyz, TEMP[7], SAMP[1], 2D
 27: MOV TEMP[8].xy, IN[7].xyyy
 28: TEX TEMP[8].xyz, TEMP[8], SAMP[1], 2D
 29: MUL TEMP[4].xyz, TEMP[4].xyzz, CONST[30].zzzz
 30: MUL TEMP[4].xyz, TEMP[4].xyzz, CONST[0].xyzz
 31: MUL TEMP[5].xyz, TEMP[5].xyzz, IN[0].xyzz
 32: MUL TEMP[3].xyz, TEMP[0].yyyy, TEMP[6].xyzz
 33: MAD TEMP[1].xyz, TEMP[0].xxxx, TEMP[7].xyzz, TEMP[3].xyzz
 34: MAD TEMP[0].xyz, TEMP[0].zzzz, TEMP[8].xyzz, TEMP[1].xyzz
 35: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[12].xyzz
 36: MAD TEMP[1].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
 37: MAD TEMP[0].xyz, TEMP[5].xyzz, TEMP[0].xyzz, TEMP[4].xyzz
 38: MIN TEMP[1].x, TEMP[1].xxxx, CONST[11].zzzz
 39: MOV_SAT TEMP[1].x, TEMP[1].xxxx
 40: MAD TEMP[2].xyz, TEMP[0].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 41: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 42: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[1].xxxx
 43: MAD TEMP[0].xyz, TEMP[0].xyzz, CONST[30].xxxx, TEMP[2].xyzz
 44: MUL TEMP[1].x, IN[2].wwww, CONST[29].wwww
 45: MOV TEMP[0].w, TEMP[1].xxxx
 46: MOV TEMP[9], TEMP[0]
 47: MOV OUT[0], TEMP[9]
 48: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 0
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 1
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 2
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 40
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 41
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 42
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 44
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 46
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 47
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 48
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 49
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr float addrspace(2)* %21, i32 50
  %45 = load float addrspace(2)* %44, !tbaa !0
  %46 = getelementptr float addrspace(2)* %21, i32 116
  %47 = load float addrspace(2)* %46, !tbaa !0
  %48 = getelementptr float addrspace(2)* %21, i32 117
  %49 = load float addrspace(2)* %48, !tbaa !0
  %50 = getelementptr float addrspace(2)* %21, i32 118
  %51 = load float addrspace(2)* %50, !tbaa !0
  %52 = getelementptr float addrspace(2)* %21, i32 119
  %53 = load float addrspace(2)* %52, !tbaa !0
  %54 = getelementptr float addrspace(2)* %21, i32 120
  %55 = load float addrspace(2)* %54, !tbaa !0
  %56 = getelementptr float addrspace(2)* %21, i32 122
  %57 = load float addrspace(2)* %56, !tbaa !0
  %58 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %59 = load <32 x i8> addrspace(2)* %58, !tbaa !0
  %60 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
  %62 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %63 = load <32 x i8> addrspace(2)* %62, !tbaa !0
  %64 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
  %66 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %67 = load <32 x i8> addrspace(2)* %66, !tbaa !0
  %68 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
  %70 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %71 = load <32 x i8> addrspace(2)* %70, !tbaa !0
  %72 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %73 = load <16 x i8> addrspace(2)* %72, !tbaa !0
  %74 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %75 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %76 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %77 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %78 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %79 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %80 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %81 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %82 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %83 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
  %84 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
  %85 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %86 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
  %87 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
  %88 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
  %89 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
  %90 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
  %91 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
  %92 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %6)
  %93 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %6)
  %94 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %3, <2 x i32> %6)
  %95 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %3, <2 x i32> %6)
  %96 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %3, <2 x i32> %6)
  %97 = call float @llvm.SI.fs.interp(i32 1, i32 7, i32 %3, <2 x i32> %6)
  %98 = bitcast float %77 to i32
  %99 = bitcast float %78 to i32
  %100 = insertelement <2 x i32> undef, i32 %98, i32 0
  %101 = insertelement <2 x i32> %100, i32 %99, i32 1
  %102 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %101, <32 x i8> %71, <16 x i8> %73, i32 2)
  %103 = extractelement <4 x float> %102, i32 0
  %104 = extractelement <4 x float> %102, i32 1
  %105 = extractelement <4 x float> %102, i32 2
  %106 = fsub float -0.000000e+00, %79
  %107 = fadd float %106, %29
  %108 = fsub float -0.000000e+00, %80
  %109 = fadd float %108, %31
  %110 = fsub float -0.000000e+00, %81
  %111 = fadd float %110, %33
  %112 = fmul float %104, 0xBFDA20BDA0000000
  %113 = fmul float %104, 0x3FE6A09E60000000
  %114 = fmul float %104, 0x3FE279A740000000
  %115 = fmul float %103, 0x3FEA20BD80000000
  %116 = fadd float %115, %112
  %117 = fmul float %103, 0.000000e+00
  %118 = fadd float %117, %113
  %119 = fmul float %103, 0x3FE279A740000000
  %120 = fadd float %119, %114
  %121 = fmul float %105, 0xBFDA20BD20000000
  %122 = fadd float %121, %116
  %123 = fmul float %105, 0xBFE6A09E80000000
  %124 = fadd float %123, %118
  %125 = fmul float %105, 0x3FE279A740000000
  %126 = fadd float %125, %120
  %127 = fmul float %122, %122
  %128 = fmul float %124, %124
  %129 = fadd float %128, %127
  %130 = fmul float %126, %126
  %131 = fadd float %129, %130
  %132 = call float @llvm.AMDGPU.rsq(float %131)
  %133 = fmul float %122, %132
  %134 = fmul float %124, %132
  %135 = fmul float %126, %132
  %136 = fmul float %133, %83
  %137 = fmul float %134, %84
  %138 = fadd float %137, %136
  %139 = fmul float %135, %85
  %140 = fadd float %138, %139
  %141 = fmul float %133, %86
  %142 = fmul float %134, %87
  %143 = fadd float %142, %141
  %144 = fmul float %135, %88
  %145 = fadd float %143, %144
  %146 = fmul float %133, %89
  %147 = fmul float %134, %90
  %148 = fadd float %147, %146
  %149 = fmul float %135, %91
  %150 = fadd float %148, %149
  %151 = fmul float %140, %107
  %152 = fmul float %145, %109
  %153 = fadd float %152, %151
  %154 = fmul float %150, %111
  %155 = fadd float %153, %154
  %156 = fadd float %155, %155
  %157 = fmul float %140, %140
  %158 = fmul float %145, %145
  %159 = fadd float %158, %157
  %160 = fmul float %150, %150
  %161 = fadd float %159, %160
  %162 = fmul float %107, %161
  %163 = fmul float %109, %161
  %164 = fmul float %111, %161
  %165 = fsub float -0.000000e+00, %162
  %166 = fmul float %156, %140
  %167 = fadd float %166, %165
  %168 = fsub float -0.000000e+00, %163
  %169 = fmul float %156, %145
  %170 = fadd float %169, %168
  %171 = fsub float -0.000000e+00, %164
  %172 = fmul float %156, %150
  %173 = fadd float %172, %171
  %174 = insertelement <4 x float> undef, float %167, i32 0
  %175 = insertelement <4 x float> %174, float %170, i32 1
  %176 = insertelement <4 x float> %175, float %173, i32 2
  %177 = insertelement <4 x float> %176, float 0.000000e+00, i32 3
  %178 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %177)
  %179 = extractelement <4 x float> %178, i32 0
  %180 = extractelement <4 x float> %178, i32 1
  %181 = extractelement <4 x float> %178, i32 2
  %182 = extractelement <4 x float> %178, i32 3
  %183 = call float @fabs(float %181)
  %184 = fdiv float 1.000000e+00, %183
  %185 = fmul float %179, %184
  %186 = fadd float %185, 1.500000e+00
  %187 = fmul float %180, %184
  %188 = fadd float %187, 1.500000e+00
  %189 = bitcast float %188 to i32
  %190 = bitcast float %186 to i32
  %191 = bitcast float %182 to i32
  %192 = insertelement <4 x i32> undef, i32 %189, i32 0
  %193 = insertelement <4 x i32> %192, i32 %190, i32 1
  %194 = insertelement <4 x i32> %193, i32 %191, i32 2
  %195 = insertelement <4 x i32> %194, i32 undef, i32 3
  %196 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %195, <32 x i8> %67, <16 x i8> %69, i32 4)
  %197 = extractelement <4 x float> %196, i32 0
  %198 = extractelement <4 x float> %196, i32 1
  %199 = extractelement <4 x float> %196, i32 2
  %200 = bitcast float %77 to i32
  %201 = bitcast float %78 to i32
  %202 = insertelement <2 x i32> undef, i32 %200, i32 0
  %203 = insertelement <2 x i32> %202, i32 %201, i32 1
  %204 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %203, <32 x i8> %59, <16 x i8> %61, i32 2)
  %205 = extractelement <4 x float> %204, i32 0
  %206 = extractelement <4 x float> %204, i32 1
  %207 = extractelement <4 x float> %204, i32 2
  %208 = bitcast float %95 to i32
  %209 = bitcast float %94 to i32
  %210 = insertelement <2 x i32> undef, i32 %208, i32 0
  %211 = insertelement <2 x i32> %210, i32 %209, i32 1
  %212 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %211, <32 x i8> %63, <16 x i8> %65, i32 2)
  %213 = extractelement <4 x float> %212, i32 0
  %214 = extractelement <4 x float> %212, i32 1
  %215 = extractelement <4 x float> %212, i32 2
  %216 = bitcast float %92 to i32
  %217 = bitcast float %93 to i32
  %218 = insertelement <2 x i32> undef, i32 %216, i32 0
  %219 = insertelement <2 x i32> %218, i32 %217, i32 1
  %220 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %219, <32 x i8> %63, <16 x i8> %65, i32 2)
  %221 = extractelement <4 x float> %220, i32 0
  %222 = extractelement <4 x float> %220, i32 1
  %223 = extractelement <4 x float> %220, i32 2
  %224 = bitcast float %96 to i32
  %225 = bitcast float %97 to i32
  %226 = insertelement <2 x i32> undef, i32 %224, i32 0
  %227 = insertelement <2 x i32> %226, i32 %225, i32 1
  %228 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %227, <32 x i8> %63, <16 x i8> %65, i32 2)
  %229 = extractelement <4 x float> %228, i32 0
  %230 = extractelement <4 x float> %228, i32 1
  %231 = extractelement <4 x float> %228, i32 2
  %232 = fmul float %197, %57
  %233 = fmul float %198, %57
  %234 = fmul float %199, %57
  %235 = fmul float %232, %23
  %236 = fmul float %233, %25
  %237 = fmul float %234, %27
  %238 = fmul float %205, %74
  %239 = fmul float %206, %75
  %240 = fmul float %207, %76
  %241 = fmul float %104, %213
  %242 = fmul float %104, %214
  %243 = fmul float %104, %215
  %244 = fmul float %103, %221
  %245 = fadd float %244, %241
  %246 = fmul float %103, %222
  %247 = fadd float %246, %242
  %248 = fmul float %103, %223
  %249 = fadd float %248, %243
  %250 = fmul float %105, %229
  %251 = fadd float %250, %245
  %252 = fmul float %105, %230
  %253 = fadd float %252, %247
  %254 = fmul float %105, %231
  %255 = fadd float %254, %249
  %256 = fmul float %251, %41
  %257 = fmul float %253, %43
  %258 = fmul float %255, %45
  %259 = fsub float -0.000000e+00, %35
  %260 = fmul float %82, %39
  %261 = fadd float %260, %259
  %262 = fmul float %238, %256
  %263 = fadd float %262, %235
  %264 = fmul float %239, %257
  %265 = fadd float %264, %236
  %266 = fmul float %240, %258
  %267 = fadd float %266, %237
  %268 = fcmp uge float %261, %37
  %269 = select i1 %268, float %37, float %261
  %270 = call float @llvm.AMDIL.clamp.(float %269, float 0.000000e+00, float 1.000000e+00)
  %271 = fsub float -0.000000e+00, %55
  %272 = fmul float %263, %271
  %273 = fadd float %272, %47
  %274 = fsub float -0.000000e+00, %55
  %275 = fmul float %265, %274
  %276 = fadd float %275, %49
  %277 = fsub float -0.000000e+00, %55
  %278 = fmul float %267, %277
  %279 = fadd float %278, %51
  %280 = fmul float %270, %270
  %281 = fmul float %273, %280
  %282 = fmul float %276, %280
  %283 = fmul float %279, %280
  %284 = fmul float %263, %55
  %285 = fadd float %284, %281
  %286 = fmul float %265, %55
  %287 = fadd float %286, %282
  %288 = fmul float %267, %55
  %289 = fadd float %288, %283
  %290 = fmul float %82, %53
  %291 = call i32 @llvm.SI.packf16(float %285, float %287)
  %292 = bitcast i32 %291 to float
  %293 = call i32 @llvm.SI.packf16(float %289, float %290)
  %294 = bitcast i32 %293 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %292, float %294, float %292, float %294)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 12; mem:LD16[%72](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 24; mem:LD32[%70](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR9<def> = V_MUL_F32_e32 7.071068e-01, %VGPR5, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR4, 0.000000e+00, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 -7.071068e-01, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR6, %VGPR10<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 -4.082483e-01, %VGPR5, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 8.164966e-01, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR4, %VGPR11<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 -4.082482e-01, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR6, %VGPR11<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR12, %VGPR12, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR10, %VGPR10, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 5.773503e-01, %VGPR5, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 5.773503e-01, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR4, %VGPR13, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR6, %VGPR13<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR9, %VGPR9, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_RSQ_LEGACY_F32_e32 %VGPR11<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR12, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR10, %VGPR14<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR13, %VGPR9<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR12, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR10, %VGPR14<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR13, %VGPR14<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR11, %VGPR11, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR9, %VGPR9, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR10<kill>, %VGPR15<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR13<kill>, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR10, %VGPR10, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 41; mem:LD4[%30]
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR7<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR15, %VGPR12, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 40; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR14<def> = V_SUB_F32_e32 %SGPR7<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR11, %VGPR14, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR9, %VGPR15<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 42; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR7<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR10, %VGPR15, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e32 %VGPR16<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR16, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %VGPR9<kill>, %VGPR13<kill>, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR16, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR9<kill>, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR20<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR10<def> = V_CUBESC_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR9<def> = V_CUBETC_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR11<def> = V_CUBEMA_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR12<def> = V_CUBEID_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR17<def> = V_ADD_F32_e64 %VGPR11, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_RCP_F32_e32 %VGPR17<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR9, %VGPR17, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR10<def> = V_MAD_F32 %VGPR10, %VGPR17<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR13<def> = KILL %VGPR13<undef>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%68](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%66](tbaa=!"const")
	S_WAITCNT 127
	%VGPR9_VGPR10_VGPR11<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR10_VGPR11_VGPR12_VGPR13, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 122; mem:LD4[%56]
	S_WAITCNT 112
	%VGPR12<def> = V_MUL_F32_e32 %SGPR7, %VGPR10, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%24]
	S_WAITCNT 127
	%VGPR24<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR2, 2, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-def>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<tied0>, %VGPR3, 2, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR2, 3, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<tied0>, %VGPR3, 3, 6, %M0<kill>, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%64](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%62](tbaa=!"const")
	S_WAITCNT 127
	%VGPR12_VGPR13_VGPR14<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR12_VGPR13<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %VGPR5, %VGPR13, %EXEC<imp-use>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR2, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-def>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<tied0>, %VGPR3, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR2, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<tied0>, %VGPR3, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR15_VGPR16_VGPR17<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR15_VGPR16<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MAD_F32 %VGPR4, %VGPR16, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_INTERP_P1_F32 %VGPR2, 1, 7, %M0<kill>, %EXEC<imp-use>, %VGPR19_VGPR20<imp-def>
	%VGPR20<def,tied1> = V_INTERP_P2_F32 %VGPR20<tied0>, %VGPR3, 1, 7, %M0<kill>, %EXEC<imp-use>, %VGPR19_VGPR20<imp-use,kill>, %VGPR19_VGPR20<imp-def>
	%VGPR19<def> = V_INTERP_P1_F32 %VGPR2, 0, 7, %M0<kill>, %EXEC<imp-use>, %VGPR19_VGPR20<imp-use,kill>, %VGPR19_VGPR20<imp-def>
	%VGPR19<def,tied1> = V_INTERP_P2_F32 %VGPR19<tied0>, %VGPR3, 0, 7, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR19_VGPR20<imp-use,kill>, %VGPR19_VGPR20<imp-def>
	%VGPR21_VGPR22_VGPR23<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR19_VGPR20<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %VGPR22, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 49; mem:LD4[%42]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%60](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%58](tbaa=!"const")
	S_WAITCNT 127
	%VGPR18_VGPR19_VGPR20<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR3<def> = V_MUL_F32_e32 %VGPR19, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR3<kill>, %VGPR2<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%54]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR7, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%48]
	S_WAITCNT 127
	%VGPR8<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 47; mem:LD4[%38]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 44; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR3<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 46; mem:LD4[%36]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR24<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR7<kill>, %SGPR2, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %SGPR7, %VGPR9, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR5, %VGPR12, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR4, %VGPR15, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR6, %VGPR21, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR24<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR25<def,tied1> = V_INTERP_P2_F32 %VGPR25<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR18, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR25<kill>, %VGPR24<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 116; mem:LD4[%46]
	S_WAITCNT 127
	%VGPR24<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8<kill>, %SGPR2, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR11, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR5, %VGPR14, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14<imp-use,kill>
	%VGPR9<def> = V_MAD_F32 %VGPR4, %VGPR17, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR15_VGPR16_VGPR17<imp-use,kill>
	%VGPR4<def> = V_MAD_F32 %VGPR6, %VGPR23, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23<imp-use,kill>, %VGPR4_VGPR5_VGPR6<imp-use,kill>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%44]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR20, %VGPR5<kill>, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20<imp-use,kill>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %VGPR4<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2, %VGPR0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 118; mem:LD4[%50]
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 119; mem:LD4[%52]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR7<kill>, %VGPR0<kill>, %VGPR7, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8200500
c8210501
c81c0400
c81d0401
c084030c
c0c60518
bf8c007f
f0800700
00430407
bf8c0770
10120aff
3f3504f3
d2820009
04250104
7e1402ff
bf3504f4
d282000a
04261506
10120aff
bed105ed
7e1602ff
3f5105ec
d2820009
04261704
7e1602ff
bed105e9
d282000c
04261706
1012190c
d282000b
0426150a
10120aff
3f13cd3a
7e1a02ff
3f13cd3a
d2820009
04261b04
d2820009
04261b06
d282000b
042e1309
7e165b0b
1014170a
1018170c
c8341000
c8351001
101a1b0c
c8381100
c8391101
d282000e
04361d0a
101a1709
c8241200
c8251201
d2820009
043a130d
c82c0c00
c82d0c01
1016170c
c8380d00
c8390d01
d282000b
042e1d0a
c8380e00
c8390e01
d282000b
042e1d0d
101c170b
d282000e
043a1309
c83c1400
c83d1401
10181f0c
c83c1500
c83d1501
d282000a
04321f0a
c8301600
c8311601
d282000a
042a190d
d282000c
043a150a
c8340900
c8350901
c0400100
bf8c007f
c0038129
bf8c007f
081e1a07
101a190f
c8380800
c8390801
c0038128
bf8c007f
081c1c07
10201d0b
d2820010
04421f09
c83c0a00
c83d0a01
c003812a
bf8c007f
081e1e07
d2820010
04421f0a
06202110
10121310
08241b09
1012190e
10161710
0822130b
1012190f
10141510
0826130a
7e280280
d28a000a
044e2511
d28c0009
044e2511
d28e000b
044e2511
d288000c
044e2511
d2060111
0201010b
7e225511
7e2402ff
3fc00000
d282000b
044a2309
d282000a
044a230a
c0840308
c0c60510
bf8c007f
f0800700
0043090a
c003817a
bf8c0070
10181407
c0040101
bf8c007f
10301808
c8341a02
c8351a03
c8301b02
c8311b03
c0840304
c0c60508
bf8c007f
f0800700
00430c0c
bf8c0770
10241b05
c8401902
c8411903
c83c1802
c83d1803
f0800700
00430f0f
bf8c0770
d2820012
044a2104
c8501d02
c8511d03
c84c1c02
c84d1c03
f0800700
00431513
bf8c0770
d2820002
044a2d06
c0040131
bf8c007f
10040408
c0840300
c0c60500
bf8c007f
f0800700
00431207
c80c0100
c80d0101
bf8c0770
10060713
d2820007
04620503
c0010178
bf8c007f
10040e02
c0018175
bf8c007f
08100403
c8080b00
c8090b01
c001812f
bf8c007f
10060403
c001812c
bf8c007f
0a060603
c001812e
bf8c007f
d00c0004
02000703
7e300203
d2000003
00123103
d2060803
02010103
10060703
10100708
d2820007
04200507
10101207
c0018100
bf8c007f
10101003
10301905
d2820018
04621f04
d2820018
04622b06
c0018130
bf8c007f
10303003
c8640000
c8650001
10323312
d2820008
04223119
10301002
c0018174
bf8c007f
08303003
10300718
d2820008
04600508
5e0e0f08
10101607
c0018102
bf8c007f
10101003
10121d05
d2820009
04262304
d2820004
04262f06
c0018132
bf8c007f
10080803
c8140200
c8150201
10000b14
d2820000
04220900
10020002
c0018176
bf8c007f
08020203
10020701
d2820000
04040500
c0000177
bf8c007f
10020400
5e000300
f8001c0f
00070007
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL OUT[7], GENERIC[23]
DCL OUT[8], GENERIC[24]
DCL OUT[9], GENERIC[25]
DCL CONST[0..51]
DCL TEMP[0..12], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[6]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: DP4 TEMP[5].x, TEMP[0], CONST[7]
 12: MOV TEMP[2].w, TEMP[5].xxxx
 13: DP4 TEMP[6].x, TEMP[0], CONST[12]
 14: DP3 TEMP[7].x, IN[1].xyzz, CONST[48].xyzz
 15: MOV TEMP[7].z, TEMP[7].xxxx
 16: DP3 TEMP[8].x, IN[1].xyzz, CONST[49].xyzz
 17: MOV TEMP[8].z, TEMP[8].xxxx
 18: DP3 TEMP[9].x, IN[1].xyzz, CONST[50].xyzz
 19: MOV TEMP[9].z, TEMP[9].xxxx
 20: DP3 TEMP[7].x, IN[5].xyzz, CONST[48].xyzz
 21: DP3 TEMP[8].x, IN[5].xyzz, CONST[49].xyzz
 22: DP3 TEMP[9].x, IN[5].xyzz, CONST[50].xyzz
 23: DP3 TEMP[10].x, IN[6].xyzz, CONST[48].xyzz
 24: MOV TEMP[7].y, TEMP[10].xxxx
 25: ADD TEMP[0].xy, IN[4].xyyy, IN[3].xyyy
 26: DP3 TEMP[10].x, IN[6].xyzz, CONST[49].xyzz
 27: MOV TEMP[8].y, TEMP[10].xxxx
 28: ADD TEMP[10].xy, TEMP[0].yxxx, IN[4].yxxx
 29: MOV TEMP[0].zw, TEMP[10].yyxy
 30: DP3 TEMP[11].x, IN[6].xyzz, CONST[50].xyzz
 31: MOV TEMP[9].y, TEMP[11].xxxx
 32: MOV TEMP[0], TEMP[0]
 33: ADD TEMP[10].xy, TEMP[10].yxxx, IN[4].xyyy
 34: MOV TEMP[1].w, TEMP[6].xxxx
 35: MOV TEMP[6].xy, IN[2].xyxx
 36: MOV TEMP[10].zw, IN[2].yyxy
 37: MAD TEMP[11], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 38: MOV TEMP[12], TEMP[2]
 39: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[5].xxxx
 40: MOV TEMP[2].z, TEMP[4].xxxx
 41: MOV TEMP[2].y, -TEMP[3].xxxx
 42: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[5].xxxx, TEMP[2].xyyy
 43: MOV OUT[3], TEMP[6]
 44: MOV OUT[8], TEMP[0]
 45: MOV OUT[9], TEMP[10]
 46: MOV OUT[0], TEMP[2]
 47: MOV OUT[4], TEMP[1]
 48: MOV OUT[2], TEMP[12]
 49: MOV OUT[5], TEMP[7]
 50: MOV OUT[6], TEMP[8]
 51: MOV_SAT OUT[1], TEMP[11]
 52: MOV OUT[7], TEMP[9]
 53: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 16
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 17
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 18
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 19
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 20
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 21
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 22
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 23
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 24
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 25
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 26
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 27
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 28
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 29
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 30
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 31
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 48
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 49
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 50
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 51
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 191
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 192
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 193
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 194
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 195
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 196
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 197
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 198
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 199
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 200
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 201
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 202
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 203
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 204
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 205
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %5)
  %90 = extractelement <4 x float> %89, i32 0
  %91 = extractelement <4 x float> %89, i32 1
  %92 = extractelement <4 x float> %89, i32 2
  %93 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %94 = load <16 x i8> addrspace(2)* %93, !tbaa !0
  %95 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %94, i32 0, i32 %5)
  %96 = extractelement <4 x float> %95, i32 0
  %97 = extractelement <4 x float> %95, i32 1
  %98 = extractelement <4 x float> %95, i32 2
  %99 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %100 = load <16 x i8> addrspace(2)* %99, !tbaa !0
  %101 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %100, i32 0, i32 %5)
  %102 = extractelement <4 x float> %101, i32 0
  %103 = extractelement <4 x float> %101, i32 1
  %104 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %105 = load <16 x i8> addrspace(2)* %104, !tbaa !0
  %106 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %105, i32 0, i32 %5)
  %107 = extractelement <4 x float> %106, i32 0
  %108 = extractelement <4 x float> %106, i32 1
  %109 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %110 = load <16 x i8> addrspace(2)* %109, !tbaa !0
  %111 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %110, i32 0, i32 %5)
  %112 = extractelement <4 x float> %111, i32 0
  %113 = extractelement <4 x float> %111, i32 1
  %114 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
  %115 = load <16 x i8> addrspace(2)* %114, !tbaa !0
  %116 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %115, i32 0, i32 %5)
  %117 = extractelement <4 x float> %116, i32 0
  %118 = extractelement <4 x float> %116, i32 1
  %119 = extractelement <4 x float> %116, i32 2
  %120 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
  %121 = load <16 x i8> addrspace(2)* %120, !tbaa !0
  %122 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %121, i32 0, i32 %5)
  %123 = extractelement <4 x float> %122, i32 0
  %124 = extractelement <4 x float> %122, i32 1
  %125 = extractelement <4 x float> %122, i32 2
  %126 = fmul float %90, %14
  %127 = fadd float %126, %12
  %128 = fmul float %91, %14
  %129 = fadd float %128, %12
  %130 = fmul float %92, %14
  %131 = fadd float %130, %12
  %132 = fmul float %90, %12
  %133 = fadd float %132, %14
  %134 = fmul float %127, %60
  %135 = fmul float %129, %62
  %136 = fadd float %134, %135
  %137 = fmul float %131, %64
  %138 = fadd float %136, %137
  %139 = fmul float %133, %66
  %140 = fadd float %138, %139
  %141 = fmul float %127, %68
  %142 = fmul float %129, %70
  %143 = fadd float %141, %142
  %144 = fmul float %131, %72
  %145 = fadd float %143, %144
  %146 = fmul float %133, %74
  %147 = fadd float %145, %146
  %148 = fmul float %127, %76
  %149 = fmul float %129, %78
  %150 = fadd float %148, %149
  %151 = fmul float %131, %80
  %152 = fadd float %150, %151
  %153 = fmul float %133, %82
  %154 = fadd float %152, %153
  %155 = fmul float %127, %18
  %156 = fmul float %129, %20
  %157 = fadd float %155, %156
  %158 = fmul float %131, %22
  %159 = fadd float %157, %158
  %160 = fmul float %133, %24
  %161 = fadd float %159, %160
  %162 = fmul float %127, %26
  %163 = fmul float %129, %28
  %164 = fadd float %162, %163
  %165 = fmul float %131, %30
  %166 = fadd float %164, %165
  %167 = fmul float %133, %32
  %168 = fadd float %166, %167
  %169 = fmul float %127, %34
  %170 = fmul float %129, %36
  %171 = fadd float %169, %170
  %172 = fmul float %131, %38
  %173 = fadd float %171, %172
  %174 = fmul float %133, %40
  %175 = fadd float %173, %174
  %176 = fmul float %127, %42
  %177 = fmul float %129, %44
  %178 = fadd float %176, %177
  %179 = fmul float %131, %46
  %180 = fadd float %178, %179
  %181 = fmul float %133, %48
  %182 = fadd float %180, %181
  %183 = fmul float %127, %50
  %184 = fmul float %129, %52
  %185 = fadd float %183, %184
  %186 = fmul float %131, %54
  %187 = fadd float %185, %186
  %188 = fmul float %133, %56
  %189 = fadd float %187, %188
  %190 = fmul float %96, %60
  %191 = fmul float %97, %62
  %192 = fadd float %191, %190
  %193 = fmul float %98, %64
  %194 = fadd float %192, %193
  %195 = fmul float %96, %68
  %196 = fmul float %97, %70
  %197 = fadd float %196, %195
  %198 = fmul float %98, %72
  %199 = fadd float %197, %198
  %200 = fmul float %96, %76
  %201 = fmul float %97, %78
  %202 = fadd float %201, %200
  %203 = fmul float %98, %80
  %204 = fadd float %202, %203
  %205 = fmul float %117, %60
  %206 = fmul float %118, %62
  %207 = fadd float %206, %205
  %208 = fmul float %119, %64
  %209 = fadd float %207, %208
  %210 = fmul float %117, %68
  %211 = fmul float %118, %70
  %212 = fadd float %211, %210
  %213 = fmul float %119, %72
  %214 = fadd float %212, %213
  %215 = fmul float %117, %76
  %216 = fmul float %118, %78
  %217 = fadd float %216, %215
  %218 = fmul float %119, %80
  %219 = fadd float %217, %218
  %220 = fmul float %123, %60
  %221 = fmul float %124, %62
  %222 = fadd float %221, %220
  %223 = fmul float %125, %64
  %224 = fadd float %222, %223
  %225 = fadd float %112, %107
  %226 = fadd float %113, %108
  %227 = fmul float %123, %68
  %228 = fmul float %124, %70
  %229 = fadd float %228, %227
  %230 = fmul float %125, %72
  %231 = fadd float %229, %230
  %232 = fadd float %226, %113
  %233 = fadd float %225, %112
  %234 = fmul float %123, %76
  %235 = fmul float %124, %78
  %236 = fadd float %235, %234
  %237 = fmul float %125, %80
  %238 = fadd float %236, %237
  %239 = fadd float %233, %112
  %240 = fadd float %232, %113
  %241 = fmul float %58, %12
  %242 = fadd float %241, %14
  %243 = fmul float %58, %12
  %244 = fadd float %243, %14
  %245 = fmul float %58, %12
  %246 = fadd float %245, %14
  %247 = fmul float %58, %14
  %248 = fadd float %247, %12
  %249 = fsub float -0.000000e+00, %182
  %250 = fmul float %175, %16
  %251 = fadd float %250, %249
  %252 = fsub float -0.000000e+00, %168
  %253 = fmul float %84, %182
  %254 = fadd float %253, %161
  %255 = fmul float %86, %182
  %256 = fadd float %255, %252
  %257 = call float @llvm.AMDIL.clamp.(float %242, float 0.000000e+00, float 1.000000e+00)
  %258 = call float @llvm.AMDIL.clamp.(float %244, float 0.000000e+00, float 1.000000e+00)
  %259 = call float @llvm.AMDIL.clamp.(float %246, float 0.000000e+00, float 1.000000e+00)
  %260 = call float @llvm.AMDIL.clamp.(float %248, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %257, float %258, float %259, float %260)
  %261 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %262 = load float addrspace(2)* addrspace(2)* %261, !tbaa !0
  %263 = getelementptr float addrspace(2)* %262, i32 0
  %264 = load float addrspace(2)* %263, !tbaa !0
  %265 = fmul float %264, %161
  %266 = getelementptr float addrspace(2)* %262, i32 1
  %267 = load float addrspace(2)* %266, !tbaa !0
  %268 = fmul float %267, %168
  %269 = fadd float %265, %268
  %270 = getelementptr float addrspace(2)* %262, i32 2
  %271 = load float addrspace(2)* %270, !tbaa !0
  %272 = fmul float %271, %175
  %273 = fadd float %269, %272
  %274 = getelementptr float addrspace(2)* %262, i32 3
  %275 = load float addrspace(2)* %274, !tbaa !0
  %276 = fmul float %275, %182
  %277 = fadd float %273, %276
  %278 = getelementptr float addrspace(2)* %262, i32 4
  %279 = load float addrspace(2)* %278, !tbaa !0
  %280 = fmul float %279, %161
  %281 = getelementptr float addrspace(2)* %262, i32 5
  %282 = load float addrspace(2)* %281, !tbaa !0
  %283 = fmul float %282, %168
  %284 = fadd float %280, %283
  %285 = getelementptr float addrspace(2)* %262, i32 6
  %286 = load float addrspace(2)* %285, !tbaa !0
  %287 = fmul float %286, %175
  %288 = fadd float %284, %287
  %289 = getelementptr float addrspace(2)* %262, i32 7
  %290 = load float addrspace(2)* %289, !tbaa !0
  %291 = fmul float %290, %182
  %292 = fadd float %288, %291
  %293 = getelementptr float addrspace(2)* %262, i32 8
  %294 = load float addrspace(2)* %293, !tbaa !0
  %295 = fmul float %294, %161
  %296 = getelementptr float addrspace(2)* %262, i32 9
  %297 = load float addrspace(2)* %296, !tbaa !0
  %298 = fmul float %297, %168
  %299 = fadd float %295, %298
  %300 = getelementptr float addrspace(2)* %262, i32 10
  %301 = load float addrspace(2)* %300, !tbaa !0
  %302 = fmul float %301, %175
  %303 = fadd float %299, %302
  %304 = getelementptr float addrspace(2)* %262, i32 11
  %305 = load float addrspace(2)* %304, !tbaa !0
  %306 = fmul float %305, %182
  %307 = fadd float %303, %306
  %308 = getelementptr float addrspace(2)* %262, i32 12
  %309 = load float addrspace(2)* %308, !tbaa !0
  %310 = fmul float %309, %161
  %311 = getelementptr float addrspace(2)* %262, i32 13
  %312 = load float addrspace(2)* %311, !tbaa !0
  %313 = fmul float %312, %168
  %314 = fadd float %310, %313
  %315 = getelementptr float addrspace(2)* %262, i32 14
  %316 = load float addrspace(2)* %315, !tbaa !0
  %317 = fmul float %316, %175
  %318 = fadd float %314, %317
  %319 = getelementptr float addrspace(2)* %262, i32 15
  %320 = load float addrspace(2)* %319, !tbaa !0
  %321 = fmul float %320, %182
  %322 = fadd float %318, %321
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %277, float %292, float %307, float %322)
  %323 = getelementptr float addrspace(2)* %262, i32 16
  %324 = load float addrspace(2)* %323, !tbaa !0
  %325 = fmul float %324, %161
  %326 = getelementptr float addrspace(2)* %262, i32 17
  %327 = load float addrspace(2)* %326, !tbaa !0
  %328 = fmul float %327, %168
  %329 = fadd float %325, %328
  %330 = getelementptr float addrspace(2)* %262, i32 18
  %331 = load float addrspace(2)* %330, !tbaa !0
  %332 = fmul float %331, %175
  %333 = fadd float %329, %332
  %334 = getelementptr float addrspace(2)* %262, i32 19
  %335 = load float addrspace(2)* %334, !tbaa !0
  %336 = fmul float %335, %182
  %337 = fadd float %333, %336
  %338 = getelementptr float addrspace(2)* %262, i32 20
  %339 = load float addrspace(2)* %338, !tbaa !0
  %340 = fmul float %339, %161
  %341 = getelementptr float addrspace(2)* %262, i32 21
  %342 = load float addrspace(2)* %341, !tbaa !0
  %343 = fmul float %342, %168
  %344 = fadd float %340, %343
  %345 = getelementptr float addrspace(2)* %262, i32 22
  %346 = load float addrspace(2)* %345, !tbaa !0
  %347 = fmul float %346, %175
  %348 = fadd float %344, %347
  %349 = getelementptr float addrspace(2)* %262, i32 23
  %350 = load float addrspace(2)* %349, !tbaa !0
  %351 = fmul float %350, %182
  %352 = fadd float %348, %351
  %353 = getelementptr float addrspace(2)* %262, i32 24
  %354 = load float addrspace(2)* %353, !tbaa !0
  %355 = fmul float %354, %161
  %356 = getelementptr float addrspace(2)* %262, i32 25
  %357 = load float addrspace(2)* %356, !tbaa !0
  %358 = fmul float %357, %168
  %359 = fadd float %355, %358
  %360 = getelementptr float addrspace(2)* %262, i32 26
  %361 = load float addrspace(2)* %360, !tbaa !0
  %362 = fmul float %361, %175
  %363 = fadd float %359, %362
  %364 = getelementptr float addrspace(2)* %262, i32 27
  %365 = load float addrspace(2)* %364, !tbaa !0
  %366 = fmul float %365, %182
  %367 = fadd float %363, %366
  %368 = getelementptr float addrspace(2)* %262, i32 28
  %369 = load float addrspace(2)* %368, !tbaa !0
  %370 = fmul float %369, %161
  %371 = getelementptr float addrspace(2)* %262, i32 29
  %372 = load float addrspace(2)* %371, !tbaa !0
  %373 = fmul float %372, %168
  %374 = fadd float %370, %373
  %375 = getelementptr float addrspace(2)* %262, i32 30
  %376 = load float addrspace(2)* %375, !tbaa !0
  %377 = fmul float %376, %175
  %378 = fadd float %374, %377
  %379 = getelementptr float addrspace(2)* %262, i32 31
  %380 = load float addrspace(2)* %379, !tbaa !0
  %381 = fmul float %380, %182
  %382 = fadd float %378, %381
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %337, float %352, float %367, float %382)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %102, float %103, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %140, float %147, float %154, float %189)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %209, float %224, float %194, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %214, float %231, float %199, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %219, float %238, float %204, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %225, float %226, float %232, float %233)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %239, float %240, float %102, float %103)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %254, float %256, float %251, float %182)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 191; mem:LD4[%57]
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR8, %VGPR1, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR2, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%87](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR5, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR9, %SGPR5, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 17; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 16; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR10, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 18; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR5<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 19; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 21; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 20; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 22; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 23; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%261](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%311]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%308]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 25; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 24; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 26; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 27; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%315]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 29; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 28; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 30; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 31; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%319]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%296]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%293]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%300]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%304]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%281]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%278]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%285]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%289]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%266]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%263]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%270]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%274]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%371]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%368]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%375]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%379]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%356]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%353]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%360]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%364]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%341]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%338]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%345]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%349]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%326]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%323]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%330]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%334]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%99](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 49; mem:LD4[%51]
	S_WAITCNT 15
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 48; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 50; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 51; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 201; mem:LD4[%77]
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR0, %VGPR6, %EXEC<imp-use>
	%SGPR1<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 200; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR5, %SGPR1, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 202; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR7, %SGPR4, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 203; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR8, %SGPR5<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR16<def> = V_MUL_F32_e32 %SGPR5, %VGPR6, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR5, %SGPR8, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 198; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR7, %SGPR9, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 199; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR8, %SGPR10<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR10, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR12<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR5<kill>, %SGPR12, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR11<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 194; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR7<kill>, %SGPR11, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR13<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 195; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR8<kill>, %SGPR13<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR5<kill>, %VGPR16<kill>, %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%93](tbaa=!"const")
	S_WAITCNT 15
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR14<def> = V_MUL_F32_e32 %SGPR12, %VGPR5, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR6, %SGPR10, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR7, %SGPR11, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 24; mem:LD16[%120](tbaa=!"const")
	S_WAITCNT 127
	%VGPR14_VGPR15_VGPR16_VGPR17<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %SGPR12, %VGPR14, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR15, %SGPR10, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR16, %SGPR11, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%114](tbaa=!"const")
	S_WAITCNT 127
	%VGPR18_VGPR19_VGPR20_VGPR21<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR24<def> = V_MUL_F32_e32 %SGPR12<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR19, %SGPR10<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR20, %SGPR11<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR24<kill>, %VGPR23<kill>, %VGPR22<kill>, %VGPR13, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR22<def> = V_MUL_F32_e32 %SGPR8, %VGPR5, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR6, %SGPR5, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR7, %SGPR9, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %SGPR8, %VGPR14, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR15, %SGPR5, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR16, %SGPR9, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR19, %SGPR5<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR20, %SGPR9<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 36, 0, 0, 0, %VGPR24<kill>, %VGPR23<kill>, %VGPR22<kill>, %VGPR13, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR22<def> = V_MUL_F32_e32 %SGPR1, %VGPR5, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR6, %SGPR0, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR7, %SGPR4, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR1, %VGPR14, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR15, %SGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR16, %SGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR19, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR20, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>
	EXP 15, 37, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%104](tbaa=!"const")
	S_WAITCNT 15
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 16; mem:LD16[%109](tbaa=!"const")
	S_WAITCNT 112
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR17<def> = V_ADD_F32_e32 %VGPR5, %VGPR13, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR17, %VGPR5, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e32 %VGPR6, %VGPR14, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR13, %VGPR6, %EXEC<imp-use>
	EXP 15, 38, 0, 0, 0, %VGPR17<kill>, %VGPR13<kill>, %VGPR14, %VGPR0, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR13<def> = V_ADD_F32_e32 %VGPR14<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR0<kill>, %VGPR5, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	EXP 15, 39, 0, 0, 0, %VGPR0<kill>, %VGPR13<kill>, %VGPR9, %VGPR10, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 204; mem:LD4[%83]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 205; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0410100
bf8c007f
c00403bf
c0020300
bf8c007f
7e040204
c0028301
bf8c007f
7e020205
d2820003
040a0208
d2060803
02010103
d2820004
04060408
d2060804
02010104
f800020f
03040404
c0840700
bf8c000f
e00c2000
80020800
bf8c0770
d2820005
04080b08
d2820006
04080b09
c0040311
bf8c007f
10060c08
c0040310
bf8c007f
d2820003
040c1105
d2820007
04080b0a
c0028312
bf8c007f
d2820002
040c0b07
d2820008
04040908
c0020313
bf8c007f
d2820001
04080908
c0020315
bf8c007f
10040c04
c0020314
bf8c007f
d2820002
04080905
c0020316
bf8c007f
d2820002
04080907
c0020317
bf8c007f
d2820002
04080908
c0400102
bf8c007f
c002010d
bf8c007f
10060404
c002010c
bf8c007f
d2820004
040e0204
c0020319
bf8c007f
10060c04
c0020318
bf8c007f
d2820003
040c0905
c002031a
bf8c007f
d2820003
040c0907
c002031b
bf8c007f
d2820003
040c0908
c002010e
bf8c007f
d2820009
04120604
c002031d
bf8c007f
10080c04
c002031c
bf8c007f
d2820004
04100905
c002031e
bf8c007f
d2820004
04100907
c002031f
bf8c007f
d2820004
04100908
c002010f
bf8c007f
d2820009
04260804
c0020109
bf8c007f
10140404
c0020108
bf8c007f
d282000a
042a0204
c002010a
bf8c007f
d282000a
042a0604
c002010b
bf8c007f
d282000a
042a0804
c0020105
bf8c007f
10160404
c0020104
bf8c007f
d282000b
042e0204
c0020106
bf8c007f
d282000b
042e0604
c0020107
bf8c007f
d282000b
042e0804
c0020101
bf8c007f
10180404
c0020100
bf8c007f
d282000c
04320204
c0020102
bf8c007f
d282000c
04320604
c0020103
bf8c007f
d282000c
04320804
f80000ef
090a0b0c
c002011d
bf8c000f
10120404
c002011c
bf8c007f
d2820009
04260204
c002011e
bf8c007f
d2820009
04260604
c002011f
bf8c007f
d2820009
04260804
c0020119
bf8c007f
10140404
c0020118
bf8c007f
d282000a
042a0204
c002011a
bf8c007f
d282000a
042a0604
c002011b
bf8c007f
d282000a
042a0804
c0020115
bf8c007f
10160404
c0020114
bf8c007f
d282000b
042e0204
c0020116
bf8c007f
d282000b
042e0604
c0020117
bf8c007f
d282000b
042e0804
c0020111
bf8c007f
10180404
c0020110
bf8c007f
d282000c
04320204
c0020112
bf8c007f
d282000c
04320604
c0000113
bf8c007f
d282000c
04320800
f80000ff
090a0b0c
c0840708
bf8c000f
e00c2000
80020900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c0000331
bf8c000f
101c0c00
c0000330
bf8c007f
d282000e
04380105
c0000332
bf8c007f
d282000e
04380107
c0000333
bf8c007f
d282000e
04380108
c00003c9
bf8c007f
101e0c00
c00083c8
bf8c007f
d282000f
043c0305
c00203ca
bf8c007f
d282000f
043c0907
c00283cb
bf8c007f
d282000f
043c0b08
c00283c5
bf8c007f
10200c05
c00403c4
bf8c007f
d2820010
04401105
c00483c6
bf8c007f
d2820010
04401307
c00503c7
bf8c007f
d2820010
04401508
c00503c1
bf8c007f
100c0c0a
c00603c0
bf8c007f
d2820005
04181905
c00583c2
bf8c007f
d2820005
04141707
c00683c3
bf8c007f
d2820005
04141b08
f800022f
0e0f1005
c0880704
bf8c000f
e00c2000
80040500
bf8c0770
101c0a0c
d282000e
04381506
d2820016
04381707
c0880718
bf8c007f
e00c2000
80040e00
bf8c0770
10241c0c
d2820012
0448150f
d2820017
04481710
c0880714
bf8c007f
e00c2000
80041200
bf8c0770
1030240c
d2820018
04601513
d2820018
04601714
f800023f
0d161718
bf8c070f
102c0a08
d2820016
04580b06
d2820016
04581307
102e1c08
d2820017
045c0b0f
d2820017
045c1310
10302408
d2820018
04600b13
d2820018
04601314
f800024f
0d161718
bf8c070f
102c0a01
d2820016
04580106
d2820005
04580907
100c1c01
d2820006
0418010f
d2820006
04180910
100e2401
d2820007
041c0113
d2820007
041c0914
f800025f
0d050607
c084070c
bf8c000f
e00c2000
80020d00
c0820710
bf8c0070
e00c2000
80010500
bf8c0770
06221b05
06000b11
061a1d06
061c0d0d
f800026f
000e0d11
bf8c070f
061a0d0e
06000b00
f800027f
0a090d00
c00003cc
bf8c000f
d2820000
04060800
c0000302
bf8c007f
10020600
08020901
c00003cd
bf8c007f
10060800
08040503
f80008cf
04010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE
DCL IN[4], GENERIC[22], PERSPECTIVE
DCL IN[5], GENERIC[23], PERSPECTIVE
DCL IN[6], GENERIC[24], PERSPECTIVE, CENTROID
DCL IN[7], GENERIC[25], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..30]
DCL TEMP[0..9], LOCAL
DCL TEMP[10], ARRAY(1), LOCAL
IMM[0] FLT32 {    2.0000,    -1.0000,     1.0000,    -0.7071}
IMM[1] FLT32 {    0.8165,     0.0000,     0.5774,    -0.4082}
IMM[2] FLT32 {   -0.4082,     0.7071,     0.5774,    -0.4082}
IMM[3] FLT32 {   -0.4082,    -0.7071,     0.5774,     0.0000}
  0: MOV TEMP[0].xy, IN[7].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[1], 2D
  2: MOV TEMP[1].xy, IN[6].xyyy
  3: TEX TEMP[1].xyz, TEMP[1], SAMP[1], 2D
  4: MOV TEMP[2].xy, IN[1].xyyy
  5: TEX TEMP[2].xyz, TEMP[2], SAMP[3], 2D
  6: MAD TEMP[3].xyz, IMM[0].xxxx, TEMP[2].xyzz, IMM[0].yyyy
  7: DP3 TEMP[2].x, TEMP[3].xyzz, IN[3].xyzz
  8: DP3 TEMP[4].x, TEMP[3].xyzz, IN[4].xyzz
  9: MOV TEMP[2].y, TEMP[4].xxxx
 10: DP3 TEMP[4].x, TEMP[3].xyzz, IN[5].xyzz
 11: MOV TEMP[2].z, TEMP[4].xxxx
 12: ADD TEMP[4].xyz, -IN[2].xyzz, CONST[10].xyzz
 13: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[4].xyzz
 14: DP3 TEMP[6].x, TEMP[2].xyzz, TEMP[2].xyzz
 15: ADD TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx
 16: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[6].xxxx
 17: MAD TEMP[2].xyz, TEMP[5].xxxx, TEMP[2].xyzz, -TEMP[4].xyzz
 18: MOV TEMP[5].xy, IN[6].wzzz
 19: TEX TEMP[5].xyz, TEMP[5], SAMP[1], 2D
 20: MOV TEMP[6].xyz, TEMP[2].xyzz
 21: TEX TEMP[6].xyz, TEMP[6], SAMP[2], CUBE
 22: MOV TEMP[7].xy, IN[1].xyyy
 23: TEX TEMP[7].xyz, TEMP[7], SAMP[0], 2D
 24: DP3 TEMP[8].x, TEMP[3].xyzz, IMM[1].xyzz
 25: MOV_SAT TEMP[8].x, TEMP[8].xxxx
 26: DP3 TEMP[9].x, TEMP[3].xyzz, IMM[2].xyzz
 27: MOV_SAT TEMP[9].x, TEMP[9].xxxx
 28: MOV TEMP[8].y, TEMP[9].xxxx
 29: DP3 TEMP[9].x, TEMP[3].xyzz, IMM[3].xyzz
 30: MOV_SAT TEMP[9].x, TEMP[9].xxxx
 31: MOV TEMP[8].z, TEMP[9].xxxx
 32: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[8].xyzz
 33: MUL TEMP[3].xyz, TEMP[5].xyzz, TEMP[8].yyyy
 34: MAD TEMP[1].xyz, TEMP[8].xxxx, TEMP[1].xyzz, TEMP[3].xyzz
 35: DP3 TEMP[3].x, TEMP[8].xyzz, IMM[0].zzzz
 36: MAD TEMP[0].xyz, TEMP[8].zzzz, TEMP[0].xyzz, TEMP[1].xyzz
 37: RCP TEMP[3].x, TEMP[3].xxxx
 38: MUL TEMP[1].xyz, TEMP[3].xxxx, CONST[12].xyzz
 39: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xyzz
 40: MUL TEMP[4].xyz, TEMP[6].xyzz, CONST[30].zzzz
 41: MUL TEMP[4].xyz, TEMP[4].xyzz, CONST[0].xyzz
 42: MUL TEMP[2].xyz, TEMP[7].xyzz, IN[0].xyzz
 43: MAD TEMP[1].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
 44: MAD TEMP[2].xyz, TEMP[2].xyzz, TEMP[0].xyzz, TEMP[4].xyzz
 45: MIN TEMP[0].x, TEMP[1].xxxx, CONST[11].zzzz
 46: MOV_SAT TEMP[0].x, TEMP[0].xxxx
 47: MAD TEMP[4].xyz, TEMP[2].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 48: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx
 49: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[0].xxxx
 50: MAD TEMP[2].xyz, TEMP[2].xyzz, CONST[30].xxxx, TEMP[4].xyzz
 51: MUL TEMP[0].x, IN[2].wwww, CONST[29].wwww
 52: MOV TEMP[2].w, TEMP[0].xxxx
 53: MOV TEMP[10], TEMP[2]
 54: MOV OUT[0], TEMP[10]
 55: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 0
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 1
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 2
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 40
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 41
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 42
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 44
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 46
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 47
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 48
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 49
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr float addrspace(2)* %21, i32 50
  %45 = load float addrspace(2)* %44, !tbaa !0
  %46 = getelementptr float addrspace(2)* %21, i32 116
  %47 = load float addrspace(2)* %46, !tbaa !0
  %48 = getelementptr float addrspace(2)* %21, i32 117
  %49 = load float addrspace(2)* %48, !tbaa !0
  %50 = getelementptr float addrspace(2)* %21, i32 118
  %51 = load float addrspace(2)* %50, !tbaa !0
  %52 = getelementptr float addrspace(2)* %21, i32 119
  %53 = load float addrspace(2)* %52, !tbaa !0
  %54 = getelementptr float addrspace(2)* %21, i32 120
  %55 = load float addrspace(2)* %54, !tbaa !0
  %56 = getelementptr float addrspace(2)* %21, i32 122
  %57 = load float addrspace(2)* %56, !tbaa !0
  %58 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %59 = load <32 x i8> addrspace(2)* %58, !tbaa !0
  %60 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
  %62 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %63 = load <32 x i8> addrspace(2)* %62, !tbaa !0
  %64 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
  %66 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %67 = load <32 x i8> addrspace(2)* %66, !tbaa !0
  %68 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
  %70 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %71 = load <32 x i8> addrspace(2)* %70, !tbaa !0
  %72 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %73 = load <16 x i8> addrspace(2)* %72, !tbaa !0
  %74 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %75 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %76 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %77 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %78 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %79 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %80 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %81 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %82 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %83 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
  %84 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
  %85 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %86 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
  %87 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
  %88 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
  %89 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
  %90 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
  %91 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
  %92 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %6)
  %93 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %6)
  %94 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %3, <2 x i32> %6)
  %95 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %3, <2 x i32> %6)
  %96 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %3, <2 x i32> %6)
  %97 = call float @llvm.SI.fs.interp(i32 1, i32 7, i32 %3, <2 x i32> %6)
  %98 = bitcast float %96 to i32
  %99 = bitcast float %97 to i32
  %100 = insertelement <2 x i32> undef, i32 %98, i32 0
  %101 = insertelement <2 x i32> %100, i32 %99, i32 1
  %102 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %101, <32 x i8> %63, <16 x i8> %65, i32 2)
  %103 = extractelement <4 x float> %102, i32 0
  %104 = extractelement <4 x float> %102, i32 1
  %105 = extractelement <4 x float> %102, i32 2
  %106 = bitcast float %92 to i32
  %107 = bitcast float %93 to i32
  %108 = insertelement <2 x i32> undef, i32 %106, i32 0
  %109 = insertelement <2 x i32> %108, i32 %107, i32 1
  %110 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %109, <32 x i8> %63, <16 x i8> %65, i32 2)
  %111 = extractelement <4 x float> %110, i32 0
  %112 = extractelement <4 x float> %110, i32 1
  %113 = extractelement <4 x float> %110, i32 2
  %114 = bitcast float %77 to i32
  %115 = bitcast float %78 to i32
  %116 = insertelement <2 x i32> undef, i32 %114, i32 0
  %117 = insertelement <2 x i32> %116, i32 %115, i32 1
  %118 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %117, <32 x i8> %71, <16 x i8> %73, i32 2)
  %119 = extractelement <4 x float> %118, i32 0
  %120 = extractelement <4 x float> %118, i32 1
  %121 = extractelement <4 x float> %118, i32 2
  %122 = fmul float 2.000000e+00, %119
  %123 = fadd float %122, -1.000000e+00
  %124 = fmul float 2.000000e+00, %120
  %125 = fadd float %124, -1.000000e+00
  %126 = fmul float 2.000000e+00, %121
  %127 = fadd float %126, -1.000000e+00
  %128 = fmul float %123, %83
  %129 = fmul float %125, %84
  %130 = fadd float %129, %128
  %131 = fmul float %127, %85
  %132 = fadd float %130, %131
  %133 = fmul float %123, %86
  %134 = fmul float %125, %87
  %135 = fadd float %134, %133
  %136 = fmul float %127, %88
  %137 = fadd float %135, %136
  %138 = fmul float %123, %89
  %139 = fmul float %125, %90
  %140 = fadd float %139, %138
  %141 = fmul float %127, %91
  %142 = fadd float %140, %141
  %143 = fsub float -0.000000e+00, %79
  %144 = fadd float %143, %29
  %145 = fsub float -0.000000e+00, %80
  %146 = fadd float %145, %31
  %147 = fsub float -0.000000e+00, %81
  %148 = fadd float %147, %33
  %149 = fmul float %132, %144
  %150 = fmul float %137, %146
  %151 = fadd float %150, %149
  %152 = fmul float %142, %148
  %153 = fadd float %151, %152
  %154 = fmul float %132, %132
  %155 = fmul float %137, %137
  %156 = fadd float %155, %154
  %157 = fmul float %142, %142
  %158 = fadd float %156, %157
  %159 = fadd float %153, %153
  %160 = fmul float %144, %158
  %161 = fmul float %146, %158
  %162 = fmul float %148, %158
  %163 = fsub float -0.000000e+00, %160
  %164 = fmul float %159, %132
  %165 = fadd float %164, %163
  %166 = fsub float -0.000000e+00, %161
  %167 = fmul float %159, %137
  %168 = fadd float %167, %166
  %169 = fsub float -0.000000e+00, %162
  %170 = fmul float %159, %142
  %171 = fadd float %170, %169
  %172 = bitcast float %95 to i32
  %173 = bitcast float %94 to i32
  %174 = insertelement <2 x i32> undef, i32 %172, i32 0
  %175 = insertelement <2 x i32> %174, i32 %173, i32 1
  %176 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %175, <32 x i8> %63, <16 x i8> %65, i32 2)
  %177 = extractelement <4 x float> %176, i32 0
  %178 = extractelement <4 x float> %176, i32 1
  %179 = extractelement <4 x float> %176, i32 2
  %180 = insertelement <4 x float> undef, float %165, i32 0
  %181 = insertelement <4 x float> %180, float %168, i32 1
  %182 = insertelement <4 x float> %181, float %171, i32 2
  %183 = insertelement <4 x float> %182, float 0.000000e+00, i32 3
  %184 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %183)
  %185 = extractelement <4 x float> %184, i32 0
  %186 = extractelement <4 x float> %184, i32 1
  %187 = extractelement <4 x float> %184, i32 2
  %188 = extractelement <4 x float> %184, i32 3
  %189 = call float @fabs(float %187)
  %190 = fdiv float 1.000000e+00, %189
  %191 = fmul float %185, %190
  %192 = fadd float %191, 1.500000e+00
  %193 = fmul float %186, %190
  %194 = fadd float %193, 1.500000e+00
  %195 = bitcast float %194 to i32
  %196 = bitcast float %192 to i32
  %197 = bitcast float %188 to i32
  %198 = insertelement <4 x i32> undef, i32 %195, i32 0
  %199 = insertelement <4 x i32> %198, i32 %196, i32 1
  %200 = insertelement <4 x i32> %199, i32 %197, i32 2
  %201 = insertelement <4 x i32> %200, i32 undef, i32 3
  %202 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %201, <32 x i8> %67, <16 x i8> %69, i32 4)
  %203 = extractelement <4 x float> %202, i32 0
  %204 = extractelement <4 x float> %202, i32 1
  %205 = extractelement <4 x float> %202, i32 2
  %206 = bitcast float %77 to i32
  %207 = bitcast float %78 to i32
  %208 = insertelement <2 x i32> undef, i32 %206, i32 0
  %209 = insertelement <2 x i32> %208, i32 %207, i32 1
  %210 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %209, <32 x i8> %59, <16 x i8> %61, i32 2)
  %211 = extractelement <4 x float> %210, i32 0
  %212 = extractelement <4 x float> %210, i32 1
  %213 = extractelement <4 x float> %210, i32 2
  %214 = fmul float %123, 0x3FEA20BD80000000
  %215 = fmul float %125, 0.000000e+00
  %216 = fadd float %215, %214
  %217 = fmul float %127, 0x3FE279A740000000
  %218 = fadd float %216, %217
  %219 = call float @llvm.AMDIL.clamp.(float %218, float 0.000000e+00, float 1.000000e+00)
  %220 = fmul float %123, 0xBFDA20BDA0000000
  %221 = fmul float %125, 0x3FE6A09E60000000
  %222 = fadd float %221, %220
  %223 = fmul float %127, 0x3FE279A740000000
  %224 = fadd float %222, %223
  %225 = call float @llvm.AMDIL.clamp.(float %224, float 0.000000e+00, float 1.000000e+00)
  %226 = fmul float %123, 0xBFDA20BD20000000
  %227 = fmul float %125, 0xBFE6A09E80000000
  %228 = fadd float %227, %226
  %229 = fmul float %127, 0x3FE279A740000000
  %230 = fadd float %228, %229
  %231 = call float @llvm.AMDIL.clamp.(float %230, float 0.000000e+00, float 1.000000e+00)
  %232 = fmul float %219, %219
  %233 = fmul float %225, %225
  %234 = fmul float %231, %231
  %235 = fmul float %177, %233
  %236 = fmul float %178, %233
  %237 = fmul float %179, %233
  %238 = fmul float %232, %111
  %239 = fadd float %238, %235
  %240 = fmul float %232, %112
  %241 = fadd float %240, %236
  %242 = fmul float %232, %113
  %243 = fadd float %242, %237
  %244 = fmul float %232, 1.000000e+00
  %245 = fmul float %233, 1.000000e+00
  %246 = fadd float %245, %244
  %247 = fmul float %234, 1.000000e+00
  %248 = fadd float %246, %247
  %249 = fmul float %234, %103
  %250 = fadd float %249, %239
  %251 = fmul float %234, %104
  %252 = fadd float %251, %241
  %253 = fmul float %234, %105
  %254 = fadd float %253, %243
  %255 = fdiv float 1.000000e+00, %248
  %256 = fmul float %255, %41
  %257 = fmul float %255, %43
  %258 = fmul float %255, %45
  %259 = fmul float %250, %256
  %260 = fmul float %252, %257
  %261 = fmul float %254, %258
  %262 = fmul float %203, %57
  %263 = fmul float %204, %57
  %264 = fmul float %205, %57
  %265 = fmul float %262, %23
  %266 = fmul float %263, %25
  %267 = fmul float %264, %27
  %268 = fmul float %211, %74
  %269 = fmul float %212, %75
  %270 = fmul float %213, %76
  %271 = fsub float -0.000000e+00, %35
  %272 = fmul float %82, %39
  %273 = fadd float %272, %271
  %274 = fmul float %268, %259
  %275 = fadd float %274, %265
  %276 = fmul float %269, %260
  %277 = fadd float %276, %266
  %278 = fmul float %270, %261
  %279 = fadd float %278, %267
  %280 = fcmp uge float %273, %37
  %281 = select i1 %280, float %37, float %273
  %282 = call float @llvm.AMDIL.clamp.(float %281, float 0.000000e+00, float 1.000000e+00)
  %283 = fsub float -0.000000e+00, %55
  %284 = fmul float %275, %283
  %285 = fadd float %284, %47
  %286 = fsub float -0.000000e+00, %55
  %287 = fmul float %277, %286
  %288 = fadd float %287, %49
  %289 = fsub float -0.000000e+00, %55
  %290 = fmul float %279, %289
  %291 = fadd float %290, %51
  %292 = fmul float %282, %282
  %293 = fmul float %285, %292
  %294 = fmul float %288, %292
  %295 = fmul float %291, %292
  %296 = fmul float %275, %55
  %297 = fadd float %296, %293
  %298 = fmul float %277, %55
  %299 = fadd float %298, %294
  %300 = fmul float %279, %55
  %301 = fadd float %300, %295
  %302 = fmul float %82, %53
  %303 = call i32 @llvm.SI.packf16(float %297, float %299)
  %304 = bitcast i32 %303 to float
  %305 = call i32 @llvm.SI.packf16(float %301, float %302)
  %306 = bitcast i32 %305 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %304, float %306, float %304, float %306)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 12; mem:LD16[%72](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 24; mem:LD32[%70](tbaa=!"const")
	S_WAITCNT 127
	%VGPR8_VGPR9_VGPR10<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_ADD_F32_e32 %VGPR8, %VGPR8, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR6, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e32 %VGPR9, %VGPR9, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR7, %VGPR12<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e32 %VGPR10, %VGPR10, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10<imp-use,kill>
	%VGPR8<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR8, %VGPR9<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR6, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR7, %VGPR11<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR8, %VGPR11<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR10, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR9, %VGPR9, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR6, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR7, %VGPR13<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR8, %VGPR13<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 41; mem:LD4[%30]
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR7<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR15, %VGPR12, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 40; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR14<def> = V_SUB_F32_e32 %SGPR7<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR10, %VGPR14, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR9, %VGPR15<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 42; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR7<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR11, %VGPR15, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e32 %VGPR16<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR16, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %VGPR9<kill>, %VGPR13<kill>, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR16, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR20<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR10<def> = V_CUBESC_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR9<def> = V_CUBETC_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR11<def> = V_CUBEMA_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR12<def> = V_CUBEID_F32 %VGPR17, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR17<def> = V_ADD_F32_e64 %VGPR11, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_RCP_F32_e32 %VGPR17<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR9, %VGPR17, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR10<def> = V_MAD_F32 %VGPR10, %VGPR17<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR13<def> = KILL %VGPR13<undef>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%68](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%66](tbaa=!"const")
	S_WAITCNT 127
	%VGPR9_VGPR10_VGPR11<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR10_VGPR11_VGPR12_VGPR13, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 122; mem:LD4[%56]
	S_WAITCNT 112
	%VGPR12<def> = V_MUL_F32_e32 %SGPR7, %VGPR10, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%24]
	S_WAITCNT 127
	%VGPR20<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 -4.082483e-01, %VGPR6, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 7.071068e-01, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR7, %VGPR13<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_MOV_B32_e32 5.773503e-01, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR8, %VGPR21, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 %VGPR12<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR24, %VGPR24, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR2, 2, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<tied0>, %VGPR3, 2, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR2, 3, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<tied0>, %VGPR3, 3, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%64](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%62](tbaa=!"const")
	S_WAITCNT 127
	%VGPR13_VGPR14_VGPR15<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR22<def> = V_MUL_F32_e32 %VGPR14, %VGPR12, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 8.164966e-01, %VGPR6, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR7, 0.000000e+00, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR8, %VGPR21, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e64 %VGPR16<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR18<def> = V_INTERP_P1_F32 %VGPR2, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR17_VGPR18<imp-def>
	%VGPR18<def,tied1> = V_INTERP_P2_F32 %VGPR18<tied0>, %VGPR3, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR17_VGPR18<imp-use,kill>, %VGPR17_VGPR18<imp-def>
	%VGPR17<def> = V_INTERP_P1_F32 %VGPR2, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR17_VGPR18<imp-use,kill>, %VGPR17_VGPR18<imp-def>
	%VGPR17<def,tied1> = V_INTERP_P2_F32 %VGPR17<tied0>, %VGPR3, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR17_VGPR18<imp-use,kill>, %VGPR17_VGPR18<imp-def>
	%VGPR17_VGPR18_VGPR19<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR17_VGPR18<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR25<def> = V_MAD_F32 %VGPR16, %VGPR18, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 -4.082482e-01, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MOV_B32_e32 -7.071068e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR7<kill>, %VGPR22<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR8<kill>, %VGPR21<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR6<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR7, %VGPR7, %EXEC<imp-use>
	%VGPR22<def> = V_INTERP_P1_F32 %VGPR2, 1, 7, %M0<kill>, %EXEC<imp-use>, %VGPR21_VGPR22<imp-def>
	%VGPR22<def,tied1> = V_INTERP_P2_F32 %VGPR22<tied0>, %VGPR3, 1, 7, %M0<kill>, %EXEC<imp-use>, %VGPR21_VGPR22<imp-use,kill>, %VGPR21_VGPR22<imp-def>
	%VGPR21<def> = V_INTERP_P1_F32 %VGPR2, 0, 7, %M0<kill>, %EXEC<imp-use>, %VGPR21_VGPR22<imp-use,kill>, %VGPR21_VGPR22<imp-def>
	%VGPR21<def,tied1> = V_INTERP_P2_F32 %VGPR21<tied0>, %VGPR3, 0, 7, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR21_VGPR22<imp-use,kill>, %VGPR21_VGPR22<imp-def>
	%VGPR21_VGPR22_VGPR23<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR21_VGPR22<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %VGPR22, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR24<kill>, %VGPR24, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR7<kill>, %VGPR7, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_RCP_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 49; mem:LD4[%42]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%60](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%58](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MUL_F32_e32 %VGPR3, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR5<kill>, %VGPR8<kill>, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%54]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR2, %VGPR20, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%48]
	S_WAITCNT 127
	%VGPR24<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 47; mem:LD4[%38]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 44; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR8<def> = V_SUBREV_F32_e32 %SGPR3<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 46; mem:LD4[%36]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR8, %SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR25<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR20<kill>, %SGPR2, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR7, %VGPR9, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR24<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR13, %VGPR12, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR16, %VGPR17, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR6, %VGPR21, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR26<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR26<def,tied1> = V_INTERP_P2_F32 %VGPR26<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR2, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR26<kill>, %VGPR25<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %SGPR2, %VGPR24, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 116; mem:LD4[%46]
	S_WAITCNT 127
	%VGPR25<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR24<kill>, %SGPR2, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR24<kill>, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR11, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR15, %VGPR12<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15<imp-use,kill>
	%VGPR10<def> = V_MAD_F32 %VGPR16<kill>, %VGPR19, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19<imp-use,kill>
	%VGPR6<def> = V_MAD_F32 %VGPR6<kill>, %VGPR23, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23<imp-use,kill>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%44]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR4, %VGPR7<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4<imp-use,kill>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %VGPR6<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2, %VGPR0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 118; mem:LD4[%50]
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 119; mem:LD4[%52]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR20<kill>, %VGPR0<kill>, %VGPR20, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140500
c8150501
c8100400
c8110401
c084030c
c0c60518
bf8c007f
f0800700
00430804
bf8c0770
060c1108
060c0cf3
c81c1000
c81d1001
10160f06
060e1309
060e0ef3
c8301100
c8311101
d282000b
042e1907
0610150a
061010f3
c8241200
c8251201
d2820009
042e1308
c8280c00
c8290c01
10141506
c82c0d00
c82d0d01
d282000a
042a1707
c82c0e00
c82d0e01
d282000a
042a1708
1016150a
d282000c
042e1309
c82c1400
c82d1401
10161706
c8341500
c8351501
d282000b
042e1b07
c8341600
c8351601
d282000b
042e1b08
d282000c
0432170b
c8340900
c8350901
c0400100
bf8c007f
c0038129
bf8c007f
081e1a07
101a190f
c8380800
c8390801
c0038128
bf8c007f
081c1c07
10201d0a
d2820010
04421f09
c83c0a00
c83d0a01
c003812a
bf8c007f
081e1e07
d2820010
04421f0b
06202110
10121310
08241b09
1012190e
10141510
0822130a
1012190f
10141710
0826130a
7e280280
d28a000a
044e2511
d28c0009
044e2511
d28e000b
044e2511
d288000c
044e2511
d2060111
0201010b
7e225511
7e2402ff
3fc00000
d282000b
044a2309
d282000a
044a230a
c0840308
c0c60510
bf8c007f
f0800700
0043090a
c003817a
bf8c0070
10181407
c0040101
bf8c007f
10281808
10180cff
bed105ed
7e1a02ff
3f3504f3
d282000c
04321b07
7e2a02ff
3f13cd3a
d282000c
04322b08
d2060818
0201010c
10183118
c8381a02
c8391a03
c8341b02
c8351b03
c0840304
c0c60508
bf8c007f
f0800700
00430d0d
bf8c0770
102c190e
10200cff
3f5105ec
d2820010
04410107
d2820010
04422b08
d2060810
02010110
10202110
c8481902
c8491903
c8441802
c8451803
f0800700
00431111
bf8c0770
d2820019
045a2510
100c0cff
bed105e9
7e2c02ff
bf3504f4
d2820006
041a2d07
d2820006
041a2b08
d2060807
02010106
100c0f07
c8581d02
c8591d03
c8541c02
c8551c03
f0800700
00431515
bf8c0770
d2820002
04662d06
d2820003
04423118
d2820003
040e0f07
7e0e5503
c0040131
bf8c007f
10060e08
10100702
c0840300
c0c60500
bf8c007f
f0800700
00430204
c8140100
c8150101
bf8c0770
100a0b03
d2820014
04521105
c0010178
bf8c007f
100a2802
c0018175
bf8c007f
08300a03
c8140b00
c8150b01
c001812f
bf8c007f
10100a03
c001812c
bf8c007f
0a101003
c001812e
bf8c007f
d00c0004
02000708
7e320203
d2000008
00123308
d2060808
02010108
10101108
10301118
d2820014
04600514
10301207
c0018100
bf8c007f
10303003
1032190d
d2820019
04662310
d2820019
04662b06
c0018130
bf8c007f
10340e03
10323519
c8680000
c8690001
10343502
d2820018
0462331a
10323002
c0018174
bf8c007f
08323203
10321119
d2820018
04640518
5e282918
10121607
c0018102
bf8c007f
10121203
1014190f
d282000a
042a2710
d2820006
042a2f06
c0018132
bf8c007f
100e0e03
100c0f06
c81c0200
c81d0201
10000f04
d2820000
04260d00
10020002
c0018176
bf8c007f
08020203
10021101
d2820000
04040500
c0000177
bf8c007f
10020a00
5e000300
f8001c0f
00140014
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL OUT[7], GENERIC[23]
DCL OUT[8], GENERIC[24]
DCL OUT[9], GENERIC[25]
DCL CONST[0..51]
DCL TEMP[0..12], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[6]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: DP4 TEMP[5].x, TEMP[0], CONST[7]
 12: MOV TEMP[2].w, TEMP[5].xxxx
 13: DP4 TEMP[6].x, TEMP[0], CONST[12]
 14: DP3 TEMP[7].x, IN[1].xyzz, CONST[48].xyzz
 15: MOV TEMP[7].z, TEMP[7].xxxx
 16: DP3 TEMP[8].x, IN[1].xyzz, CONST[49].xyzz
 17: MOV TEMP[8].z, TEMP[8].xxxx
 18: DP3 TEMP[9].x, IN[1].xyzz, CONST[50].xyzz
 19: MOV TEMP[9].z, TEMP[9].xxxx
 20: DP3 TEMP[7].x, IN[5].xyzz, CONST[48].xyzz
 21: DP3 TEMP[8].x, IN[5].xyzz, CONST[49].xyzz
 22: DP3 TEMP[9].x, IN[5].xyzz, CONST[50].xyzz
 23: DP3 TEMP[10].x, IN[6].xyzz, CONST[48].xyzz
 24: MOV TEMP[7].y, TEMP[10].xxxx
 25: ADD TEMP[0].xy, IN[4].xyyy, IN[3].xyyy
 26: DP3 TEMP[10].x, IN[6].xyzz, CONST[49].xyzz
 27: MOV TEMP[8].y, TEMP[10].xxxx
 28: ADD TEMP[10].xy, TEMP[0].yxxx, IN[4].yxxx
 29: MOV TEMP[0].zw, TEMP[10].yyxy
 30: DP3 TEMP[11].x, IN[6].xyzz, CONST[50].xyzz
 31: MOV TEMP[9].y, TEMP[11].xxxx
 32: MOV TEMP[0], TEMP[0]
 33: ADD TEMP[10].xy, TEMP[10].yxxx, IN[4].xyyy
 34: MOV TEMP[1].w, TEMP[6].xxxx
 35: MOV TEMP[6].xy, IN[2].xyxx
 36: MOV TEMP[10].zw, IN[2].yyxy
 37: MAD TEMP[11], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 38: MOV TEMP[12], TEMP[2]
 39: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[5].xxxx
 40: MOV TEMP[2].z, TEMP[4].xxxx
 41: MOV TEMP[2].y, -TEMP[3].xxxx
 42: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[5].xxxx, TEMP[2].xyyy
 43: MOV OUT[3], TEMP[6]
 44: MOV OUT[8], TEMP[0]
 45: MOV OUT[9], TEMP[10]
 46: MOV OUT[0], TEMP[2]
 47: MOV OUT[4], TEMP[1]
 48: MOV OUT[2], TEMP[12]
 49: MOV OUT[5], TEMP[7]
 50: MOV OUT[6], TEMP[8]
 51: MOV_SAT OUT[1], TEMP[11]
 52: MOV OUT[7], TEMP[9]
 53: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 16
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 17
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 18
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 19
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 20
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 21
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 22
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 23
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 24
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 25
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 26
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 27
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 28
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 29
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 30
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 31
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 48
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 49
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 50
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 51
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 191
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 192
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 193
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 194
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 195
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 196
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 197
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 198
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 199
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 200
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 201
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 202
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 203
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 204
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 205
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %5)
  %90 = extractelement <4 x float> %89, i32 0
  %91 = extractelement <4 x float> %89, i32 1
  %92 = extractelement <4 x float> %89, i32 2
  %93 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %94 = load <16 x i8> addrspace(2)* %93, !tbaa !0
  %95 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %94, i32 0, i32 %5)
  %96 = extractelement <4 x float> %95, i32 0
  %97 = extractelement <4 x float> %95, i32 1
  %98 = extractelement <4 x float> %95, i32 2
  %99 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %100 = load <16 x i8> addrspace(2)* %99, !tbaa !0
  %101 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %100, i32 0, i32 %5)
  %102 = extractelement <4 x float> %101, i32 0
  %103 = extractelement <4 x float> %101, i32 1
  %104 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %105 = load <16 x i8> addrspace(2)* %104, !tbaa !0
  %106 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %105, i32 0, i32 %5)
  %107 = extractelement <4 x float> %106, i32 0
  %108 = extractelement <4 x float> %106, i32 1
  %109 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %110 = load <16 x i8> addrspace(2)* %109, !tbaa !0
  %111 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %110, i32 0, i32 %5)
  %112 = extractelement <4 x float> %111, i32 0
  %113 = extractelement <4 x float> %111, i32 1
  %114 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
  %115 = load <16 x i8> addrspace(2)* %114, !tbaa !0
  %116 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %115, i32 0, i32 %5)
  %117 = extractelement <4 x float> %116, i32 0
  %118 = extractelement <4 x float> %116, i32 1
  %119 = extractelement <4 x float> %116, i32 2
  %120 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
  %121 = load <16 x i8> addrspace(2)* %120, !tbaa !0
  %122 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %121, i32 0, i32 %5)
  %123 = extractelement <4 x float> %122, i32 0
  %124 = extractelement <4 x float> %122, i32 1
  %125 = extractelement <4 x float> %122, i32 2
  %126 = fmul float %90, %14
  %127 = fadd float %126, %12
  %128 = fmul float %91, %14
  %129 = fadd float %128, %12
  %130 = fmul float %92, %14
  %131 = fadd float %130, %12
  %132 = fmul float %90, %12
  %133 = fadd float %132, %14
  %134 = fmul float %127, %60
  %135 = fmul float %129, %62
  %136 = fadd float %134, %135
  %137 = fmul float %131, %64
  %138 = fadd float %136, %137
  %139 = fmul float %133, %66
  %140 = fadd float %138, %139
  %141 = fmul float %127, %68
  %142 = fmul float %129, %70
  %143 = fadd float %141, %142
  %144 = fmul float %131, %72
  %145 = fadd float %143, %144
  %146 = fmul float %133, %74
  %147 = fadd float %145, %146
  %148 = fmul float %127, %76
  %149 = fmul float %129, %78
  %150 = fadd float %148, %149
  %151 = fmul float %131, %80
  %152 = fadd float %150, %151
  %153 = fmul float %133, %82
  %154 = fadd float %152, %153
  %155 = fmul float %127, %18
  %156 = fmul float %129, %20
  %157 = fadd float %155, %156
  %158 = fmul float %131, %22
  %159 = fadd float %157, %158
  %160 = fmul float %133, %24
  %161 = fadd float %159, %160
  %162 = fmul float %127, %26
  %163 = fmul float %129, %28
  %164 = fadd float %162, %163
  %165 = fmul float %131, %30
  %166 = fadd float %164, %165
  %167 = fmul float %133, %32
  %168 = fadd float %166, %167
  %169 = fmul float %127, %34
  %170 = fmul float %129, %36
  %171 = fadd float %169, %170
  %172 = fmul float %131, %38
  %173 = fadd float %171, %172
  %174 = fmul float %133, %40
  %175 = fadd float %173, %174
  %176 = fmul float %127, %42
  %177 = fmul float %129, %44
  %178 = fadd float %176, %177
  %179 = fmul float %131, %46
  %180 = fadd float %178, %179
  %181 = fmul float %133, %48
  %182 = fadd float %180, %181
  %183 = fmul float %127, %50
  %184 = fmul float %129, %52
  %185 = fadd float %183, %184
  %186 = fmul float %131, %54
  %187 = fadd float %185, %186
  %188 = fmul float %133, %56
  %189 = fadd float %187, %188
  %190 = fmul float %96, %60
  %191 = fmul float %97, %62
  %192 = fadd float %191, %190
  %193 = fmul float %98, %64
  %194 = fadd float %192, %193
  %195 = fmul float %96, %68
  %196 = fmul float %97, %70
  %197 = fadd float %196, %195
  %198 = fmul float %98, %72
  %199 = fadd float %197, %198
  %200 = fmul float %96, %76
  %201 = fmul float %97, %78
  %202 = fadd float %201, %200
  %203 = fmul float %98, %80
  %204 = fadd float %202, %203
  %205 = fmul float %117, %60
  %206 = fmul float %118, %62
  %207 = fadd float %206, %205
  %208 = fmul float %119, %64
  %209 = fadd float %207, %208
  %210 = fmul float %117, %68
  %211 = fmul float %118, %70
  %212 = fadd float %211, %210
  %213 = fmul float %119, %72
  %214 = fadd float %212, %213
  %215 = fmul float %117, %76
  %216 = fmul float %118, %78
  %217 = fadd float %216, %215
  %218 = fmul float %119, %80
  %219 = fadd float %217, %218
  %220 = fmul float %123, %60
  %221 = fmul float %124, %62
  %222 = fadd float %221, %220
  %223 = fmul float %125, %64
  %224 = fadd float %222, %223
  %225 = fadd float %112, %107
  %226 = fadd float %113, %108
  %227 = fmul float %123, %68
  %228 = fmul float %124, %70
  %229 = fadd float %228, %227
  %230 = fmul float %125, %72
  %231 = fadd float %229, %230
  %232 = fadd float %226, %113
  %233 = fadd float %225, %112
  %234 = fmul float %123, %76
  %235 = fmul float %124, %78
  %236 = fadd float %235, %234
  %237 = fmul float %125, %80
  %238 = fadd float %236, %237
  %239 = fadd float %233, %112
  %240 = fadd float %232, %113
  %241 = fmul float %58, %12
  %242 = fadd float %241, %14
  %243 = fmul float %58, %12
  %244 = fadd float %243, %14
  %245 = fmul float %58, %12
  %246 = fadd float %245, %14
  %247 = fmul float %58, %14
  %248 = fadd float %247, %12
  %249 = fsub float -0.000000e+00, %182
  %250 = fmul float %175, %16
  %251 = fadd float %250, %249
  %252 = fsub float -0.000000e+00, %168
  %253 = fmul float %84, %182
  %254 = fadd float %253, %161
  %255 = fmul float %86, %182
  %256 = fadd float %255, %252
  %257 = call float @llvm.AMDIL.clamp.(float %242, float 0.000000e+00, float 1.000000e+00)
  %258 = call float @llvm.AMDIL.clamp.(float %244, float 0.000000e+00, float 1.000000e+00)
  %259 = call float @llvm.AMDIL.clamp.(float %246, float 0.000000e+00, float 1.000000e+00)
  %260 = call float @llvm.AMDIL.clamp.(float %248, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %257, float %258, float %259, float %260)
  %261 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %262 = load float addrspace(2)* addrspace(2)* %261, !tbaa !0
  %263 = getelementptr float addrspace(2)* %262, i32 0
  %264 = load float addrspace(2)* %263, !tbaa !0
  %265 = fmul float %264, %161
  %266 = getelementptr float addrspace(2)* %262, i32 1
  %267 = load float addrspace(2)* %266, !tbaa !0
  %268 = fmul float %267, %168
  %269 = fadd float %265, %268
  %270 = getelementptr float addrspace(2)* %262, i32 2
  %271 = load float addrspace(2)* %270, !tbaa !0
  %272 = fmul float %271, %175
  %273 = fadd float %269, %272
  %274 = getelementptr float addrspace(2)* %262, i32 3
  %275 = load float addrspace(2)* %274, !tbaa !0
  %276 = fmul float %275, %182
  %277 = fadd float %273, %276
  %278 = getelementptr float addrspace(2)* %262, i32 4
  %279 = load float addrspace(2)* %278, !tbaa !0
  %280 = fmul float %279, %161
  %281 = getelementptr float addrspace(2)* %262, i32 5
  %282 = load float addrspace(2)* %281, !tbaa !0
  %283 = fmul float %282, %168
  %284 = fadd float %280, %283
  %285 = getelementptr float addrspace(2)* %262, i32 6
  %286 = load float addrspace(2)* %285, !tbaa !0
  %287 = fmul float %286, %175
  %288 = fadd float %284, %287
  %289 = getelementptr float addrspace(2)* %262, i32 7
  %290 = load float addrspace(2)* %289, !tbaa !0
  %291 = fmul float %290, %182
  %292 = fadd float %288, %291
  %293 = getelementptr float addrspace(2)* %262, i32 8
  %294 = load float addrspace(2)* %293, !tbaa !0
  %295 = fmul float %294, %161
  %296 = getelementptr float addrspace(2)* %262, i32 9
  %297 = load float addrspace(2)* %296, !tbaa !0
  %298 = fmul float %297, %168
  %299 = fadd float %295, %298
  %300 = getelementptr float addrspace(2)* %262, i32 10
  %301 = load float addrspace(2)* %300, !tbaa !0
  %302 = fmul float %301, %175
  %303 = fadd float %299, %302
  %304 = getelementptr float addrspace(2)* %262, i32 11
  %305 = load float addrspace(2)* %304, !tbaa !0
  %306 = fmul float %305, %182
  %307 = fadd float %303, %306
  %308 = getelementptr float addrspace(2)* %262, i32 12
  %309 = load float addrspace(2)* %308, !tbaa !0
  %310 = fmul float %309, %161
  %311 = getelementptr float addrspace(2)* %262, i32 13
  %312 = load float addrspace(2)* %311, !tbaa !0
  %313 = fmul float %312, %168
  %314 = fadd float %310, %313
  %315 = getelementptr float addrspace(2)* %262, i32 14
  %316 = load float addrspace(2)* %315, !tbaa !0
  %317 = fmul float %316, %175
  %318 = fadd float %314, %317
  %319 = getelementptr float addrspace(2)* %262, i32 15
  %320 = load float addrspace(2)* %319, !tbaa !0
  %321 = fmul float %320, %182
  %322 = fadd float %318, %321
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %277, float %292, float %307, float %322)
  %323 = getelementptr float addrspace(2)* %262, i32 16
  %324 = load float addrspace(2)* %323, !tbaa !0
  %325 = fmul float %324, %161
  %326 = getelementptr float addrspace(2)* %262, i32 17
  %327 = load float addrspace(2)* %326, !tbaa !0
  %328 = fmul float %327, %168
  %329 = fadd float %325, %328
  %330 = getelementptr float addrspace(2)* %262, i32 18
  %331 = load float addrspace(2)* %330, !tbaa !0
  %332 = fmul float %331, %175
  %333 = fadd float %329, %332
  %334 = getelementptr float addrspace(2)* %262, i32 19
  %335 = load float addrspace(2)* %334, !tbaa !0
  %336 = fmul float %335, %182
  %337 = fadd float %333, %336
  %338 = getelementptr float addrspace(2)* %262, i32 20
  %339 = load float addrspace(2)* %338, !tbaa !0
  %340 = fmul float %339, %161
  %341 = getelementptr float addrspace(2)* %262, i32 21
  %342 = load float addrspace(2)* %341, !tbaa !0
  %343 = fmul float %342, %168
  %344 = fadd float %340, %343
  %345 = getelementptr float addrspace(2)* %262, i32 22
  %346 = load float addrspace(2)* %345, !tbaa !0
  %347 = fmul float %346, %175
  %348 = fadd float %344, %347
  %349 = getelementptr float addrspace(2)* %262, i32 23
  %350 = load float addrspace(2)* %349, !tbaa !0
  %351 = fmul float %350, %182
  %352 = fadd float %348, %351
  %353 = getelementptr float addrspace(2)* %262, i32 24
  %354 = load float addrspace(2)* %353, !tbaa !0
  %355 = fmul float %354, %161
  %356 = getelementptr float addrspace(2)* %262, i32 25
  %357 = load float addrspace(2)* %356, !tbaa !0
  %358 = fmul float %357, %168
  %359 = fadd float %355, %358
  %360 = getelementptr float addrspace(2)* %262, i32 26
  %361 = load float addrspace(2)* %360, !tbaa !0
  %362 = fmul float %361, %175
  %363 = fadd float %359, %362
  %364 = getelementptr float addrspace(2)* %262, i32 27
  %365 = load float addrspace(2)* %364, !tbaa !0
  %366 = fmul float %365, %182
  %367 = fadd float %363, %366
  %368 = getelementptr float addrspace(2)* %262, i32 28
  %369 = load float addrspace(2)* %368, !tbaa !0
  %370 = fmul float %369, %161
  %371 = getelementptr float addrspace(2)* %262, i32 29
  %372 = load float addrspace(2)* %371, !tbaa !0
  %373 = fmul float %372, %168
  %374 = fadd float %370, %373
  %375 = getelementptr float addrspace(2)* %262, i32 30
  %376 = load float addrspace(2)* %375, !tbaa !0
  %377 = fmul float %376, %175
  %378 = fadd float %374, %377
  %379 = getelementptr float addrspace(2)* %262, i32 31
  %380 = load float addrspace(2)* %379, !tbaa !0
  %381 = fmul float %380, %182
  %382 = fadd float %378, %381
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %337, float %352, float %367, float %382)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %102, float %103, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %140, float %147, float %154, float %189)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %209, float %224, float %194, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %214, float %231, float %199, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %219, float %238, float %204, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %225, float %226, float %232, float %233)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %239, float %240, float %102, float %103)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %254, float %256, float %251, float %182)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 191; mem:LD4[%57]
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR8, %VGPR1, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR2, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%87](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR5, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR9, %SGPR5, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 17; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 16; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR10, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 18; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR5<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 19; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 21; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 20; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 22; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 23; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%261](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%311]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%308]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 25; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 24; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 26; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 27; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%315]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 29; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 28; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 30; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 31; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%319]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%296]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%293]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%300]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%304]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%281]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%278]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%285]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%289]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%266]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%263]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%270]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%274]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%371]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%368]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%375]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%379]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%356]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%353]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%360]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%364]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%341]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%338]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%345]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%349]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%326]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%323]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%330]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%334]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%99](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 49; mem:LD4[%51]
	S_WAITCNT 15
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 48; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 50; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 51; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 201; mem:LD4[%77]
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR0, %VGPR6, %EXEC<imp-use>
	%SGPR1<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 200; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR5, %SGPR1, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 202; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR7, %SGPR4, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 203; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR8, %SGPR5<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR16<def> = V_MUL_F32_e32 %SGPR5, %VGPR6, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR5, %SGPR8, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 198; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR7, %SGPR9, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 199; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR8, %SGPR10<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR10, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR12<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR5<kill>, %SGPR12, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR11<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 194; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR7<kill>, %SGPR11, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR13<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 195; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR8<kill>, %SGPR13<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR5<kill>, %VGPR16<kill>, %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%93](tbaa=!"const")
	S_WAITCNT 15
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR14<def> = V_MUL_F32_e32 %SGPR12, %VGPR5, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR6, %SGPR10, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR7, %SGPR11, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 24; mem:LD16[%120](tbaa=!"const")
	S_WAITCNT 127
	%VGPR14_VGPR15_VGPR16_VGPR17<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %SGPR12, %VGPR14, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR15, %SGPR10, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR16, %SGPR11, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%114](tbaa=!"const")
	S_WAITCNT 127
	%VGPR18_VGPR19_VGPR20_VGPR21<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR24<def> = V_MUL_F32_e32 %SGPR12<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR19, %SGPR10<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR20, %SGPR11<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR24<kill>, %VGPR23<kill>, %VGPR22<kill>, %VGPR13, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR22<def> = V_MUL_F32_e32 %SGPR8, %VGPR5, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR6, %SGPR5, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR7, %SGPR9, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %SGPR8, %VGPR14, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR15, %SGPR5, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR16, %SGPR9, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR19, %SGPR5<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR20, %SGPR9<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 36, 0, 0, 0, %VGPR24<kill>, %VGPR23<kill>, %VGPR22<kill>, %VGPR13, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR22<def> = V_MUL_F32_e32 %SGPR1, %VGPR5, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR6, %SGPR0, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR7, %SGPR4, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR1, %VGPR14, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR15, %SGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR16, %SGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR19, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR20, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>
	EXP 15, 37, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%104](tbaa=!"const")
	S_WAITCNT 15
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 16; mem:LD16[%109](tbaa=!"const")
	S_WAITCNT 112
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR17<def> = V_ADD_F32_e32 %VGPR5, %VGPR13, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR17, %VGPR5, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e32 %VGPR6, %VGPR14, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR13, %VGPR6, %EXEC<imp-use>
	EXP 15, 38, 0, 0, 0, %VGPR17<kill>, %VGPR13<kill>, %VGPR14, %VGPR0, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR13<def> = V_ADD_F32_e32 %VGPR14<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR0<kill>, %VGPR5, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	EXP 15, 39, 0, 0, 0, %VGPR0<kill>, %VGPR13<kill>, %VGPR9, %VGPR10, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 204; mem:LD4[%83]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 205; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0410100
bf8c007f
c00403bf
c0020300
bf8c007f
7e040204
c0028301
bf8c007f
7e020205
d2820003
040a0208
d2060803
02010103
d2820004
04060408
d2060804
02010104
f800020f
03040404
c0840700
bf8c000f
e00c2000
80020800
bf8c0770
d2820005
04080b08
d2820006
04080b09
c0040311
bf8c007f
10060c08
c0040310
bf8c007f
d2820003
040c1105
d2820007
04080b0a
c0028312
bf8c007f
d2820002
040c0b07
d2820008
04040908
c0020313
bf8c007f
d2820001
04080908
c0020315
bf8c007f
10040c04
c0020314
bf8c007f
d2820002
04080905
c0020316
bf8c007f
d2820002
04080907
c0020317
bf8c007f
d2820002
04080908
c0400102
bf8c007f
c002010d
bf8c007f
10060404
c002010c
bf8c007f
d2820004
040e0204
c0020319
bf8c007f
10060c04
c0020318
bf8c007f
d2820003
040c0905
c002031a
bf8c007f
d2820003
040c0907
c002031b
bf8c007f
d2820003
040c0908
c002010e
bf8c007f
d2820009
04120604
c002031d
bf8c007f
10080c04
c002031c
bf8c007f
d2820004
04100905
c002031e
bf8c007f
d2820004
04100907
c002031f
bf8c007f
d2820004
04100908
c002010f
bf8c007f
d2820009
04260804
c0020109
bf8c007f
10140404
c0020108
bf8c007f
d282000a
042a0204
c002010a
bf8c007f
d282000a
042a0604
c002010b
bf8c007f
d282000a
042a0804
c0020105
bf8c007f
10160404
c0020104
bf8c007f
d282000b
042e0204
c0020106
bf8c007f
d282000b
042e0604
c0020107
bf8c007f
d282000b
042e0804
c0020101
bf8c007f
10180404
c0020100
bf8c007f
d282000c
04320204
c0020102
bf8c007f
d282000c
04320604
c0020103
bf8c007f
d282000c
04320804
f80000ef
090a0b0c
c002011d
bf8c000f
10120404
c002011c
bf8c007f
d2820009
04260204
c002011e
bf8c007f
d2820009
04260604
c002011f
bf8c007f
d2820009
04260804
c0020119
bf8c007f
10140404
c0020118
bf8c007f
d282000a
042a0204
c002011a
bf8c007f
d282000a
042a0604
c002011b
bf8c007f
d282000a
042a0804
c0020115
bf8c007f
10160404
c0020114
bf8c007f
d282000b
042e0204
c0020116
bf8c007f
d282000b
042e0604
c0020117
bf8c007f
d282000b
042e0804
c0020111
bf8c007f
10180404
c0020110
bf8c007f
d282000c
04320204
c0020112
bf8c007f
d282000c
04320604
c0000113
bf8c007f
d282000c
04320800
f80000ff
090a0b0c
c0840708
bf8c000f
e00c2000
80020900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c0000331
bf8c000f
101c0c00
c0000330
bf8c007f
d282000e
04380105
c0000332
bf8c007f
d282000e
04380107
c0000333
bf8c007f
d282000e
04380108
c00003c9
bf8c007f
101e0c00
c00083c8
bf8c007f
d282000f
043c0305
c00203ca
bf8c007f
d282000f
043c0907
c00283cb
bf8c007f
d282000f
043c0b08
c00283c5
bf8c007f
10200c05
c00403c4
bf8c007f
d2820010
04401105
c00483c6
bf8c007f
d2820010
04401307
c00503c7
bf8c007f
d2820010
04401508
c00503c1
bf8c007f
100c0c0a
c00603c0
bf8c007f
d2820005
04181905
c00583c2
bf8c007f
d2820005
04141707
c00683c3
bf8c007f
d2820005
04141b08
f800022f
0e0f1005
c0880704
bf8c000f
e00c2000
80040500
bf8c0770
101c0a0c
d282000e
04381506
d2820016
04381707
c0880718
bf8c007f
e00c2000
80040e00
bf8c0770
10241c0c
d2820012
0448150f
d2820017
04481710
c0880714
bf8c007f
e00c2000
80041200
bf8c0770
1030240c
d2820018
04601513
d2820018
04601714
f800023f
0d161718
bf8c070f
102c0a08
d2820016
04580b06
d2820016
04581307
102e1c08
d2820017
045c0b0f
d2820017
045c1310
10302408
d2820018
04600b13
d2820018
04601314
f800024f
0d161718
bf8c070f
102c0a01
d2820016
04580106
d2820005
04580907
100c1c01
d2820006
0418010f
d2820006
04180910
100e2401
d2820007
041c0113
d2820007
041c0914
f800025f
0d050607
c084070c
bf8c000f
e00c2000
80020d00
c0820710
bf8c0070
e00c2000
80010500
bf8c0770
06221b05
06000b11
061a1d06
061c0d0d
f800026f
000e0d11
bf8c070f
061a0d0e
06000b00
f800027f
0a090d00
c00003cc
bf8c000f
d2820000
04060800
c0000302
bf8c007f
10020600
08020901
c00003cd
bf8c007f
10060800
08040503
f80008cf
04010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE
DCL IN[4], GENERIC[22], PERSPECTIVE
DCL IN[5], GENERIC[23], PERSPECTIVE
DCL IN[6], GENERIC[24], PERSPECTIVE, CENTROID
DCL IN[7], GENERIC[25], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..30]
DCL TEMP[0..8], LOCAL
DCL TEMP[9], ARRAY(1), LOCAL
IMM[0] FLT32 {   -0.4082,     0.7071,     0.5774,    -0.4082}
IMM[1] FLT32 {    0.8165,     0.0000,     0.5774,    -0.4082}
IMM[2] FLT32 {   -0.4082,    -0.7071,     0.5774,     0.0000}
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[3], 2D
  2: ADD TEMP[1].xyz, -IN[2].xyzz, CONST[10].xyzz
  3: MUL TEMP[2].xyz, TEMP[0].yyyy, IMM[0].xyzz
  4: MAD TEMP[2].xyz, TEMP[0].xxxx, IMM[1].xyzz, TEMP[2].xyzz
  5: MAD TEMP[2].xyz, TEMP[0].zzzz, IMM[2].xyzz, TEMP[2].xyzz
  6: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
  7: RSQ TEMP[3].x, TEMP[3].xxxx
  8: MUL TEMP[3].xyz, TEMP[2].xyzz, TEMP[3].xxxx
  9: DP3 TEMP[2].x, TEMP[3].xyzz, IN[3].xyzz
 10: DP3 TEMP[4].x, TEMP[3].xyzz, IN[4].xyzz
 11: MOV TEMP[2].y, TEMP[4].xxxx
 12: DP3 TEMP[4].x, TEMP[3].xyzz, IN[5].xyzz
 13: MOV TEMP[2].z, TEMP[4].xxxx
 14: DP3 TEMP[4].x, TEMP[2].xyzz, TEMP[1].xyzz
 15: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[2].xyzz
 16: ADD TEMP[4].x, TEMP[4].xxxx, TEMP[4].xxxx
 17: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[5].xxxx
 18: MAD TEMP[2].xyz, TEMP[4].xxxx, TEMP[2].xyzz, -TEMP[1].xyzz
 19: MOV TEMP[4].xyz, TEMP[2].xyzz
 20: TEX TEMP[4].xyz, TEMP[4], SAMP[2], CUBE
 21: MOV TEMP[5].xy, IN[1].xyyy
 22: TEX TEMP[5].xyz, TEMP[5], SAMP[0], 2D
 23: MOV TEMP[6].xy, IN[6].wzzz
 24: TEX TEMP[6].xyz, TEMP[6], SAMP[1], 2D
 25: MOV TEMP[7].xy, IN[6].xyyy
 26: TEX TEMP[7].xyz, TEMP[7], SAMP[1], 2D
 27: MOV TEMP[8].xy, IN[7].xyyy
 28: TEX TEMP[8].xyz, TEMP[8], SAMP[1], 2D
 29: MUL TEMP[4].xyz, TEMP[4].xyzz, CONST[30].zzzz
 30: MUL TEMP[4].xyz, TEMP[0].wwww, TEMP[4].xyzz
 31: MUL TEMP[4].xyz, TEMP[4].xyzz, CONST[0].xyzz
 32: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[4].xyzz
 33: MUL TEMP[5].xyz, TEMP[5].xyzz, IN[0].xyzz
 34: MUL TEMP[3].xyz, TEMP[0].yyyy, TEMP[6].xyzz
 35: MAD TEMP[1].xyz, TEMP[0].xxxx, TEMP[7].xyzz, TEMP[3].xyzz
 36: MAD TEMP[0].xyz, TEMP[0].zzzz, TEMP[8].xyzz, TEMP[1].xyzz
 37: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[12].xyzz
 38: MAD TEMP[1].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
 39: MAD TEMP[0].xyz, TEMP[5].xyzz, TEMP[0].xyzz, TEMP[4].xyzz
 40: MIN TEMP[1].x, TEMP[1].xxxx, CONST[11].zzzz
 41: MOV_SAT TEMP[1].x, TEMP[1].xxxx
 42: MAD TEMP[2].xyz, TEMP[0].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 43: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 44: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[1].xxxx
 45: MAD TEMP[0].xyz, TEMP[0].xyzz, CONST[30].xxxx, TEMP[2].xyzz
 46: MUL TEMP[1].x, IN[2].wwww, CONST[29].wwww
 47: MOV TEMP[0].w, TEMP[1].xxxx
 48: MOV TEMP[9], TEMP[0]
 49: MOV OUT[0], TEMP[9]
 50: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 0
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 1
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 2
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 40
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 41
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 42
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 44
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 46
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 47
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 48
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 49
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr float addrspace(2)* %21, i32 50
  %45 = load float addrspace(2)* %44, !tbaa !0
  %46 = getelementptr float addrspace(2)* %21, i32 116
  %47 = load float addrspace(2)* %46, !tbaa !0
  %48 = getelementptr float addrspace(2)* %21, i32 117
  %49 = load float addrspace(2)* %48, !tbaa !0
  %50 = getelementptr float addrspace(2)* %21, i32 118
  %51 = load float addrspace(2)* %50, !tbaa !0
  %52 = getelementptr float addrspace(2)* %21, i32 119
  %53 = load float addrspace(2)* %52, !tbaa !0
  %54 = getelementptr float addrspace(2)* %21, i32 120
  %55 = load float addrspace(2)* %54, !tbaa !0
  %56 = getelementptr float addrspace(2)* %21, i32 122
  %57 = load float addrspace(2)* %56, !tbaa !0
  %58 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %59 = load <32 x i8> addrspace(2)* %58, !tbaa !0
  %60 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
  %62 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %63 = load <32 x i8> addrspace(2)* %62, !tbaa !0
  %64 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
  %66 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %67 = load <32 x i8> addrspace(2)* %66, !tbaa !0
  %68 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
  %70 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %71 = load <32 x i8> addrspace(2)* %70, !tbaa !0
  %72 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %73 = load <16 x i8> addrspace(2)* %72, !tbaa !0
  %74 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %75 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %76 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %77 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %78 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %79 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %80 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %81 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %82 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %83 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
  %84 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
  %85 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %86 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
  %87 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
  %88 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
  %89 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
  %90 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
  %91 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
  %92 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %6)
  %93 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %6)
  %94 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %3, <2 x i32> %6)
  %95 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %3, <2 x i32> %6)
  %96 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %3, <2 x i32> %6)
  %97 = call float @llvm.SI.fs.interp(i32 1, i32 7, i32 %3, <2 x i32> %6)
  %98 = bitcast float %77 to i32
  %99 = bitcast float %78 to i32
  %100 = insertelement <2 x i32> undef, i32 %98, i32 0
  %101 = insertelement <2 x i32> %100, i32 %99, i32 1
  %102 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %101, <32 x i8> %71, <16 x i8> %73, i32 2)
  %103 = extractelement <4 x float> %102, i32 0
  %104 = extractelement <4 x float> %102, i32 1
  %105 = extractelement <4 x float> %102, i32 2
  %106 = extractelement <4 x float> %102, i32 3
  %107 = fsub float -0.000000e+00, %79
  %108 = fadd float %107, %29
  %109 = fsub float -0.000000e+00, %80
  %110 = fadd float %109, %31
  %111 = fsub float -0.000000e+00, %81
  %112 = fadd float %111, %33
  %113 = fmul float %104, 0xBFDA20BDA0000000
  %114 = fmul float %104, 0x3FE6A09E60000000
  %115 = fmul float %104, 0x3FE279A740000000
  %116 = fmul float %103, 0x3FEA20BD80000000
  %117 = fadd float %116, %113
  %118 = fmul float %103, 0.000000e+00
  %119 = fadd float %118, %114
  %120 = fmul float %103, 0x3FE279A740000000
  %121 = fadd float %120, %115
  %122 = fmul float %105, 0xBFDA20BD20000000
  %123 = fadd float %122, %117
  %124 = fmul float %105, 0xBFE6A09E80000000
  %125 = fadd float %124, %119
  %126 = fmul float %105, 0x3FE279A740000000
  %127 = fadd float %126, %121
  %128 = fmul float %123, %123
  %129 = fmul float %125, %125
  %130 = fadd float %129, %128
  %131 = fmul float %127, %127
  %132 = fadd float %130, %131
  %133 = call float @llvm.AMDGPU.rsq(float %132)
  %134 = fmul float %123, %133
  %135 = fmul float %125, %133
  %136 = fmul float %127, %133
  %137 = fmul float %134, %83
  %138 = fmul float %135, %84
  %139 = fadd float %138, %137
  %140 = fmul float %136, %85
  %141 = fadd float %139, %140
  %142 = fmul float %134, %86
  %143 = fmul float %135, %87
  %144 = fadd float %143, %142
  %145 = fmul float %136, %88
  %146 = fadd float %144, %145
  %147 = fmul float %134, %89
  %148 = fmul float %135, %90
  %149 = fadd float %148, %147
  %150 = fmul float %136, %91
  %151 = fadd float %149, %150
  %152 = fmul float %141, %108
  %153 = fmul float %146, %110
  %154 = fadd float %153, %152
  %155 = fmul float %151, %112
  %156 = fadd float %154, %155
  %157 = fmul float %141, %141
  %158 = fmul float %146, %146
  %159 = fadd float %158, %157
  %160 = fmul float %151, %151
  %161 = fadd float %159, %160
  %162 = fadd float %156, %156
  %163 = fmul float %108, %161
  %164 = fmul float %110, %161
  %165 = fmul float %112, %161
  %166 = fsub float -0.000000e+00, %163
  %167 = fmul float %162, %141
  %168 = fadd float %167, %166
  %169 = fsub float -0.000000e+00, %164
  %170 = fmul float %162, %146
  %171 = fadd float %170, %169
  %172 = fsub float -0.000000e+00, %165
  %173 = fmul float %162, %151
  %174 = fadd float %173, %172
  %175 = insertelement <4 x float> undef, float %168, i32 0
  %176 = insertelement <4 x float> %175, float %171, i32 1
  %177 = insertelement <4 x float> %176, float %174, i32 2
  %178 = insertelement <4 x float> %177, float 0.000000e+00, i32 3
  %179 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %178)
  %180 = extractelement <4 x float> %179, i32 0
  %181 = extractelement <4 x float> %179, i32 1
  %182 = extractelement <4 x float> %179, i32 2
  %183 = extractelement <4 x float> %179, i32 3
  %184 = call float @fabs(float %182)
  %185 = fdiv float 1.000000e+00, %184
  %186 = fmul float %180, %185
  %187 = fadd float %186, 1.500000e+00
  %188 = fmul float %181, %185
  %189 = fadd float %188, 1.500000e+00
  %190 = bitcast float %189 to i32
  %191 = bitcast float %187 to i32
  %192 = bitcast float %183 to i32
  %193 = insertelement <4 x i32> undef, i32 %190, i32 0
  %194 = insertelement <4 x i32> %193, i32 %191, i32 1
  %195 = insertelement <4 x i32> %194, i32 %192, i32 2
  %196 = insertelement <4 x i32> %195, i32 undef, i32 3
  %197 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %196, <32 x i8> %67, <16 x i8> %69, i32 4)
  %198 = extractelement <4 x float> %197, i32 0
  %199 = extractelement <4 x float> %197, i32 1
  %200 = extractelement <4 x float> %197, i32 2
  %201 = bitcast float %77 to i32
  %202 = bitcast float %78 to i32
  %203 = insertelement <2 x i32> undef, i32 %201, i32 0
  %204 = insertelement <2 x i32> %203, i32 %202, i32 1
  %205 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %204, <32 x i8> %59, <16 x i8> %61, i32 2)
  %206 = extractelement <4 x float> %205, i32 0
  %207 = extractelement <4 x float> %205, i32 1
  %208 = extractelement <4 x float> %205, i32 2
  %209 = bitcast float %95 to i32
  %210 = bitcast float %94 to i32
  %211 = insertelement <2 x i32> undef, i32 %209, i32 0
  %212 = insertelement <2 x i32> %211, i32 %210, i32 1
  %213 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %212, <32 x i8> %63, <16 x i8> %65, i32 2)
  %214 = extractelement <4 x float> %213, i32 0
  %215 = extractelement <4 x float> %213, i32 1
  %216 = extractelement <4 x float> %213, i32 2
  %217 = bitcast float %92 to i32
  %218 = bitcast float %93 to i32
  %219 = insertelement <2 x i32> undef, i32 %217, i32 0
  %220 = insertelement <2 x i32> %219, i32 %218, i32 1
  %221 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %220, <32 x i8> %63, <16 x i8> %65, i32 2)
  %222 = extractelement <4 x float> %221, i32 0
  %223 = extractelement <4 x float> %221, i32 1
  %224 = extractelement <4 x float> %221, i32 2
  %225 = bitcast float %96 to i32
  %226 = bitcast float %97 to i32
  %227 = insertelement <2 x i32> undef, i32 %225, i32 0
  %228 = insertelement <2 x i32> %227, i32 %226, i32 1
  %229 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %228, <32 x i8> %63, <16 x i8> %65, i32 2)
  %230 = extractelement <4 x float> %229, i32 0
  %231 = extractelement <4 x float> %229, i32 1
  %232 = extractelement <4 x float> %229, i32 2
  %233 = fmul float %198, %57
  %234 = fmul float %199, %57
  %235 = fmul float %200, %57
  %236 = fmul float %106, %233
  %237 = fmul float %106, %234
  %238 = fmul float %106, %235
  %239 = fmul float %236, %23
  %240 = fmul float %237, %25
  %241 = fmul float %238, %27
  %242 = fmul float %239, %239
  %243 = fmul float %240, %240
  %244 = fmul float %241, %241
  %245 = fmul float %206, %74
  %246 = fmul float %207, %75
  %247 = fmul float %208, %76
  %248 = fmul float %104, %214
  %249 = fmul float %104, %215
  %250 = fmul float %104, %216
  %251 = fmul float %103, %222
  %252 = fadd float %251, %248
  %253 = fmul float %103, %223
  %254 = fadd float %253, %249
  %255 = fmul float %103, %224
  %256 = fadd float %255, %250
  %257 = fmul float %105, %230
  %258 = fadd float %257, %252
  %259 = fmul float %105, %231
  %260 = fadd float %259, %254
  %261 = fmul float %105, %232
  %262 = fadd float %261, %256
  %263 = fmul float %258, %41
  %264 = fmul float %260, %43
  %265 = fmul float %262, %45
  %266 = fsub float -0.000000e+00, %35
  %267 = fmul float %82, %39
  %268 = fadd float %267, %266
  %269 = fmul float %245, %263
  %270 = fadd float %269, %242
  %271 = fmul float %246, %264
  %272 = fadd float %271, %243
  %273 = fmul float %247, %265
  %274 = fadd float %273, %244
  %275 = fcmp uge float %268, %37
  %276 = select i1 %275, float %37, float %268
  %277 = call float @llvm.AMDIL.clamp.(float %276, float 0.000000e+00, float 1.000000e+00)
  %278 = fsub float -0.000000e+00, %55
  %279 = fmul float %270, %278
  %280 = fadd float %279, %47
  %281 = fsub float -0.000000e+00, %55
  %282 = fmul float %272, %281
  %283 = fadd float %282, %49
  %284 = fsub float -0.000000e+00, %55
  %285 = fmul float %274, %284
  %286 = fadd float %285, %51
  %287 = fmul float %277, %277
  %288 = fmul float %280, %287
  %289 = fmul float %283, %287
  %290 = fmul float %286, %287
  %291 = fmul float %270, %55
  %292 = fadd float %291, %288
  %293 = fmul float %272, %55
  %294 = fadd float %293, %289
  %295 = fmul float %274, %55
  %296 = fadd float %295, %290
  %297 = fmul float %82, %53
  %298 = call i32 @llvm.SI.packf16(float %292, float %294)
  %299 = bitcast i32 %298 to float
  %300 = call i32 @llvm.SI.packf16(float %296, float %297)
  %301 = bitcast i32 %300 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %299, float %301, float %299, float %301)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 12; mem:LD16[%72](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 24; mem:LD32[%70](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6_VGPR7<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR8_VGPR9, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR10<def> = V_MUL_F32_e32 7.071068e-01, %VGPR5, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR4, 0.000000e+00, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 -7.071068e-01, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR6, %VGPR11<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 -4.082483e-01, %VGPR5, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 8.164966e-01, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR4, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 -4.082482e-01, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR6, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR13, %VGPR13, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 5.773503e-01, %VGPR5, %EXEC<imp-use>
	%VGPR14<def> = V_MOV_B32_e32 5.773503e-01, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR4, %VGPR14, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR6, %VGPR14<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR10, %VGPR10, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_RSQ_LEGACY_F32_e32 %VGPR12<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR13, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR11, %VGPR15<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR14, %VGPR10<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR13, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR11, %VGPR15<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR14, %VGPR15<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR12, %VGPR12, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR10, %VGPR10, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR0, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<kill,tied0>, %VGPR1, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR0, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<kill,tied0>, %VGPR1, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %VGPR16<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR14<kill>, %VGPR13<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 41; mem:LD4[%30]
	S_WAITCNT 127
	%VGPR16<def> = V_SUB_F32_e32 %SGPR7<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR16, %VGPR13, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 40; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR7<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR12, %VGPR15, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR10, %VGPR16<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 42; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR16<def> = V_SUB_F32_e32 %SGPR7<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR11, %VGPR16, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e32 %VGPR17<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR17, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 %VGPR10<kill>, %VGPR14<kill>, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-def>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR17, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %VGPR12<kill>, %VGPR10<kill>, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-def>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR10<kill>, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-def>
	%VGPR21<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-def>
	%VGPR11<def> = V_CUBESC_F32 %VGPR18, %VGPR19, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR10<def> = V_CUBETC_F32 %VGPR18, %VGPR19, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR12<def> = V_CUBEMA_F32 %VGPR18, %VGPR19, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR13<def> = V_CUBEID_F32 %VGPR18, %VGPR19, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR18<def> = V_ADD_F32_e64 %VGPR12, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_RCP_F32_e32 %VGPR18<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR10, %VGPR18, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR11<def> = V_MAD_F32 %VGPR11, %VGPR18<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR14<def> = KILL %VGPR14<undef>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%68](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%66](tbaa=!"const")
	S_WAITCNT 127
	%VGPR10_VGPR11_VGPR12<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR11_VGPR12_VGPR13_VGPR14, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 122; mem:LD4[%56]
	S_WAITCNT 112
	%VGPR13<def> = V_MUL_F32_e32 %SGPR7, %VGPR11, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR7, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%24]
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR2, 2, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<tied0>, %VGPR3, 2, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR2, 3, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<tied0>, %VGPR3, 3, 6, %M0<kill>, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%64](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%62](tbaa=!"const")
	S_WAITCNT 127
	%VGPR13_VGPR14_VGPR15<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR19<def> = V_MUL_F32_e32 %VGPR5, %VGPR14, %EXEC<imp-use>
	%VGPR17<def> = V_INTERP_P1_F32 %VGPR2, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-def>
	%VGPR17<def,tied1> = V_INTERP_P2_F32 %VGPR17<tied0>, %VGPR3, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-use,kill>, %VGPR16_VGPR17<imp-def>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR2, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-use,kill>, %VGPR16_VGPR17<imp-def>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<tied0>, %VGPR3, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-use,kill>, %VGPR16_VGPR17<imp-def>
	%VGPR16_VGPR17_VGPR18<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR16_VGPR17<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR19<def> = V_MAD_F32 %VGPR4, %VGPR17, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_INTERP_P1_F32 %VGPR2, 1, 7, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-def>
	%VGPR21<def,tied1> = V_INTERP_P2_F32 %VGPR21<tied0>, %VGPR3, 1, 7, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-use,kill>, %VGPR20_VGPR21<imp-def>
	%VGPR20<def> = V_INTERP_P1_F32 %VGPR2, 0, 7, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-use,kill>, %VGPR20_VGPR21<imp-def>
	%VGPR20<def,tied1> = V_INTERP_P2_F32 %VGPR20<tied0>, %VGPR3, 0, 7, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR20_VGPR21<imp-use,kill>, %VGPR20_VGPR21<imp-def>
	%VGPR22_VGPR23_VGPR24<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR20_VGPR21<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR6, %VGPR23, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 49; mem:LD4[%42]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%60](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%58](tbaa=!"const")
	S_WAITCNT 127
	%VGPR19_VGPR20_VGPR21<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR8_VGPR9<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR3<def> = V_MUL_F32_e32 %VGPR20, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR3<kill>, %VGPR2<kill>, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%54]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%48]
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 47; mem:LD4[%38]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 44; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR3<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 46; mem:LD4[%36]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR25<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8<kill>, %SGPR2, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR7, %VGPR10, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR7, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR5, %VGPR13, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR4, %VGPR16, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR6, %VGPR22, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR25<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR26<def,tied1> = V_INTERP_P2_F32 %VGPR26<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR19, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR26<kill>, %VGPR25<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %SGPR2, %VGPR9, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 116; mem:LD4[%46]
	S_WAITCNT 127
	%VGPR25<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR9<kill>, %SGPR2, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR12, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12<imp-use,kill>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR7, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR5, %VGPR15, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15<imp-use,kill>
	%VGPR10<def> = V_MAD_F32 %VGPR4, %VGPR18, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR16_VGPR17_VGPR18<imp-use,kill>
	%VGPR4<def> = V_MAD_F32 %VGPR6, %VGPR24, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR22_VGPR23_VGPR24<imp-use,kill>, %VGPR4_VGPR5_VGPR6_VGPR7<imp-use,kill>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%44]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR21, %VGPR5<kill>, %EXEC<imp-use>, %VGPR19_VGPR20_VGPR21<imp-use,kill>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %VGPR4<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR2, %VGPR0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 118; mem:LD4[%50]
	S_WAITCNT 127
	%VGPR1<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 119; mem:LD4[%52]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR8<kill>, %VGPR0<kill>, %VGPR8, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8240500
c8250501
c8200400
c8210401
c084030c
c0c60518
bf8c007f
f0800f00
00430408
bf8c0770
10140aff
3f3504f3
d282000a
04290104
7e1602ff
bf3504f4
d282000b
042a1706
10140aff
bed105ed
7e1802ff
3f5105ec
d282000a
042a1904
7e1802ff
bed105e9
d282000d
042a1906
10141b0d
d282000c
042a170b
10140aff
3f13cd3a
7e1c02ff
3f13cd3a
d282000a
042a1d04
d282000a
042a1d06
d282000c
0432150a
7e185b0c
1016190b
101a190d
c8381000
c8391001
101c1d0d
c83c1100
c83d1101
d282000f
043a1f0b
101c190a
c8281200
c8291201
d282000a
043e150e
c8300c00
c8310c01
1018190d
c83c0d00
c83d0d01
d282000c
04321f0b
c83c0e00
c83d0e01
d282000c
04321f0e
101e190c
d282000f
043e150a
c8401400
c8411401
101a210d
c8401500
c8411501
d282000b
0436210b
c8341600
c8351601
d282000b
042e1b0e
d282000d
043e170b
c8380900
c8390901
c0400100
bf8c007f
c0038129
bf8c007f
08201c07
101c1b10
c83c0800
c83d0801
c0038128
bf8c007f
081e1e07
10221f0c
d2820011
0446210a
c8400a00
c8410a01
c003812a
bf8c007f
08202007
d2820011
0446210b
06222311
10141511
08261d0a
10141b0f
10181911
0824150c
10141b10
10161711
0828150b
7e2a0280
d28a000b
04522712
d28c000a
04522712
d28e000c
04522712
d288000d
04522712
d2060112
0201010c
7e245512
7e2602ff
3fc00000
d282000c
044e250a
d282000b
044e250b
c0840308
c0c60510
bf8c007f
f0800700
00430a0b
c003817a
bf8c0070
101a1607
101a1b07
c0040101
bf8c007f
101a1a08
10321b0d
c8381a02
c8391a03
c8341b02
c8351b03
c0840304
c0c60508
bf8c007f
f0800700
00430d0d
bf8c0770
10261d05
c8441902
c8451903
c8401802
c8411803
f0800700
00431010
bf8c0770
d2820013
044e2304
c8541d02
c8551d03
c8501c02
c8511c03
f0800700
00431614
bf8c0770
d2820002
044e2f06
c0040131
bf8c007f
10040408
c0840300
c0c60500
bf8c007f
f0800700
00431308
c80c0100
c80d0101
bf8c0770
10060714
d2820008
04660503
c0010178
bf8c007f
10041002
c0018175
bf8c007f
08120403
c8080b00
c8090b01
c001812f
bf8c007f
10060403
c001812c
bf8c007f
0a060603
c001812e
bf8c007f
d00c0004
02000703
7e320203
d2000003
00123303
d2060803
02010103
10060703
10120709
d2820008
04240508
10121407
10121307
c0018100
bf8c007f
10121203
10121309
10321b05
d2820019
04662104
d2820019
04662d06
c0018130
bf8c007f
10323203
c8680000
c8690001
10343513
d2820009
0426331a
10321202
c0018174
bf8c007f
08323203
10320719
d2820009
04640509
5e101109
10121807
10121307
c0018102
bf8c007f
10121203
10121309
10141f05
d282000a
042a2504
d2820004
042a3106
c0018132
bf8c007f
10080803
c8140200
c8150201
10000b15
d2820000
04260900
10020002
c0018176
bf8c007f
08020203
10020701
d2820000
04040500
c0000177
bf8c007f
10020400
5e000300
f8001c0f
00080008
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL OUT[7], GENERIC[23]
DCL OUT[8], GENERIC[24]
DCL OUT[9], GENERIC[25]
DCL CONST[0..51]
DCL TEMP[0..12], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[48]
  2: DP4 TEMP[2].x, TEMP[0], CONST[49]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[50]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[6]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: DP4 TEMP[5].x, TEMP[0], CONST[7]
 12: MOV TEMP[2].w, TEMP[5].xxxx
 13: DP4 TEMP[6].x, TEMP[0], CONST[12]
 14: DP3 TEMP[7].x, IN[1].xyzz, CONST[48].xyzz
 15: MOV TEMP[7].z, TEMP[7].xxxx
 16: DP3 TEMP[8].x, IN[1].xyzz, CONST[49].xyzz
 17: MOV TEMP[8].z, TEMP[8].xxxx
 18: DP3 TEMP[9].x, IN[1].xyzz, CONST[50].xyzz
 19: MOV TEMP[9].z, TEMP[9].xxxx
 20: DP3 TEMP[7].x, IN[5].xyzz, CONST[48].xyzz
 21: DP3 TEMP[8].x, IN[5].xyzz, CONST[49].xyzz
 22: DP3 TEMP[9].x, IN[5].xyzz, CONST[50].xyzz
 23: DP3 TEMP[10].x, IN[6].xyzz, CONST[48].xyzz
 24: MOV TEMP[7].y, TEMP[10].xxxx
 25: ADD TEMP[0].xy, IN[4].xyyy, IN[3].xyyy
 26: DP3 TEMP[10].x, IN[6].xyzz, CONST[49].xyzz
 27: MOV TEMP[8].y, TEMP[10].xxxx
 28: ADD TEMP[10].xy, TEMP[0].yxxx, IN[4].yxxx
 29: MOV TEMP[0].zw, TEMP[10].yyxy
 30: DP3 TEMP[11].x, IN[6].xyzz, CONST[50].xyzz
 31: MOV TEMP[9].y, TEMP[11].xxxx
 32: MOV TEMP[0], TEMP[0]
 33: ADD TEMP[10].xy, TEMP[10].yxxx, IN[4].xyyy
 34: MOV TEMP[1].w, TEMP[6].xxxx
 35: MOV TEMP[6].xy, IN[2].xyxx
 36: MOV TEMP[10].zw, IN[2].yyxy
 37: MAD TEMP[11], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx
 38: MOV TEMP[12], TEMP[2]
 39: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[5].xxxx
 40: MOV TEMP[2].z, TEMP[4].xxxx
 41: MOV TEMP[2].y, -TEMP[3].xxxx
 42: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[5].xxxx, TEMP[2].xyyy
 43: MOV OUT[3], TEMP[6]
 44: MOV OUT[8], TEMP[0]
 45: MOV OUT[9], TEMP[10]
 46: MOV OUT[0], TEMP[2]
 47: MOV OUT[4], TEMP[1]
 48: MOV OUT[2], TEMP[12]
 49: MOV OUT[5], TEMP[7]
 50: MOV OUT[6], TEMP[8]
 51: MOV_SAT OUT[1], TEMP[11]
 52: MOV OUT[7], TEMP[9]
 53: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 16
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 17
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 18
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 19
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 20
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 21
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 22
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 23
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 24
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 25
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 26
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 27
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 28
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 29
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 30
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 31
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 48
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 49
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 50
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 51
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 191
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 192
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 193
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 194
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 195
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 196
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 197
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 198
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 199
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 200
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 201
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 202
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 203
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 204
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 205
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %5)
  %90 = extractelement <4 x float> %89, i32 0
  %91 = extractelement <4 x float> %89, i32 1
  %92 = extractelement <4 x float> %89, i32 2
  %93 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %94 = load <16 x i8> addrspace(2)* %93, !tbaa !0
  %95 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %94, i32 0, i32 %5)
  %96 = extractelement <4 x float> %95, i32 0
  %97 = extractelement <4 x float> %95, i32 1
  %98 = extractelement <4 x float> %95, i32 2
  %99 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %100 = load <16 x i8> addrspace(2)* %99, !tbaa !0
  %101 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %100, i32 0, i32 %5)
  %102 = extractelement <4 x float> %101, i32 0
  %103 = extractelement <4 x float> %101, i32 1
  %104 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %105 = load <16 x i8> addrspace(2)* %104, !tbaa !0
  %106 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %105, i32 0, i32 %5)
  %107 = extractelement <4 x float> %106, i32 0
  %108 = extractelement <4 x float> %106, i32 1
  %109 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %110 = load <16 x i8> addrspace(2)* %109, !tbaa !0
  %111 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %110, i32 0, i32 %5)
  %112 = extractelement <4 x float> %111, i32 0
  %113 = extractelement <4 x float> %111, i32 1
  %114 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
  %115 = load <16 x i8> addrspace(2)* %114, !tbaa !0
  %116 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %115, i32 0, i32 %5)
  %117 = extractelement <4 x float> %116, i32 0
  %118 = extractelement <4 x float> %116, i32 1
  %119 = extractelement <4 x float> %116, i32 2
  %120 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
  %121 = load <16 x i8> addrspace(2)* %120, !tbaa !0
  %122 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %121, i32 0, i32 %5)
  %123 = extractelement <4 x float> %122, i32 0
  %124 = extractelement <4 x float> %122, i32 1
  %125 = extractelement <4 x float> %122, i32 2
  %126 = fmul float %90, %14
  %127 = fadd float %126, %12
  %128 = fmul float %91, %14
  %129 = fadd float %128, %12
  %130 = fmul float %92, %14
  %131 = fadd float %130, %12
  %132 = fmul float %90, %12
  %133 = fadd float %132, %14
  %134 = fmul float %127, %60
  %135 = fmul float %129, %62
  %136 = fadd float %134, %135
  %137 = fmul float %131, %64
  %138 = fadd float %136, %137
  %139 = fmul float %133, %66
  %140 = fadd float %138, %139
  %141 = fmul float %127, %68
  %142 = fmul float %129, %70
  %143 = fadd float %141, %142
  %144 = fmul float %131, %72
  %145 = fadd float %143, %144
  %146 = fmul float %133, %74
  %147 = fadd float %145, %146
  %148 = fmul float %127, %76
  %149 = fmul float %129, %78
  %150 = fadd float %148, %149
  %151 = fmul float %131, %80
  %152 = fadd float %150, %151
  %153 = fmul float %133, %82
  %154 = fadd float %152, %153
  %155 = fmul float %127, %18
  %156 = fmul float %129, %20
  %157 = fadd float %155, %156
  %158 = fmul float %131, %22
  %159 = fadd float %157, %158
  %160 = fmul float %133, %24
  %161 = fadd float %159, %160
  %162 = fmul float %127, %26
  %163 = fmul float %129, %28
  %164 = fadd float %162, %163
  %165 = fmul float %131, %30
  %166 = fadd float %164, %165
  %167 = fmul float %133, %32
  %168 = fadd float %166, %167
  %169 = fmul float %127, %34
  %170 = fmul float %129, %36
  %171 = fadd float %169, %170
  %172 = fmul float %131, %38
  %173 = fadd float %171, %172
  %174 = fmul float %133, %40
  %175 = fadd float %173, %174
  %176 = fmul float %127, %42
  %177 = fmul float %129, %44
  %178 = fadd float %176, %177
  %179 = fmul float %131, %46
  %180 = fadd float %178, %179
  %181 = fmul float %133, %48
  %182 = fadd float %180, %181
  %183 = fmul float %127, %50
  %184 = fmul float %129, %52
  %185 = fadd float %183, %184
  %186 = fmul float %131, %54
  %187 = fadd float %185, %186
  %188 = fmul float %133, %56
  %189 = fadd float %187, %188
  %190 = fmul float %96, %60
  %191 = fmul float %97, %62
  %192 = fadd float %191, %190
  %193 = fmul float %98, %64
  %194 = fadd float %192, %193
  %195 = fmul float %96, %68
  %196 = fmul float %97, %70
  %197 = fadd float %196, %195
  %198 = fmul float %98, %72
  %199 = fadd float %197, %198
  %200 = fmul float %96, %76
  %201 = fmul float %97, %78
  %202 = fadd float %201, %200
  %203 = fmul float %98, %80
  %204 = fadd float %202, %203
  %205 = fmul float %117, %60
  %206 = fmul float %118, %62
  %207 = fadd float %206, %205
  %208 = fmul float %119, %64
  %209 = fadd float %207, %208
  %210 = fmul float %117, %68
  %211 = fmul float %118, %70
  %212 = fadd float %211, %210
  %213 = fmul float %119, %72
  %214 = fadd float %212, %213
  %215 = fmul float %117, %76
  %216 = fmul float %118, %78
  %217 = fadd float %216, %215
  %218 = fmul float %119, %80
  %219 = fadd float %217, %218
  %220 = fmul float %123, %60
  %221 = fmul float %124, %62
  %222 = fadd float %221, %220
  %223 = fmul float %125, %64
  %224 = fadd float %222, %223
  %225 = fadd float %112, %107
  %226 = fadd float %113, %108
  %227 = fmul float %123, %68
  %228 = fmul float %124, %70
  %229 = fadd float %228, %227
  %230 = fmul float %125, %72
  %231 = fadd float %229, %230
  %232 = fadd float %226, %113
  %233 = fadd float %225, %112
  %234 = fmul float %123, %76
  %235 = fmul float %124, %78
  %236 = fadd float %235, %234
  %237 = fmul float %125, %80
  %238 = fadd float %236, %237
  %239 = fadd float %233, %112
  %240 = fadd float %232, %113
  %241 = fmul float %58, %12
  %242 = fadd float %241, %14
  %243 = fmul float %58, %12
  %244 = fadd float %243, %14
  %245 = fmul float %58, %12
  %246 = fadd float %245, %14
  %247 = fmul float %58, %14
  %248 = fadd float %247, %12
  %249 = fsub float -0.000000e+00, %182
  %250 = fmul float %175, %16
  %251 = fadd float %250, %249
  %252 = fsub float -0.000000e+00, %168
  %253 = fmul float %84, %182
  %254 = fadd float %253, %161
  %255 = fmul float %86, %182
  %256 = fadd float %255, %252
  %257 = call float @llvm.AMDIL.clamp.(float %242, float 0.000000e+00, float 1.000000e+00)
  %258 = call float @llvm.AMDIL.clamp.(float %244, float 0.000000e+00, float 1.000000e+00)
  %259 = call float @llvm.AMDIL.clamp.(float %246, float 0.000000e+00, float 1.000000e+00)
  %260 = call float @llvm.AMDIL.clamp.(float %248, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %257, float %258, float %259, float %260)
  %261 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %262 = load float addrspace(2)* addrspace(2)* %261, !tbaa !0
  %263 = getelementptr float addrspace(2)* %262, i32 0
  %264 = load float addrspace(2)* %263, !tbaa !0
  %265 = fmul float %264, %161
  %266 = getelementptr float addrspace(2)* %262, i32 1
  %267 = load float addrspace(2)* %266, !tbaa !0
  %268 = fmul float %267, %168
  %269 = fadd float %265, %268
  %270 = getelementptr float addrspace(2)* %262, i32 2
  %271 = load float addrspace(2)* %270, !tbaa !0
  %272 = fmul float %271, %175
  %273 = fadd float %269, %272
  %274 = getelementptr float addrspace(2)* %262, i32 3
  %275 = load float addrspace(2)* %274, !tbaa !0
  %276 = fmul float %275, %182
  %277 = fadd float %273, %276
  %278 = getelementptr float addrspace(2)* %262, i32 4
  %279 = load float addrspace(2)* %278, !tbaa !0
  %280 = fmul float %279, %161
  %281 = getelementptr float addrspace(2)* %262, i32 5
  %282 = load float addrspace(2)* %281, !tbaa !0
  %283 = fmul float %282, %168
  %284 = fadd float %280, %283
  %285 = getelementptr float addrspace(2)* %262, i32 6
  %286 = load float addrspace(2)* %285, !tbaa !0
  %287 = fmul float %286, %175
  %288 = fadd float %284, %287
  %289 = getelementptr float addrspace(2)* %262, i32 7
  %290 = load float addrspace(2)* %289, !tbaa !0
  %291 = fmul float %290, %182
  %292 = fadd float %288, %291
  %293 = getelementptr float addrspace(2)* %262, i32 8
  %294 = load float addrspace(2)* %293, !tbaa !0
  %295 = fmul float %294, %161
  %296 = getelementptr float addrspace(2)* %262, i32 9
  %297 = load float addrspace(2)* %296, !tbaa !0
  %298 = fmul float %297, %168
  %299 = fadd float %295, %298
  %300 = getelementptr float addrspace(2)* %262, i32 10
  %301 = load float addrspace(2)* %300, !tbaa !0
  %302 = fmul float %301, %175
  %303 = fadd float %299, %302
  %304 = getelementptr float addrspace(2)* %262, i32 11
  %305 = load float addrspace(2)* %304, !tbaa !0
  %306 = fmul float %305, %182
  %307 = fadd float %303, %306
  %308 = getelementptr float addrspace(2)* %262, i32 12
  %309 = load float addrspace(2)* %308, !tbaa !0
  %310 = fmul float %309, %161
  %311 = getelementptr float addrspace(2)* %262, i32 13
  %312 = load float addrspace(2)* %311, !tbaa !0
  %313 = fmul float %312, %168
  %314 = fadd float %310, %313
  %315 = getelementptr float addrspace(2)* %262, i32 14
  %316 = load float addrspace(2)* %315, !tbaa !0
  %317 = fmul float %316, %175
  %318 = fadd float %314, %317
  %319 = getelementptr float addrspace(2)* %262, i32 15
  %320 = load float addrspace(2)* %319, !tbaa !0
  %321 = fmul float %320, %182
  %322 = fadd float %318, %321
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %277, float %292, float %307, float %322)
  %323 = getelementptr float addrspace(2)* %262, i32 16
  %324 = load float addrspace(2)* %323, !tbaa !0
  %325 = fmul float %324, %161
  %326 = getelementptr float addrspace(2)* %262, i32 17
  %327 = load float addrspace(2)* %326, !tbaa !0
  %328 = fmul float %327, %168
  %329 = fadd float %325, %328
  %330 = getelementptr float addrspace(2)* %262, i32 18
  %331 = load float addrspace(2)* %330, !tbaa !0
  %332 = fmul float %331, %175
  %333 = fadd float %329, %332
  %334 = getelementptr float addrspace(2)* %262, i32 19
  %335 = load float addrspace(2)* %334, !tbaa !0
  %336 = fmul float %335, %182
  %337 = fadd float %333, %336
  %338 = getelementptr float addrspace(2)* %262, i32 20
  %339 = load float addrspace(2)* %338, !tbaa !0
  %340 = fmul float %339, %161
  %341 = getelementptr float addrspace(2)* %262, i32 21
  %342 = load float addrspace(2)* %341, !tbaa !0
  %343 = fmul float %342, %168
  %344 = fadd float %340, %343
  %345 = getelementptr float addrspace(2)* %262, i32 22
  %346 = load float addrspace(2)* %345, !tbaa !0
  %347 = fmul float %346, %175
  %348 = fadd float %344, %347
  %349 = getelementptr float addrspace(2)* %262, i32 23
  %350 = load float addrspace(2)* %349, !tbaa !0
  %351 = fmul float %350, %182
  %352 = fadd float %348, %351
  %353 = getelementptr float addrspace(2)* %262, i32 24
  %354 = load float addrspace(2)* %353, !tbaa !0
  %355 = fmul float %354, %161
  %356 = getelementptr float addrspace(2)* %262, i32 25
  %357 = load float addrspace(2)* %356, !tbaa !0
  %358 = fmul float %357, %168
  %359 = fadd float %355, %358
  %360 = getelementptr float addrspace(2)* %262, i32 26
  %361 = load float addrspace(2)* %360, !tbaa !0
  %362 = fmul float %361, %175
  %363 = fadd float %359, %362
  %364 = getelementptr float addrspace(2)* %262, i32 27
  %365 = load float addrspace(2)* %364, !tbaa !0
  %366 = fmul float %365, %182
  %367 = fadd float %363, %366
  %368 = getelementptr float addrspace(2)* %262, i32 28
  %369 = load float addrspace(2)* %368, !tbaa !0
  %370 = fmul float %369, %161
  %371 = getelementptr float addrspace(2)* %262, i32 29
  %372 = load float addrspace(2)* %371, !tbaa !0
  %373 = fmul float %372, %168
  %374 = fadd float %370, %373
  %375 = getelementptr float addrspace(2)* %262, i32 30
  %376 = load float addrspace(2)* %375, !tbaa !0
  %377 = fmul float %376, %175
  %378 = fadd float %374, %377
  %379 = getelementptr float addrspace(2)* %262, i32 31
  %380 = load float addrspace(2)* %379, !tbaa !0
  %381 = fmul float %380, %182
  %382 = fadd float %378, %381
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %337, float %352, float %367, float %382)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %102, float %103, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %140, float %147, float %154, float %189)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %209, float %224, float %194, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %214, float %231, float %199, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %219, float %238, float %204, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %225, float %226, float %232, float %233)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %239, float %240, float %102, float %103)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %254, float %256, float %251, float %182)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 191; mem:LD4[%57]
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR8, %VGPR1, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR8<kill>, %VGPR2, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR4<kill>, %VGPR4, %VGPR4, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%87](tbaa=!"const")
	S_WAITCNT 15
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR5, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR9, %SGPR5, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 17; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 16; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR10, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 18; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR5<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 19; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 21; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 20; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 22; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 23; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%261](tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%311]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%308]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 25; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 24; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 26; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 27; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%315]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 29; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 28; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 30; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 31; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%319]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%296]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%293]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%300]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%304]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%281]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%278]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%285]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%289]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%266]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%263]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%270]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%274]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%371]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%368]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%375]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%379]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%356]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%353]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%360]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%364]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%341]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%338]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%345]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%349]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR4<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%326]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%323]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%330]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR4<kill>, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%334]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%99](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 49; mem:LD4[%51]
	S_WAITCNT 15
	%VGPR14<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 48; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 50; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 51; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR8, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 201; mem:LD4[%77]
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR0, %VGPR6, %EXEC<imp-use>
	%SGPR1<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 200; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR5, %SGPR1, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 202; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR7, %SGPR4, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 203; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %VGPR8, %SGPR5<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR16<def> = V_MUL_F32_e32 %SGPR5, %VGPR6, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR5, %SGPR8, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 198; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR7, %SGPR9, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 199; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR8, %SGPR10<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR10, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR12<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR5<kill>, %SGPR12, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR11<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 194; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR7<kill>, %SGPR11, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR13<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 195; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR8<kill>, %SGPR13<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR5<kill>, %VGPR16<kill>, %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%93](tbaa=!"const")
	S_WAITCNT 15
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR14<def> = V_MUL_F32_e32 %SGPR12, %VGPR5, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR6, %SGPR10, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR7, %SGPR11, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 24; mem:LD16[%120](tbaa=!"const")
	S_WAITCNT 127
	%VGPR14_VGPR15_VGPR16_VGPR17<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %SGPR12, %VGPR14, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR15, %SGPR10, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR16, %SGPR11, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%114](tbaa=!"const")
	S_WAITCNT 127
	%VGPR18_VGPR19_VGPR20_VGPR21<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR24<def> = V_MUL_F32_e32 %SGPR12<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR19, %SGPR10<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR20, %SGPR11<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR24<kill>, %VGPR23<kill>, %VGPR22<kill>, %VGPR13, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR22<def> = V_MUL_F32_e32 %SGPR8, %VGPR5, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR6, %SGPR5, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR7, %SGPR9, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %SGPR8, %VGPR14, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR15, %SGPR5, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR16, %SGPR9, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR19, %SGPR5<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR20, %SGPR9<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 36, 0, 0, 0, %VGPR24<kill>, %VGPR23<kill>, %VGPR22<kill>, %VGPR13, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR22<def> = V_MUL_F32_e32 %SGPR1, %VGPR5, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR6, %SGPR0, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR7, %SGPR4, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR1, %VGPR14, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR15, %SGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR16, %SGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR19, %SGPR0<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR20, %SGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>
	EXP 15, 37, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%104](tbaa=!"const")
	S_WAITCNT 15
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 16; mem:LD16[%109](tbaa=!"const")
	S_WAITCNT 112
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR17<def> = V_ADD_F32_e32 %VGPR5, %VGPR13, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR17, %VGPR5, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e32 %VGPR6, %VGPR14, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR13, %VGPR6, %EXEC<imp-use>
	EXP 15, 38, 0, 0, 0, %VGPR17<kill>, %VGPR13<kill>, %VGPR14, %VGPR0, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR13<def> = V_ADD_F32_e32 %VGPR14<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR0<kill>, %VGPR5, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	EXP 15, 39, 0, 0, 0, %VGPR0<kill>, %VGPR13<kill>, %VGPR9, %VGPR10, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 204; mem:LD4[%83]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR4, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 205; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR4<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0410100
bf8c007f
c00403bf
c0020300
bf8c007f
7e040204
c0028301
bf8c007f
7e020205
d2820003
040a0208
d2060803
02010103
d2820004
04060408
d2060804
02010104
f800020f
03040404
c0840700
bf8c000f
e00c2000
80020800
bf8c0770
d2820005
04080b08
d2820006
04080b09
c0040311
bf8c007f
10060c08
c0040310
bf8c007f
d2820003
040c1105
d2820007
04080b0a
c0028312
bf8c007f
d2820002
040c0b07
d2820008
04040908
c0020313
bf8c007f
d2820001
04080908
c0020315
bf8c007f
10040c04
c0020314
bf8c007f
d2820002
04080905
c0020316
bf8c007f
d2820002
04080907
c0020317
bf8c007f
d2820002
04080908
c0400102
bf8c007f
c002010d
bf8c007f
10060404
c002010c
bf8c007f
d2820004
040e0204
c0020319
bf8c007f
10060c04
c0020318
bf8c007f
d2820003
040c0905
c002031a
bf8c007f
d2820003
040c0907
c002031b
bf8c007f
d2820003
040c0908
c002010e
bf8c007f
d2820009
04120604
c002031d
bf8c007f
10080c04
c002031c
bf8c007f
d2820004
04100905
c002031e
bf8c007f
d2820004
04100907
c002031f
bf8c007f
d2820004
04100908
c002010f
bf8c007f
d2820009
04260804
c0020109
bf8c007f
10140404
c0020108
bf8c007f
d282000a
042a0204
c002010a
bf8c007f
d282000a
042a0604
c002010b
bf8c007f
d282000a
042a0804
c0020105
bf8c007f
10160404
c0020104
bf8c007f
d282000b
042e0204
c0020106
bf8c007f
d282000b
042e0604
c0020107
bf8c007f
d282000b
042e0804
c0020101
bf8c007f
10180404
c0020100
bf8c007f
d282000c
04320204
c0020102
bf8c007f
d282000c
04320604
c0020103
bf8c007f
d282000c
04320804
f80000ef
090a0b0c
c002011d
bf8c000f
10120404
c002011c
bf8c007f
d2820009
04260204
c002011e
bf8c007f
d2820009
04260604
c002011f
bf8c007f
d2820009
04260804
c0020119
bf8c007f
10140404
c0020118
bf8c007f
d282000a
042a0204
c002011a
bf8c007f
d282000a
042a0604
c002011b
bf8c007f
d282000a
042a0804
c0020115
bf8c007f
10160404
c0020114
bf8c007f
d282000b
042e0204
c0020116
bf8c007f
d282000b
042e0604
c0020117
bf8c007f
d282000b
042e0804
c0020111
bf8c007f
10180404
c0020110
bf8c007f
d282000c
04320204
c0020112
bf8c007f
d282000c
04320604
c0000113
bf8c007f
d282000c
04320800
f80000ff
090a0b0c
c0840708
bf8c000f
e00c2000
80020900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c0000331
bf8c000f
101c0c00
c0000330
bf8c007f
d282000e
04380105
c0000332
bf8c007f
d282000e
04380107
c0000333
bf8c007f
d282000e
04380108
c00003c9
bf8c007f
101e0c00
c00083c8
bf8c007f
d282000f
043c0305
c00203ca
bf8c007f
d282000f
043c0907
c00283cb
bf8c007f
d282000f
043c0b08
c00283c5
bf8c007f
10200c05
c00403c4
bf8c007f
d2820010
04401105
c00483c6
bf8c007f
d2820010
04401307
c00503c7
bf8c007f
d2820010
04401508
c00503c1
bf8c007f
100c0c0a
c00603c0
bf8c007f
d2820005
04181905
c00583c2
bf8c007f
d2820005
04141707
c00683c3
bf8c007f
d2820005
04141b08
f800022f
0e0f1005
c0880704
bf8c000f
e00c2000
80040500
bf8c0770
101c0a0c
d282000e
04381506
d2820016
04381707
c0880718
bf8c007f
e00c2000
80040e00
bf8c0770
10241c0c
d2820012
0448150f
d2820017
04481710
c0880714
bf8c007f
e00c2000
80041200
bf8c0770
1030240c
d2820018
04601513
d2820018
04601714
f800023f
0d161718
bf8c070f
102c0a08
d2820016
04580b06
d2820016
04581307
102e1c08
d2820017
045c0b0f
d2820017
045c1310
10302408
d2820018
04600b13
d2820018
04601314
f800024f
0d161718
bf8c070f
102c0a01
d2820016
04580106
d2820005
04580907
100c1c01
d2820006
0418010f
d2820006
04180910
100e2401
d2820007
041c0113
d2820007
041c0914
f800025f
0d050607
c084070c
bf8c000f
e00c2000
80020d00
c0820710
bf8c0070
e00c2000
80010500
bf8c0770
06221b05
06000b11
061a1d06
061c0d0d
f800026f
000e0d11
bf8c070f
061a0d0e
06000b00
f800027f
0a090d00
c00003cc
bf8c000f
d2820000
04060800
c0000302
bf8c007f
10020600
08020901
c00003cd
bf8c007f
10060800
08040503
f80008cf
04010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..30]
DCL TEMP[0..3], LOCAL
DCL TEMP[4], ARRAY(1), LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MOV TEMP[1].xy, IN[3].xyyy
  3: TEX TEMP[2].xyz, TEMP[1], SAMP[1], 2D
  4: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[12].xyzz
  5: MAD TEMP[3].x, IN[2].wwww, CONST[11].wwww, -CONST[11].xxxx
  6: MUL TEMP[1].xyz, TEMP[0].xyzz, IN[0].xyzz
  7: MIN TEMP[3].x, TEMP[3].xxxx, CONST[11].zzzz
  8: MOV_SAT TEMP[3].x, TEMP[3].xxxx
  9: MUL TEMP[1].xyz, TEMP[2].xyzz, TEMP[1].xyzz
 10: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[3].xxxx
 11: MAD TEMP[2].xyz, TEMP[1].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 12: MUL TEMP[2].xyz, TEMP[3].xxxx, TEMP[2].xyzz
 13: MUL TEMP[3].x, IN[0].wwww, CONST[12].wwww
 14: MAD TEMP[1].xyz, TEMP[1].xyzz, CONST[30].xxxx, TEMP[2].xyzz
 15: MUL TEMP[0].x, TEMP[0].wwww, TEMP[3].xxxx
 16: MOV TEMP[1].w, TEMP[0].xxxx
 17: MOV TEMP[4], TEMP[1]
 18: MOV OUT[0], TEMP[4]
 19: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 44
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 46
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 47
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 48
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 49
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 50
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 51
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 116
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 117
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 118
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 120
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %45 = load <32 x i8> addrspace(2)* %44, !tbaa !0
  %46 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0
  %48 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %49 = load <32 x i8> addrspace(2)* %48, !tbaa !0
  %50 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %53 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %54 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %55 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %56 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %57 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %59 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %6)
  %60 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %6)
  %61 = bitcast float %56 to i32
  %62 = bitcast float %57 to i32
  %63 = insertelement <2 x i32> undef, i32 %61, i32 0
  %64 = insertelement <2 x i32> %63, i32 %62, i32 1
  %65 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %64, <32 x i8> %45, <16 x i8> %47, i32 2)
  %66 = extractelement <4 x float> %65, i32 0
  %67 = extractelement <4 x float> %65, i32 1
  %68 = extractelement <4 x float> %65, i32 2
  %69 = extractelement <4 x float> %65, i32 3
  %70 = bitcast float %59 to i32
  %71 = bitcast float %60 to i32
  %72 = insertelement <2 x i32> undef, i32 %70, i32 0
  %73 = insertelement <2 x i32> %72, i32 %71, i32 1
  %74 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %73, <32 x i8> %49, <16 x i8> %51, i32 2)
  %75 = extractelement <4 x float> %74, i32 0
  %76 = extractelement <4 x float> %74, i32 1
  %77 = extractelement <4 x float> %74, i32 2
  %78 = fmul float %75, %29
  %79 = fmul float %76, %31
  %80 = fmul float %77, %33
  %81 = fsub float -0.000000e+00, %23
  %82 = fmul float %58, %27
  %83 = fadd float %82, %81
  %84 = fmul float %66, %52
  %85 = fmul float %67, %53
  %86 = fmul float %68, %54
  %87 = fcmp uge float %83, %25
  %88 = select i1 %87, float %25, float %83
  %89 = call float @llvm.AMDIL.clamp.(float %88, float 0.000000e+00, float 1.000000e+00)
  %90 = fmul float %78, %84
  %91 = fmul float %79, %85
  %92 = fmul float %80, %86
  %93 = fmul float %89, %89
  %94 = fsub float -0.000000e+00, %43
  %95 = fmul float %90, %94
  %96 = fadd float %95, %37
  %97 = fsub float -0.000000e+00, %43
  %98 = fmul float %91, %97
  %99 = fadd float %98, %39
  %100 = fsub float -0.000000e+00, %43
  %101 = fmul float %92, %100
  %102 = fadd float %101, %41
  %103 = fmul float %93, %96
  %104 = fmul float %93, %99
  %105 = fmul float %93, %102
  %106 = fmul float %55, %35
  %107 = fmul float %90, %43
  %108 = fadd float %107, %103
  %109 = fmul float %91, %43
  %110 = fadd float %109, %104
  %111 = fmul float %92, %43
  %112 = fadd float %111, %105
  %113 = fmul float %69, %106
  %114 = call i32 @llvm.SI.packf16(float %108, float %110)
  %115 = bitcast i32 %114 to float
  %116 = call i32 @llvm.SI.packf16(float %112, float %113)
  %117 = bitcast i32 %116 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %115, float %117, float %115, float %117)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%46](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%44](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6_VGPR7<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR11<def> = V_MUL_F32_e32 %VGPR5, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR2, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<tied0>, %VGPR3, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR2, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR3, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%50](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%48](tbaa=!"const")
	S_WAITCNT 127
	%VGPR8_VGPR9_VGPR10<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR8_VGPR9<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 49; mem:LD4[%30]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%42]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%38]
	S_WAITCNT 127
	%VGPR11<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 47; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 44; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR2<def> = V_SUBREV_F32_e32 %SGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 46; mem:LD4[%24]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR12<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR2, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %SGPR2, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR4, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %SGPR2, %VGPR11, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 116; mem:LD4[%36]
	S_WAITCNT 127
	%VGPR12<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR2, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %SGPR2, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR11<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR6, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR10, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10<imp-use,kill>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 118; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR8<kill>, %SGPR2<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 51; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR7, %VGPR0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7<imp-use,kill>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR0<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR3<kill>, %VGPR0<kill>, %VGPR3, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140500
c8150501
c8100400
c8110401
c0840300
c0c60500
bf8c007f
f0800f00
00430404
c8200100
c8210101
bf8c0770
10161105
c8240d02
c8250d03
c8200c02
c8210c03
c0840304
c0c60508
bf8c007f
f0800700
00430808
c0400100
bf8c0070
c0010131
bf8c007f
10041202
10061702
c0010178
bf8c007f
10040602
c0018175
bf8c007f
08160403
c8080b00
c8090b01
c001812f
bf8c007f
10040403
c001812c
bf8c007f
0a040403
c001812e
bf8c007f
d00c0004
02000702
7e180203
d2000002
00121902
d2060802
02010102
10040502
10161702
d2820003
042c0503
c82c0000
c82d0001
10161704
c0018130
bf8c007f
10181003
1016170c
10181602
c0018174
bf8c007f
08181803
10181902
d282000b
0430050b
5e06070b
c82c0200
c82d0201
10161706
c0018132
bf8c007f
10101403
10101708
10121002
c0018176
bf8c007f
08121203
10041302
d2820002
04080508
c8200300
c8210301
c0000133
bf8c007f
10001000
10000107
5e000102
f8001c0f
00030003
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL CONST[0..20]
DCL TEMP[0..7], LOCAL
  0: MAD TEMP[0], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy
  1: DP4 TEMP[1].x, TEMP[0], CONST[17]
  2: DP4 TEMP[2].x, TEMP[0], CONST[18]
  3: MOV TEMP[1].y, TEMP[2].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[19]
  5: MOV TEMP[1].z, TEMP[2].xxxx
  6: DP4 TEMP[2].x, TEMP[0], CONST[4]
  7: DP4 TEMP[3].x, TEMP[0], CONST[5]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[0], CONST[12]
 10: DP4 TEMP[5].x, TEMP[0], CONST[6]
 11: MOV TEMP[2].z, TEMP[5].xxxx
 12: DP4 TEMP[0].x, TEMP[0], CONST[7]
 13: MOV TEMP[2].w, TEMP[0].xxxx
 14: MOV TEMP[1].w, TEMP[4].xxxx
 15: MOV TEMP[4].xy, IN[1].xyxx
 16: MUL TEMP[6], IN[2].xyxx, CONST[0].yyxx
 17: MOV TEMP[7], TEMP[2]
 18: MAD TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
 19: MOV TEMP[2].z, TEMP[5].xxxx
 20: MOV TEMP[2].y, -TEMP[3].xxxx
 21: MAD TEMP[2].xy, CONST[20].xyyy, TEMP[0].xxxx, TEMP[2].xyyy
 22: MOV OUT[3], TEMP[4]
 23: MOV OUT[5], TEMP[6]
 24: MOV OUT[0], TEMP[2]
 25: MOV OUT[4], TEMP[1]
 26: MOV OUT[2], TEMP[7]
 27: MOV_SAT OUT[1], IN[3]
 28: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 16
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 17
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 18
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 19
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 20
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 21
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 22
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 23
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 24
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 25
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 26
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 27
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 28
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 29
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 30
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 31
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 48
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 49
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 50
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 51
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 68
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 69
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 70
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 71
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 72
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 73
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 74
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 75
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 76
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 77
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 78
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 79
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 80
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 81
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %86 = load <16 x i8> addrspace(2)* %85, !tbaa !0
  %87 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %86, i32 0, i32 %5)
  %88 = extractelement <4 x float> %87, i32 0
  %89 = extractelement <4 x float> %87, i32 1
  %90 = extractelement <4 x float> %87, i32 2
  %91 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %92 = load <16 x i8> addrspace(2)* %91, !tbaa !0
  %93 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %92, i32 0, i32 %5)
  %94 = extractelement <4 x float> %93, i32 0
  %95 = extractelement <4 x float> %93, i32 1
  %96 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %97 = load <16 x i8> addrspace(2)* %96, !tbaa !0
  %98 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %97, i32 0, i32 %5)
  %99 = extractelement <4 x float> %98, i32 0
  %100 = extractelement <4 x float> %98, i32 1
  %101 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %102 = load <16 x i8> addrspace(2)* %101, !tbaa !0
  %103 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %102, i32 0, i32 %5)
  %104 = extractelement <4 x float> %103, i32 0
  %105 = extractelement <4 x float> %103, i32 1
  %106 = extractelement <4 x float> %103, i32 2
  %107 = extractelement <4 x float> %103, i32 3
  %108 = fmul float %88, %14
  %109 = fadd float %108, %12
  %110 = fmul float %89, %14
  %111 = fadd float %110, %12
  %112 = fmul float %90, %14
  %113 = fadd float %112, %12
  %114 = fmul float %88, %12
  %115 = fadd float %114, %14
  %116 = fmul float %109, %58
  %117 = fmul float %111, %60
  %118 = fadd float %116, %117
  %119 = fmul float %113, %62
  %120 = fadd float %118, %119
  %121 = fmul float %115, %64
  %122 = fadd float %120, %121
  %123 = fmul float %109, %66
  %124 = fmul float %111, %68
  %125 = fadd float %123, %124
  %126 = fmul float %113, %70
  %127 = fadd float %125, %126
  %128 = fmul float %115, %72
  %129 = fadd float %127, %128
  %130 = fmul float %109, %74
  %131 = fmul float %111, %76
  %132 = fadd float %130, %131
  %133 = fmul float %113, %78
  %134 = fadd float %132, %133
  %135 = fmul float %115, %80
  %136 = fadd float %134, %135
  %137 = fmul float %109, %18
  %138 = fmul float %111, %20
  %139 = fadd float %137, %138
  %140 = fmul float %113, %22
  %141 = fadd float %139, %140
  %142 = fmul float %115, %24
  %143 = fadd float %141, %142
  %144 = fmul float %109, %26
  %145 = fmul float %111, %28
  %146 = fadd float %144, %145
  %147 = fmul float %113, %30
  %148 = fadd float %146, %147
  %149 = fmul float %115, %32
  %150 = fadd float %148, %149
  %151 = fmul float %109, %50
  %152 = fmul float %111, %52
  %153 = fadd float %151, %152
  %154 = fmul float %113, %54
  %155 = fadd float %153, %154
  %156 = fmul float %115, %56
  %157 = fadd float %155, %156
  %158 = fmul float %109, %34
  %159 = fmul float %111, %36
  %160 = fadd float %158, %159
  %161 = fmul float %113, %38
  %162 = fadd float %160, %161
  %163 = fmul float %115, %40
  %164 = fadd float %162, %163
  %165 = fmul float %109, %42
  %166 = fmul float %111, %44
  %167 = fadd float %165, %166
  %168 = fmul float %113, %46
  %169 = fadd float %167, %168
  %170 = fmul float %115, %48
  %171 = fadd float %169, %170
  %172 = fmul float %99, %14
  %173 = fmul float %100, %14
  %174 = fmul float %99, %12
  %175 = fmul float %99, %12
  %176 = fsub float -0.000000e+00, %171
  %177 = fmul float %164, %16
  %178 = fadd float %177, %176
  %179 = fsub float -0.000000e+00, %150
  %180 = fmul float %82, %171
  %181 = fadd float %180, %143
  %182 = fmul float %84, %171
  %183 = fadd float %182, %179
  %184 = call float @llvm.AMDIL.clamp.(float %104, float 0.000000e+00, float 1.000000e+00)
  %185 = call float @llvm.AMDIL.clamp.(float %105, float 0.000000e+00, float 1.000000e+00)
  %186 = call float @llvm.AMDIL.clamp.(float %106, float 0.000000e+00, float 1.000000e+00)
  %187 = call float @llvm.AMDIL.clamp.(float %107, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %184, float %185, float %186, float %187)
  %188 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %189 = load float addrspace(2)* addrspace(2)* %188, !tbaa !0
  %190 = getelementptr float addrspace(2)* %189, i32 0
  %191 = load float addrspace(2)* %190, !tbaa !0
  %192 = fmul float %191, %143
  %193 = getelementptr float addrspace(2)* %189, i32 1
  %194 = load float addrspace(2)* %193, !tbaa !0
  %195 = fmul float %194, %150
  %196 = fadd float %192, %195
  %197 = getelementptr float addrspace(2)* %189, i32 2
  %198 = load float addrspace(2)* %197, !tbaa !0
  %199 = fmul float %198, %164
  %200 = fadd float %196, %199
  %201 = getelementptr float addrspace(2)* %189, i32 3
  %202 = load float addrspace(2)* %201, !tbaa !0
  %203 = fmul float %202, %171
  %204 = fadd float %200, %203
  %205 = getelementptr float addrspace(2)* %189, i32 4
  %206 = load float addrspace(2)* %205, !tbaa !0
  %207 = fmul float %206, %143
  %208 = getelementptr float addrspace(2)* %189, i32 5
  %209 = load float addrspace(2)* %208, !tbaa !0
  %210 = fmul float %209, %150
  %211 = fadd float %207, %210
  %212 = getelementptr float addrspace(2)* %189, i32 6
  %213 = load float addrspace(2)* %212, !tbaa !0
  %214 = fmul float %213, %164
  %215 = fadd float %211, %214
  %216 = getelementptr float addrspace(2)* %189, i32 7
  %217 = load float addrspace(2)* %216, !tbaa !0
  %218 = fmul float %217, %171
  %219 = fadd float %215, %218
  %220 = getelementptr float addrspace(2)* %189, i32 8
  %221 = load float addrspace(2)* %220, !tbaa !0
  %222 = fmul float %221, %143
  %223 = getelementptr float addrspace(2)* %189, i32 9
  %224 = load float addrspace(2)* %223, !tbaa !0
  %225 = fmul float %224, %150
  %226 = fadd float %222, %225
  %227 = getelementptr float addrspace(2)* %189, i32 10
  %228 = load float addrspace(2)* %227, !tbaa !0
  %229 = fmul float %228, %164
  %230 = fadd float %226, %229
  %231 = getelementptr float addrspace(2)* %189, i32 11
  %232 = load float addrspace(2)* %231, !tbaa !0
  %233 = fmul float %232, %171
  %234 = fadd float %230, %233
  %235 = getelementptr float addrspace(2)* %189, i32 12
  %236 = load float addrspace(2)* %235, !tbaa !0
  %237 = fmul float %236, %143
  %238 = getelementptr float addrspace(2)* %189, i32 13
  %239 = load float addrspace(2)* %238, !tbaa !0
  %240 = fmul float %239, %150
  %241 = fadd float %237, %240
  %242 = getelementptr float addrspace(2)* %189, i32 14
  %243 = load float addrspace(2)* %242, !tbaa !0
  %244 = fmul float %243, %164
  %245 = fadd float %241, %244
  %246 = getelementptr float addrspace(2)* %189, i32 15
  %247 = load float addrspace(2)* %246, !tbaa !0
  %248 = fmul float %247, %171
  %249 = fadd float %245, %248
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %204, float %219, float %234, float %249)
  %250 = getelementptr float addrspace(2)* %189, i32 16
  %251 = load float addrspace(2)* %250, !tbaa !0
  %252 = fmul float %251, %143
  %253 = getelementptr float addrspace(2)* %189, i32 17
  %254 = load float addrspace(2)* %253, !tbaa !0
  %255 = fmul float %254, %150
  %256 = fadd float %252, %255
  %257 = getelementptr float addrspace(2)* %189, i32 18
  %258 = load float addrspace(2)* %257, !tbaa !0
  %259 = fmul float %258, %164
  %260 = fadd float %256, %259
  %261 = getelementptr float addrspace(2)* %189, i32 19
  %262 = load float addrspace(2)* %261, !tbaa !0
  %263 = fmul float %262, %171
  %264 = fadd float %260, %263
  %265 = getelementptr float addrspace(2)* %189, i32 20
  %266 = load float addrspace(2)* %265, !tbaa !0
  %267 = fmul float %266, %143
  %268 = getelementptr float addrspace(2)* %189, i32 21
  %269 = load float addrspace(2)* %268, !tbaa !0
  %270 = fmul float %269, %150
  %271 = fadd float %267, %270
  %272 = getelementptr float addrspace(2)* %189, i32 22
  %273 = load float addrspace(2)* %272, !tbaa !0
  %274 = fmul float %273, %164
  %275 = fadd float %271, %274
  %276 = getelementptr float addrspace(2)* %189, i32 23
  %277 = load float addrspace(2)* %276, !tbaa !0
  %278 = fmul float %277, %171
  %279 = fadd float %275, %278
  %280 = getelementptr float addrspace(2)* %189, i32 24
  %281 = load float addrspace(2)* %280, !tbaa !0
  %282 = fmul float %281, %143
  %283 = getelementptr float addrspace(2)* %189, i32 25
  %284 = load float addrspace(2)* %283, !tbaa !0
  %285 = fmul float %284, %150
  %286 = fadd float %282, %285
  %287 = getelementptr float addrspace(2)* %189, i32 26
  %288 = load float addrspace(2)* %287, !tbaa !0
  %289 = fmul float %288, %164
  %290 = fadd float %286, %289
  %291 = getelementptr float addrspace(2)* %189, i32 27
  %292 = load float addrspace(2)* %291, !tbaa !0
  %293 = fmul float %292, %171
  %294 = fadd float %290, %293
  %295 = getelementptr float addrspace(2)* %189, i32 28
  %296 = load float addrspace(2)* %295, !tbaa !0
  %297 = fmul float %296, %143
  %298 = getelementptr float addrspace(2)* %189, i32 29
  %299 = load float addrspace(2)* %298, !tbaa !0
  %300 = fmul float %299, %150
  %301 = fadd float %297, %300
  %302 = getelementptr float addrspace(2)* %189, i32 30
  %303 = load float addrspace(2)* %302, !tbaa !0
  %304 = fmul float %303, %164
  %305 = fadd float %301, %304
  %306 = getelementptr float addrspace(2)* %189, i32 31
  %307 = load float addrspace(2)* %306, !tbaa !0
  %308 = fmul float %307, %171
  %309 = fadd float %305, %308
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %264, float %279, float %294, float %309)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %94, float %95, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %122, float %129, float %136, float %157)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %172, float %173, float %174, float %175)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %181, float %183, float %178, float %171)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%101](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_ADD_F32_e64 %VGPR4, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 %VGPR3, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR2, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 %VGPR1, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%85](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%13]
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 0; mem:LD4[%11]
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR4, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR4, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 17; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 16; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR8, %SGPR4, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 18; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6, %SGPR5, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 19; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 21; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 20; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 22; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 23; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%188](tbaa=!"const")
	S_WAITCNT 127
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%238]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%235]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 25; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 24; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 26; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 27; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%242]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 29; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 28; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR2, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 30; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR5, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 31; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR6, %SGPR8<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%246]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%223]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%220]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%227]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%231]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%208]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%205]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%212]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%216]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%193]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%190]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%197]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%201]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%298]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%295]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%302]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%306]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%283]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%280]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%287]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%291]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%268]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%265]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%272]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%276]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR8<kill>, %VGPR8, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%253]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%250]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%257]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR8<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%261]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR12<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%91](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR9, %VGPR10, %VGPR13<kill>, %VGPR13, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 49; mem:LD4[%51]
	S_WAITCNT 15
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 48; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 50; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 51; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 77; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 76; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 78; mem:LD4[%77]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 79; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 73; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 72; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR2, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 74; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 75; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR6, %SGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 69; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 68; mem:LD4[%57]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 70; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR5<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 71; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR2<kill>, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 8; mem:LD16[%96](tbaa=!"const")
	S_WAITCNT 15
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4, %VGPR10, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	EXP 15, 35, 0, 0, 0, %VGPR4<kill>, %VGPR2<kill>, %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 80; mem:LD4[%81]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR8, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 81; mem:LD4[%83]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR8<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c084070c
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0840700
bf8c000f
e00c2000
80020600
c0410100
bf8c0070
c0020301
c0028300
bf8c007f
7e020205
d2820002
04040906
d2820004
04040907
c0040311
bf8c007f
10060808
c0040310
bf8c007f
d2820003
040c1102
d2820005
04040908
c0040312
bf8c007f
d2820001
040c1105
7e060204
d2820006
040c0b06
c0040313
bf8c007f
d2820001
04041106
c0040315
bf8c007f
10060808
c0040314
bf8c007f
d2820003
040c1102
c0040316
bf8c007f
d2820003
040c1105
c0040317
bf8c007f
d2820003
040c1106
c0400102
bf8c007f
c004010d
bf8c007f
100e0608
c004010c
bf8c007f
d2820008
041e0208
c0040319
bf8c007f
100e0808
c0040318
bf8c007f
d2820007
041c1102
c004031a
bf8c007f
d2820007
041c1105
c004031b
bf8c007f
d2820007
041c1106
c004010e
bf8c007f
d2820009
04220e08
c004031d
bf8c007f
10100808
c004031c
bf8c007f
d2820008
04201102
c004031e
bf8c007f
d2820008
04201105
c004031f
bf8c007f
d2820008
04201106
c004010f
bf8c007f
d2820009
04261008
c0040109
bf8c007f
10140608
c0040108
bf8c007f
d282000a
042a0208
c004010a
bf8c007f
d282000a
042a0e08
c004010b
bf8c007f
d282000a
042a1008
c0040105
bf8c007f
10160608
c0040104
bf8c007f
d282000b
042e0208
c0040106
bf8c007f
d282000b
042e0e08
c0040107
bf8c007f
d282000b
042e1008
c0040101
bf8c007f
10180608
c0040100
bf8c007f
d282000c
04320208
c0040102
bf8c007f
d282000c
04320e08
c0040103
bf8c007f
d282000c
04321008
f80000ef
090a0b0c
c004011d
bf8c000f
10120608
c004011c
bf8c007f
d2820009
04260208
c004011e
bf8c007f
d2820009
04260e08
c004011f
bf8c007f
d2820009
04261008
c0040119
bf8c007f
10140608
c0040118
bf8c007f
d282000a
042a0208
c004011a
bf8c007f
d282000a
042a0e08
c004011b
bf8c007f
d282000a
042a1008
c0040115
bf8c007f
10160608
c0040114
bf8c007f
d282000b
042e0208
c0040116
bf8c007f
d282000b
042e0e08
c0040117
bf8c007f
d282000b
042e1008
c0040111
bf8c007f
10180608
c0040110
bf8c007f
d282000c
04320208
c0040112
bf8c007f
d282000c
04320e08
c0000113
bf8c007f
d282000c
04321000
f80000ff
090a0b0c
c0840704
bf8c000f
e00c2000
80020900
7e1a0280
bf8c0770
f800021f
0d0d0a09
c0000331
bf8c000f
10120800
c0000330
bf8c007f
d2820009
04240102
c0000332
bf8c007f
d2820009
04240105
c0000333
bf8c007f
d2820009
04240106
c000034d
bf8c007f
10140800
c000034c
bf8c007f
d282000a
04280102
c000034e
bf8c007f
d282000a
04280105
c000034f
bf8c007f
d282000a
04280106
c0000349
bf8c007f
10160800
c0000348
bf8c007f
d282000b
042c0102
c000034a
bf8c007f
d282000b
042c0105
c000034b
bf8c007f
d282000b
042c0106
c0000345
bf8c007f
10080800
c0000344
bf8c007f
d2820002
04100102
c0000346
bf8c007f
d2820002
04080105
c0000347
bf8c007f
d2820002
04080106
f800022f
090a0b02
c0840708
bf8c000f
e00c2000
80020900
bf8c0770
10001205
10041404
10081204
f800023f
00000204
c0000350
bf8c000f
d2820000
04061000
c0000302
bf8c007f
10020e00
08021101
c0000351
bf8c007f
10041000
08040702
f80008cf
08010200
bf810000
FRAG
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE, CENTROID
DCL IN[3], GENERIC[21], PERSPECTIVE, CENTROID
DCL IN[4], GENERIC[22], PERSPECTIVE, CENTROID
DCL IN[5], GENERIC[23], PERSPECTIVE, CENTROID
DCL IN[6], GENERIC[24], PERSPECTIVE, CENTROID
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..3]
DCL TEMP[0..4], LOCAL
DCL TEMP[5], ARRAY(1), LOCAL
IMM[0] FLT32 {    0.2000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[2].xyyy
  1: TEX TEMP[0].w, TEMP[0], SAMP[0], 2D
  2: MOV TEMP[1].xy, IN[4].xyyy
  3: TEX TEMP[1].w, TEMP[1], SAMP[0], 2D
  4: MOV TEMP[2].xy, IN[5].xyyy
  5: TEX TEMP[2].w, TEMP[2], SAMP[0], 2D
  6: MOV TEMP[3].xy, IN[6].xyyy
  7: TEX TEMP[3].w, TEMP[3], SAMP[0], 2D
  8: MOV TEMP[4].xy, IN[3].xyyy
  9: TEX TEMP[4].w, TEMP[4], SAMP[0], 2D
 10: ADD TEMP[4].x, TEMP[0].wwww, TEMP[4].wwww
 11: ADD TEMP[1].x, TEMP[1].wwww, TEMP[4].xxxx
 12: ADD TEMP[1].x, TEMP[2].wwww, TEMP[1].xxxx
 13: ADD TEMP[1].x, TEMP[3].wwww, TEMP[1].xxxx
 14: MAD TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx, -IN[0].wwww
 15: MOV_SAT TEMP[1].x, TEMP[1].xxxx
 16: MAD TEMP[2].x, IN[1].wwww, CONST[3].wwww, -CONST[3].xxxx
 17: MIN TEMP[2].x, TEMP[2].xxxx, CONST[3].zzzz
 18: MOV_SAT TEMP[2].x, TEMP[2].xxxx
 19: MAD TEMP[0].xyz, TEMP[1].xxxx, CONST[1].xyzz, -TEMP[1].xxxx
 20: ADD TEMP[1].x, -TEMP[2].xxxx, IMM[0].yyyy
 21: ADD TEMP[0].xyz, TEMP[0].xyzz, IMM[0].yyyy
 22: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 23: ADD TEMP[0].xyz, -TEMP[0].xyzz, IMM[0].yyyy
 24: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 25: MAD TEMP[0].xyz, TEMP[0].xyzz, -TEMP[1].xxxx, IMM[0].yyyy
 26: MOV TEMP[0].w, IMM[0].yyyy
 27: MOV TEMP[5], TEMP[0]
 28: MOV OUT[0], TEMP[5]
 29: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 4
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 5
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 6
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 12
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 14
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 15
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %35 = load <32 x i8> addrspace(2)* %34, !tbaa !0
  %36 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
  %38 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %39 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %40 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %6)
  %41 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %6)
  %42 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %6)
  %43 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %6)
  %44 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %6)
  %45 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %6)
  %46 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %6)
  %47 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %6)
  %48 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %6)
  %49 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %6)
  %50 = bitcast float %40 to i32
  %51 = bitcast float %41 to i32
  %52 = insertelement <2 x i32> undef, i32 %50, i32 0
  %53 = insertelement <2 x i32> %52, i32 %51, i32 1
  %54 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %53, <32 x i8> %35, <16 x i8> %37, i32 2)
  %55 = extractelement <4 x float> %54, i32 3
  %56 = bitcast float %44 to i32
  %57 = bitcast float %45 to i32
  %58 = insertelement <2 x i32> undef, i32 %56, i32 0
  %59 = insertelement <2 x i32> %58, i32 %57, i32 1
  %60 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %59, <32 x i8> %35, <16 x i8> %37, i32 2)
  %61 = extractelement <4 x float> %60, i32 3
  %62 = bitcast float %46 to i32
  %63 = bitcast float %47 to i32
  %64 = insertelement <2 x i32> undef, i32 %62, i32 0
  %65 = insertelement <2 x i32> %64, i32 %63, i32 1
  %66 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %65, <32 x i8> %35, <16 x i8> %37, i32 2)
  %67 = extractelement <4 x float> %66, i32 3
  %68 = bitcast float %48 to i32
  %69 = bitcast float %49 to i32
  %70 = insertelement <2 x i32> undef, i32 %68, i32 0
  %71 = insertelement <2 x i32> %70, i32 %69, i32 1
  %72 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %71, <32 x i8> %35, <16 x i8> %37, i32 2)
  %73 = extractelement <4 x float> %72, i32 3
  %74 = bitcast float %42 to i32
  %75 = bitcast float %43 to i32
  %76 = insertelement <2 x i32> undef, i32 %74, i32 0
  %77 = insertelement <2 x i32> %76, i32 %75, i32 1
  %78 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %77, <32 x i8> %35, <16 x i8> %37, i32 2)
  %79 = extractelement <4 x float> %78, i32 3
  %80 = fadd float %55, %79
  %81 = fadd float %61, %80
  %82 = fadd float %67, %81
  %83 = fadd float %73, %82
  %84 = fsub float -0.000000e+00, %38
  %85 = fmul float %83, 0x3FC99999A0000000
  %86 = fadd float %85, %84
  %87 = call float @llvm.AMDIL.clamp.(float %86, float 0.000000e+00, float 1.000000e+00)
  %88 = fsub float -0.000000e+00, %29
  %89 = fmul float %39, %33
  %90 = fadd float %89, %88
  %91 = fcmp uge float %90, %31
  %92 = select i1 %91, float %31, float %90
  %93 = call float @llvm.AMDIL.clamp.(float %92, float 0.000000e+00, float 1.000000e+00)
  %94 = fsub float -0.000000e+00, %87
  %95 = fmul float %87, %23
  %96 = fadd float %95, %94
  %97 = fsub float -0.000000e+00, %87
  %98 = fmul float %87, %25
  %99 = fadd float %98, %97
  %100 = fsub float -0.000000e+00, %87
  %101 = fmul float %87, %27
  %102 = fadd float %101, %100
  %103 = fsub float -0.000000e+00, %93
  %104 = fadd float %103, 1.000000e+00
  %105 = fadd float %96, 1.000000e+00
  %106 = fadd float %99, 1.000000e+00
  %107 = fadd float %102, 1.000000e+00
  %108 = fmul float %104, %104
  %109 = fsub float -0.000000e+00, %105
  %110 = fadd float %109, 1.000000e+00
  %111 = fsub float -0.000000e+00, %106
  %112 = fadd float %111, 1.000000e+00
  %113 = fsub float -0.000000e+00, %107
  %114 = fadd float %113, 1.000000e+00
  %115 = fmul float %108, %108
  %116 = fsub float -0.000000e+00, %115
  %117 = fmul float %110, %116
  %118 = fadd float %117, 1.000000e+00
  %119 = fsub float -0.000000e+00, %115
  %120 = fmul float %112, %119
  %121 = fadd float %120, 1.000000e+00
  %122 = fsub float -0.000000e+00, %115
  %123 = fmul float %114, %122
  %124 = fadd float %123, 1.000000e+00
  %125 = call i32 @llvm.SI.packf16(float %118, float %121)
  %126 = bitcast i32 %125 to float
  %127 = call i32 @llvm.SI.packf16(float %124, float 1.000000e+00)
  %128 = bitcast i32 %127 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %126, float %128, float %126, float %128)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5, %VGPR2 in %vreg6, %VGPR3 in %vreg7

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR3<def> = KILL %VGPR3, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = KILL %VGPR2, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR2, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR3, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR2, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR3, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%36](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%34](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR2, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR3, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR2, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR3, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_ADD_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR2, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR3, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR2, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR3, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_ADD_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR2, 1, 5, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR3, 1, 5, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR2, 0, 5, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR3, 0, 5, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_ADD_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR2, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR3, 1, 6, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR2, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR3, 0, 6, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR2<def> = IMAGE_SAMPLE 8, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_ADD_F32_e32 %VGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 2.000000e-01, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%24]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR2<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%30]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR0, %SGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_SUB_F32_e32 1.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 1.000000e+00, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 6; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e32 1.000000e+00, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 1.000000e+00, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_SUB_F32_e32 1.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 %VGPR0<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c8140d02
c8150d03
c8100c02
c8110c03
c0840300
c0c60500
bf8c007f
f0800800
00430404
c8180902
c8190903
c8140802
c8150803
f0800800
00430505
bf8c0770
06080905
c8181102
c8191103
c8141002
c8151003
f0800800
00430505
bf8c0770
06080905
c8181502
c8191503
c8141402
c8151403
f0800800
00430505
bf8c0770
06080905
c8181902
c8191903
c8141802
c8151803
f0800800
00430205
bf8c0770
06040902
100404ff
3e4ccccd
c80c0300
c80d0301
08040702
d2060802
02010102
c0400100
bf8c007f
c0010105
bf8c007f
10060402
08060503
060606f2
080606f2
c8100700
c8110701
c001010f
bf8c007f
10000802
c001010c
bf8c007f
0a000002
c001010e
bf8c007f
d00c0004
02000500
7e020202
d2000000
00120300
d2060800
02010100
080000f2
10000100
10000100
10020103
080202f2
c0010104
bf8c007f
10060402
08060503
060606f2
080606f2
10060103
080606f2
5e020303
c0000106
bf8c007f
10060400
08040503
060404f2
080404f2
10000102
080000f2
d25e0000
0201e500
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], CLIPVERTEX
DCL OUT[3], GENERIC[19]
DCL OUT[4], GENERIC[20]
DCL OUT[5], GENERIC[21]
DCL OUT[6], GENERIC[22]
DCL OUT[7], GENERIC[23]
DCL OUT[8], GENERIC[24]
DCL CONST[0..55]
DCL TEMP[0..10], LOCAL
  0: MOV TEMP[0].w, CONST[0].yyyy
  1: DP4 TEMP[0].x, IN[0], CONST[52]
  2: DP4 TEMP[1].x, IN[0], CONST[53]
  3: MOV TEMP[0].y, TEMP[1].xxxx
  4: DP4 TEMP[1].x, IN[0], CONST[54]
  5: MOV TEMP[0].z, TEMP[1].xxxx
  6: DP4 TEMP[1].x, TEMP[0], CONST[8]
  7: DP4 TEMP[2].x, TEMP[0], CONST[9]
  8: MOV TEMP[1].y, TEMP[2].xxxx
  9: DP4 TEMP[3].x, TEMP[0], CONST[10]
 10: MOV TEMP[1].z, TEMP[3].xxxx
 11: DP4 TEMP[4].x, TEMP[0], CONST[11]
 12: MOV TEMP[1].w, TEMP[4].xxxx
 13: DP4 TEMP[5].x, TEMP[0], CONST[13]
 14: DP4 TEMP[6].x, IN[2], CONST[48]
 15: DP4 TEMP[7].x, IN[2], CONST[49]
 16: MOV TEMP[6].y, TEMP[7].xxxx
 17: MOV TEMP[0].xyz, TEMP[0].xyzx
 18: ADD TEMP[7].xy, TEMP[6].xyyy, CONST[50].xyyy
 19: ADD TEMP[8].xy, TEMP[6].xyyy, -CONST[50].xyyy
 20: ADD TEMP[9].xy, TEMP[6].xyyy, CONST[51].xyyy
 21: ADD TEMP[10].xy, TEMP[6].xyyy, -CONST[51].xyyy
 22: MOV TEMP[6].xy, TEMP[6].xyxx
 23: MOV TEMP[0].w, TEMP[5].xxxx
 24: MOV TEMP[5], TEMP[1]
 25: MAD TEMP[3].x, TEMP[3].xxxx, CONST[0].zzzz, -TEMP[4].xxxx
 26: MOV TEMP[1].z, TEMP[3].xxxx
 27: MOV TEMP[1].y, -TEMP[2].xxxx
 28: MAD TEMP[1].xy, CONST[55].xyyy, TEMP[4].xxxx, TEMP[1].xyyy
 29: MOV OUT[4], TEMP[6]
 30: MOV OUT[5], TEMP[7]
 31: MOV OUT[6], TEMP[8]
 32: MOV OUT[7], TEMP[9]
 33: MOV OUT[0], TEMP[1]
 34: MOV OUT[8], TEMP[10]
 35: MOV OUT[2], TEMP[5]
 36: MOV OUT[3], TEMP[0]
 37: MOV_SAT OUT[1], IN[1]
 38: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 1
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 2
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 32
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 33
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 34
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 35
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 36
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 37
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 38
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 39
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 40
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 41
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 42
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 43
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 44
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 45
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 46
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 47
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 52
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 53
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 54
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 55
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 192
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 193
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 194
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 195
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 196
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 197
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 198
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 199
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 200
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 201
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 204
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 205
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 208
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 209
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 210
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 211
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr float addrspace(2)* %10, i32 212
  %88 = load float addrspace(2)* %87, !tbaa !0
  %89 = getelementptr float addrspace(2)* %10, i32 213
  %90 = load float addrspace(2)* %89, !tbaa !0
  %91 = getelementptr float addrspace(2)* %10, i32 214
  %92 = load float addrspace(2)* %91, !tbaa !0
  %93 = getelementptr float addrspace(2)* %10, i32 215
  %94 = load float addrspace(2)* %93, !tbaa !0
  %95 = getelementptr float addrspace(2)* %10, i32 216
  %96 = load float addrspace(2)* %95, !tbaa !0
  %97 = getelementptr float addrspace(2)* %10, i32 217
  %98 = load float addrspace(2)* %97, !tbaa !0
  %99 = getelementptr float addrspace(2)* %10, i32 218
  %100 = load float addrspace(2)* %99, !tbaa !0
  %101 = getelementptr float addrspace(2)* %10, i32 219
  %102 = load float addrspace(2)* %101, !tbaa !0
  %103 = getelementptr float addrspace(2)* %10, i32 220
  %104 = load float addrspace(2)* %103, !tbaa !0
  %105 = getelementptr float addrspace(2)* %10, i32 221
  %106 = load float addrspace(2)* %105, !tbaa !0
  %107 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %108 = load <16 x i8> addrspace(2)* %107, !tbaa !0
  %109 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %108, i32 0, i32 %5)
  %110 = extractelement <4 x float> %109, i32 0
  %111 = extractelement <4 x float> %109, i32 1
  %112 = extractelement <4 x float> %109, i32 2
  %113 = extractelement <4 x float> %109, i32 3
  %114 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %115 = load <16 x i8> addrspace(2)* %114, !tbaa !0
  %116 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %115, i32 0, i32 %5)
  %117 = extractelement <4 x float> %116, i32 0
  %118 = extractelement <4 x float> %116, i32 1
  %119 = extractelement <4 x float> %116, i32 2
  %120 = extractelement <4 x float> %116, i32 3
  %121 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %122 = load <16 x i8> addrspace(2)* %121, !tbaa !0
  %123 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %122, i32 0, i32 %5)
  %124 = extractelement <4 x float> %123, i32 0
  %125 = extractelement <4 x float> %123, i32 1
  %126 = extractelement <4 x float> %123, i32 2
  %127 = extractelement <4 x float> %123, i32 3
  %128 = fmul float %110, %80
  %129 = fmul float %111, %82
  %130 = fadd float %128, %129
  %131 = fmul float %112, %84
  %132 = fadd float %130, %131
  %133 = fmul float %113, %86
  %134 = fadd float %132, %133
  %135 = fmul float %110, %88
  %136 = fmul float %111, %90
  %137 = fadd float %135, %136
  %138 = fmul float %112, %92
  %139 = fadd float %137, %138
  %140 = fmul float %113, %94
  %141 = fadd float %139, %140
  %142 = fmul float %110, %96
  %143 = fmul float %111, %98
  %144 = fadd float %142, %143
  %145 = fmul float %112, %100
  %146 = fadd float %144, %145
  %147 = fmul float %113, %102
  %148 = fadd float %146, %147
  %149 = fmul float %134, %16
  %150 = fmul float %141, %18
  %151 = fadd float %149, %150
  %152 = fmul float %148, %20
  %153 = fadd float %151, %152
  %154 = fmul float %12, %22
  %155 = fadd float %153, %154
  %156 = fmul float %134, %24
  %157 = fmul float %141, %26
  %158 = fadd float %156, %157
  %159 = fmul float %148, %28
  %160 = fadd float %158, %159
  %161 = fmul float %12, %30
  %162 = fadd float %160, %161
  %163 = fmul float %134, %32
  %164 = fmul float %141, %34
  %165 = fadd float %163, %164
  %166 = fmul float %148, %36
  %167 = fadd float %165, %166
  %168 = fmul float %12, %38
  %169 = fadd float %167, %168
  %170 = fmul float %134, %40
  %171 = fmul float %141, %42
  %172 = fadd float %170, %171
  %173 = fmul float %148, %44
  %174 = fadd float %172, %173
  %175 = fmul float %12, %46
  %176 = fadd float %174, %175
  %177 = fmul float %134, %48
  %178 = fmul float %141, %50
  %179 = fadd float %177, %178
  %180 = fmul float %148, %52
  %181 = fadd float %179, %180
  %182 = fmul float %12, %54
  %183 = fadd float %181, %182
  %184 = fmul float %124, %56
  %185 = fmul float %125, %58
  %186 = fadd float %184, %185
  %187 = fmul float %126, %60
  %188 = fadd float %186, %187
  %189 = fmul float %127, %62
  %190 = fadd float %188, %189
  %191 = fmul float %124, %64
  %192 = fmul float %125, %66
  %193 = fadd float %191, %192
  %194 = fmul float %126, %68
  %195 = fadd float %193, %194
  %196 = fmul float %127, %70
  %197 = fadd float %195, %196
  %198 = fadd float %190, %72
  %199 = fadd float %197, %74
  %200 = fsub float -0.000000e+00, %72
  %201 = fadd float %190, %200
  %202 = fsub float -0.000000e+00, %74
  %203 = fadd float %197, %202
  %204 = fadd float %190, %76
  %205 = fadd float %197, %78
  %206 = fsub float -0.000000e+00, %76
  %207 = fadd float %190, %206
  %208 = fsub float -0.000000e+00, %78
  %209 = fadd float %197, %208
  %210 = fsub float -0.000000e+00, %176
  %211 = fmul float %169, %14
  %212 = fadd float %211, %210
  %213 = fsub float -0.000000e+00, %162
  %214 = fmul float %104, %176
  %215 = fadd float %214, %155
  %216 = fmul float %106, %176
  %217 = fadd float %216, %213
  %218 = call float @llvm.AMDIL.clamp.(float %117, float 0.000000e+00, float 1.000000e+00)
  %219 = call float @llvm.AMDIL.clamp.(float %118, float 0.000000e+00, float 1.000000e+00)
  %220 = call float @llvm.AMDIL.clamp.(float %119, float 0.000000e+00, float 1.000000e+00)
  %221 = call float @llvm.AMDIL.clamp.(float %120, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %218, float %219, float %220, float %221)
  %222 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %223 = load float addrspace(2)* addrspace(2)* %222, !tbaa !0
  %224 = getelementptr float addrspace(2)* %223, i32 0
  %225 = load float addrspace(2)* %224, !tbaa !0
  %226 = fmul float %225, %155
  %227 = getelementptr float addrspace(2)* %223, i32 1
  %228 = load float addrspace(2)* %227, !tbaa !0
  %229 = fmul float %228, %162
  %230 = fadd float %226, %229
  %231 = getelementptr float addrspace(2)* %223, i32 2
  %232 = load float addrspace(2)* %231, !tbaa !0
  %233 = fmul float %232, %169
  %234 = fadd float %230, %233
  %235 = getelementptr float addrspace(2)* %223, i32 3
  %236 = load float addrspace(2)* %235, !tbaa !0
  %237 = fmul float %236, %176
  %238 = fadd float %234, %237
  %239 = getelementptr float addrspace(2)* %223, i32 4
  %240 = load float addrspace(2)* %239, !tbaa !0
  %241 = fmul float %240, %155
  %242 = getelementptr float addrspace(2)* %223, i32 5
  %243 = load float addrspace(2)* %242, !tbaa !0
  %244 = fmul float %243, %162
  %245 = fadd float %241, %244
  %246 = getelementptr float addrspace(2)* %223, i32 6
  %247 = load float addrspace(2)* %246, !tbaa !0
  %248 = fmul float %247, %169
  %249 = fadd float %245, %248
  %250 = getelementptr float addrspace(2)* %223, i32 7
  %251 = load float addrspace(2)* %250, !tbaa !0
  %252 = fmul float %251, %176
  %253 = fadd float %249, %252
  %254 = getelementptr float addrspace(2)* %223, i32 8
  %255 = load float addrspace(2)* %254, !tbaa !0
  %256 = fmul float %255, %155
  %257 = getelementptr float addrspace(2)* %223, i32 9
  %258 = load float addrspace(2)* %257, !tbaa !0
  %259 = fmul float %258, %162
  %260 = fadd float %256, %259
  %261 = getelementptr float addrspace(2)* %223, i32 10
  %262 = load float addrspace(2)* %261, !tbaa !0
  %263 = fmul float %262, %169
  %264 = fadd float %260, %263
  %265 = getelementptr float addrspace(2)* %223, i32 11
  %266 = load float addrspace(2)* %265, !tbaa !0
  %267 = fmul float %266, %176
  %268 = fadd float %264, %267
  %269 = getelementptr float addrspace(2)* %223, i32 12
  %270 = load float addrspace(2)* %269, !tbaa !0
  %271 = fmul float %270, %155
  %272 = getelementptr float addrspace(2)* %223, i32 13
  %273 = load float addrspace(2)* %272, !tbaa !0
  %274 = fmul float %273, %162
  %275 = fadd float %271, %274
  %276 = getelementptr float addrspace(2)* %223, i32 14
  %277 = load float addrspace(2)* %276, !tbaa !0
  %278 = fmul float %277, %169
  %279 = fadd float %275, %278
  %280 = getelementptr float addrspace(2)* %223, i32 15
  %281 = load float addrspace(2)* %280, !tbaa !0
  %282 = fmul float %281, %176
  %283 = fadd float %279, %282
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %238, float %253, float %268, float %283)
  %284 = getelementptr float addrspace(2)* %223, i32 16
  %285 = load float addrspace(2)* %284, !tbaa !0
  %286 = fmul float %285, %155
  %287 = getelementptr float addrspace(2)* %223, i32 17
  %288 = load float addrspace(2)* %287, !tbaa !0
  %289 = fmul float %288, %162
  %290 = fadd float %286, %289
  %291 = getelementptr float addrspace(2)* %223, i32 18
  %292 = load float addrspace(2)* %291, !tbaa !0
  %293 = fmul float %292, %169
  %294 = fadd float %290, %293
  %295 = getelementptr float addrspace(2)* %223, i32 19
  %296 = load float addrspace(2)* %295, !tbaa !0
  %297 = fmul float %296, %176
  %298 = fadd float %294, %297
  %299 = getelementptr float addrspace(2)* %223, i32 20
  %300 = load float addrspace(2)* %299, !tbaa !0
  %301 = fmul float %300, %155
  %302 = getelementptr float addrspace(2)* %223, i32 21
  %303 = load float addrspace(2)* %302, !tbaa !0
  %304 = fmul float %303, %162
  %305 = fadd float %301, %304
  %306 = getelementptr float addrspace(2)* %223, i32 22
  %307 = load float addrspace(2)* %306, !tbaa !0
  %308 = fmul float %307, %169
  %309 = fadd float %305, %308
  %310 = getelementptr float addrspace(2)* %223, i32 23
  %311 = load float addrspace(2)* %310, !tbaa !0
  %312 = fmul float %311, %176
  %313 = fadd float %309, %312
  %314 = getelementptr float addrspace(2)* %223, i32 24
  %315 = load float addrspace(2)* %314, !tbaa !0
  %316 = fmul float %315, %155
  %317 = getelementptr float addrspace(2)* %223, i32 25
  %318 = load float addrspace(2)* %317, !tbaa !0
  %319 = fmul float %318, %162
  %320 = fadd float %316, %319
  %321 = getelementptr float addrspace(2)* %223, i32 26
  %322 = load float addrspace(2)* %321, !tbaa !0
  %323 = fmul float %322, %169
  %324 = fadd float %320, %323
  %325 = getelementptr float addrspace(2)* %223, i32 27
  %326 = load float addrspace(2)* %325, !tbaa !0
  %327 = fmul float %326, %176
  %328 = fadd float %324, %327
  %329 = getelementptr float addrspace(2)* %223, i32 28
  %330 = load float addrspace(2)* %329, !tbaa !0
  %331 = fmul float %330, %155
  %332 = getelementptr float addrspace(2)* %223, i32 29
  %333 = load float addrspace(2)* %332, !tbaa !0
  %334 = fmul float %333, %162
  %335 = fadd float %331, %334
  %336 = getelementptr float addrspace(2)* %223, i32 30
  %337 = load float addrspace(2)* %336, !tbaa !0
  %338 = fmul float %337, %169
  %339 = fadd float %335, %338
  %340 = getelementptr float addrspace(2)* %223, i32 31
  %341 = load float addrspace(2)* %340, !tbaa !0
  %342 = fmul float %341, %176
  %343 = fadd float %339, %342
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %298, float %313, float %328, float %343)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %134, float %141, float %148, float %183)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %190, float %197, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %198, float %199, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %201, float %203, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %204, float %205, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %207, float %209, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %215, float %217, float %212, float %176)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%114](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_ADD_F32_e64 %VGPR4, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 %VGPR3, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR2, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 %VGPR1, 0, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%107](tbaa=!"const")
	S_WAITCNT 15
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 209; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 208; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 210; mem:LD4[%83]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 211; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR9, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 213; mem:LD4[%89]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 212; mem:LD4[%87]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 214; mem:LD4[%91]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 215; mem:LD4[%93]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR9, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 33; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 32; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR3, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 217; mem:LD4[%97]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 216; mem:LD4[%95]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 218; mem:LD4[%99]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 219; mem:LD4[%101]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR9, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 34; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%11]
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 35; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %SGPR4, %VGPR2<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 37; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 36; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR3, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 38; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR7, %SGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 39; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR4, %VGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%222](tbaa=!"const")
	S_WAITCNT 127
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%272]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%269]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 41; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 40; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR3, %SGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 42; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR7, %SGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 43; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR4, %VGPR8<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%276]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 45; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 44; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR3, %SGPR5<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 46; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR7, %SGPR5<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 47; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR4, %VGPR9<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%280]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%257]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%254]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%261]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%265]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%242]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%239]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%246]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%250]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%227]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%224]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%231]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%235]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%332]
	S_WAITCNT 15
	%VGPR8<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%329]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%336]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%340]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%317]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%314]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%321]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%325]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%302]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%299]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%306]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%310]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR5<kill>, %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%287]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%284]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR1, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%291]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR5<kill>, %VGPR4, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%295]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR11<kill>, %VGPR10<kill>, %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 53; mem:LD4[%49]
	S_WAITCNT 15
	%VGPR8<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 52; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 54; mem:LD4[%51]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 55; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %SGPR4<kill>, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR3<kill>, %VGPR5<kill>, %VGPR7<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 8; mem:LD16[%121](tbaa=!"const")
	S_WAITCNT 15
	%VGPR7_VGPR8_VGPR9_VGPR10<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%65]
	S_WAITCNT 112
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 198; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR9, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 199; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%57]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%55]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 194; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR9, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 195; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR10, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8_VGPR9_VGPR10<imp-use,kill>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR3, %VGPR0, %VGPR5, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 201; mem:LD4[%73]
	S_WAITCNT 15
	%VGPR7<def> = V_ADD_F32_e32 %SGPR0, %VGPR0, %EXEC<imp-use>
	%SGPR1<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 200; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR8<def> = V_ADD_F32_e32 %SGPR1, %VGPR3, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR8<kill>, %VGPR7<kill>, %VGPR5, %VGPR5, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR7<def> = V_SUBREV_F32_e32 %SGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR8<def> = V_SUBREV_F32_e32 %SGPR1<kill>, %VGPR3, %EXEC<imp-use>
	EXP 15, 36, 0, 0, 0, %VGPR8<kill>, %VGPR7<kill>, %VGPR5, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 205; mem:LD4[%77]
	S_WAITCNT 15
	%VGPR7<def> = V_ADD_F32_e32 %SGPR0, %VGPR0, %EXEC<imp-use>
	%SGPR1<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 204; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR8<def> = V_ADD_F32_e32 %SGPR1, %VGPR3, %EXEC<imp-use>
	EXP 15, 37, 0, 0, 0, %VGPR8<kill>, %VGPR7<kill>, %VGPR5, %VGPR5, %EXEC<imp-use>
	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 38, 0, 0, 0, %VGPR3<kill>, %VGPR0<kill>, %VGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 220; mem:LD4[%103]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%13]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 221; mem:LD4[%105]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR6<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0840700
bf8c000f
e00c2000
80020600
c0410100
bf8c0070
c00203d1
bf8c007f
10020e04
c00203d0
bf8c007f
d2820001
04040906
c00203d2
bf8c007f
d2820001
04040908
c00203d3
bf8c007f
d2820003
04040909
c00203d5
bf8c007f
10020e04
c00203d4
bf8c007f
d2820001
04040906
c00203d6
bf8c007f
d2820001
04040908
c00203d7
bf8c007f
d2820005
04040909
c0020321
bf8c007f
10020a04
c0020320
bf8c007f
d2820001
04040903
c00203d9
bf8c007f
10040e04
c00203d8
bf8c007f
d2820002
04080906
c00203da
bf8c007f
d2820002
04080908
c00203db
bf8c007f
d2820007
04080909
c0020322
bf8c007f
d2820001
04040907
c0020301
c0028323
bf8c007f
7e040205
d2820001
04060404
c0028325
bf8c007f
10040a05
c0028324
bf8c007f
d2820002
04080b03
c0028326
bf8c007f
d2820002
04080b07
c0028327
bf8c007f
7e080205
d2820002
040a0804
c0400102
bf8c007f
c002810d
bf8c007f
10080405
c002810c
bf8c007f
d2820006
04120205
c0028329
bf8c007f
10080a05
c0028328
bf8c007f
d2820004
04100b03
c002832a
bf8c007f
d2820004
04100b07
c002832b
bf8c007f
7e100205
d2820004
04121004
c002810e
bf8c007f
d2820008
041a0805
c002832d
bf8c007f
100c0a05
c002832c
bf8c007f
d2820006
04180b03
c002832e
bf8c007f
d2820006
04180b07
c002832f
bf8c007f
7e120205
d2820006
041a1204
c002810f
bf8c007f
d2820008
04220c05
c0028109
bf8c007f
10120405
c0028108
bf8c007f
d2820009
04260205
c002810a
bf8c007f
d2820009
04260805
c002810b
bf8c007f
d2820009
04260c05
c0028105
bf8c007f
10140405
c0028104
bf8c007f
d282000a
042a0205
c0028106
bf8c007f
d282000a
042a0805
c0028107
bf8c007f
d282000a
042a0c05
c0028101
bf8c007f
10160405
c0028100
bf8c007f
d282000b
042e0205
c0028102
bf8c007f
d282000b
042e0805
c0028103
bf8c007f
d282000b
042e0c05
f80000ef
08090a0b
c002811d
bf8c000f
10100405
c002811c
bf8c007f
d2820008
04220205
c002811e
bf8c007f
d2820008
04220805
c002811f
bf8c007f
d2820008
04220c05
c0028119
bf8c007f
10120405
c0028118
bf8c007f
d2820009
04260205
c002811a
bf8c007f
d2820009
04260805
c002811b
bf8c007f
d2820009
04260c05
c0028115
bf8c007f
10140405
c0028114
bf8c007f
d282000a
042a0205
c0028116
bf8c007f
d282000a
042a0805
c0028117
bf8c007f
d282000a
042a0c05
c0028111
bf8c007f
10160405
c0028110
bf8c007f
d282000b
042e0205
c0028112
bf8c007f
d282000b
042e0805
c0000113
bf8c007f
d282000b
042e0c00
f80000ff
08090a0b
c0000335
bf8c000f
10100a00
c0000334
bf8c007f
d2820008
04200103
c0000336
bf8c007f
d2820008
04200107
c0000337
bf8c007f
7e120200
d2820008
04221204
f800021f
08070503
c0820708
bf8c000f
e00c2000
80010700
c00003c5
bf8c0070
10001000
c00003c4
bf8c007f
d2820000
04000107
c00003c6
bf8c007f
d2820000
04000109
c00003c7
bf8c007f
d2820000
0400010a
c00003c1
bf8c007f
10061000
c00003c0
bf8c007f
d2820003
040c0107
c00003c2
bf8c007f
d2820003
040c0109
c00003c3
bf8c007f
d2820003
040c010a
7e0a0280
f800022f
05050003
c00003c9
bf8c000f
060e0000
c00083c8
bf8c007f
06100601
f800023f
05050708
bf8c070f
0a0e0000
0a100601
f800024f
05050708
c00003cd
bf8c000f
060e0000
c00083cc
bf8c007f
06100601
f800025f
05050708
0a000000
0a060601
f800026f
05050003
c00003dc
bf8c000f
d2820000
04060c00
c0000302
bf8c007f
10020800
08020d01
c00003dd
bf8c007f
10060c00
08040503
f80008cf
06010200
bf810000
FRAG
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL IN[3], GENERIC[22], PERSPECTIVE
DCL IN[4], GENERIC[23], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..30]
DCL TEMP[0..11], LOCAL
DCL TEMP[12], ARRAY(1), LOCAL
IMM[0] FLT32 {    2.0000,    -1.0000,     0.0000,     1.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[1], 2D
  2: MOV TEMP[1].xy, IN[0].xyyy
  3: TEX TEMP[1], TEMP[1], SAMP[0], 2D
  4: MOV TEMP[2].xy, IN[0].xyyy
  5: TEX TEMP[3].xyz, TEMP[2], SAMP[2], 2D
  6: MAD TEMP[4].xyz, IMM[0].xxxx, TEMP[0].xyzz, IMM[0].yyyy
  7: ADD TEMP[0].xyz, -TEMP[4].xyzz, IMM[0].zzww
  8: MAD TEMP[0].xyz, CONST[27].xxxx, TEMP[0].xyzz, TEMP[4].xyzz
  9: MUL TEMP[4].xyz, TEMP[0].yyyy, IN[2].xyzz
 10: MAD TEMP[4].xyz, IN[1].xyzz, TEMP[0].xxxx, TEMP[4].xyzz
 11: MAD TEMP[0].xyz, IN[3].xyzz, TEMP[0].zzzz, TEMP[4].xyzz
 12: DP3 TEMP[5].x, TEMP[0].xyzz, TEMP[0].xyzz
 13: RSQ TEMP[5].x, TEMP[5].xxxx
 14: MUL TEMP[5].xyz, TEMP[0].xyzz, TEMP[5].xxxx
 15: MUL TEMP[6].xyz, TEMP[5].xyzz, TEMP[5].xyzz
 16: SGE TEMP[7].x, TEMP[5].xxxx, IMM[0].zzzz
 17: F2I TEMP[7].x, -TEMP[7]
 18: UIF TEMP[7].xxxx :0
 19:   MOV TEMP[7].x, IMM[0].zzzz
 20: ELSE :0
 21:   MOV TEMP[7].x, TEMP[6].xxxx
 22: ENDIF
 23: SGE TEMP[8].x, TEMP[5].yyyy, IMM[0].zzzz
 24: F2I TEMP[8].x, -TEMP[8]
 25: UIF TEMP[8].xxxx :0
 26:   MOV TEMP[8].x, IMM[0].zzzz
 27: ELSE :0
 28:   MOV TEMP[8].x, TEMP[6].yyyy
 29: ENDIF
 30: SGE TEMP[9].x, TEMP[5].zzzz, IMM[0].zzzz
 31: F2I TEMP[9].x, -TEMP[9]
 32: UIF TEMP[9].xxxx :0
 33:   MOV TEMP[9].x, IMM[0].zzzz
 34: ELSE :0
 35:   MOV TEMP[9].x, TEMP[6].zzzz
 36: ENDIF
 37: SGE TEMP[10].x, TEMP[5].xxxx, IMM[0].zzzz
 38: F2I TEMP[10].x, -TEMP[10]
 39: UIF TEMP[10].xxxx :0
 40:   MOV TEMP[10].x, TEMP[6].xxxx
 41: ELSE :0
 42:   MOV TEMP[10].x, IMM[0].zzzz
 43: ENDIF
 44: SGE TEMP[11].x, TEMP[5].yyyy, IMM[0].zzzz
 45: F2I TEMP[11].x, -TEMP[11]
 46: UIF TEMP[11].xxxx :0
 47:   MOV TEMP[11].x, TEMP[6].yyyy
 48: ELSE :0
 49:   MOV TEMP[11].x, IMM[0].zzzz
 50: ENDIF
 51: SGE TEMP[5].x, TEMP[5].zzzz, IMM[0].zzzz
 52: F2I TEMP[5].x, -TEMP[5]
 53: UIF TEMP[5].xxxx :0
 54:   MOV TEMP[5].x, TEMP[6].zzzz
 55: ELSE :0
 56:   MOV TEMP[5].x, IMM[0].zzzz
 57: ENDIF
 58: MUL TEMP[6].xyz, TEMP[7].xxxx, CONST[5].xyzz
 59: MAD TEMP[6].xyz, TEMP[10].xxxx, CONST[4].xyzz, TEMP[6].xyzz
 60: MAD TEMP[6].xyz, TEMP[11].xxxx, CONST[6].xyzz, TEMP[6].xyzz
 61: MAD TEMP[6].xyz, TEMP[8].xxxx, CONST[7].xyzz, TEMP[6].xyzz
 62: MAD TEMP[4].xyz, TEMP[5].xxxx, CONST[8].xyzz, TEMP[6].xyzz
 63: MAD TEMP[0].xyz, TEMP[9].xxxx, CONST[9].xyzz, TEMP[4].xyzz
 64: MUL TEMP[2].xyz, TEMP[1].xyzz, CONST[1].xyzz
 65: MUL TEMP[4].xyz, TEMP[0].xyzz, TEMP[2].xyzz
 66: MAD TEMP[2].xyz, CONST[0].xyzz, TEMP[2].xyzz, -TEMP[4].xyzz
 67: ADD TEMP[3].xyz, TEMP[3].xyzz, -TEMP[1].wwww
 68: MAD TEMP[0].xyz, CONST[10].wwww, TEMP[3].xyzz, TEMP[1].wwww
 69: MAD TEMP[2].xyz, TEMP[0].xyzz, TEMP[2].xyzz, TEMP[4].xyzz
 70: MAD TEMP[1].x, IN[4].zzzz, CONST[12].wwww, -CONST[12].xxxx
 71: MAX TEMP[3].xyz, TEMP[2].xyzz, IMM[0].zzzz
 72: MIN TEMP[1].x, TEMP[1].xxxx, CONST[12].zzzz
 73: MOV_SAT TEMP[1].x, TEMP[1].xxxx
 74: MAD TEMP[2].xyz, TEMP[3].xyzz, -CONST[30].xxxx, CONST[29].xyzz
 75: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 76: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[1].xxxx
 77: MAD TEMP[0].xyz, TEMP[3].xyzz, CONST[30].xxxx, TEMP[2].xyzz
 78: MUL TEMP[1].x, IN[4].zzzz, CONST[29].wwww
 79: MOV TEMP[0].w, TEMP[1].xxxx
 80: MOV TEMP[12], TEMP[0]
 81: MOV OUT[0], TEMP[12]
 82: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 0
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 1
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 2
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 4
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 5
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 6
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 16
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 17
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 18
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 20
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 21
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr float addrspace(2)* %21, i32 22
  %45 = load float addrspace(2)* %44, !tbaa !0
  %46 = getelementptr float addrspace(2)* %21, i32 24
  %47 = load float addrspace(2)* %46, !tbaa !0
  %48 = getelementptr float addrspace(2)* %21, i32 25
  %49 = load float addrspace(2)* %48, !tbaa !0
  %50 = getelementptr float addrspace(2)* %21, i32 26
  %51 = load float addrspace(2)* %50, !tbaa !0
  %52 = getelementptr float addrspace(2)* %21, i32 28
  %53 = load float addrspace(2)* %52, !tbaa !0
  %54 = getelementptr float addrspace(2)* %21, i32 29
  %55 = load float addrspace(2)* %54, !tbaa !0
  %56 = getelementptr float addrspace(2)* %21, i32 30
  %57 = load float addrspace(2)* %56, !tbaa !0
  %58 = getelementptr float addrspace(2)* %21, i32 32
  %59 = load float addrspace(2)* %58, !tbaa !0
  %60 = getelementptr float addrspace(2)* %21, i32 33
  %61 = load float addrspace(2)* %60, !tbaa !0
  %62 = getelementptr float addrspace(2)* %21, i32 34
  %63 = load float addrspace(2)* %62, !tbaa !0
  %64 = getelementptr float addrspace(2)* %21, i32 36
  %65 = load float addrspace(2)* %64, !tbaa !0
  %66 = getelementptr float addrspace(2)* %21, i32 37
  %67 = load float addrspace(2)* %66, !tbaa !0
  %68 = getelementptr float addrspace(2)* %21, i32 38
  %69 = load float addrspace(2)* %68, !tbaa !0
  %70 = getelementptr float addrspace(2)* %21, i32 43
  %71 = load float addrspace(2)* %70, !tbaa !0
  %72 = getelementptr float addrspace(2)* %21, i32 48
  %73 = load float addrspace(2)* %72, !tbaa !0
  %74 = getelementptr float addrspace(2)* %21, i32 50
  %75 = load float addrspace(2)* %74, !tbaa !0
  %76 = getelementptr float addrspace(2)* %21, i32 51
  %77 = load float addrspace(2)* %76, !tbaa !0
  %78 = getelementptr float addrspace(2)* %21, i32 108
  %79 = load float addrspace(2)* %78, !tbaa !0
  %80 = getelementptr float addrspace(2)* %21, i32 116
  %81 = load float addrspace(2)* %80, !tbaa !0
  %82 = getelementptr float addrspace(2)* %21, i32 117
  %83 = load float addrspace(2)* %82, !tbaa !0
  %84 = getelementptr float addrspace(2)* %21, i32 118
  %85 = load float addrspace(2)* %84, !tbaa !0
  %86 = getelementptr float addrspace(2)* %21, i32 119
  %87 = load float addrspace(2)* %86, !tbaa !0
  %88 = getelementptr float addrspace(2)* %21, i32 120
  %89 = load float addrspace(2)* %88, !tbaa !0
  %90 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %91 = load <32 x i8> addrspace(2)* %90, !tbaa !0
  %92 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %93 = load <16 x i8> addrspace(2)* %92, !tbaa !0
  %94 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %95 = load <32 x i8> addrspace(2)* %94, !tbaa !0
  %96 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %97 = load <16 x i8> addrspace(2)* %96, !tbaa !0
  %98 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %99 = load <32 x i8> addrspace(2)* %98, !tbaa !0
  %100 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %101 = load <16 x i8> addrspace(2)* %100, !tbaa !0
  %102 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %103 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %104 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %105 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %106 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %107 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %108 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %109 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %110 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
  %111 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
  %112 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %113 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
  %114 = bitcast float %102 to i32
  %115 = bitcast float %103 to i32
  %116 = insertelement <2 x i32> undef, i32 %114, i32 0
  %117 = insertelement <2 x i32> %116, i32 %115, i32 1
  %118 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %117, <32 x i8> %95, <16 x i8> %97, i32 2)
  %119 = extractelement <4 x float> %118, i32 0
  %120 = extractelement <4 x float> %118, i32 1
  %121 = extractelement <4 x float> %118, i32 2
  %122 = bitcast float %102 to i32
  %123 = bitcast float %103 to i32
  %124 = insertelement <2 x i32> undef, i32 %122, i32 0
  %125 = insertelement <2 x i32> %124, i32 %123, i32 1
  %126 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %125, <32 x i8> %91, <16 x i8> %93, i32 2)
  %127 = extractelement <4 x float> %126, i32 0
  %128 = extractelement <4 x float> %126, i32 1
  %129 = extractelement <4 x float> %126, i32 2
  %130 = extractelement <4 x float> %126, i32 3
  %131 = bitcast float %102 to i32
  %132 = bitcast float %103 to i32
  %133 = insertelement <2 x i32> undef, i32 %131, i32 0
  %134 = insertelement <2 x i32> %133, i32 %132, i32 1
  %135 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %134, <32 x i8> %99, <16 x i8> %101, i32 2)
  %136 = extractelement <4 x float> %135, i32 0
  %137 = extractelement <4 x float> %135, i32 1
  %138 = extractelement <4 x float> %135, i32 2
  %139 = fmul float 2.000000e+00, %119
  %140 = fadd float %139, -1.000000e+00
  %141 = fmul float 2.000000e+00, %120
  %142 = fadd float %141, -1.000000e+00
  %143 = fmul float 2.000000e+00, %121
  %144 = fadd float %143, -1.000000e+00
  %145 = fsub float -0.000000e+00, %140
  %146 = fadd float %145, 0.000000e+00
  %147 = fsub float -0.000000e+00, %142
  %148 = fadd float %147, 0.000000e+00
  %149 = fsub float -0.000000e+00, %144
  %150 = fadd float %149, 1.000000e+00
  %151 = fmul float %79, %146
  %152 = fadd float %151, %140
  %153 = fmul float %79, %148
  %154 = fadd float %153, %142
  %155 = fmul float %79, %150
  %156 = fadd float %155, %144
  %157 = fmul float %154, %107
  %158 = fmul float %154, %108
  %159 = fmul float %154, %109
  %160 = fmul float %104, %152
  %161 = fadd float %160, %157
  %162 = fmul float %105, %152
  %163 = fadd float %162, %158
  %164 = fmul float %106, %152
  %165 = fadd float %164, %159
  %166 = fmul float %110, %156
  %167 = fadd float %166, %161
  %168 = fmul float %111, %156
  %169 = fadd float %168, %163
  %170 = fmul float %112, %156
  %171 = fadd float %170, %165
  %172 = fmul float %167, %167
  %173 = fmul float %169, %169
  %174 = fadd float %173, %172
  %175 = fmul float %171, %171
  %176 = fadd float %174, %175
  %177 = call float @llvm.AMDGPU.rsq(float %176)
  %178 = fmul float %167, %177
  %179 = fmul float %169, %177
  %180 = fmul float %171, %177
  %181 = fmul float %178, %178
  %182 = fmul float %179, %179
  %183 = fmul float %180, %180
  %184 = fcmp uge float %178, 0.000000e+00
  %185 = select i1 %184, float 1.000000e+00, float 0.000000e+00
  %186 = fsub float -0.000000e+00, %185
  %187 = fptosi float %186 to i32
  %188 = bitcast i32 %187 to float
  %189 = bitcast float %188 to i32
  %190 = icmp ne i32 %189, 0
  %. = select i1 %190, float 0.000000e+00, float %181
  %191 = fcmp uge float %179, 0.000000e+00
  %192 = select i1 %191, float 1.000000e+00, float 0.000000e+00
  %193 = fsub float -0.000000e+00, %192
  %194 = fptosi float %193 to i32
  %195 = bitcast i32 %194 to float
  %196 = bitcast float %195 to i32
  %197 = icmp ne i32 %196, 0
  %temp32.0 = select i1 %197, float 0.000000e+00, float %182
  %198 = fcmp uge float %180, 0.000000e+00
  %199 = select i1 %198, float 1.000000e+00, float 0.000000e+00
  %200 = fsub float -0.000000e+00, %199
  %201 = fptosi float %200 to i32
  %202 = bitcast i32 %201 to float
  %203 = bitcast float %202 to i32
  %204 = icmp ne i32 %203, 0
  %.67 = select i1 %204, float 0.000000e+00, float %183
  %205 = fcmp uge float %178, 0.000000e+00
  %206 = select i1 %205, float 1.000000e+00, float 0.000000e+00
  %207 = fsub float -0.000000e+00, %206
  %208 = fptosi float %207 to i32
  %209 = bitcast i32 %208 to float
  %210 = bitcast float %209 to i32
  %211 = icmp ne i32 %210, 0
  %temp40.0 = select i1 %211, float %181, float 0.000000e+00
  %212 = fcmp uge float %179, 0.000000e+00
  %213 = select i1 %212, float 1.000000e+00, float 0.000000e+00
  %214 = fsub float -0.000000e+00, %213
  %215 = fptosi float %214 to i32
  %216 = bitcast i32 %215 to float
  %217 = bitcast float %216 to i32
  %218 = icmp ne i32 %217, 0
  %.68 = select i1 %218, float %182, float 0.000000e+00
  %219 = fcmp uge float %180, 0.000000e+00
  %220 = select i1 %219, float 1.000000e+00, float 0.000000e+00
  %221 = fsub float -0.000000e+00, %220
  %222 = fptosi float %221 to i32
  %223 = bitcast i32 %222 to float
  %224 = bitcast float %223 to i32
  %225 = icmp ne i32 %224, 0
  %temp20.0 = select i1 %225, float %183, float 0.000000e+00
  %226 = fmul float %., %41
  %227 = fmul float %., %43
  %228 = fmul float %., %45
  %229 = fmul float %temp40.0, %35
  %230 = fadd float %229, %226
  %231 = fmul float %temp40.0, %37
  %232 = fadd float %231, %227
  %233 = fmul float %temp40.0, %39
  %234 = fadd float %233, %228
  %235 = fmul float %.68, %47
  %236 = fadd float %235, %230
  %237 = fmul float %.68, %49
  %238 = fadd float %237, %232
  %239 = fmul float %.68, %51
  %240 = fadd float %239, %234
  %241 = fmul float %temp32.0, %53
  %242 = fadd float %241, %236
  %243 = fmul float %temp32.0, %55
  %244 = fadd float %243, %238
  %245 = fmul float %temp32.0, %57
  %246 = fadd float %245, %240
  %247 = fmul float %temp20.0, %59
  %248 = fadd float %247, %242
  %249 = fmul float %temp20.0, %61
  %250 = fadd float %249, %244
  %251 = fmul float %temp20.0, %63
  %252 = fadd float %251, %246
  %253 = fmul float %.67, %65
  %254 = fadd float %253, %248
  %255 = fmul float %.67, %67
  %256 = fadd float %255, %250
  %257 = fmul float %.67, %69
  %258 = fadd float %257, %252
  %259 = fmul float %127, %29
  %260 = fmul float %128, %31
  %261 = fmul float %129, %33
  %262 = fmul float %254, %259
  %263 = fmul float %256, %260
  %264 = fmul float %258, %261
  %265 = fsub float -0.000000e+00, %262
  %266 = fmul float %23, %259
  %267 = fadd float %266, %265
  %268 = fsub float -0.000000e+00, %263
  %269 = fmul float %25, %260
  %270 = fadd float %269, %268
  %271 = fsub float -0.000000e+00, %264
  %272 = fmul float %27, %261
  %273 = fadd float %272, %271
  %274 = fsub float -0.000000e+00, %130
  %275 = fadd float %136, %274
  %276 = fsub float -0.000000e+00, %130
  %277 = fadd float %137, %276
  %278 = fsub float -0.000000e+00, %130
  %279 = fadd float %138, %278
  %280 = fmul float %71, %275
  %281 = fadd float %280, %130
  %282 = fmul float %71, %277
  %283 = fadd float %282, %130
  %284 = fmul float %71, %279
  %285 = fadd float %284, %130
  %286 = fmul float %281, %267
  %287 = fadd float %286, %262
  %288 = fmul float %283, %270
  %289 = fadd float %288, %263
  %290 = fmul float %285, %273
  %291 = fadd float %290, %264
  %292 = fsub float -0.000000e+00, %73
  %293 = fmul float %113, %77
  %294 = fadd float %293, %292
  %295 = fcmp uge float %287, 0.000000e+00
  %296 = select i1 %295, float %287, float 0.000000e+00
  %297 = fcmp uge float %289, 0.000000e+00
  %298 = select i1 %297, float %289, float 0.000000e+00
  %299 = fcmp uge float %291, 0.000000e+00
  %300 = select i1 %299, float %291, float 0.000000e+00
  %301 = fcmp uge float %294, %75
  %302 = select i1 %301, float %75, float %294
  %303 = call float @llvm.AMDIL.clamp.(float %302, float 0.000000e+00, float 1.000000e+00)
  %304 = fsub float -0.000000e+00, %89
  %305 = fmul float %296, %304
  %306 = fadd float %305, %81
  %307 = fsub float -0.000000e+00, %89
  %308 = fmul float %298, %307
  %309 = fadd float %308, %83
  %310 = fsub float -0.000000e+00, %89
  %311 = fmul float %300, %310
  %312 = fadd float %311, %85
  %313 = fmul float %303, %303
  %314 = fmul float %306, %313
  %315 = fmul float %309, %313
  %316 = fmul float %312, %313
  %317 = fmul float %296, %89
  %318 = fadd float %317, %314
  %319 = fmul float %298, %89
  %320 = fadd float %319, %315
  %321 = fmul float %300, %89
  %322 = fadd float %321, %316
  %323 = fmul float %113, %87
  %324 = call i32 @llvm.SI.packf16(float %318, float %320)
  %325 = bitcast i32 %324 to float
  %326 = call i32 @llvm.SI.packf16(float %322, float %323)
  %327 = bitcast i32 %326 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %325, float %327, float %325, float %327)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%96](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%94](tbaa=!"const")
	S_WAITCNT 127
	%VGPR6_VGPR7_VGPR8<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_ADD_F32_e32 %VGPR6, %VGPR6, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_SUB_F32_e32 0.000000e+00, %VGPR4, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 108; mem:LD4[%78]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR7, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_F32_e32 %VGPR7, %VGPR7, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_SUB_F32_e32 0.000000e+00, %VGPR5, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %SGPR7, %VGPR9<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR5, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR10<kill>, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 %VGPR8, %VGPR8, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_SUB_F32_e32 1.000000e+00, %VGPR6, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %SGPR7<kill>, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6<kill>, %VGPR7, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR5, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR9<kill>, %VGPR4, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR9<kill>, %VGPR7, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR10, %VGPR10, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR6, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR8<kill>, %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR5<kill>, %VGPR7<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR8, %VGPR8, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_RSQ_LEGACY_F32_e32 %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR4, %VGPR4, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR4<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR4<def> = V_CVT_I32_F32_e32 %VGPR4<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_NE_I32_e64 %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR5, %SGPR8_SGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR5<kill>, 0.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%42]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%36]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR4, %SGPR7<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR6, %VGPR6, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR6<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 %VGPR6<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR6<def> = V_CVT_I32_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_NE_I32_e64 %VGPR6<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR10, %SGPR8_SGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%48]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR6, %SGPR7<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR10<kill>, 0.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%54]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR7, %SGPR7<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR9, %VGPR9, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR9<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e64 %VGPR9<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR9<def> = V_CVT_I32_F32_e32 %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_NE_I32_e64 %VGPR9<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR8, %SGPR8_SGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 33; mem:LD4[%60]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR12, %SGPR7<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, 0.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 37; mem:LD4[%66]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR13, %SGPR7<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%92](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%90](tbaa=!"const")
	S_WAITCNT 127
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%30]
	S_WAITCNT 112
	%VGPR15<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR15, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%24]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %VGPR14<kill>, %VGPR17, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 8; mem:LD16[%100](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 16; mem:LD32[%98](tbaa=!"const")
	S_WAITCNT 127
	%VGPR14_VGPR15_VGPR16<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_SUB_F32_e32 %VGPR15, %VGPR11, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 43; mem:LD4[%70]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %SGPR3, %VGPR2<kill>, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %VGPR18<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR2, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR2<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%88]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%82]
	S_WAITCNT 127
	%VGPR17<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 51; mem:LD4[%76]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%72]
	S_WAITCNT 127
	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%74]
	S_WAITCNT 127
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR0, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR3<kill>, %SGPR2, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%46]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%52]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 32; mem:LD4[%58]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR12, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 36; mem:LD4[%64]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR13, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR17<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR17, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR17<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %VGPR17<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %VGPR14, %VGPR11, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %SGPR3, %VGPR18<kill>, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR18<kill>, %VGPR17<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR3, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR3<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 116; mem:LD4[%80]
	S_WAITCNT 127
	%VGPR17<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %SGPR2, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%44]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%38]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR4<kill>, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%50]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR6<kill>, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%56]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR7<kill>, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 34; mem:LD4[%62]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR12<kill>, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 38; mem:LD4[%68]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR13<kill>, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR10, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR4, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_SUB_F32_e32 %VGPR4<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR5<def> = V_SUB_F32_e32 %VGPR16, %VGPR11, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16<imp-use,kill>
	%VGPR5<def> = V_MAD_F32 %SGPR3<kill>, %VGPR5<kill>, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%VGPR3<def> = V_MAD_F32 %VGPR5<kill>, %VGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR3, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR3<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 118; mem:LD4[%84]
	S_WAITCNT 127
	%VGPR4<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3<kill>, %SGPR2<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 119; mem:LD4[%86]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840304
c0c60508
bf8c007f
f0800700
00430602
bf8c0770
06080d06
060808f3
080a0880
c0400100
bf8c007f
c003816c
bf8c007f
d2820004
04120a07
060a0f07
060a0af3
08120a80
d2820005
04161207
c8240900
c8250901
10121305
c8280500
c8290501
d2820009
0426090a
060c1108
060c0cf3
080e0cf2
d2820007
041a0e07
c8180d00
c8190d01
d2820006
04260f06
c8200800
c8210801
10101105
c8240400
c8250401
d2820008
04220909
c8240c00
c8250c01
d282000a
04220f09
1010150a
d2820009
04220d06
c8200a00
c8210a01
100a1105
c8200600
c8210601
d2820004
04160908
c8140e00
c8150e01
d2820008
04120f05
d2820004
04261108
7e125b04
1008130a
100a0904
d00c0008
02010104
d2000004
0021e480
d2060004
22010104
7e081104
d10a0008
02010104
d2000004
00220a80
d2000005
00210105
c0038115
bf8c007f
100e0a07
c0038111
bf8c007f
d2820007
041c0f04
100c1306
10140d06
d00c0008
02010106
d2000006
0021e480
d2060006
22010106
7e0c1106
d10a0008
02010106
d2000006
00221480
c0038119
bf8c007f
d282000b
041c0f06
d2000007
0021010a
c003811d
bf8c007f
d282000a
042c0f07
10121308
10101309
d00c0008
02010109
d2000009
0021e480
d2060009
22010109
7e121109
d10a0008
02010109
d200000c
00221080
c0038121
bf8c007f
d2820009
04280f0c
d200000d
00210108
c0038125
bf8c007f
d282000e
04240f0d
c0840300
c0c60500
bf8c007f
f0800f00
00430802
c0038105
bf8c0070
101e1207
10221f0e
c0038101
bf8c007f
101c1e07
0824230e
c0840308
c0c60510
bf8c007f
f0800700
00430e02
bf8c0770
0804170f
c001812b
bf8c007f
d2820002
042e0403
d2820002
04462502
d00c0004
02010102
d2000003
00120480
c0010178
bf8c007f
10040602
c0020175
bf8c007f
08220404
c8081200
c8091201
c0020133
bf8c007f
10000404
c0020130
bf8c007f
0a000004
c0020132
bf8c007f
d00c0006
02000900
7e020204
d2000000
001a0300
d2060800
02010100
10000100
10020111
d2820001
04040503
c0020114
bf8c007f
10060a04
c0020110
bf8c007f
d2820003
040c0904
c0020118
bf8c007f
d2820003
040c0906
c002011c
bf8c007f
d2820003
040c0907
c0020120
bf8c007f
d2820003
040c090c
c0020124
bf8c007f
d2820003
040c090d
c0020104
bf8c007f
10221004
10062303
c0020100
bf8c007f
10222204
08220711
0824170e
d2820012
042e2403
d2820003
040e2312
d00c0004
02010103
d2000003
00120680
10220602
c0020174
bf8c007f
08222204
10220111
d2820003
04440503
5e020303
c0020116
bf8c007f
10060a04
c0020112
bf8c007f
d2820003
040c0904
c002011a
bf8c007f
d2820003
040c0906
c002011e
bf8c007f
d2820003
040c0907
c0020122
bf8c007f
d2820003
040c090c
c0020126
bf8c007f
d2820003
040c090d
c0020106
bf8c007f
10081404
10060903
c0020102
bf8c007f
10080804
08080704
080a1710
d2820005
042e0a03
d2820003
040e0905
d00c0004
02010103
d2000003
00120680
10080602
c0018176
bf8c007f
08080803
10000104
d2820000
04000503
c0000177
bf8c007f
10040400
5e000500
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL OUT[5], GENERIC[22]
DCL OUT[6], GENERIC[23]
DCL CONST[0..61]
DCL TEMP[0..10], LOCAL
IMM[0] FLT32 { -128.0000,     1.0000,   -64.0000,    -0.0159}
IMM[1] FLT32 {    0.0159,     0.0001,     0.0000,     0.0000}
  0: ADD TEMP[0], IN[1], IMM[0].xxxx
  1: SLT TEMP[1], TEMP[0], CONST[0].xxxx
  2: F2I TEMP[1], -TEMP[1]
  3: AND TEMP[1], TEMP[1], IMM[0].yyyy
  4: ABS TEMP[0], TEMP[0]
  5: ADD TEMP[0], TEMP[0], -TEMP[1]
  6: ADD TEMP[0], TEMP[0], IMM[0].zzzz
  7: SLT TEMP[2], TEMP[0], CONST[0].xxxx
  8: F2I TEMP[2], -TEMP[2]
  9: AND TEMP[2], TEMP[2], IMM[0].yyyy
 10: ABS TEMP[0], TEMP[0]
 11: ADD TEMP[0], TEMP[0], -TEMP[2]
 12: MAD TEMP[1].xyz, CONST[0].zzzz, -TEMP[1].xzww, CONST[0].yyyy
 13: MAD TEMP[3].xy, TEMP[0].xzzz, IMM[0].wwww, IMM[0].yyyy
 14: MAD TEMP[4].x, TEMP[0].yyyy, IMM[0].wwww, TEMP[3].xxxx
 15: MOV TEMP[3].z, TEMP[4].xxxx
 16: MUL TEMP[4], TEMP[0], IMM[1].xxxx
 17: MAD TEMP[5].x, TEMP[0].wwww, IMM[0].wwww, TEMP[3].yyyy
 18: MOV TEMP[0].z, TEMP[5].xxxx
 19: MOV TEMP[3].xy, TEMP[4].xyxx
 20: MAD TEMP[5], CONST[0].zzzz, -TEMP[2], CONST[0].yyyy
 21: DP3 TEMP[6].x, TEMP[3].xyzz, TEMP[3].xyzz
 22: RSQ TEMP[6].x, TEMP[6].xxxx
 23: MUL TEMP[6].xyz, TEMP[3].xyzz, TEMP[6].xxxx
 24: MUL TEMP[3].xy, TEMP[5].xyyy, TEMP[6].xyyy
 25: MUL TEMP[6].x, TEMP[1].xxxx, TEMP[6].zzzz
 26: MOV TEMP[3].z, TEMP[6].xxxx
 27: MAD TEMP[3].xyz, IN[4].xyzz, CONST[3].xxxx, TEMP[3].xyzz
 28: MOV TEMP[0].xy, TEMP[4].zwzz
 29: DP3 TEMP[4].x, TEMP[3].xyzz, CONST[56].xyzz
 30: MOV TEMP[2].z, TEMP[4].xxxx
 31: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz
 32: RSQ TEMP[4].x, TEMP[4].xxxx
 33: MUL TEMP[4].xyz, TEMP[0].xyzz, TEMP[4].xxxx
 34: MUL TEMP[5].xy, TEMP[5].zwww, TEMP[4].xyyy
 35: MUL TEMP[4].x, TEMP[1].yyyy, TEMP[4].zzzz
 36: MOV TEMP[5].z, TEMP[4].xxxx
 37: DP3 TEMP[2].x, TEMP[3].xyzz, CONST[54].xyzz
 38: DP3 TEMP[3].x, TEMP[3].xyzz, CONST[55].xyzz
 39: MOV TEMP[2].y, TEMP[3].xxxx
 40: MAD TEMP[0].xyz, IN[4].xyzz, CONST[3].xxxx, TEMP[5].xyzz
 41: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[2].xyzz
 42: DP3 TEMP[3].x, TEMP[0].xyzz, CONST[56].xyzz
 43: MOV TEMP[5].z, TEMP[3].xxxx
 44: RSQ TEMP[3].x, TEMP[5].xxxx
 45: DP3 TEMP[5].x, TEMP[0].xyzz, CONST[54].xyzz
 46: DP3 TEMP[4].x, TEMP[0].xyzz, CONST[55].xyzz
 47: MOV TEMP[5].y, TEMP[4].xxxx
 48: MUL TEMP[3].xyz, TEMP[2].xyzz, TEMP[3].xxxx
 49: DP3 TEMP[0].x, TEMP[5].xyzz, TEMP[5].xyzz
 50: RSQ TEMP[4].x, TEMP[0].xxxx
 51: MUL TEMP[0].xyz, TEMP[2].zxyy, TEMP[5].yzxx
 52: MUL TEMP[4].xyz, TEMP[5].xyzz, TEMP[4].xxxx
 53: MAD TEMP[5].xyz, TEMP[2].yzxx, TEMP[5].zxyy, -TEMP[0].xyzz
 54: MOV TEMP[5].w, IN[0].wwww
 55: MUL TEMP[2].xyz, TEMP[1].zzzz, TEMP[5].xyzz
 56: MAD TEMP[5].xyz, IN[3].xyzz, CONST[3].xxxx, IN[0].xyzz
 57: DP3 TEMP[0].x, TEMP[2].xyzz, TEMP[2].xyzz
 58: DP4 TEMP[1].x, TEMP[5], CONST[56]
 59: MOV TEMP[0].z, TEMP[1].xxxx
 60: RSQ TEMP[1].x, TEMP[0].xxxx
 61: DP4 TEMP[0].x, TEMP[5], CONST[54]
 62: DP4 TEMP[6].x, TEMP[5], CONST[55]
 63: MOV TEMP[0].y, TEMP[6].xxxx
 64: MUL TEMP[1].xyz, TEMP[2].xyzz, TEMP[1].xxxx
 65: UIF CONST[58].xxxx :0
 66: ENDIF
 67: UIF CONST[59].xxxx :0
 68: ENDIF
 69: UIF CONST[60].xxxx :0
 70: ENDIF
 71: UIF CONST[61].xxxx :0
 72: ELSE :0
 73: ENDIF
 74: MOV TEMP[0].w, CONST[0].yyyy
 75: DP4 TEMP[6].x, TEMP[0], CONST[13]
 76: MOV TEMP[2].z, TEMP[6].xxxx
 77: MUL TEMP[6].x, IN[3].wwww, CONST[3].yyyy
 78: MOV TEMP[2].w, TEMP[6].xxxx
 79: MOV TEMP[2].zw, TEMP[2].wwzw
 80: DP4 TEMP[5].x, TEMP[0], CONST[8]
 81: DP4 TEMP[6].x, TEMP[0], CONST[9]
 82: MOV TEMP[5].y, TEMP[6].xxxx
 83: MOV TEMP[2].xy, TEMP[5].xyxx
 84: DP4 TEMP[7].x, TEMP[0], CONST[10]
 85: MOV TEMP[5].z, TEMP[7].xxxx
 86: DP4 TEMP[0].x, TEMP[0], CONST[11]
 87: MOV TEMP[5].w, TEMP[0].xxxx
 88: MOV TEMP[8].xw, TEMP[5].xxxw
 89: DP4 TEMP[9].x, IN[2], CONST[48]
 90: DP4 TEMP[10].x, IN[2], CONST[49]
 91: MOV TEMP[9].y, TEMP[10].xxxx
 92: DP4 TEMP[10].x, IN[2], CONST[52]
 93: MOV TEMP[9].z, TEMP[10].xxxx
 94: DP4 TEMP[10].x, IN[2], CONST[53]
 95: MOV TEMP[9].w, TEMP[10].xxxx
 96: MAD TEMP[7].x, TEMP[7].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
 97: MOV TEMP[8].z, TEMP[7].xxxx
 98: MOV TEMP[8].y, -TEMP[6].xxxx
 99: MAD TEMP[8].xy, CONST[57].xyyy, TEMP[0].xxxx, TEMP[8].xyyy
100: MOV OUT[2], TEMP[9]
101: MOV OUT[3], TEMP[4]
102: MOV OUT[0], TEMP[8]
103: MOV OUT[4], TEMP[1]
104: MOV OUT[1], TEMP[5]
105: MOV OUT[5], TEMP[3]
106: MOV OUT[6], TEMP[2]
107: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 12
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 13
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 32
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 33
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 34
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 35
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 36
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 37
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 38
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 39
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 40
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 41
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 42
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 43
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 44
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 45
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 46
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 47
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 52
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 53
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 54
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 55
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 192
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 193
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 194
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 195
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 196
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 197
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 198
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 199
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 208
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 209
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 210
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 211
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 212
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr float addrspace(2)* %10, i32 213
  %88 = load float addrspace(2)* %87, !tbaa !0
  %89 = getelementptr float addrspace(2)* %10, i32 214
  %90 = load float addrspace(2)* %89, !tbaa !0
  %91 = getelementptr float addrspace(2)* %10, i32 215
  %92 = load float addrspace(2)* %91, !tbaa !0
  %93 = getelementptr float addrspace(2)* %10, i32 216
  %94 = load float addrspace(2)* %93, !tbaa !0
  %95 = getelementptr float addrspace(2)* %10, i32 217
  %96 = load float addrspace(2)* %95, !tbaa !0
  %97 = getelementptr float addrspace(2)* %10, i32 218
  %98 = load float addrspace(2)* %97, !tbaa !0
  %99 = getelementptr float addrspace(2)* %10, i32 219
  %100 = load float addrspace(2)* %99, !tbaa !0
  %101 = getelementptr float addrspace(2)* %10, i32 220
  %102 = load float addrspace(2)* %101, !tbaa !0
  %103 = getelementptr float addrspace(2)* %10, i32 221
  %104 = load float addrspace(2)* %103, !tbaa !0
  %105 = getelementptr float addrspace(2)* %10, i32 222
  %106 = load float addrspace(2)* %105, !tbaa !0
  %107 = getelementptr float addrspace(2)* %10, i32 223
  %108 = load float addrspace(2)* %107, !tbaa !0
  %109 = getelementptr float addrspace(2)* %10, i32 224
  %110 = load float addrspace(2)* %109, !tbaa !0
  %111 = getelementptr float addrspace(2)* %10, i32 225
  %112 = load float addrspace(2)* %111, !tbaa !0
  %113 = getelementptr float addrspace(2)* %10, i32 226
  %114 = load float addrspace(2)* %113, !tbaa !0
  %115 = getelementptr float addrspace(2)* %10, i32 227
  %116 = load float addrspace(2)* %115, !tbaa !0
  %117 = getelementptr float addrspace(2)* %10, i32 228
  %118 = load float addrspace(2)* %117, !tbaa !0
  %119 = getelementptr float addrspace(2)* %10, i32 229
  %120 = load float addrspace(2)* %119, !tbaa !0
  %121 = getelementptr float addrspace(2)* %10, i32 236
  %122 = load float addrspace(2)* %121, !tbaa !0
  %123 = getelementptr float addrspace(2)* %10, i32 240
  %124 = load float addrspace(2)* %123, !tbaa !0
  %125 = getelementptr float addrspace(2)* %10, i32 244
  %126 = load float addrspace(2)* %125, !tbaa !0
  %127 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %128 = load <16 x i8> addrspace(2)* %127, !tbaa !0
  %129 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %128, i32 0, i32 %5)
  %130 = extractelement <4 x float> %129, i32 0
  %131 = extractelement <4 x float> %129, i32 1
  %132 = extractelement <4 x float> %129, i32 2
  %133 = extractelement <4 x float> %129, i32 3
  %134 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %135 = load <16 x i8> addrspace(2)* %134, !tbaa !0
  %136 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %135, i32 0, i32 %5)
  %137 = extractelement <4 x float> %136, i32 0
  %138 = extractelement <4 x float> %136, i32 1
  %139 = extractelement <4 x float> %136, i32 2
  %140 = extractelement <4 x float> %136, i32 3
  %141 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %142 = load <16 x i8> addrspace(2)* %141, !tbaa !0
  %143 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %142, i32 0, i32 %5)
  %144 = extractelement <4 x float> %143, i32 0
  %145 = extractelement <4 x float> %143, i32 1
  %146 = extractelement <4 x float> %143, i32 2
  %147 = extractelement <4 x float> %143, i32 3
  %148 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %149 = load <16 x i8> addrspace(2)* %148, !tbaa !0
  %150 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %149, i32 0, i32 %5)
  %151 = extractelement <4 x float> %150, i32 0
  %152 = extractelement <4 x float> %150, i32 1
  %153 = extractelement <4 x float> %150, i32 2
  %154 = extractelement <4 x float> %150, i32 3
  %155 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %156 = load <16 x i8> addrspace(2)* %155, !tbaa !0
  %157 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %156, i32 0, i32 %5)
  %158 = extractelement <4 x float> %157, i32 0
  %159 = extractelement <4 x float> %157, i32 1
  %160 = extractelement <4 x float> %157, i32 2
  %161 = fadd float %137, -1.280000e+02
  %162 = fadd float %138, -1.280000e+02
  %163 = fadd float %139, -1.280000e+02
  %164 = fadd float %140, -1.280000e+02
  %165 = fcmp ult float %161, %12
  %166 = select i1 %165, float 1.000000e+00, float 0.000000e+00
  %167 = fcmp ult float %162, %12
  %168 = select i1 %167, float 1.000000e+00, float 0.000000e+00
  %169 = fcmp ult float %163, %12
  %170 = select i1 %169, float 1.000000e+00, float 0.000000e+00
  %171 = fcmp ult float %164, %12
  %172 = select i1 %171, float 1.000000e+00, float 0.000000e+00
  %173 = fsub float -0.000000e+00, %166
  %174 = fptosi float %173 to i32
  %175 = fsub float -0.000000e+00, %168
  %176 = fptosi float %175 to i32
  %177 = fsub float -0.000000e+00, %170
  %178 = fptosi float %177 to i32
  %179 = fsub float -0.000000e+00, %172
  %180 = fptosi float %179 to i32
  %181 = bitcast i32 %174 to float
  %182 = bitcast i32 %176 to float
  %183 = bitcast i32 %178 to float
  %184 = bitcast i32 %180 to float
  %185 = bitcast float %181 to i32
  %186 = and i32 %185, 1065353216
  %187 = bitcast float %182 to i32
  %188 = and i32 %187, 1065353216
  %189 = bitcast float %183 to i32
  %190 = and i32 %189, 1065353216
  %191 = bitcast float %184 to i32
  %192 = and i32 %191, 1065353216
  %193 = bitcast i32 %186 to float
  %194 = bitcast i32 %188 to float
  %195 = bitcast i32 %190 to float
  %196 = bitcast i32 %192 to float
  %197 = call float @fabs(float %161)
  %198 = call float @fabs(float %162)
  %199 = call float @fabs(float %163)
  %200 = call float @fabs(float %164)
  %201 = fsub float -0.000000e+00, %193
  %202 = fadd float %197, %201
  %203 = fsub float -0.000000e+00, %194
  %204 = fadd float %198, %203
  %205 = fsub float -0.000000e+00, %195
  %206 = fadd float %199, %205
  %207 = fsub float -0.000000e+00, %196
  %208 = fadd float %200, %207
  %209 = fadd float %202, -6.400000e+01
  %210 = fadd float %204, -6.400000e+01
  %211 = fadd float %206, -6.400000e+01
  %212 = fadd float %208, -6.400000e+01
  %213 = fcmp ult float %209, %12
  %214 = select i1 %213, float 1.000000e+00, float 0.000000e+00
  %215 = fcmp ult float %210, %12
  %216 = select i1 %215, float 1.000000e+00, float 0.000000e+00
  %217 = fcmp ult float %211, %12
  %218 = select i1 %217, float 1.000000e+00, float 0.000000e+00
  %219 = fcmp ult float %212, %12
  %220 = select i1 %219, float 1.000000e+00, float 0.000000e+00
  %221 = fsub float -0.000000e+00, %214
  %222 = fptosi float %221 to i32
  %223 = fsub float -0.000000e+00, %216
  %224 = fptosi float %223 to i32
  %225 = fsub float -0.000000e+00, %218
  %226 = fptosi float %225 to i32
  %227 = fsub float -0.000000e+00, %220
  %228 = fptosi float %227 to i32
  %229 = bitcast i32 %222 to float
  %230 = bitcast i32 %224 to float
  %231 = bitcast i32 %226 to float
  %232 = bitcast i32 %228 to float
  %233 = bitcast float %229 to i32
  %234 = and i32 %233, 1065353216
  %235 = bitcast float %230 to i32
  %236 = and i32 %235, 1065353216
  %237 = bitcast float %231 to i32
  %238 = and i32 %237, 1065353216
  %239 = bitcast float %232 to i32
  %240 = and i32 %239, 1065353216
  %241 = bitcast i32 %234 to float
  %242 = bitcast i32 %236 to float
  %243 = bitcast i32 %238 to float
  %244 = bitcast i32 %240 to float
  %245 = call float @fabs(float %209)
  %246 = call float @fabs(float %210)
  %247 = call float @fabs(float %211)
  %248 = call float @fabs(float %212)
  %249 = fsub float -0.000000e+00, %241
  %250 = fadd float %245, %249
  %251 = fsub float -0.000000e+00, %242
  %252 = fadd float %246, %251
  %253 = fsub float -0.000000e+00, %243
  %254 = fadd float %247, %253
  %255 = fsub float -0.000000e+00, %244
  %256 = fadd float %248, %255
  %257 = fsub float -0.000000e+00, %193
  %258 = fmul float %16, %257
  %259 = fadd float %258, %14
  %260 = fsub float -0.000000e+00, %195
  %261 = fmul float %16, %260
  %262 = fadd float %261, %14
  %263 = fsub float -0.000000e+00, %196
  %264 = fmul float %16, %263
  %265 = fadd float %264, %14
  %266 = fmul float %250, 0xBF90410420000000
  %267 = fadd float %266, 1.000000e+00
  %268 = fmul float %254, 0xBF90410420000000
  %269 = fadd float %268, 1.000000e+00
  %270 = fmul float %252, 0xBF90410420000000
  %271 = fadd float %270, %267
  %272 = fmul float %250, 0x3F90410420000000
  %273 = fmul float %252, 0x3F90410420000000
  %274 = fmul float %254, 0x3F90410420000000
  %275 = fmul float %256, 0x3F90410420000000
  %276 = fmul float %256, 0xBF90410420000000
  %277 = fadd float %276, %269
  %278 = fsub float -0.000000e+00, %241
  %279 = fmul float %16, %278
  %280 = fadd float %279, %14
  %281 = fsub float -0.000000e+00, %242
  %282 = fmul float %16, %281
  %283 = fadd float %282, %14
  %284 = fsub float -0.000000e+00, %243
  %285 = fmul float %16, %284
  %286 = fadd float %285, %14
  %287 = fsub float -0.000000e+00, %244
  %288 = fmul float %16, %287
  %289 = fadd float %288, %14
  %290 = fmul float %272, %272
  %291 = fmul float %273, %273
  %292 = fadd float %291, %290
  %293 = fmul float %271, %271
  %294 = fadd float %292, %293
  %295 = call float @llvm.AMDGPU.rsq(float %294)
  %296 = fmul float %272, %295
  %297 = fmul float %273, %295
  %298 = fmul float %271, %295
  %299 = fmul float %280, %296
  %300 = fmul float %283, %297
  %301 = fmul float %259, %298
  %302 = fmul float %158, %18
  %303 = fadd float %302, %299
  %304 = fmul float %159, %18
  %305 = fadd float %304, %300
  %306 = fmul float %160, %18
  %307 = fadd float %306, %301
  %308 = fmul float %303, %110
  %309 = fmul float %305, %112
  %310 = fadd float %309, %308
  %311 = fmul float %307, %114
  %312 = fadd float %310, %311
  %313 = fmul float %274, %274
  %314 = fmul float %275, %275
  %315 = fadd float %314, %313
  %316 = fmul float %277, %277
  %317 = fadd float %315, %316
  %318 = call float @llvm.AMDGPU.rsq(float %317)
  %319 = fmul float %274, %318
  %320 = fmul float %275, %318
  %321 = fmul float %277, %318
  %322 = fmul float %286, %319
  %323 = fmul float %289, %320
  %324 = fmul float %262, %321
  %325 = fmul float %303, %94
  %326 = fmul float %305, %96
  %327 = fadd float %326, %325
  %328 = fmul float %307, %98
  %329 = fadd float %327, %328
  %330 = fmul float %303, %102
  %331 = fmul float %305, %104
  %332 = fadd float %331, %330
  %333 = fmul float %307, %106
  %334 = fadd float %332, %333
  %335 = fmul float %158, %18
  %336 = fadd float %335, %322
  %337 = fmul float %159, %18
  %338 = fadd float %337, %323
  %339 = fmul float %160, %18
  %340 = fadd float %339, %324
  %341 = fmul float %329, %329
  %342 = fmul float %334, %334
  %343 = fadd float %342, %341
  %344 = fmul float %312, %312
  %345 = fadd float %343, %344
  %346 = fmul float %336, %110
  %347 = fmul float %338, %112
  %348 = fadd float %347, %346
  %349 = fmul float %340, %114
  %350 = fadd float %348, %349
  %351 = call float @llvm.AMDGPU.rsq(float %345)
  %352 = fmul float %336, %94
  %353 = fmul float %338, %96
  %354 = fadd float %353, %352
  %355 = fmul float %340, %98
  %356 = fadd float %354, %355
  %357 = fmul float %336, %102
  %358 = fmul float %338, %104
  %359 = fadd float %358, %357
  %360 = fmul float %340, %106
  %361 = fadd float %359, %360
  %362 = fmul float %329, %351
  %363 = fmul float %334, %351
  %364 = fmul float %312, %351
  %365 = fmul float %356, %356
  %366 = fmul float %361, %361
  %367 = fadd float %366, %365
  %368 = fmul float %350, %350
  %369 = fadd float %367, %368
  %370 = call float @llvm.AMDGPU.rsq(float %369)
  %371 = fmul float %312, %361
  %372 = fmul float %329, %350
  %373 = fmul float %334, %356
  %374 = fmul float %356, %370
  %375 = fmul float %361, %370
  %376 = fmul float %350, %370
  %377 = fsub float -0.000000e+00, %371
  %378 = fmul float %334, %350
  %379 = fadd float %378, %377
  %380 = fsub float -0.000000e+00, %372
  %381 = fmul float %312, %356
  %382 = fadd float %381, %380
  %383 = fsub float -0.000000e+00, %373
  %384 = fmul float %329, %361
  %385 = fadd float %384, %383
  %386 = fmul float %265, %379
  %387 = fmul float %265, %382
  %388 = fmul float %265, %385
  %389 = fmul float %151, %18
  %390 = fadd float %389, %130
  %391 = fmul float %152, %18
  %392 = fadd float %391, %131
  %393 = fmul float %153, %18
  %394 = fadd float %393, %132
  %395 = fmul float %386, %386
  %396 = fmul float %387, %387
  %397 = fadd float %396, %395
  %398 = fmul float %388, %388
  %399 = fadd float %397, %398
  %400 = fmul float %390, %110
  %401 = fmul float %392, %112
  %402 = fadd float %400, %401
  %403 = fmul float %394, %114
  %404 = fadd float %402, %403
  %405 = fmul float %133, %116
  %406 = fadd float %404, %405
  %407 = call float @llvm.AMDGPU.rsq(float %399)
  %408 = fmul float %390, %94
  %409 = fmul float %392, %96
  %410 = fadd float %408, %409
  %411 = fmul float %394, %98
  %412 = fadd float %410, %411
  %413 = fmul float %133, %100
  %414 = fadd float %412, %413
  %415 = fmul float %390, %102
  %416 = fmul float %392, %104
  %417 = fadd float %415, %416
  %418 = fmul float %394, %106
  %419 = fadd float %417, %418
  %420 = fmul float %133, %108
  %421 = fadd float %419, %420
  %422 = fmul float %386, %407
  %423 = fmul float %387, %407
  %424 = fmul float %388, %407
  %425 = bitcast float %122 to i32
  %426 = icmp ne i32 %425, 0
  %427 = bitcast float %124 to i32
  %428 = icmp ne i32 %427, 0
  %429 = bitcast float %126 to i32
  %430 = icmp ne i32 %429, 0
  %431 = fmul float %414, %54
  %432 = fmul float %421, %56
  %433 = fadd float %431, %432
  %434 = fmul float %406, %58
  %435 = fadd float %433, %434
  %436 = fmul float %14, %60
  %437 = fadd float %435, %436
  %438 = fmul float %154, %20
  %439 = fmul float %414, %22
  %440 = fmul float %421, %24
  %441 = fadd float %439, %440
  %442 = fmul float %406, %26
  %443 = fadd float %441, %442
  %444 = fmul float %14, %28
  %445 = fadd float %443, %444
  %446 = fmul float %414, %30
  %447 = fmul float %421, %32
  %448 = fadd float %446, %447
  %449 = fmul float %406, %34
  %450 = fadd float %448, %449
  %451 = fmul float %14, %36
  %452 = fadd float %450, %451
  %453 = fmul float %414, %38
  %454 = fmul float %421, %40
  %455 = fadd float %453, %454
  %456 = fmul float %406, %42
  %457 = fadd float %455, %456
  %458 = fmul float %14, %44
  %459 = fadd float %457, %458
  %460 = fmul float %414, %46
  %461 = fmul float %421, %48
  %462 = fadd float %460, %461
  %463 = fmul float %406, %50
  %464 = fadd float %462, %463
  %465 = fmul float %14, %52
  %466 = fadd float %464, %465
  %467 = fmul float %144, %62
  %468 = fmul float %145, %64
  %469 = fadd float %467, %468
  %470 = fmul float %146, %66
  %471 = fadd float %469, %470
  %472 = fmul float %147, %68
  %473 = fadd float %471, %472
  %474 = fmul float %144, %70
  %475 = fmul float %145, %72
  %476 = fadd float %474, %475
  %477 = fmul float %146, %74
  %478 = fadd float %476, %477
  %479 = fmul float %147, %76
  %480 = fadd float %478, %479
  %481 = fmul float %144, %78
  %482 = fmul float %145, %80
  %483 = fadd float %481, %482
  %484 = fmul float %146, %82
  %485 = fadd float %483, %484
  %486 = fmul float %147, %84
  %487 = fadd float %485, %486
  %488 = fmul float %144, %86
  %489 = fmul float %145, %88
  %490 = fadd float %488, %489
  %491 = fmul float %146, %90
  %492 = fadd float %490, %491
  %493 = fmul float %147, %92
  %494 = fadd float %492, %493
  %495 = fsub float -0.000000e+00, %466
  %496 = fmul float %459, %16
  %497 = fadd float %496, %495
  %498 = fsub float -0.000000e+00, %452
  %499 = fmul float %118, %466
  %500 = fadd float %499, %445
  %501 = fmul float %120, %466
  %502 = fadd float %501, %498
  %503 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %504 = load float addrspace(2)* addrspace(2)* %503, !tbaa !0
  %505 = getelementptr float addrspace(2)* %504, i32 0
  %506 = load float addrspace(2)* %505, !tbaa !0
  %507 = fmul float %506, %445
  %508 = getelementptr float addrspace(2)* %504, i32 1
  %509 = load float addrspace(2)* %508, !tbaa !0
  %510 = fmul float %509, %452
  %511 = fadd float %507, %510
  %512 = getelementptr float addrspace(2)* %504, i32 2
  %513 = load float addrspace(2)* %512, !tbaa !0
  %514 = fmul float %513, %459
  %515 = fadd float %511, %514
  %516 = getelementptr float addrspace(2)* %504, i32 3
  %517 = load float addrspace(2)* %516, !tbaa !0
  %518 = fmul float %517, %466
  %519 = fadd float %515, %518
  %520 = getelementptr float addrspace(2)* %504, i32 4
  %521 = load float addrspace(2)* %520, !tbaa !0
  %522 = fmul float %521, %445
  %523 = getelementptr float addrspace(2)* %504, i32 5
  %524 = load float addrspace(2)* %523, !tbaa !0
  %525 = fmul float %524, %452
  %526 = fadd float %522, %525
  %527 = getelementptr float addrspace(2)* %504, i32 6
  %528 = load float addrspace(2)* %527, !tbaa !0
  %529 = fmul float %528, %459
  %530 = fadd float %526, %529
  %531 = getelementptr float addrspace(2)* %504, i32 7
  %532 = load float addrspace(2)* %531, !tbaa !0
  %533 = fmul float %532, %466
  %534 = fadd float %530, %533
  %535 = getelementptr float addrspace(2)* %504, i32 8
  %536 = load float addrspace(2)* %535, !tbaa !0
  %537 = fmul float %536, %445
  %538 = getelementptr float addrspace(2)* %504, i32 9
  %539 = load float addrspace(2)* %538, !tbaa !0
  %540 = fmul float %539, %452
  %541 = fadd float %537, %540
  %542 = getelementptr float addrspace(2)* %504, i32 10
  %543 = load float addrspace(2)* %542, !tbaa !0
  %544 = fmul float %543, %459
  %545 = fadd float %541, %544
  %546 = getelementptr float addrspace(2)* %504, i32 11
  %547 = load float addrspace(2)* %546, !tbaa !0
  %548 = fmul float %547, %466
  %549 = fadd float %545, %548
  %550 = getelementptr float addrspace(2)* %504, i32 12
  %551 = load float addrspace(2)* %550, !tbaa !0
  %552 = fmul float %551, %445
  %553 = getelementptr float addrspace(2)* %504, i32 13
  %554 = load float addrspace(2)* %553, !tbaa !0
  %555 = fmul float %554, %452
  %556 = fadd float %552, %555
  %557 = getelementptr float addrspace(2)* %504, i32 14
  %558 = load float addrspace(2)* %557, !tbaa !0
  %559 = fmul float %558, %459
  %560 = fadd float %556, %559
  %561 = getelementptr float addrspace(2)* %504, i32 15
  %562 = load float addrspace(2)* %561, !tbaa !0
  %563 = fmul float %562, %466
  %564 = fadd float %560, %563
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %519, float %534, float %549, float %564)
  %565 = getelementptr float addrspace(2)* %504, i32 16
  %566 = load float addrspace(2)* %565, !tbaa !0
  %567 = fmul float %566, %445
  %568 = getelementptr float addrspace(2)* %504, i32 17
  %569 = load float addrspace(2)* %568, !tbaa !0
  %570 = fmul float %569, %452
  %571 = fadd float %567, %570
  %572 = getelementptr float addrspace(2)* %504, i32 18
  %573 = load float addrspace(2)* %572, !tbaa !0
  %574 = fmul float %573, %459
  %575 = fadd float %571, %574
  %576 = getelementptr float addrspace(2)* %504, i32 19
  %577 = load float addrspace(2)* %576, !tbaa !0
  %578 = fmul float %577, %466
  %579 = fadd float %575, %578
  %580 = getelementptr float addrspace(2)* %504, i32 20
  %581 = load float addrspace(2)* %580, !tbaa !0
  %582 = fmul float %581, %445
  %583 = getelementptr float addrspace(2)* %504, i32 21
  %584 = load float addrspace(2)* %583, !tbaa !0
  %585 = fmul float %584, %452
  %586 = fadd float %582, %585
  %587 = getelementptr float addrspace(2)* %504, i32 22
  %588 = load float addrspace(2)* %587, !tbaa !0
  %589 = fmul float %588, %459
  %590 = fadd float %586, %589
  %591 = getelementptr float addrspace(2)* %504, i32 23
  %592 = load float addrspace(2)* %591, !tbaa !0
  %593 = fmul float %592, %466
  %594 = fadd float %590, %593
  %595 = getelementptr float addrspace(2)* %504, i32 24
  %596 = load float addrspace(2)* %595, !tbaa !0
  %597 = fmul float %596, %445
  %598 = getelementptr float addrspace(2)* %504, i32 25
  %599 = load float addrspace(2)* %598, !tbaa !0
  %600 = fmul float %599, %452
  %601 = fadd float %597, %600
  %602 = getelementptr float addrspace(2)* %504, i32 26
  %603 = load float addrspace(2)* %602, !tbaa !0
  %604 = fmul float %603, %459
  %605 = fadd float %601, %604
  %606 = getelementptr float addrspace(2)* %504, i32 27
  %607 = load float addrspace(2)* %606, !tbaa !0
  %608 = fmul float %607, %466
  %609 = fadd float %605, %608
  %610 = getelementptr float addrspace(2)* %504, i32 28
  %611 = load float addrspace(2)* %610, !tbaa !0
  %612 = fmul float %611, %445
  %613 = getelementptr float addrspace(2)* %504, i32 29
  %614 = load float addrspace(2)* %613, !tbaa !0
  %615 = fmul float %614, %452
  %616 = fadd float %612, %615
  %617 = getelementptr float addrspace(2)* %504, i32 30
  %618 = load float addrspace(2)* %617, !tbaa !0
  %619 = fmul float %618, %459
  %620 = fadd float %616, %619
  %621 = getelementptr float addrspace(2)* %504, i32 31
  %622 = load float addrspace(2)* %621, !tbaa !0
  %623 = fmul float %622, %466
  %624 = fadd float %620, %623
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %579, float %594, float %609, float %624)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %473, float %480, float %487, float %494)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %374, float %375, float %376, float %275)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %422, float %423, float %424, float %196)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %362, float %363, float %364, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %445, float %452, float %437, float %438)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %500, float %502, float %497, float %466)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #3

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%127](tbaa=!"const")
	S_WAITCNT 127
	%VGPR7_VGPR8_VGPR9_VGPR10<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%148](tbaa=!"const")
	S_WAITCNT 112
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 0; mem:LD8[%9](tbaa=!"const")
	S_WAITCNT 112
	%SGPR5<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 12; mem:LD4[%17]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR1, %SGPR5, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR2, %SGPR5, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR11<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 217; mem:LD4[%95]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR11, %VGPR12, %EXEC<imp-use>
	%SGPR13<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 216; mem:LD4[%93]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR11, %SGPR13, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR3, %SGPR5, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 218; mem:LD4[%97]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR13, %SGPR12, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 219; mem:LD4[%99]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %VGPR10, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 221; mem:LD4[%103]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR8, %VGPR12, %EXEC<imp-use>
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 220; mem:LD4[%101]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR11, %SGPR9, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 222; mem:LD4[%105]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR13, %SGPR10, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 223; mem:LD4[%107]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR10, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 33; mem:LD4[%23]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 32; mem:LD4[%21]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR5, %SGPR4<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR14<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 225; mem:LD4[%111]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR14, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR15<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 224; mem:LD4[%109]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %SGPR15, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 226; mem:LD4[%113]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR13<kill>, %SGPR16, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 227; mem:LD4[%115]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %VGPR10, %SGPR4<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8_VGPR9_VGPR10<imp-use,kill>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 34; mem:LD4[%25]
	S_WAITCNT 127
	%VGPR7<def> = V_MAD_F32 %VGPR8, %SGPR4<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 1; mem:LD4[%13]
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 35; mem:LD4[%27]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %SGPR4, %VGPR9<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 37; mem:LD4[%31]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR17<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 36; mem:LD4[%29]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR5, %SGPR17<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 38; mem:LD4[%33]
	S_WAITCNT 127
	%VGPR9<def> = V_MAD_F32 %VGPR8, %SGPR17<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 39; mem:LD4[%35]
	S_WAITCNT 127
	%VGPR10<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %SGPR4, %VGPR10<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 2; mem:LD8[%500](tbaa=!"const")
	S_WAITCNT 127
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 13; mem:LD4[%550]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR17<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 12; mem:LD4[%547]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR17<kill>, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 41; mem:LD4[%39]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR17<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 40; mem:LD4[%37]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR5, %SGPR17<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 42; mem:LD4[%41]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR8, %SGPR17<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 43; mem:LD4[%43]
	S_WAITCNT 127
	%VGPR12<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %SGPR4, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 14; mem:LD4[%554]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR17<kill>, %VGPR10, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 45; mem:LD4[%47]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR17<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 44; mem:LD4[%45]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR5, %SGPR17<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 46; mem:LD4[%49]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR8, %SGPR17<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 47; mem:LD4[%51]
	S_WAITCNT 127
	%VGPR13<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %SGPR4, %VGPR13<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[%558]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR17<kill>, %VGPR11, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 9; mem:LD4[%535]
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR17<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 8; mem:LD4[%532]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %SGPR17<kill>, %VGPR7, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 10; mem:LD4[%539]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %SGPR17<kill>, %VGPR10, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[%543]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %SGPR17<kill>, %VGPR11, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%520]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR17<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%517]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %SGPR17<kill>, %VGPR7, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%524]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %SGPR17<kill>, %VGPR10, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[%528]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %SGPR17<kill>, %VGPR11, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%505]
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR17<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%502]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %SGPR17<kill>, %VGPR7, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%509]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %SGPR17<kill>, %VGPR10, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 3; mem:LD4[%513]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %SGPR17<kill>, %VGPR11, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 14, 0, 0, 0, %VGPR15<kill>, %VGPR14<kill>, %VGPR13<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%610]
	S_WAITCNT 15
	%VGPR12<def> = V_MUL_F32_e32 %SGPR17<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%607]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR17<kill>, %VGPR7, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%614]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR17<kill>, %VGPR10, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 31; mem:LD4[%618]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %SGPR17<kill>, %VGPR11, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%595]
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR17<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%592]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %SGPR17<kill>, %VGPR7, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%599]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %SGPR17<kill>, %VGPR10, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 27; mem:LD4[%603]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %SGPR17<kill>, %VGPR11, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%580]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR17<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%577]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %SGPR17<kill>, %VGPR7, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%584]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %SGPR17<kill>, %VGPR10, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[%588]
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %SGPR17<kill>, %VGPR11, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%565]
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR17<kill>, %VGPR9, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%562]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %SGPR17<kill>, %VGPR7, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR17<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%569]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %SGPR17<kill>, %VGPR10, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 19; mem:LD4[%573]
	S_WAITCNT 127
	%VGPR15<def> = V_MAD_F32 %SGPR0<kill>, %VGPR11, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 15, 0, 0, 0, %VGPR15<kill>, %VGPR14<kill>, %VGPR13<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%141](tbaa=!"const")
	S_WAITCNT 15
	%VGPR12_VGPR13_VGPR14_VGPR15<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR20_SGPR21_SGPR22_SGPR23<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 213; mem:LD4[%87]
	S_WAITCNT 112
	%VGPR16<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 212; mem:LD4[%85]
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR12, %SGPR0<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 214; mem:LD4[%89]
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR14, %SGPR0<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 215; mem:LD4[%91]
	S_WAITCNT 127
	%VGPR16<def> = V_MAD_F32 %VGPR15, %SGPR0<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 209; mem:LD4[%79]
	S_WAITCNT 127
	%VGPR17<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 208; mem:LD4[%77]
	S_WAITCNT 127
	%VGPR17<def> = V_MAD_F32 %VGPR12, %SGPR0<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 210; mem:LD4[%81]
	S_WAITCNT 127
	%VGPR17<def> = V_MAD_F32 %VGPR14, %SGPR0<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 211; mem:LD4[%83]
	S_WAITCNT 127
	%VGPR17<def> = V_MAD_F32 %VGPR15, %SGPR0<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 197; mem:LD4[%71]
	S_WAITCNT 127
	%VGPR18<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 196; mem:LD4[%69]
	S_WAITCNT 127
	%VGPR18<def> = V_MAD_F32 %VGPR12, %SGPR0<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 198; mem:LD4[%73]
	S_WAITCNT 127
	%VGPR18<def> = V_MAD_F32 %VGPR14, %SGPR0<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 199; mem:LD4[%75]
	S_WAITCNT 127
	%VGPR18<def> = V_MAD_F32 %VGPR15, %SGPR0<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 193; mem:LD4[%63]
	S_WAITCNT 127
	%VGPR19<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR13, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 192; mem:LD4[%61]
	S_WAITCNT 127
	%VGPR19<def> = V_MAD_F32 %VGPR12, %SGPR0<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 194; mem:LD4[%65]
	S_WAITCNT 127
	%VGPR19<def> = V_MAD_F32 %VGPR14, %SGPR0<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 195; mem:LD4[%67]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR15, %SGPR0<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR12<kill>, %VGPR18<kill>, %VGPR17<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%134](tbaa=!"const")
	S_WAITCNT 15
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR20_SGPR21_SGPR22_SGPR23<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR12<def> = V_ADD_F32_e32 -1.280000e+02, %VGPR16, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e64 %VGPR12, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 0; mem:LD4[%11]
	S_WAITCNT 127
	%SGPR18_SGPR19<def> = V_CMP_LT_F32_e64 %VGPR12<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR18_SGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_F32_e64 %VGPR12<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR12<def> = V_CVT_I32_F32_e32 %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %VGPR17<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e32 -6.400000e+01, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e64 %VGPR17, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = V_CMP_LT_F32_e64 %VGPR17<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR18_SGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e64 %VGPR17<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR17<def> = V_CVT_I32_F32_e32 %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_AND_B32_e32 1065353216, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %VGPR18<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e32 -1.280000e+02, %VGPR15, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e64 %VGPR20, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = V_CMP_LT_F32_e64 %VGPR20<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR18_SGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e64 %VGPR20<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR20<def> = V_CVT_I32_F32_e32 %VGPR20<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_AND_B32_e32 1065353216, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 %VGPR19<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e32 -6.400000e+01, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e64 %VGPR20, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = V_CMP_LT_F32_e64 %VGPR20<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR18_SGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e64 %VGPR20<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR20<def> = V_CVT_I32_F32_e32 %VGPR20<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_AND_B32_e32 1065353216, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 %VGPR19<kill>, %VGPR26, %EXEC<imp-use>
	%VGPR22<def> = V_MOV_B32_e32 -1.587302e-02, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR19, %VGPR22, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR18, %VGPR22, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 1.587302e-02, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 1.587302e-02, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR28, %VGPR28, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR24, %VGPR24, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR23, %VGPR23, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_RSQ_LEGACY_F32_e32 %VGPR18<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR24, %VGPR27, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 2; mem:LD4[%15]
	S_WAITCNT 127
	%VGPR17<def> = V_MUL_F32_e32 %SGPR0, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %SGPR4, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR18<kill>, %EXEC<imp-use>
	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 16; mem:LD16[%155](tbaa=!"const")
	S_WAITCNT 127
	%VGPR17_VGPR18_VGPR19_VGPR20<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR20_SGPR21_SGPR22_SGPR23<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR25<def> = V_MAD_F32 %VGPR18, %SGPR5, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR27, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %SGPR0, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_SUB_F32_e32 %SGPR4, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR17, %SGPR5, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %SGPR9, %VGPR26, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR25, %SGPR8, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR23<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %SGPR0, %VGPR21<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_SUB_F32_e32 %SGPR4, %VGPR21<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR21<kill>, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR19, %SGPR5, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR23, %SGPR10, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %SGPR13, %VGPR26, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR25, %SGPR11, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR23, %SGPR12, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR21, %VGPR21, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR0, %VGPR0, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %SGPR15, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR25<kill>, %SGPR14, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR23<kill>, %SGPR16, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR23, %VGPR23, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_RSQ_LEGACY_F32_e32 %VGPR25<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR23, %VGPR25, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR0, %VGPR25, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR21, %VGPR25<kill>, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR25<kill>, %VGPR27<kill>, %VGPR26<kill>, %VGPR24<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR25<def> = V_ADD_F32_e32 -1.280000e+02, %VGPR14, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 %VGPR25, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_F32_e64 %VGPR25<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR25<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR25<def> = V_CVT_I32_F32_e32 %VGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_AND_B32_e32 1065353216, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_SUB_F32_e32 %VGPR24<kill>, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e32 -6.400000e+01, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR24, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_F32_e64 %VGPR24<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 %VGPR24<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR24<def> = V_CVT_I32_F32_e32 %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_AND_B32_e32 1065353216, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_SUB_F32_e32 %VGPR25<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e32 -1.280000e+02, %VGPR13, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%VGPR14<def> = V_ADD_F32_e64 %VGPR13, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_F32_e64 %VGPR13<kill>, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e64 %VGPR13<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR13<def> = V_CVT_I32_F32_e32 %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_AND_B32_e32 1065353216, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR14<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e32 -6.400000e+01, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e64 %VGPR15, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_F32_e64 %VGPR15<kill>, %SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e64 %VGPR15<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR15<def> = V_CVT_I32_F32_e32 %VGPR15<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_AND_B32_e32 1065353216, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_SUB_F32_e32 %VGPR14<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR26, %VGPR22, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR25, %VGPR22<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 1.587302e-02, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 1.587302e-02, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR25, %VGPR25, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR15, %VGPR15, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR14, %VGPR14, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_RSQ_LEGACY_F32_e32 %VGPR22<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR22, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR0, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_SUB_F32_e32 %SGPR4, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR18, %SGPR5, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR22, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %SGPR0, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_SUB_F32_e32 %SGPR4, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR17, %SGPR5, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR13<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR15, %SGPR11<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %SGPR0, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %SGPR4, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR19, %SGPR5<kill>, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>
	%VGPR13<def> = V_MAD_F32 %VGPR18, %SGPR12<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR13, %VGPR23, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %SGPR15<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR15, %SGPR14<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR18, %SGPR16<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR14, %VGPR21, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %VGPR19<kill>, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %SGPR0, %VGPR12, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 %SGPR4, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR19, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR14, %VGPR0, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %SGPR9<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR15<kill>, %SGPR8<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR18<kill>, %SGPR10<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR15, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_SUB_F32_e32 %VGPR16<kill>, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR19, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR16, %VGPR16, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR17, %VGPR17, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR15, %VGPR21<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR13, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_SUB_F32_e32 %VGPR0<kill>, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR19<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR0, %VGPR0, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_RSQ_LEGACY_F32_e32 %VGPR18<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR18<kill>, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR16<kill>, %VGPR17<kill>, %VGPR0<kill>, %VGPR12<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_MUL_F32_e32 %VGPR13, %VGPR13, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR15, %VGPR15, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR14, %VGPR14, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_RSQ_LEGACY_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR12<kill>, %VGPR14<kill>, %VGPR0<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 53; mem:LD4[%55]
	S_WAITCNT 15
	%VGPR0<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 52; mem:LD4[%53]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR5<kill>, %SGPR1<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 54; mem:LD4[%57]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR8<kill>, %SGPR1<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 55; mem:LD4[%59]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 13; mem:LD4[%19]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 36, 0, 0, 0, %VGPR7, %VGPR9, %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3, 228; mem:LD4[%117]
	S_WAITCNT 15
	%VGPR0<def> = V_MAD_F32 %SGPR1<kill>, %VGPR11, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR11, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR2_SGPR3<kill>, 229; mem:LD4[%119]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR9<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR11<kill>, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
c0840700
bf8c007f
e00c2000
80020700
c084070c
bf8c0070
e00c2000
80020100
c0410100
bf8c0070
c002830c
bf8c007f
d282000b
041c0b01
d282000c
04200b02
c00583d9
bf8c007f
100a180b
c00683d8
bf8c007f
d2820005
04141b0b
d282000d
04240b03
c00603da
bf8c007f
d2820005
0414190d
c00203db
bf8c007f
d2820005
0414090a
c00403dd
bf8c007f
100c1808
c00483dc
bf8c007f
d2820006
0418130b
c00503de
bf8c007f
d2820006
0418150d
c00203df
bf8c007f
d2820006
0418090a
c0020321
bf8c007f
101c0c04
c0020320
bf8c007f
d282000e
04380905
c00703e1
bf8c007f
1018180e
c00783e0
bf8c007f
d282000b
04301f0b
c00803e2
bf8c007f
d282000b
042c210d
c00203e3
bf8c007f
d2820008
042c090a
c0020322
bf8c007f
d2820007
04380908
c0020301
c0088323
bf8c007f
7e120211
d2820007
041e1204
c0088325
bf8c007f
10120c11
c0088324
bf8c007f
d2820009
04242305
c0088326
bf8c007f
d2820009
04242308
c0088327
bf8c007f
7e140211
d2820009
04261404
c0400102
bf8c007f
c008810d
bf8c007f
10141211
c008810c
bf8c007f
d282000b
042a0e11
c0088329
bf8c007f
10140c11
c0088328
bf8c007f
d282000a
04282305
c008832a
bf8c007f
d282000a
04282308
c008832b
bf8c007f
7e180211
d282000a
042a1804
c008810e
bf8c007f
d282000c
042e1411
c008832d
bf8c007f
10160c11
c008832c
bf8c007f
d282000b
042c2305
c008832e
bf8c007f
d282000b
042c2308
c008832f
bf8c007f
7e1a0211
d282000b
042e1a04
c008810f
bf8c007f
d282000c
04321611
c0088109
bf8c007f
101a1211
c0088108
bf8c007f
d282000d
04360e11
c008810a
bf8c007f
d282000d
04361411
c008810b
bf8c007f
d282000d
04361611
c0088105
bf8c007f
101c1211
c0088104
bf8c007f
d282000e
043a0e11
c0088106
bf8c007f
d282000e
043a1411
c0088107
bf8c007f
d282000e
043a1611
c0088101
bf8c007f
101e1211
c0088100
bf8c007f
d282000f
043e0e11
c0088102
bf8c007f
d282000f
043e1411
c0088103
bf8c007f
d282000f
043e1611
f80000ef
0c0d0e0f
c008811d
bf8c000f
10181211
c008811c
bf8c007f
d282000c
04320e11
c008811e
bf8c007f
d282000c
04321411
c008811f
bf8c007f
d282000c
04321611
c0088119
bf8c007f
101a1211
c0088118
bf8c007f
d282000d
04360e11
c008811a
bf8c007f
d282000d
04361411
c008811b
bf8c007f
d282000d
04361611
c0088115
bf8c007f
101c1211
c0088114
bf8c007f
d282000e
043a0e11
c0088116
bf8c007f
d282000e
043a1411
c0088117
bf8c007f
d282000e
043a1611
c0088111
bf8c007f
101e1211
c0088110
bf8c007f
d282000f
043e0e11
c0088112
bf8c007f
d282000f
043e1411
c0000113
bf8c007f
d282000f
043e1600
f80000ff
0c0d0e0f
c08a0708
bf8c000f
e00c2000
80050c00
c00003d5
bf8c0070
10201a00
c00003d4
bf8c007f
d2820010
0440010c
c00003d6
bf8c007f
d2820010
0440010e
c00003d7
bf8c007f
d2820010
0440010f
c00003d1
bf8c007f
10221a00
c00003d0
bf8c007f
d2820011
0444010c
c00003d2
bf8c007f
d2820011
0444010e
c00003d3
bf8c007f
d2820011
0444010f
c00003c5
bf8c007f
10241a00
c00003c4
bf8c007f
d2820012
0448010c
c00003c6
bf8c007f
d2820012
0448010e
c00003c7
bf8c007f
d2820012
0448010f
c00003c1
bf8c007f
10261a00
c00003c0
bf8c007f
d2820013
044c010c
c00003c2
bf8c007f
d2820013
044c010e
c00003c3
bf8c007f
d282000c
044c010f
f800020f
1011120c
c08a0704
bf8c000f
e00c2000
80050d00
bf8c0770
061820ff
c3000000
d2060111
0201010c
c0008300
bf8c007f
d0020012
0200030c
d200000c
0049e480
d206000c
2201010c
7e18110c
361818f2
08221911
062222ff
c2800000
d2060112
02010111
d0020012
02000311
d2000011
0049e480
d2060011
22010111
7e221111
362222f2
08242312
06281eff
c3000000
d2060113
02010114
d0020012
02000314
d2000014
0049e480
d2060014
22010114
7e281114
362a28f2
08262b13
062826ff
c2800000
d2060113
02010114
d0020012
02000314
d2000014
0049e480
d2060014
22010114
7e281114
363428f2
08263513
7e2c02ff
bc820821
d2820014
03ca2d13
d2820017
04522d12
103024ff
3c820821
103826ff
3c820821
1024391c
d2820012
044a3118
d2820012
044a2f17
7e365b12
10243718
c0000302
bf8c007f
10222200
08222204
10322511
c08a0710
bf8c007f
e00c2000
80051100
bf8c0770
d2820019
04640b12
1000371c
10343400
08343404
1000011a
d282001a
04000b11
10003409
d2820000
04001119
102e3717
102a2a00
082a2a04
102a2f15
d2820017
04540b13
d2820000
04001517
102a340d
d2820015
04541719
d2820015
04541917
10362b15
d282001b
046e0100
1034340f
d2820019
04681d19
d2820017
04642117
d2820019
046e2f17
7e325b19
10343317
10363300
10323315
f800021f
181a1b19
bf8c070f
06321cff
c3000000
d2060118
02010119
d0020006
02000319
d2000019
0019e480
d2060019
22010119
7e321119
363232f2
08303318
063030ff
c2800000
d2060119
02010118
d0020006
02000318
d2000018
0019e480
d2060018
22010118
7e301118
363030f2
08323119
061a1aff
c3000000
d206010e
0201010d
d0020006
0200030d
d200000d
0019e480
d206000d
2201010d
7e1a110d
361a1af2
081c1b0e
061e1cff
c2800000
d206010e
0201010f
d0020006
0200030f
d200000f
0019e480
d206000f
2201010f
7e1e110f
36201ef2
0834210e
d282000e
03ca2d1a
d282000e
043a2d19
101e32ff
3c820821
103234ff
3c820821
102c3319
d2820016
045a1f0f
d2820016
045a1d0e
7e2c5b16
101e2d0f
10303000
08303004
101e1f18
d282000f
043c0b12
10302d19
10202000
08202004
10203110
d2820010
04400b11
1030200d
d2820018
0460170f
101c2d0e
101a1a00
081a1a04
101a1d0d
d2820012
04340b13
d282000d
04601912
10222f0d
101c200f
d282000e
04381d0f
d282000e
04382112
10262b0e
08222313
10261800
08262604
10222313
1028010e
10202009
d282000f
0440110f
d282000f
043c1512
10202f0f
08202910
10202113
10242110
d2820012
044a2311
10282b0f
1000010d
08002900
10000113
d2820012
044a0100
7e245b12
10002500
10222511
10202510
f800022f
0c001110
bf8c070f
10001b0d
d2820000
04021f0f
d2820000
04021d0e
7e185b00
1000190e
101c190f
1018190d
7e1a0280
f800023f
0d000e0c
c0008335
bf8c000f
10000c01
c0008334
bf8c007f
d2820000
04000305
c0008336
bf8c007f
d2820000
04000308
c0008337
bf8c007f
7e0a0201
d2820000
04020a04
c000830d
bf8c007f
10020801
f800024f
01000907
c00083e4
bf8c000f
d2820000
041e1601
10021400
08021701
c00003e5
bf8c007f
10041600
08041302
f80008cf
0b010200
bf810000
FRAG
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL IN[3], GENERIC[22], PERSPECTIVE
DCL IN[4], GENERIC[23], PERSPECTIVE
DCL IN[5], GENERIC[24], PERSPECTIVE
DCL IN[6], GENERIC[25], PERSPECTIVE
DCL IN[7], GENERIC[26], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..30]
DCL TEMP[0..22], LOCAL
DCL TEMP[23], ARRAY(1), LOCAL
IMM[0] FLT32 {    2.0000,    -1.0000,     0.0000,     1.0000}
IMM[1] FLT32 {  149.0000,    -0.5000,     0.5000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[1], 2D
  2: MOV TEMP[1].xy, IN[0].xyyy
  3: TEX TEMP[2].xy, TEMP[1], SAMP[2], 2D
  4: MOV TEMP[3].xy, IN[0].xyyy
  5: TEX TEMP[4], TEMP[3], SAMP[0], 2D
  6: MOV TEMP[5].xy, IN[0].xyyy
  7: TEX TEMP[5].xyz, TEMP[5], SAMP[3], 2D
  8: ADD TEMP[6].xyz, -IN[6].xyzz, CONST[23].xyzz
  9: DP3 TEMP[7].x, IN[2].xyzz, IN[2].xyzz
 10: DP3 TEMP[8].x, TEMP[6].xyzz, TEMP[6].xyzz
 11: RSQ TEMP[8].x, TEMP[8].xxxx
 12: MUL TEMP[8].xyz, TEMP[6].xyzz, TEMP[8].xxxx
 13: RSQ TEMP[9].x, TEMP[7].xxxx
 14: MUL TEMP[6].xyz, TEMP[9].xxxx, IN[2].xyzz
 15: MAD TEMP[7].xyz, IMM[0].xxxx, TEMP[0].xyzz, IMM[0].yyyy
 16: ADD TEMP[1].xyz, -TEMP[7].xyzz, IMM[0].zzww
 17: MAD TEMP[1].xyz, CONST[27].xxxx, TEMP[1].xyzz, TEMP[7].xyzz
 18: MUL TEMP[7].xyz, TEMP[1].yyyy, IN[4].xyzz
 19: MAD TEMP[7].xyz, IN[3].xyzz, TEMP[1].xxxx, TEMP[7].xyzz
 20: MAD TEMP[1].xyz, IN[5].xyzz, TEMP[1].zzzz, TEMP[7].xyzz
 21: DP3 TEMP[10].x, TEMP[1].xyzz, TEMP[1].xyzz
 22: RSQ TEMP[10].x, TEMP[10].xxxx
 23: MUL TEMP[10].xyz, TEMP[1].xyzz, TEMP[10].xxxx
 24: DP3 TEMP[11].x, TEMP[10].xyzz, TEMP[6].xyzz
 25: MUL TEMP[1].xyz, TEMP[10].xyzz, TEMP[11].xxxx
 26: ADD TEMP[1].xyz, TEMP[1].xyzz, TEMP[1].xyzz
 27: MAD TEMP[6].xyz, IN[2].xyzz, -TEMP[9].xxxx, TEMP[1].xyzz
 28: MAD TEMP[12].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[0].wwww
 29: DP3 TEMP[1].x, TEMP[6].xyzz, TEMP[8].xyzz
 30: MOV_SAT TEMP[1].x, TEMP[1].xxxx
 31: SGE TEMP[13].x, CONST[11].wwww, IMM[0].zzzz
 32: F2I TEMP[13].x, -TEMP[13]
 33: UIF TEMP[13].xxxx :0
 34:   MOV TEMP[13].x, CONST[11].wwww
 35: ELSE :0
 36:   MOV TEMP[13].x, TEMP[12].xxxx
 37: ENDIF
 38: DP3 TEMP[12].x, TEMP[10].xyzz, TEMP[8].xyzz
 39: POW TEMP[14].x, TEMP[1].xxxx, TEMP[13].xxxx
 40: MOV_SAT TEMP[15].x, TEMP[12].xxxx
 41: MUL TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx
 42: MUL TEMP[7].xyz, IN[1].yyyy, CONST[22].xyzz
 43: MUL TEMP[1].xyz, TEMP[14].xxxx, TEMP[7].xyzz
 44: ADD TEMP[14].xyz, -IN[6].xyzz, CONST[21].xyzz
 45: DP3 TEMP[15].x, TEMP[14].xyzz, TEMP[14].xyzz
 46: RSQ TEMP[15].x, TEMP[15].xxxx
 47: MUL TEMP[8].xyz, TEMP[14].xyzz, TEMP[15].xxxx
 48: DP3 TEMP[15].x, TEMP[6].xyzz, TEMP[8].xyzz
 49: MOV_SAT TEMP[15].x, TEMP[15].xxxx
 50: DP3 TEMP[16].x, TEMP[10].xyzz, TEMP[8].xyzz
 51: MUL TEMP[14].xyz, IN[1].xxxx, CONST[20].xyzz
 52: ADD TEMP[17].xyz, -IN[6].xyzz, CONST[25].xyzz
 53: DP3 TEMP[18].x, TEMP[17].xyzz, TEMP[17].xyzz
 54: RSQ TEMP[18].x, TEMP[18].xxxx
 55: MUL TEMP[8].xyz, TEMP[17].xyzz, TEMP[18].xxxx
 56: DP3 TEMP[3].x, TEMP[6].xyzz, TEMP[8].xyzz
 57: MOV_SAT TEMP[3].x, TEMP[3].xxxx
 58: ADD TEMP[11].x, -TEMP[11].xxxx, IMM[0].wwww
 59: MOV_SAT TEMP[11].x, TEMP[11].xxxx
 60: DP3 TEMP[18].x, TEMP[10].xyzz, TEMP[8].xyzz
 61: MOV TEMP[8].x, CONST[23].wwww
 62: MOV_SAT TEMP[19].x, TEMP[16].xxxx
 63: MOV TEMP[8].y, CONST[24].wwww
 64: POW TEMP[20].x, TEMP[15].xxxx, TEMP[13].xxxx
 65: MUL TEMP[19].x, TEMP[20].xxxx, TEMP[19].xxxx
 66: MOV TEMP[8].z, CONST[25].wwww
 67: ADD TEMP[17].xyz, TEMP[8].xyzz, -IN[6].xyzz
 68: DP3 TEMP[20].x, TEMP[17].xyzz, TEMP[17].xyzz
 69: RSQ TEMP[20].x, TEMP[20].xxxx
 70: MUL TEMP[8].xyz, TEMP[17].xyzz, TEMP[20].xxxx
 71: POW TEMP[20].x, TEMP[3].xxxx, TEMP[13].xxxx
 72: MOV_SAT TEMP[21].x, TEMP[18].xxxx
 73: MUL TEMP[20].x, TEMP[20].xxxx, TEMP[21].xxxx
 74: DP3 TEMP[6].x, TEMP[6].xyzz, TEMP[8].xyzz
 75: MOV_SAT TEMP[6].x, TEMP[6].xxxx
 76: DP3 TEMP[21].x, TEMP[10].xyzz, TEMP[8].xyzz
 77: POW TEMP[13].x, TEMP[6].xxxx, TEMP[13].xxxx
 78: MAD TEMP[1].xyz, TEMP[19].xxxx, TEMP[14].xyzz, TEMP[1].xyzz
 79: MOV_SAT TEMP[19].x, TEMP[21].xxxx
 80: MUL TEMP[6].xyz, IN[1].zzzz, CONST[24].xyzz
 81: MUL TEMP[13].x, TEMP[13].xxxx, TEMP[19].xxxx
 82: MAD TEMP[1].xyz, TEMP[20].xxxx, TEMP[6].xyzz, TEMP[1].xyzz
 83: MAD TEMP[11].x, TEMP[11].xxxx, TEMP[11].xxxx, IMM[1].yyyy
 84: MOV TEMP[8].x, CONST[20].wwww
 85: SGE TEMP[19].x, TEMP[11].xxxx, IMM[0].zzzz
 86: F2I TEMP[19].x, -TEMP[19]
 87: UIF TEMP[19].xxxx :0
 88:   MOV TEMP[19].x, CONST[19].zzzz
 89: ELSE :0
 90:   MOV TEMP[19].x, CONST[19].xxxx
 91: ENDIF
 92: MOV TEMP[8].y, CONST[21].wwww
 93: MAD TEMP[11].x, TEMP[19].xxxx, TEMP[11].xxxx, CONST[19].yyyy
 94: MOV TEMP[8].z, CONST[22].wwww
 95: ADD TEMP[19].x, TEMP[4].wwww, -TEMP[0].wwww
 96: MAD TEMP[19].x, CONST[27].xxxx, TEMP[19].xxxx, TEMP[0].wwww
 97: MUL TEMP[8].xyz, TEMP[8].xyzz, IN[6].wwww
 98: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[19].xxxx
 99: MAD TEMP[1].xyz, TEMP[13].xxxx, TEMP[8].xyzz, TEMP[1].xyzz
100: MUL TEMP[11].x, TEMP[11].xxxx, CONST[19].wwww
101: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[11].xxxx
102: MUL TEMP[15].xyz, TEMP[10].xyzz, TEMP[10].xyzz
103: SGE TEMP[11].x, TEMP[10].xxxx, IMM[0].zzzz
104: F2I TEMP[11].x, -TEMP[11]
105: UIF TEMP[11].xxxx :0
106:   MOV TEMP[11].x, IMM[0].zzzz
107: ELSE :0
108:   MOV TEMP[11].x, TEMP[15].xxxx
109: ENDIF
110: SGE TEMP[13].x, TEMP[10].yyyy, IMM[0].zzzz
111: F2I TEMP[13].x, -TEMP[13]
112: UIF TEMP[13].xxxx :0
113:   MOV TEMP[13].x, IMM[0].zzzz
114: ELSE :0
115:   MOV TEMP[13].x, TEMP[15].yyyy
116: ENDIF
117: SGE TEMP[19].x, TEMP[10].zzzz, IMM[0].zzzz
118: F2I TEMP[19].x, -TEMP[19]
119: UIF TEMP[19].xxxx :0
120:   MOV TEMP[19].x, IMM[0].zzzz
121: ELSE :0
122:   MOV TEMP[19].x, TEMP[15].zzzz
123: ENDIF
124: SGE TEMP[20].x, TEMP[10].xxxx, IMM[0].zzzz
125: F2I TEMP[20].x, -TEMP[20]
126: UIF TEMP[20].xxxx :0
127:   MOV TEMP[20].x, TEMP[15].xxxx
128: ELSE :0
129:   MOV TEMP[20].x, IMM[0].zzzz
130: ENDIF
131: SGE TEMP[22].x, TEMP[10].yyyy, IMM[0].zzzz
132: F2I TEMP[22].x, -TEMP[22]
133: UIF TEMP[22].xxxx :0
134:   MOV TEMP[22].x, TEMP[15].yyyy
135: ELSE :0
136:   MOV TEMP[22].x, IMM[0].zzzz
137: ENDIF
138: SGE TEMP[10].x, TEMP[10].zzzz, IMM[0].zzzz
139: F2I TEMP[10].x, -TEMP[10]
140: UIF TEMP[10].xxxx :0
141:   MOV TEMP[10].x, TEMP[15].zzzz
142: ELSE :0
143:   MOV TEMP[10].x, IMM[0].zzzz
144: ENDIF
145: MUL TEMP[15].xyz, TEMP[11].xxxx, CONST[5].xyzz
146: MAD TEMP[11].x, TEMP[12].xxxx, IMM[1].zzzz, IMM[1].zzzz
147: MOV_SAT TEMP[11].x, TEMP[11].xxxx
148: MAD TEMP[15].xyz, TEMP[20].xxxx, CONST[4].xyzz, TEMP[15].xyzz
149: MAD TEMP[12].x, TEMP[16].xxxx, IMM[1].zzzz, IMM[1].zzzz
150: MOV_SAT TEMP[12].x, TEMP[12].xxxx
151: MAD TEMP[15].xyz, TEMP[22].xxxx, CONST[6].xyzz, TEMP[15].xyzz
152: MAD TEMP[16].x, TEMP[18].xxxx, IMM[1].zzzz, IMM[1].zzzz
153: MOV_SAT TEMP[16].x, TEMP[16].xxxx
154: MAD TEMP[15].xyz, TEMP[13].xxxx, CONST[7].xyzz, TEMP[15].xyzz
155: MAD TEMP[13].x, TEMP[21].xxxx, IMM[1].zzzz, IMM[1].zzzz
156: MOV_SAT TEMP[13].x, TEMP[13].xxxx
157: MAD TEMP[9].xyz, TEMP[10].xxxx, CONST[8].xyzz, TEMP[15].xyzz
158: MAD TEMP[17].xyz, TEMP[19].xxxx, CONST[9].xyzz, TEMP[9].xyzz
159: MUL TEMP[9].x, TEMP[12].xxxx, TEMP[12].xxxx
160: MAD TEMP[14].xyz, TEMP[14].xyzz, TEMP[9].xxxx, TEMP[17].xyzz
161: MUL TEMP[9].x, TEMP[11].xxxx, TEMP[11].xxxx
162: MAD TEMP[7].xyz, TEMP[7].xyzz, TEMP[9].xxxx, TEMP[14].xyzz
163: MUL TEMP[9].x, TEMP[16].xxxx, TEMP[16].xxxx
164: MAD TEMP[6].xyz, TEMP[6].xyzz, TEMP[9].xxxx, TEMP[7].xyzz
165: MUL TEMP[9].x, TEMP[13].xxxx, TEMP[13].xxxx
166: MAD TEMP[6].xyz, TEMP[8].xyzz, TEMP[9].xxxx, TEMP[6].xyzz
167: MUL TEMP[8].xyz, TEMP[4].xyzz, CONST[1].xyzz
168: MUL TEMP[7].xyz, TEMP[6].xyzz, TEMP[8].xyzz
169: MAD TEMP[6].xyz, CONST[0].xyzz, TEMP[8].xyzz, -TEMP[7].xyzz
170: ADD TEMP[5].xyz, TEMP[5].xyzz, -TEMP[4].wwww
171: MAD TEMP[8].xyz, CONST[10].wwww, TEMP[5].xyzz, TEMP[4].wwww
172: ADD TEMP[4].xyz, TEMP[4].xyzz, IMM[0].yyyy
173: MAD TEMP[8].xyz, TEMP[8].xyzz, TEMP[6].xyzz, TEMP[7].xyzz
174: MAX TEMP[5].xyz, TEMP[8].xyzz, IMM[0].zzzz
175: MAD TEMP[3].xyz, TEMP[2].yyyy, TEMP[4].xyzz, IMM[0].wwww
176: SGE TEMP[2].x, CONST[26].xxxx, IMM[0].zzzz
177: F2I TEMP[2].x, -TEMP[2]
178: UIF TEMP[2].xxxx :0
179:   MOV TEMP[2].x, CONST[26].xxxx
180: ELSE :0
181:   MOV TEMP[2].x, TEMP[3].xxxx
182: ENDIF
183: MOV TEMP[3].x, TEMP[2].xxxx
184: SGE TEMP[2].x, CONST[26].xxxx, IMM[0].zzzz
185: F2I TEMP[2].x, -TEMP[2]
186: UIF TEMP[2].xxxx :0
187:   MOV TEMP[2].x, CONST[26].yyyy
188: ELSE :0
189:   MOV TEMP[2].x, TEMP[3].yyyy
190: ENDIF
191: MOV TEMP[3].y, TEMP[2].xxxx
192: SGE TEMP[2].x, CONST[26].xxxx, IMM[0].zzzz
193: F2I TEMP[2].x, -TEMP[2]
194: UIF TEMP[2].xxxx :0
195:   MOV TEMP[2].x, CONST[26].zzzz
196: ELSE :0
197:   MOV TEMP[2].x, TEMP[3].zzzz
198: ENDIF
199: MOV TEMP[3].z, TEMP[2].xxxx
200: MAD TEMP[2].x, IN[7].zzzz, CONST[12].wwww, -CONST[12].xxxx
201: MAD TEMP[3].xyz, TEMP[1].xyzz, TEMP[3].xyzz, TEMP[5].xyzz
202: MIN TEMP[1].x, TEMP[2].xxxx, CONST[12].zzzz
203: MOV_SAT TEMP[1].x, TEMP[1].xxxx
204: MAD TEMP[0].xyz, TEMP[3].xyzz, -CONST[30].xxxx, CONST[29].xyzz
205: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
206: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx
207: MAD TEMP[3].xyz, TEMP[3].xyzz, CONST[30].xxxx, TEMP[0].xyzz
208: MUL TEMP[0].x, IN[7].zzzz, CONST[29].wwww
209: MOV TEMP[3].w, TEMP[0].xxxx
210: MOV TEMP[23], TEMP[3]
211: MOV OUT[0], TEMP[23]
212: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !0
  %22 = getelementptr float addrspace(2)* %21, i32 0
  %23 = load float addrspace(2)* %22, !tbaa !0
  %24 = getelementptr float addrspace(2)* %21, i32 1
  %25 = load float addrspace(2)* %24, !tbaa !0
  %26 = getelementptr float addrspace(2)* %21, i32 2
  %27 = load float addrspace(2)* %26, !tbaa !0
  %28 = getelementptr float addrspace(2)* %21, i32 4
  %29 = load float addrspace(2)* %28, !tbaa !0
  %30 = getelementptr float addrspace(2)* %21, i32 5
  %31 = load float addrspace(2)* %30, !tbaa !0
  %32 = getelementptr float addrspace(2)* %21, i32 6
  %33 = load float addrspace(2)* %32, !tbaa !0
  %34 = getelementptr float addrspace(2)* %21, i32 16
  %35 = load float addrspace(2)* %34, !tbaa !0
  %36 = getelementptr float addrspace(2)* %21, i32 17
  %37 = load float addrspace(2)* %36, !tbaa !0
  %38 = getelementptr float addrspace(2)* %21, i32 18
  %39 = load float addrspace(2)* %38, !tbaa !0
  %40 = getelementptr float addrspace(2)* %21, i32 20
  %41 = load float addrspace(2)* %40, !tbaa !0
  %42 = getelementptr float addrspace(2)* %21, i32 21
  %43 = load float addrspace(2)* %42, !tbaa !0
  %44 = getelementptr float addrspace(2)* %21, i32 22
  %45 = load float addrspace(2)* %44, !tbaa !0
  %46 = getelementptr float addrspace(2)* %21, i32 24
  %47 = load float addrspace(2)* %46, !tbaa !0
  %48 = getelementptr float addrspace(2)* %21, i32 25
  %49 = load float addrspace(2)* %48, !tbaa !0
  %50 = getelementptr float addrspace(2)* %21, i32 26
  %51 = load float addrspace(2)* %50, !tbaa !0
  %52 = getelementptr float addrspace(2)* %21, i32 28
  %53 = load float addrspace(2)* %52, !tbaa !0
  %54 = getelementptr float addrspace(2)* %21, i32 29
  %55 = load float addrspace(2)* %54, !tbaa !0
  %56 = getelementptr float addrspace(2)* %21, i32 30
  %57 = load float addrspace(2)* %56, !tbaa !0
  %58 = getelementptr float addrspace(2)* %21, i32 32
  %59 = load float addrspace(2)* %58, !tbaa !0
  %60 = getelementptr float addrspace(2)* %21, i32 33
  %61 = load float addrspace(2)* %60, !tbaa !0
  %62 = getelementptr float addrspace(2)* %21, i32 34
  %63 = load float addrspace(2)* %62, !tbaa !0
  %64 = getelementptr float addrspace(2)* %21, i32 36
  %65 = load float addrspace(2)* %64, !tbaa !0
  %66 = getelementptr float addrspace(2)* %21, i32 37
  %67 = load float addrspace(2)* %66, !tbaa !0
  %68 = getelementptr float addrspace(2)* %21, i32 38
  %69 = load float addrspace(2)* %68, !tbaa !0
  %70 = getelementptr float addrspace(2)* %21, i32 43
  %71 = load float addrspace(2)* %70, !tbaa !0
  %72 = getelementptr float addrspace(2)* %21, i32 47
  %73 = load float addrspace(2)* %72, !tbaa !0
  %74 = getelementptr float addrspace(2)* %21, i32 48
  %75 = load float addrspace(2)* %74, !tbaa !0
  %76 = getelementptr float addrspace(2)* %21, i32 50
  %77 = load float addrspace(2)* %76, !tbaa !0
  %78 = getelementptr float addrspace(2)* %21, i32 51
  %79 = load float addrspace(2)* %78, !tbaa !0
  %80 = getelementptr float addrspace(2)* %21, i32 76
  %81 = load float addrspace(2)* %80, !tbaa !0
  %82 = getelementptr float addrspace(2)* %21, i32 77
  %83 = load float addrspace(2)* %82, !tbaa !0
  %84 = getelementptr float addrspace(2)* %21, i32 78
  %85 = load float addrspace(2)* %84, !tbaa !0
  %86 = getelementptr float addrspace(2)* %21, i32 79
  %87 = load float addrspace(2)* %86, !tbaa !0
  %88 = getelementptr float addrspace(2)* %21, i32 80
  %89 = load float addrspace(2)* %88, !tbaa !0
  %90 = getelementptr float addrspace(2)* %21, i32 81
  %91 = load float addrspace(2)* %90, !tbaa !0
  %92 = getelementptr float addrspace(2)* %21, i32 82
  %93 = load float addrspace(2)* %92, !tbaa !0
  %94 = getelementptr float addrspace(2)* %21, i32 83
  %95 = load float addrspace(2)* %94, !tbaa !0
  %96 = getelementptr float addrspace(2)* %21, i32 84
  %97 = load float addrspace(2)* %96, !tbaa !0
  %98 = getelementptr float addrspace(2)* %21, i32 85
  %99 = load float addrspace(2)* %98, !tbaa !0
  %100 = getelementptr float addrspace(2)* %21, i32 86
  %101 = load float addrspace(2)* %100, !tbaa !0
  %102 = getelementptr float addrspace(2)* %21, i32 87
  %103 = load float addrspace(2)* %102, !tbaa !0
  %104 = getelementptr float addrspace(2)* %21, i32 88
  %105 = load float addrspace(2)* %104, !tbaa !0
  %106 = getelementptr float addrspace(2)* %21, i32 89
  %107 = load float addrspace(2)* %106, !tbaa !0
  %108 = getelementptr float addrspace(2)* %21, i32 90
  %109 = load float addrspace(2)* %108, !tbaa !0
  %110 = getelementptr float addrspace(2)* %21, i32 91
  %111 = load float addrspace(2)* %110, !tbaa !0
  %112 = getelementptr float addrspace(2)* %21, i32 92
  %113 = load float addrspace(2)* %112, !tbaa !0
  %114 = getelementptr float addrspace(2)* %21, i32 93
  %115 = load float addrspace(2)* %114, !tbaa !0
  %116 = getelementptr float addrspace(2)* %21, i32 94
  %117 = load float addrspace(2)* %116, !tbaa !0
  %118 = getelementptr float addrspace(2)* %21, i32 95
  %119 = load float addrspace(2)* %118, !tbaa !0
  %120 = getelementptr float addrspace(2)* %21, i32 96
  %121 = load float addrspace(2)* %120, !tbaa !0
  %122 = getelementptr float addrspace(2)* %21, i32 97
  %123 = load float addrspace(2)* %122, !tbaa !0
  %124 = getelementptr float addrspace(2)* %21, i32 98
  %125 = load float addrspace(2)* %124, !tbaa !0
  %126 = getelementptr float addrspace(2)* %21, i32 99
  %127 = load float addrspace(2)* %126, !tbaa !0
  %128 = getelementptr float addrspace(2)* %21, i32 100
  %129 = load float addrspace(2)* %128, !tbaa !0
  %130 = getelementptr float addrspace(2)* %21, i32 101
  %131 = load float addrspace(2)* %130, !tbaa !0
  %132 = getelementptr float addrspace(2)* %21, i32 102
  %133 = load float addrspace(2)* %132, !tbaa !0
  %134 = getelementptr float addrspace(2)* %21, i32 103
  %135 = load float addrspace(2)* %134, !tbaa !0
  %136 = getelementptr float addrspace(2)* %21, i32 104
  %137 = load float addrspace(2)* %136, !tbaa !0
  %138 = getelementptr float addrspace(2)* %21, i32 105
  %139 = load float addrspace(2)* %138, !tbaa !0
  %140 = getelementptr float addrspace(2)* %21, i32 106
  %141 = load float addrspace(2)* %140, !tbaa !0
  %142 = getelementptr float addrspace(2)* %21, i32 108
  %143 = load float addrspace(2)* %142, !tbaa !0
  %144 = getelementptr float addrspace(2)* %21, i32 116
  %145 = load float addrspace(2)* %144, !tbaa !0
  %146 = getelementptr float addrspace(2)* %21, i32 117
  %147 = load float addrspace(2)* %146, !tbaa !0
  %148 = getelementptr float addrspace(2)* %21, i32 118
  %149 = load float addrspace(2)* %148, !tbaa !0
  %150 = getelementptr float addrspace(2)* %21, i32 119
  %151 = load float addrspace(2)* %150, !tbaa !0
  %152 = getelementptr float addrspace(2)* %21, i32 120
  %153 = load float addrspace(2)* %152, !tbaa !0
  %154 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %155 = load <32 x i8> addrspace(2)* %154, !tbaa !0
  %156 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %157 = load <16 x i8> addrspace(2)* %156, !tbaa !0
  %158 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %159 = load <32 x i8> addrspace(2)* %158, !tbaa !0
  %160 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %161 = load <16 x i8> addrspace(2)* %160, !tbaa !0
  %162 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %163 = load <32 x i8> addrspace(2)* %162, !tbaa !0
  %164 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %165 = load <16 x i8> addrspace(2)* %164, !tbaa !0
  %166 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %167 = load <32 x i8> addrspace(2)* %166, !tbaa !0
  %168 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %169 = load <16 x i8> addrspace(2)* %168, !tbaa !0
  %170 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %171 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %172 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %173 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %174 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %175 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %176 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %177 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %178 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
  %179 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
  %180 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
  %181 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
  %182 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
  %183 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
  %184 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
  %185 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
  %186 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
  %187 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %5)
  %188 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %5)
  %189 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %3, <2 x i32> %5)
  %190 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %3, <2 x i32> %5)
  %191 = call float @llvm.SI.fs.interp(i32 2, i32 7, i32 %3, <2 x i32> %5)
  %192 = bitcast float %170 to i32
  %193 = bitcast float %171 to i32
  %194 = insertelement <2 x i32> undef, i32 %192, i32 0
  %195 = insertelement <2 x i32> %194, i32 %193, i32 1
  %196 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %195, <32 x i8> %159, <16 x i8> %161, i32 2)
  %197 = extractelement <4 x float> %196, i32 0
  %198 = extractelement <4 x float> %196, i32 1
  %199 = extractelement <4 x float> %196, i32 2
  %200 = extractelement <4 x float> %196, i32 3
  %201 = bitcast float %170 to i32
  %202 = bitcast float %171 to i32
  %203 = insertelement <2 x i32> undef, i32 %201, i32 0
  %204 = insertelement <2 x i32> %203, i32 %202, i32 1
  %205 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %204, <32 x i8> %163, <16 x i8> %165, i32 2)
  %206 = extractelement <4 x float> %205, i32 0
  %207 = extractelement <4 x float> %205, i32 1
  %208 = bitcast float %170 to i32
  %209 = bitcast float %171 to i32
  %210 = insertelement <2 x i32> undef, i32 %208, i32 0
  %211 = insertelement <2 x i32> %210, i32 %209, i32 1
  %212 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %211, <32 x i8> %155, <16 x i8> %157, i32 2)
  %213 = extractelement <4 x float> %212, i32 0
  %214 = extractelement <4 x float> %212, i32 1
  %215 = extractelement <4 x float> %212, i32 2
  %216 = extractelement <4 x float> %212, i32 3
  %217 = bitcast float %170 to i32
  %218 = bitcast float %171 to i32
  %219 = insertelement <2 x i32> undef, i32 %217, i32 0
  %220 = insertelement <2 x i32> %219, i32 %218, i32 1
  %221 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %220, <32 x i8> %167, <16 x i8> %169, i32 2)
  %222 = extractelement <4 x float> %221, i32 0
  %223 = extractelement <4 x float> %221, i32 1
  %224 = extractelement <4 x float> %221, i32 2
  %225 = fsub float -0.000000e+00, %187
  %226 = fadd float %225, %113
  %227 = fsub float -0.000000e+00, %188
  %228 = fadd float %227, %115
  %229 = fsub float -0.000000e+00, %189
  %230 = fadd float %229, %117
  %231 = fmul float %175, %175
  %232 = fmul float %176, %176
  %233 = fadd float %232, %231
  %234 = fmul float %177, %177
  %235 = fadd float %233, %234
  %236 = fmul float %226, %226
  %237 = fmul float %228, %228
  %238 = fadd float %237, %236
  %239 = fmul float %230, %230
  %240 = fadd float %238, %239
  %241 = call float @llvm.AMDGPU.rsq(float %240)
  %242 = fmul float %226, %241
  %243 = fmul float %228, %241
  %244 = fmul float %230, %241
  %245 = call float @llvm.AMDGPU.rsq(float %235)
  %246 = fmul float %245, %175
  %247 = fmul float %245, %176
  %248 = fmul float %245, %177
  %249 = fmul float 2.000000e+00, %197
  %250 = fadd float %249, -1.000000e+00
  %251 = fmul float 2.000000e+00, %198
  %252 = fadd float %251, -1.000000e+00
  %253 = fmul float 2.000000e+00, %199
  %254 = fadd float %253, -1.000000e+00
  %255 = fsub float -0.000000e+00, %250
  %256 = fadd float %255, 0.000000e+00
  %257 = fsub float -0.000000e+00, %252
  %258 = fadd float %257, 0.000000e+00
  %259 = fsub float -0.000000e+00, %254
  %260 = fadd float %259, 1.000000e+00
  %261 = fmul float %143, %256
  %262 = fadd float %261, %250
  %263 = fmul float %143, %258
  %264 = fadd float %263, %252
  %265 = fmul float %143, %260
  %266 = fadd float %265, %254
  %267 = fmul float %264, %181
  %268 = fmul float %264, %182
  %269 = fmul float %264, %183
  %270 = fmul float %178, %262
  %271 = fadd float %270, %267
  %272 = fmul float %179, %262
  %273 = fadd float %272, %268
  %274 = fmul float %180, %262
  %275 = fadd float %274, %269
  %276 = fmul float %184, %266
  %277 = fadd float %276, %271
  %278 = fmul float %185, %266
  %279 = fadd float %278, %273
  %280 = fmul float %186, %266
  %281 = fadd float %280, %275
  %282 = fmul float %277, %277
  %283 = fmul float %279, %279
  %284 = fadd float %283, %282
  %285 = fmul float %281, %281
  %286 = fadd float %284, %285
  %287 = call float @llvm.AMDGPU.rsq(float %286)
  %288 = fmul float %277, %287
  %289 = fmul float %279, %287
  %290 = fmul float %281, %287
  %291 = fmul float %288, %246
  %292 = fmul float %289, %247
  %293 = fadd float %292, %291
  %294 = fmul float %290, %248
  %295 = fadd float %293, %294
  %296 = fmul float %288, %295
  %297 = fmul float %289, %295
  %298 = fmul float %290, %295
  %299 = fadd float %296, %296
  %300 = fadd float %297, %297
  %301 = fadd float %298, %298
  %302 = fsub float -0.000000e+00, %245
  %303 = fmul float %175, %302
  %304 = fadd float %303, %299
  %305 = fsub float -0.000000e+00, %245
  %306 = fmul float %176, %305
  %307 = fadd float %306, %300
  %308 = fsub float -0.000000e+00, %245
  %309 = fmul float %177, %308
  %310 = fadd float %309, %301
  %311 = fmul float %206, 1.490000e+02
  %312 = fadd float %311, 1.000000e+00
  %313 = fmul float %304, %242
  %314 = fmul float %307, %243
  %315 = fadd float %314, %313
  %316 = fmul float %310, %244
  %317 = fadd float %315, %316
  %318 = call float @llvm.AMDIL.clamp.(float %317, float 0.000000e+00, float 1.000000e+00)
  %319 = fcmp uge float %73, 0.000000e+00
  %320 = select i1 %319, float 1.000000e+00, float 0.000000e+00
  %321 = fsub float -0.000000e+00, %320
  %322 = fptosi float %321 to i32
  %323 = bitcast i32 %322 to float
  %324 = bitcast float %323 to i32
  %325 = icmp ne i32 %324, 0
  %. = select i1 %325, float %73, float %312
  %326 = fmul float %288, %242
  %327 = fmul float %289, %243
  %328 = fadd float %327, %326
  %329 = fmul float %290, %244
  %330 = fadd float %328, %329
  %331 = call float @llvm.pow.f32(float %318, float %.)
  %332 = call float @llvm.AMDIL.clamp.(float %330, float 0.000000e+00, float 1.000000e+00)
  %333 = fmul float %331, %332
  %334 = fmul float %173, %105
  %335 = fmul float %173, %107
  %336 = fmul float %173, %109
  %337 = fmul float %333, %334
  %338 = fmul float %333, %335
  %339 = fmul float %333, %336
  %340 = fsub float -0.000000e+00, %187
  %341 = fadd float %340, %97
  %342 = fsub float -0.000000e+00, %188
  %343 = fadd float %342, %99
  %344 = fsub float -0.000000e+00, %189
  %345 = fadd float %344, %101
  %346 = fmul float %341, %341
  %347 = fmul float %343, %343
  %348 = fadd float %347, %346
  %349 = fmul float %345, %345
  %350 = fadd float %348, %349
  %351 = call float @llvm.AMDGPU.rsq(float %350)
  %352 = fmul float %341, %351
  %353 = fmul float %343, %351
  %354 = fmul float %345, %351
  %355 = fmul float %304, %352
  %356 = fmul float %307, %353
  %357 = fadd float %356, %355
  %358 = fmul float %310, %354
  %359 = fadd float %357, %358
  %360 = call float @llvm.AMDIL.clamp.(float %359, float 0.000000e+00, float 1.000000e+00)
  %361 = fmul float %288, %352
  %362 = fmul float %289, %353
  %363 = fadd float %362, %361
  %364 = fmul float %290, %354
  %365 = fadd float %363, %364
  %366 = fmul float %172, %89
  %367 = fmul float %172, %91
  %368 = fmul float %172, %93
  %369 = fsub float -0.000000e+00, %187
  %370 = fadd float %369, %129
  %371 = fsub float -0.000000e+00, %188
  %372 = fadd float %371, %131
  %373 = fsub float -0.000000e+00, %189
  %374 = fadd float %373, %133
  %375 = fmul float %370, %370
  %376 = fmul float %372, %372
  %377 = fadd float %376, %375
  %378 = fmul float %374, %374
  %379 = fadd float %377, %378
  %380 = call float @llvm.AMDGPU.rsq(float %379)
  %381 = fmul float %370, %380
  %382 = fmul float %372, %380
  %383 = fmul float %374, %380
  %384 = fmul float %304, %381
  %385 = fmul float %307, %382
  %386 = fadd float %385, %384
  %387 = fmul float %310, %383
  %388 = fadd float %386, %387
  %389 = call float @llvm.AMDIL.clamp.(float %388, float 0.000000e+00, float 1.000000e+00)
  %390 = fsub float -0.000000e+00, %295
  %391 = fadd float %390, 1.000000e+00
  %392 = call float @llvm.AMDIL.clamp.(float %391, float 0.000000e+00, float 1.000000e+00)
  %393 = fmul float %288, %381
  %394 = fmul float %289, %382
  %395 = fadd float %394, %393
  %396 = fmul float %290, %383
  %397 = fadd float %395, %396
  %398 = call float @llvm.AMDIL.clamp.(float %365, float 0.000000e+00, float 1.000000e+00)
  %399 = call float @llvm.pow.f32(float %360, float %.)
  %400 = fmul float %399, %398
  %401 = fsub float -0.000000e+00, %187
  %402 = fadd float %119, %401
  %403 = fsub float -0.000000e+00, %188
  %404 = fadd float %127, %403
  %405 = fsub float -0.000000e+00, %189
  %406 = fadd float %135, %405
  %407 = fmul float %402, %402
  %408 = fmul float %404, %404
  %409 = fadd float %408, %407
  %410 = fmul float %406, %406
  %411 = fadd float %409, %410
  %412 = call float @llvm.AMDGPU.rsq(float %411)
  %413 = fmul float %402, %412
  %414 = fmul float %404, %412
  %415 = fmul float %406, %412
  %416 = call float @llvm.pow.f32(float %389, float %.)
  %417 = call float @llvm.AMDIL.clamp.(float %397, float 0.000000e+00, float 1.000000e+00)
  %418 = fmul float %416, %417
  %419 = fmul float %304, %413
  %420 = fmul float %307, %414
  %421 = fadd float %420, %419
  %422 = fmul float %310, %415
  %423 = fadd float %421, %422
  %424 = call float @llvm.AMDIL.clamp.(float %423, float 0.000000e+00, float 1.000000e+00)
  %425 = fmul float %288, %413
  %426 = fmul float %289, %414
  %427 = fadd float %426, %425
  %428 = fmul float %290, %415
  %429 = fadd float %427, %428
  %430 = call float @llvm.pow.f32(float %424, float %.)
  %431 = fmul float %400, %366
  %432 = fadd float %431, %337
  %433 = fmul float %400, %367
  %434 = fadd float %433, %338
  %435 = fmul float %400, %368
  %436 = fadd float %435, %339
  %437 = call float @llvm.AMDIL.clamp.(float %429, float 0.000000e+00, float 1.000000e+00)
  %438 = fmul float %174, %121
  %439 = fmul float %174, %123
  %440 = fmul float %174, %125
  %441 = fmul float %430, %437
  %442 = fmul float %418, %438
  %443 = fadd float %442, %432
  %444 = fmul float %418, %439
  %445 = fadd float %444, %434
  %446 = fmul float %418, %440
  %447 = fadd float %446, %436
  %448 = fmul float %392, %392
  %449 = fadd float %448, -5.000000e-01
  %450 = fcmp uge float %449, 0.000000e+00
  %451 = select i1 %450, float 1.000000e+00, float 0.000000e+00
  %452 = fsub float -0.000000e+00, %451
  %453 = fptosi float %452 to i32
  %454 = bitcast i32 %453 to float
  %455 = bitcast float %454 to i32
  %456 = icmp ne i32 %455, 0
  %temp76.0 = select i1 %456, float %85, float %81
  %457 = fmul float %temp76.0, %449
  %458 = fadd float %457, %83
  %459 = fsub float -0.000000e+00, %200
  %460 = fadd float %216, %459
  %461 = fmul float %143, %460
  %462 = fadd float %461, %200
  %463 = fmul float %95, %190
  %464 = fmul float %103, %190
  %465 = fmul float %111, %190
  %466 = fmul float %458, %462
  %467 = fmul float %441, %463
  %468 = fadd float %467, %443
  %469 = fmul float %441, %464
  %470 = fadd float %469, %445
  %471 = fmul float %441, %465
  %472 = fadd float %471, %447
  %473 = fmul float %466, %87
  %474 = fmul float %468, %473
  %475 = fmul float %470, %473
  %476 = fmul float %472, %473
  %477 = fmul float %288, %288
  %478 = fmul float %289, %289
  %479 = fmul float %290, %290
  %480 = fcmp uge float %288, 0.000000e+00
  %481 = select i1 %480, float 1.000000e+00, float 0.000000e+00
  %482 = fsub float -0.000000e+00, %481
  %483 = fptosi float %482 to i32
  %484 = bitcast i32 %483 to float
  %485 = bitcast float %484 to i32
  %486 = icmp ne i32 %485, 0
  %.126 = select i1 %486, float 0.000000e+00, float %477
  %487 = fcmp uge float %289, 0.000000e+00
  %488 = select i1 %487, float 1.000000e+00, float 0.000000e+00
  %489 = fsub float -0.000000e+00, %488
  %490 = fptosi float %489 to i32
  %491 = bitcast i32 %490 to float
  %492 = bitcast float %491 to i32
  %493 = icmp ne i32 %492, 0
  %temp52.1 = select i1 %493, float 0.000000e+00, float %478
  %494 = fcmp uge float %290, 0.000000e+00
  %495 = select i1 %494, float 1.000000e+00, float 0.000000e+00
  %496 = fsub float -0.000000e+00, %495
  %497 = fptosi float %496 to i32
  %498 = bitcast i32 %497 to float
  %499 = bitcast float %498 to i32
  %500 = icmp ne i32 %499, 0
  %.127 = select i1 %500, float 0.000000e+00, float %479
  %501 = fcmp uge float %288, 0.000000e+00
  %502 = select i1 %501, float 1.000000e+00, float 0.000000e+00
  %503 = fsub float -0.000000e+00, %502
  %504 = fptosi float %503 to i32
  %505 = bitcast i32 %504 to float
  %506 = bitcast float %505 to i32
  %507 = icmp ne i32 %506, 0
  %temp80.0 = select i1 %507, float %477, float 0.000000e+00
  %508 = fcmp uge float %289, 0.000000e+00
  %509 = select i1 %508, float 1.000000e+00, float 0.000000e+00
  %510 = fsub float -0.000000e+00, %509
  %511 = fptosi float %510 to i32
  %512 = bitcast i32 %511 to float
  %513 = bitcast float %512 to i32
  %514 = icmp ne i32 %513, 0
  %.128 = select i1 %514, float %478, float 0.000000e+00
  %515 = fcmp uge float %290, 0.000000e+00
  %516 = select i1 %515, float 1.000000e+00, float 0.000000e+00
  %517 = fsub float -0.000000e+00, %516
  %518 = fptosi float %517 to i32
  %519 = bitcast i32 %518 to float
  %520 = bitcast float %519 to i32
  %521 = icmp ne i32 %520, 0
  %temp40.0 = select i1 %521, float %479, float 0.000000e+00
  %522 = fmul float %.126, %41
  %523 = fmul float %.126, %43
  %524 = fmul float %.126, %45
  %525 = fmul float %330, 5.000000e-01
  %526 = fadd float %525, 5.000000e-01
  %527 = call float @llvm.AMDIL.clamp.(float %526, float 0.000000e+00, float 1.000000e+00)
  %528 = fmul float %temp80.0, %35
  %529 = fadd float %528, %522
  %530 = fmul float %temp80.0, %37
  %531 = fadd float %530, %523
  %532 = fmul float %temp80.0, %39
  %533 = fadd float %532, %524
  %534 = fmul float %365, 5.000000e-01
  %535 = fadd float %534, 5.000000e-01
  %536 = call float @llvm.AMDIL.clamp.(float %535, float 0.000000e+00, float 1.000000e+00)
  %537 = fmul float %.128, %47
  %538 = fadd float %537, %529
  %539 = fmul float %.128, %49
  %540 = fadd float %539, %531
  %541 = fmul float %.128, %51
  %542 = fadd float %541, %533
  %543 = fmul float %397, 5.000000e-01
  %544 = fadd float %543, 5.000000e-01
  %545 = call float @llvm.AMDIL.clamp.(float %544, float 0.000000e+00, float 1.000000e+00)
  %546 = fmul float %temp52.1, %53
  %547 = fadd float %546, %538
  %548 = fmul float %temp52.1, %55
  %549 = fadd float %548, %540
  %550 = fmul float %temp52.1, %57
  %551 = fadd float %550, %542
  %552 = fmul float %429, 5.000000e-01
  %553 = fadd float %552, 5.000000e-01
  %554 = call float @llvm.AMDIL.clamp.(float %553, float 0.000000e+00, float 1.000000e+00)
  %555 = fmul float %temp40.0, %59
  %556 = fadd float %555, %547
  %557 = fmul float %temp40.0, %61
  %558 = fadd float %557, %549
  %559 = fmul float %temp40.0, %63
  %560 = fadd float %559, %551
  %561 = fmul float %.127, %65
  %562 = fadd float %561, %556
  %563 = fmul float %.127, %67
  %564 = fadd float %563, %558
  %565 = fmul float %.127, %69
  %566 = fadd float %565, %560
  %567 = fmul float %536, %536
  %568 = fmul float %366, %567
  %569 = fadd float %568, %562
  %570 = fmul float %367, %567
  %571 = fadd float %570, %564
  %572 = fmul float %368, %567
  %573 = fadd float %572, %566
  %574 = fmul float %527, %527
  %575 = fmul float %334, %574
  %576 = fadd float %575, %569
  %577 = fmul float %335, %574
  %578 = fadd float %577, %571
  %579 = fmul float %336, %574
  %580 = fadd float %579, %573
  %581 = fmul float %545, %545
  %582 = fmul float %438, %581
  %583 = fadd float %582, %576
  %584 = fmul float %439, %581
  %585 = fadd float %584, %578
  %586 = fmul float %440, %581
  %587 = fadd float %586, %580
  %588 = fmul float %554, %554
  %589 = fmul float %463, %588
  %590 = fadd float %589, %583
  %591 = fmul float %464, %588
  %592 = fadd float %591, %585
  %593 = fmul float %465, %588
  %594 = fadd float %593, %587
  %595 = fmul float %213, %29
  %596 = fmul float %214, %31
  %597 = fmul float %215, %33
  %598 = fmul float %590, %595
  %599 = fmul float %592, %596
  %600 = fmul float %594, %597
  %601 = fsub float -0.000000e+00, %598
  %602 = fmul float %23, %595
  %603 = fadd float %602, %601
  %604 = fsub float -0.000000e+00, %599
  %605 = fmul float %25, %596
  %606 = fadd float %605, %604
  %607 = fsub float -0.000000e+00, %600
  %608 = fmul float %27, %597
  %609 = fadd float %608, %607
  %610 = fsub float -0.000000e+00, %216
  %611 = fadd float %222, %610
  %612 = fsub float -0.000000e+00, %216
  %613 = fadd float %223, %612
  %614 = fsub float -0.000000e+00, %216
  %615 = fadd float %224, %614
  %616 = fmul float %71, %611
  %617 = fadd float %616, %216
  %618 = fmul float %71, %613
  %619 = fadd float %618, %216
  %620 = fmul float %71, %615
  %621 = fadd float %620, %216
  %622 = fadd float %213, -1.000000e+00
  %623 = fadd float %214, -1.000000e+00
  %624 = fadd float %215, -1.000000e+00
  %625 = fmul float %617, %603
  %626 = fadd float %625, %598
  %627 = fmul float %619, %606
  %628 = fadd float %627, %599
  %629 = fmul float %621, %609
  %630 = fadd float %629, %600
  %631 = fcmp uge float %626, 0.000000e+00
  %632 = select i1 %631, float %626, float 0.000000e+00
  %633 = fcmp uge float %628, 0.000000e+00
  %634 = select i1 %633, float %628, float 0.000000e+00
  %635 = fcmp uge float %630, 0.000000e+00
  %636 = select i1 %635, float %630, float 0.000000e+00
  %637 = fmul float %207, %622
  %638 = fadd float %637, 1.000000e+00
  %639 = fmul float %207, %623
  %640 = fadd float %639, 1.000000e+00
  %641 = fmul float %207, %624
  %642 = fadd float %641, 1.000000e+00
  %643 = fcmp uge float %137, 0.000000e+00
  %644 = select i1 %643, float 1.000000e+00, float 0.000000e+00
  %645 = fsub float -0.000000e+00, %644
  %646 = fptosi float %645 to i32
  %647 = bitcast i32 %646 to float
  %648 = bitcast float %647 to i32
  %649 = icmp ne i32 %648, 0
  %.129 = select i1 %649, float %137, float %638
  %650 = fcmp uge float %137, 0.000000e+00
  %651 = select i1 %650, float 1.000000e+00, float 0.000000e+00
  %652 = fsub float -0.000000e+00, %651
  %653 = fptosi float %652 to i32
  %654 = bitcast i32 %653 to float
  %655 = bitcast float %654 to i32
  %656 = icmp ne i32 %655, 0
  %temp8.1 = select i1 %656, float %139, float %640
  %657 = fcmp uge float %137, 0.000000e+00
  %658 = select i1 %657, float 1.000000e+00, float 0.000000e+00
  %659 = fsub float -0.000000e+00, %658
  %660 = fptosi float %659 to i32
  %661 = bitcast i32 %660 to float
  %662 = bitcast float %661 to i32
  %663 = icmp ne i32 %662, 0
  %.130 = select i1 %663, float %141, float %642
  %664 = fsub float -0.000000e+00, %75
  %665 = fmul float %191, %79
  %666 = fadd float %665, %664
  %667 = fmul float %474, %.129
  %668 = fadd float %667, %632
  %669 = fmul float %475, %temp8.1
  %670 = fadd float %669, %634
  %671 = fmul float %476, %.130
  %672 = fadd float %671, %636
  %673 = fcmp uge float %666, %77
  %674 = select i1 %673, float %77, float %666
  %675 = call float @llvm.AMDIL.clamp.(float %674, float 0.000000e+00, float 1.000000e+00)
  %676 = fsub float -0.000000e+00, %153
  %677 = fmul float %668, %676
  %678 = fadd float %677, %145
  %679 = fsub float -0.000000e+00, %153
  %680 = fmul float %670, %679
  %681 = fadd float %680, %147
  %682 = fsub float -0.000000e+00, %153
  %683 = fmul float %672, %682
  %684 = fadd float %683, %149
  %685 = fmul float %675, %675
  %686 = fmul float %678, %685
  %687 = fmul float %681, %685
  %688 = fmul float %684, %685
  %689 = fmul float %668, %153
  %690 = fadd float %689, %686
  %691 = fmul float %670, %153
  %692 = fadd float %691, %687
  %693 = fmul float %672, %153
  %694 = fadd float %693, %688
  %695 = fmul float %191, %151
  %696 = call i32 @llvm.SI.packf16(float %690, float %692)
  %697 = bitcast i32 %696 to float
  %698 = call i32 @llvm.SI.packf16(float %694, float %695)
  %699 = bitcast i32 %698 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %697, float %699, float %697, float %699)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR6 in %vreg3, %VGPR0 in %vreg4, %VGPR1 in %vreg5

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR6
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%160](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%158](tbaa=!"const")
	S_WAITCNT 127
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_ADD_F32_e32 %VGPR6, %VGPR6, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_SUB_F32_e32 0.000000e+00, %VGPR4, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 0; mem:LD8[%20](tbaa=!"const")
	S_WAITCNT 127
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 108; mem:LD4[%142]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR7, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_F32_e32 %VGPR7, %VGPR7, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_SUB_F32_e32 0.000000e+00, %VGPR5, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %SGPR7, %VGPR10<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 1, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR5, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 1, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %VGPR4, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e32 %VGPR8, %VGPR8, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 1.000000e+00, %VGPR10, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %SGPR7, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 0, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR5, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 0, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR13<kill>, %VGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR13<kill>, %VGPR10, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR12, %VGPR12, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR14<kill>, %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR5<kill>, %VGPR10<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR4, %VGPR4, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_RSQ_LEGACY_F32_e32 %VGPR5<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR11, %VGPR11, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR10, %VGPR10, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR12, %VGPR12, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_RSQ_LEGACY_F32_e32 %VGPR13<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR17, %VGPR11, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR14, %VGPR10, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR18, %VGPR4, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR14, %VGPR19, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR14, %VGPR19, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR17, %VGPR19, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR17, %VGPR19, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_INTERP_P1_F32 %VGPR0, 1, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR22<def,tied1> = V_INTERP_P2_F32 %VGPR22<kill,tied0>, %VGPR1, 1, 6, %M0<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 85; mem:LD4[%98]
	S_WAITCNT 127
	%VGPR5<def> = V_SUB_F32_e32 %SGPR8<kill>, %VGPR22, %EXEC<imp-use>
	%VGPR23<def> = V_INTERP_P1_F32 %VGPR0, 0, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR23<def,tied1> = V_INTERP_P2_F32 %VGPR23<kill,tied0>, %VGPR1, 0, 6, %M0<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 84; mem:LD4[%96]
	S_WAITCNT 127
	%VGPR10<def> = V_SUB_F32_e32 %SGPR8<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR10, %VGPR10, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR5, %VGPR5, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_INTERP_P1_F32 %VGPR0, 2, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR24<def,tied1> = V_INTERP_P2_F32 %VGPR24<kill,tied0>, %VGPR1, 2, 6, %M0<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 86; mem:LD4[%100]
	S_WAITCNT 127
	%VGPR12<def> = V_SUB_F32_e32 %SGPR8<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR12, %VGPR12, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_RSQ_LEGACY_F32_e32 %VGPR11<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR21, %VGPR10, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR20, %VGPR11, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR18, %VGPR19, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR18, %VGPR19, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR29, %VGPR12, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_LOG_F32_e32 %VGPR4<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%164](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%162](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5<def> = IMAGE_SAMPLE 3, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 1.490000e+02, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MAD_F32 %VGPR4, %VGPR15<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 47; mem:LD4[%72]
	S_WAITCNT 127
	%VGPR16<def> = V_MOV_B32_e32 %SGPR8, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %SGPR8<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR25<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR25<def> = V_CVT_I32_F32_e32 %VGPR25<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_NE_I32_e64 %VGPR25<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_CNDMASK_B32_e64 %VGPR15<kill>, %VGPR16<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_LEGACY_F32_e32 %VGPR32, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_EXP_F32_e32 %VGPR13<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR17, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR14, %VGPR11<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR18, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e64 %VGPR25, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 93; mem:LD4[%114]
	S_WAITCNT 127
	%VGPR11<def> = V_SUB_F32_e32 %SGPR8<kill>, %VGPR22, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 92; mem:LD4[%112]
	S_WAITCNT 127
	%VGPR12<def> = V_SUB_F32_e32 %SGPR8<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR12, %VGPR12, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 94; mem:LD4[%116]
	S_WAITCNT 127
	%VGPR13<def> = V_SUB_F32_e32 %SGPR8<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR13, %VGPR13, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_RSQ_LEGACY_F32_e32 %VGPR15<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR15, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR21, %VGPR12, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR15, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR20, %VGPR11, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR29, %VGPR13, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e64 %VGPR15<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_LOG_F32_e32 %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_LEGACY_F32_e32 %VGPR32, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_EXP_F32_e32 %VGPR15<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR17, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR14, %VGPR11<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR18, %VGPR13<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e64 %VGPR26, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 89; mem:LD4[%106]
	S_WAITCNT 127
	%VGPR27<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR11, %VGPR27, %EXEC<imp-use>
	%VGPR13<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def,tied1> = V_INTERP_P2_F32 %VGPR13<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 81; mem:LD4[%90]
	S_WAITCNT 127
	%VGPR28<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR10, %VGPR28, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 101; mem:LD4[%130]
	S_WAITCNT 127
	%VGPR15<def> = V_SUB_F32_e32 %SGPR8<kill>, %VGPR22, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 100; mem:LD4[%128]
	S_WAITCNT 127
	%VGPR16<def> = V_SUB_F32_e32 %SGPR8<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR16, %VGPR16, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR15, %VGPR15, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 102; mem:LD4[%132]
	S_WAITCNT 127
	%VGPR30<def> = V_SUB_F32_e32 %SGPR8<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR30, %VGPR30, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_RSQ_LEGACY_F32_e32 %VGPR31<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR31, %EXEC<imp-use>
	%VGPR34<def> = V_MUL_F32_e32 %VGPR21, %VGPR16, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR31, %EXEC<imp-use>
	%VGPR34<def> = V_MAD_F32 %VGPR20, %VGPR15, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR29, %VGPR30, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_ADD_F32_e64 %VGPR31<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_LOG_F32_e32 %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_LEGACY_F32_e32 %VGPR32, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_EXP_F32_e32 %VGPR31<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR17, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR14, %VGPR15<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_MAD_F32 %VGPR18, %VGPR30<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e64 %VGPR30, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR0, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<kill,tied0>, %VGPR1, 2, 1, %M0<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 97; mem:LD4[%122]
	S_WAITCNT 127
	%VGPR31<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR34<def> = V_MAD_F32 %VGPR15, %VGPR31, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 99; mem:LD4[%126]
	S_WAITCNT 127
	%VGPR22<def> = V_SUB_F32_e32 %SGPR8<kill>, %VGPR22<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 95; mem:LD4[%118]
	S_WAITCNT 127
	%VGPR23<def> = V_SUB_F32_e32 %SGPR8<kill>, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %VGPR23, %VGPR23, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR22, %VGPR22, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 103; mem:LD4[%134]
	S_WAITCNT 127
	%VGPR24<def> = V_SUB_F32_e32 %SGPR8<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR24, %VGPR24, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_RSQ_LEGACY_F32_e32 %VGPR33<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR23<kill>, %VGPR33, %EXEC<imp-use>
	%VGPR35<def> = V_MUL_F32_e32 %VGPR21<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR22<kill>, %VGPR33, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR20<kill>, %VGPR21, %VGPR35<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR33<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR29<kill>, %VGPR20, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_ADD_F32_e64 %VGPR22<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_LOG_F32_e32 %VGPR22<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_LEGACY_F32_e32 %VGPR32<kill>, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_EXP_F32_e32 %VGPR22<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR17, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR14, %VGPR21<kill>, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR18, %VGPR20<kill>, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e64 %VGPR29, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR22<kill>, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_INTERP_P1_F32 %VGPR0, 3, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR24<def,tied1> = V_INTERP_P2_F32 %VGPR24<kill,tied0>, %VGPR1, 3, 6, %M0<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 87; mem:LD4[%102]
	S_WAITCNT 127
	%VGPR33<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR23, %VGPR33, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 1.000000e+00, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e64 %VGPR19<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR19<kill>, %VGPR19, -5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR19, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e64 %VGPR20<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR20<def> = V_CVT_I32_F32_e32 %VGPR20<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_NE_I32_e64 %VGPR20<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 78; mem:LD4[%84]
	S_WAITCNT 127
	%VGPR20<def> = V_MOV_B32_e32 %SGPR10<kill>, %EXEC<imp-use>
	%SGPR10<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 76; mem:LD4[%80]
	S_WAITCNT 127
	%VGPR21<def> = V_MOV_B32_e32 %SGPR10<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_CNDMASK_B32_e64 %VGPR21<kill>, %VGPR20<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 77; mem:LD4[%82]
	S_WAITCNT 127
	%VGPR34<def> = V_MAD_F32 %VGPR20<kill>, %VGPR19<kill>, %SGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%156](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%154](tbaa=!"const")
	S_WAITCNT 127
	%VGPR19_VGPR20_VGPR21_VGPR22<def> = IMAGE_SAMPLE 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR35<def> = V_SUB_F32_e32 %VGPR22, %VGPR9, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR7<kill>, %VGPR35<kill>, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR34<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 79; mem:LD4[%86]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR17, %VGPR17, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR17<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR7<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR7<def> = V_CVT_I32_F32_e32 %VGPR7<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_NE_I32_e64 %VGPR7<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR8, %SGPR8_SGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, 0.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[%42]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 17; mem:LD4[%36]
	S_WAITCNT 127
	%VGPR17<def> = V_MAD_F32 %VGPR7, %SGPR7<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_MUL_F32_e32 %VGPR14, %VGPR14, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR14<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e64 %VGPR9<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR9<def> = V_CVT_I32_F32_e32 %VGPR9<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_NE_I32_e64 %VGPR9<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR34, %SGPR8_SGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 25; mem:LD4[%48]
	S_WAITCNT 127
	%VGPR17<def> = V_MAD_F32 %VGPR9, %SGPR7<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_CNDMASK_B32_e64 %VGPR34<kill>, 0.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 29; mem:LD4[%54]
	S_WAITCNT 127
	%VGPR34<def> = V_MAD_F32 %VGPR14, %SGPR7<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR35<def> = V_MUL_F32_e32 %VGPR18, %VGPR18, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR18<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e64 %VGPR17<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR17<def> = V_CVT_I32_F32_e32 %VGPR17<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_NE_I32_e64 %VGPR17<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR35, %SGPR8_SGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 33; mem:LD4[%60]
	S_WAITCNT 127
	%VGPR34<def> = V_MAD_F32 %VGPR17, %SGPR7<kill>, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_CNDMASK_B32_e64 %VGPR35<kill>, 0.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 37; mem:LD4[%66]
	S_WAITCNT 127
	%VGPR34<def> = V_MAD_F32 %VGPR18, %SGPR7<kill>, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR25<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR25<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR25, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, %VGPR25, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_ADD_F32_e64 %VGPR26<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR26, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR27<kill>, %VGPR26, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR30<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_ADD_F32_e64 %VGPR27<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR27, %EXEC<imp-use>
	%VGPR30<def> = V_MAD_F32 %VGPR31<kill>, %VGPR27, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR29<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_ADD_F32_e64 %VGPR28<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR28, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR33<kill>, %VGPR28, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 5; mem:LD4[%30]
	S_WAITCNT 127
	%VGPR30<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR20, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR30, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 1; mem:LD4[%24]
	S_WAITCNT 127
	%VGPR29<def> = V_MUL_F32_e32 %SGPR7<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR34<def> = V_SUB_F32_e32 %VGPR29<kill>, %VGPR33, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 12; mem:LD16[%168](tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 24; mem:LD32[%166](tbaa=!"const")
	S_WAITCNT 127
	%VGPR29_VGPR30_VGPR31<def> = IMAGE_SAMPLE 7, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_SUB_F32_e32 %VGPR30, %VGPR22, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 43; mem:LD4[%70]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %SGPR2, %VGPR2<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %VGPR34<kill>, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR2, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR2<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR20, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR5, %VGPR3<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 105; mem:LD4[%138]
	S_WAITCNT 127
	%VGPR33<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 104; mem:LD4[%136]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %SGPR7, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_ADD_F32_e64 %VGPR34<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR34<def> = V_CVT_I32_F32_e32 %VGPR34<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %VGPR34<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR33<kill>, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR32<kill>, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 120; mem:LD4[%152]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR3, %VGPR3, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 117; mem:LD4[%146]
	S_WAITCNT 127
	%VGPR32<def> = V_SUB_F32_e32 %SGPR8<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 2, 7, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 2, 7, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 51; mem:LD4[%78]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR2, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 48; mem:LD4[%74]
	S_WAITCNT 127
	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR6<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 50; mem:LD4[%76]
	S_WAITCNT 127
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR0, %SGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR6<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR3<kill>, %SGPR3, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 88; mem:LD4[%104]
	S_WAITCNT 127
	%VGPR32<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR11, %VGPR32, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 80; mem:LD4[%88]
	S_WAITCNT 127
	%VGPR33<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR10, %VGPR33, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 96; mem:LD4[%120]
	S_WAITCNT 127
	%VGPR34<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR15, %VGPR34, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 83; mem:LD4[%94]
	S_WAITCNT 127
	%VGPR35<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR23, %VGPR35, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[%40]
	S_WAITCNT 127
	%VGPR36<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR8, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 16; mem:LD4[%34]
	S_WAITCNT 127
	%VGPR36<def> = V_MAD_F32 %VGPR7, %SGPR6<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 24; mem:LD4[%46]
	S_WAITCNT 127
	%VGPR36<def> = V_MAD_F32 %VGPR9, %SGPR6<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 28; mem:LD4[%52]
	S_WAITCNT 127
	%VGPR36<def> = V_MAD_F32 %VGPR14, %SGPR6<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 32; mem:LD4[%58]
	S_WAITCNT 127
	%VGPR36<def> = V_MAD_F32 %VGPR17, %SGPR6<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 36; mem:LD4[%64]
	S_WAITCNT 127
	%VGPR36<def> = V_MAD_F32 %VGPR18, %SGPR6<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR33<kill>, %VGPR25, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR32<kill>, %VGPR26, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR34<kill>, %VGPR27, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR35<kill>, %VGPR28, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 4; mem:LD4[%28]
	S_WAITCNT 127
	%VGPR33<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR19, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR33, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 0; mem:LD4[%22]
	S_WAITCNT 127
	%VGPR33<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR33<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_SUB_F32_e32 %VGPR33<kill>, %VGPR32, %EXEC<imp-use>
	%VGPR34<def> = V_SUB_F32_e32 %VGPR29, %VGPR22, %EXEC<imp-use>
	%VGPR34<def> = V_MAD_F32 %SGPR2, %VGPR34<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR34<kill>, %VGPR33<kill>, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR32, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR32<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR19, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR5, %VGPR33<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_MOV_B32_e32 %SGPR7<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_CNDMASK_B32_e64 %VGPR33<kill>, %VGPR34<kill>, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %VGPR33<kill>, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %SGPR3, %VGPR3, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 116; mem:LD4[%144]
	S_WAITCNT 127
	%VGPR32<def> = V_SUB_F32_e32 %SGPR6<kill>, %VGPR32<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %SGPR3, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 90; mem:LD4[%108]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR12, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 82; mem:LD4[%92]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR10<kill>, %VGPR11, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 98; mem:LD4[%124]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR15<kill>, %VGPR10, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 91; mem:LD4[%110]
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR23<kill>, %VGPR13, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[%44]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 18; mem:LD4[%38]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR7<kill>, %SGPR6<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 26; mem:LD4[%50]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR9<kill>, %SGPR6<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 30; mem:LD4[%56]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR14<kill>, %SGPR6<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 34; mem:LD4[%62]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR17<kill>, %SGPR6<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 38; mem:LD4[%68]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR18<kill>, %SGPR6<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR11<kill>, %VGPR25<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR12<kill>, %VGPR26<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR10<kill>, %VGPR27<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR13<kill>, %VGPR28<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[%32]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 2; mem:LD4[%26]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_SUB_F32_e32 %VGPR7<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR8<def> = V_SUB_F32_e32 %VGPR31, %VGPR22, %EXEC<imp-use>, %VGPR29_VGPR30_VGPR31<imp-use,kill>
	%VGPR8<def> = V_MAD_F32 %SGPR2<kill>, %VGPR8<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR8<kill>, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR6, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR6<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR21, %EXEC<imp-use>, %VGPR19_VGPR20_VGPR21_VGPR22<imp-use,kill>
	%VGPR4<def> = V_MAD_F32 %VGPR5, %VGPR7<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 106; mem:LD4[%140]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_CNDMASK_B32_e64 %VGPR4<kill>, %VGPR5<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %VGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR3, %VGPR3, %EXEC<imp-use>
	%SGPR2<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 118; mem:LD4[%148]
	S_WAITCNT 127
	%VGPR4<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3<kill>, %SGPR3<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1<kill>, 119; mem:LD4[%150]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use,kill>
	S_ENDPGM

# End machine code for function main.

SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840304
c0c60508
bf8c007f
f0800f00
00430602
bf8c0770
06080d06
060808f3
080a0880
c0400100
bf8c007f
c003816c
bf8c007f
d2820004
04120a07
060a0f07
060a0af3
08140a80
d2820005
04161407
c8281100
c8291101
10141505
c82c0d00
c82d0d01
d282000b
042a090b
06141108
061414f3
081814f2
d282000a
042a1807
c8301500
c8311501
d282000b
042e150c
c8301000
c8311001
10181905
c8340c00
c8350c01
d282000c
0432090d
c8341400
c8351401
d282000c
0432150d
101a190c
d282000d
0436170b
c8381200
c8391201
100a1d05
c8380e00
c8390e01
d2820004
0416090e
c8141600
c8151601
d2820004
04121505
d2820005
04360904
7e0a5b05
101c0b0b
10220b0c
c8280900
c8290901
c82c0800
c82d0801
1018170b
d282000d
0432150a
c8300a00
c8310a01
d282000d
0436190c
7e1a5b0d
10161b0b
101e1711
10141b0a
d282000f
043e150e
10240b04
10081b0c
d2820013
043e0912
100a270e
d2820005
0416270e
08281505
100a2711
d2820005
04162711
082a1705
c8581900
c8591901
c0040155
bf8c007f
080a2c08
c85c1800
c85d1801
c0040154
bf8c007f
08142e08
1016150a
d282000b
042e0b05
c8601a00
c8611a01
c0040156
bf8c007f
08183008
d282000b
042e190c
7e1a5b0b
10141b0a
101e1515
10161b05
d2820005
043e1714
101e2712
d282000f
043e2712
083a090f
10181b0c
d2820004
0416191d
d2060804
02010104
7e1a4f04
c0840308
c0c60510
bf8c007f
f0800300
00430402
7e1e02ff
43150000
bf8c0770
d282000f
03ca1f04
c004012f
bf8c007f
7e200208
d00c0008
02010008
d2000019
0021e480
d2060019
22010119
7e321119
d10a0008
02010119
d2000020
0022210f
0e1a1b20
7e1a4b0d
10141511
d282000a
042a170e
d2820019
042a1912
d206080a
02010119
1014150d
c004015d
bf8c007f
08162c08
c004015c
bf8c007f
08182e08
101a190c
d282000f
0436170b
c004015e
bf8c007f
081a3008
d282000f
043e1b0d
7e1e5b0f
10181f0c
10201915
10161f0b
d2820010
04421714
101a1f0d
d282000f
04421b1d
d206080f
0201010f
7e1e4f0f
0e1e1f20
7e1e4b0f
10181911
d282000b
0432170e
d282001a
042e1b12
d206080b
0201011a
1016170f
c8300500
c8310501
c0040159
bf8c007f
10361808
101e370b
c8340400
c8350401
c0040151
bf8c007f
10381a08
d2820021
043e390a
c0040165
bf8c007f
081e2c08
c0040164
bf8c007f
08202e08
103c2110
d282001f
047a1f0f
c0040166
bf8c007f
083c3008
d282001f
047e3d1e
7e3e5b1f
10203f10
10442115
101e3f0f
d2820022
048a1f14
103c3f1e
d282001f
048a3d1d
d206081f
0201011f
7e3e4f1f
0e3e3f20
7e3e4b1f
10202111
d282000f
04421f0e
d282001e
043e3d12
d206080f
0201011e
101e1f1f
c8400600
c8410601
c0040161
bf8c007f
103e2008
d2820022
04863f0f
c0040163
bf8c007f
082c2c08
c004015f
bf8c007f
082e2e08
10422f17
d2820021
04862d16
c0040167
bf8c007f
08303008
d2820021
04863118
7e425b21
102e4317
10462f15
102a4316
d2820016
048e2b14
10284318
d2820016
045a291d
d2060816
02010116
7e2c4f16
0e2c2d20
7e2c4b16
102e2f11
d2820015
045e2b0e
d282001d
04562912
d2060814
0201011d
102e2916
c8601b00
c8611b01
c0040157
bf8c007f
10423008
d2820020
048a4317
082626f2
d2060813
02010113
d2820013
03c62713
d00c0008
02010113
d2000014
0021e480
d2060014
22010114
7e281114
d10a0008
02010114
c005014e
bf8c007f
7e28020a
c005014c
bf8c007f
7e2a020a
d2000014
00222915
c004014d
bf8c007f
d2820022
00222714
c0840300
c0c60500
bf8c007f
f0800f00
00431302
bf8c0770
08461316
d2820006
04264607
100c0d22
c003814f
bf8c007f
100c0c07
10400d20
10102311
d00c0008
02010111
d2000007
0021e480
d2060007
22010107
7e0e1107
d10a0008
02010107
d2000007
00221080
d2000008
00210108
c0038115
bf8c007f
10121007
c0038111
bf8c007f
d2820011
04240f07
10441d0e
d00c0008
0201010e
d2000009
0021e480
d2060009
22010109
7e121109
d10a0008
02010109
d2000009
00224480
c0038119
bf8c007f
d2820011
04440f09
d200000e
00210122
c003811d
bf8c007f
d2820022
04440f0e
10462512
d00c0008
02010112
d2000011
0021e480
d2060011
22010111
7e221111
d10a0008
02010111
d2000011
00224680
c0038121
bf8c007f
d2820022
04880f11
d2000012
00210123
c0038125
bf8c007f
d2820022
04880f12
d2820019
03c1e119
d2060819
02010119
10323319
d282001c
048a331c
d282001a
03c1e11a
d206081a
0201011a
1034351a
d282001c
0472351b
d282001b
03c1e11e
d206081b
0201011b
1036371b
d282001e
0472371f
d282001c
03c1e11d
d206081c
0201011c
1038391c
d282001d
047a3921
c0038105
bf8c007f
103c2807
10423d1d
c0038101
bf8c007f
103a3c07
0844431d
c084030c
c0c60518
bf8c007f
f0800700
00431d02
bf8c0770
08042d1e
c001012b
bf8c007f
d2820002
045a0402
d2820002
04864502
d00c0004
02010102
d2000002
00120480
060628f3
d2820003
03ca0705
c0018169
bf8c007f
7e420203
c0038168
bf8c007f
d00c0004
02010007
d2000022
0011e480
d2060022
22010122
7e441122
d10a0004
02010122
d2000003
00124303
d2820003
040a0720
c0018178
bf8c007f
10040603
c0040175
bf8c007f
08400408
c8081e00
c8091e01
c0030133
bf8c007f
10000406
c0030130
bf8c007f
0a000006
c0030132
bf8c007f
d00c0008
02000d00
7e020206
d2000000
00220300
d2060800
02010100
10000100
10020120
d2820001
04040703
c0030158
bf8c007f
10401806
1006410b
c0030150
bf8c007f
10421a06
d2820003
040e430a
c0030160
bf8c007f
10442006
d2820003
040e450f
c0030153
bf8c007f
10463006
d2820003
040e4717
10060d03
c0030114
bf8c007f
10481006
c0030110
bf8c007f
d2820024
04900d07
c0030118
bf8c007f
d2820024
04900d09
c003011c
bf8c007f
d2820024
04900d0e
c0030120
bf8c007f
d2820024
04900d11
c0030124
bf8c007f
d2820024
04900d12
d2820021
04923321
d2820020
04863520
d2820020
04823722
d2820020
04823923
c0030104
bf8c007f
10422606
10404320
c0030100
bf8c007f
10424206
08424121
08442d1d
d2820022
045a4402
d2820020
04824322
d00c0008
02010120
d2000020
00224080
064226f3
d2820021
03ca4305
7e440207
d2000021
00124521
d2820003
04824303
10400603
c0030174
bf8c007f
08404006
10400120
d2820003
04800703
5e020303
c003015a
bf8c007f
10181806
1006190b
c0030152
bf8c007f
10161a06
d2820003
040e170a
c0030162
bf8c007f
10142006
d2820003
040e150f
c003015b
bf8c007f
101a3006
d2820003
040e1b17
10060d03
c0030116
bf8c007f
100c1006
c0030112
bf8c007f
d2820006
04180d07
c003011a
bf8c007f
d2820006
04180d09
c003011e
bf8c007f
d2820006
04180d0e
c0030122
bf8c007f
d2820006
04180d11
c0030126
bf8c007f
d2820006
04180d12
d2820006
041a330b
d2820006
041a350c
d2820006
041a370a
d2820006
041a390d
c0030106
bf8c007f
100e2a06
100c0f06
c0030102
bf8c007f
100e0e06
080e0d07
08102d1f
d2820008
045a1002
d2820006
041a0f08
d00c0006
02010106
d2000006
001a0c80
060e2af3
d2820004
03ca0f05
c001016a
bf8c007f
7e0a0202
d2000004
00120b04
d2820003
041a0903
10080603
c0010176
bf8c007f
08080802
10000104
d2820000
04000703
c0000177
bf8c007f
10040400
5e000500
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL OUT[5], GENERIC[22]
DCL OUT[6], GENERIC[23]
DCL OUT[7], GENERIC[24]
DCL OUT[8], GENERIC[25]
DCL OUT[9], GENERIC[26]
DCL CONST[0..61]
DCL TEMP[0..13], LOCAL
IMM[0] FLT32 { -128.0000,     1.0000,   -64.0000,    -0.0159}
IMM[1] FLT32 {    0.0159,     0.0001,     0.0000,     0.0000}
  0: ADD TEMP[0], IN[1], IMM[0].xxxx
  1: SLT TEMP[1], TEMP[0], CONST[0].xxxx
  2: F2I TEMP[1], -TEMP[1]
  3: AND TEMP[1], TEMP[1], IMM[0].yyyy
  4: ABS TEMP[0], TEMP[0]
  5: ADD TEMP[0], TEMP[0], -TEMP[1]
  6: ADD TEMP[0], TEMP[0], IMM[0].zzzz
  7: SLT TEMP[2], TEMP[0], CONST[0].xxxx
  8: F2I TEMP[2], -TEMP[2]
  9: AND TEMP[2], TEMP[2], IMM[0].yyyy
 10: ABS TEMP[0], TEMP[0]
 11: ADD TEMP[0], TEMP[0], -TEMP[2]
 12: MAD TEMP[1].xyz, CONST[0].zzzz, -TEMP[1].xzww, CONST[0].yyyy
 13: MAD TEMP[3].xy, TEMP[0].xzzz, IMM[0].wwww, IMM[0].yyyy
 14: MAD TEMP[4].x, TEMP[0].yyyy, IMM[0].wwww, TEMP[3].xxxx
 15: MOV TEMP[3].z, TEMP[4].xxxx
 16: MUL TEMP[4], TEMP[0], IMM[1].xxxx
 17: MAD TEMP[5].x, TEMP[0].wwww, IMM[0].wwww, TEMP[3].yyyy
 18: MOV TEMP[0].z, TEMP[5].xxxx
 19: MOV TEMP[3].xy, TEMP[4].xyxx
 20: MAD TEMP[5], CONST[0].zzzz, -TEMP[2], CONST[0].yyyy
 21: DP3 TEMP[6].x, TEMP[3].xyzz, TEMP[3].xyzz
 22: RSQ TEMP[6].x, TEMP[6].xxxx
 23: MUL TEMP[6].xyz, TEMP[3].xyzz, TEMP[6].xxxx
 24: MUL TEMP[3].xy, TEMP[5].xyyy, TEMP[6].xyyy
 25: MUL TEMP[6].x, TEMP[1].xxxx, TEMP[6].zzzz
 26: MOV TEMP[3].z, TEMP[6].xxxx
 27: MAD TEMP[3].xyz, IN[4].xyzz, CONST[3].xxxx, TEMP[3].xyzz
 28: MOV TEMP[0].xy, TEMP[4].zwzz
 29: DP3 TEMP[4].x, TEMP[3].xyzz, CONST[56].xyzz
 30: MOV TEMP[2].z, TEMP[4].xxxx
 31: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz
 32: RSQ TEMP[4].x, TEMP[4].xxxx
 33: MUL TEMP[4].xyz, TEMP[0].xyzz, TEMP[4].xxxx
 34: MUL TEMP[5].xy, TEMP[5].zwww, TEMP[4].xyyy
 35: MUL TEMP[4].x, TEMP[1].yyyy, TEMP[4].zzzz
 36: MOV TEMP[5].z, TEMP[4].xxxx
 37: DP3 TEMP[2].x, TEMP[3].xyzz, CONST[54].xyzz
 38: DP3 TEMP[4].x, TEMP[3].xyzz, CONST[55].xyzz
 39: MOV TEMP[2].y, TEMP[4].xxxx
 40: MAD TEMP[0].xyz, IN[4].xyzz, CONST[3].xxxx, TEMP[5].xyzz
 41: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[2].xyzz
 42: DP3 TEMP[4].x, TEMP[0].xyzz, CONST[56].xyzz
 43: MOV TEMP[5].z, TEMP[4].xxxx
 44: RSQ TEMP[4].x, TEMP[5].xxxx
 45: DP3 TEMP[5].x, TEMP[0].xyzz, CONST[54].xyzz
 46: DP3 TEMP[6].x, TEMP[0].xyzz, CONST[55].xyzz
 47: MOV TEMP[5].y, TEMP[6].xxxx
 48: MUL TEMP[4].xyz, TEMP[2].xyzz, TEMP[4].xxxx
 49: DP3 TEMP[0].x, TEMP[5].xyzz, TEMP[5].xyzz
 50: RSQ TEMP[6].x, TEMP[0].xxxx
 51: MUL TEMP[0].xyz, TEMP[2].zxyy, TEMP[5].yzxx
 52: MUL TEMP[6].xyz, TEMP[5].xyzz, TEMP[6].xxxx
 53: MAD TEMP[5].xyz, TEMP[2].yzxx, TEMP[5].zxyy, -TEMP[0].xyzz
 54: MOV TEMP[5].w, IN[0].wwww
 55: MUL TEMP[2].xyz, TEMP[1].zzzz, TEMP[5].xyzz
 56: MAD TEMP[5].xyz, IN[3].xyzz, CONST[3].xxxx, IN[0].xyzz
 57: DP3 TEMP[0].x, TEMP[2].xyzz, TEMP[2].xyzz
 58: DP4 TEMP[1].x, TEMP[5], CONST[56]
 59: MOV TEMP[0].z, TEMP[1].xxxx
 60: RSQ TEMP[1].x, TEMP[0].xxxx
 61: DP4 TEMP[0].x, TEMP[5], CONST[54]
 62: DP4 TEMP[7].x, TEMP[5], CONST[55]
 63: MOV TEMP[0].y, TEMP[7].xxxx
 64: MUL TEMP[1].xyz, TEMP[2].xyzz, TEMP[1].xxxx
 65: ADD TEMP[7].xyz, -TEMP[0].xyzz, CONST[2].xyzz
 66: UIF CONST[58].xxxx :0
 67:   ADD TEMP[2].xyz, -TEMP[0].xyzz, CONST[29].xyzz
 68:   DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
 69:   RSQ TEMP[8].x, TEMP[3].xxxx
 70:   MOV TEMP[5].y, TEMP[8].xxxx
 71:   MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[8].xxxx
 72:   MOV TEMP[3].y, CONST[0].yyyy
 73:   DP3 TEMP[8].x, CONST[28].xyzz, -TEMP[2].xyzz
 74:   ADD TEMP[8].x, TEMP[8].xxxx, -CONST[30].zzzz
 75:   MOV TEMP[5].xz, CONST[0].yyyy
 76:   MUL TEMP[8].x, TEMP[8].xxxx, CONST[30].wwww
 77:   MUL TEMP[5].xyz, TEMP[3].yxxx, TEMP[5].xyzz
 78:   MAX TEMP[8].x, TEMP[8].xxxx, IMM[1].yyyy
 79:   DP3 TEMP[9].x, CONST[31].xyzz, TEMP[5].xyzz
 80:   MOV TEMP[5].x, TEMP[9].xxxx
 81:   POW TEMP[8].x, TEMP[8].xxxx, CONST[30].xxxx
 82:   RCP TEMP[9].x, TEMP[9].xxxx
 83:   MIN TEMP[8].x, TEMP[8].xxxx, CONST[0].yyyy
 84:   MAD TEMP[8].x, TEMP[9].xxxx, TEMP[8].xxxx, -TEMP[9].xxxx
 85:   MAD TEMP[8].x, CONST[28].wwww, TEMP[8].xxxx, TEMP[9].xxxx
 86:   ADD TEMP[9].x, -TEMP[8].xxxx, CONST[0].yyyy
 87:   MAD TEMP[8].x, CONST[27].wwww, TEMP[9].xxxx, TEMP[8].xxxx
 88: ELSE :0
 89:   MOV TEMP[8].x, CONST[0].xxxx
 90: ENDIF
 91: UIF CONST[59].xxxx :0
 92:   ADD TEMP[2].xyz, -TEMP[0].xyzz, CONST[34].xyzz
 93:   DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
 94:   RSQ TEMP[9].x, TEMP[3].xxxx
 95:   MOV TEMP[5].y, TEMP[9].xxxx
 96:   MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[9].xxxx
 97:   MOV TEMP[3].y, CONST[0].yyyy
 98:   DP3 TEMP[9].x, CONST[33].xyzz, -TEMP[2].xyzz
 99:   ADD TEMP[9].x, TEMP[9].xxxx, -CONST[35].zzzz
100:   MOV TEMP[5].xz, CONST[0].yyyy
101:   MUL TEMP[9].x, TEMP[9].xxxx, CONST[35].wwww
102:   MUL TEMP[5].xyz, TEMP[3].yxxx, TEMP[5].xyzz
103:   MAX TEMP[9].x, TEMP[9].xxxx, IMM[1].yyyy
104:   DP3 TEMP[10].x, CONST[36].xyzz, TEMP[5].xyzz
105:   MOV TEMP[5].x, TEMP[10].xxxx
106:   POW TEMP[9].x, TEMP[9].xxxx, CONST[35].xxxx
107:   RCP TEMP[10].x, TEMP[10].xxxx
108:   MIN TEMP[9].x, TEMP[9].xxxx, CONST[0].yyyy
109:   MAD TEMP[9].x, TEMP[10].xxxx, TEMP[9].xxxx, -TEMP[10].xxxx
110:   MAD TEMP[9].x, CONST[33].wwww, TEMP[9].xxxx, TEMP[10].xxxx
111:   ADD TEMP[10].x, -TEMP[9].xxxx, CONST[0].yyyy
112:   MAD TEMP[9].x, CONST[32].wwww, TEMP[10].xxxx, TEMP[9].xxxx
113:   MOV TEMP[8].y, TEMP[9].xxxx
114: ELSE :0
115:   MOV TEMP[8].y, CONST[0].xxxx
116: ENDIF
117: UIF CONST[60].xxxx :0
118:   ADD TEMP[2].xyz, -TEMP[0].xyzz, CONST[39].xyzz
119:   DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
120:   RSQ TEMP[9].x, TEMP[3].xxxx
121:   MOV TEMP[5].y, TEMP[9].xxxx
122:   MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[9].xxxx
123:   MOV TEMP[3].y, CONST[0].yyyy
124:   DP3 TEMP[9].x, CONST[38].xyzz, -TEMP[2].xyzz
125:   ADD TEMP[9].x, TEMP[9].xxxx, -CONST[40].zzzz
126:   MOV TEMP[5].xz, CONST[0].yyyy
127:   MUL TEMP[9].x, TEMP[9].xxxx, CONST[40].wwww
128:   MUL TEMP[5].xyz, TEMP[3].yxxx, TEMP[5].xyzz
129:   MAX TEMP[9].x, TEMP[9].xxxx, IMM[1].yyyy
130:   DP3 TEMP[10].x, CONST[41].xyzz, TEMP[5].xyzz
131:   MOV TEMP[5].x, TEMP[10].xxxx
132:   POW TEMP[9].x, TEMP[9].xxxx, CONST[40].xxxx
133:   RCP TEMP[10].x, TEMP[10].xxxx
134:   MIN TEMP[9].x, TEMP[9].xxxx, CONST[0].yyyy
135:   MAD TEMP[9].x, TEMP[10].xxxx, TEMP[9].xxxx, -TEMP[10].xxxx
136:   MAD TEMP[9].x, CONST[38].wwww, TEMP[9].xxxx, TEMP[10].xxxx
137:   ADD TEMP[10].x, -TEMP[9].xxxx, CONST[0].yyyy
138:   MAD TEMP[9].x, CONST[37].wwww, TEMP[10].xxxx, TEMP[9].xxxx
139:   MOV TEMP[8].z, TEMP[9].xxxx
140: ELSE :0
141:   MOV TEMP[8].z, CONST[0].xxxx
142: ENDIF
143: UIF CONST[61].xxxx :0
144:   ADD TEMP[2].xyz, -TEMP[0].xyzz, CONST[44].xyzz
145:   DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
146:   RSQ TEMP[9].x, TEMP[3].xxxx
147:   MOV TEMP[5].y, TEMP[9].xxxx
148:   MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[9].xxxx
149:   MOV TEMP[3].y, CONST[0].yyyy
150:   DP3 TEMP[9].x, CONST[43].xyzz, -TEMP[2].xyzz
151:   ADD TEMP[9].x, TEMP[9].xxxx, -CONST[45].zzzz
152:   MOV TEMP[5].xz, CONST[0].yyyy
153:   MUL TEMP[9].x, TEMP[9].xxxx, CONST[45].wwww
154:   MUL TEMP[5].xyz, TEMP[3].yxxx, TEMP[5].xyzz
155:   MAX TEMP[3].x, TEMP[9].xxxx, IMM[1].yyyy
156:   DP3 TEMP[9].x, CONST[46].xyzz, TEMP[5].xyzz
157:   POW TEMP[3].x, TEMP[3].xxxx, CONST[45].xxxx
158:   RCP TEMP[9].x, TEMP[9].xxxx
159:   MIN TEMP[3].x, TEMP[3].xxxx, CONST[0].yyyy
160:   MAD TEMP[3].x, TEMP[9].xxxx, TEMP[3].xxxx, -TEMP[9].xxxx
161:   MAD TEMP[3].x, CONST[43].wwww, TEMP[3].xxxx, TEMP[9].xxxx
162:   ADD TEMP[9].x, -TEMP[3].xxxx, CONST[0].yyyy
163:   MAD TEMP[5].x, CONST[42].wwww, TEMP[9].xxxx, TEMP[3].xxxx
164: ELSE :0
165:   MOV TEMP[5].x, CONST[0].xxxx
166: ENDIF
167: MOV TEMP[5].yzw, TEMP[0].yxyz
168: MOV TEMP[0].w, CONST[0].yyyy
169: DP4 TEMP[3].x, TEMP[0], CONST[13]
170: MOV TEMP[2].z, TEMP[3].xxxx
171: MUL TEMP[3].x, IN[3].wwww, CONST[3].yyyy
172: MOV TEMP[2].w, TEMP[3].xxxx
173: MOV TEMP[3], TEMP[5].yzwx
174: MOV TEMP[2].zw, TEMP[2].wwzw
175: DP4 TEMP[5].x, TEMP[0], CONST[8]
176: DP4 TEMP[9].x, TEMP[0], CONST[9]
177: MOV TEMP[5].y, TEMP[9].xxxx
178: MOV TEMP[2].xy, TEMP[5].xyxx
179: DP4 TEMP[10].x, TEMP[0], CONST[10]
180: MOV TEMP[5].z, TEMP[10].xxxx
181: DP4 TEMP[0].x, TEMP[0], CONST[11]
182: MOV TEMP[5].w, TEMP[0].xxxx
183: MOV TEMP[11].xw, TEMP[5].xxxw
184: DP4 TEMP[12].x, IN[2], CONST[48]
185: DP4 TEMP[13].x, IN[2], CONST[49]
186: MOV TEMP[12].y, TEMP[13].xxxx
187: DP4 TEMP[13].x, IN[2], CONST[52]
188: MOV TEMP[12].z, TEMP[13].xxxx
189: DP4 TEMP[13].x, IN[2], CONST[53]
190: MOV TEMP[12].w, TEMP[13].xxxx
191: MAD TEMP[10].x, TEMP[10].xxxx, CONST[0].zzzz, -TEMP[0].xxxx
192: MOV TEMP[11].z, TEMP[10].xxxx
193: MOV TEMP[11].y, -TEMP[9].xxxx
194: MAD TEMP[11].xy, CONST[57].xyyy, TEMP[0].xxxx, TEMP[11].xyyy
195: MOV OUT[2], TEMP[12]
196: MOV OUT[3], TEMP[8]
197: MOV OUT[4], TEMP[7]
198: MOV OUT[5], TEMP[6]
199: MOV OUT[0], TEMP[11]
200: MOV OUT[6], TEMP[1]
201: MOV OUT[1], TEMP[5]
202: MOV OUT[7], TEMP[4]
203: MOV OUT[8], TEMP[3]
204: MOV OUT[9], TEMP[2]
205: END
; ModuleID = 'tgsi'

define void @main(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
  %10 = load float addrspace(2)* addrspace(2)* %9, !tbaa !0
  %11 = getelementptr float addrspace(2)* %10, i32 0
  %12 = load float addrspace(2)* %11, !tbaa !0
  %13 = getelementptr float addrspace(2)* %10, i32 1
  %14 = load float addrspace(2)* %13, !tbaa !0
  %15 = getelementptr float addrspace(2)* %10, i32 2
  %16 = load float addrspace(2)* %15, !tbaa !0
  %17 = getelementptr float addrspace(2)* %10, i32 8
  %18 = load float addrspace(2)* %17, !tbaa !0
  %19 = getelementptr float addrspace(2)* %10, i32 9
  %20 = load float addrspace(2)* %19, !tbaa !0
  %21 = getelementptr float addrspace(2)* %10, i32 10
  %22 = load float addrspace(2)* %21, !tbaa !0
  %23 = getelementptr float addrspace(2)* %10, i32 12
  %24 = load float addrspace(2)* %23, !tbaa !0
  %25 = getelementptr float addrspace(2)* %10, i32 13
  %26 = load float addrspace(2)* %25, !tbaa !0
  %27 = getelementptr float addrspace(2)* %10, i32 32
  %28 = load float addrspace(2)* %27, !tbaa !0
  %29 = getelementptr float addrspace(2)* %10, i32 33
  %30 = load float addrspace(2)* %29, !tbaa !0
  %31 = getelementptr float addrspace(2)* %10, i32 34
  %32 = load float addrspace(2)* %31, !tbaa !0
  %33 = getelementptr float addrspace(2)* %10, i32 35
  %34 = load float addrspace(2)* %33, !tbaa !0
  %35 = getelementptr float addrspace(2)* %10, i32 36
  %36 = load float addrspace(2)* %35, !tbaa !0
  %37 = getelementptr float addrspace(2)* %10, i32 37
  %38 = load float addrspace(2)* %37, !tbaa !0
  %39 = getelementptr float addrspace(2)* %10, i32 38
  %40 = load float addrspace(2)* %39, !tbaa !0
  %41 = getelementptr float addrspace(2)* %10, i32 39
  %42 = load float addrspace(2)* %41, !tbaa !0
  %43 = getelementptr float addrspace(2)* %10, i32 40
  %44 = load float addrspace(2)* %43, !tbaa !0
  %45 = getelementptr float addrspace(2)* %10, i32 41
  %46 = load float addrspace(2)* %45, !tbaa !0
  %47 = getelementptr float addrspace(2)* %10, i32 42
  %48 = load float addrspace(2)* %47, !tbaa !0
  %49 = getelementptr float addrspace(2)* %10, i32 43
  %50 = load float addrspace(2)* %49, !tbaa !0
  %51 = getelementptr float addrspace(2)* %10, i32 44
  %52 = load float addrspace(2)* %51, !tbaa !0
  %53 = getelementptr float addrspace(2)* %10, i32 45
  %54 = load float addrspace(2)* %53, !tbaa !0
  %55 = getelementptr float addrspace(2)* %10, i32 46
  %56 = load float addrspace(2)* %55, !tbaa !0
  %57 = getelementptr float addrspace(2)* %10, i32 47
  %58 = load float addrspace(2)* %57, !tbaa !0
  %59 = getelementptr float addrspace(2)* %10, i32 52
  %60 = load float addrspace(2)* %59, !tbaa !0
  %61 = getelementptr float addrspace(2)* %10, i32 53
  %62 = load float addrspace(2)* %61, !tbaa !0
  %63 = getelementptr float addrspace(2)* %10, i32 54
  %64 = load float addrspace(2)* %63, !tbaa !0
  %65 = getelementptr float addrspace(2)* %10, i32 55
  %66 = load float addrspace(2)* %65, !tbaa !0
  %67 = getelementptr float addrspace(2)* %10, i32 111
  %68 = load float addrspace(2)* %67, !tbaa !0
  %69 = getelementptr float addrspace(2)* %10, i32 112
  %70 = load float addrspace(2)* %69, !tbaa !0
  %71 = getelementptr float addrspace(2)* %10, i32 113
  %72 = load float addrspace(2)* %71, !tbaa !0
  %73 = getelementptr float addrspace(2)* %10, i32 114
  %74 = load float addrspace(2)* %73, !tbaa !0
  %75 = getelementptr float addrspace(2)* %10, i32 115
  %76 = load float addrspace(2)* %75, !tbaa !0
  %77 = getelementptr float addrspace(2)* %10, i32 116
  %78 = load float addrspace(2)* %77, !tbaa !0
  %79 = getelementptr float addrspace(2)* %10, i32 117
  %80 = load float addrspace(2)* %79, !tbaa !0
  %81 = getelementptr float addrspace(2)* %10, i32 118
  %82 = load float addrspace(2)* %81, !tbaa !0
  %83 = getelementptr float addrspace(2)* %10, i32 120
  %84 = load float addrspace(2)* %83, !tbaa !0
  %85 = getelementptr float addrspace(2)* %10, i32 122
  %86 = load float addrspace(2)* %85, !tbaa !0
  %87 = getelementptr float addrspace(2)* %10, i32 123
  %88 = load float addrspace(2)* %87, !tbaa !0
  %89 = getelementptr float addrspace(2)* %10, i32 124
  %90 = load float addrspace(2)* %89, !tbaa !0
  %91 = getelementptr float addrspace(2)* %10, i32 125
  %92 = load float addrspace(2)* %91, !tbaa !0
  %93 = getelementptr float addrspace(2)* %10, i32 126
  %94 = load float addrspace(2)* %93, !tbaa !0
  %95 = getelementptr float addrspace(2)* %10, i32 131
  %96 = load float addrspace(2)* %95, !tbaa !0
  %97 = getelementptr float addrspace(2)* %10, i32 132
  %98 = load float addrspace(2)* %97, !tbaa !0
  %99 = getelementptr float addrspace(2)* %10, i32 133
  %100 = load float addrspace(2)* %99, !tbaa !0
  %101 = getelementptr float addrspace(2)* %10, i32 134
  %102 = load float addrspace(2)* %101, !tbaa !0
  %103 = getelementptr float addrspace(2)* %10, i32 135
  %104 = load float addrspace(2)* %103, !tbaa !0
  %105 = getelementptr float addrspace(2)* %10, i32 136
  %106 = load float addrspace(2)* %105, !tbaa !0
  %107 = getelementptr float addrspace(2)* %10, i32 137
  %108 = load float addrspace(2)* %107, !tbaa !0
  %109 = getelementptr float addrspace(2)* %10, i32 138
  %110 = load float addrspace(2)* %109, !tbaa !0
  %111 = getelementptr float addrspace(2)* %10, i32 140
  %112 = load float addrspace(2)* %111, !tbaa !0
  %113 = getelementptr float addrspace(2)* %10, i32 142
  %114 = load float addrspace(2)* %113, !tbaa !0
  %115 = getelementptr float addrspace(2)* %10, i32 143
  %116 = load float addrspace(2)* %115, !tbaa !0
  %117 = getelementptr float addrspace(2)* %10, i32 144
  %118 = load float addrspace(2)* %117, !tbaa !0
  %119 = getelementptr float addrspace(2)* %10, i32 145
  %120 = load float addrspace(2)* %119, !tbaa !0
  %121 = getelementptr float addrspace(2)* %10, i32 146
  %122 = load float addrspace(2)* %121, !tbaa !0
  %123 = getelementptr float addrspace(2)* %10, i32 151
  %124 = load float addrspace(2)* %123, !tbaa !0
  %125 = getelementptr float addrspace(2)* %10, i32 152
  %126 = load float addrspace(2)* %125, !tbaa !0
  %127 = getelementptr float addrspace(2)* %10, i32 153
  %128 = load float addrspace(2)* %127, !tbaa !0
  %129 = getelementptr float addrspace(2)* %10, i32 154
  %130 = load float addrspace(2)* %129, !tbaa !0
  %131 = getelementptr float addrspace(2)* %10, i32 155
  %132 = load float addrspace(2)* %131, !tbaa !0
  %133 = getelementptr float addrspace(2)* %10, i32 156
  %134 = load float addrspace(2)* %133, !tbaa !0
  %135 = getelementptr float addrspace(2)* %10, i32 157
  %136 = load float addrspace(2)* %135, !tbaa !0
  %137 = getelementptr float addrspace(2)* %10, i32 158
  %138 = load float addrspace(2)* %137, !tbaa !0
  %139 = getelementptr float addrspace(2)* %10, i32 160
  %140 = load float addrspace(2)* %139, !tbaa !0
  %141 = getelementptr float addrspace(2)* %10, i32 162
  %142 = load float addrspace(2)* %141, !tbaa !0
  %143 = getelementptr float addrspace(2)* %10, i32 163
  %144 = load float addrspace(2)* %143, !tbaa !0
  %145 = getelementptr float addrspace(2)* %10, i32 164
  %146 = load float addrspace(2)* %145, !tbaa !0
  %147 = getelementptr float addrspace(2)* %10, i32 165
  %148 = load float addrspace(2)* %147, !tbaa !0
  %149 = getelementptr float addrspace(2)* %10, i32 166
  %150 = load float addrspace(2)* %149, !tbaa !0
  %151 = getelementptr float addrspace(2)* %10, i32 171
  %152 = load float addrspace(2)* %151, !tbaa !0
  %153 = getelementptr float addrspace(2)* %10, i32 172
  %154 = load float addrspace(2)* %153, !tbaa !0
  %155 = getelementptr float addrspace(2)* %10, i32 173
  %156 = load float addrspace(2)* %155, !tbaa !0
  %157 = getelementptr float addrspace(2)* %10, i32 174
  %158 = load float addrspace(2)* %157, !tbaa !0
  %159 = getelementptr float addrspace(2)* %10, i32 175
  %160 = load float addrspace(2)* %159, !tbaa !0
  %161 = getelementptr float addrspace(2)* %10, i32 176
  %162 = load float addrspace(2)* %161, !tbaa !0
  %163 = getelementptr float addrspace(2)* %10, i32 177
  %164 = load float addrspace(2)* %163, !tbaa !0
  %165 = getelementptr float addrspace(2)* %10, i32 178
  %166 = load float addrspace(2)* %165, !tbaa !0
  %167 = getelementptr float addrspace(2)* %10, i32 180
  %168 = load float addrspace(2)* %167, !tbaa !0
  %169 = getelementptr float addrspace(2)* %10, i32 182
  %170 = load float addrspace(2)* %169, !tbaa !0
  %171 = getelementptr float addrspace(2)* %10, i32 183
  %172 = load float addrspace(2)* %171, !tbaa !0
  %173 = getelementptr float addrspace(2)* %10, i32 184
  %174 = load float addrspace(2)* %173, !tbaa !0
  %175 = getelementptr float addrspace(2)* %10, i32 185
  %176 = load float addrspace(2)* %175, !tbaa !0
  %177 = getelementptr float addrspace(2)* %10, i32 186
  %178 = load float addrspace(2)* %177, !tbaa !0
  %179 = getelementptr float addrspace(2)* %10, i32 192
  %180 = load float addrspace(2)* %179, !tbaa !0
  %181 = getelementptr float addrspace(2)* %10, i32 193
  %182 = load float addrspace(2)* %181, !tbaa !0
  %183 = getelementptr float addrspace(2)* %10, i32 194
  %184 = load float addrspace(2)* %183, !tbaa !0
  %185 = getelementptr float addrspace(2)* %10, i32 195
  %186 = load float addrspace(2)* %185, !tbaa !0
  %187 = getelementptr float addrspace(2)* %10, i32 196
  %188 = load float addrspace(2)* %187, !tbaa !0
  %189 = getelementptr float addrspace(2)* %10, i32 197
  %190 = load float addrspace(2)* %189, !tbaa !0
  %191 = getelementptr float addrspace(2)* %10, i32 198
  %192 = load float addrspace(2)* %191, !tbaa !0
  %193 = getelementptr float addrspace(2)* %10, i32 199
  %194 = load float addrspace(2)* %193, !tbaa !0
  %195 = getelementptr float addrspace(2)* %10, i32 208
  %196 = load float addrspace(2)* %195, !tbaa !0
  %197 = getelementptr float addrspace(2)* %10, i32 209
  %198 = load float addrspace(2)* %197, !tbaa !0
  %199 = getelementptr float addrspace(2)* %10, i32 210
  %200 = load float addrspace(2)* %199, !tbaa !0
  %201 = getelementptr float addrspace(2)* %10, i32 211
  %202 = load float addrspace(2)* %201, !tbaa !0
  %203 = getelementptr float addrspace(2)* %10, i32 212
  %204 = load float addrspace(2)* %203, !tbaa !0
  %205 = getelementptr float addrspace(2)* %10, i32 213
  %206 = load float addrspace(2)* %205, !tbaa !0
  %207 = getelementptr float addrspace(2)* %10, i32 214
  %208 = load float addrspace(2)* %207, !tbaa !0
  %209 = getelementptr float addrspace(2)* %10, i32 215
  %210 = load float addrspace(2)* %209, !tbaa !0
  %211 = getelementptr float addrspace(2)* %10, i32 216
  %212 = load float addrspace(2)* %211, !tbaa !0
  %213 = getelementptr float addrspace(2)* %10, i32 217
  %214 = load float addrspace(2)* %213, !tbaa !0
  %215 = getelementptr float addrspace(2)* %10, i32 218
  %216 = load float addrspace(2)* %215, !tbaa !0
  %217 = getelementptr float addrspace(2)* %10, i32 219
  %218 = load float addrspace(2)* %217, !tbaa !0
  %219 = getelementptr float addrspace(2)* %10, i32 220
  %220 = load float addrspace(2)* %219, !tbaa !0
  %221 = getelementptr float addrspace(2)* %10, i32 221
  %222 = load float addrspace(2)* %221, !tbaa !0
  %223 = getelementptr float addrspace(2)* %10, i32 222
  %224 = load float addrspace(2)* %223, !tbaa !0
  %225 = getelementptr float addrspace(2)* %10, i32 223
  %226 = load float addrspace(2)* %225, !tbaa !0
  %227 = getelementptr float addrspace(2)* %10, i32 224
  %228 = load float addrspace(2)* %227, !tbaa !0
  %229 = getelementptr float addrspace(2)* %10, i32 225
  %230 = load float addrspace(2)* %229, !tbaa !0
  %231 = getelementptr float addrspace(2)* %10, i32 226
  %232 = load float addrspace(2)* %231, !tbaa !0
  %233 = getelementptr float addrspace(2)* %10, i32 227
  %234 = load float addrspace(2)* %233, !tbaa !0
  %235 = getelementptr float addrspace(2)* %10, i32 228
  %236 = load float addrspace(2)* %235, !tbaa !0
  %237 = getelementptr float addrspace(2)* %10, i32 229
  %238 = load float addrspace(2)* %237, !tbaa !0
  %239 = getelementptr float addrspace(2)* %10, i32 232
  %240 = load float addrspace(2)* %239, !tbaa !0
  %241 = getelementptr float addrspace(2)* %10, i32 236
  %242 = load float addrspace(2)* %241, !tbaa !0
  %243 = getelementptr float addrspace(2)* %10, i32 240
  %244 = load float addrspace(2)* %243, !tbaa !0
  %245 = getelementptr float addrspace(2)* %10, i32 244
  %246 = load float addrspace(2)* %245, !tbaa !0
  %247 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %248 = load <16 x i8> addrspace(2)* %247, !tbaa !0
  %249 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %248, i32 0, i32 %5)
  %250 = extractelement <4 x float> %249, i32 0
  %251 = extractelement <4 x float> %249, i32 1
  %252 = extractelement <4 x float> %249, i32 2
  %253 = extractelement <4 x float> %249, i32 3
  %254 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %255 = load <16 x i8> addrspace(2)* %254, !tbaa !0
  %256 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %255, i32 0, i32 %5)
  %257 = extractelement <4 x float> %256, i32 0
  %258 = extractelement <4 x float> %256, i32 1
  %259 = extractelement <4 x float> %256, i32 2
  %260 = extractelement <4 x float> %256, i32 3
  %261 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %262 = load <16 x i8> addrspace(2)* %261, !tbaa !0
  %263 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %262, i32 0, i32 %5)
  %264 = extractelement <4 x float> %263, i32 0
  %265 = extractelement <4 x float> %263, i32 1
  %266 = extractelement <4 x float> %263, i32 2
  %267 = extractelement <4 x float> %263, i32 3
  %268 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %269 = load <16 x i8> addrspace(2)* %268, !tbaa !0
  %270 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %269, i32 0, i32 %5)
  %271 = extractelement <4 x float> %270, i32 0
  %272 = extractelement <4 x float> %270, i32 1
  %273 = extractelement <4 x float> %270, i32 2
  %274 = extractelement <4 x float> %270, i32 3
  %275 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %276 = load <16 x i8> addrspace(2)* %275, !tbaa !0
  %277 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %276, i32 0, i32 %5)
  %278 = extractelement <4 x float> %277, i32 0
  %279 = extractelement <4 x float> %277, i32 1
  %280 = extractelement <4 x float> %277, i32 2
  %281 = fadd float %257, -1.280000e+02
  %282 = fadd float %258, -1.280000e+02
  %283 = fadd float %259, -1.280000e+02
  %284 = fadd float %260, -1.280000e+02
  %285 = fcmp ult float %281, %12
  %286 = select i1 %285, float 1.000000e+00, float 0.000000e+00
  %287 = fcmp ult float %282, %12
  %288 = select i1 %287, float 1.000000e+00, float 0.000000e+00
  %289 = fcmp ult float %283, %12
  %290 = select i1 %289, float 1.000000e+00, float 0.000000e+00
  %291 = fcmp ult float %284, %12
  %292 = select i1 %291, float 1.000000e+00, float 0.000000e+00
  %293 = fsub float -0.000000e+00, %286
  %294 = fptosi float %293 to i32
  %295 = fsub float -0.000000e+00, %288
  %296 = fptosi float %295 to i32
  %297 = fsub float -0.000000e+00, %290
  %298 = fptosi float %297 to i32
  %299 = fsub float -0.000000e+00, %292
  %300 = fptosi float %299 to i32
  %301 = bitcast i32 %294 to float
  %302 = bitcast i32 %296 to float
  %303 = bitcast i32 %298 to float
  %304 = bitcast i32 %300 to float
  %305 = bitcast float %301 to i32
  %306 = and i32 %305, 1065353216
  %307 = bitcast float %302 to i32
  %308 = and i32 %307, 1065353216
  %309 = bitcast float %303 to i32
  %310 = and i32 %309, 1065353216
  %311 = bitcast float %304 to i32
  %312 = and i32 %311, 1065353216
  %313 = bitcast i32 %306 to float
  %314 = bitcast i32 %308 to float
  %315 = bitcast i32 %310 to float
  %316 = bitcast i32 %312 to float
  %317 = call float @fabs(float %281)
  %318 = call float @fabs(float %282)
  %319 = call float @fabs(float %283)
  %320 = call float @fabs(float %284)
  %321 = fsub float -0.000000e+00, %313
  %322 = fadd float %317, %321
  %323 = fsub float -0.000000e+00, %314
  %324 = fadd float %318, %323
  %325 = fsub float -0.000000e+00, %315
  %326 = fadd float %319, %325
  %327 = fsub float -0.000000e+00, %316
  %328 = fadd float %320, %327
  %329 = fadd float %322, -6.400000e+01
  %330 = fadd float %324, -6.400000e+01
  %331 = fadd float %326, -6.400000e+01
  %332 = fadd float %328, -6.400000e+01
  %333 = fcmp ult float %329, %12
  %334 = select i1 %333, float 1.000000e+00, float 0.000000e+00
  %335 = fcmp ult float %330, %12
  %336 = select i1 %335, float 1.000000e+00, float 0.000000e+00
  %337 = fcmp ult float %331, %12
  %338 = select i1 %337, float 1.000000e+00, float 0.000000e+00
  %339 = fcmp ult float %332, %12
  %340 = select i1 %339, float 1.000000e+00, float 0.000000e+00
  %341 = fsub float -0.000000e+00, %334
  %342 = fptosi float %341 to i32
  %343 = fsub float -0.000000e+00, %336
  %344 = fptosi float %343 to i32
  %345 = fsub float -0.000000e+00, %338
  %346 = fptosi float %345 to i32
  %347 = fsub float -0.000000e+00, %340
  %348 = fptosi float %347 to i32
  %349 = bitcast i32 %342 to float
  %350 = bitcast i32 %344 to float
  %351 = bitcast i32 %346 to float
  %352 = bitcast i32 %348 to float
  %353 = bitcast float %349 to i32
  %354 = and i32 %353, 1065353216
  %355 = bitcast float %350 to i32
  %356 = and i32 %355, 1065353216
  %357 = bitcast float %351 to i32
  %358 = and i32 %357, 1065353216
  %359 = bitcast float %352 to i32
  %360 = and i32 %359, 1065353216
  %361 = bitcast i32 %354 to float
  %362 = bitcast i32 %356 to float
  %363 = bitcast i32 %358 to float
  %364 = bitcast i32 %360 to float
  %365 = call float @fabs(float %329)
  %366 = call float @fabs(float %330)
  %367 = call float @fabs(float %331)
  %368 = call float @fabs(float %332)
  %369 = fsub float -0.000000e+00, %361
  %370 = fadd float %365, %369
  %371 = fsub float -0.000000e+00, %362
  %372 = fadd float %366, %371
  %373 = fsub float -0.000000e+00, %363
  %374 = fadd float %367, %373
  %375 = fsub float -0.000000e+00, %364
  %376 = fadd float %368, %375
  %377 = fsub float -0.000000e+00, %313
  %378 = fmul float %16, %377
  %379 = fadd float %378, %14
  %380 = fsub float -0.000000e+00, %315
  %381 = fmul float %16, %380
  %382 = fadd float %381, %14
  %383 = fsub float -0.000000e+00, %316
  %384 = fmul float %16, %383
  %385 = fadd float %384, %14
  %386 = fmul float %370, 0xBF90410420000000
  %387 = fadd float %386, 1.000000e+00
  %388 = fmul float %374, 0xBF90410420000000
  %389 = fadd float %388, 1.000000e+00
  %390 = fmul float %372, 0xBF90410420000000
  %391 = fadd float %390, %387
  %392 = fmul float %370, 0x3F90410420000000
  %393 = fmul float %372, 0x3F90410420000000
  %394 = fmul float %374, 0x3F90410420000000
  %395 = fmul float %376, 0x3F90410420000000
  %396 = fmul float %376, 0xBF90410420000000
  %397 = fadd float %396, %389
  %398 = fsub float -0.000000e+00, %361
  %399 = fmul float %16, %398
  %400 = fadd float %399, %14
  %401 = fsub float -0.000000e+00, %362
  %402 = fmul float %16, %401
  %403 = fadd float %402, %14
  %404 = fsub float -0.000000e+00, %363
  %405 = fmul float %16, %404
  %406 = fadd float %405, %14
  %407 = fsub float -0.000000e+00, %364
  %408 = fmul float %16, %407
  %409 = fadd float %408, %14
  %410 = fmul float %392, %392
  %411 = fmul float %393, %393
  %412 = fadd float %411, %410
  %413 = fmul float %391, %391
  %414 = fadd float %412, %413
  %415 = call float @llvm.AMDGPU.rsq(float %414)
  %416 = fmul float %392, %415
  %417 = fmul float %393, %415
  %418 = fmul float %391, %415
  %419 = fmul float %400, %416
  %420 = fmul float %403, %417
  %421 = fmul float %379, %418
  %422 = fmul float %278, %24
  %423 = fadd float %422, %419
  %424 = fmul float %279, %24
  %425 = fadd float %424, %420
  %426 = fmul float %280, %24
  %427 = fadd float %426, %421
  %428 = fmul float %423, %228
  %429 = fmul float %425, %230
  %430 = fadd float %429, %428
  %431 = fmul float %427, %232
  %432 = fadd float %430, %431
  %433 = fmul float %394, %394
  %434 = fmul float %395, %395
  %435 = fadd float %434, %433
  %436 = fmul float %397, %397
  %437 = fadd float %435, %436
  %438 = call float @llvm.AMDGPU.rsq(float %437)
  %439 = fmul float %394, %438
  %440 = fmul float %395, %438
  %441 = fmul float %397, %438
  %442 = fmul float %406, %439
  %443 = fmul float %409, %440
  %444 = fmul float %382, %441
  %445 = fmul float %423, %212
  %446 = fmul float %425, %214
  %447 = fadd float %446, %445
  %448 = fmul float %427, %216
  %449 = fadd float %447, %448
  %450 = fmul float %423, %220
  %451 = fmul float %425, %222
  %452 = fadd float %451, %450
  %453 = fmul float %427, %224
  %454 = fadd float %452, %453
  %455 = fmul float %278, %24
  %456 = fadd float %455, %442
  %457 = fmul float %279, %24
  %458 = fadd float %457, %443
  %459 = fmul float %280, %24
  %460 = fadd float %459, %444
  %461 = fmul float %449, %449
  %462 = fmul float %454, %454
  %463 = fadd float %462, %461
  %464 = fmul float %432, %432
  %465 = fadd float %463, %464
  %466 = fmul float %456, %228
  %467 = fmul float %458, %230
  %468 = fadd float %467, %466
  %469 = fmul float %460, %232
  %470 = fadd float %468, %469
  %471 = call float @llvm.AMDGPU.rsq(float %465)
  %472 = fmul float %456, %212
  %473 = fmul float %458, %214
  %474 = fadd float %473, %472
  %475 = fmul float %460, %216
  %476 = fadd float %474, %475
  %477 = fmul float %456, %220
  %478 = fmul float %458, %222
  %479 = fadd float %478, %477
  %480 = fmul float %460, %224
  %481 = fadd float %479, %480
  %482 = fmul float %449, %471
  %483 = fmul float %454, %471
  %484 = fmul float %432, %471
  %485 = fmul float %476, %476
  %486 = fmul float %481, %481
  %487 = fadd float %486, %485
  %488 = fmul float %470, %470
  %489 = fadd float %487, %488
  %490 = call float @llvm.AMDGPU.rsq(float %489)
  %491 = fmul float %432, %481
  %492 = fmul float %449, %470
  %493 = fmul float %454, %476
  %494 = fmul float %476, %490
  %495 = fmul float %481, %490
  %496 = fmul float %470, %490
  %497 = fsub float -0.000000e+00, %491
  %498 = fmul float %454, %470
  %499 = fadd float %498, %497
  %500 = fsub float -0.000000e+00, %492
  %501 = fmul float %432, %476
  %502 = fadd float %501, %500
  %503 = fsub float -0.000000e+00, %493
  %504 = fmul float %449, %481
  %505 = fadd float %504, %503
  %506 = fmul float %385, %499
  %507 = fmul float %385, %502
  %508 = fmul float %385, %505
  %509 = fmul float %271, %24
  %510 = fadd float %509, %250
  %511 = fmul float %272, %24
  %512 = fadd float %511, %251
  %513 = fmul float %273, %24
  %514 = fadd float %513, %252
  %515 = fmul float %506, %506
  %516 = fmul float %507, %507
  %517 = fadd float %516, %515
  %518 = fmul float %508, %508
  %519 = fadd float %517, %518
  %520 = fmul float %510, %228
  %521 = fmul float %512, %230
  %522 = fadd float %520, %521
  %523 = fmul float %514, %232
  %524 = fadd float %522, %523
  %525 = fmul float %253, %234
  %526 = fadd float %524, %525
  %527 = call float @llvm.AMDGPU.rsq(float %519)
  %528 = fmul float %510, %212
  %529 = fmul float %512, %214
  %530 = fadd float %528, %529
  %531 = fmul float %514, %216
  %532 = fadd float %530, %531
  %533 = fmul float %253, %218
  %534 = fadd float %532, %533
  %535 = fmul float %510, %220
  %536 = fmul float %512, %222
  %537 = fadd float %535, %536
  %538 = fmul float %514, %224
  %539 = fadd float %537, %538
  %540 = fmul float %253, %226
  %541 = fadd float %539, %540
  %542 = fmul float %506, %527
  %543 = fmul float %507, %527
  %544 = fmul float %508, %527
  %545 = fsub float -0.000000e+00, %534
  %546 = fadd float %545, %18
  %547 = fsub float -0.000000e+00, %541
  %548 = fadd float %547, %20
  %549 = fsub float -0.000000e+00, %526
  %550 = fadd float %549, %22
  %551 = bitcast float %240 to i32
  %552 = icmp ne i32 %551, 0
  br i1 %552, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %553 = fadd float %545, %78
  %554 = fsub float -0.000000e+00, %541
  %555 = fadd float %554, %80
  %556 = fsub float -0.000000e+00, %526
  %557 = fadd float %556, %82
  %558 = fmul float %553, %553
  %559 = fmul float %555, %555
  %560 = fadd float %559, %558
  %561 = fmul float %557, %557
  %562 = fadd float %560, %561
  %563 = call float @llvm.AMDGPU.rsq(float %562)
  %564 = fmul float %553, %563
  %565 = fmul float %555, %563
  %566 = fmul float %557, %563
  %567 = fsub float -0.000000e+00, %564
  %568 = fsub float -0.000000e+00, %565
  %569 = fsub float -0.000000e+00, %566
  %570 = fmul float %70, %567
  %571 = fmul float %72, %568
  %572 = fadd float %571, %570
  %573 = fmul float %74, %569
  %574 = fadd float %572, %573
  %575 = fsub float -0.000000e+00, %86
  %576 = fadd float %574, %575
  %577 = fmul float %576, %88
  %578 = fmul float %14, %14
  %579 = fmul float %562, %563
  %580 = fmul float %562, %14
  %581 = fcmp uge float %577, 0x3F1A36E2E0000000
  %582 = select i1 %581, float %577, float 0x3F1A36E2E0000000
  %583 = fmul float %90, %578
  %584 = fmul float %92, %579
  %585 = fadd float %584, %583
  %586 = fmul float %94, %580
  %587 = fadd float %585, %586
  %588 = call float @llvm.pow.f32(float %582, float %84)
  %589 = fdiv float 1.000000e+00, %587
  %590 = fcmp uge float %588, %14
  %591 = select i1 %590, float %14, float %588
  %592 = fsub float -0.000000e+00, %589
  %593 = fmul float %589, %591
  %594 = fadd float %593, %592
  %595 = fmul float %76, %594
  %596 = fadd float %595, %589
  %597 = fsub float -0.000000e+00, %596
  %598 = fadd float %597, %14
  %599 = fmul float %68, %598
  %600 = fadd float %599, %596
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp32.0 = phi float [ %600, %IF ], [ %12, %main_body ]
  %601 = bitcast float %242 to i32
  %602 = icmp ne i32 %601, 0
  br i1 %602, label %IF57, label %ENDIF56

IF57:                                             ; preds = %ENDIF
  %603 = fsub float -0.000000e+00, %534
  %604 = fadd float %603, %106
  %605 = fsub float -0.000000e+00, %541
  %606 = fadd float %605, %108
  %607 = fsub float -0.000000e+00, %526
  %608 = fadd float %607, %110
  %609 = fmul float %604, %604
  %610 = fmul float %606, %606
  %611 = fadd float %610, %609
  %612 = fmul float %608, %608
  %613 = fadd float %611, %612
  %614 = call float @llvm.AMDGPU.rsq(float %613)
  %615 = fmul float %604, %614
  %616 = fmul float %606, %614
  %617 = fmul float %608, %614
  %618 = fsub float -0.000000e+00, %615
  %619 = fsub float -0.000000e+00, %616
  %620 = fsub float -0.000000e+00, %617
  %621 = fmul float %98, %618
  %622 = fmul float %100, %619
  %623 = fadd float %622, %621
  %624 = fmul float %102, %620
  %625 = fadd float %623, %624
  %626 = fsub float -0.000000e+00, %114
  %627 = fadd float %625, %626
  %628 = fmul float %627, %116
  %629 = fmul float %14, %14
  %630 = fmul float %613, %614
  %631 = fmul float %613, %14
  %632 = fcmp uge float %628, 0x3F1A36E2E0000000
  %633 = select i1 %632, float %628, float 0x3F1A36E2E0000000
  %634 = fmul float %118, %629
  %635 = fmul float %120, %630
  %636 = fadd float %635, %634
  %637 = fmul float %122, %631
  %638 = fadd float %636, %637
  %639 = call float @llvm.pow.f32(float %633, float %112)
  %640 = fdiv float 1.000000e+00, %638
  %641 = fcmp uge float %639, %14
  %642 = select i1 %641, float %14, float %639
  %643 = fsub float -0.000000e+00, %640
  %644 = fmul float %640, %642
  %645 = fadd float %644, %643
  %646 = fmul float %104, %645
  %647 = fadd float %646, %640
  %648 = fsub float -0.000000e+00, %647
  %649 = fadd float %648, %14
  %650 = fmul float %96, %649
  %651 = fadd float %650, %647
  br label %ENDIF56

ENDIF56:                                          ; preds = %ENDIF, %IF57
  %temp33.0 = phi float [ %651, %IF57 ], [ %12, %ENDIF ]
  %652 = bitcast float %244 to i32
  %653 = icmp ne i32 %652, 0
  br i1 %653, label %IF60, label %ENDIF59

IF60:                                             ; preds = %ENDIF56
  %654 = fsub float -0.000000e+00, %534
  %655 = fadd float %654, %134
  %656 = fsub float -0.000000e+00, %541
  %657 = fadd float %656, %136
  %658 = fsub float -0.000000e+00, %526
  %659 = fadd float %658, %138
  %660 = fmul float %655, %655
  %661 = fmul float %657, %657
  %662 = fadd float %661, %660
  %663 = fmul float %659, %659
  %664 = fadd float %662, %663
  %665 = call float @llvm.AMDGPU.rsq(float %664)
  %666 = fmul float %655, %665
  %667 = fmul float %657, %665
  %668 = fmul float %659, %665
  %669 = fsub float -0.000000e+00, %666
  %670 = fsub float -0.000000e+00, %667
  %671 = fsub float -0.000000e+00, %668
  %672 = fmul float %126, %669
  %673 = fmul float %128, %670
  %674 = fadd float %673, %672
  %675 = fmul float %130, %671
  %676 = fadd float %674, %675
  %677 = fsub float -0.000000e+00, %142
  %678 = fadd float %676, %677
  %679 = fmul float %678, %144
  %680 = fmul float %14, %14
  %681 = fmul float %664, %665
  %682 = fmul float %664, %14
  %683 = fcmp uge float %679, 0x3F1A36E2E0000000
  %684 = select i1 %683, float %679, float 0x3F1A36E2E0000000
  %685 = fmul float %146, %680
  %686 = fmul float %148, %681
  %687 = fadd float %686, %685
  %688 = fmul float %150, %682
  %689 = fadd float %687, %688
  %690 = call float @llvm.pow.f32(float %684, float %140)
  %691 = fdiv float 1.000000e+00, %689
  %692 = fcmp uge float %690, %14
  %693 = select i1 %692, float %14, float %690
  %694 = fsub float -0.000000e+00, %691
  %695 = fmul float %691, %693
  %696 = fadd float %695, %694
  %697 = fmul float %132, %696
  %698 = fadd float %697, %691
  %699 = fsub float -0.000000e+00, %698
  %700 = fadd float %699, %14
  %701 = fmul float %124, %700
  %702 = fadd float %701, %698
  br label %ENDIF59

ENDIF59:                                          ; preds = %ENDIF56, %IF60
  %temp34.0 = phi float [ %702, %IF60 ], [ %12, %ENDIF56 ]
  %703 = bitcast float %246 to i32
  %704 = icmp ne i32 %703, 0
  br i1 %704, label %IF63, label %ENDIF62

IF63:                                             ; preds = %ENDIF59
  %705 = fsub float -0.000000e+00, %534
  %706 = fadd float %705, %162
  %707 = fsub float -0.000000e+00, %541
  %708 = fadd float %707, %164
  %709 = fsub float -0.000000e+00, %526
  %710 = fadd float %709, %166
  %711 = fmul float %706, %706
  %712 = fmul float %708, %708
  %713 = fadd float %712, %711
  %714 = fmul float %710, %710
  %715 = fadd float %713, %714
  %716 = call float @llvm.AMDGPU.rsq(float %715)
  %717 = fmul float %706, %716
  %718 = fmul float %708, %716
  %719 = fmul float %710, %716
  %720 = fsub float -0.000000e+00, %717
  %721 = fsub float -0.000000e+00, %718
  %722 = fsub float -0.000000e+00, %719
  %723 = fmul float %154, %720
  %724 = fmul float %156, %721
  %725 = fadd float %724, %723
  %726 = fmul float %158, %722
  %727 = fadd float %725, %726
  %728 = fsub float -0.000000e+00, %170
  %729 = fadd float %727, %728
  %730 = fmul float %729, %172
  %731 = fmul float %14, %14
  %732 = fmul float %715, %716
  %733 = fmul float %715, %14
  %734 = fcmp uge float %730, 0x3F1A36E2E0000000
  %735 = select i1 %734, float %730, float 0x3F1A36E2E0000000
  %736 = fmul float %174, %731
  %737 = fmul float %176, %732
  %738 = fadd float %737, %736
  %739 = fmul float %178, %733
  %740 = fadd float %738, %739
  %741 = call float @llvm.pow.f32(float %735, float %168)
  %742 = fdiv float 1.000000e+00, %740
  %743 = fcmp uge float %741, %14
  %744 = select i1 %743, float %14, float %741
  %745 = fsub float -0.000000e+00, %742
  %746 = fmul float %742, %744
  %747 = fadd float %746, %745
  %748 = fmul float %160, %747
  %749 = fadd float %748, %742
  %750 = fsub float -0.000000e+00, %749
  %751 = fadd float %750, %14
  %752 = fmul float %152, %751
  %753 = fadd float %752, %749
  br label %ENDIF62

ENDIF62:                                          ; preds = %ENDIF59, %IF63
  %temp20.0 = phi float [ %753, %IF63 ], [ %12, %ENDIF59 ]
  %754 = fmul float %534, %60
  %755 = fmul float %541, %62
  %756 = fadd float %754, %755
  %757 = fmul float %526, %64
  %758 = fadd float %756, %757
  %759 = fmul float %14, %66
  %760 = fadd float %758, %759
  %761 = fmul float %274, %26
  %762 = fmul float %534, %28
  %763 = fmul float %541, %30
  %764 = fadd float %762, %763
  %765 = fmul float %526, %32
  %766 = fadd float %764, %765
  %767 = fmul float %14, %34
  %768 = fadd float %766, %767
  %769 = fmul float %534, %36
  %770 = fmul float %541, %38
  %771 = fadd float %769, %770
  %772 = fmul float %526, %40
  %773 = fadd float %771, %772
  %774 = fmul float %14, %42
  %775 = fadd float %773, %774
  %776 = fmul float %534, %44
  %777 = fmul float %541, %46
  %778 = fadd float %776, %777
  %779 = fmul float %526, %48
  %780 = fadd float %778, %779
  %781 = fmul float %14, %50
  %782 = fadd float %780, %781
  %783 = fmul float %534, %52
  %784 = fmul float %541, %54
  %785 = fadd float %783, %784
  %786 = fmul float %526, %56
  %787 = fadd float %785, %786
  %788 = fmul float %14, %58
  %789 = fadd float %787, %788
  %790 = fmul float %264, %180
  %791 = fmul float %265, %182
  %792 = fadd float %790, %791
  %793 = fmul float %266, %184
  %794 = fadd float %792, %793
  %795 = fmul float %267, %186
  %796 = fadd float %794, %795
  %797 = fmul float %264, %188
  %798 = fmul float %265, %190
  %799 = fadd float %797, %798
  %800 = fmul float %266, %192
  %801 = fadd float %799, %800
  %802 = fmul float %267, %194
  %803 = fadd float %801, %802
  %804 = fmul float %264, %196
  %805 = fmul float %265, %198
  %806 = fadd float %804, %805
  %807 = fmul float %266, %200
  %808 = fadd float %806, %807
  %809 = fmul float %267, %202
  %810 = fadd float %808, %809
  %811 = fmul float %264, %204
  %812 = fmul float %265, %206
  %813 = fadd float %811, %812
  %814 = fmul float %266, %208
  %815 = fadd float %813, %814
  %816 = fmul float %267, %210
  %817 = fadd float %815, %816
  %818 = fsub float -0.000000e+00, %789
  %819 = fmul float %782, %16
  %820 = fadd float %819, %818
  %821 = fsub float -0.000000e+00, %775
  %822 = fmul float %236, %789
  %823 = fadd float %822, %768
  %824 = fmul float %238, %789
  %825 = fadd float %824, %821
  %826 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 1
  %827 = load float addrspace(2)* addrspace(2)* %826, !tbaa !0
  %828 = getelementptr float addrspace(2)* %827, i32 0
  %829 = load float addrspace(2)* %828, !tbaa !0
  %830 = fmul float %829, %768
  %831 = getelementptr float addrspace(2)* %827, i32 1
  %832 = load float addrspace(2)* %831, !tbaa !0
  %833 = fmul float %832, %775
  %834 = fadd float %830, %833
  %835 = getelementptr float addrspace(2)* %827, i32 2
  %836 = load float addrspace(2)* %835, !tbaa !0
  %837 = fmul float %836, %782
  %838 = fadd float %834, %837
  %839 = getelementptr float addrspace(2)* %827, i32 3
  %840 = load float addrspace(2)* %839, !tbaa !0
  %841 = fmul float %840, %789
  %842 = fadd float %838, %841
  %843 = getelementptr float addrspace(2)* %827, i32 4
  %844 = load float addrspace(2)* %843, !tbaa !0
  %845 = fmul float %844, %768
  %846 = getelementptr float addrspace(2)* %827, i32 5
  %847 = load float addrspace(2)* %846, !tbaa !0
  %848 = fmul float %847, %775
  %849 = fadd float %845, %848
  %850 = getelementptr float addrspace(2)* %827, i32 6
  %851 = load float addrspace(2)* %850, !tbaa !0
  %852 = fmul float %851, %782
  %853 = fadd float %849, %852
  %854 = getelementptr float addrspace(2)* %827, i32 7
  %855 = load float addrspace(2)* %854, !tbaa !0
  %856 = fmul float %855, %789
  %857 = fadd float %853, %856
  %858 = getelementptr float addrspace(2)* %827, i32 8
  %859 = load float addrspace(2)* %858, !tbaa !0
  %860 = fmul float %859, %768
  %861 = getelementptr float addrspace(2)* %827, i32 9
  %862 = load float addrspace(2)* %861, !tbaa !0
  %863 = fmul float %862, %775
  %864 = fadd float %860, %863
  %865 = getelementptr float addrspace(2)* %827, i32 10
  %866 = load float addrspace(2)* %865, !tbaa !0
  %867 = fmul float %866, %782
  %868 = fadd float %864, %867
  %869 = getelementptr float addrspace(2)* %827, i32 11
  %870 = load float addrspace(2)* %869, !tbaa !0
  %871 = fmul float %870, %789
  %872 = fadd float %868, %871
  %873 = getelementptr float addrspace(2)* %827, i32 12
  %874 = load float addrspace(2)* %873, !tbaa !0
  %875 = fmul float %874, %768
  %876 = getelementptr float addrspace(2)* %827, i32 13
  %877 = load float addrspace(2)* %876, !tbaa !0
  %878 = fmul float %877, %775
  %879 = fadd float %875, %878
  %880 = getelementptr float addrspace(2)* %827, i32 14
  %881 = load float addrspace(2)* %880, !tbaa !0
  %882 = fmul float %881, %782
  %883 = fadd float %879, %882
  %884 = getelementptr float addrspace(2)* %827, i32 15
  %885 = load float addrspace(2)* %884, !tbaa !0
  %886 = fmul float %885, %789
  %887 = fadd float %883, %886
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %842, float %857, float %872, float %887)
  %888 = getelementptr float addrspace(2)* %827, i32 16
  %889 = load float addrspace(2)* %888, !tbaa !0
  %890 = fmul float %889, %768
  %891 = getelementptr float addrspace(2)* %827, i32 17
  %892 = load float addrspace(2)* %891, !tbaa !0
  %893 = fmul float %892, %775
  %894 = fadd float %890, %893
  %895 = getelementptr float addrspace(2)* %827, i32 18
  %896 = load float addrspace(2)* %895, !tbaa !0
  %897 = fmul float %896, %782
  %898 = fadd float %894, %897
  %899 = getelementptr float addrspace(2)* %827, i32 19
  %900 = load float addrspace(2)* %899, !tbaa !0
  %901 = fmul float %900, %789
  %902 = fadd float %898, %901
  %903 = getelementptr float addrspace(2)* %827, i32 20
  %904 = load float addrspace(2)* %903, !tbaa !0
  %905 = fmul float %904, %768
  %906 = getelementptr float addrspace(2)* %827, i32 21
  %907 = load float addrspace(2)* %906, !tbaa !0
  %908 = fmul float %907, %775
  %909 = fadd float %905, %908
  %910 = getelementptr float addrspace(2)* %827, i32 22
  %911 = load float addrspace(2)* %910, !tbaa !0
  %912 = fmul float %911, %782
  %913 = fadd float %909, %912
  %914 = getelementptr float addrspace(2)* %827, i32 23
  %915 = load float addrspace(2)* %914, !tbaa !0
  %916 = fmul float %915, %789
  %917 = fadd float %913, %916
  %918 = getelementptr float addrspace(2)* %827, i32 24
  %919 = load float addrspace(2)* %918, !tbaa !0
  %920 = fmul float %919, %768
  %921 = getelementptr float addrspace(2)* %827, i32 25
  %922 = load float addrspace(2)* %921, !tbaa !0
  %923 = fmul float %922, %775
  %924 = fadd float %920, %923
  %925 = getelementptr float addrspace(2)* %827, i32 26
  %926 = load float addrspace(2)* %925, !tbaa !0
  %927 = fmul float %926, %782
  %928 = fadd float %924, %927
  %929 = getelementptr float addrspace(2)* %827, i32 27
  %930 = load float addrspace(2)* %929, !tbaa !0
  %931 = fmul float %930, %789
  %932 = fadd float %928, %931
  %933 = getelementptr float addrspace(2)* %827, i32 28
  %934 = load float addrspace(2)* %933, !tbaa !0
  %935 = fmul float %934, %768
  %936 = getelementptr float addrspace(2)* %827, i32 29
  %937 = load float addrspace(2)* %936, !tbaa !0
  %938 = fmul float %937, %775
  %939 = fadd float %935, %938
  %940 = getelementptr float addrspace(2)* %827, i32 30
  %941 = load float addrspace(2)* %940, !tbaa !0
  %942 = fmul float %941, %782
  %943 = fadd float %939, %942
  %944 = getelementptr float addrspace(2)* %827, i32 31
  %945 = load float addrspace(2)* %944, !tbaa !0
  %946 = fmul float %945, %789
  %947 = fadd float %943, %946
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %902, float %917, float %932, float %947)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %796, float %803, float %810, float %817)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %temp32.0, float %temp33.0, float %temp34.0, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %546, float %548, float %550, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %494, float %495, float %496, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %542, float %543, float %544, float %316)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %482, float %483, float %484, float %395)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %534, float %541, float %526, float %temp20.0)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %768, float %775, float %760, float %761)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %823, float %825, float %820, float %789)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #3

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #4

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { readnone }
attributes #4 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
hl2_linux: AMDGPUInstrInfo.cpp:109: virtual void llvm::AMDGPUInstrInfo::storeRegToStackSlot(llvm::MachineBasicBlock&, llvm::MachineBasicBlock::iterator, unsigned int, bool, int, const llvm::TargetRegisterClass*, const llvm::TargetRegisterInfo*) const: Assertion `!"Not Implemented"' failed.
ALSA lib pcm.c:7339:(snd_pcm_recover) underrun occurred
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