diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
index a60a5ac..aab68c8 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
@@ -50,6 +50,10 @@ nv50_dac_sense(struct nv50_disp_priv *priv, int or, u32 loadval)
 {
 	const u32 doff = (or * 0x800);
 	int load = -EINVAL;
+
+	nv_info(priv, "%s (1) - 0x%08x(%d): 0x%08x\n", __func__,
+		(0x61a004 + doff), or, nv_rd32(priv, 0x61a004 + doff));
+
 	nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000);
 	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
 	nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval);
@@ -57,8 +61,16 @@ nv50_dac_sense(struct nv50_disp_priv *priv, int or, u32 loadval)
 	nv_wr32(priv, 0x61a00c + doff, 0x80000000);
 	load = (nv_rd32(priv, 0x61a00c + doff) & 0x38000000) >> 27;
 	nv_wr32(priv, 0x61a00c + doff, 0x00000000);
+
+	nv_info(priv, "%s (2) - 0x%08x(%d): 0x%08x\n", __func__,
+		(0x61a004 + doff), or, nv_rd32(priv, 0x61a004 + doff));
+
 	nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000);
 	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
+
+	nv_info(priv, "%s (3) - 0x%08x(%d): 0x%08x\n", __func__,
+		(0x61a004 + doff), or, nv_rd32(priv, 0x61a004 + doff));
+
 	return load;
 }
 
@@ -79,10 +91,11 @@ nv50_dac_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
 		break;
 	case NV50_DISP_DAC_LOAD:
 		ret = priv->dac.sense(priv, or, data[0]);
-		if (ret >= 0) {
-			data[0] = ret;
-			ret = 0;
-		}
+		nv_info(priv, "%s or %d\n", __func__, or);
+		nv_info(priv, "%s data[0] 0x%08x\n", __func__, data[0]);
+		nv_info(priv, "%s ret 0x%08x\n", __func__, ret);
+		data[0] = ret;
+		ret = 0;
 		break;
 	default:
 		BUG_ON(1);