[ 596.059021] netpoll: netconsole: interface 'em1' [ 596.059073] netpoll: netconsole: remote port 6666 [ 596.059122] netpoll: netconsole: remote IPv4 address 10.239.47.45 [ 596.059176] netpoll: netconsole: remote ethernet address 6c:f0:49:72:82:c6 [ 596.059260] netpoll: netconsole: local IP 10.239.47.104 [ 596.059341] console [netcon0] enabled [ 596.059376] netconsole: network logging started [ 596.066313] netpoll: netconsole: local port 6665 [ 596.066398] netpoll: netconsole: local IPv4 address 0.0.0.0 [ 596.066484] netpoll: netconsole: interface 'em1' [ 596.066526] netpoll: netconsole: remote port 6666 [ 596.066574] netpoll: netconsole: remote IPv4 address 10.239.47.45 [ 596.066628] netpoll: netconsole: remote ethernet address 6c:f0:49:72:82:c6 [ 596.066687] netpoll: netconsole: local IP 10.239.47.104 [ 596.066757] console [netcon0] enabled [ 596.066820] netconsole: network logging started [ 602.935122] [drm:i915_driver_open], [ 602.935241] [drm:intel_crtc_cursor_set], cursor off [ 602.935344] [drm:intel_crtc_set_config], [CRTC:3] [FB:31] #connectors=1 (x y) (0 0) [ 602.935504] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 602.935658] [drm:intel_crtc_cursor_set], cursor off [ 602.935758] [drm:intel_crtc_set_config], [CRTC:5] [NOFB] [ 602.935862] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 602.936073] [drm:i915_driver_open], [ 602.936422] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8] [ 602.936439] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8] [ 602.936455] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8] [ 602.936463] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8] [ 602.936473] [drm:drm_mode_getconnector], [CONNECTOR:10:?] [ 602.936481] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] [ 602.936487] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 602.936501] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 602.936736] [drm:intel_dp_probe_oui], Sink OUI: 001cf8 [ 602.936906] [drm:intel_dp_probe_oui], Branch OUI: 000000 [ 602.936910] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 602.936923] [drm:drm_edid_to_eld], ELD: no CEA Extension found [ 602.936929] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes : [ 602.936933] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 602.936939] [drm:drm_mode_debug_printmodeline], Modeline 12:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 602.936946] [drm:drm_mode_getconnector], [CONNECTOR:10:?] [ 602.936954] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8] [ 602.936959] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8] [ 602.937028] [drm:drm_mode_addfb2], [FB:32] [ 602.937038] [drm:drm_mode_addfb2], [FB:33] [ 602.937043] [drm:drm_mode_setcrtc], [CRTC:3] [ 602.937048] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 602.937052] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0) [ 602.937057] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 602.937062] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 602.937068] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 602.937073] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 602.937077] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 602.937151] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 602.937154] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0 [ 602.937164] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A [ 602.937170] [drm:intel_dump_pipe_config], cpu_transcoder: A [ 602.937175] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0 [ 602.937180] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 602.937187] [drm:intel_dump_pipe_config], requested mode: [ 602.937192] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 602.937200] [drm:intel_dump_pipe_config], adjusted mode: [ 602.937205] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 602.937214] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 602.937220] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 602.937226] [drm:intel_dump_pipe_config], ips: 0 [ 602.937231] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 602.937239] [drm:ironlake_edp_panel_vdd_on], eDP VDD already on [ 602.937247] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 602.937255] [drm:ironlake_edp_backlight_off], [ 603.138409] [drm:ironlake_edp_panel_off], Turn eDP power off [ 603.138419] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 603.138425] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 604.016742] [drm:intel_dp_link_down], [ 604.068776] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 604.120013] [drm:intel_update_fbc], no output, disabling [ 604.126988] [drm:ironlake_update_plane], Writing base 00450000 00000000 0 0 2752 [ 604.127004] [drm:intel_update_fbc], no output, disabling [ 604.127014] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 604.127022] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 604.127028] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 604.127535] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 4 [ 604.127544] [drm:ironlake_check_srwm], watermark 1: display plane 13, fbc lines 3, cursor 4 [ 604.127552] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 4 [ 604.127562] [drm:ironlake_edp_pll_on], [ 604.179838] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 604.231872] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 604.231884] [drm:intel_update_fbc], fbc set to per-chip default [ 604.231888] [drm:intel_update_fbc], fbc disabled per module param [ 604.231894] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 604.231902] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 604.231908] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 604.231921] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 604.231926] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 604.533540] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 604.534142] [drm:intel_dp_start_link_train], clock recovery OK [ 604.534147] [drm:ironlake_edp_panel_on], Turn eDP power on [ 604.534151] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 604.534156] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 604.534165] [drm:ironlake_wait_panel_on], Wait for panel power on [ 604.534170] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 604.875272] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 604.875289] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 604.926243] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 604.927203] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 604.927360] [drm:ironlake_edp_backlight_on], [ 604.968338] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 604.978343] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 604.978368] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 604.978376] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 604.978382] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 604.978390] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 604.978396] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 604.978403] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 604.978410] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 604.978416] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 604.978423] [drm:check_crtc_state], [CRTC:3] [ 604.978437] [drm:check_crtc_state], [CRTC:5] [ 604.978443] [drm:check_shared_dpll_state], PCH DPLL A [ 604.978453] [drm:check_shared_dpll_state], PCH DPLL B [ 604.993960] [drm:intel_update_fbc], fbc set to per-chip default [ 604.993971] [drm:intel_update_fbc], fbc disabled per module param [ 612.288205] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] [ 612.288226] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 612.288231] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 612.288237] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 612.288242] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 612.288250] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 612.288262] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 612.288269] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 612.288281] [drm:ironlake_edp_backlight_off], [ 612.489175] [drm:ironlake_edp_panel_off], Turn eDP power off [ 612.489184] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 612.489190] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 613.329482] [drm:intel_dp_link_down], [ 613.381512] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 613.432750] [drm:intel_update_fbc], no output, disabling [ 613.432776] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 613.432782] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 613.432788] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 613.432793] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 613.432799] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 613.432806] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 613.432812] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 613.432817] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 613.432823] [drm:check_crtc_state], [CRTC:3] [ 613.432828] [drm:check_crtc_state], [CRTC:5] [ 613.432834] [drm:check_shared_dpll_state], PCH DPLL A [ 613.432842] [drm:check_shared_dpll_state], PCH DPLL B [ 613.434789] [drm:drm_mode_addfb2], could not create framebuffer [ 613.434854] [drm:drm_mode_addfb2], [FB:32] [ 613.434867] [drm:drm_mode_addfb2], [FB:33] [ 613.434875] [drm:drm_mode_setcrtc], [CRTC:3] [ 613.434883] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 613.434888] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0) [ 613.434896] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 613.434963] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 613.434966] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 613.434974] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 613.434989] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 613.435042] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 613.435048] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18 [ 613.435054] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 613.435061] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 613.435067] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 613.435074] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1 [ 613.435080] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A [ 613.435086] [drm:intel_dump_pipe_config], cpu_transcoder: A [ 613.435091] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 613.435096] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 613.435103] [drm:intel_dump_pipe_config], requested mode: [ 613.435108] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 613.435116] [drm:intel_dump_pipe_config], adjusted mode: [ 613.435121] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 613.435129] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 613.435136] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 613.435141] [drm:intel_dump_pipe_config], ips: 0 [ 613.446220] [drm:ironlake_update_plane], Writing base 0085A000 00000000 0 0 5504 [ 613.446239] [drm:intel_update_fbc], no output, disabling [ 613.446250] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 613.446258] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 613.446264] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 613.446773] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 613.446783] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6 [ 613.446790] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6 [ 613.446800] [drm:ironlake_edp_pll_on], [ 613.498587] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 613.550619] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 613.550630] [drm:intel_update_fbc], fbc set to per-chip default [ 613.550635] [drm:intel_update_fbc], fbc disabled per module param [ 613.550641] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 613.550648] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 613.550655] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 613.550669] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 613.550675] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 613.852228] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 613.852824] [drm:intel_dp_start_link_train], clock recovery OK [ 613.852829] [drm:ironlake_edp_panel_on], Turn eDP power on [ 613.852834] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 613.852839] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 613.852848] [drm:ironlake_wait_panel_on], Wait for panel power on [ 613.852853] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 614.193963] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 614.193976] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 614.245014] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 614.245916] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 614.246071] [drm:ironlake_edp_backlight_on], [ 614.287080] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 614.297083] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 614.297110] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 614.297118] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 614.297124] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 614.297131] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 614.297138] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 614.297145] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 614.297152] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 614.297159] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 614.297166] [drm:check_crtc_state], [CRTC:3] [ 614.297180] [drm:check_crtc_state], [CRTC:5] [ 614.297186] [drm:check_shared_dpll_state], PCH DPLL A [ 614.297196] [drm:check_shared_dpll_state], PCH DPLL B [ 614.312740] [drm:intel_update_fbc], fbc set to per-chip default [ 614.312752] [drm:intel_update_fbc], fbc disabled per module param [ 621.377965] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] [ 621.377989] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 621.377994] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 621.377999] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 621.378005] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 621.378012] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 621.378025] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 621.378032] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 621.378042] [drm:ironlake_edp_backlight_off], [ 621.578730] [drm:ironlake_edp_panel_off], Turn eDP power off [ 621.578740] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 621.578745] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 622.447038] [drm:intel_dp_link_down], [ 622.499068] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 622.550387] [drm:intel_update_fbc], no output, disabling [ 622.550407] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 622.550411] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 622.550414] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 622.550418] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 622.550421] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 622.550425] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 622.550429] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 622.550433] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 622.550437] [drm:check_crtc_state], [CRTC:3] [ 622.550440] [drm:check_crtc_state], [CRTC:5] [ 622.550443] [drm:check_shared_dpll_state], PCH DPLL A [ 622.550449] [drm:check_shared_dpll_state], PCH DPLL B [ 622.553163] [drm:drm_mode_addfb2], [FB:32] [ 622.553171] [drm:drm_mode_addfb2], [FB:33] [ 622.553176] [drm:drm_mode_setcrtc], [CRTC:3] [ 622.553180] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 622.553183] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0) [ 622.553187] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 622.553190] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 622.553192] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 622.553255] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 622.553263] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 622.553267] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 622.553269] [drm:connected_sink_compute_bpp], clamping display bpp (was 30) to EDID reported max of 18 [ 622.553273] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 622.553280] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 622.553283] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 622.553285] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 18, dithering: 1 [ 622.553288] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A [ 622.553291] [drm:intel_dump_pipe_config], cpu_transcoder: A [ 622.553293] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 622.553296] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 622.553299] [drm:intel_dump_pipe_config], requested mode: [ 622.553302] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 622.553305] [drm:intel_dump_pipe_config], adjusted mode: [ 622.553307] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 622.553311] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 622.553314] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 622.553316] [drm:intel_dump_pipe_config], ips: 0 [ 622.562616] [drm:ironlake_update_plane], Writing base 0085A000 00000000 0 0 5504 [ 622.562628] [drm:intel_update_fbc], no output, disabling [ 622.562636] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 622.562641] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 622.562644] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 622.563149] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 622.563157] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6 [ 622.563162] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6 [ 622.563172] [drm:ironlake_edp_pll_on], [ 622.615203] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 622.667169] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 622.667181] [drm:intel_update_fbc], fbc set to per-chip default [ 622.667187] [drm:intel_update_fbc], fbc disabled per module param [ 622.667193] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 622.667201] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 622.667207] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 622.667221] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 622.667227] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 622.968851] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 622.969448] [drm:intel_dp_start_link_train], clock recovery OK [ 622.969455] [drm:ironlake_edp_panel_on], Turn eDP power on [ 622.969459] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 622.969464] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 622.969473] [drm:ironlake_wait_panel_on], Wait for panel power on [ 622.969479] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 623.310564] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 623.310576] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 623.361594] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 623.362490] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 623.362643] [drm:ironlake_edp_backlight_on], [ 623.403699] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 623.413706] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 623.413734] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 623.413742] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 623.413748] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 623.413755] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 623.413761] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 623.413767] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 623.413774] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 623.413780] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 623.413788] [drm:check_crtc_state], [CRTC:3] [ 623.413802] [drm:check_crtc_state], [CRTC:5] [ 623.413809] [drm:check_shared_dpll_state], PCH DPLL A [ 623.413820] [drm:check_shared_dpll_state], PCH DPLL B [ 623.429315] [drm:intel_update_fbc], fbc set to per-chip default [ 623.429327] [drm:intel_update_fbc], fbc disabled per module param [ 630.961874] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] [ 630.961892] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 630.961897] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 630.961903] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 630.961908] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 630.961915] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 630.961927] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 630.961934] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 630.961943] [drm:ironlake_edp_backlight_off], [ 631.162677] [drm:ironlake_edp_panel_off], Turn eDP power off [ 631.162687] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 631.162692] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 631.947960] [drm:intel_dp_link_down], [ 631.999988] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 632.051228] [drm:intel_update_fbc], no output, disabling [ 632.051254] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 632.051261] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 632.051266] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 632.051272] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 632.051278] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 632.051284] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 632.051290] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 632.051296] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 632.051301] [drm:check_crtc_state], [CRTC:3] [ 632.051306] [drm:check_crtc_state], [CRTC:5] [ 632.051311] [drm:check_shared_dpll_state], PCH DPLL A [ 632.051319] [drm:check_shared_dpll_state], PCH DPLL B [ 632.055334] [drm:drm_mode_addfb2], [FB:32] [ 632.055356] [drm:drm_mode_addfb2], [FB:33] [ 632.055367] [drm:drm_mode_setcrtc], [CRTC:3] [ 632.055379] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 632.055387] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0) [ 632.055474] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 632.055481] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 632.055486] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 632.055492] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 632.055498] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 632.055505] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 632.055511] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18 [ 632.055517] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 632.055524] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 632.055530] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 632.055537] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1 [ 632.055581] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A [ 632.055589] [drm:intel_dump_pipe_config], cpu_transcoder: A [ 632.055596] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 632.055604] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 632.055611] [drm:intel_dump_pipe_config], requested mode: [ 632.055616] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 632.055625] [drm:intel_dump_pipe_config], adjusted mode: [ 632.055630] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 632.055638] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 632.055644] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 632.055650] [drm:intel_dump_pipe_config], ips: 0 [ 632.066986] [drm:ironlake_update_plane], Writing base 0085A000 00000000 0 0 5504 [ 632.067005] [drm:intel_update_fbc], no output, disabling [ 632.067017] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 632.067025] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 632.067031] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 632.067540] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6 [ 632.067550] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6 [ 632.067557] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6 [ 632.067567] [drm:ironlake_edp_pll_on], [ 632.119060] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 632.171089] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 632.171101] [drm:intel_update_fbc], fbc set to per-chip default [ 632.171106] [drm:intel_update_fbc], fbc disabled per module param [ 632.171112] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 632.171119] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 632.171126] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 632.171139] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 632.171145] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 632.472712] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 632.473315] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 632.473906] [drm:intel_dp_start_link_train], clock recovery OK [ 632.473910] [drm:ironlake_edp_panel_on], Turn eDP power on [ 632.473914] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 632.473919] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 632.473928] [drm:ironlake_wait_panel_on], Wait for panel power on [ 632.473933] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 632.825500] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 632.825516] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 632.876532] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 632.877489] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 632.877660] [drm:ironlake_edp_backlight_on], [ 632.918502] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 632.928502] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 632.928528] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 632.928537] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 632.928545] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 632.928554] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 632.928563] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 632.928571] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 632.928580] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 632.928588] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 632.928598] [drm:check_crtc_state], [CRTC:3] [ 632.928613] [drm:check_crtc_state], [CRTC:5] [ 632.928620] [drm:check_shared_dpll_state], PCH DPLL A [ 632.928631] [drm:check_shared_dpll_state], PCH DPLL B [ 632.944315] [drm:intel_update_fbc], fbc set to per-chip default [ 632.944327] [drm:intel_update_fbc], fbc disabled per module param [ 640.091056] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] [ 640.091074] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 640.091079] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 640.091084] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 640.091090] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 640.091098] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 640.091109] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 640.091116] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 640.091125] [drm:ironlake_edp_backlight_off], [ 640.292312] [drm:ironlake_edp_panel_off], Turn eDP power off [ 640.292321] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 640.292327] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 641.161635] [drm:intel_dp_link_down], [ 641.213670] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 641.264906] [drm:intel_update_fbc], no output, disabling [ 641.264926] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 641.264930] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 641.264933] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 641.264937] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 641.264941] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 641.264944] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 641.264948] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 641.264952] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 641.264955] [drm:check_crtc_state], [CRTC:3] [ 641.264958] [drm:check_crtc_state], [CRTC:5] [ 641.264961] [drm:check_shared_dpll_state], PCH DPLL A [ 641.264968] [drm:check_shared_dpll_state], PCH DPLL B [ 641.267674] [drm:drm_mode_addfb2], [FB:32] [ 641.267686] [drm:drm_mode_addfb2], [FB:33] [ 641.267691] [drm:drm_mode_setcrtc], [CRTC:3] [ 641.267695] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 641.267698] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0) [ 641.267702] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 641.267705] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 641.267708] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 641.267772] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 641.267776] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 641.267779] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 641.267783] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 641.267791] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 641.267795] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 641.267802] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 641.267805] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 641.267808] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 641.267811] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0 [ 641.267814] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A [ 641.267817] [drm:intel_dump_pipe_config], cpu_transcoder: A [ 641.267819] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0 [ 641.267821] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 641.267824] [drm:intel_dump_pipe_config], requested mode: [ 641.267826] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 641.267830] [drm:intel_dump_pipe_config], adjusted mode: [ 641.267832] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 641.267836] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 641.267839] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 641.267842] [drm:intel_dump_pipe_config], ips: 0 [ 641.274066] [drm:ironlake_update_plane], Writing base 0085A000 00000000 0 0 2752 [ 641.274076] [drm:intel_update_fbc], no output, disabling [ 641.274081] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 641.274086] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 641.274089] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 641.274594] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 3, cursor: 4 [ 641.274599] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 4 [ 641.274603] [drm:ironlake_check_srwm], watermark 2: display plane 27, fbc lines 3, cursor 4 [ 641.274608] [drm:ironlake_edp_pll_on], [ 641.326740] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 641.378768] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 641.378779] [drm:intel_update_fbc], fbc set to per-chip default [ 641.378784] [drm:intel_update_fbc], fbc disabled per module param [ 641.378790] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 641.378797] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 641.378805] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 641.378817] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 641.378823] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 641.680390] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 641.680985] [drm:intel_dp_start_link_train], clock recovery OK [ 641.680990] [drm:ironlake_edp_panel_on], Turn eDP power on [ 641.680994] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 641.680999] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 641.681009] [drm:ironlake_wait_panel_on], Wait for panel power on [ 641.681014] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 642.022168] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 642.022185] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 642.073197] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 642.074147] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 642.074304] [drm:ironlake_edp_backlight_on], [ 642.115159] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 642.125159] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 642.125175] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 642.125180] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 642.125184] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 642.125189] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 642.125194] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 642.125198] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 642.125203] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 642.125208] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 642.125212] [drm:check_crtc_state], [CRTC:3] [ 642.125223] [drm:check_crtc_state], [CRTC:5] [ 642.125226] [drm:check_shared_dpll_state], PCH DPLL A [ 642.125233] [drm:check_shared_dpll_state], PCH DPLL B [ 642.140895] [drm:intel_update_fbc], fbc set to per-chip default [ 642.140900] [drm:intel_update_fbc], fbc disabled per module param [ 643.336285] [drm:ironlake_irq_handler], Pipe A FIFO underrun [ 650.448583] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] [ 650.448601] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 650.448608] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 650.448616] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 650.448624] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 650.448633] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 650.448649] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 650.448659] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 650.448670] [drm:ironlake_edp_backlight_off], [ 650.649684] [drm:ironlake_edp_panel_off], Turn eDP power off [ 650.649694] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 650.649699] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 651.475993] [drm:intel_dp_link_down], [ 651.528027] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 651.579264] [drm:intel_update_fbc], no output, disabling [ 651.579288] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 651.579295] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 651.579300] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 651.579306] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 651.579313] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 651.579318] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 651.579324] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 651.579330] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 651.579336] [drm:check_crtc_state], [CRTC:3] [ 651.579341] [drm:check_crtc_state], [CRTC:5] [ 651.579347] [drm:check_shared_dpll_state], PCH DPLL A [ 651.579355] [drm:check_shared_dpll_state], PCH DPLL B [ 651.581347] [drm:drm_mode_addfb2], could not create framebuffer [ 651.581405] [drm:drm_mode_addfb2], [FB:32] [ 651.581425] [drm:drm_mode_addfb2], [FB:33] [ 651.581433] [drm:drm_mode_setcrtc], [CRTC:3] [ 651.581441] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 651.581447] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0) [ 651.581454] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 651.581459] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 651.581465] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 651.581538] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 651.581556] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 651.581564] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 651.581570] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18 [ 651.581577] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 651.581584] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 651.581590] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 651.581596] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1 [ 651.581602] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A [ 651.581608] [drm:intel_dump_pipe_config], cpu_transcoder: A [ 651.581613] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 651.581619] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 651.581626] [drm:intel_dump_pipe_config], requested mode: [ 651.581631] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 651.581640] [drm:intel_dump_pipe_config], adjusted mode: [ 651.581645] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 651.581653] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 651.581659] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 651.581664] [drm:intel_dump_pipe_config], ips: 0 [ 651.592888] [drm:ironlake_update_plane], Writing base 01881000 00000000 0 0 5504 [ 651.592906] [drm:intel_update_fbc], no output, disabling [ 651.592917] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 651.592925] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 651.592931] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 651.593441] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6 [ 651.593451] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 651.593458] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6 [ 651.593469] [drm:ironlake_edp_pll_on], [ 651.645095] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 651.697127] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 651.697138] [drm:intel_update_fbc], fbc set to per-chip default [ 651.697143] [drm:intel_update_fbc], fbc disabled per module param [ 651.697149] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 651.697157] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 651.697164] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 651.697176] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 651.697182] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 651.998750] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 651.999347] [drm:intel_dp_start_link_train], clock recovery OK [ 651.999352] [drm:ironlake_edp_panel_on], Turn eDP power on [ 651.999357] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 651.999362] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 651.999371] [drm:ironlake_wait_panel_on], Wait for panel power on [ 651.999376] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 652.340535] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 652.340554] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 652.391565] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 652.392472] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 652.392634] [drm:ironlake_edp_backlight_on], [ 652.393331] [drm:ironlake_irq_handler], Pipe A FIFO underrun [ 652.433592] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 652.443598] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 652.443625] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 652.443633] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 652.443640] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 652.443647] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 652.443654] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 652.443661] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 652.443668] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 652.443674] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 652.443681] [drm:check_crtc_state], [CRTC:3] [ 652.443694] [drm:check_crtc_state], [CRTC:5] [ 652.443702] [drm:check_shared_dpll_state], PCH DPLL A [ 652.443711] [drm:check_shared_dpll_state], PCH DPLL B [ 652.459301] [drm:intel_update_fbc], fbc set to per-chip default [ 652.459313] [drm:intel_update_fbc], fbc disabled per module param [ 659.524565] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] [ 659.524585] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 659.524590] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 659.524595] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 659.524600] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 659.524608] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 659.524620] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 659.524629] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 659.524637] [drm:ironlake_edp_backlight_off], [ 659.725290] [drm:ironlake_edp_panel_off], Turn eDP power off [ 659.725300] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 659.725305] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 660.561595] [drm:intel_dp_link_down], [ 660.613626] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 660.664878] [drm:intel_update_fbc], no output, disabling [ 660.664898] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 660.664902] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 660.664905] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 660.664909] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 660.664913] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 660.664917] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 660.664920] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 660.664924] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 660.664928] [drm:check_crtc_state], [CRTC:3] [ 660.664931] [drm:check_crtc_state], [CRTC:5] [ 660.664934] [drm:check_shared_dpll_state], PCH DPLL A [ 660.664940] [drm:check_shared_dpll_state], PCH DPLL B [ 660.667569] [drm:drm_mode_addfb2], [FB:32] [ 660.667595] [drm:drm_mode_addfb2], [FB:33] [ 660.667600] [drm:drm_mode_setcrtc], [CRTC:3] [ 660.667606] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 660.667610] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0) [ 660.667618] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 660.667683] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 660.667686] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 660.667689] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 660.667699] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 660.667702] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 660.667705] [drm:connected_sink_compute_bpp], clamping display bpp (was 30) to EDID reported max of 18 [ 660.667709] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 660.667713] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 660.667716] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 660.667722] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 18, dithering: 1 [ 660.667726] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A [ 660.667728] [drm:intel_dump_pipe_config], cpu_transcoder: A [ 660.667731] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 660.667734] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 660.667737] [drm:intel_dump_pipe_config], requested mode: [ 660.667740] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 660.667744] [drm:intel_dump_pipe_config], adjusted mode: [ 660.667746] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 660.667749] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 660.667752] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 660.667754] [drm:intel_dump_pipe_config], ips: 0 [ 660.677313] [drm:ironlake_update_plane], Writing base 01881000 00000000 0 0 5504 [ 660.677326] [drm:intel_update_fbc], no output, disabling [ 660.677333] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 660.677338] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 660.677341] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 660.677848] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6 [ 660.677854] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 660.677858] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6 [ 660.677864] [drm:ironlake_edp_pll_on], [ 660.729695] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 660.781726] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 660.781737] [drm:intel_update_fbc], fbc set to per-chip default [ 660.781742] [drm:intel_update_fbc], fbc disabled per module param [ 660.781748] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 660.781755] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 660.781762] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 660.781774] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 660.781780] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 661.083345] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 661.083945] [drm:intel_dp_start_link_train], clock recovery OK [ 661.083950] [drm:ironlake_edp_panel_on], Turn eDP power on [ 661.083954] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 661.083959] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 661.083969] [drm:ironlake_wait_panel_on], Wait for panel power on [ 661.083974] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 661.425131] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 661.425150] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 661.476163] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 661.477094] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 661.477251] [drm:ironlake_edp_backlight_on], [ 661.477948] [drm:ironlake_irq_handler], Pipe A FIFO underrun [ 661.518193] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 661.528154] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 661.528181] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 661.528189] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 661.528195] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 661.528203] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 661.528212] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 661.528219] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 661.528225] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 661.528232] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 661.528239] [drm:check_crtc_state], [CRTC:3] [ 661.528252] [drm:check_crtc_state], [CRTC:5] [ 661.528259] [drm:check_shared_dpll_state], PCH DPLL A [ 661.528268] [drm:check_shared_dpll_state], PCH DPLL B [ 661.543960] [drm:intel_update_fbc], fbc set to per-chip default [ 661.543970] [drm:intel_update_fbc], fbc disabled per module param [ 669.509289] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] [ 669.509309] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 669.509315] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 669.509320] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 669.509325] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 669.509332] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 669.509344] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 669.509352] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 669.509361] [drm:ironlake_edp_backlight_off], [ 669.710444] [drm:ironlake_edp_panel_off], Turn eDP power off [ 669.710453] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 669.710459] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 670.561694] [drm:intel_dp_link_down], [ 670.613725] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 670.664965] [drm:intel_update_fbc], no output, disabling [ 670.664985] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 670.664989] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 670.664993] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 670.664998] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 670.665002] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 670.665007] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 670.665012] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 670.665016] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 670.665020] [drm:check_crtc_state], [CRTC:3] [ 670.665024] [drm:check_crtc_state], [CRTC:5] [ 670.665028] [drm:check_shared_dpll_state], PCH DPLL A [ 670.665036] [drm:check_shared_dpll_state], PCH DPLL B [ 670.667699] [drm:drm_mode_addfb2], [FB:32] [ 670.667707] [drm:drm_mode_addfb2], [FB:33] [ 670.667711] [drm:drm_mode_setcrtc], [CRTC:3] [ 670.667715] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 670.667718] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0) [ 670.667722] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 670.667725] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 670.667813] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3] [ 670.667822] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 670.667828] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 670.667832] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 670.667835] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18 [ 670.667838] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 670.667842] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 670.667845] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 670.667848] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1 [ 670.667851] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A [ 670.667854] [drm:intel_dump_pipe_config], cpu_transcoder: A [ 670.667856] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 670.667859] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 670.667862] [drm:intel_dump_pipe_config], requested mode: [ 670.667866] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 670.667869] [drm:intel_dump_pipe_config], adjusted mode: [ 670.667872] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 670.667876] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 670.667879] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 670.667881] [drm:intel_dump_pipe_config], ips: 0 [ 670.677382] [drm:ironlake_update_plane], Writing base 01881000 00000000 0 0 5504 [ 670.677396] [drm:intel_update_fbc], no output, disabling [ 670.677403] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 670.677408] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 670.677411] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 670.677917] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6 [ 670.677925] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 670.677929] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6 [ 670.677936] [drm:ironlake_edp_pll_on], [ 670.729854] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 670.781887] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 670.781898] [drm:intel_update_fbc], fbc set to per-chip default [ 670.781903] [drm:intel_update_fbc], fbc disabled per module param [ 670.781909] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 670.781917] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 670.781923] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 670.781939] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 670.781945] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 671.083499] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 671.084098] [drm:intel_dp_start_link_train], clock recovery OK [ 671.084103] [drm:ironlake_edp_panel_on], Turn eDP power on [ 671.084108] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 671.084113] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 671.084122] [drm:ironlake_wait_panel_on], Wait for panel power on [ 671.084127] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 671.425290] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 671.425307] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 671.476320] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 671.477273] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 671.477431] [drm:ironlake_edp_backlight_on], [ 671.518294] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 671.528311] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 671.528339] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 671.528347] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 671.528354] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 671.528361] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 671.528368] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 671.528375] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 671.528382] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 671.528388] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 671.528396] [drm:check_crtc_state], [CRTC:3] [ 671.528410] [drm:check_crtc_state], [CRTC:5] [ 671.528417] [drm:check_shared_dpll_state], PCH DPLL A [ 671.528427] [drm:check_shared_dpll_state], PCH DPLL B [ 671.544129] [drm:intel_update_fbc], fbc set to per-chip default [ 671.544139] [drm:intel_update_fbc], fbc disabled per module param [ 673.345248] [drm:ironlake_irq_handler], Pipe A FIFO underrun [ 678.690622] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] [ 678.690642] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 678.690647] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 678.690652] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 678.690657] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 678.690665] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 678.690677] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 678.690687] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 678.690707] [drm:ironlake_edp_backlight_off], [ 678.892009] [drm:ironlake_edp_panel_off], Turn eDP power off [ 678.892019] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 678.892024] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 679.761426] [drm:intel_dp_link_down], [ 679.813430] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 679.864663] [drm:intel_update_fbc], no output, disabling [ 679.864689] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 679.864697] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 679.864703] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 679.864710] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 679.864717] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 679.864724] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 679.864731] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 679.864737] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 679.864745] [drm:check_crtc_state], [CRTC:3] [ 679.864751] [drm:check_crtc_state], [CRTC:5] [ 679.864757] [drm:check_shared_dpll_state], PCH DPLL A [ 679.864766] [drm:check_shared_dpll_state], PCH DPLL B [ 679.868968] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8] [ 679.868981] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8] [ 679.868992] [drm:drm_mode_getconnector], [CONNECTOR:10:?] [ 679.868999] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] [ 679.869005] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 679.869013] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 679.869020] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 679.869033] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 679.869039] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 680.169896] [drm:intel_dp_probe_oui], Sink OUI: 001cf8 [ 680.170069] [drm:intel_dp_probe_oui], Branch OUI: 000000 [ 680.170076] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 680.170089] [drm:drm_edid_to_eld], ELD: no CEA Extension found [ 680.170095] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes : [ 680.170099] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 680.170105] [drm:drm_mode_debug_printmodeline], Modeline 12:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 680.170113] [drm:drm_mode_getconnector], [CONNECTOR:10:?] [ 680.170121] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8] [ 680.170126] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8] [ 680.170166] [drm:drm_mode_addfb2], [FB:32] [ 680.170174] [drm:drm_mode_addfb2], [FB:33] [ 680.170178] [drm:drm_mode_setcrtc], [CRTC:5] [ 680.170182] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 680.170186] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0) [ 680.170191] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 680.170194] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 680.170261] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [ 680.170266] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 680.170271] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 680.170275] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5] [ 680.170279] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 680.170289] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 680.170294] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 680.170298] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 680.170302] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 680.170306] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 680.170310] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0 [ 680.170314] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B [ 680.170317] [drm:intel_dump_pipe_config], cpu_transcoder: B [ 680.170321] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0 [ 680.170326] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 680.170330] [drm:intel_dump_pipe_config], requested mode: [ 680.170333] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 680.170338] [drm:intel_dump_pipe_config], adjusted mode: [ 680.170341] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 680.170346] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 680.170350] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 680.170353] [drm:intel_dump_pipe_config], ips: 0 [ 680.177194] [drm:ironlake_update_plane], Writing base 01881000 00000000 0 0 2752 [ 680.177211] [drm:intel_update_fbc], no output, disabling [ 680.177222] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 680.177230] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 680.177238] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 680.177748] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 4, cursor: 4 [ 680.177758] [drm:ironlake_check_srwm], watermark 1: display plane 13, fbc lines 3, cursor 4 [ 680.177767] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 4 [ 680.177779] [drm:ironlake_edp_pll_on], [ 680.229649] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 680.281681] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 680.281692] [drm:intel_update_fbc], fbc set to per-chip default [ 680.281698] [drm:intel_update_fbc], fbc disabled per module param [ 680.281706] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 680.281713] [drm:ironlake_edp_panel_vdd_on], eDP VDD already on [ 680.282165] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 680.282761] [drm:intel_dp_start_link_train], clock recovery OK [ 680.282766] [drm:ironlake_edp_panel_on], Turn eDP power on [ 680.282770] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 680.282775] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 680.282785] [drm:ironlake_wait_panel_on], Wait for panel power on [ 680.282790] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 680.623898] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 680.623915] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 680.674931] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 680.675897] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 680.676054] [drm:ironlake_edp_backlight_on], [ 680.717017] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 680.727045] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 680.727069] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 680.727077] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 680.727083] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 680.727090] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 680.727097] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 680.727104] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 680.727110] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 680.727117] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 680.727124] [drm:check_crtc_state], [CRTC:3] [ 680.727130] [drm:check_crtc_state], [CRTC:5] [ 680.727144] [drm:check_shared_dpll_state], PCH DPLL A [ 680.727153] [drm:check_shared_dpll_state], PCH DPLL B [ 680.742727] [drm:intel_update_fbc], fbc set to per-chip default [ 680.742737] [drm:intel_update_fbc], fbc disabled per module param [ 689.050366] [drm:intel_crtc_set_config], [CRTC:5] [NOFB] [ 689.050384] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 689.050390] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 689.050395] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 689.050400] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2 [ 689.050408] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 689.050420] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 689.050430] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 689.050436] [drm:ironlake_edp_backlight_off], [ 689.251458] [drm:ironlake_edp_panel_off], Turn eDP power off [ 689.251468] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 689.251474] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 690.076784] [drm:intel_dp_link_down], [ 690.128818] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 690.180850] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 690.232088] [drm:intel_update_fbc], no output, disabling [ 690.232113] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 690.232121] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 690.232126] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 690.232132] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 690.232138] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 690.232145] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 690.232150] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 690.232156] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 690.232162] [drm:check_crtc_state], [CRTC:3] [ 690.232167] [drm:check_crtc_state], [CRTC:5] [ 690.232172] [drm:check_shared_dpll_state], PCH DPLL A [ 690.232180] [drm:check_shared_dpll_state], PCH DPLL B [ 690.234175] [drm:drm_mode_addfb2], could not create framebuffer [ 690.234232] [drm:drm_mode_addfb2], [FB:32] [ 690.234243] [drm:drm_mode_addfb2], [FB:33] [ 690.234323] [drm:drm_mode_setcrtc], [CRTC:5] [ 690.234328] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 690.234331] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0) [ 690.234335] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 690.234338] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 690.234341] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5] [ 690.234350] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 690.234356] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 690.234364] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 690.234370] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18 [ 690.234376] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 690.234383] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 690.234390] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 690.234396] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1 [ 690.234402] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B [ 690.234408] [drm:intel_dump_pipe_config], cpu_transcoder: B [ 690.234413] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 690.234419] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 690.234426] [drm:intel_dump_pipe_config], requested mode: [ 690.234431] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 690.234439] [drm:intel_dump_pipe_config], adjusted mode: [ 690.234444] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 690.234452] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 690.234459] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 690.234464] [drm:intel_dump_pipe_config], ips: 0 [ 690.245495] [drm:ironlake_update_plane], Writing base 028A8000 00000000 0 0 5504 [ 690.245513] [drm:intel_update_fbc], no output, disabling [ 690.245523] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 690.245531] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 690.245537] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 690.246046] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 6, cursor: 6 [ 690.246055] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6 [ 690.246063] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6 [ 690.246073] [drm:ironlake_edp_pll_on], [ 690.297919] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 690.349947] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 690.349958] [drm:intel_update_fbc], fbc set to per-chip default [ 690.349963] [drm:intel_update_fbc], fbc disabled per module param [ 690.349969] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 690.349976] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 690.349982] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 690.349996] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 690.350001] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 690.651571] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 690.652171] [drm:intel_dp_start_link_train], clock recovery OK [ 690.652177] [drm:ironlake_edp_panel_on], Turn eDP power on [ 690.652181] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 690.652186] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 690.652196] [drm:ironlake_wait_panel_on], Wait for panel power on [ 690.652201] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 690.993350] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 690.993367] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 691.044380] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 691.045327] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 691.045500] [drm:ironlake_edp_backlight_on], [ 691.086407] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 691.096388] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 691.096417] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 691.096425] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 691.096431] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 691.096438] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 691.096445] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 691.096452] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 691.096460] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 691.096467] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 691.096474] [drm:check_crtc_state], [CRTC:3] [ 691.096480] [drm:check_crtc_state], [CRTC:5] [ 691.096494] [drm:check_shared_dpll_state], PCH DPLL A [ 691.096504] [drm:check_shared_dpll_state], PCH DPLL B [ 691.112149] [drm:intel_update_fbc], fbc set to per-chip default [ 691.112159] [drm:intel_update_fbc], fbc disabled per module param [ 698.258682] [drm:intel_crtc_set_config], [CRTC:5] [NOFB] [ 698.258701] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 698.258707] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 698.258712] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 698.258717] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2 [ 698.258724] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 698.258736] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 698.258773] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 698.258791] [drm:ironlake_edp_backlight_off], [ 698.460162] [drm:ironlake_edp_panel_off], Turn eDP power off [ 698.460172] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 698.460177] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 699.296470] [drm:intel_dp_link_down], [ 699.348497] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 699.400532] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 699.451788] [drm:intel_update_fbc], no output, disabling [ 699.451814] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 699.451820] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 699.451826] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 699.451832] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 699.451838] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 699.451844] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 699.451850] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 699.451856] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 699.451862] [drm:check_crtc_state], [CRTC:3] [ 699.451867] [drm:check_crtc_state], [CRTC:5] [ 699.451872] [drm:check_shared_dpll_state], PCH DPLL A [ 699.451881] [drm:check_shared_dpll_state], PCH DPLL B [ 699.455913] [drm:drm_mode_addfb2], [FB:32] [ 699.455928] [drm:drm_mode_addfb2], [FB:33] [ 699.455936] [drm:drm_mode_setcrtc], [CRTC:5] [ 699.455944] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 699.455949] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0) [ 699.455959] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 699.455964] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 699.455970] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5] [ 699.455976] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 699.456055] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 699.456063] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 699.456068] [drm:connected_sink_compute_bpp], clamping display bpp (was 30) to EDID reported max of 18 [ 699.456075] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 699.456082] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 699.456088] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 699.456094] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 18, dithering: 1 [ 699.456100] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B [ 699.456106] [drm:intel_dump_pipe_config], cpu_transcoder: B [ 699.456111] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 699.456116] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 699.456123] [drm:intel_dump_pipe_config], requested mode: [ 699.456128] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 699.456137] [drm:intel_dump_pipe_config], adjusted mode: [ 699.456142] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 699.456150] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 699.456156] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 699.456162] [drm:intel_dump_pipe_config], ips: 0 [ 699.467481] [drm:ironlake_update_plane], Writing base 028A8000 00000000 0 0 5504 [ 699.467560] [drm:intel_update_fbc], no output, disabling [ 699.467571] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 699.467588] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 699.467594] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 699.468103] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 6, cursor: 6 [ 699.468112] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6 [ 699.468121] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6 [ 699.468132] [drm:ironlake_edp_pll_on], [ 699.519602] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 699.571634] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 699.571646] [drm:intel_update_fbc], fbc set to per-chip default [ 699.571650] [drm:intel_update_fbc], fbc disabled per module param [ 699.571656] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 699.571664] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 699.571670] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 699.571683] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 699.571688] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 699.873237] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 699.873838] [drm:intel_dp_start_link_train], clock recovery OK [ 699.873843] [drm:ironlake_edp_panel_on], Turn eDP power on [ 699.873847] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 699.873853] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 699.873863] [drm:ironlake_wait_panel_on], Wait for panel power on [ 699.873868] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 700.214963] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 700.214975] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 700.266077] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 700.266996] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 700.267152] [drm:ironlake_edp_backlight_on], [ 700.308036] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 700.318035] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 700.318061] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 700.318071] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 700.318081] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 700.318089] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 700.318098] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 700.318108] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 700.318116] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 700.318124] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 700.318133] [drm:check_crtc_state], [CRTC:3] [ 700.318141] [drm:check_crtc_state], [CRTC:5] [ 700.318157] [drm:check_shared_dpll_state], PCH DPLL A [ 700.318169] [drm:check_shared_dpll_state], PCH DPLL B [ 700.333755] [drm:intel_update_fbc], fbc set to per-chip default [ 700.333766] [drm:intel_update_fbc], fbc disabled per module param [ 708.300020] [drm:intel_crtc_set_config], [CRTC:5] [NOFB] [ 708.300040] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 708.300046] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 708.300052] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 708.300057] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2 [ 708.300064] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 708.300076] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 708.300086] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 708.300093] [drm:ironlake_edp_backlight_off], [ 708.501343] [drm:ironlake_edp_panel_off], Turn eDP power off [ 708.501353] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 708.501358] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 709.302637] [drm:intel_dp_link_down], [ 709.354668] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 709.406700] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 709.457934] [drm:intel_update_fbc], no output, disabling [ 709.457961] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 709.457967] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 709.457972] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 709.457978] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 709.457984] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 709.457990] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 709.457996] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 709.458003] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 709.458009] [drm:check_crtc_state], [CRTC:3] [ 709.458014] [drm:check_crtc_state], [CRTC:5] [ 709.458019] [drm:check_shared_dpll_state], PCH DPLL A [ 709.458027] [drm:check_shared_dpll_state], PCH DPLL B [ 709.462023] [drm:drm_mode_addfb2], [FB:32] [ 709.462038] [drm:drm_mode_addfb2], [FB:33] [ 709.462046] [drm:drm_mode_setcrtc], [CRTC:5] [ 709.462054] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 709.462060] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0) [ 709.462068] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 709.462073] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 709.462079] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5] [ 709.462085] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 709.462092] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 709.462173] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 709.462179] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18 [ 709.462186] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 709.462193] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 709.462199] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 709.462206] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1 [ 709.462212] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B [ 709.462218] [drm:intel_dump_pipe_config], cpu_transcoder: B [ 709.462223] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 709.462228] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 709.462236] [drm:intel_dump_pipe_config], requested mode: [ 709.462241] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 709.462250] [drm:intel_dump_pipe_config], adjusted mode: [ 709.462254] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 709.462263] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 709.462269] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 709.462274] [drm:intel_dump_pipe_config], ips: 0 [ 709.473501] [drm:ironlake_update_plane], Writing base 028A8000 00000000 0 0 5504 [ 709.473519] [drm:intel_update_fbc], no output, disabling [ 709.473530] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 709.473538] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 709.473544] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 709.474053] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 6, cursor: 6 [ 709.474062] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6 [ 709.474070] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6 [ 709.474081] [drm:ironlake_edp_pll_on], [ 709.525766] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 709.577798] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 709.577809] [drm:intel_update_fbc], fbc set to per-chip default [ 709.577814] [drm:intel_update_fbc], fbc disabled per module param [ 709.577820] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 709.577827] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 709.577833] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 709.577846] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 709.577851] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 709.879418] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 709.880016] [drm:intel_dp_start_link_train], clock recovery OK [ 709.880020] [drm:ironlake_edp_panel_on], Turn eDP power on [ 709.880025] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 709.880030] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 709.880039] [drm:ironlake_wait_panel_on], Wait for panel power on [ 709.880044] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 710.221131] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 710.221142] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 710.272172] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 710.273104] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 710.273257] [drm:ironlake_edp_backlight_on], [ 710.314192] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 710.324269] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 710.324296] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 710.324304] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 710.324311] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 710.324317] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 710.324325] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 710.324331] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 710.324339] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 710.324346] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 710.324353] [drm:check_crtc_state], [CRTC:3] [ 710.324360] [drm:check_crtc_state], [CRTC:5] [ 710.324373] [drm:check_shared_dpll_state], PCH DPLL A [ 710.324383] [drm:check_shared_dpll_state], PCH DPLL B [ 710.339861] [drm:intel_update_fbc], fbc set to per-chip default [ 710.339871] [drm:intel_update_fbc], fbc disabled per module param [ 717.486696] [drm:intel_crtc_set_config], [CRTC:5] [NOFB] [ 717.486716] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 717.486721] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 717.486726] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 717.486732] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2 [ 717.486739] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 717.486751] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 717.486759] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 717.486767] [drm:ironlake_edp_backlight_off], [ 717.688009] [drm:ironlake_edp_panel_off], Turn eDP power off [ 717.688019] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 717.688024] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 718.524320] [drm:intel_dp_link_down], [ 718.576350] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 718.628380] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 718.679616] [drm:intel_update_fbc], no output, disabling [ 718.679636] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 718.679640] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 718.679643] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 718.679647] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 718.679651] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 718.679655] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 718.679658] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 718.679662] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 718.679666] [drm:check_crtc_state], [CRTC:3] [ 718.679669] [drm:check_crtc_state], [CRTC:5] [ 718.679672] [drm:check_shared_dpll_state], PCH DPLL A [ 718.679679] [drm:check_shared_dpll_state], PCH DPLL B [ 718.682402] [drm:drm_mode_addfb2], [FB:32] [ 718.682411] [drm:drm_mode_addfb2], [FB:33] [ 718.682414] [drm:drm_mode_setcrtc], [CRTC:5] [ 718.682419] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 718.682421] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0) [ 718.682426] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 718.682428] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set [ 718.682492] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9 [ 718.682496] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 718.682500] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 718.682503] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5] [ 718.682510] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 718.682519] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 718.682523] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 718.682526] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 718.682529] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 718.682532] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 718.682535] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0 [ 718.682538] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B [ 718.682540] [drm:intel_dump_pipe_config], cpu_transcoder: B [ 718.682543] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0 [ 718.682545] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 718.682548] [drm:intel_dump_pipe_config], requested mode: [ 718.682551] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 718.682554] [drm:intel_dump_pipe_config], adjusted mode: [ 718.682557] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 718.682561] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 718.682564] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 718.682567] [drm:intel_dump_pipe_config], ips: 0 [ 718.688910] [drm:ironlake_update_plane], Writing base 028A8000 00000000 0 0 2752 [ 718.688919] [drm:intel_update_fbc], no output, disabling [ 718.688925] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 718.688929] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 718.688931] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 718.689436] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 3, cursor: 4 [ 718.689442] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 4 [ 718.689446] [drm:ironlake_check_srwm], watermark 2: display plane 27, fbc lines 3, cursor 4 [ 718.689453] [drm:ironlake_edp_pll_on], [ 718.741425] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 718.793495] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 718.793509] [drm:intel_update_fbc], fbc set to per-chip default [ 718.793515] [drm:intel_update_fbc], fbc disabled per module param [ 718.793522] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 718.793529] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 718.793536] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 718.793549] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 718.793556] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 719.095096] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 719.095690] [drm:intel_dp_start_link_train], clock recovery OK [ 719.095695] [drm:ironlake_edp_panel_on], Turn eDP power on [ 719.095699] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 719.095704] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 719.095714] [drm:ironlake_wait_panel_on], Wait for panel power on [ 719.095719] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 719.436820] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 719.436838] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 719.487852] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 719.488829] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 719.488998] [drm:ironlake_edp_backlight_on], [ 719.529882] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 719.539894] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 719.539926] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 719.539935] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 719.539943] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 719.539952] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 719.539960] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 719.539969] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 719.539978] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 719.539986] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 719.539995] [drm:check_crtc_state], [CRTC:3] [ 719.540003] [drm:check_crtc_state], [CRTC:5] [ 719.540018] [drm:check_shared_dpll_state], PCH DPLL A [ 719.540028] [drm:check_shared_dpll_state], PCH DPLL B [ 719.555665] [drm:intel_update_fbc], fbc set to per-chip default [ 719.555676] [drm:intel_update_fbc], fbc disabled per module param [ 719.840032] [drm:ironlake_irq_handler], Pipe B FIFO underrun [ 727.770256] [drm:intel_crtc_set_config], [CRTC:5] [NOFB] [ 727.770277] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 727.770285] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 727.770292] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 727.770299] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2 [ 727.770308] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 727.770323] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 727.770400] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 727.770409] [drm:ironlake_edp_backlight_off], [ 727.971358] [drm:ironlake_edp_panel_off], Turn eDP power off [ 727.971368] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 727.971373] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 728.839677] [drm:intel_dp_link_down], [ 728.891709] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 728.943739] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 728.994976] [drm:intel_update_fbc], no output, disabling [ 728.995002] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 728.995009] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 728.995014] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 728.995020] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 728.995026] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 728.995031] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 728.995038] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 728.995044] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 728.995050] [drm:check_crtc_state], [CRTC:3] [ 728.995055] [drm:check_crtc_state], [CRTC:5] [ 728.995060] [drm:check_shared_dpll_state], PCH DPLL A [ 728.995068] [drm:check_shared_dpll_state], PCH DPLL B [ 728.997061] [drm:drm_mode_addfb2], could not create framebuffer [ 728.997117] [drm:drm_mode_addfb2], [FB:32] [ 728.997130] [drm:drm_mode_addfb2], [FB:33] [ 728.997138] [drm:drm_mode_setcrtc], [CRTC:5] [ 728.997145] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 728.997151] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0) [ 728.997158] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 728.997164] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 728.997171] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5] [ 728.997177] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 728.997256] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 728.997324] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 728.997330] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18 [ 728.997336] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 728.997343] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 728.997349] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 728.997356] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1 [ 728.997362] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B [ 728.997368] [drm:intel_dump_pipe_config], cpu_transcoder: B [ 728.997373] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 728.997378] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 728.997385] [drm:intel_dump_pipe_config], requested mode: [ 728.997390] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 728.997399] [drm:intel_dump_pipe_config], adjusted mode: [ 728.997404] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 728.997413] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 728.997419] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 728.997424] [drm:intel_dump_pipe_config], ips: 0 [ 729.008896] [drm:ironlake_update_plane], Writing base 038CF000 00000000 0 0 5504 [ 729.008918] [drm:intel_update_fbc], no output, disabling [ 729.008929] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 729.008937] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 729.008943] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 729.009453] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 4, cursor: 6 [ 729.009461] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 729.009469] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6 [ 729.009479] [drm:ironlake_edp_pll_on], [ 729.061807] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 729.113842] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 729.113854] [drm:intel_update_fbc], fbc set to per-chip default [ 729.113858] [drm:intel_update_fbc], fbc disabled per module param [ 729.113864] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 729.113872] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 729.113879] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 729.113891] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 729.113897] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 729.415466] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 729.416066] [drm:intel_dp_start_link_train], clock recovery OK [ 729.416071] [drm:ironlake_edp_panel_on], Turn eDP power on [ 729.416075] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 729.416081] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 729.416090] [drm:ironlake_wait_panel_on], Wait for panel power on [ 729.416095] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 729.757180] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 729.757198] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 729.808275] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 729.809230] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 729.809389] [drm:ironlake_edp_backlight_on], [ 729.810083] [drm:ironlake_irq_handler], Pipe B FIFO underrun [ 729.850326] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 729.860308] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 729.860333] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 729.860339] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 729.860344] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 729.860350] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 729.860357] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 729.860362] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 729.860368] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 729.860374] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 729.860380] [drm:check_crtc_state], [CRTC:3] [ 729.860385] [drm:check_crtc_state], [CRTC:5] [ 729.860397] [drm:check_shared_dpll_state], PCH DPLL A [ 729.860406] [drm:check_shared_dpll_state], PCH DPLL B [ 729.876054] [drm:intel_update_fbc], fbc set to per-chip default [ 729.876064] [drm:intel_update_fbc], fbc disabled per module param [ 736.941220] [drm:intel_crtc_set_config], [CRTC:5] [NOFB] [ 736.941242] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 736.941250] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 736.941261] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 736.941268] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2 [ 736.941278] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 736.941292] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 736.941301] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 736.941313] [drm:ironlake_edp_backlight_off], [ 737.142024] [drm:ironlake_edp_panel_off], Turn eDP power off [ 737.142034] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 737.142039] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 737.944287] [drm:intel_dp_link_down], [ 737.996253] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 738.048353] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 738.099586] [drm:intel_update_fbc], no output, disabling [ 738.099606] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 738.099610] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 738.099613] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 738.099617] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 738.099621] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 738.099625] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 738.099629] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 738.099633] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 738.099637] [drm:check_crtc_state], [CRTC:3] [ 738.099640] [drm:check_crtc_state], [CRTC:5] [ 738.099643] [drm:check_shared_dpll_state], PCH DPLL A [ 738.099649] [drm:check_shared_dpll_state], PCH DPLL B [ 738.102379] [drm:drm_mode_addfb2], [FB:32] [ 738.102390] [drm:drm_mode_addfb2], [FB:33] [ 738.102395] [drm:drm_mode_setcrtc], [CRTC:5] [ 738.102399] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 738.102401] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0) [ 738.102405] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 738.102408] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 738.102411] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5] [ 738.102474] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 738.102482] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 738.102485] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 738.102488] [drm:connected_sink_compute_bpp], clamping display bpp (was 30) to EDID reported max of 18 [ 738.102495] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 738.102499] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 738.102501] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 738.102504] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 18, dithering: 1 [ 738.102507] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B [ 738.102510] [drm:intel_dump_pipe_config], cpu_transcoder: B [ 738.102512] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 738.102514] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 738.102518] [drm:intel_dump_pipe_config], requested mode: [ 738.102521] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 738.102524] [drm:intel_dump_pipe_config], adjusted mode: [ 738.102527] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 738.102530] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 738.102533] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 738.102535] [drm:intel_dump_pipe_config], ips: 0 [ 738.111861] [drm:ironlake_update_plane], Writing base 038CF000 00000000 0 0 5504 [ 738.111874] [drm:intel_update_fbc], no output, disabling [ 738.111881] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 738.111885] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 738.111888] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 738.112395] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 4, cursor: 6 [ 738.112402] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 738.112406] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6 [ 738.112413] [drm:ironlake_edp_pll_on], [ 738.164396] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 738.216463] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 738.216477] [drm:intel_update_fbc], fbc set to per-chip default [ 738.216482] [drm:intel_update_fbc], fbc disabled per module param [ 738.216489] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 738.216497] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 738.216505] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 738.216518] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 738.216525] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 738.518069] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 738.518666] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 738.519256] [drm:intel_dp_start_link_train], clock recovery OK [ 738.519261] [drm:ironlake_edp_panel_on], Turn eDP power on [ 738.519265] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 738.519271] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 738.519280] [drm:ironlake_wait_panel_on], Wait for panel power on [ 738.519285] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 738.870859] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 738.870877] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 738.921889] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 738.922844] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 738.923001] [drm:ironlake_edp_backlight_on], [ 738.923697] [drm:ironlake_irq_handler], Pipe B FIFO underrun [ 738.963931] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 738.973932] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 738.973958] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 738.973967] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 738.973973] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 738.973980] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 738.973986] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 738.973994] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 738.974000] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 738.974007] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 738.974014] [drm:check_crtc_state], [CRTC:3] [ 738.974021] [drm:check_crtc_state], [CRTC:5] [ 738.974034] [drm:check_shared_dpll_state], PCH DPLL A [ 738.974043] [drm:check_shared_dpll_state], PCH DPLL B [ 738.989602] [drm:intel_update_fbc], fbc set to per-chip default [ 738.989612] [drm:intel_update_fbc], fbc disabled per module param [ 747.523410] [drm:intel_crtc_set_config], [CRTC:5] [NOFB] [ 747.523429] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 747.523434] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 747.523439] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 747.523444] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2 [ 747.523452] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 747.523464] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 747.523472] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 747.523480] [drm:ironlake_edp_backlight_off], [ 747.724514] [drm:ironlake_edp_panel_off], Turn eDP power off [ 747.724525] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 747.724531] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000 [ 748.540818] [drm:intel_dp_link_down], [ 748.592848] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 748.644883] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 748.696118] [drm:intel_update_fbc], no output, disabling [ 748.696145] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 748.696151] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 748.696156] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 748.696162] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 748.696168] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 748.696174] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 748.696180] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 748.696186] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 748.696192] [drm:check_crtc_state], [CRTC:3] [ 748.696197] [drm:check_crtc_state], [CRTC:5] [ 748.696202] [drm:check_shared_dpll_state], PCH DPLL A [ 748.696211] [drm:check_shared_dpll_state], PCH DPLL B [ 748.700255] [drm:drm_mode_addfb2], [FB:32] [ 748.700272] [drm:drm_mode_addfb2], [FB:33] [ 748.700280] [drm:drm_mode_setcrtc], [CRTC:5] [ 748.700288] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1] [ 748.700293] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0) [ 748.700301] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set [ 748.700307] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 748.700313] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5] [ 748.700319] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 748.700398] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 748.700406] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains [ 748.700411] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18 [ 748.700418] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz [ 748.700425] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18 [ 748.700431] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600 [ 748.700437] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1 [ 748.700443] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B [ 748.700449] [drm:intel_dump_pipe_config], cpu_transcoder: B [ 748.700454] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 [ 748.700459] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 748.700467] [drm:intel_dump_pipe_config], requested mode: [ 748.700472] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 748.700480] [drm:intel_dump_pipe_config], adjusted mode: [ 748.700485] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9 [ 748.700493] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 748.700501] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000 [ 748.700506] [drm:intel_dump_pipe_config], ips: 0 [ 748.711905] [drm:ironlake_update_plane], Writing base 038CF000 00000000 0 0 5504 [ 748.711926] [drm:intel_update_fbc], no output, disabling [ 748.711937] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768] [ 748.711945] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000 [ 748.711951] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a [ 748.712460] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 4, cursor: 6 [ 748.712469] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6 [ 748.712477] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6 [ 748.712488] [drm:ironlake_edp_pll_on], [ 748.763953] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 748.815983] [drm:ironlake_wait_for_vblank], vblank wait timed out [ 748.815994] [drm:intel_update_fbc], fbc set to per-chip default [ 748.815999] [drm:intel_update_fbc], fbc disabled per module param [ 748.816005] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 748.816012] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 748.816019] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000 [ 748.816031] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008 [ 748.816037] [drm:ironlake_edp_panel_vdd_on], eDP was not running [ 749.117603] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 749.118199] [drm:intel_dp_start_link_train], clock recovery OK [ 749.118203] [drm:ironlake_edp_panel_on], Turn eDP power on [ 749.118207] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle [ 749.118212] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008 [ 749.118222] [drm:ironlake_wait_panel_on], Wait for panel power on [ 749.118227] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009 [ 749.459388] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1 [ 749.459405] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 749.510415] [drm:intel_dp_set_signal_levels], Using signal levels 00000000 [ 749.511366] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful [ 749.511539] [drm:ironlake_edp_backlight_on], [ 749.512218] [drm:ironlake_irq_handler], Pipe B FIFO underrun [ 749.552447] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93 [ 749.562424] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1] [ 749.562452] [drm:check_encoder_state], [ENCODER:8:DAC-8] [ 749.562460] [drm:check_encoder_state], [ENCODER:9:TMDS-9] [ 749.562466] [drm:check_encoder_state], [ENCODER:18:TMDS-18] [ 749.562474] [drm:check_encoder_state], [ENCODER:20:TMDS-20] [ 749.562481] [drm:check_encoder_state], [ENCODER:22:TMDS-22] [ 749.562489] [drm:check_encoder_state], [ENCODER:24:TMDS-24] [ 749.562495] [drm:check_encoder_state], [ENCODER:26:TMDS-26] [ 749.562503] [drm:check_encoder_state], [ENCODER:28:TMDS-28] [ 749.562509] [drm:check_crtc_state], [CRTC:3] [ 749.562516] [drm:check_crtc_state], [CRTC:5] [ 749.562530] [drm:check_shared_dpll_state], PCH DPLL A [ 749.562540] [drm:check_shared_dpll_state], PCH DPLL B [ 749.578187] [drm:intel_update_fbc], fbc set to per-chip default [ 749.578197] [drm:intel_update_fbc], fbc disabled per module param [ 756.724515] [drm:intel_crtc_set_config], [CRTC:5] [NOFB] [ 756.724534] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC] [ 756.724542] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch [ 756.724547] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch [ 756.724552] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2 [ 756.724560] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on [ 756.724572] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f [ 756.724579] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 [ 756.724587] [drm:ironlake_edp_backlight_off], [ 756.925200] [drm:ironlake_edp_panel_off], Turn eDP power off [ 756.925210] [drm:ironlake_wait_panel_off], Wait for panel power off time [ 756.925216] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000