[  124.859230] [drm:intel_crtc_set_config], [CRTC:3] [FB:50] #connectors=1 (x y) (0 0)
[  124.859233] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:DP-1] to [CRTC:3]
[  124.941007] [drm:ilk_check_wm], WM1: enabled
[  124.941008] [drm:ilk_check_wm], WM2: enabled
[  124.941009] [drm:ilk_check_wm], WM3: enabled
[  124.941009] [drm:ilk_check_wm], WM4: enabled
[  124.941020] [drm:check_encoder_state], [ENCODER:10:DAC-10]
[  124.941021] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
[  124.941021] [drm:check_encoder_state], [ENCODER:16:TMDS-16]
[  124.941022] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
[  124.941023] [drm:check_crtc_state], [CRTC:3]
[  124.941025] [drm:check_crtc_state], [CRTC:5]
[  124.941026] [drm:check_crtc_state], [CRTC:7]
[  124.941048] [drm:intel_crtc_set_config], [CRTC:3] [FB:50] #connectors=1 (x y) (0 0)
[  124.941051] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:DP-1] to [CRTC:3]
[  124.941053] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  124.941055] [drm:connected_sink_compute_bpp], [CONNECTOR:12:DP-1] checking for sink bpp constrains
[  124.941056] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 148500KHz
[  124.941059] [drm:intel_dp_compute_config], DP link bw 06 lane count 4 clock 162000 bpp 24
[  124.941059] [drm:intel_dp_compute_config], DP link bw required 356400 available 518400
[  124.941060] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  124.941061] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  124.941062] [drm:intel_dump_pipe_config], cpu_transcoder: A
[  124.941063] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  124.941064] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  124.941064] [drm:intel_dump_pipe_config], requested mode:
[  124.941066] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[  124.941066] [drm:intel_dump_pipe_config], adjusted mode:
[  124.941067] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[  124.941068] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  124.941069] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
[  124.941069] [drm:intel_dump_pipe_config], ips: 0
[  124.941085] [drm:ironlake_update_plane], Writing base 000A1000 00000000 0 0 7680
[  124.941087] [drm:ilk_check_wm], WM1: enabled
[  124.941088] [drm:ilk_check_wm], WM2: enabled
[  124.941088] [drm:ilk_check_wm], WM3: enabled
[  124.941089] [drm:ilk_check_wm], WM4: enabled
[  124.941092] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:0:1920x1080]
[  124.941093] [drm:intel_ddi_mode_set], Preparing DDI mode on port B, pipe A
[  124.941093] [drm:intel_ddi_mode_set], DP audio on pipe A on DDI
[  124.941094] [drm:intel_ddi_mode_set], DP audio: write eld information
[  124.941095] [drm:intel_write_eld], ELD on [CONNECTOR:12:DP-1], [ENCODER:11:TMDS-11]
[  124.941096] [drm:haswell_write_eld], HDMI: Haswell Audio initialize....
[  124.941096] [drm:haswell_write_eld], HDMI audio: enable codec
[  125.005096] [drm:ironlake_wait_for_vblank], vblank wait timed out
[  125.005101] [drm:haswell_write_eld], HDMI audio: pin eld vld status=0x       4
[  125.005105] [drm:haswell_write_eld], HDMI audio: eld vld status=0x       5
[  125.005107] [drm:haswell_write_eld], HDMI audio: audio conf: 0x20800000
[  125.005110] [drm:haswell_write_eld], ELD on pipe A
[  125.005113] [drm:haswell_write_eld], ELD: DisplayPort detected
[  125.005130] [drm:ilk_check_wm], WM1: enabled
[  125.005132] [drm:ilk_check_wm], WM2: enabled
[  125.005134] [drm:ilk_check_wm], WM3: enabled
[  125.005136] [drm:ilk_check_wm], WM4: enabled
[  125.006240] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  125.007110] [drm:intel_dp_set_signal_levels], Using signal levels 03000000
[  125.008265] [drm:intel_dp_start_link_train], clock recovery OK
[  125.008267] [drm:intel_dp_set_signal_levels], Using signal levels 03000000
[  125.009383] [drm:intel_dp_set_signal_levels], Using signal levels 02000000
[  125.010806] [drm:intel_dp_set_signal_levels], Using signal levels 01000000
[  125.011947] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  125.013093] [drm:intel_dp_set_signal_levels], Using signal levels 01000000
[  125.021037] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  125.077170] [drm:intel_connector_check_state], [CONNECTOR:12:DP-1]
[  125.077180] [drm:check_encoder_state], [ENCODER:10:DAC-10]
[  125.077183] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
[  125.077187] [drm:check_encoder_state], [ENCODER:16:TMDS-16]
[  125.077190] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
[  125.077192] [drm:check_crtc_state], [CRTC:3]
[  125.077203] [drm:check_crtc_state], [CRTC:5]
[  125.077206] [drm:check_crtc_state], [CRTC:7]
[  126.598630] [drm:intel_connector_check_state], [CONNECTOR:12:DP-1]
[  126.598638] [drm:check_encoder_state], [ENCODER:10:DAC-10]
[  126.598642] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
[  126.598645] [drm:check_encoder_state], [ENCODER:16:TMDS-16]
[  126.598648] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
[  126.598651] [drm:check_crtc_state], [CRTC:3]
[  126.598662] [drm:check_crtc_state], [CRTC:5]
[  126.598666] [drm:check_crtc_state], [CRTC:7]
[  126.598672] [drm:intel_connector_check_state], [CONNECTOR:12:DP-1]
[  126.598677] [drm:check_encoder_state], [ENCODER:10:DAC-10]
[  126.598680] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
[  126.598683] [drm:check_encoder_state], [ENCODER:16:TMDS-16]
[  126.598686] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
[  126.598688] [drm:check_crtc_state], [CRTC:3]
[  126.598696] [drm:check_crtc_state], [CRTC:5]
[  126.598699] [drm:check_crtc_state], [CRTC:7]
[  126.598703] [drm:intel_connector_check_state], [CONNECTOR:12:DP-1]
[  126.598709] [drm:check_encoder_state], [ENCODER:10:DAC-10]
[  126.598711] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
[  126.598714] [drm:check_encoder_state], [ENCODER:16:TMDS-16]
[  126.598717] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
[  126.598719] [drm:check_crtc_state], [CRTC:3]
[  126.598727] [drm:check_crtc_state], [CRTC:5]
[  126.598730] [drm:check_crtc_state], [CRTC:7]
[  126.598735] [drm:intel_connector_check_state], [CONNECTOR:12:DP-1]
[  126.598741] [drm:check_encoder_state], [ENCODER:10:DAC-10]
[  126.598743] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
[  126.598746] [drm:check_encoder_state], [ENCODER:16:TMDS-16]
[  126.598749] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
[  126.598751] [drm:check_crtc_state], [CRTC:3]
[  126.598759] [drm:check_crtc_state], [CRTC:5]
[  126.598761] [drm:check_crtc_state], [CRTC:7]
[  126.598766] [drm:intel_connector_check_state], [CONNECTOR:12:DP-1]
[  126.598772] [drm:check_encoder_state], [ENCODER:10:DAC-10]
[  126.598774] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
[  126.598777] [drm:check_encoder_state], [ENCODER:16:TMDS-16]
[  126.598780] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
[  126.598782] [drm:check_crtc_state], [CRTC:3]
[  126.598790] [drm:check_crtc_state], [CRTC:5]
[  126.598793] [drm:check_crtc_state], [CRTC:7]
[  130.490987] [drm:intel_crtc_set_config], [CRTC:3] [FB:50] #connectors=1 (x y) (0 0)
[  130.490991] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:DP-1] to [CRTC:3]
[  130.490992] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  130.490993] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:DP-1] to [CRTC:3]
[  130.490994] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  130.490995] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:DP-1] to [CRTC:3]
[  130.490996] [drm:intel_crtc_set_config], [CRTC:3] [FB:50] #connectors=1 (x y) (0 0)
[  130.490997] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:DP-1] to [CRTC:3]
[  130.491003] [drm:intel_crtc_set_config], [CRTC:3] [FB:50] #connectors=1 (x y) (0 0)
[  130.491004] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:DP-1] to [CRTC:3]
[  130.493995] [drm:intel_crtc_set_config], [CRTC:3] [FB:50] #connectors=1 (x y) (0 0)
[  130.493996] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:DP-1] to [CRTC:3]