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$(libradeonsi_la_LIBADD) $(LIBS) + +mostlyclean-compile: + -rm -f *.$(OBJEXT) + +distclean-compile: + -rm -f *.tab.c + +#include ./$(DEPDIR)/radeonsi_blit.Plo +#include ./$(DEPDIR)/radeonsi_buffer.Plo +#include ./$(DEPDIR)/radeonsi_compute.Plo +#include ./$(DEPDIR)/radeonsi_hw_context.Plo +#include ./$(DEPDIR)/radeonsi_pipe.Plo +#include ./$(DEPDIR)/radeonsi_pm4.Plo +#include ./$(DEPDIR)/radeonsi_query.Plo +#include ./$(DEPDIR)/radeonsi_resource.Plo +#include ./$(DEPDIR)/radeonsi_shader.Plo +#include ./$(DEPDIR)/radeonsi_texture.Plo +#include ./$(DEPDIR)/radeonsi_translate.Plo +#include ./$(DEPDIR)/radeonsi_uvd.Plo +#include ./$(DEPDIR)/si_commands.Plo +#include ./$(DEPDIR)/si_state.Plo +#include ./$(DEPDIR)/si_state_draw.Plo +#include ./$(DEPDIR)/si_state_streamout.Plo + +.c.o: +# $(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $< +# $(AM_V_at)$(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po +# $(AM_V_CC)source='$<' object='$@' libtool=no +# DEPDIR=$(DEPDIR) $(CCDEPMODE) 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b/src/gallium/drivers/radeonsi/Makefile.in --- a/src/gallium/drivers/radeonsi/Makefile.in 2013-08-20 01:51:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/Makefile.in 2013-08-28 04:15:13.856313555 +0200 @@ -1,4 +1,4 @@ -# Makefile.in generated by automake 1.12.2 from Makefile.am. +# Makefile.in generated by automake 1.12.6 from Makefile.am. # @configure_input@ # Copyright (C) 1994-2012 Free Software Foundation, Inc. @@ -95,12 +95,12 @@ LTLIBRARIES = $(noinst_LTLIBRARIES) libradeonsi_la_DEPENDENCIES = ../radeon/libradeon.la \ ../radeon/libllvmradeon.la -am__objects_1 = r600_blit.lo r600_buffer.lo r600_hw_context.lo \ - radeonsi_pipe.lo r600_query.lo r600_resource.lo \ - radeonsi_shader.lo r600_texture.lo r600_translate.lo \ - radeonsi_pm4.lo radeonsi_compute.lo si_state.lo \ - si_state_streamout.lo si_state_draw.lo si_commands.lo \ - radeonsi_uvd.lo +am__objects_1 = radeonsi_blit.lo radeonsi_buffer.lo \ + radeonsi_hw_context.lo radeonsi_pipe.lo radeonsi_query.lo \ + radeonsi_resource.lo radeonsi_shader.lo radeonsi_texture.lo \ + radeonsi_translate.lo radeonsi_pm4.lo radeonsi_compute.lo \ + si_state.lo si_state_streamout.lo si_state_draw.lo \ + si_commands.lo radeonsi_uvd.lo am_libradeonsi_la_OBJECTS = $(am__objects_1) libradeonsi_la_OBJECTS = $(am_libradeonsi_la_OBJECTS) AM_V_lt = $(am__v_lt_@AM_V@) @@ -434,15 +434,15 @@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ C_SOURCES := \ - r600_blit.c \ - r600_buffer.c \ - r600_hw_context.c \ + radeonsi_blit.c \ + radeonsi_buffer.c \ + radeonsi_hw_context.c \ radeonsi_pipe.c \ - r600_query.c \ - r600_resource.c \ + radeonsi_query.c \ + radeonsi_resource.c \ radeonsi_shader.c \ - r600_texture.c \ - r600_translate.c \ + radeonsi_texture.c \ + radeonsi_translate.c \ radeonsi_pm4.c \ radeonsi_compute.c \ si_state.c \ @@ -525,17 +525,17 @@ distclean-compile: -rm -f *.tab.c -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_blit.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_buffer.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_hw_context.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_query.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_resource.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_texture.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_translate.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_blit.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_buffer.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_compute.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_hw_context.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_pipe.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_pm4.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_query.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_resource.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_shader.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_texture.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_translate.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_uvd.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_commands.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_state.Plo@am__quote@ diff -uNr a/src/gallium/drivers/radeonsi/Makefile.sources b/src/gallium/drivers/radeonsi/Makefile.sources --- a/src/gallium/drivers/radeonsi/Makefile.sources 2013-08-14 03:34:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/Makefile.sources 2013-08-28 04:15:13.856313555 +0200 @@ -1,13 +1,13 @@ C_SOURCES := \ - r600_blit.c \ - r600_buffer.c \ - r600_hw_context.c \ + radeonsi_blit.c \ + radeonsi_buffer.c \ + radeonsi_hw_context.c \ radeonsi_pipe.c \ - r600_query.c \ - r600_resource.c \ + radeonsi_query.c \ + radeonsi_resource.c \ radeonsi_shader.c \ - r600_texture.c \ - r600_translate.c \ + radeonsi_texture.c \ + radeonsi_translate.c \ radeonsi_pm4.c \ radeonsi_compute.c \ si_state.c \ diff -uNr a/src/gallium/drivers/radeonsi/r600.h b/src/gallium/drivers/radeonsi/r600.h --- a/src/gallium/drivers/radeonsi/r600.h 2013-06-27 20:13:13.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/r600.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,109 +0,0 @@ -/* - * Copyright 2010 Jerome Glisse - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jerome Glisse - */ -#ifndef R600_H -#define R600_H - -#include "../../winsys/radeon/drm/radeon_winsys.h" -#include "util/u_double_list.h" -#include "util/u_transfer.h" - -#include "radeonsi_resource.h" - -#define R600_ERR(fmt, args...) \ - fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args) - -struct winsys_handle; - -struct r600_tiling_info { - unsigned num_channels; - unsigned num_banks; - unsigned group_bytes; -}; - -/* R600/R700 STATES */ -struct r600_query { - union { - uint64_t u64; - boolean b; - struct pipe_query_data_so_statistics so; - } result; - /* The kind of query */ - unsigned type; - /* Offset of the first result for current query */ - unsigned results_start; - /* Offset of the next free result after current query data */ - unsigned results_end; - /* Size of the result in memory for both begin_query and end_query, - * this can be one or two numbers, or it could even be a size of a structure. */ - unsigned result_size; - /* The buffer where query results are stored. It's used as a ring, - * data blocks for current query are stored sequentially from - * results_start to results_end, with wrapping on the buffer end */ - struct si_resource *buffer; - /* The number of dwords for begin_query or end_query. */ - unsigned num_cs_dw; - /* linked list of queries */ - struct list_head list; -}; - -struct r600_so_target { - struct pipe_stream_output_target b; - - /* The buffer where BUFFER_FILLED_SIZE is stored. */ - struct si_resource *filled_size; - unsigned stride; - unsigned so_index; -}; - -#define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1) -#define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2) - -struct r600_context; -struct r600_screen; - -void si_get_backend_mask(struct r600_context *ctx); -void si_context_flush(struct r600_context *ctx, unsigned flags); - -struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type); -void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query); -boolean r600_context_query_result(struct r600_context *ctx, - struct r600_query *query, - boolean wait, void *vresult); -void r600_query_begin(struct r600_context *ctx, struct r600_query *query); -void r600_query_end(struct r600_context *ctx, struct r600_query *query); -void r600_context_queries_suspend(struct r600_context *ctx); -void r600_context_queries_resume(struct r600_context *ctx); -void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, - int flag_wait); -void si_context_emit_fence(struct r600_context *ctx, struct si_resource *fence, - unsigned offset, unsigned value); - -void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t); -void si_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in); - -int si_context_init(struct r600_context *ctx); - -#endif diff -uNr a/src/gallium/drivers/radeonsi/r600_blit.c b/src/gallium/drivers/radeonsi/r600_blit.c --- a/src/gallium/drivers/radeonsi/r600_blit.c 2013-08-14 03:34:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/r600_blit.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,501 +0,0 @@ -/* - * Copyright 2010 Jerome Glisse - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#include "util/u_surface.h" -#include "util/u_blitter.h" -#include "util/u_format.h" -#include "radeonsi_pipe.h" -#include "si_state.h" - -enum r600_blitter_op /* bitmask */ -{ - R600_SAVE_TEXTURES = 1, - R600_SAVE_FRAMEBUFFER = 2, - R600_DISABLE_RENDER_COND = 4, - - R600_CLEAR = 0, - - R600_CLEAR_SURFACE = R600_SAVE_FRAMEBUFFER, - - R600_COPY = R600_SAVE_FRAMEBUFFER | R600_SAVE_TEXTURES | - R600_DISABLE_RENDER_COND, - - R600_BLIT = R600_SAVE_FRAMEBUFFER | R600_SAVE_TEXTURES | - R600_DISABLE_RENDER_COND, - - R600_DECOMPRESS = R600_SAVE_FRAMEBUFFER | R600_DISABLE_RENDER_COND, -}; - -static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - - r600_context_queries_suspend(rctx); - - util_blitter_save_blend(rctx->blitter, rctx->queued.named.blend); - util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->queued.named.dsa); - util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref); - util_blitter_save_rasterizer(rctx->blitter, rctx->queued.named.rasterizer); - util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader); - util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader); - util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements); - if (rctx->queued.named.viewport) { - util_blitter_save_viewport(rctx->blitter, &rctx->queued.named.viewport->viewport); - } - util_blitter_save_vertex_buffer_slot(rctx->blitter, rctx->vertex_buffer); - util_blitter_save_so_targets(rctx->blitter, rctx->num_so_targets, - (struct pipe_stream_output_target**)rctx->so_targets); - - if (op & R600_SAVE_FRAMEBUFFER) - util_blitter_save_framebuffer(rctx->blitter, &rctx->framebuffer); - - if (op & R600_SAVE_TEXTURES) { - util_blitter_save_fragment_sampler_states( - rctx->blitter, rctx->ps_samplers.n_samplers, - (void**)rctx->ps_samplers.samplers); - - util_blitter_save_fragment_sampler_views( - rctx->blitter, rctx->ps_samplers.n_views, - (struct pipe_sampler_view**)rctx->ps_samplers.views); - } - - if ((op & R600_DISABLE_RENDER_COND) && rctx->current_render_cond) { - rctx->saved_render_cond = rctx->current_render_cond; - rctx->saved_render_cond_cond = rctx->current_render_cond_cond; - rctx->saved_render_cond_mode = rctx->current_render_cond_mode; - rctx->context.render_condition(&rctx->context, NULL, FALSE, 0); - } - -} - -static void r600_blitter_end(struct pipe_context *ctx) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - if (rctx->saved_render_cond) { - rctx->context.render_condition(&rctx->context, - rctx->saved_render_cond, - rctx->saved_render_cond_cond, - rctx->saved_render_cond_mode); - rctx->saved_render_cond = NULL; - } - r600_context_queries_resume(rctx); -} - -void si_blit_uncompress_depth(struct pipe_context *ctx, - struct r600_resource_texture *texture, - struct r600_resource_texture *staging, - unsigned first_level, unsigned last_level, - unsigned first_layer, unsigned last_layer) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - unsigned layer, level, checked_last_layer, max_layer; - float depth = 1.0f; - const struct util_format_description *desc; - void *custom_dsa; - struct r600_resource_texture *flushed_depth_texture = staging ? - staging : texture->flushed_depth_texture; - - if (!staging && !texture->dirty_db_mask) - return; - - desc = util_format_description(flushed_depth_texture->resource.b.b.format); - switch (util_format_has_depth(desc) | util_format_has_stencil(desc) << 1) { - default: - assert(!"No depth or stencil to uncompress"); - case 3: - custom_dsa = rctx->custom_dsa_flush_depth_stencil; - break; - case 2: - custom_dsa = rctx->custom_dsa_flush_stencil; - break; - case 1: - custom_dsa = rctx->custom_dsa_flush_depth; - break; - } - - for (level = first_level; level <= last_level; level++) { - if (!staging && !(texture->dirty_db_mask & (1 << level))) - continue; - - /* The smaller the mipmap level, the less layers there are - * as far as 3D textures are concerned. */ - max_layer = util_max_layer(&texture->resource.b.b, level); - checked_last_layer = last_layer < max_layer ? last_layer : max_layer; - - for (layer = first_layer; layer <= checked_last_layer; layer++) { - struct pipe_surface *zsurf, *cbsurf, surf_tmpl; - - surf_tmpl.format = texture->real_format; - surf_tmpl.u.tex.level = level; - surf_tmpl.u.tex.first_layer = layer; - surf_tmpl.u.tex.last_layer = layer; - - zsurf = ctx->create_surface(ctx, &texture->resource.b.b, &surf_tmpl); - - surf_tmpl.format = flushed_depth_texture->real_format; - cbsurf = ctx->create_surface(ctx, - (struct pipe_resource*)flushed_depth_texture, &surf_tmpl); - - r600_blitter_begin(ctx, R600_DECOMPRESS); - util_blitter_custom_depth_stencil(rctx->blitter, zsurf, cbsurf, ~0, custom_dsa, depth); - r600_blitter_end(ctx); - - pipe_surface_reference(&zsurf, NULL); - pipe_surface_reference(&cbsurf, NULL); - } - - /* The texture will always be dirty if some layers aren't flushed. - * I don't think this case can occur though. */ - if (!staging && first_layer == 0 && last_layer == max_layer) { - texture->dirty_db_mask &= ~(1 << level); - } - } -} - -static void si_blit_decompress_depth_in_place(struct r600_context *rctx, - struct r600_resource_texture *texture, - unsigned first_level, unsigned last_level, - unsigned first_layer, unsigned last_layer) -{ - struct pipe_surface *zsurf, surf_tmpl = {{0}}; - unsigned layer, max_layer, checked_last_layer, level; - - surf_tmpl.format = texture->resource.b.b.format; - - for (level = first_level; level <= last_level; level++) { - if (!(texture->dirty_db_mask & (1 << level))) - continue; - - surf_tmpl.u.tex.level = level; - - /* The smaller the mipmap level, the less layers there are - * as far as 3D textures are concerned. */ - max_layer = util_max_layer(&texture->resource.b.b, level); - checked_last_layer = last_layer < max_layer ? last_layer : max_layer; - - for (layer = first_layer; layer <= checked_last_layer; layer++) { - surf_tmpl.u.tex.first_layer = layer; - surf_tmpl.u.tex.last_layer = layer; - - zsurf = rctx->context.create_surface(&rctx->context, &texture->resource.b.b, &surf_tmpl); - - r600_blitter_begin(&rctx->context, R600_DECOMPRESS); - util_blitter_custom_depth_stencil(rctx->blitter, zsurf, NULL, ~0, - rctx->custom_dsa_flush_inplace, - 1.0f); - r600_blitter_end(&rctx->context); - - pipe_surface_reference(&zsurf, NULL); - } - - /* The texture will always be dirty if some layers aren't flushed. - * I don't think this case occurs often though. */ - if (first_layer == 0 && last_layer == max_layer) { - texture->dirty_db_mask &= ~(1 << level); - } - } -} - -void si_flush_depth_textures(struct r600_context *rctx, - struct r600_textures_info *textures) -{ - unsigned i; - - for (i = 0; i < textures->n_views; ++i) { - struct pipe_sampler_view *view; - struct r600_resource_texture *tex; - - view = &textures->views[i]->base; - if (!view) continue; - - tex = (struct r600_resource_texture *)view->texture; - if (!tex->is_depth || tex->is_flushing_texture) - continue; - - si_blit_decompress_depth_in_place(rctx, tex, - view->u.tex.first_level, view->u.tex.last_level, - 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level)); - } -} - -static void r600_clear(struct pipe_context *ctx, unsigned buffers, - const union pipe_color_union *color, - double depth, unsigned stencil) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - struct pipe_framebuffer_state *fb = &rctx->framebuffer; - - r600_blitter_begin(ctx, R600_CLEAR); - util_blitter_clear(rctx->blitter, fb->width, fb->height, - buffers, color, depth, stencil); - r600_blitter_end(ctx); -} - -static void r600_clear_render_target(struct pipe_context *ctx, - struct pipe_surface *dst, - const union pipe_color_union *color, - unsigned dstx, unsigned dsty, - unsigned width, unsigned height) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - - r600_blitter_begin(ctx, R600_CLEAR_SURFACE); - util_blitter_clear_render_target(rctx->blitter, dst, color, - dstx, dsty, width, height); - r600_blitter_end(ctx); -} - -static void r600_clear_depth_stencil(struct pipe_context *ctx, - struct pipe_surface *dst, - unsigned clear_flags, - double depth, - unsigned stencil, - unsigned dstx, unsigned dsty, - unsigned width, unsigned height) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - - r600_blitter_begin(ctx, R600_CLEAR_SURFACE); - util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil, - dstx, dsty, width, height); - r600_blitter_end(ctx); -} - -struct texture_orig_info { - unsigned format; - unsigned width0; - unsigned height0; - unsigned npix_x; - unsigned npix_y; - unsigned npix0_x; - unsigned npix0_y; -}; - -static void r600_compressed_to_blittable(struct pipe_resource *tex, - unsigned level, - struct texture_orig_info *orig) -{ - struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex; - unsigned pixsize = util_format_get_blocksize(rtex->real_format); - int new_format; - int new_height, new_width; - - orig->format = tex->format; - orig->width0 = tex->width0; - orig->height0 = tex->height0; - orig->npix0_x = rtex->surface.level[0].npix_x; - orig->npix0_y = rtex->surface.level[0].npix_y; - orig->npix_x = rtex->surface.level[level].npix_x; - orig->npix_y = rtex->surface.level[level].npix_y; - - if (pixsize == 8) - new_format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */ - else - new_format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */ - - new_width = util_format_get_nblocksx(tex->format, orig->width0); - new_height = util_format_get_nblocksy(tex->format, orig->height0); - - tex->width0 = new_width; - tex->height0 = new_height; - tex->format = new_format; - rtex->surface.level[0].npix_x = util_format_get_nblocksx(orig->format, orig->npix0_x); - rtex->surface.level[0].npix_y = util_format_get_nblocksy(orig->format, orig->npix0_y); - rtex->surface.level[level].npix_x = util_format_get_nblocksx(orig->format, orig->npix_x); - rtex->surface.level[level].npix_y = util_format_get_nblocksy(orig->format, orig->npix_y); -} - -static void r600_change_format(struct pipe_resource *tex, - unsigned level, - struct texture_orig_info *orig, - enum pipe_format format) -{ - struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex; - - orig->format = tex->format; - orig->width0 = tex->width0; - orig->height0 = tex->height0; - orig->npix0_x = rtex->surface.level[0].npix_x; - orig->npix0_y = rtex->surface.level[0].npix_y; - orig->npix_x = rtex->surface.level[level].npix_x; - orig->npix_y = rtex->surface.level[level].npix_y; - - tex->format = format; -} - -static void r600_reset_blittable_to_orig(struct pipe_resource *tex, - unsigned level, - struct texture_orig_info *orig) -{ - struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex; - - tex->format = orig->format; - tex->width0 = orig->width0; - tex->height0 = orig->height0; - rtex->surface.level[0].npix_x = orig->npix0_x; - rtex->surface.level[0].npix_y = orig->npix0_y; - rtex->surface.level[level].npix_x = orig->npix_x; - rtex->surface.level[level].npix_y = orig->npix_y; -} - -static void r600_resource_copy_region(struct pipe_context *ctx, - struct pipe_resource *dst, - unsigned dst_level, - unsigned dstx, unsigned dsty, unsigned dstz, - struct pipe_resource *src, - unsigned src_level, - const struct pipe_box *src_box) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_resource_texture *rsrc = (struct r600_resource_texture*)src; - struct texture_orig_info orig_info[2]; - struct pipe_box sbox; - const struct pipe_box *psbox = src_box; - boolean restore_orig[2]; - - memset(orig_info, 0, sizeof(orig_info)); - - /* Fallback for buffers. */ - if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { - util_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz, - src, src_level, src_box); - return; - } - - /* This must be done before entering u_blitter to avoid recursion. */ - if (rsrc->is_depth && !rsrc->is_flushing_texture) { - si_blit_decompress_depth_in_place(rctx, rsrc, - src_level, src_level, - src_box->z, src_box->z + src_box->depth - 1); - } - - restore_orig[0] = restore_orig[1] = FALSE; - - if (util_format_is_compressed(src->format) && - util_format_is_compressed(dst->format)) { - r600_compressed_to_blittable(src, src_level, &orig_info[0]); - restore_orig[0] = TRUE; - sbox.x = util_format_get_nblocksx(orig_info[0].format, src_box->x); - sbox.y = util_format_get_nblocksy(orig_info[0].format, src_box->y); - sbox.z = src_box->z; - sbox.width = util_format_get_nblocksx(orig_info[0].format, src_box->width); - sbox.height = util_format_get_nblocksy(orig_info[0].format, src_box->height); - sbox.depth = src_box->depth; - psbox=&sbox; - - r600_compressed_to_blittable(dst, dst_level, &orig_info[1]); - restore_orig[1] = TRUE; - /* translate the dst box as well */ - dstx = util_format_get_nblocksx(orig_info[1].format, dstx); - dsty = util_format_get_nblocksy(orig_info[1].format, dsty); - } else if (!util_blitter_is_copy_supported(rctx->blitter, dst, src, - PIPE_MASK_RGBAZS)) { - unsigned blocksize = util_format_get_blocksize(src->format); - - switch (blocksize) { - case 1: - r600_change_format(src, src_level, &orig_info[0], - PIPE_FORMAT_R8_UNORM); - r600_change_format(dst, dst_level, &orig_info[1], - PIPE_FORMAT_R8_UNORM); - break; - case 2: - r600_change_format(src, src_level, &orig_info[0], - PIPE_FORMAT_R8G8_UNORM); - r600_change_format(dst, dst_level, &orig_info[1], - PIPE_FORMAT_R8G8_UNORM); - break; - case 4: - r600_change_format(src, src_level, &orig_info[0], - PIPE_FORMAT_R8G8B8A8_UNORM); - r600_change_format(dst, dst_level, &orig_info[1], - PIPE_FORMAT_R8G8B8A8_UNORM); - break; - case 8: - r600_change_format(src, src_level, &orig_info[0], - PIPE_FORMAT_R16G16B16A16_UINT); - r600_change_format(dst, dst_level, &orig_info[1], - PIPE_FORMAT_R16G16B16A16_UINT); - break; - case 16: - r600_change_format(src, src_level, &orig_info[0], - PIPE_FORMAT_R32G32B32A32_UINT); - r600_change_format(dst, dst_level, &orig_info[1], - PIPE_FORMAT_R32G32B32A32_UINT); - break; - default: - fprintf(stderr, "Unhandled format %s with blocksize %u\n", - util_format_short_name(src->format), blocksize); - assert(0); - } - restore_orig[0] = TRUE; - restore_orig[1] = TRUE; - } - - r600_blitter_begin(ctx, R600_COPY); - util_blitter_copy_texture(rctx->blitter, dst, dst_level, dstx, dsty, dstz, - src, src_level, psbox, PIPE_MASK_RGBAZS, TRUE); - r600_blitter_end(ctx); - - if (restore_orig[0]) - r600_reset_blittable_to_orig(src, src_level, &orig_info[0]); - - if (restore_orig[1]) - r600_reset_blittable_to_orig(dst, dst_level, &orig_info[1]); -} - -static void si_blit(struct pipe_context *ctx, - const struct pipe_blit_info *info) -{ - struct r600_context *rctx = (struct r600_context*)ctx; - struct r600_resource_texture *rsrc = (struct r600_resource_texture*)info->src.resource; - - assert(util_blitter_is_blit_supported(rctx->blitter, info)); - - if (info->src.resource->nr_samples > 1 && - info->dst.resource->nr_samples <= 1 && - !util_format_is_depth_or_stencil(info->src.resource->format) && - !util_format_is_pure_integer(info->src.resource->format)) { - debug_printf("radeonsi: color resolve is unimplemented\n"); - return; - } - - if (rsrc->is_depth && !rsrc->is_flushing_texture) { - si_blit_decompress_depth_in_place(rctx, rsrc, - info->src.level, info->src.level, - info->src.box.z, - info->src.box.z + info->src.box.depth - 1); - } - - r600_blitter_begin(ctx, R600_BLIT); - util_blitter_blit(rctx->blitter, info); - r600_blitter_end(ctx); -} - -void si_init_blit_functions(struct r600_context *rctx) -{ - rctx->context.clear = r600_clear; - rctx->context.clear_render_target = r600_clear_render_target; - rctx->context.clear_depth_stencil = r600_clear_depth_stencil; - rctx->context.resource_copy_region = r600_resource_copy_region; - rctx->context.blit = si_blit; -} diff -uNr a/src/gallium/drivers/radeonsi/r600_buffer.c b/src/gallium/drivers/radeonsi/r600_buffer.c --- a/src/gallium/drivers/radeonsi/r600_buffer.c 2013-08-14 03:34:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/r600_buffer.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,197 +0,0 @@ -/* - * Copyright 2010 Jerome Glisse - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jerome Glisse - * Corbin Simpson - */ - -#include "pipe/p_screen.h" -#include "util/u_format.h" -#include "util/u_math.h" -#include "util/u_inlines.h" -#include "util/u_memory.h" -#include "util/u_upload_mgr.h" - -#include "r600.h" -#include "radeonsi_pipe.h" - -static void r600_buffer_destroy(struct pipe_screen *screen, - struct pipe_resource *buf) -{ - struct si_resource *rbuffer = si_resource(buf); - - pb_reference(&rbuffer->buf, NULL); - FREE(rbuffer); -} - -static void *r600_buffer_transfer_map(struct pipe_context *ctx, - struct pipe_resource *resource, - unsigned level, - unsigned usage, - const struct pipe_box *box, - struct pipe_transfer **ptransfer) -{ - struct r600_context *rctx = (struct r600_context*)ctx; - struct pipe_transfer *transfer; - struct si_resource *rbuffer = si_resource(resource); - uint8_t *data; - - data = rctx->ws->buffer_map(rbuffer->cs_buf, rctx->cs, usage); - if (!data) { - return NULL; - } - - transfer = util_slab_alloc(&rctx->pool_transfers); - transfer->resource = resource; - transfer->level = level; - transfer->usage = usage; - transfer->box = *box; - transfer->stride = 0; - transfer->layer_stride = 0; - *ptransfer = transfer; - - return (uint8_t*)data + transfer->box.x; -} - -static void r600_buffer_transfer_unmap(struct pipe_context *ctx, - struct pipe_transfer *transfer) -{ - struct r600_context *rctx = (struct r600_context*)ctx; - util_slab_free(&rctx->pool_transfers, transfer); -} - -static void r600_buffer_transfer_flush_region(struct pipe_context *pipe, - struct pipe_transfer *transfer, - const struct pipe_box *box) -{ -} - -static const struct u_resource_vtbl r600_buffer_vtbl = -{ - u_default_resource_get_handle, /* get_handle */ - r600_buffer_destroy, /* resource_destroy */ - r600_buffer_transfer_map, /* transfer_map */ - r600_buffer_transfer_flush_region, /* transfer_flush_region */ - r600_buffer_transfer_unmap, /* transfer_unmap */ - NULL /* transfer_inline_write */ -}; - -bool si_init_resource(struct r600_screen *rscreen, - struct si_resource *res, - unsigned size, unsigned alignment, - boolean use_reusable_pool, unsigned usage) -{ - uint32_t initial_domain, domains; - - /* Staging resources particpate in transfers and blits only - * and are used for uploads and downloads from regular - * resources. We generate them internally for some transfers. - */ - if (usage == PIPE_USAGE_STAGING) { - domains = RADEON_DOMAIN_GTT; - initial_domain = RADEON_DOMAIN_GTT; - } else { - domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; - - switch(usage) { - case PIPE_USAGE_DYNAMIC: - case PIPE_USAGE_STREAM: - case PIPE_USAGE_STAGING: - initial_domain = RADEON_DOMAIN_GTT; - break; - case PIPE_USAGE_DEFAULT: - case PIPE_USAGE_STATIC: - case PIPE_USAGE_IMMUTABLE: - default: - initial_domain = RADEON_DOMAIN_VRAM; - break; - } - } - - res->buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment, - use_reusable_pool, - initial_domain); - if (!res->buf) { - return false; - } - - res->cs_buf = rscreen->ws->buffer_get_cs_handle(res->buf); - res->domains = domains; - return true; -} - -struct pipe_resource *si_buffer_create(struct pipe_screen *screen, - const struct pipe_resource *templ) -{ - struct r600_screen *rscreen = (struct r600_screen*)screen; - struct si_resource *rbuffer; - /* XXX We probably want a different alignment for buffers and textures. */ - unsigned alignment = 4096; - - rbuffer = MALLOC_STRUCT(si_resource); - - rbuffer->b.b = *templ; - pipe_reference_init(&rbuffer->b.b.reference, 1); - rbuffer->b.b.screen = screen; - rbuffer->b.vtbl = &r600_buffer_vtbl; - - if (!si_init_resource(rscreen, rbuffer, templ->width0, alignment, TRUE, templ->usage)) { - FREE(rbuffer); - return NULL; - } - return &rbuffer->b.b; -} - -void r600_upload_index_buffer(struct r600_context *rctx, - struct pipe_index_buffer *ib, unsigned count) -{ - u_upload_data(rctx->uploader, 0, count * ib->index_size, - ib->user_buffer, &ib->offset, &ib->buffer); -} - -void r600_upload_const_buffer(struct r600_context *rctx, struct si_resource **rbuffer, - const uint8_t *ptr, unsigned size, - uint32_t *const_offset) -{ - if (R600_BIG_ENDIAN) { - uint32_t *tmpPtr; - unsigned i; - - if (!(tmpPtr = malloc(size))) { - R600_ERR("Failed to allocate BE swap buffer.\n"); - return; - } - - for (i = 0; i < size / 4; ++i) { - tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]); - } - - u_upload_data(rctx->uploader, 0, size, tmpPtr, const_offset, - (struct pipe_resource**)rbuffer); - - free(tmpPtr); - } else { - u_upload_data(rctx->uploader, 0, size, ptr, const_offset, - (struct pipe_resource**)rbuffer); - } -} diff -uNr a/src/gallium/drivers/radeonsi/r600_hw_context.c b/src/gallium/drivers/radeonsi/r600_hw_context.c --- a/src/gallium/drivers/radeonsi/r600_hw_context.c 2013-08-14 03:34:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/r600_hw_context.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,729 +0,0 @@ -/* - * Copyright 2010 Jerome Glisse - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jerome Glisse - */ -#include "r600_hw_context_priv.h" -#include "radeonsi_pm4.h" -#include "radeonsi_pipe.h" -#include "sid.h" -#include "util/u_memory.h" -#include - -#define GROUP_FORCE_NEW_BLOCK 0 - -/* Get backends mask */ -void si_get_backend_mask(struct r600_context *ctx) -{ - struct radeon_winsys_cs *cs = ctx->cs; - struct si_resource *buffer; - uint32_t *results; - unsigned num_backends = ctx->screen->info.r600_num_backends; - unsigned i, mask = 0; - - /* if backend_map query is supported by the kernel */ - if (ctx->screen->info.r600_backend_map_valid) { - unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes; - unsigned backend_map = ctx->screen->info.r600_backend_map; - unsigned item_width = 4, item_mask = 0x7; - - while(num_tile_pipes--) { - i = backend_map & item_mask; - mask |= (1<>= item_width; - } - if (mask != 0) { - ctx->backend_mask = mask; - return; - } - } - - /* otherwise backup path for older kernels */ - - /* create buffer for event data */ - buffer = si_resource_create_custom(&ctx->screen->screen, - PIPE_USAGE_STAGING, - ctx->max_db*16); - if (!buffer) - goto err; - - /* initialize buffer with zeroes */ - results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE); - if (results) { - uint64_t va = 0; - - memset(results, 0, ctx->max_db * 4 * 4); - ctx->ws->buffer_unmap(buffer->cs_buf); - - /* emit EVENT_WRITE for ZPASS_DONE */ - va = r600_resource_va(&ctx->screen->screen, (void *)buffer); - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); - cs->buf[cs->cdw++] = va; - cs->buf[cs->cdw++] = va >> 32; - - cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE); - - /* analyze results */ - results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_READ); - if (results) { - for(i = 0; i < ctx->max_db; i++) { - /* at least highest bit will be set if backend is used */ - if (results[i*4 + 1]) - mask |= (1<ws->buffer_unmap(buffer->cs_buf); - } - } - - si_resource_reference(&buffer, NULL); - - if (mask != 0) { - ctx->backend_mask = mask; - return; - } - -err: - /* fallback to old method - set num_backends lower bits to 1 */ - ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends); - return; -} - -/* initialize */ -void si_need_cs_space(struct r600_context *ctx, unsigned num_dw, - boolean count_draw_in) -{ - /* The number of dwords we already used in the CS so far. */ - num_dw += ctx->cs->cdw; - - if (count_draw_in) { - /* The number of dwords all the dirty states would take. */ - num_dw += ctx->pm4_dirty_cdwords; - - /* The upper-bound of how much a draw command would take. */ - num_dw += SI_MAX_DRAW_CS_DWORDS; - } - - /* Count in queries_suspend. */ - num_dw += ctx->num_cs_dw_queries_suspend; - - /* Count in streamout_end at the end of CS. */ - num_dw += ctx->num_cs_dw_streamout_end; - - /* Count in render_condition(NULL) at the end of CS. */ - if (ctx->predicate_drawing) { - num_dw += 3; - } - - /* Count in framebuffer cache flushes at the end of CS. */ - num_dw += 7; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */ - - /* Save 16 dwords for the fence mechanism. */ - num_dw += 16; - -#if R600_TRACE_CS - if (ctx->screen->trace_bo) { - num_dw += R600_TRACE_CS_DWORDS; - } -#endif - - /* Flush if there's not enough space. */ - if (num_dw > RADEON_MAX_CMDBUF_DWORDS) { - radeonsi_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC); - } -} - -static void r600_flush_framebuffer(struct r600_context *ctx) -{ - struct si_pm4_state *pm4; - - if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY)) - return; - - pm4 = si_pm4_alloc_state(ctx); - - if (pm4 == NULL) - return; - - si_cmd_surface_sync(pm4, S_0085F0_CB0_DEST_BASE_ENA(1) | - S_0085F0_CB1_DEST_BASE_ENA(1) | - S_0085F0_CB2_DEST_BASE_ENA(1) | - S_0085F0_CB3_DEST_BASE_ENA(1) | - S_0085F0_CB4_DEST_BASE_ENA(1) | - S_0085F0_CB5_DEST_BASE_ENA(1) | - S_0085F0_CB6_DEST_BASE_ENA(1) | - S_0085F0_CB7_DEST_BASE_ENA(1) | - S_0085F0_DB_ACTION_ENA(1) | - S_0085F0_DB_DEST_BASE_ENA(1)); - si_pm4_emit(ctx, pm4); - si_pm4_free_state(ctx, pm4, ~0); - - ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY; -} - -void si_context_flush(struct r600_context *ctx, unsigned flags) -{ - struct radeon_winsys_cs *cs = ctx->cs; - bool queries_suspended = false; - -#if 0 - bool streamout_suspended = false; -#endif - - if (!cs->cdw) - return; - - /* suspend queries */ - if (ctx->num_cs_dw_queries_suspend) { - r600_context_queries_suspend(ctx); - queries_suspended = true; - } - -#if 0 - if (ctx->num_cs_dw_streamout_end) { - r600_context_streamout_end(ctx); - streamout_suspended = true; - } -#endif - - r600_flush_framebuffer(ctx); - - /* partial flush is needed to avoid lockups on some chips with user fences */ - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); - - /* force to keep tiling flags */ - flags |= RADEON_FLUSH_KEEP_TILING_FLAGS; - -#if R600_TRACE_CS - if (ctx->screen->trace_bo) { - struct r600_screen *rscreen = ctx->screen; - unsigned i; - - for (i = 0; i < cs->cdw; i++) { - fprintf(stderr, "[%4d] [%5d] 0x%08x\n", rscreen->cs_count, i, cs->buf[i]); - } - rscreen->cs_count++; - } -#endif - - /* Flush the CS. */ - ctx->ws->cs_flush(ctx->cs, flags, 0); - -#if R600_TRACE_CS - if (ctx->screen->trace_bo) { - struct r600_screen *rscreen = ctx->screen; - unsigned i; - - for (i = 0; i < 10; i++) { - usleep(5); - if (!ctx->ws->buffer_is_busy(rscreen->trace_bo->buf, RADEON_USAGE_READWRITE)) { - break; - } - } - if (i == 10) { - fprintf(stderr, "timeout on cs lockup likely happen at cs %d dw %d\n", - rscreen->trace_ptr[1], rscreen->trace_ptr[0]); - } else { - fprintf(stderr, "cs %d executed in %dms\n", rscreen->trace_ptr[1], i * 5); - } - } -#endif - - ctx->pm4_dirty_cdwords = 0; - ctx->flags = 0; - -#if 0 - if (streamout_suspended) { - ctx->streamout_start = TRUE; - ctx->streamout_append_bitmask = ~0; - } -#endif - - /* resume queries */ - if (queries_suspended) { - r600_context_queries_resume(ctx); - } - - /* set all valid group as dirty so they get reemited on - * next draw command - */ - si_pm4_reset_emitted(ctx); -} - -void si_context_emit_fence(struct r600_context *ctx, struct si_resource *fence_bo, unsigned offset, unsigned value) -{ - struct radeon_winsys_cs *cs = ctx->cs; - uint64_t va; - - si_need_cs_space(ctx, 10, FALSE); - - va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo); - va = va + (offset << 2); - - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); - cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */ - /* DATA_SEL | INT_EN | ADDRESS_HI */ - cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF); - cs->buf[cs->cdw++] = value; /* DATA_LO */ - cs->buf[cs->cdw++] = 0; /* DATA_HI */ - cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE); -} - -static unsigned r600_query_read_result(char *map, unsigned start_index, unsigned end_index, - bool test_status_bit) -{ - uint32_t *current_result = (uint32_t*)map; - uint64_t start, end; - - start = (uint64_t)current_result[start_index] | - (uint64_t)current_result[start_index+1] << 32; - end = (uint64_t)current_result[end_index] | - (uint64_t)current_result[end_index+1] << 32; - - if (!test_status_bit || - ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) { - return end - start; - } - return 0; -} - -static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait) -{ - unsigned results_base = query->results_start; - char *map; - - map = ctx->ws->buffer_map(query->buffer->cs_buf, ctx->cs, - PIPE_TRANSFER_READ | - (wait ? 0 : PIPE_TRANSFER_DONTBLOCK)); - if (!map) - return FALSE; - - /* count all results across all data blocks */ - switch (query->type) { - case PIPE_QUERY_OCCLUSION_COUNTER: - while (results_base != query->results_end) { - query->result.u64 += - r600_query_read_result(map + results_base, 0, 2, true); - results_base = (results_base + 16) % query->buffer->b.b.width0; - } - break; - case PIPE_QUERY_OCCLUSION_PREDICATE: - while (results_base != query->results_end) { - query->result.b = query->result.b || - r600_query_read_result(map + results_base, 0, 2, true) != 0; - results_base = (results_base + 16) % query->buffer->b.b.width0; - } - break; - case PIPE_QUERY_TIME_ELAPSED: - while (results_base != query->results_end) { - query->result.u64 += - r600_query_read_result(map + results_base, 0, 2, false); - results_base = (results_base + query->result_size) % query->buffer->b.b.width0; - } - break; - case PIPE_QUERY_PRIMITIVES_EMITTED: - /* SAMPLE_STREAMOUTSTATS stores this structure: - * { - * u64 NumPrimitivesWritten; - * u64 PrimitiveStorageNeeded; - * } - * We only need NumPrimitivesWritten here. */ - while (results_base != query->results_end) { - query->result.u64 += - r600_query_read_result(map + results_base, 2, 6, true); - results_base = (results_base + query->result_size) % query->buffer->b.b.width0; - } - break; - case PIPE_QUERY_PRIMITIVES_GENERATED: - /* Here we read PrimitiveStorageNeeded. */ - while (results_base != query->results_end) { - query->result.u64 += - r600_query_read_result(map + results_base, 0, 4, true); - results_base = (results_base + query->result_size) % query->buffer->b.b.width0; - } - break; - case PIPE_QUERY_SO_STATISTICS: - while (results_base != query->results_end) { - query->result.so.num_primitives_written += - r600_query_read_result(map + results_base, 2, 6, true); - query->result.so.primitives_storage_needed += - r600_query_read_result(map + results_base, 0, 4, true); - results_base = (results_base + query->result_size) % query->buffer->b.b.width0; - } - break; - case PIPE_QUERY_SO_OVERFLOW_PREDICATE: - while (results_base != query->results_end) { - query->result.b = query->result.b || - r600_query_read_result(map + results_base, 2, 6, true) != - r600_query_read_result(map + results_base, 0, 4, true); - results_base = (results_base + query->result_size) % query->buffer->b.b.width0; - } - break; - default: - assert(0); - } - - query->results_start = query->results_end; - ctx->ws->buffer_unmap(query->buffer->cs_buf); - return TRUE; -} - -void r600_query_begin(struct r600_context *ctx, struct r600_query *query) -{ - struct radeon_winsys_cs *cs = ctx->cs; - unsigned new_results_end, i; - uint32_t *results; - uint64_t va; - - si_need_cs_space(ctx, query->num_cs_dw * 2, TRUE); - - new_results_end = (query->results_end + query->result_size) % query->buffer->b.b.width0; - - /* collect current results if query buffer is full */ - if (new_results_end == query->results_start) { - r600_query_result(ctx, query, TRUE); - } - - switch (query->type) { - case PIPE_QUERY_OCCLUSION_COUNTER: - case PIPE_QUERY_OCCLUSION_PREDICATE: - results = ctx->ws->buffer_map(query->buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE); - if (results) { - results = (uint32_t*)((char*)results + query->results_end); - memset(results, 0, query->result_size); - - /* Set top bits for unused backends */ - for (i = 0; i < ctx->max_db; i++) { - if (!(ctx->backend_mask & (1<ws->buffer_unmap(query->buffer->cs_buf); - } - break; - case PIPE_QUERY_TIME_ELAPSED: - break; - case PIPE_QUERY_PRIMITIVES_EMITTED: - case PIPE_QUERY_PRIMITIVES_GENERATED: - case PIPE_QUERY_SO_STATISTICS: - case PIPE_QUERY_SO_OVERFLOW_PREDICATE: - results = ctx->ws->buffer_map(query->buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE); - results = (uint32_t*)((char*)results + query->results_end); - memset(results, 0, query->result_size); - ctx->ws->buffer_unmap(query->buffer->cs_buf); - break; - default: - assert(0); - } - - /* emit begin query */ - va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); - va += query->results_end; - - switch (query->type) { - case PIPE_QUERY_OCCLUSION_COUNTER: - case PIPE_QUERY_OCCLUSION_PREDICATE: - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); - cs->buf[cs->cdw++] = va; - cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; - break; - case PIPE_QUERY_PRIMITIVES_EMITTED: - case PIPE_QUERY_PRIMITIVES_GENERATED: - case PIPE_QUERY_SO_STATISTICS: - case PIPE_QUERY_SO_OVERFLOW_PREDICATE: - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3); - cs->buf[cs->cdw++] = query->results_end; - cs->buf[cs->cdw++] = 0; - break; - case PIPE_QUERY_TIME_ELAPSED: - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); - cs->buf[cs->cdw++] = va; - cs->buf[cs->cdw++] = (3 << 29) | ((va >> 32UL) & 0xFF); - cs->buf[cs->cdw++] = 0; - cs->buf[cs->cdw++] = 0; - break; - default: - assert(0); - } - cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); - - ctx->num_cs_dw_queries_suspend += query->num_cs_dw; -} - -void r600_query_end(struct r600_context *ctx, struct r600_query *query) -{ - struct radeon_winsys_cs *cs = ctx->cs; - uint64_t va; - - va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); - /* emit end query */ - switch (query->type) { - case PIPE_QUERY_OCCLUSION_COUNTER: - case PIPE_QUERY_OCCLUSION_PREDICATE: - va += query->results_end + 8; - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); - cs->buf[cs->cdw++] = va; - cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; - break; - case PIPE_QUERY_PRIMITIVES_EMITTED: - case PIPE_QUERY_PRIMITIVES_GENERATED: - case PIPE_QUERY_SO_STATISTICS: - case PIPE_QUERY_SO_OVERFLOW_PREDICATE: - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3); - cs->buf[cs->cdw++] = query->results_end + query->result_size/2; - cs->buf[cs->cdw++] = 0; - break; - case PIPE_QUERY_TIME_ELAPSED: - va += query->results_end + query->result_size/2; - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); - cs->buf[cs->cdw++] = va; - cs->buf[cs->cdw++] = (3 << 29) | ((va >> 32UL) & 0xFF); - cs->buf[cs->cdw++] = 0; - cs->buf[cs->cdw++] = 0; - break; - default: - assert(0); - } - cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); - - query->results_end = (query->results_end + query->result_size) % query->buffer->b.b.width0; - ctx->num_cs_dw_queries_suspend -= query->num_cs_dw; -} - -void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, - int flag_wait) -{ - struct radeon_winsys_cs *cs = ctx->cs; - uint64_t va; - - if (operation == PREDICATION_OP_CLEAR) { - si_need_cs_space(ctx, 3, FALSE); - - cs->buf[cs->cdw++] = PKT3(PKT3_SET_PREDICATION, 1, 0); - cs->buf[cs->cdw++] = 0; - cs->buf[cs->cdw++] = PRED_OP(PREDICATION_OP_CLEAR); - } else { - unsigned results_base = query->results_start; - unsigned count; - uint32_t op; - - /* find count of the query data blocks */ - count = (query->buffer->b.b.width0 + query->results_end - query->results_start) % query->buffer->b.b.width0; - count /= query->result_size; - - si_need_cs_space(ctx, 5 * count, TRUE); - - op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE | - (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW); - va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); - - /* emit predicate packets for all data blocks */ - while (results_base != query->results_end) { - cs->buf[cs->cdw++] = PKT3(PKT3_SET_PREDICATION, 1, 0); - cs->buf[cs->cdw++] = (va + results_base) & 0xFFFFFFFFUL; - cs->buf[cs->cdw++] = op | (((va + results_base) >> 32UL) & 0xFF); - cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, - RADEON_USAGE_READ); - results_base = (results_base + query->result_size) % query->buffer->b.b.width0; - - /* set CONTINUE bit for all packets except the first */ - op |= PREDICATION_CONTINUE; - } - } -} - -struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type) -{ - struct r600_query *query; - unsigned buffer_size = 4096; - - query = CALLOC_STRUCT(r600_query); - if (query == NULL) - return NULL; - - query->type = query_type; - - switch (query_type) { - case PIPE_QUERY_OCCLUSION_COUNTER: - case PIPE_QUERY_OCCLUSION_PREDICATE: - query->result_size = 16 * ctx->max_db; - query->num_cs_dw = 6; - break; - case PIPE_QUERY_TIME_ELAPSED: - query->result_size = 16; - query->num_cs_dw = 8; - break; - case PIPE_QUERY_PRIMITIVES_EMITTED: - case PIPE_QUERY_PRIMITIVES_GENERATED: - case PIPE_QUERY_SO_STATISTICS: - case PIPE_QUERY_SO_OVERFLOW_PREDICATE: - /* NumPrimitivesWritten, PrimitiveStorageNeeded. */ - query->result_size = 32; - query->num_cs_dw = 6; - break; - default: - assert(0); - FREE(query); - return NULL; - } - - /* adjust buffer size to simplify offsets wrapping math */ - buffer_size -= buffer_size % query->result_size; - - /* Queries are normally read by the CPU after - * being written by the gpu, hence staging is probably a good - * usage pattern. - */ - query->buffer = si_resource_create_custom(&ctx->screen->screen, - PIPE_USAGE_STAGING, - buffer_size); - if (!query->buffer) { - FREE(query); - return NULL; - } - return query; -} - -void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query) -{ - si_resource_reference(&query->buffer, NULL); - free(query); -} - -boolean r600_context_query_result(struct r600_context *ctx, - struct r600_query *query, - boolean wait, void *vresult) -{ - boolean *result_b = (boolean*)vresult; - uint64_t *result_u64 = (uint64_t*)vresult; - struct pipe_query_data_so_statistics *result_so = - (struct pipe_query_data_so_statistics*)vresult; - - if (!r600_query_result(ctx, query, wait)) - return FALSE; - - switch (query->type) { - case PIPE_QUERY_OCCLUSION_COUNTER: - case PIPE_QUERY_PRIMITIVES_EMITTED: - case PIPE_QUERY_PRIMITIVES_GENERATED: - *result_u64 = query->result.u64; - break; - case PIPE_QUERY_OCCLUSION_PREDICATE: - case PIPE_QUERY_SO_OVERFLOW_PREDICATE: - *result_b = query->result.b; - break; - case PIPE_QUERY_TIME_ELAPSED: - *result_u64 = (1000000 * query->result.u64) / ctx->screen->info.r600_clock_crystal_freq; - break; - case PIPE_QUERY_SO_STATISTICS: - *result_so = query->result.so; - break; - default: - assert(0); - } - return TRUE; -} - -void r600_context_queries_suspend(struct r600_context *ctx) -{ - struct r600_query *query; - - LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) { - r600_query_end(ctx, query); - } - assert(ctx->num_cs_dw_queries_suspend == 0); -} - -void r600_context_queries_resume(struct r600_context *ctx) -{ - struct r600_query *query; - - assert(ctx->num_cs_dw_queries_suspend == 0); - - LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) { - r600_query_begin(ctx, query); - } -} - -void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t) -{ - struct radeon_winsys_cs *cs = ctx->cs; - si_need_cs_space(ctx, 14 + 21, TRUE); - - cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); - cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - SI_CONTEXT_REG_OFFSET) >> 2; - cs->buf[cs->cdw++] = 0; - - cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); - cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - SI_CONTEXT_REG_OFFSET) >> 2; - cs->buf[cs->cdw++] = t->stride >> 2; - -#if 0 - cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0); - cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG; - cs->buf[cs->cdw++] = 0; /* src address lo */ - cs->buf[cs->cdw++] = 0; /* src address hi */ - cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */ - cs->buf[cs->cdw++] = 0; /* unused */ -#endif - - cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ); - -} - -#if R600_TRACE_CS -void r600_trace_emit(struct r600_context *rctx) -{ - struct r600_screen *rscreen = rctx->screen; - struct radeon_winsys_cs *cs = rctx->cs; - uint64_t va; - - va = r600_resource_va(&rscreen->screen, (void*)rscreen->trace_bo); - r600_context_bo_reloc(rctx, rscreen->trace_bo, RADEON_USAGE_READWRITE); - cs->buf[cs->cdw++] = PKT3(PKT3_WRITE_DATA, 4, 0); - cs->buf[cs->cdw++] = PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) | - PKT3_WRITE_DATA_WR_CONFIRM | - PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME); - cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; - cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFFFFFFFUL; - cs->buf[cs->cdw++] = cs->cdw; - cs->buf[cs->cdw++] = rscreen->cs_count; -} -#endif diff -uNr a/src/gallium/drivers/radeonsi/r600_hw_context_priv.h b/src/gallium/drivers/radeonsi/r600_hw_context_priv.h --- a/src/gallium/drivers/radeonsi/r600_hw_context_priv.h 2013-06-27 20:13:13.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/r600_hw_context_priv.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,45 +0,0 @@ -/* - * Copyright 2010 Jerome Glisse - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jerome Glisse - */ -#ifndef R600_PRIV_H -#define R600_PRIV_H - -#include "radeonsi_pipe.h" -#include "util/u_hash_table.h" -#include "os/os_thread.h" - -#define SI_MAX_DRAW_CS_DWORDS 18 - -#define PKT_COUNT_C 0xC000FFFF -#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) - -static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct si_resource *rbo, - enum radeon_bo_usage usage) -{ - assert(usage); - return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; -} - -#endif diff -uNr a/src/gallium/drivers/radeonsi/r600_query.c b/src/gallium/drivers/radeonsi/r600_query.c --- a/src/gallium/drivers/radeonsi/r600_query.c 2013-08-14 03:34:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/r600_query.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,132 +0,0 @@ -/* - * Copyright 2010 Jerome Glisse - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#include "radeonsi_pipe.h" -#include "sid.h" - -static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - - return (struct pipe_query*)r600_context_query_create(rctx, query_type); -} - -static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - - r600_context_query_destroy(rctx, (struct r600_query *)query); -} - -static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_query *rquery = (struct r600_query *)query; - - memset(&rquery->result, 0, sizeof(rquery->result)); - rquery->results_start = rquery->results_end; - r600_query_begin(rctx, (struct r600_query *)query); - LIST_ADDTAIL(&rquery->list, &rctx->active_query_list); -} - -static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_query *rquery = (struct r600_query *)query; - - r600_query_end(rctx, rquery); - LIST_DELINIT(&rquery->list); -} - -static boolean r600_get_query_result(struct pipe_context *ctx, - struct pipe_query *query, - boolean wait, union pipe_query_result *vresult) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_query *rquery = (struct r600_query *)query; - - return r600_context_query_result(rctx, rquery, wait, vresult); -} - -static void r600_render_condition(struct pipe_context *ctx, - struct pipe_query *query, - boolean condition, - uint mode) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_query *rquery = (struct r600_query *)query; - int wait_flag = 0; - - /* If we already have nonzero result, render unconditionally */ - if (query != NULL && rquery->result.u64 != 0) { - if (rctx->current_render_cond) { - r600_render_condition(ctx, NULL, FALSE, 0); - } - return; - } - - rctx->current_render_cond = query; - rctx->current_render_cond_cond = condition; - rctx->current_render_cond_mode = mode; - - if (query == NULL) { - if (rctx->predicate_drawing) { - rctx->predicate_drawing = false; - r600_query_predication(rctx, NULL, PREDICATION_OP_CLEAR, 1); - } - return; - } - - if (mode == PIPE_RENDER_COND_WAIT || - mode == PIPE_RENDER_COND_BY_REGION_WAIT) { - wait_flag = 1; - } - - rctx->predicate_drawing = true; - - switch (rquery->type) { - case PIPE_QUERY_OCCLUSION_COUNTER: - case PIPE_QUERY_OCCLUSION_PREDICATE: - r600_query_predication(rctx, rquery, PREDICATION_OP_ZPASS, wait_flag); - break; - case PIPE_QUERY_PRIMITIVES_EMITTED: - case PIPE_QUERY_PRIMITIVES_GENERATED: - case PIPE_QUERY_SO_STATISTICS: - case PIPE_QUERY_SO_OVERFLOW_PREDICATE: - r600_query_predication(rctx, rquery, PREDICATION_OP_PRIMCOUNT, wait_flag); - break; - default: - assert(0); - } -} - -void r600_init_query_functions(struct r600_context *rctx) -{ - rctx->context.create_query = r600_create_query; - rctx->context.destroy_query = r600_destroy_query; - rctx->context.begin_query = r600_begin_query; - rctx->context.end_query = r600_end_query; - rctx->context.get_query_result = r600_get_query_result; - - if (rctx->screen->info.r600_num_backends > 0) - rctx->context.render_condition = r600_render_condition; -} diff -uNr a/src/gallium/drivers/radeonsi/r600_resource.c b/src/gallium/drivers/radeonsi/r600_resource.c --- a/src/gallium/drivers/radeonsi/r600_resource.c 2013-06-27 20:13:13.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/r600_resource.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,61 +0,0 @@ -/* - * Copyright 2010 Marek Olšák target == PIPE_BUFFER) { - return si_buffer_create(screen, templ); - } else { - return si_texture_create(screen, templ); - } -} - -static struct pipe_resource *r600_resource_from_handle(struct pipe_screen * screen, - const struct pipe_resource *templ, - struct winsys_handle *whandle) -{ - if (templ->target == PIPE_BUFFER) { - return NULL; - } else { - return si_texture_from_handle(screen, templ, whandle); - } -} - -void r600_init_screen_resource_functions(struct pipe_screen *screen) -{ - screen->resource_create = r600_resource_create; - screen->resource_from_handle = r600_resource_from_handle; - screen->resource_get_handle = u_resource_get_handle_vtbl; - screen->resource_destroy = u_resource_destroy_vtbl; -} - -void r600_init_context_resource_functions(struct r600_context *r600) -{ - r600->context.transfer_map = u_transfer_map_vtbl; - r600->context.transfer_flush_region = u_transfer_flush_region_vtbl; - r600->context.transfer_unmap = u_transfer_unmap_vtbl; - r600->context.transfer_inline_write = u_default_transfer_inline_write; -} diff -uNr a/src/gallium/drivers/radeonsi/r600_resource.h b/src/gallium/drivers/radeonsi/r600_resource.h --- a/src/gallium/drivers/radeonsi/r600_resource.h 2013-06-27 20:13:13.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/r600_resource.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,82 +0,0 @@ -/* - * Copyright 2010 Marek Olšák - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jerome Glisse - * Corbin Simpson - */ -#include -#include "pipe/p_screen.h" -#include "util/u_format.h" -#include "util/u_format_s3tc.h" -#include "util/u_math.h" -#include "util/u_inlines.h" -#include "util/u_memory.h" -#include "pipebuffer/pb_buffer.h" -#include "radeonsi_pipe.h" -#include "r600_resource.h" -#include "sid.h" - -/* Copy from a full GPU texture to a transfer's staging one. */ -static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) -{ - struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; - struct pipe_resource *texture = transfer->resource; - - ctx->resource_copy_region(ctx, rtransfer->staging, - 0, 0, 0, 0, texture, transfer->level, - &transfer->box); -} - -/* Copy from a transfer's staging texture to a full GPU one. */ -static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) -{ - struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; - struct pipe_resource *texture = transfer->resource; - struct pipe_box sbox; - - u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox); - - ctx->resource_copy_region(ctx, texture, transfer->level, - transfer->box.x, transfer->box.y, transfer->box.z, - rtransfer->staging, - 0, &sbox); -} - -static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, - unsigned level, unsigned layer) -{ - return rtex->surface.level[level].offset + - layer * rtex->surface.level[level].slice_size; -} - -static int r600_init_surface(struct r600_screen *rscreen, - struct radeon_surface *surface, - const struct pipe_resource *ptex, - unsigned array_mode, - bool is_flushed_depth) -{ - const struct util_format_description *desc = - util_format_description(ptex->format); - bool is_depth, is_stencil; - - is_depth = util_format_has_depth(desc); - is_stencil = util_format_has_stencil(desc); - - surface->npix_x = ptex->width0; - surface->npix_y = ptex->height0; - surface->npix_z = ptex->depth0; - surface->blk_w = util_format_get_blockwidth(ptex->format); - surface->blk_h = util_format_get_blockheight(ptex->format); - surface->blk_d = 1; - surface->array_size = 1; - surface->last_level = ptex->last_level; - - if (!is_flushed_depth && - ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { - surface->bpe = 4; /* stencil is allocated separately on evergreen */ - } else { - surface->bpe = util_format_get_blocksize(ptex->format); - /* align byte per element on dword */ - if (surface->bpe == 3) { - surface->bpe = 4; - } - } - - surface->nsamples = 1; - surface->flags = 0; - switch (array_mode) { - case V_009910_ARRAY_1D_TILED_THIN1: - surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); - break; - case V_009910_ARRAY_2D_TILED_THIN1: - surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); - break; - case V_009910_ARRAY_LINEAR_ALIGNED: - surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); - break; - case V_009910_ARRAY_LINEAR_GENERAL: - default: - surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); - break; - } - switch (ptex->target) { - case PIPE_TEXTURE_1D: - surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE); - break; - case PIPE_TEXTURE_RECT: - case PIPE_TEXTURE_2D: - surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); - break; - case PIPE_TEXTURE_3D: - surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE); - break; - case PIPE_TEXTURE_1D_ARRAY: - surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE); - surface->array_size = ptex->array_size; - break; - case PIPE_TEXTURE_2D_ARRAY: - surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE); - surface->array_size = ptex->array_size; - break; - case PIPE_TEXTURE_CUBE: - surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE); - break; - case PIPE_BUFFER: - default: - return -EINVAL; - } - if (ptex->bind & PIPE_BIND_SCANOUT) { - surface->flags |= RADEON_SURF_SCANOUT; - } - - if (!is_flushed_depth && is_depth) { - surface->flags |= RADEON_SURF_ZBUFFER; - if (is_stencil) { - surface->flags |= RADEON_SURF_SBUFFER | - RADEON_SURF_HAS_SBUFFER_MIPTREE; - } - } - surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; - return 0; -} - -static int r600_setup_surface(struct pipe_screen *screen, - struct r600_resource_texture *rtex, - unsigned array_mode, - unsigned pitch_in_bytes_override) -{ - struct r600_screen *rscreen = (struct r600_screen*)screen; - int r; - - r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface); - if (r) { - return r; - } - if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) { - /* old ddx on evergreen over estimate alignment for 1d, only 1 level - * for those - */ - rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe; - rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override; - rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y; - if (rtex->surface.flags & RADEON_SURF_SBUFFER) { - rtex->surface.stencil_offset = - rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size; - } - } - return 0; -} - -static boolean r600_texture_get_handle(struct pipe_screen* screen, - struct pipe_resource *ptex, - struct winsys_handle *whandle) -{ - struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; - struct si_resource *resource = &rtex->resource; - struct radeon_surface *surface = &rtex->surface; - struct r600_screen *rscreen = (struct r600_screen*)screen; - - rscreen->ws->buffer_set_tiling(resource->buf, - NULL, - surface->level[0].mode >= RADEON_SURF_MODE_1D ? - RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, - surface->level[0].mode >= RADEON_SURF_MODE_2D ? - RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, - surface->bankw, surface->bankh, - surface->tile_split, - surface->stencil_tile_split, - surface->mtilea, - surface->level[0].pitch_bytes); - - return rscreen->ws->buffer_get_handle(resource->buf, - surface->level[0].pitch_bytes, whandle); -} - -static void r600_texture_destroy(struct pipe_screen *screen, - struct pipe_resource *ptex) -{ - struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; - struct si_resource *resource = &rtex->resource; - - if (rtex->flushed_depth_texture) - si_resource_reference((struct si_resource **)&rtex->flushed_depth_texture, NULL); - - pb_reference(&resource->buf, NULL); - FREE(rtex); -} - -static void *si_texture_transfer_map(struct pipe_context *ctx, - struct pipe_resource *texture, - unsigned level, - unsigned usage, - const struct pipe_box *box, - struct pipe_transfer **ptransfer) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; - struct r600_transfer *trans; - boolean use_staging_texture = FALSE; - struct radeon_winsys_cs_handle *buf; - enum pipe_format format = texture->format; - unsigned offset = 0; - char *map; - - /* We cannot map a tiled texture directly because the data is - * in a different order, therefore we do detiling using a blit. - * - * Also, use a temporary in GTT memory for read transfers, as - * the CPU is much happier reading out of cached system memory - * than uncached VRAM. - */ - if (rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR_ALIGNED && - rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR) - use_staging_texture = TRUE; - - /* XXX: Use a staging texture for uploads if the underlying BO - * is busy. No interface for checking that currently? so do - * it eagerly whenever the transfer doesn't require a readback - * and might block. - */ - if ((usage & PIPE_TRANSFER_WRITE) && - !(usage & (PIPE_TRANSFER_READ | - PIPE_TRANSFER_DONTBLOCK | - PIPE_TRANSFER_UNSYNCHRONIZED))) - use_staging_texture = TRUE; - - if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) - use_staging_texture = FALSE; - - if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) - return NULL; - - trans = CALLOC_STRUCT(r600_transfer); - if (trans == NULL) - return NULL; - pipe_resource_reference(&trans->transfer.resource, texture); - trans->transfer.level = level; - trans->transfer.usage = usage; - trans->transfer.box = *box; - if (rtex->is_depth) { - /* XXX: only readback the rectangle which is being mapped? - */ - /* XXX: when discard is true, no need to read back from depth texture - */ - struct r600_resource_texture *staging_depth; - - if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) { - R600_ERR("failed to create temporary texture to hold untiled copy\n"); - pipe_resource_reference(&trans->transfer.resource, NULL); - FREE(trans); - return NULL; - } - si_blit_uncompress_depth(ctx, rtex, staging_depth, - level, level, - box->z, box->z + box->depth - 1); - trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes; - trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size; - trans->offset = r600_texture_get_offset(staging_depth, level, box->z); - - trans->staging = &staging_depth->resource.b.b; - } else if (use_staging_texture) { - struct pipe_resource resource; - struct r600_resource_texture *staging; - - memset(&resource, 0, sizeof(resource)); - resource.format = texture->format; - resource.width0 = box->width; - resource.height0 = box->height; - resource.depth0 = 1; - resource.array_size = 1; - resource.usage = PIPE_USAGE_STAGING; - resource.flags = R600_RESOURCE_FLAG_TRANSFER; - - /* We must set the correct texture target and dimensions if needed for a 3D transfer. */ - if (box->depth > 1 && util_max_layer(texture, level) > 0) - resource.target = texture->target; - else - resource.target = PIPE_TEXTURE_2D; - - switch (resource.target) { - case PIPE_TEXTURE_1D_ARRAY: - case PIPE_TEXTURE_2D_ARRAY: - case PIPE_TEXTURE_CUBE_ARRAY: - resource.array_size = box->depth; - break; - case PIPE_TEXTURE_3D: - resource.depth0 = box->depth; - break; - default:; - } - /* Create the temporary texture. */ - staging = (struct r600_resource_texture*)ctx->screen->resource_create(ctx->screen, &resource); - if (staging == NULL) { - R600_ERR("failed to create temporary texture to hold untiled copy\n"); - pipe_resource_reference(&trans->transfer.resource, NULL); - FREE(trans); - return NULL; - } - - trans->staging = &staging->resource.b.b; - trans->transfer.stride = staging->surface.level[0].pitch_bytes; - trans->transfer.layer_stride = staging->surface.level[0].slice_size; - if (usage & PIPE_TRANSFER_READ) { - r600_copy_to_staging_texture(ctx, trans); - /* Always referenced in the blit. */ - radeonsi_flush(ctx, NULL, 0); - } - } else { - trans->transfer.stride = rtex->surface.level[level].pitch_bytes; - trans->transfer.layer_stride = rtex->surface.level[level].slice_size; - trans->offset = r600_texture_get_offset(rtex, level, box->z); - } - - if (trans->staging) { - buf = si_resource(trans->staging)->cs_buf; - } else { - buf = rtex->resource.cs_buf; - } - - if (rtex->is_depth || !trans->staging) - offset = trans->offset + - box->y / util_format_get_blockheight(format) * trans->transfer.stride + - box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); - - if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) { - pipe_resource_reference(&trans->staging, NULL); - pipe_resource_reference(&trans->transfer.resource, NULL); - FREE(trans); - return NULL; - } - - *ptransfer = &trans->transfer; - return map + offset; -} - -static void si_texture_transfer_unmap(struct pipe_context *ctx, - struct pipe_transfer* transfer) -{ - struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; - struct r600_context *rctx = (struct r600_context*)ctx; - struct radeon_winsys_cs_handle *buf; - struct pipe_resource *texture = transfer->resource; - struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; - - if (rtransfer->staging) { - buf = si_resource(rtransfer->staging)->cs_buf; - } else { - buf = si_resource(transfer->resource)->cs_buf; - } - rctx->ws->buffer_unmap(buf); - - if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) { - if (rtex->is_depth) { - ctx->resource_copy_region(ctx, texture, transfer->level, - transfer->box.x, transfer->box.y, transfer->box.z, - &si_resource(rtransfer->staging)->b.b, transfer->level, - &transfer->box); - } else { - r600_copy_from_staging_texture(ctx, rtransfer); - } - } - - if (rtransfer->staging) - pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL); - - pipe_resource_reference(&transfer->resource, NULL); - FREE(transfer); -} - -static const struct u_resource_vtbl r600_texture_vtbl = -{ - r600_texture_get_handle, /* get_handle */ - r600_texture_destroy, /* resource_destroy */ - si_texture_transfer_map, /* transfer_map */ - u_default_transfer_flush_region,/* transfer_flush_region */ - si_texture_transfer_unmap, /* transfer_unmap */ - NULL /* transfer_inline_write */ -}; - -DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "RADEON_PRINT_TEXDEPTH", FALSE); - -static struct r600_resource_texture * -r600_texture_create_object(struct pipe_screen *screen, - const struct pipe_resource *base, - unsigned array_mode, - unsigned pitch_in_bytes_override, - unsigned max_buffer_size, - struct pb_buffer *buf, - boolean alloc_bo, - struct radeon_surface *surface) -{ - struct r600_resource_texture *rtex; - struct si_resource *resource; - struct r600_screen *rscreen = (struct r600_screen*)screen; - int r; - - rtex = CALLOC_STRUCT(r600_resource_texture); - if (rtex == NULL) - return NULL; - - resource = &rtex->resource; - resource->b.b = *base; - resource->b.vtbl = &r600_texture_vtbl; - pipe_reference_init(&resource->b.b.reference, 1); - resource->b.b.screen = screen; - rtex->pitch_override = pitch_in_bytes_override; - rtex->real_format = base->format; - - /* don't include stencil-only formats which we don't support for rendering */ - rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format)); - - rtex->surface = *surface; - r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override); - if (r) { - FREE(rtex); - return NULL; - } - - /* Now create the backing buffer. */ - if (!buf && alloc_bo) { - unsigned base_align = rtex->surface.bo_alignment; - unsigned size = rtex->surface.bo_size; - - base_align = rtex->surface.bo_alignment; - if (!si_init_resource(rscreen, resource, size, base_align, FALSE, base->usage)) { - FREE(rtex); - return NULL; - } - } else if (buf) { - resource->buf = buf; - resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); - resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; - } - - if (debug_get_option_print_texdepth() && rtex->is_depth) { - printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, " - "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, " - "bpe=%u, nsamples=%u, flags=%u\n", - rtex->surface.npix_x, rtex->surface.npix_y, - rtex->surface.npix_z, rtex->surface.blk_w, - rtex->surface.blk_h, rtex->surface.blk_d, - rtex->surface.array_size, rtex->surface.last_level, - rtex->surface.bpe, rtex->surface.nsamples, - rtex->surface.flags); - if (rtex->surface.flags & RADEON_SURF_ZBUFFER) { - for (int i = 0; i <= rtex->surface.last_level; i++) { - printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, " - "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " - "nblk_z=%u, pitch_bytes=%u, mode=%u\n", - i, rtex->surface.level[i].offset, - rtex->surface.level[i].slice_size, - rtex->surface.level[i].npix_x, - rtex->surface.level[i].npix_y, - rtex->surface.level[i].npix_z, - rtex->surface.level[i].nblk_x, - rtex->surface.level[i].nblk_y, - rtex->surface.level[i].nblk_z, - rtex->surface.level[i].pitch_bytes, - rtex->surface.level[i].mode); - } - } - if (rtex->surface.flags & RADEON_SURF_SBUFFER) { - for (int i = 0; i <= rtex->surface.last_level; i++) { - printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, " - "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " - "nblk_z=%u, pitch_bytes=%u, mode=%u\n", - i, rtex->surface.stencil_level[i].offset, - rtex->surface.stencil_level[i].slice_size, - rtex->surface.stencil_level[i].npix_x, - rtex->surface.stencil_level[i].npix_y, - rtex->surface.stencil_level[i].npix_z, - rtex->surface.stencil_level[i].nblk_x, - rtex->surface.stencil_level[i].nblk_y, - rtex->surface.stencil_level[i].nblk_z, - rtex->surface.stencil_level[i].pitch_bytes, - rtex->surface.stencil_level[i].mode); - } - } - } - return rtex; -} - -struct pipe_resource *si_texture_create(struct pipe_screen *screen, - const struct pipe_resource *templ) -{ - struct r600_screen *rscreen = (struct r600_screen*)screen; - struct radeon_surface surface; - unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED; - int r; - - if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) && - !(templ->bind & PIPE_BIND_SCANOUT)) { - if (util_format_is_compressed(templ->format)) { - array_mode = V_009910_ARRAY_1D_TILED_THIN1; - } else { - if (rscreen->chip_class >= CIK) - array_mode = V_009910_ARRAY_1D_TILED_THIN1; /* XXX fix me */ - else - array_mode = V_009910_ARRAY_2D_TILED_THIN1; - } - } - - r = r600_init_surface(rscreen, &surface, templ, array_mode, - templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH); - if (r) { - return NULL; - } - r = rscreen->ws->surface_best(rscreen->ws, &surface); - if (r) { - return NULL; - } - return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, - 0, 0, NULL, TRUE, &surface); -} - -static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, - struct pipe_resource *texture, - const struct pipe_surface *surf_tmpl) -{ - struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; - struct r600_surface *surface = CALLOC_STRUCT(r600_surface); - unsigned level = surf_tmpl->u.tex.level; - - assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level)); - assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level)); - assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); - if (surface == NULL) - return NULL; - /* XXX no offset */ -/* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/ - pipe_reference_init(&surface->base.reference, 1); - pipe_resource_reference(&surface->base.texture, texture); - surface->base.context = pipe; - surface->base.format = surf_tmpl->format; - surface->base.width = rtex->surface.level[level].npix_x; - surface->base.height = rtex->surface.level[level].npix_y; - surface->base.texture = texture; - surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer; - surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer; - surface->base.u.tex.level = level; - - return &surface->base; -} - -static void r600_surface_destroy(struct pipe_context *pipe, - struct pipe_surface *surface) -{ - pipe_resource_reference(&surface->texture, NULL); - FREE(surface); -} - -struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, - const struct pipe_resource *templ, - struct winsys_handle *whandle) -{ - struct r600_screen *rscreen = (struct r600_screen*)screen; - struct pb_buffer *buf = NULL; - unsigned stride = 0; - unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED; - enum radeon_bo_layout micro, macro; - struct radeon_surface surface; - int r; - - /* Support only 2D textures without mipmaps */ - if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || - templ->depth0 != 1 || templ->last_level != 0) - return NULL; - - buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); - if (!buf) - return NULL; - - rscreen->ws->buffer_get_tiling(buf, µ, ¯o, - &surface.bankw, &surface.bankh, - &surface.tile_split, - &surface.stencil_tile_split, - &surface.mtilea); - - if (macro == RADEON_LAYOUT_TILED) - array_mode = V_009910_ARRAY_2D_TILED_THIN1; - else if (micro == RADEON_LAYOUT_TILED) - array_mode = V_009910_ARRAY_1D_TILED_THIN1; - else - array_mode = V_009910_ARRAY_LINEAR_ALIGNED; - - r = r600_init_surface(rscreen, &surface, templ, array_mode, false); - if (r) { - return NULL; - } - /* always set the scanout flags */ - surface.flags |= RADEON_SURF_SCANOUT; - return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, - stride, 0, buf, FALSE, &surface); -} - -bool r600_init_flushed_depth_texture(struct pipe_context *ctx, - struct pipe_resource *texture, - struct r600_resource_texture **staging) -{ - struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; - struct pipe_resource resource; - struct r600_resource_texture **flushed_depth_texture = staging ? - staging : &rtex->flushed_depth_texture; - - if (!staging && rtex->flushed_depth_texture) - return true; /* it's ready */ - - resource.target = texture->target; - resource.format = texture->format; - resource.width0 = texture->width0; - resource.height0 = texture->height0; - resource.depth0 = texture->depth0; - resource.array_size = texture->array_size; - resource.last_level = texture->last_level; - resource.nr_samples = texture->nr_samples; - resource.usage = staging ? PIPE_USAGE_DYNAMIC : PIPE_USAGE_DEFAULT; - resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL; - resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH; - - if (staging) - resource.flags |= R600_RESOURCE_FLAG_TRANSFER; - else - rtex->dirty_db_mask = (1 << (resource.last_level+1)) - 1; - - *flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource); - if (*flushed_depth_texture == NULL) { - R600_ERR("failed to create temporary texture to hold flushed depth\n"); - return false; - } - - (*flushed_depth_texture)->is_flushing_texture = TRUE; - return true; -} - -void si_init_surface_functions(struct r600_context *r600) -{ - r600->context.create_surface = r600_create_surface; - r600->context.surface_destroy = r600_surface_destroy; -} diff -uNr a/src/gallium/drivers/radeonsi/r600_translate.c b/src/gallium/drivers/radeonsi/r600_translate.c --- a/src/gallium/drivers/radeonsi/r600_translate.c 2013-06-27 20:13:13.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/r600_translate.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,53 +0,0 @@ -/* - * Copyright 2010 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Dave Airlie - */ - -#include "util/u_index_modify.h" -#include "util/u_upload_mgr.h" -#include "radeonsi_pipe.h" - - -void r600_translate_index_buffer(struct r600_context *r600, - struct pipe_index_buffer *ib, - unsigned count) -{ - struct pipe_resource *out_buffer = NULL; - unsigned out_offset; - void *ptr; - - switch (ib->index_size) { - case 1: - u_upload_alloc(r600->uploader, 0, count * 2, - &out_offset, &out_buffer, &ptr); - - util_shorten_ubyte_elts_to_userptr( - &r600->context, ib, 0, ib->offset, count, ptr); - - pipe_resource_reference(&ib->buffer, NULL); - ib->buffer = out_buffer; - ib->offset = out_offset; - ib->index_size = 2; - break; - } -} diff -uNr a/src/gallium/drivers/radeonsi/radeonsi.h b/src/gallium/drivers/radeonsi/radeonsi.h --- a/src/gallium/drivers/radeonsi/radeonsi.h 1970-01-01 01:00:00.000000000 +0100 +++ b/src/gallium/drivers/radeonsi/radeonsi.h 2013-08-28 04:15:13.856313555 +0200 @@ -0,0 +1,109 @@ +/* + * Copyright 2010 Jerome Glisse + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef RADEONSI_H +#define RADEONSI_H + +#include "../../winsys/radeon/drm/radeon_winsys.h" +#include "util/u_double_list.h" +#include "util/u_transfer.h" + +#include "radeonsi_resource.h" + +#define RADEONSI_ERR(fmt, args...) \ + fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args) + +struct winsys_handle; + +struct radeonsi_tiling_info { + unsigned num_channels; + unsigned num_banks; + unsigned group_bytes; +}; + +/* R600/R700 STATES */ +struct radeonsi_query { + union { + uint64_t u64; + boolean b; + struct pipe_query_data_so_statistics so; + } result; + /* The kind of query */ + unsigned type; + /* Offset of the first result for current query */ + unsigned results_start; + /* Offset of the next free result after current query data */ + unsigned results_end; + /* Size of the result in memory for both begin_query and end_query, + * this can be one or two numbers, or it could even be a size of a structure. */ + unsigned result_size; + /* The buffer where query results are stored. It's used as a ring, + * data blocks for current query are stored sequentially from + * results_start to results_end, with wrapping on the buffer end */ + struct si_resource *buffer; + /* The number of dwords for begin_query or end_query. */ + unsigned num_cs_dw; + /* linked list of queries */ + struct list_head list; +}; + +struct radeonsi_so_target { + struct pipe_stream_output_target b; + + /* The buffer where BUFFER_FILLED_SIZE is stored. */ + struct si_resource *filled_size; + unsigned stride; + unsigned so_index; +}; + +#define RADEONSI_CONTEXT_DST_CACHES_DIRTY (1 << 1) +#define RADEONSI_CONTEXT_CHECK_EVENT_FLUSH (1 << 2) + +struct radeonsi_context; +struct radeonsi_screen; + +void si_get_backend_mask(struct radeonsi_context *ctx); +void si_context_flush(struct radeonsi_context *ctx, unsigned flags); + +struct radeonsi_query *radeonsi_context_query_create(struct radeonsi_context *ctx, unsigned query_type); +void radeonsi_context_query_destroy(struct radeonsi_context *ctx, struct radeonsi_query *query); +boolean radeonsi_context_query_result(struct radeonsi_context *ctx, + struct radeonsi_query *query, + boolean wait, void *vresult); +void radeonsi_query_begin(struct radeonsi_context *ctx, struct radeonsi_query *query); +void radeonsi_query_end(struct radeonsi_context *ctx, struct radeonsi_query *query); +void radeonsi_context_queries_suspend(struct radeonsi_context *ctx); +void radeonsi_context_queries_resume(struct radeonsi_context *ctx); +void radeonsi_query_predication(struct radeonsi_context *ctx, struct radeonsi_query *query, int operation, + int flag_wait); +void si_context_emit_fence(struct radeonsi_context *ctx, struct si_resource *fence, + unsigned offset, unsigned value); + +void radeonsi_context_draw_opaque_count(struct radeonsi_context *ctx, struct radeonsi_so_target *t); +void si_need_cs_space(struct radeonsi_context *ctx, unsigned num_dw, boolean count_draw_in); + +int si_context_init(struct radeonsi_context *ctx); + +#endif diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_blit.c b/src/gallium/drivers/radeonsi/radeonsi_blit.c --- a/src/gallium/drivers/radeonsi/radeonsi_blit.c 1970-01-01 01:00:00.000000000 +0100 +++ b/src/gallium/drivers/radeonsi/radeonsi_blit.c 2013-08-28 04:15:13.856313555 +0200 @@ -0,0 +1,501 @@ +/* + * Copyright 2010 Jerome Glisse + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include "util/u_surface.h" +#include "util/u_blitter.h" +#include "util/u_format.h" +#include "radeonsi_pipe.h" +#include "si_state.h" + +enum radeonsi_blitter_op /* bitmask */ +{ + RADEONSI_SAVE_TEXTURES = 1, + RADEONSI_SAVE_FRAMEBUFFER = 2, + RADEONSI_DISABLE_RENDER_COND = 4, + + RADEONSI_CLEAR = 0, + + RADEONSI_CLEAR_SURFACE = RADEONSI_SAVE_FRAMEBUFFER, + + RADEONSI_COPY = RADEONSI_SAVE_FRAMEBUFFER | RADEONSI_SAVE_TEXTURES | + RADEONSI_DISABLE_RENDER_COND, + + RADEONSI_BLIT = RADEONSI_SAVE_FRAMEBUFFER | RADEONSI_SAVE_TEXTURES | + RADEONSI_DISABLE_RENDER_COND, + + RADEONSI_DECOMPRESS = RADEONSI_SAVE_FRAMEBUFFER | RADEONSI_DISABLE_RENDER_COND, +}; + +static void radeonsi_blitter_begin(struct pipe_context *ctx, enum radeonsi_blitter_op op) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + + radeonsi_context_queries_suspend(rctx); + + util_blitter_save_blend(rctx->blitter, rctx->queued.named.blend); + util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->queued.named.dsa); + util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref); + util_blitter_save_rasterizer(rctx->blitter, rctx->queued.named.rasterizer); + util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader); + util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader); + util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements); + if (rctx->queued.named.viewport) { + util_blitter_save_viewport(rctx->blitter, &rctx->queued.named.viewport->viewport); + } + util_blitter_save_vertex_buffer_slot(rctx->blitter, rctx->vertex_buffer); + util_blitter_save_so_targets(rctx->blitter, rctx->num_so_targets, + (struct pipe_stream_output_target**)rctx->so_targets); + + if (op & RADEONSI_SAVE_FRAMEBUFFER) + util_blitter_save_framebuffer(rctx->blitter, &rctx->framebuffer); + + if (op & RADEONSI_SAVE_TEXTURES) { + util_blitter_save_fragment_sampler_states( + rctx->blitter, rctx->ps_samplers.n_samplers, + (void**)rctx->ps_samplers.samplers); + + util_blitter_save_fragment_sampler_views( + rctx->blitter, rctx->ps_samplers.n_views, + (struct pipe_sampler_view**)rctx->ps_samplers.views); + } + + if ((op & RADEONSI_DISABLE_RENDER_COND) && rctx->current_render_cond) { + rctx->saved_render_cond = rctx->current_render_cond; + rctx->saved_render_cond_cond = rctx->current_render_cond_cond; + rctx->saved_render_cond_mode = rctx->current_render_cond_mode; + rctx->context.render_condition(&rctx->context, NULL, FALSE, 0); + } + +} + +static void radeonsi_blitter_end(struct pipe_context *ctx) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + if (rctx->saved_render_cond) { + rctx->context.render_condition(&rctx->context, + rctx->saved_render_cond, + rctx->saved_render_cond_cond, + rctx->saved_render_cond_mode); + rctx->saved_render_cond = NULL; + } + radeonsi_context_queries_resume(rctx); +} + +void si_blit_uncompress_depth(struct pipe_context *ctx, + struct radeonsi_resource_texture *texture, + struct radeonsi_resource_texture *staging, + unsigned first_level, unsigned last_level, + unsigned first_layer, unsigned last_layer) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + unsigned layer, level, checked_last_layer, max_layer; + float depth = 1.0f; + const struct util_format_description *desc; + void *custom_dsa; + struct radeonsi_resource_texture *flushed_depth_texture = staging ? + staging : texture->flushed_depth_texture; + + if (!staging && !texture->dirty_db_mask) + return; + + desc = util_format_description(flushed_depth_texture->resource.b.b.format); + switch (util_format_has_depth(desc) | util_format_has_stencil(desc) << 1) { + default: + assert(!"No depth or stencil to uncompress"); + case 3: + custom_dsa = rctx->custom_dsa_flush_depth_stencil; + break; + case 2: + custom_dsa = rctx->custom_dsa_flush_stencil; + break; + case 1: + custom_dsa = rctx->custom_dsa_flush_depth; + break; + } + + for (level = first_level; level <= last_level; level++) { + if (!staging && !(texture->dirty_db_mask & (1 << level))) + continue; + + /* The smaller the mipmap level, the less layers there are + * as far as 3D textures are concerned. */ + max_layer = util_max_layer(&texture->resource.b.b, level); + checked_last_layer = last_layer < max_layer ? last_layer : max_layer; + + for (layer = first_layer; layer <= checked_last_layer; layer++) { + struct pipe_surface *zsurf, *cbsurf, surf_tmpl; + + surf_tmpl.format = texture->real_format; + surf_tmpl.u.tex.level = level; + surf_tmpl.u.tex.first_layer = layer; + surf_tmpl.u.tex.last_layer = layer; + + zsurf = ctx->create_surface(ctx, &texture->resource.b.b, &surf_tmpl); + + surf_tmpl.format = flushed_depth_texture->real_format; + cbsurf = ctx->create_surface(ctx, + (struct pipe_resource*)flushed_depth_texture, &surf_tmpl); + + radeonsi_blitter_begin(ctx, RADEONSI_DECOMPRESS); + util_blitter_custom_depth_stencil(rctx->blitter, zsurf, cbsurf, ~0, custom_dsa, depth); + radeonsi_blitter_end(ctx); + + pipe_surface_reference(&zsurf, NULL); + pipe_surface_reference(&cbsurf, NULL); + } + + /* The texture will always be dirty if some layers aren't flushed. + * I don't think this case can occur though. */ + if (!staging && first_layer == 0 && last_layer == max_layer) { + texture->dirty_db_mask &= ~(1 << level); + } + } +} + +static void si_blit_decompress_depth_in_place(struct radeonsi_context *rctx, + struct radeonsi_resource_texture *texture, + unsigned first_level, unsigned last_level, + unsigned first_layer, unsigned last_layer) +{ + struct pipe_surface *zsurf, surf_tmpl = {{0}}; + unsigned layer, max_layer, checked_last_layer, level; + + surf_tmpl.format = texture->resource.b.b.format; + + for (level = first_level; level <= last_level; level++) { + if (!(texture->dirty_db_mask & (1 << level))) + continue; + + surf_tmpl.u.tex.level = level; + + /* The smaller the mipmap level, the less layers there are + * as far as 3D textures are concerned. */ + max_layer = util_max_layer(&texture->resource.b.b, level); + checked_last_layer = last_layer < max_layer ? last_layer : max_layer; + + for (layer = first_layer; layer <= checked_last_layer; layer++) { + surf_tmpl.u.tex.first_layer = layer; + surf_tmpl.u.tex.last_layer = layer; + + zsurf = rctx->context.create_surface(&rctx->context, &texture->resource.b.b, &surf_tmpl); + + radeonsi_blitter_begin(&rctx->context, RADEONSI_DECOMPRESS); + util_blitter_custom_depth_stencil(rctx->blitter, zsurf, NULL, ~0, + rctx->custom_dsa_flush_inplace, + 1.0f); + radeonsi_blitter_end(&rctx->context); + + pipe_surface_reference(&zsurf, NULL); + } + + /* The texture will always be dirty if some layers aren't flushed. + * I don't think this case occurs often though. */ + if (first_layer == 0 && last_layer == max_layer) { + texture->dirty_db_mask &= ~(1 << level); + } + } +} + +void si_flush_depth_textures(struct radeonsi_context *rctx, + struct radeonsi_textures_info *textures) +{ + unsigned i; + + for (i = 0; i < textures->n_views; ++i) { + struct pipe_sampler_view *view; + struct radeonsi_resource_texture *tex; + + view = &textures->views[i]->base; + if (!view) continue; + + tex = (struct radeonsi_resource_texture *)view->texture; + if (!tex->is_depth || tex->is_flushing_texture) + continue; + + si_blit_decompress_depth_in_place(rctx, tex, + view->u.tex.first_level, view->u.tex.last_level, + 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level)); + } +} + +static void radeonsi_clear(struct pipe_context *ctx, unsigned buffers, + const union pipe_color_union *color, + double depth, unsigned stencil) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + struct pipe_framebuffer_state *fb = &rctx->framebuffer; + + radeonsi_blitter_begin(ctx, RADEONSI_CLEAR); + util_blitter_clear(rctx->blitter, fb->width, fb->height, + buffers, color, depth, stencil); + radeonsi_blitter_end(ctx); +} + +static void radeonsi_clear_render_target(struct pipe_context *ctx, + struct pipe_surface *dst, + const union pipe_color_union *color, + unsigned dstx, unsigned dsty, + unsigned width, unsigned height) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + + radeonsi_blitter_begin(ctx, RADEONSI_CLEAR_SURFACE); + util_blitter_clear_render_target(rctx->blitter, dst, color, + dstx, dsty, width, height); + radeonsi_blitter_end(ctx); +} + +static void radeonsi_clear_depth_stencil(struct pipe_context *ctx, + struct pipe_surface *dst, + unsigned clear_flags, + double depth, + unsigned stencil, + unsigned dstx, unsigned dsty, + unsigned width, unsigned height) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + + radeonsi_blitter_begin(ctx, RADEONSI_CLEAR_SURFACE); + util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil, + dstx, dsty, width, height); + radeonsi_blitter_end(ctx); +} + +struct texture_orig_info { + unsigned format; + unsigned width0; + unsigned height0; + unsigned npix_x; + unsigned npix_y; + unsigned npix0_x; + unsigned npix0_y; +}; + +static void radeonsi_compressed_to_blittable(struct pipe_resource *tex, + unsigned level, + struct texture_orig_info *orig) +{ + struct radeonsi_resource_texture *rtex = (struct radeonsi_resource_texture*)tex; + unsigned pixsize = util_format_get_blocksize(rtex->real_format); + int new_format; + int new_height, new_width; + + orig->format = tex->format; + orig->width0 = tex->width0; + orig->height0 = tex->height0; + orig->npix0_x = rtex->surface.level[0].npix_x; + orig->npix0_y = rtex->surface.level[0].npix_y; + orig->npix_x = rtex->surface.level[level].npix_x; + orig->npix_y = rtex->surface.level[level].npix_y; + + if (pixsize == 8) + new_format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */ + else + new_format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */ + + new_width = util_format_get_nblocksx(tex->format, orig->width0); + new_height = util_format_get_nblocksy(tex->format, orig->height0); + + tex->width0 = new_width; + tex->height0 = new_height; + tex->format = new_format; + rtex->surface.level[0].npix_x = util_format_get_nblocksx(orig->format, orig->npix0_x); + rtex->surface.level[0].npix_y = util_format_get_nblocksy(orig->format, orig->npix0_y); + rtex->surface.level[level].npix_x = util_format_get_nblocksx(orig->format, orig->npix_x); + rtex->surface.level[level].npix_y = util_format_get_nblocksy(orig->format, orig->npix_y); +} + +static void radeonsi_change_format(struct pipe_resource *tex, + unsigned level, + struct texture_orig_info *orig, + enum pipe_format format) +{ + struct radeonsi_resource_texture *rtex = (struct radeonsi_resource_texture*)tex; + + orig->format = tex->format; + orig->width0 = tex->width0; + orig->height0 = tex->height0; + orig->npix0_x = rtex->surface.level[0].npix_x; + orig->npix0_y = rtex->surface.level[0].npix_y; + orig->npix_x = rtex->surface.level[level].npix_x; + orig->npix_y = rtex->surface.level[level].npix_y; + + tex->format = format; +} + +static void radeonsi_reset_blittable_to_orig(struct pipe_resource *tex, + unsigned level, + struct texture_orig_info *orig) +{ + struct radeonsi_resource_texture *rtex = (struct radeonsi_resource_texture*)tex; + + tex->format = orig->format; + tex->width0 = orig->width0; + tex->height0 = orig->height0; + rtex->surface.level[0].npix_x = orig->npix0_x; + rtex->surface.level[0].npix_y = orig->npix0_y; + rtex->surface.level[level].npix_x = orig->npix_x; + rtex->surface.level[level].npix_y = orig->npix_y; +} + +static void radeonsi_resource_copy_region(struct pipe_context *ctx, + struct pipe_resource *dst, + unsigned dst_level, + unsigned dstx, unsigned dsty, unsigned dstz, + struct pipe_resource *src, + unsigned src_level, + const struct pipe_box *src_box) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + struct radeonsi_resource_texture *rsrc = (struct radeonsi_resource_texture*)src; + struct texture_orig_info orig_info[2]; + struct pipe_box sbox; + const struct pipe_box *psbox = src_box; + boolean restore_orig[2]; + + memset(orig_info, 0, sizeof(orig_info)); + + /* Fallback for buffers. */ + if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { + util_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz, + src, src_level, src_box); + return; + } + + /* This must be done before entering u_blitter to avoid recursion. */ + if (rsrc->is_depth && !rsrc->is_flushing_texture) { + si_blit_decompress_depth_in_place(rctx, rsrc, + src_level, src_level, + src_box->z, src_box->z + src_box->depth - 1); + } + + restore_orig[0] = restore_orig[1] = FALSE; + + if (util_format_is_compressed(src->format) && + util_format_is_compressed(dst->format)) { + radeonsi_compressed_to_blittable(src, src_level, &orig_info[0]); + restore_orig[0] = TRUE; + sbox.x = util_format_get_nblocksx(orig_info[0].format, src_box->x); + sbox.y = util_format_get_nblocksy(orig_info[0].format, src_box->y); + sbox.z = src_box->z; + sbox.width = util_format_get_nblocksx(orig_info[0].format, src_box->width); + sbox.height = util_format_get_nblocksy(orig_info[0].format, src_box->height); + sbox.depth = src_box->depth; + psbox=&sbox; + + radeonsi_compressed_to_blittable(dst, dst_level, &orig_info[1]); + restore_orig[1] = TRUE; + /* translate the dst box as well */ + dstx = util_format_get_nblocksx(orig_info[1].format, dstx); + dsty = util_format_get_nblocksy(orig_info[1].format, dsty); + } else if (!util_blitter_is_copy_supported(rctx->blitter, dst, src, + PIPE_MASK_RGBAZS)) { + unsigned blocksize = util_format_get_blocksize(src->format); + + switch (blocksize) { + case 1: + radeonsi_change_format(src, src_level, &orig_info[0], + PIPE_FORMAT_R8_UNORM); + radeonsi_change_format(dst, dst_level, &orig_info[1], + PIPE_FORMAT_R8_UNORM); + break; + case 2: + radeonsi_change_format(src, src_level, &orig_info[0], + PIPE_FORMAT_R8G8_UNORM); + radeonsi_change_format(dst, dst_level, &orig_info[1], + PIPE_FORMAT_R8G8_UNORM); + break; + case 4: + radeonsi_change_format(src, src_level, &orig_info[0], + PIPE_FORMAT_R8G8B8A8_UNORM); + radeonsi_change_format(dst, dst_level, &orig_info[1], + PIPE_FORMAT_R8G8B8A8_UNORM); + break; + case 8: + radeonsi_change_format(src, src_level, &orig_info[0], + PIPE_FORMAT_R16G16B16A16_UINT); + radeonsi_change_format(dst, dst_level, &orig_info[1], + PIPE_FORMAT_R16G16B16A16_UINT); + break; + case 16: + radeonsi_change_format(src, src_level, &orig_info[0], + PIPE_FORMAT_R32G32B32A32_UINT); + radeonsi_change_format(dst, dst_level, &orig_info[1], + PIPE_FORMAT_R32G32B32A32_UINT); + break; + default: + fprintf(stderr, "Unhandled format %s with blocksize %u\n", + util_format_short_name(src->format), blocksize); + assert(0); + } + restore_orig[0] = TRUE; + restore_orig[1] = TRUE; + } + + radeonsi_blitter_begin(ctx, RADEONSI_COPY); + util_blitter_copy_texture(rctx->blitter, dst, dst_level, dstx, dsty, dstz, + src, src_level, psbox, PIPE_MASK_RGBAZS, TRUE); + radeonsi_blitter_end(ctx); + + if (restore_orig[0]) + radeonsi_reset_blittable_to_orig(src, src_level, &orig_info[0]); + + if (restore_orig[1]) + radeonsi_reset_blittable_to_orig(dst, dst_level, &orig_info[1]); +} + +static void si_blit(struct pipe_context *ctx, + const struct pipe_blit_info *info) +{ + struct radeonsi_context *rctx = (struct radeonsi_context*)ctx; + struct radeonsi_resource_texture *rsrc = (struct radeonsi_resource_texture*)info->src.resource; + + assert(util_blitter_is_blit_supported(rctx->blitter, info)); + + if (info->src.resource->nr_samples > 1 && + info->dst.resource->nr_samples <= 1 && + !util_format_is_depth_or_stencil(info->src.resource->format) && + !util_format_is_pure_integer(info->src.resource->format)) { + debug_printf("radeonsi: color resolve is unimplemented\n"); + return; + } + + if (rsrc->is_depth && !rsrc->is_flushing_texture) { + si_blit_decompress_depth_in_place(rctx, rsrc, + info->src.level, info->src.level, + info->src.box.z, + info->src.box.z + info->src.box.depth - 1); + } + + radeonsi_blitter_begin(ctx, RADEONSI_BLIT); + util_blitter_blit(rctx->blitter, info); + radeonsi_blitter_end(ctx); +} + +void si_init_blit_functions(struct radeonsi_context *rctx) +{ + rctx->context.clear = radeonsi_clear; + rctx->context.clear_render_target = radeonsi_clear_render_target; + rctx->context.clear_depth_stencil = radeonsi_clear_depth_stencil; + rctx->context.resource_copy_region = radeonsi_resource_copy_region; + rctx->context.blit = si_blit; +} diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_buffer.c b/src/gallium/drivers/radeonsi/radeonsi_buffer.c --- a/src/gallium/drivers/radeonsi/radeonsi_buffer.c 1970-01-01 01:00:00.000000000 +0100 +++ b/src/gallium/drivers/radeonsi/radeonsi_buffer.c 2013-08-28 04:15:13.856313555 +0200 @@ -0,0 +1,197 @@ +/* + * Copyright 2010 Jerome Glisse + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Corbin Simpson + */ + +#include "pipe/p_screen.h" +#include "util/u_format.h" +#include "util/u_math.h" +#include "util/u_inlines.h" +#include "util/u_memory.h" +#include "util/u_upload_mgr.h" + +#include "radeonsi.h" +#include "radeonsi_pipe.h" + +static void radeonsi_buffer_destroy(struct pipe_screen *screen, + struct pipe_resource *buf) +{ + struct si_resource *rbuffer = si_resource(buf); + + pb_reference(&rbuffer->buf, NULL); + FREE(rbuffer); +} + +static void *radeonsi_buffer_transfer_map(struct pipe_context *ctx, + struct pipe_resource *resource, + unsigned level, + unsigned usage, + const struct pipe_box *box, + struct pipe_transfer **ptransfer) +{ + struct radeonsi_context *rctx = (struct radeonsi_context*)ctx; + struct pipe_transfer *transfer; + struct si_resource *rbuffer = si_resource(resource); + uint8_t *data; + + data = rctx->ws->buffer_map(rbuffer->cs_buf, rctx->cs, usage); + if (!data) { + return NULL; + } + + transfer = util_slab_alloc(&rctx->pool_transfers); + transfer->resource = resource; + transfer->level = level; + transfer->usage = usage; + transfer->box = *box; + transfer->stride = 0; + transfer->layer_stride = 0; + *ptransfer = transfer; + + return (uint8_t*)data + transfer->box.x; +} + +static void radeonsi_buffer_transfer_unmap(struct pipe_context *ctx, + struct pipe_transfer *transfer) +{ + struct radeonsi_context *rctx = (struct radeonsi_context*)ctx; + util_slab_free(&rctx->pool_transfers, transfer); +} + +static void radeonsi_buffer_transfer_flush_region(struct pipe_context *pipe, + struct pipe_transfer *transfer, + const struct pipe_box *box) +{ +} + +static const struct u_resource_vtbl radeonsi_buffer_vtbl = +{ + u_default_resource_get_handle, /* get_handle */ + radeonsi_buffer_destroy, /* resource_destroy */ + radeonsi_buffer_transfer_map, /* transfer_map */ + radeonsi_buffer_transfer_flush_region, /* transfer_flush_region */ + radeonsi_buffer_transfer_unmap, /* transfer_unmap */ + NULL /* transfer_inline_write */ +}; + +bool si_init_resource(struct radeonsi_screen *rscreen, + struct si_resource *res, + unsigned size, unsigned alignment, + boolean use_reusable_pool, unsigned usage) +{ + uint32_t initial_domain, domains; + + /* Staging resources particpate in transfers and blits only + * and are used for uploads and downloads from regular + * resources. We generate them internally for some transfers. + */ + if (usage == PIPE_USAGE_STAGING) { + domains = RADEON_DOMAIN_GTT; + initial_domain = RADEON_DOMAIN_GTT; + } else { + domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; + + switch(usage) { + case PIPE_USAGE_DYNAMIC: + case PIPE_USAGE_STREAM: + case PIPE_USAGE_STAGING: + initial_domain = RADEON_DOMAIN_GTT; + break; + case PIPE_USAGE_DEFAULT: + case PIPE_USAGE_STATIC: + case PIPE_USAGE_IMMUTABLE: + default: + initial_domain = RADEON_DOMAIN_VRAM; + break; + } + } + + res->buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment, + use_reusable_pool, + initial_domain); + if (!res->buf) { + return false; + } + + res->cs_buf = rscreen->ws->buffer_get_cs_handle(res->buf); + res->domains = domains; + return true; +} + +struct pipe_resource *si_buffer_create(struct pipe_screen *screen, + const struct pipe_resource *templ) +{ + struct radeonsi_screen *rscreen = (struct radeonsi_screen*)screen; + struct si_resource *rbuffer; + /* XXX We probably want a different alignment for buffers and textures. */ + unsigned alignment = 4096; + + rbuffer = MALLOC_STRUCT(si_resource); + + rbuffer->b.b = *templ; + pipe_reference_init(&rbuffer->b.b.reference, 1); + rbuffer->b.b.screen = screen; + rbuffer->b.vtbl = &radeonsi_buffer_vtbl; + + if (!si_init_resource(rscreen, rbuffer, templ->width0, alignment, TRUE, templ->usage)) { + FREE(rbuffer); + return NULL; + } + return &rbuffer->b.b; +} + +void radeonsi_upload_index_buffer(struct radeonsi_context *rctx, + struct pipe_index_buffer *ib, unsigned count) +{ + u_upload_data(rctx->uploader, 0, count * ib->index_size, + ib->user_buffer, &ib->offset, &ib->buffer); +} + +void radeonsi_upload_const_buffer(struct radeonsi_context *rctx, struct si_resource **rbuffer, + const uint8_t *ptr, unsigned size, + uint32_t *const_offset) +{ + if (RADEONSI_BIG_ENDIAN) { + uint32_t *tmpPtr; + unsigned i; + + if (!(tmpPtr = malloc(size))) { + RADEONSI_ERR("Failed to allocate BE swap buffer.\n"); + return; + } + + for (i = 0; i < size / 4; ++i) { + tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]); + } + + u_upload_data(rctx->uploader, 0, size, tmpPtr, const_offset, + (struct pipe_resource**)rbuffer); + + free(tmpPtr); + } else { + u_upload_data(rctx->uploader, 0, size, ptr, const_offset, + (struct pipe_resource**)rbuffer); + } +} diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_compute.c b/src/gallium/drivers/radeonsi/radeonsi_compute.c --- a/src/gallium/drivers/radeonsi/radeonsi_compute.c 2013-08-14 03:34:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/radeonsi_compute.c 2013-08-28 04:15:13.856313555 +0200 @@ -8,7 +8,7 @@ #define MAX_GLOBAL_BUFFERS 20 struct si_pipe_compute { - struct r600_context *ctx; + struct radeonsi_context *ctx; unsigned local_size; unsigned private_size; @@ -25,7 +25,7 @@ struct pipe_context *ctx, const struct pipe_compute_state *cso) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pipe_compute *program = CALLOC_STRUCT(si_pipe_compute); const struct pipe_llvm_program_header *header; @@ -55,7 +55,7 @@ static void radeonsi_bind_compute_state(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context*)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context*)ctx; rctx->cs_shader_state.program = (struct si_pipe_compute*)state; } @@ -65,7 +65,7 @@ uint32_t **handles) { unsigned i; - struct r600_context *rctx = (struct r600_context*)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context*)ctx; struct si_pipe_compute *program = rctx->cs_shader_state.program; if (!resources) { @@ -78,7 +78,7 @@ for (i = first; i < first + n; i++) { uint64_t va; program->global_buffers[i] = resources[i]; - va = r600_resource_va(ctx->screen, resources[i]); + va = radeonsi_resource_va(ctx->screen, resources[i]); memcpy(handles[i], &va, sizeof(va)); } } @@ -88,7 +88,7 @@ const uint *block_layout, const uint *grid_layout, uint32_t pc, const void *input) { - struct r600_context *rctx = (struct r600_context*)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context*)ctx; struct si_pipe_compute *program = rctx->cs_shader_state.program; struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); struct si_resource *kernel_args_buffer = NULL; @@ -128,9 +128,9 @@ memcpy(kernel_args + (num_work_size_bytes / 4), input, program->input_size); - r600_upload_const_buffer(rctx, &kernel_args_buffer, (uint8_t*)kernel_args, + radeonsi_upload_const_buffer(rctx, &kernel_args_buffer, (uint8_t*)kernel_args, kernel_args_size, &kernel_args_offset); - kernel_args_va = r600_resource_va(ctx->screen, + kernel_args_va = radeonsi_resource_va(ctx->screen, (struct pipe_resource*)kernel_args_buffer); kernel_args_va += kernel_args_offset; @@ -164,7 +164,7 @@ * (number of compute units) * 4 * (waves per simd) - 1 */ si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */); - shader_va = r600_resource_va(ctx->screen, (void *)shader->bo); + shader_va = radeonsi_resource_va(ctx->screen, (void *)shader->bo); si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ); si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff); si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40); @@ -251,7 +251,7 @@ unsigned start_slot, unsigned num_samplers, void **samplers_) { } -void si_init_compute_functions(struct r600_context *rctx) +void si_init_compute_functions(struct radeonsi_context *rctx) { rctx->context.create_compute_state = radeonsi_create_compute_state; rctx->context.delete_compute_state = si_delete_compute_state; diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_hw_context.c b/src/gallium/drivers/radeonsi/radeonsi_hw_context.c --- a/src/gallium/drivers/radeonsi/radeonsi_hw_context.c 1970-01-01 01:00:00.000000000 +0100 +++ b/src/gallium/drivers/radeonsi/radeonsi_hw_context.c 2013-08-28 04:15:13.856313555 +0200 @@ -0,0 +1,729 @@ +/* + * Copyright 2010 Jerome Glisse + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include "radeonsi_hw_context_priv.h" +#include "radeonsi_pm4.h" +#include "radeonsi_pipe.h" +#include "sid.h" +#include "util/u_memory.h" +#include + +#define GROUP_FORCE_NEW_BLOCK 0 + +/* Get backends mask */ +void si_get_backend_mask(struct radeonsi_context *ctx) +{ + struct radeon_winsys_cs *cs = ctx->cs; + struct si_resource *buffer; + uint32_t *results; + unsigned num_backends = ctx->screen->info.r600_num_backends; + unsigned i, mask = 0; + + /* if backend_map query is supported by the kernel */ + if (ctx->screen->info.r600_backend_map_valid) { + unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes; + unsigned backend_map = ctx->screen->info.r600_backend_map; + unsigned item_width = 4, item_mask = 0x7; + + while(num_tile_pipes--) { + i = backend_map & item_mask; + mask |= (1<>= item_width; + } + if (mask != 0) { + ctx->backend_mask = mask; + return; + } + } + + /* otherwise backup path for older kernels */ + + /* create buffer for event data */ + buffer = si_resource_create_custom(&ctx->screen->screen, + PIPE_USAGE_STAGING, + ctx->max_db*16); + if (!buffer) + goto err; + + /* initialize buffer with zeroes */ + results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE); + if (results) { + uint64_t va = 0; + + memset(results, 0, ctx->max_db * 4 * 4); + ctx->ws->buffer_unmap(buffer->cs_buf); + + /* emit EVENT_WRITE for ZPASS_DONE */ + va = radeonsi_resource_va(&ctx->screen->screen, (void *)buffer); + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); + cs->buf[cs->cdw++] = va; + cs->buf[cs->cdw++] = va >> 32; + + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = radeonsi_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE); + + /* analyze results */ + results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_READ); + if (results) { + for(i = 0; i < ctx->max_db; i++) { + /* at least highest bit will be set if backend is used */ + if (results[i*4 + 1]) + mask |= (1<ws->buffer_unmap(buffer->cs_buf); + } + } + + si_resource_reference(&buffer, NULL); + + if (mask != 0) { + ctx->backend_mask = mask; + return; + } + +err: + /* fallback to old method - set num_backends lower bits to 1 */ + ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends); + return; +} + +/* initialize */ +void si_need_cs_space(struct radeonsi_context *ctx, unsigned num_dw, + boolean count_draw_in) +{ + /* The number of dwords we already used in the CS so far. */ + num_dw += ctx->cs->cdw; + + if (count_draw_in) { + /* The number of dwords all the dirty states would take. */ + num_dw += ctx->pm4_dirty_cdwords; + + /* The upper-bound of how much a draw command would take. */ + num_dw += SI_MAX_DRAW_CS_DWORDS; + } + + /* Count in queries_suspend. */ + num_dw += ctx->num_cs_dw_queries_suspend; + + /* Count in streamout_end at the end of CS. */ + num_dw += ctx->num_cs_dw_streamout_end; + + /* Count in render_condition(NULL) at the end of CS. */ + if (ctx->predicate_drawing) { + num_dw += 3; + } + + /* Count in framebuffer cache flushes at the end of CS. */ + num_dw += 7; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */ + + /* Save 16 dwords for the fence mechanism. */ + num_dw += 16; + +#if RADEONSI_TRACE_CS + if (ctx->screen->trace_bo) { + num_dw += RADEONSI_TRACE_CS_DWORDS; + } +#endif + + /* Flush if there's not enough space. */ + if (num_dw > RADEON_MAX_CMDBUF_DWORDS) { + radeonsi_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC); + } +} + +static void radeonsi_flush_framebuffer(struct radeonsi_context *ctx) +{ + struct si_pm4_state *pm4; + + if (!(ctx->flags & RADEONSI_CONTEXT_DST_CACHES_DIRTY)) + return; + + pm4 = si_pm4_alloc_state(ctx); + + if (pm4 == NULL) + return; + + si_cmd_surface_sync(pm4, S_0085F0_CB0_DEST_BASE_ENA(1) | + S_0085F0_CB1_DEST_BASE_ENA(1) | + S_0085F0_CB2_DEST_BASE_ENA(1) | + S_0085F0_CB3_DEST_BASE_ENA(1) | + S_0085F0_CB4_DEST_BASE_ENA(1) | + S_0085F0_CB5_DEST_BASE_ENA(1) | + S_0085F0_CB6_DEST_BASE_ENA(1) | + S_0085F0_CB7_DEST_BASE_ENA(1) | + S_0085F0_DB_ACTION_ENA(1) | + S_0085F0_DB_DEST_BASE_ENA(1)); + si_pm4_emit(ctx, pm4); + si_pm4_free_state(ctx, pm4, ~0); + + ctx->flags &= ~RADEONSI_CONTEXT_DST_CACHES_DIRTY; +} + +void si_context_flush(struct radeonsi_context *ctx, unsigned flags) +{ + struct radeon_winsys_cs *cs = ctx->cs; + bool queries_suspended = false; + +#if 0 + bool streamout_suspended = false; +#endif + + if (!cs->cdw) + return; + + /* suspend queries */ + if (ctx->num_cs_dw_queries_suspend) { + radeonsi_context_queries_suspend(ctx); + queries_suspended = true; + } + +#if 0 + if (ctx->num_cs_dw_streamout_end) { + radeonsi_context_streamout_end(ctx); + streamout_suspended = true; + } +#endif + + radeonsi_flush_framebuffer(ctx); + + /* partial flush is needed to avoid lockups on some chips with user fences */ + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); + + /* force to keep tiling flags */ + flags |= RADEON_FLUSH_KEEP_TILING_FLAGS; + +#if RADEONSI_TRACE_CS + if (ctx->screen->trace_bo) { + struct radeonsi_screen *rscreen = ctx->screen; + unsigned i; + + for (i = 0; i < cs->cdw; i++) { + fprintf(stderr, "[%4d] [%5d] 0x%08x\n", rscreen->cs_count, i, cs->buf[i]); + } + rscreen->cs_count++; + } +#endif + + /* Flush the CS. */ + ctx->ws->cs_flush(ctx->cs, flags, 0); + +#if RADEONSI_TRACE_CS + if (ctx->screen->trace_bo) { + struct radeonsi_screen *rscreen = ctx->screen; + unsigned i; + + for (i = 0; i < 10; i++) { + usleep(5); + if (!ctx->ws->buffer_is_busy(rscreen->trace_bo->buf, RADEON_USAGE_READWRITE)) { + break; + } + } + if (i == 10) { + fprintf(stderr, "timeout on cs lockup likely happen at cs %d dw %d\n", + rscreen->trace_ptr[1], rscreen->trace_ptr[0]); + } else { + fprintf(stderr, "cs %d executed in %dms\n", rscreen->trace_ptr[1], i * 5); + } + } +#endif + + ctx->pm4_dirty_cdwords = 0; + ctx->flags = 0; + +#if 0 + if (streamout_suspended) { + ctx->streamout_start = TRUE; + ctx->streamout_append_bitmask = ~0; + } +#endif + + /* resume queries */ + if (queries_suspended) { + radeonsi_context_queries_resume(ctx); + } + + /* set all valid group as dirty so they get reemited on + * next draw command + */ + si_pm4_reset_emitted(ctx); +} + +void si_context_emit_fence(struct radeonsi_context *ctx, struct si_resource *fence_bo, unsigned offset, unsigned value) +{ + struct radeon_winsys_cs *cs = ctx->cs; + uint64_t va; + + si_need_cs_space(ctx, 10, FALSE); + + va = radeonsi_resource_va(&ctx->screen->screen, (void*)fence_bo); + va = va + (offset << 2); + + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); + cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */ + /* DATA_SEL | INT_EN | ADDRESS_HI */ + cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF); + cs->buf[cs->cdw++] = value; /* DATA_LO */ + cs->buf[cs->cdw++] = 0; /* DATA_HI */ + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = radeonsi_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE); +} + +static unsigned radeonsi_query_read_result(char *map, unsigned start_index, unsigned end_index, + bool test_status_bit) +{ + uint32_t *current_result = (uint32_t*)map; + uint64_t start, end; + + start = (uint64_t)current_result[start_index] | + (uint64_t)current_result[start_index+1] << 32; + end = (uint64_t)current_result[end_index] | + (uint64_t)current_result[end_index+1] << 32; + + if (!test_status_bit || + ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) { + return end - start; + } + return 0; +} + +static boolean radeonsi_query_result(struct radeonsi_context *ctx, struct radeonsi_query *query, boolean wait) +{ + unsigned results_base = query->results_start; + char *map; + + map = ctx->ws->buffer_map(query->buffer->cs_buf, ctx->cs, + PIPE_TRANSFER_READ | + (wait ? 0 : PIPE_TRANSFER_DONTBLOCK)); + if (!map) + return FALSE; + + /* count all results across all data blocks */ + switch (query->type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + while (results_base != query->results_end) { + query->result.u64 += + radeonsi_query_read_result(map + results_base, 0, 2, true); + results_base = (results_base + 16) % query->buffer->b.b.width0; + } + break; + case PIPE_QUERY_OCCLUSION_PREDICATE: + while (results_base != query->results_end) { + query->result.b = query->result.b || + radeonsi_query_read_result(map + results_base, 0, 2, true) != 0; + results_base = (results_base + 16) % query->buffer->b.b.width0; + } + break; + case PIPE_QUERY_TIME_ELAPSED: + while (results_base != query->results_end) { + query->result.u64 += + radeonsi_query_read_result(map + results_base, 0, 2, false); + results_base = (results_base + query->result_size) % query->buffer->b.b.width0; + } + break; + case PIPE_QUERY_PRIMITIVES_EMITTED: + /* SAMPLE_STREAMOUTSTATS stores this structure: + * { + * u64 NumPrimitivesWritten; + * u64 PrimitiveStorageNeeded; + * } + * We only need NumPrimitivesWritten here. */ + while (results_base != query->results_end) { + query->result.u64 += + radeonsi_query_read_result(map + results_base, 2, 6, true); + results_base = (results_base + query->result_size) % query->buffer->b.b.width0; + } + break; + case PIPE_QUERY_PRIMITIVES_GENERATED: + /* Here we read PrimitiveStorageNeeded. */ + while (results_base != query->results_end) { + query->result.u64 += + radeonsi_query_read_result(map + results_base, 0, 4, true); + results_base = (results_base + query->result_size) % query->buffer->b.b.width0; + } + break; + case PIPE_QUERY_SO_STATISTICS: + while (results_base != query->results_end) { + query->result.so.num_primitives_written += + radeonsi_query_read_result(map + results_base, 2, 6, true); + query->result.so.primitives_storage_needed += + radeonsi_query_read_result(map + results_base, 0, 4, true); + results_base = (results_base + query->result_size) % query->buffer->b.b.width0; + } + break; + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + while (results_base != query->results_end) { + query->result.b = query->result.b || + radeonsi_query_read_result(map + results_base, 2, 6, true) != + radeonsi_query_read_result(map + results_base, 0, 4, true); + results_base = (results_base + query->result_size) % query->buffer->b.b.width0; + } + break; + default: + assert(0); + } + + query->results_start = query->results_end; + ctx->ws->buffer_unmap(query->buffer->cs_buf); + return TRUE; +} + +void radeonsi_query_begin(struct radeonsi_context *ctx, struct radeonsi_query *query) +{ + struct radeon_winsys_cs *cs = ctx->cs; + unsigned new_results_end, i; + uint32_t *results; + uint64_t va; + + si_need_cs_space(ctx, query->num_cs_dw * 2, TRUE); + + new_results_end = (query->results_end + query->result_size) % query->buffer->b.b.width0; + + /* collect current results if query buffer is full */ + if (new_results_end == query->results_start) { + radeonsi_query_result(ctx, query, TRUE); + } + + switch (query->type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + case PIPE_QUERY_OCCLUSION_PREDICATE: + results = ctx->ws->buffer_map(query->buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE); + if (results) { + results = (uint32_t*)((char*)results + query->results_end); + memset(results, 0, query->result_size); + + /* Set top bits for unused backends */ + for (i = 0; i < ctx->max_db; i++) { + if (!(ctx->backend_mask & (1<ws->buffer_unmap(query->buffer->cs_buf); + } + break; + case PIPE_QUERY_TIME_ELAPSED: + break; + case PIPE_QUERY_PRIMITIVES_EMITTED: + case PIPE_QUERY_PRIMITIVES_GENERATED: + case PIPE_QUERY_SO_STATISTICS: + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + results = ctx->ws->buffer_map(query->buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE); + results = (uint32_t*)((char*)results + query->results_end); + memset(results, 0, query->result_size); + ctx->ws->buffer_unmap(query->buffer->cs_buf); + break; + default: + assert(0); + } + + /* emit begin query */ + va = radeonsi_resource_va(&ctx->screen->screen, (void*)query->buffer); + va += query->results_end; + + switch (query->type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + case PIPE_QUERY_OCCLUSION_PREDICATE: + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); + cs->buf[cs->cdw++] = va; + cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; + break; + case PIPE_QUERY_PRIMITIVES_EMITTED: + case PIPE_QUERY_PRIMITIVES_GENERATED: + case PIPE_QUERY_SO_STATISTICS: + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3); + cs->buf[cs->cdw++] = query->results_end; + cs->buf[cs->cdw++] = 0; + break; + case PIPE_QUERY_TIME_ELAPSED: + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); + cs->buf[cs->cdw++] = va; + cs->buf[cs->cdw++] = (3 << 29) | ((va >> 32UL) & 0xFF); + cs->buf[cs->cdw++] = 0; + cs->buf[cs->cdw++] = 0; + break; + default: + assert(0); + } + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = radeonsi_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); + + ctx->num_cs_dw_queries_suspend += query->num_cs_dw; +} + +void radeonsi_query_end(struct radeonsi_context *ctx, struct radeonsi_query *query) +{ + struct radeon_winsys_cs *cs = ctx->cs; + uint64_t va; + + va = radeonsi_resource_va(&ctx->screen->screen, (void*)query->buffer); + /* emit end query */ + switch (query->type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + case PIPE_QUERY_OCCLUSION_PREDICATE: + va += query->results_end + 8; + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); + cs->buf[cs->cdw++] = va; + cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; + break; + case PIPE_QUERY_PRIMITIVES_EMITTED: + case PIPE_QUERY_PRIMITIVES_GENERATED: + case PIPE_QUERY_SO_STATISTICS: + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3); + cs->buf[cs->cdw++] = query->results_end + query->result_size/2; + cs->buf[cs->cdw++] = 0; + break; + case PIPE_QUERY_TIME_ELAPSED: + va += query->results_end + query->result_size/2; + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); + cs->buf[cs->cdw++] = va; + cs->buf[cs->cdw++] = (3 << 29) | ((va >> 32UL) & 0xFF); + cs->buf[cs->cdw++] = 0; + cs->buf[cs->cdw++] = 0; + break; + default: + assert(0); + } + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = radeonsi_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); + + query->results_end = (query->results_end + query->result_size) % query->buffer->b.b.width0; + ctx->num_cs_dw_queries_suspend -= query->num_cs_dw; +} + +void radeonsi_query_predication(struct radeonsi_context *ctx, struct radeonsi_query *query, int operation, + int flag_wait) +{ + struct radeon_winsys_cs *cs = ctx->cs; + uint64_t va; + + if (operation == PREDICATION_OP_CLEAR) { + si_need_cs_space(ctx, 3, FALSE); + + cs->buf[cs->cdw++] = PKT3(PKT3_SET_PREDICATION, 1, 0); + cs->buf[cs->cdw++] = 0; + cs->buf[cs->cdw++] = PRED_OP(PREDICATION_OP_CLEAR); + } else { + unsigned results_base = query->results_start; + unsigned count; + uint32_t op; + + /* find count of the query data blocks */ + count = (query->buffer->b.b.width0 + query->results_end - query->results_start) % query->buffer->b.b.width0; + count /= query->result_size; + + si_need_cs_space(ctx, 5 * count, TRUE); + + op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE | + (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW); + va = radeonsi_resource_va(&ctx->screen->screen, (void*)query->buffer); + + /* emit predicate packets for all data blocks */ + while (results_base != query->results_end) { + cs->buf[cs->cdw++] = PKT3(PKT3_SET_PREDICATION, 1, 0); + cs->buf[cs->cdw++] = (va + results_base) & 0xFFFFFFFFUL; + cs->buf[cs->cdw++] = op | (((va + results_base) >> 32UL) & 0xFF); + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = radeonsi_context_bo_reloc(ctx, query->buffer, + RADEON_USAGE_READ); + results_base = (results_base + query->result_size) % query->buffer->b.b.width0; + + /* set CONTINUE bit for all packets except the first */ + op |= PREDICATION_CONTINUE; + } + } +} + +struct radeonsi_query *radeonsi_context_query_create(struct radeonsi_context *ctx, unsigned query_type) +{ + struct radeonsi_query *query; + unsigned buffer_size = 4096; + + query = CALLOC_STRUCT(radeonsi_query); + if (query == NULL) + return NULL; + + query->type = query_type; + + switch (query_type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + case PIPE_QUERY_OCCLUSION_PREDICATE: + query->result_size = 16 * ctx->max_db; + query->num_cs_dw = 6; + break; + case PIPE_QUERY_TIME_ELAPSED: + query->result_size = 16; + query->num_cs_dw = 8; + break; + case PIPE_QUERY_PRIMITIVES_EMITTED: + case PIPE_QUERY_PRIMITIVES_GENERATED: + case PIPE_QUERY_SO_STATISTICS: + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + /* NumPrimitivesWritten, PrimitiveStorageNeeded. */ + query->result_size = 32; + query->num_cs_dw = 6; + break; + default: + assert(0); + FREE(query); + return NULL; + } + + /* adjust buffer size to simplify offsets wrapping math */ + buffer_size -= buffer_size % query->result_size; + + /* Queries are normally read by the CPU after + * being written by the gpu, hence staging is probably a good + * usage pattern. + */ + query->buffer = si_resource_create_custom(&ctx->screen->screen, + PIPE_USAGE_STAGING, + buffer_size); + if (!query->buffer) { + FREE(query); + return NULL; + } + return query; +} + +void radeonsi_context_query_destroy(struct radeonsi_context *ctx, struct radeonsi_query *query) +{ + si_resource_reference(&query->buffer, NULL); + free(query); +} + +boolean radeonsi_context_query_result(struct radeonsi_context *ctx, + struct radeonsi_query *query, + boolean wait, void *vresult) +{ + boolean *result_b = (boolean*)vresult; + uint64_t *result_u64 = (uint64_t*)vresult; + struct pipe_query_data_so_statistics *result_so = + (struct pipe_query_data_so_statistics*)vresult; + + if (!radeonsi_query_result(ctx, query, wait)) + return FALSE; + + switch (query->type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + case PIPE_QUERY_PRIMITIVES_EMITTED: + case PIPE_QUERY_PRIMITIVES_GENERATED: + *result_u64 = query->result.u64; + break; + case PIPE_QUERY_OCCLUSION_PREDICATE: + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + *result_b = query->result.b; + break; + case PIPE_QUERY_TIME_ELAPSED: + *result_u64 = (1000000 * query->result.u64) / ctx->screen->info.r600_clock_crystal_freq; + break; + case PIPE_QUERY_SO_STATISTICS: + *result_so = query->result.so; + break; + default: + assert(0); + } + return TRUE; +} + +void radeonsi_context_queries_suspend(struct radeonsi_context *ctx) +{ + struct radeonsi_query *query; + + LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) { + radeonsi_query_end(ctx, query); + } + assert(ctx->num_cs_dw_queries_suspend == 0); +} + +void radeonsi_context_queries_resume(struct radeonsi_context *ctx) +{ + struct radeonsi_query *query; + + assert(ctx->num_cs_dw_queries_suspend == 0); + + LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) { + radeonsi_query_begin(ctx, query); + } +} + +void radeonsi_context_draw_opaque_count(struct radeonsi_context *ctx, struct radeonsi_so_target *t) +{ + struct radeon_winsys_cs *cs = ctx->cs; + si_need_cs_space(ctx, 14 + 21, TRUE); + + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); + cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - SI_CONTEXT_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = 0; + + cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); + cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - SI_CONTEXT_REG_OFFSET) >> 2; + cs->buf[cs->cdw++] = t->stride >> 2; + +#if 0 + cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0); + cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG; + cs->buf[cs->cdw++] = 0; /* src address lo */ + cs->buf[cs->cdw++] = 0; /* src address hi */ + cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */ + cs->buf[cs->cdw++] = 0; /* unused */ +#endif + + cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); + cs->buf[cs->cdw++] = radeonsi_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ); + +} + +#if RADEONSI_TRACE_CS +void radeonsi_trace_emit(struct radeonsi_context *rctx) +{ + struct radeonsi_screen *rscreen = rctx->screen; + struct radeon_winsys_cs *cs = rctx->cs; + uint64_t va; + + va = radeonsi_resource_va(&rscreen->screen, (void*)rscreen->trace_bo); + radeonsi_context_bo_reloc(rctx, rscreen->trace_bo, RADEON_USAGE_READWRITE); + cs->buf[cs->cdw++] = PKT3(PKT3_WRITE_DATA, 4, 0); + cs->buf[cs->cdw++] = PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) | + PKT3_WRITE_DATA_WR_CONFIRM | + PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME); + cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; + cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFFFFFFFUL; + cs->buf[cs->cdw++] = cs->cdw; + cs->buf[cs->cdw++] = rscreen->cs_count; +} +#endif diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_hw_context_priv.h b/src/gallium/drivers/radeonsi/radeonsi_hw_context_priv.h --- a/src/gallium/drivers/radeonsi/radeonsi_hw_context_priv.h 1970-01-01 01:00:00.000000000 +0100 +++ b/src/gallium/drivers/radeonsi/radeonsi_hw_context_priv.h 2013-08-28 04:15:13.856313555 +0200 @@ -0,0 +1,45 @@ +/* + * Copyright 2010 Jerome Glisse + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef RADEONSI_PRIV_H +#define RADEONSI_PRIV_H + +#include "radeonsi_pipe.h" +#include "util/u_hash_table.h" +#include "os/os_thread.h" + +#define SI_MAX_DRAW_CS_DWORDS 18 + +#define PKT_COUNT_C 0xC000FFFF +#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) + +static INLINE unsigned radeonsi_context_bo_reloc(struct radeonsi_context *ctx, struct si_resource *rbo, + enum radeon_bo_usage usage) +{ + assert(usage); + return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; +} + +#endif diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c 2013-08-14 03:34:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c 2013-08-28 04:15:13.856313555 +0200 @@ -45,20 +45,20 @@ #include "pipebuffer/pb_buffer.h" #include "radeonsi_pipe.h" #include "radeon/radeon_uvd.h" -#include "r600.h" +#include "radeonsi.h" #include "sid.h" -#include "r600_resource.h" +#include "radeonsi_resource.h" #include "radeonsi_pipe.h" -#include "r600_hw_context_priv.h" +#include "radeonsi_hw_context_priv.h" #include "si_state.h" /* * pipe_context */ -static struct r600_fence *r600_create_fence(struct r600_context *rctx) +static struct radeonsi_fence *radeonsi_create_fence(struct radeonsi_context *rctx) { - struct r600_screen *rscreen = rctx->screen; - struct r600_fence *fence = NULL; + struct radeonsi_screen *rscreen = rctx->screen; + struct radeonsi_fence *fence = NULL; pipe_mutex_lock(rscreen->fences.mutex); @@ -68,7 +68,7 @@ PIPE_USAGE_STAGING, 4096); if (!rscreen->fences.bo) { - R600_ERR("r600: failed to create bo for fence objects\n"); + RADEONSI_ERR("radeonsi: failed to create bo for fence objects\n"); goto out; } rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf, @@ -77,7 +77,7 @@ } if (!LIST_IS_EMPTY(&rscreen->fences.pool)) { - struct r600_fence *entry; + struct radeonsi_fence *entry; /* Try to find a freed fence that has been signalled */ LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) { @@ -91,11 +91,11 @@ if (!fence) { /* Allocate a new fence */ - struct r600_fence_block *block; + struct radeonsi_fence_block *block; unsigned index; if ((rscreen->fences.next_index + 1) >= 1024) { - R600_ERR("r600: too many concurrent fences\n"); + RADEONSI_ERR("radeonsi: too many concurrent fences\n"); goto out; } @@ -103,13 +103,13 @@ if (!(index % FENCE_BLOCK_SIZE)) { /* Allocate a new block */ - block = CALLOC_STRUCT(r600_fence_block); + block = CALLOC_STRUCT(radeonsi_fence_block); if (block == NULL) goto out; LIST_ADD(&block->head, &rscreen->fences.blocks); } else { - block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head); + block = LIST_ENTRY(struct radeonsi_fence_block, rscreen->fences.blocks.next, head); } fence = &block->fences[index % FENCE_BLOCK_SIZE]; @@ -125,7 +125,7 @@ fence->sleep_bo = si_resource_create_custom(&rctx->screen->screen, PIPE_USAGE_STAGING, 1); /* Add the fence as a dummy relocation. */ - r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE); + radeonsi_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE); out: pipe_mutex_unlock(rscreen->fences.mutex); @@ -136,14 +136,14 @@ void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, unsigned flags) { - struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_fence **rfence = (struct r600_fence**)fence; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + struct radeonsi_fence **rfence = (struct radeonsi_fence**)fence; struct pipe_query *render_cond = NULL; boolean render_cond_cond = FALSE; unsigned render_cond_mode = 0; if (rfence) - *rfence = r600_create_fence(rctx); + *rfence = radeonsi_create_fence(rctx); /* Disable render condition. */ if (rctx->current_render_cond) { @@ -161,7 +161,7 @@ } } -static void r600_flush_from_st(struct pipe_context *ctx, +static void radeonsi_flush_from_st(struct pipe_context *ctx, struct pipe_fence_handle **fence, unsigned flags) { @@ -169,14 +169,14 @@ flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0); } -static void r600_flush_from_winsys(void *ctx, unsigned flags) +static void radeonsi_flush_from_winsys(void *ctx, unsigned flags) { radeonsi_flush((struct pipe_context*)ctx, NULL, flags); } -static void r600_destroy_context(struct pipe_context *context) +static void radeonsi_destroy_context(struct pipe_context *context) { - struct r600_context *rctx = (struct r600_context *)context; + struct radeonsi_context *rctx = (struct radeonsi_context *)context; si_resource_reference(&rctx->border_color_table, NULL); @@ -198,18 +198,18 @@ FREE(rctx); } -static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) +static struct pipe_context *radeonsi_create_context(struct pipe_screen *screen, void *priv) { - struct r600_context *rctx = CALLOC_STRUCT(r600_context); - struct r600_screen* rscreen = (struct r600_screen *)screen; + struct radeonsi_context *rctx = CALLOC_STRUCT(radeonsi_context); + struct radeonsi_screen* rscreen = (struct radeonsi_screen *)screen; if (rctx == NULL) return NULL; rctx->context.screen = screen; rctx->context.priv = priv; - rctx->context.destroy = r600_destroy_context; - rctx->context.flush = r600_flush_from_st; + rctx->context.destroy = radeonsi_destroy_context; + rctx->context.flush = radeonsi_flush_from_st; /* Easy accessing of screen/winsys. */ rctx->screen = rscreen; @@ -218,8 +218,8 @@ rctx->chip_class = rscreen->chip_class; si_init_blit_functions(rctx); - r600_init_query_functions(rctx); - r600_init_context_resource_functions(rctx); + radeonsi_init_query_functions(rctx); + radeonsi_init_context_resource_functions(rctx); si_init_surface_functions(rctx); si_init_compute_functions(rctx); @@ -247,12 +247,12 @@ si_init_config(rctx); break; default: - R600_ERR("Unsupported chip class %d.\n", rctx->chip_class); - r600_destroy_context(&rctx->context); + RADEONSI_ERR("Unsupported chip class %d.\n", rctx->chip_class); + radeonsi_destroy_context(&rctx->context); return NULL; } - rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx); + rctx->ws->cs_set_flush_callback(rctx->cs, radeonsi_flush_from_winsys, rctx); util_slab_create(&rctx->pool_transfers, sizeof(struct pipe_transfer), 64, @@ -262,13 +262,13 @@ PIPE_BIND_INDEX_BUFFER | PIPE_BIND_CONSTANT_BUFFER); if (!rctx->uploader) { - r600_destroy_context(&rctx->context); + radeonsi_destroy_context(&rctx->context); return NULL; } rctx->blitter = util_blitter_create(&rctx->context); if (rctx->blitter == NULL) { - r600_destroy_context(&rctx->context); + radeonsi_destroy_context(&rctx->context); return NULL; } @@ -286,12 +286,12 @@ /* * pipe_screen */ -static const char* r600_get_vendor(struct pipe_screen* pscreen) +static const char* radeonsi_get_vendor(struct pipe_screen* pscreen) { return "X.Org"; } -const char *r600_get_llvm_processor_name(enum radeon_family family) +const char *radeonsi_get_llvm_processor_name(enum radeon_family family) { switch (family) { case CHIP_TAHITI: return "tahiti"; @@ -306,7 +306,7 @@ } } -static const char *r600_get_family_name(enum radeon_family family) +static const char *radeonsi_get_family_name(enum radeon_family family) { switch(family) { case CHIP_TAHITI: return "AMD TAHITI"; @@ -321,16 +321,16 @@ } } -static const char* r600_get_name(struct pipe_screen* pscreen) +static const char* radeonsi_get_name(struct pipe_screen* pscreen) { - struct r600_screen *rscreen = (struct r600_screen *)pscreen; + struct radeonsi_screen *rscreen = (struct radeonsi_screen *)pscreen; - return r600_get_family_name(rscreen->family); + return radeonsi_get_family_name(rscreen->family); } -static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) +static int radeonsi_get_param(struct pipe_screen* pscreen, enum pipe_cap param) { - struct r600_screen *rscreen = (struct r600_screen *)pscreen; + struct radeonsi_screen *rscreen = (struct radeonsi_screen *)pscreen; switch (param) { /* Supported features (boolean caps). */ @@ -403,9 +403,9 @@ /* Stream output. */ #if 0 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: - return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0; + return debug_get_bool_option("RADEONSI_STREAMOUT", FALSE) ? 4 : 0; case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: - return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0; + return debug_get_bool_option("RADEONSI_STREAMOUT", FALSE) ? 1 : 0; case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: return 16*4; @@ -446,7 +446,7 @@ return 0; } -static float r600_get_paramf(struct pipe_screen* pscreen, +static float radeonsi_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param) { switch (param) { @@ -468,7 +468,7 @@ return 0.0f; } -static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) +static int radeonsi_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) { switch(shader) { @@ -532,7 +532,7 @@ return 0; } -static int r600_get_video_param(struct pipe_screen *screen, +static int radeonsi_get_video_param(struct pipe_screen *screen, enum pipe_video_profile profile, enum pipe_video_cap param) { @@ -551,17 +551,17 @@ } } -static int r600_get_compute_param(struct pipe_screen *screen, +static int radeonsi_get_compute_param(struct pipe_screen *screen, enum pipe_compute_cap param, void *ret) { - struct r600_screen *rscreen = (struct r600_screen *)screen; + struct radeonsi_screen *rscreen = (struct radeonsi_screen *)screen; //TODO: select these params by asic switch (param) { case PIPE_COMPUTE_CAP_IR_TARGET: { - const char *gpu = r600_get_llvm_processor_name(rscreen->family); + const char *gpu = radeonsi_get_llvm_processor_name(rscreen->family); if (ret) { - sprintf(ret, "%s-r600--", gpu); + sprintf(ret, "%s-radeonsi--", gpu); } return (8 + strlen(gpu)) * sizeof(char); } @@ -607,7 +607,7 @@ if (ret) { uint64_t max_global_size; uint64_t *max_mem_alloc_size = ret; - r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size); + radeonsi_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size); *max_mem_alloc_size = max_global_size / 4; } return sizeof(uint64_t); @@ -617,15 +617,15 @@ } } -static void r600_destroy_screen(struct pipe_screen* pscreen) +static void radeonsi_destroy_screen(struct pipe_screen* pscreen) { - struct r600_screen *rscreen = (struct r600_screen *)pscreen; + struct radeonsi_screen *rscreen = (struct radeonsi_screen *)pscreen; if (rscreen == NULL) return; if (rscreen->fences.bo) { - struct r600_fence_block *entry, *tmp; + struct radeonsi_fence_block *entry, *tmp; LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) { LIST_DEL(&entry->head); @@ -636,7 +636,7 @@ si_resource_reference(&rscreen->fences.bo, NULL); } -#if R600_TRACE_CS +#if RADEONSI_TRACE_CS if (rscreen->trace_bo) { rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf); pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL); @@ -649,15 +649,15 @@ FREE(rscreen); } -static void r600_fence_reference(struct pipe_screen *pscreen, +static void radeonsi_fence_reference(struct pipe_screen *pscreen, struct pipe_fence_handle **ptr, struct pipe_fence_handle *fence) { - struct r600_fence **oldf = (struct r600_fence**)ptr; - struct r600_fence *newf = (struct r600_fence*)fence; + struct radeonsi_fence **oldf = (struct radeonsi_fence**)ptr; + struct radeonsi_fence *newf = (struct radeonsi_fence*)fence; if (pipe_reference(&(*oldf)->reference, &newf->reference)) { - struct r600_screen *rscreen = (struct r600_screen *)pscreen; + struct radeonsi_screen *rscreen = (struct radeonsi_screen *)pscreen; pipe_mutex_lock(rscreen->fences.mutex); si_resource_reference(&(*oldf)->sleep_bo, NULL); LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool); @@ -667,21 +667,21 @@ *ptr = fence; } -static boolean r600_fence_signalled(struct pipe_screen *pscreen, +static boolean radeonsi_fence_signalled(struct pipe_screen *pscreen, struct pipe_fence_handle *fence) { - struct r600_screen *rscreen = (struct r600_screen *)pscreen; - struct r600_fence *rfence = (struct r600_fence*)fence; + struct radeonsi_screen *rscreen = (struct radeonsi_screen *)pscreen; + struct radeonsi_fence *rfence = (struct radeonsi_fence*)fence; return rscreen->fences.data[rfence->index] != 0; } -static boolean r600_fence_finish(struct pipe_screen *pscreen, +static boolean radeonsi_fence_finish(struct pipe_screen *pscreen, struct pipe_fence_handle *fence, uint64_t timeout) { - struct r600_screen *rscreen = (struct r600_screen *)pscreen; - struct r600_fence *rfence = (struct r600_fence*)fence; + struct radeonsi_screen *rscreen = (struct radeonsi_screen *)pscreen; + struct radeonsi_fence *rfence = (struct radeonsi_fence*)fence; int64_t start_time = 0; unsigned spins = 0; @@ -720,7 +720,7 @@ return rscreen->fences.data[rfence->index] != 0; } -static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) +static int evergreen_interpret_tiling(struct radeonsi_screen *rscreen, uint32_t tiling_config) { switch (tiling_config & 0xf) { case 0: @@ -766,7 +766,7 @@ return 0; } -static int r600_init_tiling(struct r600_screen *rscreen) +static int radeonsi_init_tiling(struct radeonsi_screen *rscreen) { uint32_t tiling_config = rscreen->info.r600_tiling_config; @@ -792,7 +792,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws) { - struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen); + struct radeonsi_screen *rscreen = CALLOC_STRUCT(radeonsi_screen); if (rscreen == NULL) { return NULL; } @@ -802,7 +802,7 @@ rscreen->family = radeon_family_from_device(rscreen->info.pci_id); if (rscreen->family == CHIP_UNKNOWN) { - fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id); + fprintf(stderr, "radeonsi: Unknown chipset 0x%04X\n", rscreen->info.pci_id); FREE(rscreen); return NULL; } @@ -813,35 +813,35 @@ } else if (rscreen->family >= CHIP_TAHITI) { rscreen->chip_class = SI; } else { - fprintf(stderr, "r600: Unsupported family %d\n", rscreen->family); + fprintf(stderr, "radeonsi: Unsupported family %d\n", rscreen->family); FREE(rscreen); return NULL; } - if (r600_init_tiling(rscreen)) { + if (radeonsi_init_tiling(rscreen)) { FREE(rscreen); return NULL; } - rscreen->screen.destroy = r600_destroy_screen; - rscreen->screen.get_name = r600_get_name; - rscreen->screen.get_vendor = r600_get_vendor; - rscreen->screen.get_param = r600_get_param; - rscreen->screen.get_shader_param = r600_get_shader_param; - rscreen->screen.get_paramf = r600_get_paramf; - rscreen->screen.get_compute_param = r600_get_compute_param; + rscreen->screen.destroy = radeonsi_destroy_screen; + rscreen->screen.get_name = radeonsi_get_name; + rscreen->screen.get_vendor = radeonsi_get_vendor; + rscreen->screen.get_param = radeonsi_get_param; + rscreen->screen.get_shader_param = radeonsi_get_shader_param; + rscreen->screen.get_paramf = radeonsi_get_paramf; + rscreen->screen.get_compute_param = radeonsi_get_compute_param; rscreen->screen.is_format_supported = si_is_format_supported; - rscreen->screen.context_create = r600_create_context; - rscreen->screen.fence_reference = r600_fence_reference; - rscreen->screen.fence_signalled = r600_fence_signalled; - rscreen->screen.fence_finish = r600_fence_finish; - r600_init_screen_resource_functions(&rscreen->screen); + rscreen->screen.context_create = radeonsi_create_context; + rscreen->screen.fence_reference = radeonsi_fence_reference; + rscreen->screen.fence_signalled = radeonsi_fence_signalled; + rscreen->screen.fence_finish = radeonsi_fence_finish; + radeonsi_init_screen_resource_functions(&rscreen->screen); if (rscreen->info.has_uvd) { rscreen->screen.get_video_param = ruvd_get_video_param; rscreen->screen.is_video_format_supported = ruvd_is_format_supported; } else { - rscreen->screen.get_video_param = r600_get_video_param; + rscreen->screen.get_video_param = radeonsi_get_video_param; rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; } @@ -854,7 +854,7 @@ LIST_INITHEAD(&rscreen->fences.blocks); pipe_mutex_init(rscreen->fences.mutex); -#if R600_TRACE_CS +#if RADEONSI_TRACE_CS rscreen->cs_count = 0; if (rscreen->info.drm_minor >= 28) { rscreen->trace_bo = (struct si_resource*)pipe_buffer_create(&rscreen->screen, diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_pipe.h b/src/gallium/drivers/radeonsi/radeonsi_pipe.h --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h 2013-08-14 03:34:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h 2013-08-28 04:15:13.856313555 +0200 @@ -34,25 +34,25 @@ #include "util/u_format.h" #include "util/u_math.h" #include "util/u_slab.h" -#include "r600.h" +#include "radeonsi.h" #include "radeonsi_public.h" #include "radeonsi_pm4.h" #include "si_state.h" -#include "r600_resource.h" +#include "radeonsi_resource.h" #include "sid.h" #ifdef PIPE_ARCH_BIG_ENDIAN -#define R600_BIG_ENDIAN 1 +#define RADEONSI_BIG_ENDIAN 1 #else -#define R600_BIG_ENDIAN 0 +#define RADEONSI_BIG_ENDIAN 0 #endif -#define R600_TRACE_CS 0 -#define R600_TRACE_CS_DWORDS 6 +#define RADEONSI_TRACE_CS 0 +#define RADEONSI_TRACE_CS_DWORDS 6 struct si_pipe_compute; -struct r600_pipe_fences { +struct radeonsi_pipe_fences { struct si_resource *bo; unsigned *data; unsigned next_index; @@ -63,16 +63,16 @@ pipe_mutex mutex; }; -struct r600_screen { +struct radeonsi_screen { struct pipe_screen screen; struct radeon_winsys *ws; unsigned family; enum chip_class chip_class; struct radeon_info info; - struct r600_tiling_info tiling_info; + struct radeonsi_tiling_info tiling_info; struct util_slab_mempool pool_buffers; - struct r600_pipe_fences fences; -#if R600_TRACE_CS + struct radeonsi_pipe_fences fences; +#if RADEONSI_TRACE_CS struct si_resource *trace_bo; uint32_t *trace_ptr; unsigned cs_count; @@ -97,7 +97,7 @@ /* needed for blitter save */ #define NUM_TEX_UNITS 16 -struct r600_textures_info { +struct radeonsi_textures_info { struct si_pipe_sampler_view *views[NUM_TEX_UNITS]; struct si_pipe_sampler_state *samplers[NUM_TEX_UNITS]; unsigned n_views; @@ -107,7 +107,7 @@ bool is_array_sampler[NUM_TEX_UNITS]; }; -struct r600_fence { +struct radeonsi_fence { struct pipe_reference reference; unsigned index; /* in the shared bo */ struct si_resource *sleep_bo; @@ -116,22 +116,22 @@ #define FENCE_BLOCK_SIZE 16 -struct r600_fence_block { - struct r600_fence fences[FENCE_BLOCK_SIZE]; +struct radeonsi_fence_block { + struct radeonsi_fence fences[FENCE_BLOCK_SIZE]; struct list_head head; }; -#define R600_CONSTANT_ARRAY_SIZE 256 -#define R600_RESOURCE_ARRAY_SIZE 160 +#define RADEONSI_CONSTANT_ARRAY_SIZE 256 +#define RADEONSI_RESOURCE_ARRAY_SIZE 160 -struct r600_constbuf_state +struct radeonsi_constbuf_state { struct pipe_constant_buffer cb[2]; uint32_t enabled_mask; uint32_t dirty_mask; }; -struct r600_context { +struct radeonsi_context { struct pipe_context context; struct blitter_context *blitter; enum radeon_family family; @@ -140,7 +140,7 @@ void *custom_dsa_flush_depth; void *custom_dsa_flush_stencil; void *custom_dsa_flush_inplace; - struct r600_screen *screen; + struct radeonsi_screen *screen; struct radeon_winsys *ws; struct si_vertex_element *vertex_elements; struct pipe_framebuffer_state framebuffer; @@ -160,9 +160,9 @@ /* shader information */ unsigned sprite_coord_enable; unsigned export_16bpc; - struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES]; - struct r600_textures_info vs_samplers; - struct r600_textures_info ps_samplers; + struct radeonsi_constbuf_state constbuf_state[PIPE_SHADER_TYPES]; + struct radeonsi_textures_info vs_samplers; + struct radeonsi_textures_info ps_samplers; struct si_resource *border_color_table; unsigned border_color_offset; @@ -171,7 +171,7 @@ unsigned default_ps_gprs, default_vs_gprs; - /* Below are variables from the old r600_context. + /* Below are variables from the old radeonsi_context. */ struct radeon_winsys_cs *cs; @@ -188,7 +188,7 @@ boolean predicate_drawing; unsigned num_so_targets; - struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; + struct radeonsi_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; boolean streamout_start; unsigned streamout_append_bitmask; unsigned *vs_so_stride_in_dw; @@ -209,53 +209,53 @@ union si_state emitted; }; -/* r600_blit.c */ -void si_init_blit_functions(struct r600_context *rctx); +/* radeonsi_blit.c */ +void si_init_blit_functions(struct radeonsi_context *rctx); void si_blit_uncompress_depth(struct pipe_context *ctx, - struct r600_resource_texture *texture, - struct r600_resource_texture *staging, + struct radeonsi_resource_texture *texture, + struct radeonsi_resource_texture *staging, unsigned first_level, unsigned last_level, unsigned first_layer, unsigned last_layer); -void si_flush_depth_textures(struct r600_context *rctx, - struct r600_textures_info *textures); +void si_flush_depth_textures(struct radeonsi_context *rctx, + struct radeonsi_textures_info *textures); -/* r600_buffer.c */ -bool si_init_resource(struct r600_screen *rscreen, +/* radeonsi_buffer.c */ +bool si_init_resource(struct radeonsi_screen *rscreen, struct si_resource *res, unsigned size, unsigned alignment, boolean use_reusable_pool, unsigned usage); struct pipe_resource *si_buffer_create(struct pipe_screen *screen, const struct pipe_resource *templ); -void r600_upload_index_buffer(struct r600_context *rctx, +void radeonsi_upload_index_buffer(struct radeonsi_context *rctx, struct pipe_index_buffer *ib, unsigned count); -/* r600_pipe.c */ +/* radeonsi_pipe.c */ void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, unsigned flags); -const char *r600_get_llvm_processor_name(enum radeon_family family); +const char *radeonsi_get_llvm_processor_name(enum radeon_family family); -/* r600_query.c */ -void r600_init_query_functions(struct r600_context *rctx); +/* radeonsi_query.c */ +void radeonsi_init_query_functions(struct radeonsi_context *rctx); -/* r600_resource.c */ -void r600_init_context_resource_functions(struct r600_context *r600); +/* radeonsi_resource.c */ +void radeonsi_init_context_resource_functions(struct radeonsi_context *radeonsi); -/* r600_texture.c */ -void r600_init_screen_texture_functions(struct pipe_screen *screen); -void si_init_surface_functions(struct r600_context *r600); +/* radeonsi_texture.c */ +void radeonsi_init_screen_texture_functions(struct pipe_screen *screen); +void si_init_surface_functions(struct radeonsi_context *radeonsi); -/* r600_translate.c */ -void r600_translate_index_buffer(struct r600_context *r600, +/* radeonsi_translate.c */ +void radeonsi_translate_index_buffer(struct radeonsi_context *radeonsi, struct pipe_index_buffer *ib, unsigned count); -#if R600_TRACE_CS -void r600_trace_emit(struct r600_context *rctx); +#if RADEONSI_TRACE_CS +void radeonsi_trace_emit(struct radeonsi_context *rctx); #endif /* radeonsi_compute.c */ -void si_init_compute_functions(struct r600_context *rctx); +void si_init_compute_functions(struct radeonsi_context *rctx); /* radeonsi_uvd.c */ struct pipe_video_decoder *radeonsi_uvd_create_decoder(struct pipe_context *context, @@ -295,7 +295,7 @@ } } -static inline unsigned r600_tex_aniso_filter(unsigned filter) +static inline unsigned radeonsi_tex_aniso_filter(unsigned filter) { if (filter <= 1) return 0; if (filter <= 2) return 1; @@ -305,15 +305,15 @@ } /* 12.4 fixed-point */ -static INLINE unsigned r600_pack_float_12p4(float x) +static INLINE unsigned radeonsi_pack_float_12p4(float x) { return x <= 0 ? 0 : x >= 4096 ? 0xffff : x * 16; } -static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) +static INLINE uint64_t radeonsi_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) { - struct r600_screen *rscreen = (struct r600_screen*)screen; + struct radeonsi_screen *rscreen = (struct radeonsi_screen*)screen; struct si_resource *rresource = (struct si_resource*)resource; return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_pm4.c b/src/gallium/drivers/radeonsi/radeonsi_pm4.c --- a/src/gallium/drivers/radeonsi/radeonsi_pm4.c 2013-08-14 03:34:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/radeonsi_pm4.c 2013-08-28 04:15:13.856313555 +0200 @@ -28,7 +28,7 @@ #include "radeonsi_pipe.h" #include "radeonsi_pm4.h" #include "sid.h" -#include "r600_hw_context_priv.h" +#include "radeonsi_hw_context_priv.h" #define NUMBER_OF_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *)) @@ -75,7 +75,7 @@ reg -= CIK_UCONFIG_REG_OFFSET; } else { - R600_ERR("Invalid register offset %08x!\n", reg); + RADEONSI_ERR("Invalid register offset %08x!\n", reg); return; } @@ -156,7 +156,7 @@ state->cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1); } -void si_pm4_free_state(struct r600_context *rctx, +void si_pm4_free_state(struct radeonsi_context *rctx, struct si_pm4_state *state, unsigned idx) { @@ -173,7 +173,7 @@ FREE(state); } -struct si_pm4_state * si_pm4_alloc_state(struct r600_context *rctx) +struct si_pm4_state * si_pm4_alloc_state(struct radeonsi_context *rctx) { struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); @@ -185,7 +185,7 @@ return pm4; } -uint32_t si_pm4_sync_flags(struct r600_context *rctx) +uint32_t si_pm4_sync_flags(struct radeonsi_context *rctx) { uint32_t cp_coher_cntl = 0; @@ -200,7 +200,7 @@ return cp_coher_cntl; } -unsigned si_pm4_dirty_dw(struct r600_context *rctx) +unsigned si_pm4_dirty_dw(struct radeonsi_context *rctx) { unsigned count = 0; @@ -211,10 +211,10 @@ continue; count += state->ndw; -#if R600_TRACE_CS +#if RADEONSI_TRACE_CS /* for tracing each states */ if (rctx->screen->trace_bo) { - count += R600_TRACE_CS_DWORDS; + count += RADEONSI_TRACE_CS_DWORDS; } #endif } @@ -222,11 +222,11 @@ return count; } -void si_pm4_emit(struct r600_context *rctx, struct si_pm4_state *state) +void si_pm4_emit(struct radeonsi_context *rctx, struct si_pm4_state *state) { struct radeon_winsys_cs *cs = rctx->cs; for (int i = 0; i < state->nbo; ++i) { - r600_context_bo_reloc(rctx, state->bo[i], + radeonsi_context_bo_reloc(rctx, state->bo[i], state->bo_usage[i]); } @@ -238,14 +238,14 @@ cs->cdw += state->ndw; -#if R600_TRACE_CS +#if RADEONSI_TRACE_CS if (rctx->screen->trace_bo) { - r600_trace_emit(rctx); + radeonsi_trace_emit(rctx); } #endif } -void si_pm4_emit_dirty(struct r600_context *rctx) +void si_pm4_emit_dirty(struct radeonsi_context *rctx) { for (int i = 0; i < NUMBER_OF_STATES; ++i) { struct si_pm4_state *state = rctx->queued.array[i]; @@ -258,7 +258,7 @@ } } -void si_pm4_reset_emitted(struct r600_context *rctx) +void si_pm4_reset_emitted(struct radeonsi_context *rctx) { memset(&rctx->emitted, 0, sizeof(rctx->emitted)); } diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_pm4.h b/src/gallium/drivers/radeonsi/radeonsi_pm4.h --- a/src/gallium/drivers/radeonsi/radeonsi_pm4.h 2013-08-14 03:34:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/radeonsi_pm4.h 2013-08-28 04:15:13.856313555 +0200 @@ -34,7 +34,7 @@ #define SI_PM4_MAX_RELOCS 4 // forward defines -struct r600_context; +struct radeonsi_context; enum chip_class; struct si_pm4_state @@ -83,15 +83,15 @@ void si_pm4_inval_fb_cache(struct si_pm4_state *state, unsigned nr_cbufs); void si_pm4_inval_zsbuf_cache(struct si_pm4_state *state); -void si_pm4_free_state(struct r600_context *rctx, +void si_pm4_free_state(struct radeonsi_context *rctx, struct si_pm4_state *state, unsigned idx); -struct si_pm4_state * si_pm4_alloc_state(struct r600_context *rctx); +struct si_pm4_state * si_pm4_alloc_state(struct radeonsi_context *rctx); -uint32_t si_pm4_sync_flags(struct r600_context *rctx); -unsigned si_pm4_dirty_dw(struct r600_context *rctx); -void si_pm4_emit(struct r600_context *rctx, struct si_pm4_state *state); -void si_pm4_emit_dirty(struct r600_context *rctx); -void si_pm4_reset_emitted(struct r600_context *rctx); +uint32_t si_pm4_sync_flags(struct radeonsi_context *rctx); +unsigned si_pm4_dirty_dw(struct radeonsi_context *rctx); +void si_pm4_emit(struct radeonsi_context *rctx, struct si_pm4_state *state); +void si_pm4_emit_dirty(struct radeonsi_context *rctx); +void si_pm4_reset_emitted(struct radeonsi_context *rctx); #endif diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_query.c b/src/gallium/drivers/radeonsi/radeonsi_query.c --- a/src/gallium/drivers/radeonsi/radeonsi_query.c 1970-01-01 01:00:00.000000000 +0100 +++ b/src/gallium/drivers/radeonsi/radeonsi_query.c 2013-08-28 04:15:13.856313555 +0200 @@ -0,0 +1,132 @@ +/* + * Copyright 2010 Jerome Glisse + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include "radeonsi_pipe.h" +#include "sid.h" + +static struct pipe_query *radeonsi_create_query(struct pipe_context *ctx, unsigned query_type) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + + return (struct pipe_query*)radeonsi_context_query_create(rctx, query_type); +} + +static void radeonsi_destroy_query(struct pipe_context *ctx, struct pipe_query *query) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + + radeonsi_context_query_destroy(rctx, (struct radeonsi_query *)query); +} + +static void radeonsi_begin_query(struct pipe_context *ctx, struct pipe_query *query) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + struct radeonsi_query *rquery = (struct radeonsi_query *)query; + + memset(&rquery->result, 0, sizeof(rquery->result)); + rquery->results_start = rquery->results_end; + radeonsi_query_begin(rctx, (struct radeonsi_query *)query); + LIST_ADDTAIL(&rquery->list, &rctx->active_query_list); +} + +static void radeonsi_end_query(struct pipe_context *ctx, struct pipe_query *query) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + struct radeonsi_query *rquery = (struct radeonsi_query *)query; + + radeonsi_query_end(rctx, rquery); + LIST_DELINIT(&rquery->list); +} + +static boolean radeonsi_get_query_result(struct pipe_context *ctx, + struct pipe_query *query, + boolean wait, union pipe_query_result *vresult) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + struct radeonsi_query *rquery = (struct radeonsi_query *)query; + + return radeonsi_context_query_result(rctx, rquery, wait, vresult); +} + +static void radeonsi_render_condition(struct pipe_context *ctx, + struct pipe_query *query, + boolean condition, + uint mode) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + struct radeonsi_query *rquery = (struct radeonsi_query *)query; + int wait_flag = 0; + + /* If we already have nonzero result, render unconditionally */ + if (query != NULL && rquery->result.u64 != 0) { + if (rctx->current_render_cond) { + radeonsi_render_condition(ctx, NULL, FALSE, 0); + } + return; + } + + rctx->current_render_cond = query; + rctx->current_render_cond_cond = condition; + rctx->current_render_cond_mode = mode; + + if (query == NULL) { + if (rctx->predicate_drawing) { + rctx->predicate_drawing = false; + radeonsi_query_predication(rctx, NULL, PREDICATION_OP_CLEAR, 1); + } + return; + } + + if (mode == PIPE_RENDER_COND_WAIT || + mode == PIPE_RENDER_COND_BY_REGION_WAIT) { + wait_flag = 1; + } + + rctx->predicate_drawing = true; + + switch (rquery->type) { + case PIPE_QUERY_OCCLUSION_COUNTER: + case PIPE_QUERY_OCCLUSION_PREDICATE: + radeonsi_query_predication(rctx, rquery, PREDICATION_OP_ZPASS, wait_flag); + break; + case PIPE_QUERY_PRIMITIVES_EMITTED: + case PIPE_QUERY_PRIMITIVES_GENERATED: + case PIPE_QUERY_SO_STATISTICS: + case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + radeonsi_query_predication(rctx, rquery, PREDICATION_OP_PRIMCOUNT, wait_flag); + break; + default: + assert(0); + } +} + +void radeonsi_init_query_functions(struct radeonsi_context *rctx) +{ + rctx->context.create_query = radeonsi_create_query; + rctx->context.destroy_query = radeonsi_destroy_query; + rctx->context.begin_query = radeonsi_begin_query; + rctx->context.end_query = radeonsi_end_query; + rctx->context.get_query_result = radeonsi_get_query_result; + + if (rctx->screen->info.r600_num_backends > 0) + rctx->context.render_condition = radeonsi_render_condition; +} diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_resource.c b/src/gallium/drivers/radeonsi/radeonsi_resource.c --- a/src/gallium/drivers/radeonsi/radeonsi_resource.c 1970-01-01 01:00:00.000000000 +0100 +++ b/src/gallium/drivers/radeonsi/radeonsi_resource.c 2013-08-28 04:15:13.856313555 +0200 @@ -0,0 +1,61 @@ +/* + * Copyright 2010 Marek Olšák target == PIPE_BUFFER) { + return si_buffer_create(screen, templ); + } else { + return si_texture_create(screen, templ); + } +} + +static struct pipe_resource *radeonsi_resource_from_handle(struct pipe_screen * screen, + const struct pipe_resource *templ, + struct winsys_handle *whandle) +{ + if (templ->target == PIPE_BUFFER) { + return NULL; + } else { + return si_texture_from_handle(screen, templ, whandle); + } +} + +void radeonsi_init_screen_resource_functions(struct pipe_screen *screen) +{ + screen->resource_create = radeonsi_resource_create; + screen->resource_from_handle = radeonsi_resource_from_handle; + screen->resource_get_handle = u_resource_get_handle_vtbl; + screen->resource_destroy = u_resource_destroy_vtbl; +} + +void radeonsi_init_context_resource_functions(struct radeonsi_context *radeonsi) +{ + radeonsi->context.transfer_map = u_transfer_map_vtbl; + radeonsi->context.transfer_flush_region = u_transfer_flush_region_vtbl; + radeonsi->context.transfer_unmap = u_transfer_unmap_vtbl; + radeonsi->context.transfer_inline_write = u_default_transfer_inline_write; +} diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_resource.h b/src/gallium/drivers/radeonsi/radeonsi_resource.h --- a/src/gallium/drivers/radeonsi/radeonsi_resource.h 2013-06-27 20:13:13.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/radeonsi_resource.h 2013-08-28 04:15:13.856313555 +0200 @@ -1,5 +1,5 @@ /* - * Copyright 2012 Advanced Micro Devices, Inc. + * Copyright 2010 Marek Olšák */ - #ifndef RADEONSI_RESOURCE_H #define RADEONSI_RESOURCE_H @@ -31,22 +27,26 @@ #include "util/u_transfer.h" #include "util/u_inlines.h" +/* flag to indicate a resource is to be used as a transfer so should not be tiled */ +#define RADEONSI_RESOURCE_FLAG_TRANSFER PIPE_RESOURCE_FLAG_DRV_PRIV +#define RADEONSI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1) + struct si_resource { - struct u_resource b; + struct u_resource b; - /* Winsys objects. */ - struct pb_buffer *buf; - struct radeon_winsys_cs_handle *cs_buf; + /* Winsys objects. */ + struct pb_buffer *buf; + struct radeon_winsys_cs_handle *cs_buf; - /* Resource state. */ - unsigned domains; + /* Resource state. */ + unsigned domains; }; static INLINE void si_resource_reference(struct si_resource **ptr, struct si_resource *res) { - pipe_resource_reference((struct pipe_resource **)ptr, - (struct pipe_resource *)res); + pipe_resource_reference((struct pipe_resource **)ptr, + (struct pipe_resource *)res); } static INLINE struct si_resource * @@ -57,11 +57,61 @@ static INLINE struct si_resource * si_resource_create_custom(struct pipe_screen *screen, - unsigned usage, unsigned size) + unsigned usage, unsigned size) { - assert(size); - return si_resource(pipe_buffer_create(screen, - PIPE_BIND_CUSTOM, usage, size)); + assert(size); + return si_resource(pipe_buffer_create(screen, + PIPE_BIND_CUSTOM, usage, size)); } +/* Texture transfer. */ +struct radeonsi_transfer { + /* Base class. */ + struct pipe_transfer transfer; + /* Buffer transfer. */ + struct pipe_transfer *buffer_transfer; + unsigned offset; + struct pipe_resource *staging; +}; + +struct radeonsi_resource_texture { + struct si_resource resource; + + /* If this resource is a depth-stencil buffer on evergreen, this contains + * the depth part of the format. There is a separate stencil resource + * for the stencil buffer below. */ + enum pipe_format real_format; + + unsigned pitch_override; + unsigned is_depth; + unsigned dirty_db_mask; /* each bit says if that miplevel is dirty */ + struct radeonsi_resource_texture *flushed_depth_texture; + boolean is_flushing_texture; + struct radeon_surface surface; +}; + +struct radeonsi_surface { + struct pipe_surface base; +}; + +void radeonsi_init_screen_resource_functions(struct pipe_screen *screen); + +/* radeonsi_texture */ +struct pipe_resource *si_texture_create(struct pipe_screen *screen, + const struct pipe_resource *templ); +struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, + const struct pipe_resource *base, + struct winsys_handle *whandle); + +bool radeonsi_init_flushed_depth_texture(struct pipe_context *ctx, + struct pipe_resource *texture, + struct radeonsi_resource_texture **staging); + + +struct radeonsi_context; + +void radeonsi_upload_const_buffer(struct radeonsi_context *rctx, struct si_resource **rbuffer, + const uint8_t *ptr, unsigned size, + uint32_t *const_offset); + #endif diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c --- a/src/gallium/drivers/radeonsi/radeonsi_shader.c 2013-08-16 00:16:44.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c 2013-08-28 04:15:13.856313555 +0200 @@ -890,7 +890,7 @@ last_args, 9); } /* XXX: Look up what this function does */ -/* ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/ +/* ctx->shader->output[i].spi_sid = radeonsi_spi_sid(&ctx->shader->output[i]);*/ } static void tex_fetch_args( @@ -1349,7 +1349,7 @@ } } -int si_compile_llvm(struct r600_context *rctx, struct si_pipe_shader *shader, +int si_compile_llvm(struct radeonsi_context *rctx, struct si_pipe_shader *shader, LLVMModuleRef mod) { unsigned i; @@ -1361,7 +1361,7 @@ memset(&binary, 0, sizeof(binary)); radeon_llvm_compile(mod, &binary, - r600_get_llvm_processor_name(rctx->screen->family), dump); + radeonsi_get_llvm_processor_name(rctx->screen->family), dump); if (dump) { fprintf(stderr, "SI CODE:\n"); for (i = 0; i < binary.code_size; i+=4 ) { @@ -1410,7 +1410,7 @@ } ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE); - if (0 /*R600_BIG_ENDIAN*/) { + if (0 /*RADEONSI_BIG_ENDIAN*/) { for (i = 0; i < binary.code_size / 4; ++i) { ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4)); } @@ -1429,7 +1429,7 @@ struct pipe_context *ctx, struct si_pipe_shader *shader) { - struct r600_context *rctx = (struct r600_context*)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context*)ctx; struct si_pipe_shader_selector *sel = shader->selector; struct si_shader_context si_shader_ctx; struct tgsi_shader_info shader_info; diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_shader.h b/src/gallium/drivers/radeonsi/radeonsi_shader.h --- a/src/gallium/drivers/radeonsi/radeonsi_shader.h 2013-08-16 00:16:44.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/radeonsi_shader.h 2013-08-28 04:15:13.857313555 +0200 @@ -151,7 +151,7 @@ /* radeonsi_shader.c */ int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader); int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader); -int si_compile_llvm(struct r600_context *rctx, struct si_pipe_shader *shader, +int si_compile_llvm(struct radeonsi_context *rctx, struct si_pipe_shader *shader, LLVMModuleRef mod); void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader); diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_texture.c b/src/gallium/drivers/radeonsi/radeonsi_texture.c --- a/src/gallium/drivers/radeonsi/radeonsi_texture.c 1970-01-01 01:00:00.000000000 +0100 +++ b/src/gallium/drivers/radeonsi/radeonsi_texture.c 2013-08-28 04:15:13.857313555 +0200 @@ -0,0 +1,678 @@ +/* + * Copyright 2010 Jerome Glisse + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Corbin Simpson + */ +#include +#include "pipe/p_screen.h" +#include "util/u_format.h" +#include "util/u_format_s3tc.h" +#include "util/u_math.h" +#include "util/u_inlines.h" +#include "util/u_memory.h" +#include "pipebuffer/pb_buffer.h" +#include "radeonsi_pipe.h" +#include "radeonsi_resource.h" +#include "sid.h" + +/* Copy from a full GPU texture to a transfer's staging one. */ +static void radeonsi_copy_to_staging_texture(struct pipe_context *ctx, struct radeonsi_transfer *rtransfer) +{ + struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; + struct pipe_resource *texture = transfer->resource; + + ctx->resource_copy_region(ctx, rtransfer->staging, + 0, 0, 0, 0, texture, transfer->level, + &transfer->box); +} + +/* Copy from a transfer's staging texture to a full GPU one. */ +static void radeonsi_copy_from_staging_texture(struct pipe_context *ctx, struct radeonsi_transfer *rtransfer) +{ + struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; + struct pipe_resource *texture = transfer->resource; + struct pipe_box sbox; + + u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox); + + ctx->resource_copy_region(ctx, texture, transfer->level, + transfer->box.x, transfer->box.y, transfer->box.z, + rtransfer->staging, + 0, &sbox); +} + +static unsigned radeonsi_texture_get_offset(struct radeonsi_resource_texture *rtex, + unsigned level, unsigned layer) +{ + return rtex->surface.level[level].offset + + layer * rtex->surface.level[level].slice_size; +} + +static int radeonsi_init_surface(struct radeonsi_screen *rscreen, + struct radeon_surface *surface, + const struct pipe_resource *ptex, + unsigned array_mode, + bool is_flushed_depth) +{ + const struct util_format_description *desc = + util_format_description(ptex->format); + bool is_depth, is_stencil; + + is_depth = util_format_has_depth(desc); + is_stencil = util_format_has_stencil(desc); + + surface->npix_x = ptex->width0; + surface->npix_y = ptex->height0; + surface->npix_z = ptex->depth0; + surface->blk_w = util_format_get_blockwidth(ptex->format); + surface->blk_h = util_format_get_blockheight(ptex->format); + surface->blk_d = 1; + surface->array_size = 1; + surface->last_level = ptex->last_level; + + if (!is_flushed_depth && + ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { + surface->bpe = 4; /* stencil is allocated separately on evergreen */ + } else { + surface->bpe = util_format_get_blocksize(ptex->format); + /* align byte per element on dword */ + if (surface->bpe == 3) { + surface->bpe = 4; + } + } + + surface->nsamples = 1; + surface->flags = 0; + switch (array_mode) { + case V_009910_ARRAY_1D_TILED_THIN1: + surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); + break; + case V_009910_ARRAY_2D_TILED_THIN1: + surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); + break; + case V_009910_ARRAY_LINEAR_ALIGNED: + surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); + break; + case V_009910_ARRAY_LINEAR_GENERAL: + default: + surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); + break; + } + switch (ptex->target) { + case PIPE_TEXTURE_1D: + surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE); + break; + case PIPE_TEXTURE_RECT: + case PIPE_TEXTURE_2D: + surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); + break; + case PIPE_TEXTURE_3D: + surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE); + break; + case PIPE_TEXTURE_1D_ARRAY: + surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE); + surface->array_size = ptex->array_size; + break; + case PIPE_TEXTURE_2D_ARRAY: + surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE); + surface->array_size = ptex->array_size; + break; + case PIPE_TEXTURE_CUBE: + surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE); + break; + case PIPE_BUFFER: + default: + return -EINVAL; + } + if (ptex->bind & PIPE_BIND_SCANOUT) { + surface->flags |= RADEON_SURF_SCANOUT; + } + + if (!is_flushed_depth && is_depth) { + surface->flags |= RADEON_SURF_ZBUFFER; + if (is_stencil) { + surface->flags |= RADEON_SURF_SBUFFER | + RADEON_SURF_HAS_SBUFFER_MIPTREE; + } + } + surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; + return 0; +} + +static int radeonsi_setup_surface(struct pipe_screen *screen, + struct radeonsi_resource_texture *rtex, + unsigned array_mode, + unsigned pitch_in_bytes_override) +{ + struct radeonsi_screen *rscreen = (struct radeonsi_screen*)screen; + int r; + + r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface); + if (r) { + return r; + } + if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) { + /* old ddx on evergreen over estimate alignment for 1d, only 1 level + * for those + */ + rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe; + rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override; + rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y; + if (rtex->surface.flags & RADEON_SURF_SBUFFER) { + rtex->surface.stencil_offset = + rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size; + } + } + return 0; +} + +static boolean radeonsi_texture_get_handle(struct pipe_screen* screen, + struct pipe_resource *ptex, + struct winsys_handle *whandle) +{ + struct radeonsi_resource_texture *rtex = (struct radeonsi_resource_texture*)ptex; + struct si_resource *resource = &rtex->resource; + struct radeon_surface *surface = &rtex->surface; + struct radeonsi_screen *rscreen = (struct radeonsi_screen*)screen; + + rscreen->ws->buffer_set_tiling(resource->buf, + NULL, + surface->level[0].mode >= RADEON_SURF_MODE_1D ? + RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, + surface->level[0].mode >= RADEON_SURF_MODE_2D ? + RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, + surface->bankw, surface->bankh, + surface->tile_split, + surface->stencil_tile_split, + surface->mtilea, + surface->level[0].pitch_bytes); + + return rscreen->ws->buffer_get_handle(resource->buf, + surface->level[0].pitch_bytes, whandle); +} + +static void radeonsi_texture_destroy(struct pipe_screen *screen, + struct pipe_resource *ptex) +{ + struct radeonsi_resource_texture *rtex = (struct radeonsi_resource_texture*)ptex; + struct si_resource *resource = &rtex->resource; + + if (rtex->flushed_depth_texture) + si_resource_reference((struct si_resource **)&rtex->flushed_depth_texture, NULL); + + pb_reference(&resource->buf, NULL); + FREE(rtex); +} + +static void *si_texture_transfer_map(struct pipe_context *ctx, + struct pipe_resource *texture, + unsigned level, + unsigned usage, + const struct pipe_box *box, + struct pipe_transfer **ptransfer) +{ + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + struct radeonsi_resource_texture *rtex = (struct radeonsi_resource_texture*)texture; + struct radeonsi_transfer *trans; + boolean use_staging_texture = FALSE; + struct radeon_winsys_cs_handle *buf; + enum pipe_format format = texture->format; + unsigned offset = 0; + char *map; + + /* We cannot map a tiled texture directly because the data is + * in a different order, therefore we do detiling using a blit. + * + * Also, use a temporary in GTT memory for read transfers, as + * the CPU is much happier reading out of cached system memory + * than uncached VRAM. + */ + if (rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR_ALIGNED && + rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR) + use_staging_texture = TRUE; + + /* XXX: Use a staging texture for uploads if the underlying BO + * is busy. No interface for checking that currently? so do + * it eagerly whenever the transfer doesn't require a readback + * and might block. + */ + if ((usage & PIPE_TRANSFER_WRITE) && + !(usage & (PIPE_TRANSFER_READ | + PIPE_TRANSFER_DONTBLOCK | + PIPE_TRANSFER_UNSYNCHRONIZED))) + use_staging_texture = TRUE; + + if (texture->flags & RADEONSI_RESOURCE_FLAG_TRANSFER) + use_staging_texture = FALSE; + + if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) + return NULL; + + trans = CALLOC_STRUCT(radeonsi_transfer); + if (trans == NULL) + return NULL; + pipe_resource_reference(&trans->transfer.resource, texture); + trans->transfer.level = level; + trans->transfer.usage = usage; + trans->transfer.box = *box; + if (rtex->is_depth) { + /* XXX: only readback the rectangle which is being mapped? + */ + /* XXX: when discard is true, no need to read back from depth texture + */ + struct radeonsi_resource_texture *staging_depth; + + if (!radeonsi_init_flushed_depth_texture(ctx, texture, &staging_depth)) { + RADEONSI_ERR("failed to create temporary texture to hold untiled copy\n"); + pipe_resource_reference(&trans->transfer.resource, NULL); + FREE(trans); + return NULL; + } + si_blit_uncompress_depth(ctx, rtex, staging_depth, + level, level, + box->z, box->z + box->depth - 1); + trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes; + trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size; + trans->offset = radeonsi_texture_get_offset(staging_depth, level, box->z); + + trans->staging = &staging_depth->resource.b.b; + } else if (use_staging_texture) { + struct pipe_resource resource; + struct radeonsi_resource_texture *staging; + + memset(&resource, 0, sizeof(resource)); + resource.format = texture->format; + resource.width0 = box->width; + resource.height0 = box->height; + resource.depth0 = 1; + resource.array_size = 1; + resource.usage = PIPE_USAGE_STAGING; + resource.flags = RADEONSI_RESOURCE_FLAG_TRANSFER; + + /* We must set the correct texture target and dimensions if needed for a 3D transfer. */ + if (box->depth > 1 && util_max_layer(texture, level) > 0) + resource.target = texture->target; + else + resource.target = PIPE_TEXTURE_2D; + + switch (resource.target) { + case PIPE_TEXTURE_1D_ARRAY: + case PIPE_TEXTURE_2D_ARRAY: + case PIPE_TEXTURE_CUBE_ARRAY: + resource.array_size = box->depth; + break; + case PIPE_TEXTURE_3D: + resource.depth0 = box->depth; + break; + default:; + } + /* Create the temporary texture. */ + staging = (struct radeonsi_resource_texture*)ctx->screen->resource_create(ctx->screen, &resource); + if (staging == NULL) { + RADEONSI_ERR("failed to create temporary texture to hold untiled copy\n"); + pipe_resource_reference(&trans->transfer.resource, NULL); + FREE(trans); + return NULL; + } + + trans->staging = &staging->resource.b.b; + trans->transfer.stride = staging->surface.level[0].pitch_bytes; + trans->transfer.layer_stride = staging->surface.level[0].slice_size; + if (usage & PIPE_TRANSFER_READ) { + radeonsi_copy_to_staging_texture(ctx, trans); + /* Always referenced in the blit. */ + radeonsi_flush(ctx, NULL, 0); + } + } else { + trans->transfer.stride = rtex->surface.level[level].pitch_bytes; + trans->transfer.layer_stride = rtex->surface.level[level].slice_size; + trans->offset = radeonsi_texture_get_offset(rtex, level, box->z); + } + + if (trans->staging) { + buf = si_resource(trans->staging)->cs_buf; + } else { + buf = rtex->resource.cs_buf; + } + + if (rtex->is_depth || !trans->staging) + offset = trans->offset + + box->y / util_format_get_blockheight(format) * trans->transfer.stride + + box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); + + if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) { + pipe_resource_reference(&trans->staging, NULL); + pipe_resource_reference(&trans->transfer.resource, NULL); + FREE(trans); + return NULL; + } + + *ptransfer = &trans->transfer; + return map + offset; +} + +static void si_texture_transfer_unmap(struct pipe_context *ctx, + struct pipe_transfer* transfer) +{ + struct radeonsi_transfer *rtransfer = (struct radeonsi_transfer*)transfer; + struct radeonsi_context *rctx = (struct radeonsi_context*)ctx; + struct radeon_winsys_cs_handle *buf; + struct pipe_resource *texture = transfer->resource; + struct radeonsi_resource_texture *rtex = (struct radeonsi_resource_texture*)texture; + + if (rtransfer->staging) { + buf = si_resource(rtransfer->staging)->cs_buf; + } else { + buf = si_resource(transfer->resource)->cs_buf; + } + rctx->ws->buffer_unmap(buf); + + if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) { + if (rtex->is_depth) { + ctx->resource_copy_region(ctx, texture, transfer->level, + transfer->box.x, transfer->box.y, transfer->box.z, + &si_resource(rtransfer->staging)->b.b, transfer->level, + &transfer->box); + } else { + radeonsi_copy_from_staging_texture(ctx, rtransfer); + } + } + + if (rtransfer->staging) + pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL); + + pipe_resource_reference(&transfer->resource, NULL); + FREE(transfer); +} + +static const struct u_resource_vtbl radeonsi_texture_vtbl = +{ + radeonsi_texture_get_handle, /* get_handle */ + radeonsi_texture_destroy, /* resource_destroy */ + si_texture_transfer_map, /* transfer_map */ + u_default_transfer_flush_region,/* transfer_flush_region */ + si_texture_transfer_unmap, /* transfer_unmap */ + NULL /* transfer_inline_write */ +}; + +DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "RADEON_PRINT_TEXDEPTH", FALSE); + +static struct radeonsi_resource_texture * +radeonsi_texture_create_object(struct pipe_screen *screen, + const struct pipe_resource *base, + unsigned array_mode, + unsigned pitch_in_bytes_override, + unsigned max_buffer_size, + struct pb_buffer *buf, + boolean alloc_bo, + struct radeon_surface *surface) +{ + struct radeonsi_resource_texture *rtex; + struct si_resource *resource; + struct radeonsi_screen *rscreen = (struct radeonsi_screen*)screen; + int r; + + rtex = CALLOC_STRUCT(radeonsi_resource_texture); + if (rtex == NULL) + return NULL; + + resource = &rtex->resource; + resource->b.b = *base; + resource->b.vtbl = &radeonsi_texture_vtbl; + pipe_reference_init(&resource->b.b.reference, 1); + resource->b.b.screen = screen; + rtex->pitch_override = pitch_in_bytes_override; + rtex->real_format = base->format; + + /* don't include stencil-only formats which we don't support for rendering */ + rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format)); + + rtex->surface = *surface; + r = radeonsi_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override); + if (r) { + FREE(rtex); + return NULL; + } + + /* Now create the backing buffer. */ + if (!buf && alloc_bo) { + unsigned base_align = rtex->surface.bo_alignment; + unsigned size = rtex->surface.bo_size; + + base_align = rtex->surface.bo_alignment; + if (!si_init_resource(rscreen, resource, size, base_align, FALSE, base->usage)) { + FREE(rtex); + return NULL; + } + } else if (buf) { + resource->buf = buf; + resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); + resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; + } + + if (debug_get_option_print_texdepth() && rtex->is_depth) { + printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, " + "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, " + "bpe=%u, nsamples=%u, flags=%u\n", + rtex->surface.npix_x, rtex->surface.npix_y, + rtex->surface.npix_z, rtex->surface.blk_w, + rtex->surface.blk_h, rtex->surface.blk_d, + rtex->surface.array_size, rtex->surface.last_level, + rtex->surface.bpe, rtex->surface.nsamples, + rtex->surface.flags); + if (rtex->surface.flags & RADEON_SURF_ZBUFFER) { + for (int i = 0; i <= rtex->surface.last_level; i++) { + printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, " + "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " + "nblk_z=%u, pitch_bytes=%u, mode=%u\n", + i, rtex->surface.level[i].offset, + rtex->surface.level[i].slice_size, + rtex->surface.level[i].npix_x, + rtex->surface.level[i].npix_y, + rtex->surface.level[i].npix_z, + rtex->surface.level[i].nblk_x, + rtex->surface.level[i].nblk_y, + rtex->surface.level[i].nblk_z, + rtex->surface.level[i].pitch_bytes, + rtex->surface.level[i].mode); + } + } + if (rtex->surface.flags & RADEON_SURF_SBUFFER) { + for (int i = 0; i <= rtex->surface.last_level; i++) { + printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, " + "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " + "nblk_z=%u, pitch_bytes=%u, mode=%u\n", + i, rtex->surface.stencil_level[i].offset, + rtex->surface.stencil_level[i].slice_size, + rtex->surface.stencil_level[i].npix_x, + rtex->surface.stencil_level[i].npix_y, + rtex->surface.stencil_level[i].npix_z, + rtex->surface.stencil_level[i].nblk_x, + rtex->surface.stencil_level[i].nblk_y, + rtex->surface.stencil_level[i].nblk_z, + rtex->surface.stencil_level[i].pitch_bytes, + rtex->surface.stencil_level[i].mode); + } + } + } + return rtex; +} + +struct pipe_resource *si_texture_create(struct pipe_screen *screen, + const struct pipe_resource *templ) +{ + struct radeonsi_screen *rscreen = (struct radeonsi_screen*)screen; + struct radeon_surface surface; + unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED; + int r; + + if (!(templ->flags & RADEONSI_RESOURCE_FLAG_TRANSFER) && + !(templ->bind & PIPE_BIND_SCANOUT)) { + if (util_format_is_compressed(templ->format)) { + array_mode = V_009910_ARRAY_1D_TILED_THIN1; + } else { + if (rscreen->chip_class >= CIK) + array_mode = V_009910_ARRAY_1D_TILED_THIN1; /* XXX fix me */ + else + array_mode = V_009910_ARRAY_2D_TILED_THIN1; + } + } + + r = radeonsi_init_surface(rscreen, &surface, templ, array_mode, + templ->flags & RADEONSI_RESOURCE_FLAG_FLUSHED_DEPTH); + if (r) { + return NULL; + } + r = rscreen->ws->surface_best(rscreen->ws, &surface); + if (r) { + return NULL; + } + return (struct pipe_resource *)radeonsi_texture_create_object(screen, templ, array_mode, + 0, 0, NULL, TRUE, &surface); +} + +static struct pipe_surface *radeonsi_create_surface(struct pipe_context *pipe, + struct pipe_resource *texture, + const struct pipe_surface *surf_tmpl) +{ + struct radeonsi_resource_texture *rtex = (struct radeonsi_resource_texture*)texture; + struct radeonsi_surface *surface = CALLOC_STRUCT(radeonsi_surface); + unsigned level = surf_tmpl->u.tex.level; + + assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level)); + assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level)); + assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); + if (surface == NULL) + return NULL; + /* XXX no offset */ +/* offset = radeonsi_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/ + pipe_reference_init(&surface->base.reference, 1); + pipe_resource_reference(&surface->base.texture, texture); + surface->base.context = pipe; + surface->base.format = surf_tmpl->format; + surface->base.width = rtex->surface.level[level].npix_x; + surface->base.height = rtex->surface.level[level].npix_y; + surface->base.texture = texture; + surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer; + surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer; + surface->base.u.tex.level = level; + + return &surface->base; +} + +static void radeonsi_surface_destroy(struct pipe_context *pipe, + struct pipe_surface *surface) +{ + pipe_resource_reference(&surface->texture, NULL); + FREE(surface); +} + +struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, + const struct pipe_resource *templ, + struct winsys_handle *whandle) +{ + struct radeonsi_screen *rscreen = (struct radeonsi_screen*)screen; + struct pb_buffer *buf = NULL; + unsigned stride = 0; + unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED; + enum radeon_bo_layout micro, macro; + struct radeon_surface surface; + int r; + + /* Support only 2D textures without mipmaps */ + if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || + templ->depth0 != 1 || templ->last_level != 0) + return NULL; + + buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); + if (!buf) + return NULL; + + rscreen->ws->buffer_get_tiling(buf, µ, ¯o, + &surface.bankw, &surface.bankh, + &surface.tile_split, + &surface.stencil_tile_split, + &surface.mtilea); + + if (macro == RADEON_LAYOUT_TILED) + array_mode = V_009910_ARRAY_2D_TILED_THIN1; + else if (micro == RADEON_LAYOUT_TILED) + array_mode = V_009910_ARRAY_1D_TILED_THIN1; + else + array_mode = V_009910_ARRAY_LINEAR_ALIGNED; + + r = radeonsi_init_surface(rscreen, &surface, templ, array_mode, false); + if (r) { + return NULL; + } + /* always set the scanout flags */ + surface.flags |= RADEON_SURF_SCANOUT; + return (struct pipe_resource *)radeonsi_texture_create_object(screen, templ, array_mode, + stride, 0, buf, FALSE, &surface); +} + +bool radeonsi_init_flushed_depth_texture(struct pipe_context *ctx, + struct pipe_resource *texture, + struct radeonsi_resource_texture **staging) +{ + struct radeonsi_resource_texture *rtex = (struct radeonsi_resource_texture*)texture; + struct pipe_resource resource; + struct radeonsi_resource_texture **flushed_depth_texture = staging ? + staging : &rtex->flushed_depth_texture; + + if (!staging && rtex->flushed_depth_texture) + return true; /* it's ready */ + + resource.target = texture->target; + resource.format = texture->format; + resource.width0 = texture->width0; + resource.height0 = texture->height0; + resource.depth0 = texture->depth0; + resource.array_size = texture->array_size; + resource.last_level = texture->last_level; + resource.nr_samples = texture->nr_samples; + resource.usage = staging ? PIPE_USAGE_DYNAMIC : PIPE_USAGE_DEFAULT; + resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL; + resource.flags = texture->flags | RADEONSI_RESOURCE_FLAG_FLUSHED_DEPTH; + + if (staging) + resource.flags |= RADEONSI_RESOURCE_FLAG_TRANSFER; + else + rtex->dirty_db_mask = (1 << (resource.last_level+1)) - 1; + + *flushed_depth_texture = (struct radeonsi_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource); + if (*flushed_depth_texture == NULL) { + RADEONSI_ERR("failed to create temporary texture to hold flushed depth\n"); + return false; + } + + (*flushed_depth_texture)->is_flushing_texture = TRUE; + return true; +} + +void si_init_surface_functions(struct radeonsi_context *radeonsi) +{ + radeonsi->context.create_surface = radeonsi_create_surface; + radeonsi->context.surface_destroy = radeonsi_surface_destroy; +} diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_translate.c b/src/gallium/drivers/radeonsi/radeonsi_translate.c --- a/src/gallium/drivers/radeonsi/radeonsi_translate.c 1970-01-01 01:00:00.000000000 +0100 +++ b/src/gallium/drivers/radeonsi/radeonsi_translate.c 2013-08-28 04:15:13.857313555 +0200 @@ -0,0 +1,53 @@ +/* + * Copyright 2010 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + */ + +#include "util/u_index_modify.h" +#include "util/u_upload_mgr.h" +#include "radeonsi_pipe.h" + + +void radeonsi_translate_index_buffer(struct radeonsi_context *radeonsi, + struct pipe_index_buffer *ib, + unsigned count) +{ + struct pipe_resource *out_buffer = NULL; + unsigned out_offset; + void *ptr; + + switch (ib->index_size) { + case 1: + u_upload_alloc(radeonsi->uploader, 0, count * 2, + &out_offset, &out_buffer, &ptr); + + util_shorten_ubyte_elts_to_userptr( + &radeonsi->context, ib, 0, ib->offset, count, ptr); + + pipe_resource_reference(&ib->buffer, NULL); + ib->buffer = out_buffer; + ib->offset = out_offset; + ib->index_size = 2; + break; + } +} diff -uNr a/src/gallium/drivers/radeonsi/radeonsi_uvd.c b/src/gallium/drivers/radeonsi/radeonsi_uvd.c --- a/src/gallium/drivers/radeonsi/radeonsi_uvd.c 2013-08-14 03:34:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/radeonsi_uvd.c 2013-08-28 04:15:13.857313555 +0200 @@ -54,8 +54,8 @@ struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe, const struct pipe_video_buffer *tmpl) { - struct r600_context *ctx = (struct r600_context *)pipe; - struct r600_resource_texture *resources[VL_NUM_COMPONENTS] = {}; + struct radeonsi_context *ctx = (struct radeonsi_context *)pipe; + struct radeonsi_resource_texture *resources[VL_NUM_COMPONENTS] = {}; struct radeon_surface *surfaces[VL_NUM_COMPONENTS] = {}; struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {}; const enum pipe_format *resource_formats; @@ -77,16 +77,16 @@ vl_video_buffer_template(&templ, &template, resource_formats[0], 1, array_size, PIPE_USAGE_STATIC, 0); /* TODO: Setting the transfer flag is only a workaround till we get tiling working */ - templ.flags = R600_RESOURCE_FLAG_TRANSFER; - resources[0] = (struct r600_resource_texture *) + templ.flags = RADEONSI_RESOURCE_FLAG_TRANSFER; + resources[0] = (struct radeonsi_resource_texture *) pipe->screen->resource_create(pipe->screen, &templ); if (!resources[0]) goto error; if (resource_formats[1] != PIPE_FORMAT_NONE) { vl_video_buffer_template(&templ, &template, resource_formats[1], 1, array_size, PIPE_USAGE_STATIC, 1); - templ.flags = R600_RESOURCE_FLAG_TRANSFER; - resources[1] = (struct r600_resource_texture *) + templ.flags = RADEONSI_RESOURCE_FLAG_TRANSFER; + resources[1] = (struct radeonsi_resource_texture *) pipe->screen->resource_create(pipe->screen, &templ); if (!resources[1]) goto error; @@ -94,8 +94,8 @@ if (resource_formats[2] != PIPE_FORMAT_NONE) { vl_video_buffer_template(&templ, &template, resource_formats[2], 1, array_size, PIPE_USAGE_STATIC, 2); - templ.flags = R600_RESOURCE_FLAG_TRANSFER; - resources[2] = (struct r600_resource_texture *) + templ.flags = RADEONSI_RESOURCE_FLAG_TRANSFER; + resources[2] = (struct radeonsi_resource_texture *) pipe->screen->resource_create(pipe->screen, &templ); if (!resources[2]) goto error; @@ -133,8 +133,8 @@ /* set the decoding target buffer offsets */ static struct radeon_winsys_cs_handle* radeonsi_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf) { - struct r600_resource_texture *luma = (struct r600_resource_texture *)buf->resources[0]; - struct r600_resource_texture *chroma = (struct r600_resource_texture *)buf->resources[1]; + struct radeonsi_resource_texture *luma = (struct radeonsi_resource_texture *)buf->resources[0]; + struct radeonsi_resource_texture *chroma = (struct radeonsi_resource_texture *)buf->resources[1]; msg->body.decode.dt_field_mode = buf->base.interlaced; @@ -153,7 +153,7 @@ unsigned width, unsigned height, unsigned max_references, bool expect_chunked_decode) { - struct r600_context *ctx = (struct r600_context *)context; + struct radeonsi_context *ctx = (struct radeonsi_context *)context; return ruvd_create_decoder(context, profile, entrypoint, chroma_format, width, height, max_references, expect_chunked_decode, diff -uNr a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c --- a/src/gallium/drivers/radeonsi/si_state.c 2013-08-14 03:34:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/si_state.c 2013-08-28 04:15:13.857313555 +0200 @@ -149,7 +149,7 @@ /* * inferred framebuffer and blender state */ -static void si_update_fb_blend_state(struct r600_context *rctx) +static void si_update_fb_blend_state(struct radeonsi_context *rctx) { struct si_pm4_state *pm4; struct si_state_blend *blend = rctx->queued.named.blend; @@ -187,7 +187,7 @@ case PIPE_BLEND_MAX: return V_028780_COMB_MAX_DST_SRC; default: - R600_ERR("Unknown blend function %d\n", blend_func); + RADEONSI_ERR("Unknown blend function %d\n", blend_func); assert(0); break; } @@ -236,7 +236,7 @@ case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: return V_028780_BLEND_INV_SRC1_ALPHA; default: - R600_ERR("Bad blend factor %d not supported!\n", blend_fact); + RADEONSI_ERR("Bad blend factor %d not supported!\n", blend_fact); assert(0); break; } @@ -306,21 +306,21 @@ static void si_bind_blend_state(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state); si_update_fb_blend_state(rctx); } static void si_delete_blend_state(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state); } static void si_set_blend_color(struct pipe_context *ctx, const struct pipe_blend_color *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); if (pm4 == NULL) @@ -341,7 +341,7 @@ static void si_set_clip_state(struct pipe_context *ctx, const struct pipe_clip_state *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); struct pipe_constant_buffer cb; @@ -374,7 +374,7 @@ unsigned num_scissors, const struct pipe_scissor_state *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); uint32_t tl, br; @@ -400,7 +400,7 @@ unsigned num_viewports, const struct pipe_viewport_state *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport); struct si_pm4_state *pm4 = &viewport->pm4; @@ -424,7 +424,7 @@ /* * inferred state between framebuffer and rasterizer */ -static void si_update_fb_rs_state(struct r600_context *rctx) +static void si_update_fb_rs_state(struct radeonsi_context *rctx) { struct si_state_rasterizer *rs = rctx->queued.named.rasterizer; struct si_pm4_state *pm4; @@ -573,8 +573,8 @@ } /* Divide by two, because 0.5 = 1 pixel. */ si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX, - S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | - S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); + S_028A04_MIN_SIZE(radeonsi_pack_float_12p4(psize_min/2)) | + S_028A04_MAX_SIZE(radeonsi_pack_float_12p4(psize_max/2))); tmp = (unsigned)state->line_width * 8; si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); @@ -597,7 +597,7 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state; if (state == NULL) @@ -614,14 +614,14 @@ static void si_delete_rs_state(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state); } /* * infeered state between dsa and stencil ref */ -static void si_update_dsa_stencil_ref(struct r600_context *rctx) +static void si_update_dsa_stencil_ref(struct radeonsi_context *rctx) { struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); struct pipe_stencil_ref *ref = &rctx->stencil_ref; @@ -647,7 +647,7 @@ static void si_set_pipe_stencil_ref(struct pipe_context *ctx, const struct pipe_stencil_ref *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; rctx->stencil_ref = *state; si_update_dsa_stencil_ref(rctx); } @@ -677,7 +677,7 @@ case PIPE_STENCIL_OP_INVERT: return V_02842C_STENCIL_INVERT; default: - R600_ERR("Unknown stencil op %d", s_op); + RADEONSI_ERR("Unknown stencil op %d", s_op); assert(0); break; } @@ -757,7 +757,7 @@ static void si_bind_dsa_state(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_state_dsa *dsa = state; if (state == NULL) @@ -769,11 +769,11 @@ static void si_delete_dsa_state(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state); } -static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth, +static void *si_create_db_flush_dsa(struct radeonsi_context *rctx, bool copy_depth, bool copy_stencil) { struct pipe_depth_stencil_alpha_state dsa; @@ -1164,7 +1164,7 @@ case PIPE_FORMAT_R32G32B32X32_SINT: return V_028C70_SWAP_STD; default: - R600_ERR("unsupported colorswap format %d\n", format); + RADEONSI_ERR("unsupported colorswap format %d\n", format); return ~0U; } return ~0U; @@ -1172,7 +1172,7 @@ static uint32_t si_colorformat_endian_swap(uint32_t colorformat) { - if (R600_BIG_ENDIAN) { + if (RADEONSI_BIG_ENDIAN) { switch(colorformat) { /* 8-bit buffers. */ case V_028C70_COLOR_8: @@ -1286,7 +1286,7 @@ const struct util_format_description *desc, int first_non_void) { - struct r600_screen *rscreen = (struct r600_screen*)screen; + struct radeonsi_screen *rscreen = (struct radeonsi_screen*)screen; bool enable_s3tc = rscreen->info.drm_minor >= 31; boolean uniform = TRUE; int i; @@ -1467,7 +1467,7 @@ } out_unknown: - /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ + /* RADEONSI_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ return ~0; } @@ -1663,7 +1663,7 @@ unsigned retval = 0; if (target >= PIPE_MAX_TEXTURE_TYPES) { - R600_ERR("r600: unsupported texture type %d\n", target); + RADEONSI_ERR("radeonsi: unsupported texture type %d\n", target); return FALSE; } @@ -1709,7 +1709,7 @@ return retval == usage; } -static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level, bool stencil) +static unsigned si_tile_mode_index(struct radeonsi_resource_texture *rtex, unsigned level, bool stencil) { unsigned tile_mode_index = 0; @@ -1725,11 +1725,11 @@ * framebuffer handling */ -static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, +static void si_cb(struct radeonsi_context *rctx, struct si_pm4_state *pm4, const struct pipe_framebuffer_state *state, int cb) { - struct r600_resource_texture *rtex; - struct r600_surface *surf; + struct radeonsi_resource_texture *rtex; + struct radeonsi_surface *surf; unsigned level = state->cbufs[cb]->u.tex.level; unsigned pitch, slice; unsigned color_info, color_attrib; @@ -1741,8 +1741,8 @@ unsigned blend_clamp = 0, blend_bypass = 0; unsigned max_comp_size; - surf = (struct r600_surface *)state->cbufs[cb]; - rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; + surf = (struct radeonsi_surface *)state->cbufs[cb]; + rtex = (struct radeonsi_resource_texture*)state->cbufs[cb]->texture; offset = rtex->surface.level[level].offset; if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { @@ -1788,7 +1788,7 @@ format = si_translate_colorformat(surf->base.format); if (format == V_028C70_COLOR_INVALID) { - R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format); + RADEONSI_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format); } assert(format != V_028C70_COLOR_INVALID); swap = si_translate_colorswap(surf->base.format); @@ -1823,7 +1823,7 @@ color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) | S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1); - offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture); + offset += radeonsi_resource_va(rctx->context.screen, state->cbufs[cb]->texture); offset >>= 8; /* FIXME handle enabling of CB beyond BASE8 which has different offset */ @@ -1861,12 +1861,12 @@ } } -static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, +static void si_db(struct radeonsi_context *rctx, struct si_pm4_state *pm4, const struct pipe_framebuffer_state *state) { - struct r600_screen *rscreen = rctx->screen; - struct r600_resource_texture *rtex; - struct r600_surface *surf; + struct radeonsi_screen *rscreen = rctx->screen; + struct radeonsi_resource_texture *rtex; + struct radeonsi_surface *surf; unsigned level, pitch, slice, format, tile_mode_index, array_mode; unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config; uint32_t z_info, s_info, db_depth_info; @@ -1878,18 +1878,18 @@ return; } - surf = (struct r600_surface *)state->zsbuf; + surf = (struct radeonsi_surface *)state->zsbuf; level = surf->base.u.tex.level; - rtex = (struct r600_resource_texture*)surf->base.texture; + rtex = (struct radeonsi_resource_texture*)surf->base.texture; format = si_translate_dbformat(rtex->real_format); if (format == V_028040_Z_INVALID) { - R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format); + RADEONSI_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format); } assert(format != V_028040_Z_INVALID); - s_offs = z_offs = r600_resource_va(rctx->context.screen, surf->base.texture); + s_offs = z_offs = radeonsi_resource_va(rctx->context.screen, surf->base.texture); z_offs += rtex->surface.level[level].offset; s_offs += rtex->surface.stencil_level[level].offset; @@ -1972,7 +1972,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, const struct pipe_framebuffer_state *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); uint32_t tl, br; int tl_x, tl_y, br_x, br_y; @@ -2029,7 +2029,7 @@ struct si_pipe_shader_selector *sel, union si_shader_key *key) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; memset(key, 0, sizeof(*key)); if (sel->type == PIPE_SHADER_VERTEX) { @@ -2099,7 +2099,7 @@ r = si_pipe_shader_create(ctx, shader); if (unlikely(r)) { - R600_ERR("Failed to build shader variant (type=%u) %d\n", + RADEONSI_ERR("Failed to build shader variant (type=%u) %d\n", sel->type, r); sel->current = NULL; FREE(shader); @@ -2162,7 +2162,7 @@ static void si_bind_vs_shader(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pipe_shader_selector *sel = state; if (rctx->vs_shader == sel) @@ -2178,7 +2178,7 @@ static void si_bind_ps_shader(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pipe_shader_selector *sel = state; if (rctx->ps_shader == sel) @@ -2195,7 +2195,7 @@ static void si_delete_shader_selector(struct pipe_context *ctx, struct si_pipe_shader_selector *sel) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pipe_shader *p = sel->current, *c; while (p) { @@ -2212,7 +2212,7 @@ static void si_delete_vs_shader(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; if (rctx->vs_shader == sel) { @@ -2224,7 +2224,7 @@ static void si_delete_ps_shader(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; if (rctx->ps_shader == sel) { @@ -2243,7 +2243,7 @@ const struct pipe_sampler_view *state) { struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view); - struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture; + struct radeonsi_resource_texture *tmp = (struct radeonsi_resource_texture*)texture; const struct util_format_description *desc; unsigned format, num_format; uint32_t pitch = 0; @@ -2392,7 +2392,7 @@ depth = texture->array_size; } - va = r600_resource_va(ctx->screen, texture); + va = radeonsi_resource_va(ctx->screen, texture); va += surflevel[0].offset; view->state[0] = va >> 8; view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) | @@ -2421,7 +2421,7 @@ static void si_sampler_view_destroy(struct pipe_context *ctx, struct pipe_sampler_view *state) { - struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state; + struct radeonsi_pipe_sampler_view *resource = (struct radeonsi_pipe_sampler_view *)state; pipe_resource_reference(&state->texture, NULL); FREE(resource); @@ -2488,10 +2488,10 @@ return rstate; } -static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx, +static struct si_pm4_state *si_set_sampler_view(struct radeonsi_context *rctx, unsigned count, struct pipe_sampler_view **views, - struct r600_textures_info *samplers, + struct radeonsi_textures_info *samplers, unsigned user_data_reg) { struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views; @@ -2510,8 +2510,8 @@ views[i]); if (views[i]) { - struct r600_resource_texture *rtex = - (struct r600_resource_texture*)views[i]->texture; + struct radeonsi_resource_texture *rtex = + (struct radeonsi_resource_texture*)views[i]->texture; if (rtex->is_depth && !rtex->is_flushing_texture) { samplers->depth_texture_mask |= 1 << i; @@ -2544,7 +2544,7 @@ static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count, struct pipe_sampler_view **views) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pm4_state *pm4; pm4 = si_set_sampler_view(rctx, count, views, &rctx->vs_samplers, @@ -2555,7 +2555,7 @@ static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count, struct pipe_sampler_view **views) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pm4_state *pm4; pm4 = si_set_sampler_view(rctx, count, views, &rctx->ps_samplers, @@ -2563,9 +2563,9 @@ si_pm4_set_state(rctx, ps_sampler_views, pm4); } -static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned count, +static struct si_pm4_state *si_bind_sampler(struct radeonsi_context *rctx, unsigned count, void **states, - struct r600_textures_info *samplers, + struct radeonsi_textures_info *samplers, unsigned user_data_reg) { struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states; @@ -2620,7 +2620,7 @@ if (border_color_table) { uint64_t va_offset = - r600_resource_va(&rctx->screen->screen, + radeonsi_resource_va(&rctx->screen->screen, (void*)rctx->border_color_table); si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8); @@ -2639,7 +2639,7 @@ static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pm4_state *pm4; pm4 = si_bind_sampler(rctx, count, states, &rctx->vs_samplers, @@ -2649,7 +2649,7 @@ static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pm4_state *pm4; pm4 = si_bind_sampler(rctx, count, states, &rctx->ps_samplers, @@ -2672,8 +2672,8 @@ static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, struct pipe_constant_buffer *input) { - struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_constbuf_state *state = &rctx->constbuf_state[shader]; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; + struct radeonsi_constbuf_state *state = &rctx->constbuf_state[shader]; struct pipe_constant_buffer *cb; const uint8_t *ptr; @@ -2693,7 +2693,7 @@ ptr = input->user_buffer; if (ptr) { - r600_upload_const_buffer(rctx, + radeonsi_upload_const_buffer(rctx, (struct si_resource**)&cb->buffer, ptr, cb->buffer_size, &cb->buffer_offset); } else { @@ -2771,7 +2771,7 @@ static void si_bind_vertex_elements(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_vertex_element *v = (struct si_vertex_element*)state; rctx->vertex_elements = v; @@ -2779,7 +2779,7 @@ static void si_delete_vertex_element(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; if (rctx->vertex_elements == state) rctx->vertex_elements = NULL; @@ -2789,7 +2789,7 @@ static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count, const struct pipe_vertex_buffer *buffers) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count); } @@ -2797,7 +2797,7 @@ static void si_set_index_buffer(struct pipe_context *ctx, const struct pipe_index_buffer *ib) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; if (ib) { pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer); @@ -2817,7 +2817,7 @@ static void si_texture_barrier(struct pipe_context *ctx) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); if (pm4 == NULL) @@ -2828,7 +2828,7 @@ si_pm4_set_state(rctx, texture_barrier, pm4); } -void si_init_state_functions(struct r600_context *rctx) +void si_init_state_functions(struct radeonsi_context *rctx) { rctx->context.create_blend_state = si_create_blend_state; rctx->context.bind_blend_state = si_bind_blend_state; @@ -2891,7 +2891,7 @@ rctx->context.draw_vbo = si_draw_vbo; } -void si_init_config(struct r600_context *rctx) +void si_init_config(struct radeonsi_context *rctx) { struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); diff -uNr a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h --- a/src/gallium/drivers/radeonsi/si_state.h 2013-08-14 03:34:38.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/si_state.h 2013-08-28 04:15:13.857313555 +0200 @@ -144,8 +144,8 @@ int si_shader_select(struct pipe_context *ctx, struct si_pipe_shader_selector *sel, unsigned *dirty); -void si_init_state_functions(struct r600_context *rctx); -void si_init_config(struct r600_context *rctx); +void si_init_state_functions(struct radeonsi_context *rctx); +void si_init_config(struct radeonsi_context *rctx); /* si_state_streamout.c */ struct pipe_stream_output_target * diff -uNr a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c --- a/src/gallium/drivers/radeonsi/si_state_draw.c 2013-08-16 00:16:44.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/si_state_draw.c 2013-08-28 04:15:13.857313555 +0200 @@ -39,7 +39,7 @@ static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pm4_state *pm4; unsigned num_sgprs, num_user_sgprs; unsigned nparams, i, vgpr_comp_cnt; @@ -54,7 +54,7 @@ si_pm4_inval_shader_cache(pm4); /* Certain attributes (position, psize, etc.) don't count as params. - * VS is required to export at least one param and r600_shader_from_tgsi() + * VS is required to export at least one param and radeonsi_shader_from_tgsi() * takes care of adding a dummy export. */ for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) { @@ -84,7 +84,7 @@ V_02870C_SPI_SHADER_4COMP : V_02870C_SPI_SHADER_NONE)); - va = r600_resource_va(ctx->screen, (void *)shader->bo); + va = radeonsi_resource_va(ctx->screen, (void *)shader->bo); si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ); si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8); si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40); @@ -118,7 +118,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct si_pm4_state *pm4; unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control; unsigned num_sgprs, num_user_sgprs; @@ -228,7 +228,7 @@ shader->spi_shader_col_format); si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask); - va = r600_resource_va(ctx->screen, (void *)shader->bo); + va = radeonsi_resource_va(ctx->screen, (void *)shader->bo); si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ); si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8); si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40); @@ -282,12 +282,12 @@ }; unsigned result = prim_conv[pprim]; if (result == ~0) { - R600_ERR("unsupported primitive type %d\n", pprim); + RADEONSI_ERR("unsupported primitive type %d\n", pprim); } return result; } -static bool si_update_draw_info_state(struct r600_context *rctx, +static bool si_update_draw_info_state(struct radeonsi_context *rctx, const struct pipe_draw_info *info) { struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); @@ -346,7 +346,7 @@ return true; } -static void si_update_spi_map(struct r600_context *rctx) +static void si_update_spi_map(struct radeonsi_context *rctx) { struct si_shader *ps = &rctx->ps_shader->current->shader; struct si_shader *vs = &rctx->vs_shader->current->shader; @@ -403,7 +403,7 @@ si_pm4_set_state(rctx, spi, pm4); } -static void si_update_derived_state(struct r600_context *rctx) +static void si_update_derived_state(struct radeonsi_context *rctx) { struct pipe_context * ctx = (struct pipe_context*)rctx; unsigned vs_dirty = 0, ps_dirty = 0; @@ -459,7 +459,7 @@ } } -static void si_constant_buffer_update(struct r600_context *rctx) +static void si_constant_buffer_update(struct radeonsi_context *rctx) { struct pipe_context *ctx = &rctx->context; struct si_pm4_state *pm4; @@ -471,7 +471,7 @@ return; for (shader = PIPE_SHADER_VERTEX ; shader <= PIPE_SHADER_FRAGMENT; shader++) { - struct r600_constbuf_state *state = &rctx->constbuf_state[shader]; + struct radeonsi_constbuf_state *state = &rctx->constbuf_state[shader]; pm4 = CALLOC_STRUCT(si_pm4_state); if (!pm4) @@ -485,7 +485,7 @@ struct pipe_constant_buffer *cb = &state->cb[i]; struct si_resource *rbuffer = si_resource(cb->buffer); - va = r600_resource_va(ctx->screen, (void*)rbuffer); + va = radeonsi_resource_va(ctx->screen, (void*)rbuffer); va += cb->buffer_offset; si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ); @@ -522,7 +522,7 @@ break; default: - R600_ERR("unsupported %d\n", shader); + RADEONSI_ERR("unsupported %d\n", shader); FREE(pm4); return; } @@ -531,7 +531,7 @@ } } -static void si_vertex_buffer_update(struct r600_context *rctx) +static void si_vertex_buffer_update(struct radeonsi_context *rctx) { struct pipe_context *ctx = &rctx->context; struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); @@ -564,7 +564,7 @@ offset += vb->buffer_offset; offset += ve->src_offset; - va = r600_resource_va(ctx->screen, (void*)rbuffer); + va = radeonsi_resource_va(ctx->screen, (void*)rbuffer); va += offset; /* Fill in T# buffer resource description */ @@ -590,7 +590,7 @@ si_pm4_set_state(rctx, vertex_buffers, pm4); } -static void si_state_draw(struct r600_context *rctx, +static void si_state_draw(struct radeonsi_context *rctx, const struct pipe_draw_info *info, const struct pipe_index_buffer *ib) { @@ -614,10 +614,10 @@ /* draw packet */ si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE); if (ib->index_size == 4) { - si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ? + si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (RADEONSI_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_32_BIT : 0)); } else { - si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ? + si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (RADEONSI_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_16_BIT : 0)); } si_pm4_cmd_end(pm4, rctx->predicate_drawing); @@ -630,7 +630,7 @@ uint32_t max_size = (ib->buffer->width0 - ib->offset) / rctx->index_buffer.index_size; uint64_t va; - va = r600_resource_va(&rctx->screen->screen, ib->buffer); + va = radeonsi_resource_va(&rctx->screen->screen, ib->buffer); va += ib->offset; si_pm4_add_bo(pm4, (struct si_resource *)ib->buffer, RADEON_USAGE_READ); @@ -647,7 +647,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) { - struct r600_context *rctx = (struct r600_context *)ctx; + struct radeonsi_context *rctx = (struct radeonsi_context *)ctx; struct pipe_index_buffer ib = {}; uint32_t cp_coher_cntl; @@ -669,14 +669,14 @@ ib.offset = rctx->index_buffer.offset + info->start * ib.index_size; /* Translate or upload, if needed. */ - r600_translate_index_buffer(rctx, &ib, info->count); + radeonsi_translate_index_buffer(rctx, &ib, info->count); if (ib.user_buffer && !ib.buffer) { - r600_upload_index_buffer(rctx, &ib, info->count); + radeonsi_upload_index_buffer(rctx, &ib, info->count); } } else if (info->count_from_stream_output) { - r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info->count_from_stream_output); + radeonsi_context_draw_opaque_count(rctx, (struct radeonsi_so_target*)info->count_from_stream_output); } rctx->vs_shader_so_strides = rctx->vs_shader->current->so_strides; @@ -705,26 +705,26 @@ si_pm4_emit_dirty(rctx); rctx->pm4_dirty_cdwords = 0; -#if R600_TRACE_CS +#if RADEONSI_TRACE_CS if (rctx->screen->trace_bo) { - r600_trace_emit(rctx); + radeonsi_trace_emit(rctx); } #endif #if 0 /* Enable stream out if needed. */ if (rctx->streamout_start) { - r600_context_streamout_begin(rctx); + radeonsi_context_streamout_begin(rctx); rctx->streamout_start = FALSE; } #endif - rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY; + rctx->flags |= RADEONSI_CONTEXT_DST_CACHES_DIRTY; /* Set the depth buffer as dirty. */ if (rctx->framebuffer.zsbuf) { struct pipe_surface *surf = rctx->framebuffer.zsbuf; - struct r600_resource_texture *rtex = (struct r600_resource_texture *)surf->texture; + struct radeonsi_resource_texture *rtex = (struct radeonsi_resource_texture *)surf->texture; rtex->dirty_db_mask |= 1 << surf->u.tex.level; } diff -uNr a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c --- a/src/gallium/drivers/radeonsi/si_state_streamout.c 2013-06-27 20:13:13.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/si_state_streamout.c 2013-08-28 04:15:13.857313555 +0200 @@ -32,7 +32,7 @@ */ #if 0 -void si_context_streamout_begin(struct r600_context *ctx) +void si_context_streamout_begin(struct radeonsi_context *ctx) { struct radeon_winsys_cs *cs = ctx->cs; struct si_so_target **t = ctx->so_targets; @@ -107,7 +107,7 @@ } } -void si_context_streamout_end(struct r600_context *ctx) +void si_context_streamout_end(struct radeonsi_context *ctx) { struct radeon_winsys_cs *cs = ctx->cs; struct si_so_target **t = ctx->so_targets; @@ -203,7 +203,7 @@ unsigned buffer_size) { #if 0 - struct si_context *rctx = (struct r600_context *)ctx; + struct si_context *rctx = (struct radeonsi_context *)ctx; struct si_so_target *t; void *ptr; @@ -232,7 +232,7 @@ struct pipe_stream_output_target *target) { #if 0 - struct si_so_target *t = (struct r600_so_target*)target; + struct si_so_target *t = (struct radeonsi_so_target*)target; pipe_resource_reference(&t->b.buffer, NULL); si_resource_reference(&t->filled_size, NULL); FREE(t); @@ -246,7 +246,7 @@ { assert(num_targets == 0); #if 0 - struct si_context *rctx = (struct r600_context *)ctx; + struct si_context *rctx = (struct radeonsi_context *)ctx; unsigned i; /* Stop streamout. */ diff -uNr a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h --- a/src/gallium/drivers/radeonsi/sid.h 2013-08-14 03:34:42.000000000 +0200 +++ b/src/gallium/drivers/radeonsi/sid.h 2013-08-28 04:15:13.857313555 +0200 @@ -67,7 +67,7 @@ #define PREDICATION_DRAW_NOT_VISIBLE (0 << 8) #define PREDICATION_DRAW_VISIBLE (1 << 8) -#define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7 +#define RADEONSI_TEXEL_PITCH_ALIGNMENT_MASK 0x7 #define PKT3_NOP 0x10 #define PKT3_DISPATCH_DIRECT 0x15