Running Steam on ubuntu 13.04 64-bit
STEAM_RUNTIME is enabled automatically
Installing breakpad exception handler for appid(steam)/version(1378500910_client)
[2013-09-08 03:54:09] Startup - updater built Sep  6 2013 12:04:22
[2013-09-08 03:54:09] Opted in to client beta 'publicbeta' via beta file
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
Installing breakpad exception handler for appid(steam)/version(1378500910_client)
unlinked 0 orphaned pipes
Installing breakpad exception handler for appid(steam)/version(1378500910_client)
[0908/035409:WARNING:proxy_service.cc(958)] PAC support disabled because there is no system implementation
[2013-09-08 03:54:09] Verificando instalación...
[2013-09-08 03:54:09] Verification complete
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
Installing breakpad exception handler for appid(steam)/version(1378500910_client)
Installing breakpad exception handler for appid(steam)/version(1378500910_client)
Installing breakpad exception handler for appid(steam)/version(1378500910_client)
Installing breakpad exception handler for appid(steam)/version(1378500910_client)
Installing breakpad exception handler for appid(steam)/version(1378500910_client)
Installing breakpad exception handler for appid(steam)/version(1378500910_client)
Installing breakpad exception handler for appid(steam)/version(1378500910_client)
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %21 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %22 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %23 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8080300
c8090301
c80c0200
c80d0201
c8100100
c8110101
c8140000
c8150001
f800180f
02030405
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = fmul float %30, %11
  %42 = fmul float %30, %12
  %43 = fmul float %30, %13
  %44 = fmul float %30, %14
  %45 = fmul float %31, %15
  %46 = fadd float %45, %41
  %47 = fmul float %31, %16
  %48 = fadd float %47, %42
  %49 = fmul float %31, %17
  %50 = fadd float %49, %43
  %51 = fmul float %31, %18
  %52 = fadd float %51, %44
  %53 = fmul float %32, %19
  %54 = fadd float %53, %46
  %55 = fmul float %32, %20
  %56 = fadd float %55, %48
  %57 = fmul float %32, %21
  %58 = fadd float %57, %50
  %59 = fmul float %32, %22
  %60 = fadd float %59, %52
  %61 = fmul float %33, %23
  %62 = fadd float %61, %54
  %63 = fmul float %33, %24
  %64 = fadd float %63, %56
  %65 = fmul float %33, %25
  %66 = fadd float %65, %58
  %67 = fmul float %33, %26
  %68 = fadd float %67, %60
  %69 = call float @llvm.AMDIL.clamp.(float %37, float 0,000000e+00, float 0x3FF0000000000000)
  %70 = call float @llvm.AMDIL.clamp.(float %38, float 0,000000e+00, float 0x3FF0000000000000)
  %71 = call float @llvm.AMDIL.clamp.(float %39, float 0,000000e+00, float 0x3FF0000000000000)
  %72 = call float @llvm.AMDIL.clamp.(float %40, float 0,000000e+00, float 0x3FF0000000000000)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %69, float %70, float %71, float %72)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
10080004
c2020107
bf8c007f
d2820004
04100901
c202010b
bf8c007f
d2820004
04100902
c202010f
bf8c007f
d2820004
04100903
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04140901
c202010a
bf8c007f
d2820005
04140902
c202010e
bf8c007f
d2820005
04140903
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
04180901
c2020109
bf8c007f
d2820006
04180902
c202010d
bf8c007f
d2820006
04180903
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041c0901
c2020108
bf8c007f
d2820007
041c0902
c200010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
  %25 = bitcast i32 %24 to float
  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
  %27 = bitcast i32 %26 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
5e000101
c8060102
c80a0002
5e020302
f8001c0f
00010001
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
  %36 = bitcast i32 %35 to float
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
  %36 = bitcast i32 %35 to float
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[1..4]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: MOV TEMP[0].w, IN[0].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], CONST[4]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %32 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %33 = fdiv float %30, %32
  %34 = fdiv float %31, %32
  %35 = bitcast float %33 to i32
  %36 = bitcast float %34 to i32
  %37 = insertelement <2 x i32> undef, i32 %35, i32 0
  %38 = insertelement <2 x i32> %37, i32 %36, i32 1
  %39 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %38, <32 x i8> %27, <16 x i8> %29, i32 2)
  %40 = extractelement <4 x float> %39, i32 0
  %41 = extractelement <4 x float> %39, i32 1
  %42 = extractelement <4 x float> %39, i32 2
  %43 = extractelement <4 x float> %39, i32 3
  %44 = fmul float %40, %22
  %45 = fmul float %41, %23
  %46 = fmul float %42, %24
  %47 = fmul float %43, %25
  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
  %49 = bitcast i32 %48 to float
  %50 = call i32 @llvm.SI.packf16(float %46, float %47)
  %51 = bitcast i32 %50 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %49, float %51, float %49, float %51)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080100
c8090101
c80c0300
c80d0301
7e085503
10060902
c8140000
c8150001
10040905
c0840300
c0c60500
bf8c007f
f0800f00
00430002
c0800100
bf8c0070
c2020113
bf8c007f
10080604
c2020112
bf8c007f
100a0404
5e080905
c2020111
bf8c007f
100a0204
c2000110
bf8c007f
10000000
5e000b00
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV OUT[1], IN[1]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = fmul float %30, %11
  %42 = fmul float %30, %12
  %43 = fmul float %30, %13
  %44 = fmul float %30, %14
  %45 = fmul float %31, %15
  %46 = fadd float %45, %41
  %47 = fmul float %31, %16
  %48 = fadd float %47, %42
  %49 = fmul float %31, %17
  %50 = fadd float %49, %43
  %51 = fmul float %31, %18
  %52 = fadd float %51, %44
  %53 = fmul float %32, %19
  %54 = fadd float %53, %46
  %55 = fmul float %32, %20
  %56 = fadd float %55, %48
  %57 = fmul float %32, %21
  %58 = fadd float %57, %50
  %59 = fmul float %32, %22
  %60 = fadd float %59, %52
  %61 = fmul float %33, %23
  %62 = fadd float %61, %54
  %63 = fmul float %33, %24
  %64 = fadd float %63, %56
  %65 = fmul float %33, %25
  %66 = fadd float %65, %58
  %67 = fmul float %33, %26
  %68 = fadd float %67, %60
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
f800020f
04030201
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
10080004
c2020107
bf8c007f
d2820004
04100901
c202010b
bf8c007f
d2820004
04100902
c202010f
bf8c007f
d2820004
04100903
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04140901
c202010a
bf8c007f
d2820005
04140902
c202010e
bf8c007f
d2820005
04140903
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
04180901
c2020109
bf8c007f
d2820006
04180902
c202010d
bf8c007f
d2820006
04180903
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041c0901
c2020108
bf8c007f
d2820007
041c0902
c200010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
Generating new string page texture 2: 48x256, total string texture memory is 49,15 KB
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: MOV TEMP[0].w, IN[1].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], IN[0]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %31 = fdiv float %28, %30
  %32 = fdiv float %29, %30
  %33 = bitcast float %31 to i32
  %34 = bitcast float %32 to i32
  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %38, %24
  %43 = fmul float %39, %25
  %44 = fmul float %40, %26
  %45 = fmul float %41, %27
  %46 = call i32 @llvm.SI.packf16(float %42, float %43)
  %47 = bitcast i32 %46 to float
  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
  %49 = bitcast i32 %48 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %47, float %49, float %47, float %49)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080500
c8090501
c80c0700
c80d0701
7e085503
10060902
c8140400
c8150401
10040905
c0800300
c0c40500
bf8c007f
f0800f00
00020202
c8180300
c8190301
bf8c0770
100c0d05
c81c0200
c81d0201
100e0f04
5e0c0d07
c81c0100
c81d0101
100e0f03
c8200000
c8210001
10001102
5e000f00
f8001c0f
06000600
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], GENERIC[0]
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: MOV OUT[2], IN[2]
  6: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
  %44 = extractelement <4 x float> %43, i32 0
  %45 = extractelement <4 x float> %43, i32 1
  %46 = extractelement <4 x float> %43, i32 2
  %47 = extractelement <4 x float> %43, i32 3
  %48 = fmul float %30, %11
  %49 = fmul float %30, %12
  %50 = fmul float %30, %13
  %51 = fmul float %30, %14
  %52 = fmul float %31, %15
  %53 = fadd float %52, %48
  %54 = fmul float %31, %16
  %55 = fadd float %54, %49
  %56 = fmul float %31, %17
  %57 = fadd float %56, %50
  %58 = fmul float %31, %18
  %59 = fadd float %58, %51
  %60 = fmul float %32, %19
  %61 = fadd float %60, %53
  %62 = fmul float %32, %20
  %63 = fadd float %62, %55
  %64 = fmul float %32, %21
  %65 = fadd float %64, %57
  %66 = fmul float %32, %22
  %67 = fadd float %66, %59
  %68 = fmul float %33, %23
  %69 = fadd float %68, %61
  %70 = fmul float %33, %24
  %71 = fadd float %70, %63
  %72 = fmul float %33, %25
  %73 = fadd float %72, %65
  %74 = fmul float %33, %26
  %75 = fadd float %74, %67
  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0,000000e+00, float 0x3FF0000000000000)
  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0,000000e+00, float 0x3FF0000000000000)
  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0,000000e+00, float 0x3FF0000000000000)
  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0,000000e+00, float 0x3FF0000000000000)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0840708
bf8c000f
e00c2000
80020100
bf8c0770
f800021f
04030201
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
10080004
c2020107
bf8c007f
d2820004
04100901
c202010b
bf8c007f
d2820004
04100902
c202010f
bf8c007f
d2820004
04100903
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04140901
c202010a
bf8c007f
d2820005
04140902
c202010e
bf8c007f
d2820005
04140903
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
04180901
c2020109
bf8c007f
d2820006
04180902
c202010d
bf8c007f
d2820006
04180903
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041c0901
c2020108
bf8c007f
d2820007
041c0902
c200010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
Generating new string page texture 3: 384x256, total string texture memory is 442,37 KB

(steam:4127): Gtk-WARNING **: Imposible encontrar el motor de temas en la ruta al _modulo: «oxygen-gtk»,

(steam:4127): Gtk-WARNING **: Imposible encontrar el motor de temas en la ruta al _modulo: «oxygen-gtk»,
Installing breakpad exception handler for appid(steam)/version(1378500910_client)
`menu_proxy_module_load': /home/jose/.local/share/Steam/ubuntu12_32/steam: undefined symbol: menu_proxy_module_load

(steam:4127): Gtk-WARNING **: Failed to load type module: (null)


(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Translation has an invalid value 'I-->D' for default text direction.  Defaulting to left-to-right.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
roaming config store loaded successfully - 9188 bytes.
migrating temporary roaming config store

** (steam:4127): WARNING **: replace_settings: error updating connection /org/freedesktop/NetworkManager/Settings/1 settings: (1) type
Adding license for package 0
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ExecCommandLine: "/home/jose/.local/share/Steam/ubuntu12_32/steam"
System startup time: 8,23 seconds
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
Installing breakpad exception handler for appid(steam)/version(1378500910_client)
Installing breakpad exception handler for appid(steam)/version(1378500910_client)
Running Steam on ubuntu 13.04 64-bit
STEAM_RUNTIME has been set by the user to: /home/jose/.local/share/Steam/ubuntu12_32/steam-runtime
Generating new string page texture 74: 1024x256, total string texture memory is 1,49 MB
Generating new string page texture 75: 256x256, total string texture memory is 262,14 KB
Generating new string page texture 76: 256x256, total string texture memory is 1,75 MB
Generating new string page texture 77: 128x256, total string texture memory is 1,88 MB
Generating new string page texture 78: 32x256, total string texture memory is 1,92 MB
Generating new string page texture 79: 64x256, total string texture memory is 1,98 MB
Generating new string page texture 80: 24x256, total string texture memory is 2,01 MB

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:4127): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
ExecCommandLine: "/home/jose/.steam/root/ubuntu12_32/steam steam://open/driverhelperready"
ExecSteamURL: "steam://open/driverhelperready"
Generating new string page texture 86: 256x256, total string texture memory is 2,27 MB
Generating new string page texture 87: 128x256, total string texture memory is 2,40 MB
Generating new string page texture 89: 256x256, total string texture memory is 2,66 MB
CAPIJobRequestUserStats - Server response failed 2
Generating new string page texture 97: 256x256, total string texture memory is 2,92 MB
Generating new string page texture 98: 512x256, total string texture memory is 3,45 MB
Game update: AppID 203770 "Crusader Kings II", ProcID 4229, IP 0.0.0.0:0
Setting breakpad minidump AppID = 203770
Steam_SetMinidumpSteamID:  Caching Steam ID:  76561198042971456 [API loaded no]
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
  %12 = extractelement <4 x float> %11, i32 0
  %13 = extractelement <4 x float> %11, i32 1
  %14 = extractelement <4 x float> %11, i32 2
  %15 = extractelement <4 x float> %11, i32 3
  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
  %19 = extractelement <4 x float> %18, i32 0
  %20 = extractelement <4 x float> %18, i32 1
  %21 = extractelement <4 x float> %18, i32 2
  %22 = extractelement <4 x float> %18, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %32, float %33, float %34)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
f800180f
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %32, float %33, float %34)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
f800180f
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
  %36 = bitcast i32 %35 to float
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = fmul float %30, %11
  %42 = fmul float %30, %12
  %43 = fmul float %30, %13
  %44 = fmul float %30, %14
  %45 = fmul float %31, %15
  %46 = fadd float %45, %41
  %47 = fmul float %31, %16
  %48 = fadd float %47, %42
  %49 = fmul float %31, %17
  %50 = fadd float %49, %43
  %51 = fmul float %31, %18
  %52 = fadd float %51, %44
  %53 = fmul float %32, %19
  %54 = fadd float %53, %46
  %55 = fmul float %32, %20
  %56 = fadd float %55, %48
  %57 = fmul float %32, %21
  %58 = fadd float %57, %50
  %59 = fmul float %32, %22
  %60 = fadd float %59, %52
  %61 = fmul float %33, %23
  %62 = fadd float %61, %54
  %63 = fmul float %33, %24
  %64 = fadd float %63, %56
  %65 = fmul float %33, %25
  %66 = fadd float %65, %58
  %67 = fmul float %33, %26
  %68 = fadd float %67, %60
  %69 = call float @llvm.AMDIL.clamp.(float %37, float 0.000000e+00, float 1.000000e+00)
  %70 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
  %71 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
  %72 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %69, float %70, float %71, float %72)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
10080004
c2020107
bf8c007f
d2820004
04100901
c202010b
bf8c007f
d2820004
04100902
c202010f
bf8c007f
d2820004
04100903
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04140901
c202010a
bf8c007f
d2820005
04140902
c202010e
bf8c007f
d2820005
04140903
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
04180901
c2020109
bf8c007f
d2820006
04180902
c202010d
bf8c007f
d2820006
04180903
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041c0901
c2020108
bf8c007f
d2820007
041c0902
c200010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
  %25 = bitcast i32 %24 to float
  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
  %27 = bitcast i32 %26 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
5e000101
c8060102
c80a0002
5e020302
f8001c0f
00010001
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MUL TEMP[0], TEMP[0], IN[0]
  3: MOV OUT[0], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %30 = bitcast float %28 to i32
  %31 = bitcast float %29 to i32
  %32 = insertelement <2 x i32> undef, i32 %30, i32 0
  %33 = insertelement <2 x i32> %32, i32 %31, i32 1
  %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %33, <32 x i8> %21, <16 x i8> %23, i32 2)
  %35 = extractelement <4 x float> %34, i32 0
  %36 = extractelement <4 x float> %34, i32 1
  %37 = extractelement <4 x float> %34, i32 2
  %38 = extractelement <4 x float> %34, i32 3
  %39 = fmul float %35, %24
  %40 = fmul float %36, %25
  %41 = fmul float %37, %26
  %42 = fmul float %38, %27
  %43 = call i32 @llvm.SI.packf16(float %39, float %40)
  %44 = bitcast i32 %43 to float
  %45 = call i32 @llvm.SI.packf16(float %41, float %42)
  %46 = bitcast i32 %45 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %44, float %46, float %44, float %46)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0500
c80d0501
c8080400
c8090401
c0800300
c0c40500
bf8c007f
f0800f00
00020202
c8180300
c8190301
bf8c0770
100c0d05
c81c0200
c81d0201
100e0f04
5e0c0d07
c81c0100
c81d0101
100e0f03
c8200000
c8210001
10001102
5e000f00
f8001c0f
06000600
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..3]
DCL TEMP[0..1], LOCAL
  0: DP4 TEMP[0].x, IN[0], CONST[0]
  1: DP4 TEMP[1].x, IN[0], CONST[1]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: DP4 TEMP[1].x, IN[0], CONST[2]
  4: MOV TEMP[0].z, TEMP[1].xxxx
  5: DP4 TEMP[1].x, IN[0], CONST[3]
  6: MOV TEMP[0].w, TEMP[1].xxxx
  7: MOV TEMP[1].xy, IN[1].xyxx
  8: MOV OUT[1], IN[2]
  9: MOV OUT[2], TEMP[1]
 10: MOV OUT[0], TEMP[0]
 11: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %40, i32 0, i32 %5)
  %42 = extractelement <4 x float> %41, i32 0
  %43 = extractelement <4 x float> %41, i32 1
  %44 = extractelement <4 x float> %41, i32 2
  %45 = extractelement <4 x float> %41, i32 3
  %46 = fmul float %30, %11
  %47 = fmul float %31, %12
  %48 = fadd float %46, %47
  %49 = fmul float %32, %13
  %50 = fadd float %48, %49
  %51 = fmul float %33, %14
  %52 = fadd float %50, %51
  %53 = fmul float %30, %15
  %54 = fmul float %31, %16
  %55 = fadd float %53, %54
  %56 = fmul float %32, %17
  %57 = fadd float %55, %56
  %58 = fmul float %33, %18
  %59 = fadd float %57, %58
  %60 = fmul float %30, %19
  %61 = fmul float %31, %20
  %62 = fadd float %60, %61
  %63 = fmul float %32, %21
  %64 = fadd float %62, %63
  %65 = fmul float %33, %22
  %66 = fadd float %64, %65
  %67 = fmul float %30, %23
  %68 = fmul float %31, %24
  %69 = fadd float %67, %68
  %70 = fmul float %32, %25
  %71 = fadd float %69, %70
  %72 = fmul float %33, %26
  %73 = fadd float %71, %72
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %42, float %43, float %44, float %45)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %37, float %38, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %52, float %59, float %66, float %73)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840708
bf8c007f
e00c2000
80020100
bf8c0770
f800020f
04030201
c0840704
bf8c000f
e00c2000
80020100
7e0a0280
bf8c0770
f800021f
05050201
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c202010d
bf8c007f
10080204
c202010c
bf8c007f
d2820004
04100900
c202010e
bf8c007f
d2820004
04100902
c202010f
bf8c007f
d2820004
04100903
c2020109
bf8c007f
100a0204
c2020108
bf8c007f
d2820005
04140900
c202010a
bf8c007f
d2820005
04140902
c202010b
bf8c007f
d2820005
04140903
c2020105
bf8c007f
100c0204
c2020104
bf8c007f
d2820006
04180900
c2020106
bf8c007f
d2820006
04180902
c2020107
bf8c007f
d2820006
04180903
c2020101
bf8c007f
100e0204
c2020100
bf8c007f
d2820007
041c0900
c2020102
bf8c007f
d2820007
041c0902
c2000103
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
Installing breakpad exception handler for appid(gameoverlayui)/version(20130906120449_client)
Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
[0908/035423:WARNING:proxy_service.cc(958)] PAC support disabled because there is no system implementation
































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..5]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MUL TEMP[0], TEMP[0], CONST[4]
  3: MOV OUT[0], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %32 = bitcast float %30 to i32
  %33 = bitcast float %31 to i32
  %34 = insertelement <2 x i32> undef, i32 %32, i32 0
  %35 = insertelement <2 x i32> %34, i32 %33, i32 1
  %36 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %27, <16 x i8> %29, i32 2)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = fmul float %37, %22
  %42 = fmul float %38, %23
  %43 = fmul float %39, %24
  %44 = fmul float %40, %25
  %45 = call i32 @llvm.SI.packf16(float %41, float %42)
  %46 = bitcast i32 %45 to float
  %47 = call i32 @llvm.SI.packf16(float %43, float %44)
  %48 = bitcast i32 %47 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %46, float %48, float %46, float %48)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430002
c0800100
bf8c0070
c2020113
bf8c007f
10080604
c2020112
bf8c007f
100a0404
5e080905
c2020111
bf8c007f
100a0204
c2000110
bf8c007f
10000000
5e000b00
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..5]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xyz, IN[0].xyzx
  2: MOV TEMP[1].y, IN[1].yyyy
  3: ADD TEMP[1].x, IN[1].xxxx, CONST[5].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[0]
  5: DP4 TEMP[3].x, TEMP[0], CONST[1]
  6: MOV TEMP[2].y, TEMP[3].xxxx
  7: DP4 TEMP[3].x, TEMP[0], CONST[2]
  8: MOV TEMP[2].z, TEMP[3].xxxx
  9: DP4 TEMP[0].x, TEMP[0], CONST[3]
 10: MOV TEMP[2].w, TEMP[0].xxxx
 11: MOV TEMP[0].xy, TEMP[1].xyxx
 12: MOV OUT[1], TEMP[0]
 13: MOV OUT[0], TEMP[2]
 14: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %28 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %5)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = fadd float %37, %27
  %40 = fmul float %31, %11
  %41 = fmul float %32, %12
  %42 = fadd float %40, %41
  %43 = fmul float %33, %13
  %44 = fadd float %42, %43
  %45 = fmul float 1.000000e+00, %14
  %46 = fadd float %44, %45
  %47 = fmul float %31, %15
  %48 = fmul float %32, %16
  %49 = fadd float %47, %48
  %50 = fmul float %33, %17
  %51 = fadd float %49, %50
  %52 = fmul float 1.000000e+00, %18
  %53 = fadd float %51, %52
  %54 = fmul float %31, %19
  %55 = fmul float %32, %20
  %56 = fadd float %54, %55
  %57 = fmul float %33, %21
  %58 = fadd float %56, %57
  %59 = fmul float 1.000000e+00, %22
  %60 = fadd float %58, %59
  %61 = fmul float %31, %23
  %62 = fmul float %32, %24
  %63 = fadd float %61, %62
  %64 = fmul float %33, %25
  %65 = fadd float %63, %64
  %66 = fmul float 1.000000e+00, %26
  %67 = fadd float %65, %66
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %39, float %38, float %33, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %46, float %53, float %60, float %67)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020400
c0800100
bf8c0070
c2020114
bf8c007f
06100804
c0820700
bf8c007f
e00c2000
80010000
7e1202f2
bf8c0770
f800020f
09020508
c202010d
bf8c000f
10080204
c202010c
bf8c007f
d2820004
04100900
c202010e
bf8c007f
d2820004
04100902
c202010f
bf8c007f
06080804
c2020109
bf8c007f
100a0204
c2020108
bf8c007f
d2820005
04140900
c202010a
bf8c007f
d2820005
04140902
c202010b
bf8c007f
060a0a04
c2020105
bf8c007f
100c0204
c2020104
bf8c007f
d2820006
04180900
c2020106
bf8c007f
d2820006
04180902
c2020107
bf8c007f
060c0c04
c2020101
bf8c007f
100e0204
c2020100
bf8c007f
d2820007
041c0900
c2020102
bf8c007f
d2820000
041c0902
c2000103
bf8c007f
06000000
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..6]
DCL TEMP[0..1], LOCAL
  0: FSGE TEMP[0].x, CONST[6].xxxx, IN[0].xxxx
  1: UIF TEMP[0].xxxx :0
  2:   MOV TEMP[0].xy, IN[0].xyyy
  3:   TEX TEMP[0], TEMP[0], SAMP[0], 2D
  4:   MOV TEMP[0], TEMP[0]
  5: ELSE :0
  6:   MOV TEMP[1].xy, IN[0].xyyy
  7:   TEX TEMP[1], TEMP[1], SAMP[1], 2D
  8:   MOV TEMP[0], TEMP[1]
  9: ENDIF
 10: MOV OUT[0], TEMP[0]
 11: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
  %23 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %24 = load <32 x i8> addrspace(2)* %23, !tbaa !0
  %25 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %26 = load <16 x i8> addrspace(2)* %25, !tbaa !0
  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %33 = fcmp oge float %22, %31
  %34 = sext i1 %33 to i32
  %35 = bitcast i32 %34 to float
  %36 = bitcast float %35 to i32
  %37 = icmp ne i32 %36, 0
  %38 = bitcast float %31 to i32
  %39 = bitcast float %32 to i32
  %40 = insertelement <2 x i32> undef, i32 %38, i32 0
  %41 = insertelement <2 x i32> %40, i32 %39, i32 1
  br i1 %37, label %IF, label %ELSE

IF:                                               ; preds = %main_body
  %42 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %41, <32 x i8> %24, <16 x i8> %26, i32 2)
  %43 = extractelement <4 x float> %42, i32 0
  %44 = extractelement <4 x float> %42, i32 1
  %45 = extractelement <4 x float> %42, i32 2
  br label %ENDIF

ELSE:                                             ; preds = %main_body
  %46 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %41, <32 x i8> %28, <16 x i8> %30, i32 2)
  %47 = extractelement <4 x float> %46, i32 0
  %48 = extractelement <4 x float> %46, i32 1
  %49 = extractelement <4 x float> %46, i32 2
  br label %ENDIF

ENDIF:                                            ; preds = %ELSE, %IF
  %.sink = phi <4 x float> [ %42, %IF ], [ %46, %ELSE ]
  %temp.0 = phi float [ %43, %IF ], [ %47, %ELSE ]
  %temp1.0 = phi float [ %44, %IF ], [ %48, %ELSE ]
  %temp2.0 = phi float [ %45, %IF ], [ %49, %ELSE ]
  %50 = extractelement <4 x float> %.sink, i32 3
  %51 = call i32 @llvm.SI.packf16(float %temp.0, float %temp1.0)
  %52 = bitcast i32 %51 to float
  %53 = call i32 @llvm.SI.packf16(float %temp2.0, float %50)
  %54 = bitcast i32 %53 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %52, float %54, float %52, float %54)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840100
bf8c007f
c2000918
bf8c007f
d00c0000
02020400
d2000000
00018280
d1040000
02010100
be802400
8980007e
c0840304
c0c60508
bf8c007f
f0800f00
00430402
bf8c0770
be802500
89fe007e
c0840300
c0c60500
bf8c007f
f0800f00
00430402
bf8c0770
88fe007e
5e000b04
5e020f06
f8001c0f
01000100
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..6]
DCL TEMP[0..1], LOCAL
  0: DP4 TEMP[0].x, IN[0], CONST[0]
  1: DP4 TEMP[1].x, IN[0], CONST[1]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: DP4 TEMP[1].x, IN[0], CONST[2]
  4: MOV TEMP[0].z, TEMP[1].xxxx
  5: DP4 TEMP[1].x, IN[0], CONST[3]
  6: MOV TEMP[0].w, TEMP[1].xxxx
  7: MOV TEMP[1].xy, IN[1].xyxx
  8: MOV OUT[1], TEMP[1]
  9: MOV OUT[0], TEMP[0]
 10: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = extractelement <4 x float> %29, i32 2
  %33 = extractelement <4 x float> %29, i32 3
  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = fmul float %30, %11
  %40 = fmul float %31, %12
  %41 = fadd float %39, %40
  %42 = fmul float %32, %13
  %43 = fadd float %41, %42
  %44 = fmul float %33, %14
  %45 = fadd float %43, %44
  %46 = fmul float %30, %15
  %47 = fmul float %31, %16
  %48 = fadd float %46, %47
  %49 = fmul float %32, %17
  %50 = fadd float %48, %49
  %51 = fmul float %33, %18
  %52 = fadd float %50, %51
  %53 = fmul float %30, %19
  %54 = fmul float %31, %20
  %55 = fadd float %53, %54
  %56 = fmul float %32, %21
  %57 = fadd float %55, %56
  %58 = fmul float %33, %22
  %59 = fadd float %57, %58
  %60 = fmul float %30, %23
  %61 = fmul float %31, %24
  %62 = fadd float %60, %61
  %63 = fmul float %32, %25
  %64 = fadd float %62, %63
  %65 = fmul float %33, %26
  %66 = fadd float %64, %65
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %45, float %52, float %59, float %66)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
7e0a0280
bf8c0770
f800020f
05050201
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c202010d
bf8c007f
10080204
c202010c
bf8c007f
d2820004
04100900
c202010e
bf8c007f
d2820004
04100902
c202010f
bf8c007f
d2820004
04100903
c2020109
bf8c007f
100a0204
c2020108
bf8c007f
d2820005
04140900
c202010a
bf8c007f
d2820005
04140902
c202010b
bf8c007f
d2820005
04140903
c2020105
bf8c007f
100c0204
c2020104
bf8c007f
d2820006
04180900
c2020106
bf8c007f
d2820006
04180902
c2020107
bf8c007f
d2820006
04180903
c2020101
bf8c007f
100e0204
c2020100
bf8c007f
d2820007
041c0900
c2020102
bf8c007f
d2820007
041c0902
c2000103
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: MOV TEMP[0].w, IN[1].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], IN[0]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %31 = fdiv float %28, %30
  %32 = fdiv float %29, %30
  %33 = bitcast float %31 to i32
  %34 = bitcast float %32 to i32
  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %38, %24
  %43 = fmul float %39, %25
  %44 = fmul float %40, %26
  %45 = fmul float %41, %27
  %46 = call i32 @llvm.SI.packf16(float %42, float %43)
  %47 = bitcast i32 %46 to float
  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
  %49 = bitcast i32 %48 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %47, float %49, float %47, float %49)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080500
c8090501
c80c0700
c80d0701
7e085503
10060902
c8140400
c8150401
10040905
c0800300
c0c40500
bf8c007f
f0800f00
00020202
c8180300
c8190301
bf8c0770
100c0d05
c81c0200
c81d0201
100e0f04
5e0c0d07
c81c0100
c81d0101
100e0f03
c8200000
c8210001
10001102
5e000f00
f8001c0f
06000600
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], GENERIC[0]
DCL CONST[0..7]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
  9: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
  %53 = extractelement <4 x float> %52, i32 0
  %54 = extractelement <4 x float> %52, i32 1
  %55 = extractelement <4 x float> %52, i32 2
  %56 = extractelement <4 x float> %52, i32 3
  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
  %60 = extractelement <4 x float> %59, i32 0
  %61 = extractelement <4 x float> %59, i32 1
  %62 = extractelement <4 x float> %59, i32 2
  %63 = extractelement <4 x float> %59, i32 3
  %64 = fmul float %46, %11
  %65 = fmul float %46, %12
  %66 = fmul float %46, %13
  %67 = fmul float %46, %14
  %68 = fmul float %47, %15
  %69 = fadd float %68, %64
  %70 = fmul float %47, %16
  %71 = fadd float %70, %65
  %72 = fmul float %47, %17
  %73 = fadd float %72, %66
  %74 = fmul float %47, %18
  %75 = fadd float %74, %67
  %76 = fmul float %48, %19
  %77 = fadd float %76, %69
  %78 = fmul float %48, %20
  %79 = fadd float %78, %71
  %80 = fmul float %48, %21
  %81 = fadd float %80, %73
  %82 = fmul float %48, %22
  %83 = fadd float %82, %75
  %84 = fmul float %49, %23
  %85 = fadd float %84, %77
  %86 = fmul float %49, %24
  %87 = fadd float %86, %79
  %88 = fmul float %49, %25
  %89 = fadd float %88, %81
  %90 = fmul float %49, %26
  %91 = fadd float %90, %83
  %92 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00)
  %93 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
  %94 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
  %95 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
  %96 = fmul float %60, %27
  %97 = fmul float %60, %28
  %98 = fmul float %60, %29
  %99 = fmul float %60, %30
  %100 = fmul float %61, %31
  %101 = fadd float %100, %96
  %102 = fmul float %61, %32
  %103 = fadd float %102, %97
  %104 = fmul float %61, %33
  %105 = fadd float %104, %98
  %106 = fmul float %61, %34
  %107 = fadd float %106, %99
  %108 = fmul float %62, %35
  %109 = fadd float %108, %101
  %110 = fmul float %62, %36
  %111 = fadd float %110, %103
  %112 = fmul float %62, %37
  %113 = fadd float %112, %105
  %114 = fmul float %62, %38
  %115 = fadd float %114, %107
  %116 = fmul float %63, %39
  %117 = fadd float %116, %109
  %118 = fmul float %63, %40
  %119 = fadd float %118, %111
  %120 = fmul float %63, %41
  %121 = fadd float %120, %113
  %122 = fmul float %63, %42
  %123 = fadd float %122, %115
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %92, float %93, float %94, float %95)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %117, float %119, float %121, float %123)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %85, float %87, float %89, float %91)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0840708
bf8c000f
e00c2000
80020100
c0800100
bf8c0070
c2020113
bf8c007f
100a0204
c2020117
bf8c007f
d2820005
04140902
c202011b
bf8c007f
d2820005
04140903
c202011f
bf8c007f
d2820005
04140904
c2020112
bf8c007f
100c0204
c2020116
bf8c007f
d2820006
04180902
c202011a
bf8c007f
d2820006
04180903
c202011e
bf8c007f
d2820006
04180904
c2020111
bf8c007f
100e0204
c2020115
bf8c007f
d2820007
041c0902
c2020119
bf8c007f
d2820007
041c0903
c202011d
bf8c007f
d2820007
041c0904
c2020110
bf8c007f
10100204
c2020114
bf8c007f
d2820008
04200902
c2020118
bf8c007f
d2820008
04200903
c202011c
bf8c007f
d2820001
04200904
f800021f
05060701
c0820700
bf8c000f
e00c2000
80010000
c2020103
bf8c0070
10080004
c2020107
bf8c007f
d2820004
04100901
c202010b
bf8c007f
d2820004
04100902
c202010f
bf8c007f
d2820004
04100903
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04140901
c202010a
bf8c007f
d2820005
04140902
c202010e
bf8c007f
d2820005
04140903
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
04180901
c2020109
bf8c007f
d2820006
04180902
c202010d
bf8c007f
d2820006
04180903
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041c0901
c2020108
bf8c007f
d2820007
041c0902
c200010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[1..4]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: MOV TEMP[0].w, IN[0].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], CONST[4]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %32 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %33 = fdiv float %30, %32
  %34 = fdiv float %31, %32
  %35 = bitcast float %33 to i32
  %36 = bitcast float %34 to i32
  %37 = insertelement <2 x i32> undef, i32 %35, i32 0
  %38 = insertelement <2 x i32> %37, i32 %36, i32 1
  %39 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %38, <32 x i8> %27, <16 x i8> %29, i32 2)
  %40 = extractelement <4 x float> %39, i32 0
  %41 = extractelement <4 x float> %39, i32 1
  %42 = extractelement <4 x float> %39, i32 2
  %43 = extractelement <4 x float> %39, i32 3
  %44 = fmul float %40, %22
  %45 = fmul float %41, %23
  %46 = fmul float %42, %24
  %47 = fmul float %43, %25
  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
  %49 = bitcast i32 %48 to float
  %50 = call i32 @llvm.SI.packf16(float %46, float %47)
  %51 = bitcast i32 %50 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %49, float %51, float %49, float %51)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080100
c8090101
c80c0300
c80d0301
7e085503
10060902
c8140000
c8150001
10040905
c0840300
c0c60500
bf8c007f
f0800f00
00430002
c0800100
bf8c0070
c2020113
bf8c007f
10080604
c2020112
bf8c007f
100a0404
5e080905
c2020111
bf8c007f
100a0204
c2000110
bf8c007f
10000000
5e000b00
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
DCL CONST[0..7]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MUL TEMP[0], IN[1].xxxx, CONST[4]
  5: MAD TEMP[0], IN[1].yyyy, CONST[5], TEMP[0]
  6: MAD TEMP[0], IN[1].zzzz, CONST[6], TEMP[0]
  7: MAD OUT[1], IN[1].wwww, CONST[7], TEMP[0]
  8: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
  %53 = extractelement <4 x float> %52, i32 0
  %54 = extractelement <4 x float> %52, i32 1
  %55 = extractelement <4 x float> %52, i32 2
  %56 = extractelement <4 x float> %52, i32 3
  %57 = fmul float %46, %11
  %58 = fmul float %46, %12
  %59 = fmul float %46, %13
  %60 = fmul float %46, %14
  %61 = fmul float %47, %15
  %62 = fadd float %61, %57
  %63 = fmul float %47, %16
  %64 = fadd float %63, %58
  %65 = fmul float %47, %17
  %66 = fadd float %65, %59
  %67 = fmul float %47, %18
  %68 = fadd float %67, %60
  %69 = fmul float %48, %19
  %70 = fadd float %69, %62
  %71 = fmul float %48, %20
  %72 = fadd float %71, %64
  %73 = fmul float %48, %21
  %74 = fadd float %73, %66
  %75 = fmul float %48, %22
  %76 = fadd float %75, %68
  %77 = fmul float %49, %23
  %78 = fadd float %77, %70
  %79 = fmul float %49, %24
  %80 = fadd float %79, %72
  %81 = fmul float %49, %25
  %82 = fadd float %81, %74
  %83 = fmul float %49, %26
  %84 = fadd float %83, %76
  %85 = fmul float %53, %27
  %86 = fmul float %53, %28
  %87 = fmul float %53, %29
  %88 = fmul float %53, %30
  %89 = fmul float %54, %31
  %90 = fadd float %89, %85
  %91 = fmul float %54, %32
  %92 = fadd float %91, %86
  %93 = fmul float %54, %33
  %94 = fadd float %93, %87
  %95 = fmul float %54, %34
  %96 = fadd float %95, %88
  %97 = fmul float %55, %35
  %98 = fadd float %97, %90
  %99 = fmul float %55, %36
  %100 = fadd float %99, %92
  %101 = fmul float %55, %37
  %102 = fadd float %101, %94
  %103 = fmul float %55, %38
  %104 = fadd float %103, %96
  %105 = fmul float %56, %39
  %106 = fadd float %105, %98
  %107 = fmul float %56, %40
  %108 = fadd float %107, %100
  %109 = fmul float %56, %41
  %110 = fadd float %109, %102
  %111 = fmul float %56, %42
  %112 = fadd float %111, %104
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %106, float %108, float %110, float %112)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %78, float %80, float %82, float %84)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020113
bf8c007f
100a0204
c2020117
bf8c007f
d2820005
04140902
c202011b
bf8c007f
d2820005
04140903
c202011f
bf8c007f
d2820005
04140904
c2020112
bf8c007f
100c0204
c2020116
bf8c007f
d2820006
04180902
c202011a
bf8c007f
d2820006
04180903
c202011e
bf8c007f
d2820006
04180904
c2020111
bf8c007f
100e0204
c2020115
bf8c007f
d2820007
041c0902
c2020119
bf8c007f
d2820007
041c0903
c202011d
bf8c007f
d2820007
041c0904
c2020110
bf8c007f
10100204
c2020114
bf8c007f
d2820008
04200902
c2020118
bf8c007f
d2820008
04200903
c202011c
bf8c007f
d2820001
04200904
f800020f
05060701
c0820700
bf8c000f
e00c2000
80010000
c2020103
bf8c0070
10080004
c2020107
bf8c007f
d2820004
04100901
c202010b
bf8c007f
d2820004
04100902
c202010f
bf8c007f
d2820004
04100903
c2020102
bf8c007f
100a0004
c2020106
bf8c007f
d2820005
04140901
c202010a
bf8c007f
d2820005
04140902
c202010e
bf8c007f
d2820005
04140903
c2020101
bf8c007f
100c0004
c2020105
bf8c007f
d2820006
04180901
c2020109
bf8c007f
d2820006
04180902
c202010d
bf8c007f
d2820006
04180903
c2020100
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041c0901
c2020108
bf8c007f
d2820007
041c0902
c200010c
bf8c007f
d2820000
041c0103
f80008cf
04050600
bf810000






































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..22]
DCL TEMP[0..4], LOCAL
IMM[0] FLT32 {   22.0000,     0.0000,    -0.5000,     0.0156}
IMM[1] FLT32 {    0.0001,     0.5000,     1.0000,     0.8000}
IMM[2] FLT32 {    0.2000,   -17.0000,     0.6667,     1.2000}
  0: ADD TEMP[0].x, IMM[0].xxxx, -IN[0].wwww
  1: FSLT TEMP[0].x, TEMP[0].xxxx, IMM[0].yyyy
  2: UIF TEMP[0].xxxx :0
  3:   KILL
  4: ENDIF
  5: MUL TEMP[0].xy, IN[0].xyyy, CONST[16].zwww
  6: MOV TEMP[0].xy, TEMP[0].xyyy
  7: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
  8: ADD TEMP[0].xyz, TEMP[0].xzyy, IMM[0].zzzz
  9: MUL TEMP[1].x, CONST[16].xxxx, IMM[0].wwww
 10: MUL TEMP[2].x, CONST[16].yyyy, IMM[0].wwww
 11: MOV TEMP[1].y, TEMP[2].xxxx
 12: DP3 TEMP[2].x, TEMP[0].xyzz, TEMP[0].xyzz
 13: RSQ TEMP[2].x, TEMP[2].xxxx
 14: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
 15: MUL TEMP[2].x, IN[0].wwww, IN[0].wwww
 16: MUL TEMP[2].x, TEMP[2].xxxx, IN[0].wwww
 17: MUL_SAT TEMP[2].x, IMM[1].xxxx, TEMP[2].xxxx
 18: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
 19: DP3 TEMP[0].x, TEMP[0].xyzz, -CONST[17].xyzz
 20: MAD TEMP[0].x, TEMP[0].xxxx, IMM[1].yyyy, IMM[1].yyyy
 21: MOV TEMP[2].w, IMM[1].zzzz
 22: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx
 23: MAD TEMP[0].x, IMM[1].wwww, TEMP[0].xxxx, IMM[2].xxxx
 24: MUL TEMP[1].xy, IN[0].xyyy, TEMP[1].xyyy
 25: MOV TEMP[1].xy, TEMP[1].xyyy
 26: TEX TEMP[1].xyz, TEMP[1], SAMP[2], 2D
 27: MUL TEMP[3].xy, IN[0].xyyy, CONST[16].zwww
 28: MOV TEMP[3].xy, TEMP[3].xyyy
 29: TEX TEMP[3].xyz, TEMP[3], SAMP[1], 2D
 30: ADD TEMP[4].x, IN[0].wwww, IMM[2].yyyy
 31: MUL TEMP[4].x, TEMP[4].xxxx, IMM[2].zzzz
 32: ADD_SAT TEMP[4].x, IMM[1].zzzz, -TEMP[4].xxxx
 33: LRP TEMP[1].xyz, TEMP[4].xxxx, TEMP[3].xyzz, TEMP[1].xyzz
 34: MUL TEMP[0].xyz, TEMP[0].xxxx, TEMP[1].xyzz
 35: MUL_SAT TEMP[0].xyz, TEMP[0].xyzz, IMM[2].wwww
 36: MOV TEMP[2].xyz, TEMP[0].xyzx
 37: MOV OUT[0], TEMP[2]
 38: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 264)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 268)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 276)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 280)
  %29 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %30 = load <32 x i8> addrspace(2)* %29, !tbaa !0
  %31 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0
  %35 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %43 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %44 = fsub float -0.000000e+00, %43
  %45 = fadd float 2.200000e+01, %44
  %46 = fcmp olt float %45, 0.000000e+00
  %47 = sext i1 %46 to i32
  %48 = bitcast i32 %47 to float
  %49 = bitcast float %48 to i32
  %50 = icmp ne i32 %49, 0
  br i1 %50, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  call void @llvm.AMDGPU.kilp()
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %51 = fmul float %41, %24
  %52 = fmul float %42, %25
  %53 = bitcast float %51 to i32
  %54 = bitcast float %52 to i32
  %55 = insertelement <2 x i32> undef, i32 %53, i32 0
  %56 = insertelement <2 x i32> %55, i32 %54, i32 1
  %57 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %56, <32 x i8> %30, <16 x i8> %32, i32 2)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = extractelement <4 x float> %57, i32 2
  %61 = fadd float %58, -5.000000e-01
  %62 = fadd float %60, -5.000000e-01
  %63 = fadd float %59, -5.000000e-01
  %64 = fmul float %22, 1.562500e-02
  %65 = fmul float %23, 1.562500e-02
  %66 = fmul float %61, %61
  %67 = fmul float %62, %62
  %68 = fadd float %67, %66
  %69 = fmul float %63, %63
  %70 = fadd float %68, %69
  %71 = call float @llvm.AMDGPU.rsq(float %70)
  %72 = fmul float %61, %71
  %73 = fmul float %62, %71
  %74 = fmul float %63, %71
  %75 = fmul float %43, %43
  %76 = fmul float %75, %43
  %77 = fmul float 0x3F231C07C0000000, %76
  %78 = call float @llvm.AMDIL.clamp.(float %77, float 0.000000e+00, float 1.000000e+00)
  %79 = fmul float %72, %78
  %80 = fmul float %73, %78
  %81 = fmul float %74, %78
  %82 = fsub float -0.000000e+00, %26
  %83 = fsub float -0.000000e+00, %27
  %84 = fsub float -0.000000e+00, %28
  %85 = fmul float %79, %82
  %86 = fmul float %80, %83
  %87 = fadd float %86, %85
  %88 = fmul float %81, %84
  %89 = fadd float %87, %88
  %90 = fmul float %89, 5.000000e-01
  %91 = fadd float %90, 5.000000e-01
  %92 = fmul float %91, %91
  %93 = fmul float 0x3FE99999A0000000, %92
  %94 = fadd float %93, 0x3FC99999A0000000
  %95 = fmul float %41, %64
  %96 = fmul float %42, %65
  %97 = bitcast float %95 to i32
  %98 = bitcast float %96 to i32
  %99 = insertelement <2 x i32> undef, i32 %97, i32 0
  %100 = insertelement <2 x i32> %99, i32 %98, i32 1
  %101 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %100, <32 x i8> %38, <16 x i8> %40, i32 2)
  %102 = extractelement <4 x float> %101, i32 0
  %103 = extractelement <4 x float> %101, i32 1
  %104 = extractelement <4 x float> %101, i32 2
  %105 = fmul float %41, %24
  %106 = fmul float %42, %25
  %107 = bitcast float %105 to i32
  %108 = bitcast float %106 to i32
  %109 = insertelement <2 x i32> undef, i32 %107, i32 0
  %110 = insertelement <2 x i32> %109, i32 %108, i32 1
  %111 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %110, <32 x i8> %34, <16 x i8> %36, i32 2)
  %112 = extractelement <4 x float> %111, i32 0
  %113 = extractelement <4 x float> %111, i32 1
  %114 = extractelement <4 x float> %111, i32 2
  %115 = fadd float %43, -1.700000e+01
  %116 = fmul float %115, 0x3FE5555560000000
  %117 = fsub float -0.000000e+00, %116
  %118 = fadd float 1.000000e+00, %117
  %119 = call float @llvm.AMDIL.clamp.(float %118, float 0.000000e+00, float 1.000000e+00)
  %120 = call float @llvm.AMDGPU.lrp(float %119, float %112, float %102)
  %121 = call float @llvm.AMDGPU.lrp(float %119, float %113, float %103)
  %122 = call float @llvm.AMDGPU.lrp(float %119, float %114, float %104)
  %123 = fmul float %94, %120
  %124 = fmul float %94, %121
  %125 = fmul float %94, %122
  %126 = fmul float %123, 0x3FF3333340000000
  %127 = fmul float %124, 0x3FF3333340000000
  %128 = fmul float %125, 0x3FF3333340000000
  %129 = call float @llvm.AMDIL.clamp.(float %126, float 0.000000e+00, float 1.000000e+00)
  %130 = call float @llvm.AMDIL.clamp.(float %127, float 0.000000e+00, float 1.000000e+00)
  %131 = call float @llvm.AMDIL.clamp.(float %128, float 0.000000e+00, float 1.000000e+00)
  %132 = call i32 @llvm.SI.packf16(float %129, float %130)
  %133 = bitcast i32 %132 to float
  %134 = call i32 @llvm.SI.packf16(float %131, float 1.000000e+00)
  %135 = bitcast i32 %134 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %133, float %135, float %133, float %135)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

declare void @llvm.AMDGPU.kilp()

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080100
c8090101
c8100000
c8110001
c80c0300
c80d0301
080006ff
41b00000
d0020006
02010100
c08a0308
c0cc0510
c0840304
c0c60508
c0900300
c0d20500
c0800100
bf8c007f
c2020146
c2028145
c2160144
c2168143
c2170142
c2178141
c2000140
bf8c007f
7e0e0204
7e100205
7e12022c
7e00022d
7e14022e
7e0c022f
7e0a0200
be802406
8980007e
7e0202f3
7c260280
88fe007e
10020102
10001504
f0800700
01090b00
bf8c0770
06141af1
061c16f1
101e1d0e
d282000f
043e150a
061618f1
d282000c
043e170b
7e185b0c
101c190e
101a0703
101a070d
101a1aff
3918e03e
d206080d
0201010d
101c1b0e
1012130e
1014190a
10141b0a
d2060008
22010108
1010110a
08101308
1012190b
10121b09
100e0f09
080e0f08
d2820007
03c1e107
100e0f07
7e1002ff
3e4ccccd
7e1202ff
3f4ccccd
d2820007
04221307
100c0cff
3c800000
10120d02
10040aff
3c800000
10100504
f0800700
00a60408
060406ff
c1880000
7e0602ff
bf2aaaab
d2820002
03ca0702
d2060802
02010102
080604f2
bf8c0770
10160b03
f0800700
00430800
bf8c0770
d2820000
042e1302
10000107
100000ff
3f99999a
d2060800
02010100
10020903
d2820001
04061102
10020307
100202ff
3f99999a
d2060801
02010101
5e000101
10020d03
d2820001
04061502
10020307
100202ff
3f99999a
d2060801
02010101
d25e0001
0201e501
f8001c0f
01000100
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..24]
DCL TEMP[0..5], LOCAL
IMM[0] FLT32 {   -1.0000,     1.0000,     0.5000,     0.0100}
IMM[1] INT32 {0, 1, 2, 3}
  0: MAD TEMP[0].xy, IN[0].xyyy, CONST[23].zzzz, CONST[23].xyyy
  1: ADD TEMP[1].x, IN[0].zzzz, IMM[0].xxxx
  2: F2I TEMP[1].x, TEMP[1].xxxx
  3: USEQ TEMP[1].yzw, TEMP[1].xxxx, IMM[1]
  4: I2F TEMP[2].y, TEMP[1].yyyy
  5: CMP TEMP[2].x, TEMP[2].yyyy, CONST[24].yyyy, CONST[24].xxxx
  6: I2F TEMP[3].z, TEMP[1].zzzz
  7: CMP TEMP[2].x, TEMP[3].zzzz, CONST[24].zzzz, TEMP[2].xxxx
  8: I2F TEMP[1].w, TEMP[1].wwww
  9: CMP TEMP[2].x, TEMP[1].wwww, CONST[24].wwww, TEMP[2].xxxx
 10: MOV_SAT TEMP[1].x, IN[0].zzzz
 11: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
 12: ADD TEMP[2].x, IMM[0].yyyy, -IN[0].wwww
 13: MOV TEMP[2].y, IN[0].wwww
 14: MUL TEMP[2].xy, TEMP[1].xxxx, TEMP[2].xyyy
 15: MAD TEMP[0].xy, TEMP[2].xyyy, CONST[23].zzzz, TEMP[0].xyyy
 16: ADD TEMP[2].x, TEMP[0].xxxx, IMM[0].zzzz
 17: RCP TEMP[3].x, CONST[16].xxxx
 18: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
 19: ADD TEMP[3].x, TEMP[0].yyyy, IMM[0].zzzz
 20: ADD TEMP[3].x, TEMP[3].xxxx, -CONST[16].yyyy
 21: RCP TEMP[4].x, -CONST[16].yyyy
 22: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 23: MOV TEMP[2].y, TEMP[3].xxxx
 24: MOV TEMP[3].x, TEMP[0].xxxx
 25: ADD TEMP[4].x, IMM[0].yyyy, -TEMP[1].xxxx
 26: MUL TEMP[4].x, IN[1].xxxx, TEMP[4].xxxx
 27: MAD TEMP[1].x, IN[1].yyyy, TEMP[1].xxxx, TEMP[4].xxxx
 28: MUL TEMP[1].x, TEMP[1].xxxx, IMM[0].wwww
 29: MOV TEMP[3].y, TEMP[1].xxxx
 30: MOV TEMP[4].w, IMM[0].yyyy
 31: MOV TEMP[4].x, TEMP[0].xxxx
 32: MOV TEMP[4].y, TEMP[1].xxxx
 33: MOV TEMP[4].z, TEMP[0].yyyy
 34: DP4 TEMP[1].x, TEMP[4], CONST[0]
 35: DP4 TEMP[5].x, TEMP[4], CONST[1]
 36: MOV TEMP[1].y, TEMP[5].xxxx
 37: DP4 TEMP[5].x, TEMP[4], CONST[2]
 38: MOV TEMP[1].z, TEMP[5].xxxx
 39: DP4 TEMP[4].x, TEMP[4], CONST[3]
 40: MOV TEMP[1].w, TEMP[4].xxxx
 41: MOV TEMP[2].xy, TEMP[2].xyxx
 42: MOV TEMP[2].zw, TEMP[3].yyxy
 43: MOV TEMP[0].x, TEMP[0].yyyy
 44: MOV OUT[0], TEMP[1]
 45: MOV OUT[2], TEMP[0]
 46: MOV OUT[1], TEMP[2]
 47: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
  %36 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
  %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %37, i32 0, i32 %5)
  %39 = extractelement <4 x float> %38, i32 0
  %40 = extractelement <4 x float> %38, i32 1
  %41 = extractelement <4 x float> %38, i32 2
  %42 = extractelement <4 x float> %38, i32 3
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = fmul float %39, %31
  %49 = fadd float %48, %29
  %50 = fmul float %40, %31
  %51 = fadd float %50, %30
  %52 = fadd float %41, -1.000000e+00
  %53 = fptosi float %52 to i32
  %54 = bitcast i32 %53 to float
  %55 = bitcast float %54 to i32
  %56 = icmp eq i32 %55, 1
  %57 = sext i1 %56 to i32
  %58 = bitcast float %54 to i32
  %59 = icmp eq i32 %58, 2
  %60 = sext i1 %59 to i32
  %61 = bitcast float %54 to i32
  %62 = icmp eq i32 %61, 3
  %63 = sext i1 %62 to i32
  %64 = bitcast i32 %57 to float
  %65 = bitcast i32 %60 to float
  %66 = bitcast i32 %63 to float
  %67 = bitcast float %64 to i32
  %68 = sitofp i32 %67 to float
  %69 = call float @llvm.AMDGPU.cndlt(float %68, float %33, float %32)
  %70 = bitcast float %65 to i32
  %71 = sitofp i32 %70 to float
  %72 = call float @llvm.AMDGPU.cndlt(float %71, float %34, float %69)
  %73 = bitcast float %66 to i32
  %74 = sitofp i32 %73 to float
  %75 = call float @llvm.AMDGPU.cndlt(float %74, float %35, float %72)
  %76 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
  %77 = fmul float %76, %75
  %78 = fsub float -0.000000e+00, %42
  %79 = fadd float 1.000000e+00, %78
  %80 = fmul float %77, %79
  %81 = fmul float %77, %42
  %82 = fmul float %80, %31
  %83 = fadd float %82, %49
  %84 = fmul float %81, %31
  %85 = fadd float %84, %51
  %86 = fadd float %83, 5.000000e-01
  %87 = fdiv float 1.000000e+00, %27
  %88 = fmul float %86, %87
  %89 = fadd float %85, 5.000000e-01
  %90 = fsub float -0.000000e+00, %28
  %91 = fadd float %89, %90
  %92 = fsub float -0.000000e+00, %28
  %93 = fdiv float 1.000000e+00, %92
  %94 = fmul float %91, %93
  %95 = fsub float -0.000000e+00, %77
  %96 = fadd float 1.000000e+00, %95
  %97 = fmul float %46, %96
  %98 = fmul float %47, %77
  %99 = fadd float %98, %97
  %100 = fmul float %99, 0x3F847AE140000000
  %101 = fmul float %83, %11
  %102 = fmul float %100, %12
  %103 = fadd float %101, %102
  %104 = fmul float %85, %13
  %105 = fadd float %103, %104
  %106 = fmul float 1.000000e+00, %14
  %107 = fadd float %105, %106
  %108 = fmul float %83, %15
  %109 = fmul float %100, %16
  %110 = fadd float %108, %109
  %111 = fmul float %85, %17
  %112 = fadd float %110, %111
  %113 = fmul float 1.000000e+00, %18
  %114 = fadd float %112, %113
  %115 = fmul float %83, %19
  %116 = fmul float %100, %20
  %117 = fadd float %115, %116
  %118 = fmul float %85, %21
  %119 = fadd float %117, %118
  %120 = fmul float 1.000000e+00, %22
  %121 = fadd float %119, %120
  %122 = fmul float %83, %23
  %123 = fmul float %100, %24
  %124 = fadd float %122, %123
  %125 = fmul float %85, %25
  %126 = fadd float %124, %125
  %127 = fmul float 1.000000e+00, %26
  %128 = fadd float %126, %127
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %88, float %94, float %83, float %100)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %85, float %85, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %107, float %114, float %121, float %128)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.cndlt(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840700
bf8c007f
e00c2000
80020100
bf8c0770
060a06f3
7e0a1105
d1040002
02010305
d2000006
00098280
7e0c0b06
d0080004
02020c80
c0800100
bf8c007f
c2040161
bf8c007f
7e0c0208
c2040160
bf8c007f
7e0e0208
d2000006
00120d07
d1040004
02010505
d2000007
00118280
7e0e0b07
d0080004
02020e80
c2040162
bf8c007f
7e0e0208
d2000006
00120f06
d1040004
02010705
d2000005
00118280
7e0a0b05
d0080004
02020a80
c2040163
bf8c007f
7e0a0208
d2000005
00120b06
d2060806
02010103
100c0b06
080a0cf2
c0820704
bf8c007f
e00c2000
80010700
bf8c0770
10000b07
d2820000
04020d08
100000ff
3c23d70a
080a08f2
100a0b06
c202015e
c202815c
bf8c007f
7e0e0205
d2820007
041c0901
d2820005
041c0905
060e0af0
c2028140
bf8c007f
7e105405
100e1107
100c0906
c202815d
bf8c007f
7e100205
d2820001
04200902
d2820001
04040906
060402f0
c2020141
bf8c007f
0a040404
d2060003
22010004
7e065503
10040702
f800020f
00050207
bf8c070f
7e040280
f800021f
02020101
c202010d
bf8c000f
10040004
c202010c
bf8c007f
d2820002
04080905
c202010e
bf8c007f
d2820002
04080901
c202010f
bf8c007f
06040404
c2020109
bf8c007f
10060004
c2020108
bf8c007f
d2820003
040c0905
c202010a
bf8c007f
d2820003
040c0901
c202010b
bf8c007f
06060604
c2020105
bf8c007f
10080004
c2020104
bf8c007f
d2820004
04100905
c2020106
bf8c007f
d2820004
04100901
c2020107
bf8c007f
06080804
c2020101
bf8c007f
10000004
c2020100
bf8c007f
d2820000
04000905
c2020102
bf8c007f
d2820000
04000901
c2000103
bf8c007f
06000000
f80008cf
02030400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL SAMP[4]
DCL SAMP[5]
DCL CONST[0..22]
DCL TEMP[0..7], LOCAL
IMM[0] FLT32 {    0.5000,     2.0000,     1.0000,    -0.5000}
IMM[1] FLT32 {    0.8000,     0.2000,     0.2500,     1.2000}
IMM[2] FLT32 {-160000.0000,     0.0000,     0.0200,     0.0039}
IMM[3] FLT32 {    0.1000,     6.2832,     0.0000,     0.0000}
  0: MOV TEMP[0].x, IN[1].wwww
  1: MOV TEMP[0].yz, IN[2].yxyy
  2: MOV TEMP[1].xy, IN[0].xyyy
  3: TEX TEMP[1].xyz, TEMP[1], SAMP[2], 2D
  4: MOV TEMP[2].xy, IN[0].zwww
  5: TEX TEMP[2].xyz, TEMP[2], SAMP[3], 2D
  6: FSLT TEMP[3].x, TEMP[2].xxxx, IMM[0].xxxx
  7: UIF TEMP[3].xxxx :0
  8:   MUL TEMP[3].x, IMM[0].yyyy, TEMP[2].xxxx
  9:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[1].xxxx
 10: ELSE :0
 11:   ADD TEMP[4].x, IMM[0].zzzz, -TEMP[2].xxxx
 12:   MUL TEMP[4].x, IMM[0].yyyy, TEMP[4].xxxx
 13:   ADD TEMP[5].x, IMM[0].zzzz, -TEMP[1].xxxx
 14:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 15:   ADD TEMP[3].x, IMM[0].zzzz, -TEMP[4].xxxx
 16: ENDIF
 17: MOV TEMP[3].x, TEMP[3].xxxx
 18: FSLT TEMP[4].x, TEMP[2].yyyy, IMM[0].xxxx
 19: UIF TEMP[4].xxxx :0
 20:   MUL TEMP[4].x, IMM[0].yyyy, TEMP[2].yyyy
 21:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[1].yyyy
 22: ELSE :0
 23:   ADD TEMP[5].x, IMM[0].zzzz, -TEMP[2].yyyy
 24:   MUL TEMP[5].x, IMM[0].yyyy, TEMP[5].xxxx
 25:   ADD TEMP[6].x, IMM[0].zzzz, -TEMP[1].yyyy
 26:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 27:   ADD TEMP[4].x, IMM[0].zzzz, -TEMP[5].xxxx
 28: ENDIF
 29: MOV TEMP[3].y, TEMP[4].xxxx
 30: FSLT TEMP[4].x, TEMP[2].zzzz, IMM[0].xxxx
 31: UIF TEMP[4].xxxx :0
 32:   MUL TEMP[4].x, IMM[0].yyyy, TEMP[2].zzzz
 33:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[1].zzzz
 34: ELSE :0
 35:   ADD TEMP[2].x, IMM[0].zzzz, -TEMP[2].zzzz
 36:   MUL TEMP[2].x, IMM[0].yyyy, TEMP[2].xxxx
 37:   ADD TEMP[5].x, IMM[0].zzzz, -TEMP[1].zzzz
 38:   MUL TEMP[2].x, TEMP[2].xxxx, TEMP[5].xxxx
 39:   ADD TEMP[4].x, IMM[0].zzzz, -TEMP[2].xxxx
 40: ENDIF
 41: MOV TEMP[3].z, TEMP[4].xxxx
 42: LRP TEMP[1].xyz, IMM[0].xxxx, TEMP[3].xyzz, TEMP[1].xyzz
 43: MOV TEMP[2].xy, IN[0].xyyy
 44: TEX TEMP[2].xyz, TEMP[2], SAMP[1], 2D
 45: ADD TEMP[2].xyz, TEMP[2].xyzz, IMM[0].wwww
 46: ADD TEMP[3].x, IN[1].wwww, IMM[0].xxxx
 47: RCP TEMP[4].x, CONST[16].xxxx
 48: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 49: ADD TEMP[4].x, IN[2].yyyy, IMM[0].xxxx
 50: ADD TEMP[4].x, TEMP[4].xxxx, -CONST[16].yyyy
 51: RCP TEMP[5].x, -CONST[16].yyyy
 52: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 53: MOV TEMP[3].y, TEMP[4].xxxx
 54: MOV TEMP[3].xy, TEMP[3].xyyy
 55: TEX TEMP[3].xyz, TEMP[3], SAMP[0], 2D
 56: FSLT TEMP[4].x, TEMP[3].xxxx, IMM[0].xxxx
 57: UIF TEMP[4].xxxx :0
 58:   MUL TEMP[4].x, IMM[0].yyyy, TEMP[3].xxxx
 59:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[1].xxxx
 60: ELSE :0
 61:   ADD TEMP[5].x, IMM[0].zzzz, -TEMP[3].xxxx
 62:   MUL TEMP[5].x, IMM[0].yyyy, TEMP[5].xxxx
 63:   ADD TEMP[6].x, IMM[0].zzzz, -TEMP[1].xxxx
 64:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 65:   ADD TEMP[4].x, IMM[0].zzzz, -TEMP[5].xxxx
 66: ENDIF
 67: MOV TEMP[4].x, TEMP[4].xxxx
 68: FSLT TEMP[5].x, TEMP[3].yyyy, IMM[0].xxxx
 69: UIF TEMP[5].xxxx :0
 70:   MUL TEMP[5].x, IMM[0].yyyy, TEMP[3].yyyy
 71:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[1].yyyy
 72: ELSE :0
 73:   ADD TEMP[6].x, IMM[0].zzzz, -TEMP[3].yyyy
 74:   MUL TEMP[6].x, IMM[0].yyyy, TEMP[6].xxxx
 75:   ADD TEMP[7].x, IMM[0].zzzz, -TEMP[1].yyyy
 76:   MUL TEMP[6].x, TEMP[6].xxxx, TEMP[7].xxxx
 77:   ADD TEMP[5].x, IMM[0].zzzz, -TEMP[6].xxxx
 78: ENDIF
 79: MOV TEMP[4].y, TEMP[5].xxxx
 80: FSLT TEMP[5].x, TEMP[3].zzzz, IMM[0].xxxx
 81: UIF TEMP[5].xxxx :0
 82:   MUL TEMP[5].x, IMM[0].yyyy, TEMP[3].zzzz
 83:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[1].zzzz
 84: ELSE :0
 85:   ADD TEMP[3].x, IMM[0].zzzz, -TEMP[3].zzzz
 86:   MUL TEMP[3].x, IMM[0].yyyy, TEMP[3].xxxx
 87:   ADD TEMP[6].x, IMM[0].zzzz, -TEMP[1].zzzz
 88:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
 89:   ADD TEMP[5].x, IMM[0].zzzz, -TEMP[3].xxxx
 90: ENDIF
 91: MOV TEMP[4].z, TEMP[5].xxxx
 92: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
 93: RSQ TEMP[3].x, TEMP[3].xxxx
 94: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx
 95: DP3 TEMP[3].x, IN[1].xyzz, IN[1].xyzz
 96: RSQ TEMP[3].x, TEMP[3].xxxx
 97: MUL TEMP[3].xyz, IN[1].xyzz, TEMP[3].xxxx
 98: DP3 TEMP[2].x, TEMP[2].xyzz, -TEMP[3].xyzz
 99: MAD TEMP[2].x, TEMP[2].xxxx, IMM[0].xxxx, IMM[0].xxxx
100: ADD TEMP[3].xyz, CONST[18].xyzz, -TEMP[0].xyzz
101: ADD TEMP[5].x, IN[1].wwww, IMM[0].xxxx
102: RCP TEMP[6].x, CONST[16].xxxx
103: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
104: ADD TEMP[6].x, IN[2].yyyy, IMM[0].xxxx
105: RCP TEMP[7].x, CONST[16].yyyy
106: MUL TEMP[6].x, TEMP[6].xxxx, TEMP[7].xxxx
107: MOV TEMP[5].y, TEMP[6].xxxx
108: MOV TEMP[6].w, IMM[0].zzzz
109: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
110: MAD TEMP[2].x, IMM[1].xxxx, TEMP[2].xxxx, IMM[1].yyyy
111: LRP TEMP[1].xyz, IMM[1].zzzz, TEMP[4].xyzz, TEMP[1].xyzz
112: MUL TEMP[1].xyz, TEMP[2].xxxx, TEMP[1].xyzz
113: MUL_SAT TEMP[1].xyz, TEMP[1].xyzz, IMM[1].wwww
114: DP3 TEMP[2].x, TEMP[3].xyzz, TEMP[3].xyzz
115: ADD TEMP[2].x, TEMP[2].xxxx, IMM[2].xxxx
116: MUL TEMP[2].x, TEMP[2].xxxx, IMM[2].yyyy
117: MIN TEMP[2].x, TEMP[2].xxxx, IMM[0].xxxx
118: MOV_SAT TEMP[2].x, TEMP[2].xxxx
119: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[3].xyzz
120: RSQ TEMP[4].x, TEMP[4].xxxx
121: MUL TEMP[3].y, TEMP[3].xyzz, TEMP[4].xxxx
122: ADD TEMP[3].x, IMM[0].zzzz, -TEMP[3].yyyy
123: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
124: LRP TEMP[1].xyz, TEMP[2].xxxx, IMM[0].xxxx, TEMP[1].xyzz
125: MOV TEMP[2].xy, TEMP[5].xyyy
126: TEX TEMP[2].w, TEMP[2], SAMP[5], 2D
127: ADD TEMP[0].xy, TEMP[0].xzzz, IMM[0].xxxx
128: MUL TEMP[0].xy, TEMP[0].xyyy, IMM[2].wwww
129: MAD TEMP[0].xy, CONST[22].yyyy, IMM[2].zzzz, TEMP[0].xyyy
130: MOV TEMP[0].xy, TEMP[0].xyyy
131: TEX TEMP[0].x, TEMP[0], SAMP[4], 2D
132: MUL TEMP[3].x, CONST[22].yyyy, IMM[3].xxxx
133: FRC TEMP[3].x, TEMP[3].xxxx
134: ADD TEMP[0].x, TEMP[0].xxxx, TEMP[3].xxxx
135: MUL TEMP[0].x, TEMP[0].xxxx, IMM[3].yyyy
136: SIN TEMP[0].x, TEMP[0].xxxx
137: MAD TEMP[0].x, TEMP[0].xxxx, IMM[3].xxxx, IMM[0].xxxx
138: ADD_SAT TEMP[0].x, TEMP[2].wwww, TEMP[0].xxxx
139: LRP TEMP[0].x, CONST[22].xxxx, TEMP[0].xxxx, IMM[0].zzzz
140: MUL_SAT TEMP[0].xyz, TEMP[1].xyzz, TEMP[0].xxxx
141: MOV TEMP[6].xyz, TEMP[0].xyzx
142: MOV OUT[0], TEMP[6]
143: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %29 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %30 = load <32 x i8> addrspace(2)* %29, !tbaa !0
  %31 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0
  %35 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %42 = load <32 x i8> addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
  %46 = load <32 x i8> addrspace(2)* %45, !tbaa !0
  %47 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
  %50 = load <32 x i8> addrspace(2)* %49, !tbaa !0
  %51 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %54 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %55 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %56 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %57 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %59 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %60 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %61 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %62 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %63 = bitcast float %53 to i32
  %64 = bitcast float %54 to i32
  %65 = insertelement <2 x i32> undef, i32 %63, i32 0
  %66 = insertelement <2 x i32> %65, i32 %64, i32 1
  %67 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %66, <32 x i8> %38, <16 x i8> %40, i32 2)
  %68 = extractelement <4 x float> %67, i32 0
  %69 = extractelement <4 x float> %67, i32 1
  %70 = extractelement <4 x float> %67, i32 2
  %71 = bitcast float %55 to i32
  %72 = bitcast float %56 to i32
  %73 = insertelement <2 x i32> undef, i32 %71, i32 0
  %74 = insertelement <2 x i32> %73, i32 %72, i32 1
  %75 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %74, <32 x i8> %42, <16 x i8> %44, i32 2)
  %76 = extractelement <4 x float> %75, i32 0
  %77 = extractelement <4 x float> %75, i32 1
  %78 = extractelement <4 x float> %75, i32 2
  %79 = fcmp olt float %76, 5.000000e-01
  %80 = sext i1 %79 to i32
  %81 = bitcast i32 %80 to float
  %82 = bitcast float %81 to i32
  %83 = icmp ne i32 %82, 0
  br i1 %83, label %IF, label %ELSE

IF:                                               ; preds = %main_body
  %84 = fmul float 2.000000e+00, %76
  %85 = fmul float %84, %68
  br label %ENDIF

ELSE:                                             ; preds = %main_body
  %86 = fsub float -0.000000e+00, %76
  %87 = fadd float 1.000000e+00, %86
  %88 = fmul float 2.000000e+00, %87
  %89 = fsub float -0.000000e+00, %68
  %90 = fadd float 1.000000e+00, %89
  %91 = fmul float %88, %90
  %92 = fsub float -0.000000e+00, %91
  %93 = fadd float 1.000000e+00, %92
  br label %ENDIF

ENDIF:                                            ; preds = %ELSE, %IF
  %temp12.0 = phi float [ %85, %IF ], [ %93, %ELSE ]
  %94 = fcmp olt float %77, 5.000000e-01
  %95 = sext i1 %94 to i32
  %96 = bitcast i32 %95 to float
  %97 = bitcast float %96 to i32
  %98 = icmp ne i32 %97, 0
  br i1 %98, label %IF33, label %ELSE34

IF33:                                             ; preds = %ENDIF
  %99 = fmul float 2.000000e+00, %77
  %100 = fmul float %99, %69
  br label %ENDIF32

ELSE34:                                           ; preds = %ENDIF
  %101 = fsub float -0.000000e+00, %77
  %102 = fadd float 1.000000e+00, %101
  %103 = fmul float 2.000000e+00, %102
  %104 = fsub float -0.000000e+00, %69
  %105 = fadd float 1.000000e+00, %104
  %106 = fmul float %103, %105
  %107 = fsub float -0.000000e+00, %106
  %108 = fadd float 1.000000e+00, %107
  br label %ENDIF32

ENDIF32:                                          ; preds = %ELSE34, %IF33
  %temp16.0 = phi float [ %100, %IF33 ], [ %108, %ELSE34 ]
  %109 = fcmp olt float %78, 5.000000e-01
  %110 = sext i1 %109 to i32
  %111 = bitcast i32 %110 to float
  %112 = bitcast float %111 to i32
  %113 = icmp ne i32 %112, 0
  br i1 %113, label %IF36, label %ELSE37

IF36:                                             ; preds = %ENDIF32
  %114 = fmul float 2.000000e+00, %78
  %115 = fmul float %114, %70
  br label %ENDIF35

ELSE37:                                           ; preds = %ENDIF32
  %116 = fsub float -0.000000e+00, %78
  %117 = fadd float 1.000000e+00, %116
  %118 = fmul float 2.000000e+00, %117
  %119 = fsub float -0.000000e+00, %70
  %120 = fadd float 1.000000e+00, %119
  %121 = fmul float %118, %120
  %122 = fsub float -0.000000e+00, %121
  %123 = fadd float 1.000000e+00, %122
  br label %ENDIF35

ENDIF35:                                          ; preds = %ELSE37, %IF36
  %temp16.1 = phi float [ %115, %IF36 ], [ %123, %ELSE37 ]
  %124 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp12.0, float %68)
  %125 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp16.0, float %69)
  %126 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp16.1, float %70)
  %127 = bitcast float %53 to i32
  %128 = bitcast float %54 to i32
  %129 = insertelement <2 x i32> undef, i32 %127, i32 0
  %130 = insertelement <2 x i32> %129, i32 %128, i32 1
  %131 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %130, <32 x i8> %34, <16 x i8> %36, i32 2)
  %132 = extractelement <4 x float> %131, i32 0
  %133 = extractelement <4 x float> %131, i32 1
  %134 = extractelement <4 x float> %131, i32 2
  %135 = fadd float %132, -5.000000e-01
  %136 = fadd float %133, -5.000000e-01
  %137 = fadd float %134, -5.000000e-01
  %138 = fadd float %60, 5.000000e-01
  %139 = fdiv float 1.000000e+00, %22
  %140 = fmul float %138, %139
  %141 = fadd float %62, 5.000000e-01
  %142 = fsub float -0.000000e+00, %23
  %143 = fadd float %141, %142
  %144 = fsub float -0.000000e+00, %23
  %145 = fdiv float 1.000000e+00, %144
  %146 = fmul float %143, %145
  %147 = bitcast float %140 to i32
  %148 = bitcast float %146 to i32
  %149 = insertelement <2 x i32> undef, i32 %147, i32 0
  %150 = insertelement <2 x i32> %149, i32 %148, i32 1
  %151 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %150, <32 x i8> %30, <16 x i8> %32, i32 2)
  %152 = extractelement <4 x float> %151, i32 0
  %153 = extractelement <4 x float> %151, i32 1
  %154 = extractelement <4 x float> %151, i32 2
  %155 = fcmp olt float %152, 5.000000e-01
  %156 = sext i1 %155 to i32
  %157 = bitcast i32 %156 to float
  %158 = bitcast float %157 to i32
  %159 = icmp ne i32 %158, 0
  br i1 %159, label %IF39, label %ELSE40

IF39:                                             ; preds = %ENDIF35
  %160 = fmul float 2.000000e+00, %152
  %161 = fmul float %160, %124
  br label %ENDIF38

ELSE40:                                           ; preds = %ENDIF35
  %162 = fsub float -0.000000e+00, %152
  %163 = fadd float 1.000000e+00, %162
  %164 = fmul float 2.000000e+00, %163
  %165 = fsub float -0.000000e+00, %124
  %166 = fadd float 1.000000e+00, %165
  %167 = fmul float %164, %166
  %168 = fsub float -0.000000e+00, %167
  %169 = fadd float 1.000000e+00, %168
  br label %ENDIF38

ENDIF38:                                          ; preds = %ELSE40, %IF39
  %temp16.2 = phi float [ %161, %IF39 ], [ %169, %ELSE40 ]
  %170 = fcmp olt float %153, 5.000000e-01
  %171 = sext i1 %170 to i32
  %172 = bitcast i32 %171 to float
  %173 = bitcast float %172 to i32
  %174 = icmp ne i32 %173, 0
  br i1 %174, label %IF42, label %ELSE43

IF42:                                             ; preds = %ENDIF38
  %175 = fmul float 2.000000e+00, %153
  %176 = fmul float %175, %125
  br label %ENDIF41

ELSE43:                                           ; preds = %ENDIF38
  %177 = fsub float -0.000000e+00, %153
  %178 = fadd float 1.000000e+00, %177
  %179 = fmul float 2.000000e+00, %178
  %180 = fsub float -0.000000e+00, %125
  %181 = fadd float 1.000000e+00, %180
  %182 = fmul float %179, %181
  %183 = fsub float -0.000000e+00, %182
  %184 = fadd float 1.000000e+00, %183
  br label %ENDIF41

ENDIF41:                                          ; preds = %ELSE43, %IF42
  %temp20.0 = phi float [ %176, %IF42 ], [ %184, %ELSE43 ]
  %185 = fcmp olt float %154, 5.000000e-01
  %186 = sext i1 %185 to i32
  %187 = bitcast i32 %186 to float
  %188 = bitcast float %187 to i32
  %189 = icmp ne i32 %188, 0
  br i1 %189, label %IF45, label %ELSE46

IF45:                                             ; preds = %ENDIF41
  %190 = fmul float 2.000000e+00, %154
  %191 = fmul float %190, %126
  br label %ENDIF44

ELSE46:                                           ; preds = %ENDIF41
  %192 = fsub float -0.000000e+00, %154
  %193 = fadd float 1.000000e+00, %192
  %194 = fmul float 2.000000e+00, %193
  %195 = fsub float -0.000000e+00, %126
  %196 = fadd float 1.000000e+00, %195
  %197 = fmul float %194, %196
  %198 = fsub float -0.000000e+00, %197
  %199 = fadd float 1.000000e+00, %198
  br label %ENDIF44

ENDIF44:                                          ; preds = %ELSE46, %IF45
  %temp20.1 = phi float [ %191, %IF45 ], [ %199, %ELSE46 ]
  %200 = fmul float %135, %135
  %201 = fmul float %136, %136
  %202 = fadd float %201, %200
  %203 = fmul float %137, %137
  %204 = fadd float %202, %203
  %205 = call float @llvm.AMDGPU.rsq(float %204)
  %206 = fmul float %135, %205
  %207 = fmul float %136, %205
  %208 = fmul float %137, %205
  %209 = fmul float %57, %57
  %210 = fmul float %58, %58
  %211 = fadd float %210, %209
  %212 = fmul float %59, %59
  %213 = fadd float %211, %212
  %214 = call float @llvm.AMDGPU.rsq(float %213)
  %215 = fmul float %57, %214
  %216 = fmul float %58, %214
  %217 = fmul float %59, %214
  %218 = fsub float -0.000000e+00, %215
  %219 = fsub float -0.000000e+00, %216
  %220 = fsub float -0.000000e+00, %217
  %221 = fmul float %206, %218
  %222 = fmul float %207, %219
  %223 = fadd float %222, %221
  %224 = fmul float %208, %220
  %225 = fadd float %223, %224
  %226 = fmul float %225, 5.000000e-01
  %227 = fadd float %226, 5.000000e-01
  %228 = fsub float -0.000000e+00, %60
  %229 = fadd float %24, %228
  %230 = fsub float -0.000000e+00, %61
  %231 = fadd float %25, %230
  %232 = fsub float -0.000000e+00, %62
  %233 = fadd float %26, %232
  %234 = fadd float %60, 5.000000e-01
  %235 = fdiv float 1.000000e+00, %22
  %236 = fmul float %234, %235
  %237 = fadd float %62, 5.000000e-01
  %238 = fdiv float 1.000000e+00, %23
  %239 = fmul float %237, %238
  %240 = fmul float %227, %227
  %241 = fmul float 0x3FE99999A0000000, %240
  %242 = fadd float %241, 0x3FC99999A0000000
  %243 = call float @llvm.AMDGPU.lrp(float 2.500000e-01, float %temp16.2, float %124)
  %244 = call float @llvm.AMDGPU.lrp(float 2.500000e-01, float %temp20.0, float %125)
  %245 = call float @llvm.AMDGPU.lrp(float 2.500000e-01, float %temp20.1, float %126)
  %246 = fmul float %242, %243
  %247 = fmul float %242, %244
  %248 = fmul float %242, %245
  %249 = fmul float %246, 0x3FF3333340000000
  %250 = fmul float %247, 0x3FF3333340000000
  %251 = fmul float %248, 0x3FF3333340000000
  %252 = call float @llvm.AMDIL.clamp.(float %249, float 0.000000e+00, float 1.000000e+00)
  %253 = call float @llvm.AMDIL.clamp.(float %250, float 0.000000e+00, float 1.000000e+00)
  %254 = call float @llvm.AMDIL.clamp.(float %251, float 0.000000e+00, float 1.000000e+00)
  %255 = fmul float %229, %229
  %256 = fmul float %231, %231
  %257 = fadd float %256, %255
  %258 = fmul float %233, %233
  %259 = fadd float %257, %258
  %260 = fadd float %259, -1.600000e+05
  %261 = fmul float %260, 0x3EAA36E2E0000000
  %262 = fcmp uge float %261, 5.000000e-01
  %263 = select i1 %262, float 5.000000e-01, float %261
  %264 = call float @llvm.AMDIL.clamp.(float %263, float 0.000000e+00, float 1.000000e+00)
  %265 = fmul float %229, %229
  %266 = fmul float %231, %231
  %267 = fadd float %266, %265
  %268 = fmul float %233, %233
  %269 = fadd float %267, %268
  %270 = call float @llvm.AMDGPU.rsq(float %269)
  %271 = fmul float %231, %270
  %272 = fsub float -0.000000e+00, %271
  %273 = fadd float 1.000000e+00, %272
  %274 = fmul float %264, %273
  %275 = call float @llvm.AMDGPU.lrp(float %274, float 5.000000e-01, float %252)
  %276 = call float @llvm.AMDGPU.lrp(float %274, float 5.000000e-01, float %253)
  %277 = call float @llvm.AMDGPU.lrp(float %274, float 5.000000e-01, float %254)
  %278 = bitcast float %236 to i32
  %279 = bitcast float %239 to i32
  %280 = insertelement <2 x i32> undef, i32 %278, i32 0
  %281 = insertelement <2 x i32> %280, i32 %279, i32 1
  %282 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %281, <32 x i8> %50, <16 x i8> %52, i32 2)
  %283 = extractelement <4 x float> %282, i32 3
  %284 = fadd float %60, 5.000000e-01
  %285 = fadd float %62, 5.000000e-01
  %286 = fmul float %284, 3.906250e-03
  %287 = fmul float %285, 3.906250e-03
  %288 = fmul float %28, 0x3F947AE140000000
  %289 = fadd float %288, %286
  %290 = fmul float %28, 0x3F947AE140000000
  %291 = fadd float %290, %287
  %292 = bitcast float %289 to i32
  %293 = bitcast float %291 to i32
  %294 = insertelement <2 x i32> undef, i32 %292, i32 0
  %295 = insertelement <2 x i32> %294, i32 %293, i32 1
  %296 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %295, <32 x i8> %46, <16 x i8> %48, i32 2)
  %297 = extractelement <4 x float> %296, i32 0
  %298 = fmul float %28, 0x3FB99999A0000000
  %299 = call float @llvm.AMDIL.fraction.(float %298)
  %300 = fadd float %297, %299
  %301 = fmul float %300, 0x401921FB60000000
  %302 = call float @llvm.sin.f32(float %301)
  %303 = fmul float %302, 0x3FB99999A0000000
  %304 = fadd float %303, 5.000000e-01
  %305 = fadd float %283, %304
  %306 = call float @llvm.AMDIL.clamp.(float %305, float 0.000000e+00, float 1.000000e+00)
  %307 = call float @llvm.AMDGPU.lrp(float %27, float %306, float 1.000000e+00)
  %308 = fmul float %275, %307
  %309 = fmul float %276, %307
  %310 = fmul float %277, %307
  %311 = call float @llvm.AMDIL.clamp.(float %308, float 0.000000e+00, float 1.000000e+00)
  %312 = call float @llvm.AMDIL.clamp.(float %309, float 0.000000e+00, float 1.000000e+00)
  %313 = call float @llvm.AMDIL.clamp.(float %310, float 0.000000e+00, float 1.000000e+00)
  %314 = call i32 @llvm.SI.packf16(float %311, float %312)
  %315 = bitcast i32 %314 to float
  %316 = call i32 @llvm.SI.packf16(float %313, float 1.000000e+00)
  %317 = bitcast i32 %316 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %315, float %317, float %315, float %317)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0300
c80d0301
c8080200
c8090201
c084030c
c0c60518
bf8c007f
f0800700
00430f02
c82c0100
c82d0101
c8280000
c8290001
c0840308
c0c60510
bf8c0070
f0800700
00430c0a
d0020008
0201e10f
d2000002
00218280
d104000c
02010102
c8080900
c8090901
c81c0800
c81d0801
c80c0700
c80d0701
c8100600
c8110601
c8140500
c8150501
c8180400
c8190401
c0880100
bf8c0070
c2001159
c2009158
c203114a
c2039149
c2041148
c2049141
c2051140
bf8c007f
be8c240c
898c0c7e
080018f2
08021ef2
100202f5
d2820009
03ca0101
be8c250c
89fe0c7e
06001f0f
10121900
88fe0c7e
d002000c
0201e110
d2000000
00318280
d104000c
02010100
be8c240c
898c0c7e
08001af2
080220f2
100202f5
d2820013
03ca0101
be8c250c
89fe0c7e
06002110
10261b00
88fe0c7e
d002000c
0201e111
d2000000
00318280
d104000c
02010100
be98240c
8998187e
08001cf2
080222f2
100202f5
d2820008
03ca0101
be982518
c0860304
c0c80508
c08e0300
c0d00500
7e020209
7e00020a
bf8c007f
89fe187e
06102311
10101d08
88fe187e
061e04f0
081e030f
d2060010
22010101
7e205510
1020210f
7e225500
062406f0
101e2312
f0800700
00e8100f
bf8c0770
d002000a
0201e110
d200000f
00298280
d104000a
0201010f
101e1cf0
d2820008
043de108
101e1af0
d282000f
043de113
101818f0
d2820009
0431e109
f0800700
0064130a
bf8c0770
06162af1
061a28f1
061c26f1
be8a240a
898a0a7e
081412f2
081820f2
101818f5
d282000a
03ca150c
be8a250a
89fe0a7e
06142110
1014130a
88fe0a7e
d002000a
0201e111
d200000c
00298280
d104000a
0201010c
be8a240a
898a0a7e
08181ef2
082622f2
102626f5
d2820013
03ca1913
be8a250a
89fe0a7e
06182311
10261f0c
88fe0a7e
d002000a
0201e112
d200000c
00298280
d104000a
0201010c
be8a240a
898a0a7e
081810f2
082824f2
102828f5
d282000c
03ca1914
be8a250a
c0860314
c0c80528
c08c0310
c0ce0520
7e2a0200
7e280201
7e2c0206
7e300207
7e2e0208
bf8c007f
89fe0a7e
06182512
1018110c
88fe0a7e
080e0f18
08200717
10202110
d2820010
04420f07
08220516
d2820010
04422311
062220ff
c81c4000
102222ff
3551b717
d00c0000
0201e111
d2000011
0001e111
d2060811
02010111
7e205b10
100e2107
080e0ef2
100e0f11
08200ef2
10220d06
d2820011
04460b05
d2820011
04460904
7e225b11
10242306
100c1d0e
d2820006
041a1b0d
d2820006
041a170b
7e0c5b06
101c0d0e
101c250e
101a0d0d
100a2305
d2060005
22010105
100a0b0d
080a1d05
10082304
100c0d0b
10080906
08080905
d2820004
03c1e104
10080904
7e0a02ff
3e4ccccd
7e0c02ff
3f4ccccd
d2820004
04160d04
100c1eff
3f400000
7e0a02ff
3e800000
d2820006
041a0b13
100c0d04
100c0cff
3f99999a
d2060806
02010106
100c0d10
d2820006
0419e107
060404f0
101a04ff
3b800000
7e1602ff
3ca3d70a
d282000e
04361715
060606f0
101e06ff
3b800000
d282000d
043e1715
f0800100
00c70b0d
101a2aff
3dcccccd
7e1a410d
bf8c0770
06161b0b
101616ff
40c90fdb
101616ff
3e22f983
7e166b0b
7e1a02ff
3dcccccd
d282000b
03c21b0b
7e025501
10040302
7e005500
10020103
f0800800
00640001
bf8c0770
06001700
d2060800
02010100
080228f2
d2820000
04060114
10020106
d2060801
02010101
100412ff
3f400000
d2820002
040a0b0a
10040504
100404ff
3f99999a
d2060802
02010102
10040510
d2820002
0409e107
10040102
d2060802
02010102
5e020302
100410ff
3f400000
d2820002
040a0b0c
10040504
100404ff
3f99999a
d2060802
02010102
10040510
d2820002
0409e107
10000102
d2060800
02010100
d25e0000
0201e500
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL OUT[3], GENERIC[21]
DCL CONST[0..22]
DCL TEMP[0..8], LOCAL
IMM[0] FLT32 {    0.1592,     1.0000,    -1.0000,     0.5000}
IMM[1] FLT32 {    0.7500,     0.0000,     0.0000,     0.0000}
  0: MUL TEMP[0].x, IN[5].wwww, IMM[0].xxxx
  1: ADD TEMP[1].x, IN[4].xxxx, TEMP[0].xxxx
  2: FSGE TEMP[2].x, TEMP[1].xxxx, IMM[0].yyyy
  3: UIF TEMP[2].xxxx :0
  4:   ADD TEMP[2].x, TEMP[1].xxxx, IMM[0].zzzz
  5: ELSE :0
  6:   MOV TEMP[2].x, TEMP[1].xxxx
  7: ENDIF
  8: MOV TEMP[1].w, IMM[0].yyyy
  9: MAD TEMP[2].x, TEMP[2].xxxx, IMM[0].wwww, IMM[1].xxxx
 10: MUL TEMP[2].x, IN[0].yyyy, TEMP[2].xxxx
 11: SIN TEMP[3].x, IN[5].wwww
 12: COS TEMP[4].x, IN[5].wwww
 13: MUL TEMP[5].x, IN[0].zzzz, TEMP[3].xxxx
 14: MAD TEMP[5].x, IN[0].xxxx, TEMP[4].xxxx, -TEMP[5].xxxx
 15: MUL TEMP[6].x, IN[0].xxxx, TEMP[3].xxxx
 16: MAD TEMP[6].x, IN[0].zzzz, TEMP[4].xxxx, TEMP[6].xxxx
 17: MOV TEMP[5].y, TEMP[6].xxxx
 18: MOV TEMP[1].xz, TEMP[5].xxyx
 19: MUL TEMP[5].x, TEMP[5].xxxx, IN[6].xxxx
 20: MAD TEMP[5].x, TEMP[6].xxxx, IN[6].yyyy, TEMP[5].xxxx
 21: ADD TEMP[2].x, TEMP[2].xxxx, TEMP[5].xxxx
 22: MOV TEMP[1].y, TEMP[2].xxxx
 23: ADD TEMP[1].xyz, TEMP[1].xyzz, IN[5].xyzz
 24: MOV TEMP[2].xyz, TEMP[1].xyzx
 25: DP4 TEMP[5].x, TEMP[1], CONST[0]
 26: DP4 TEMP[6].x, TEMP[1], CONST[1]
 27: MOV TEMP[5].y, TEMP[6].xxxx
 28: DP4 TEMP[6].x, TEMP[1], CONST[2]
 29: MOV TEMP[5].z, TEMP[6].xxxx
 30: DP4 TEMP[1].x, TEMP[1], CONST[3]
 31: MOV TEMP[5].w, TEMP[1].xxxx
 32: MOV TEMP[1].xy, IN[3].xyxx
 33: MOV TEMP[6].y, IN[1].yyyy
 34: MUL TEMP[7].x, IN[1].zzzz, TEMP[3].xxxx
 35: MAD TEMP[7].x, IN[1].xxxx, TEMP[4].xxxx, -TEMP[7].xxxx
 36: MUL TEMP[8].x, IN[1].xxxx, TEMP[3].xxxx
 37: MAD TEMP[8].x, IN[1].zzzz, TEMP[4].xxxx, TEMP[8].xxxx
 38: MOV TEMP[7].y, TEMP[8].xxxx
 39: MOV TEMP[6].xz, TEMP[7].xxyx
 40: MOV TEMP[7].y, IN[2].yyyy
 41: MUL TEMP[8].x, IN[2].zzzz, TEMP[3].xxxx
 42: MAD TEMP[8].x, IN[2].xxxx, TEMP[4].xxxx, -TEMP[8].xxxx
 43: MUL TEMP[3].x, IN[2].xxxx, TEMP[3].xxxx
 44: MAD TEMP[3].x, IN[2].zzzz, TEMP[4].xxxx, TEMP[3].xxxx
 45: MOV TEMP[8].y, TEMP[3].xxxx
 46: MOV TEMP[7].xz, TEMP[8].xxyx
 47: MOV TEMP[3].y, IMM[1].yyyy
 48: MOV TEMP[3].x, TEMP[0].xxxx
 49: ADD TEMP[0].xy, TEMP[3].xyyy, IN[4].xyyy
 50: MOV TEMP[1].zw, TEMP[0].yyxy
 51: DP3 TEMP[0].x, CONST[17].xyzz, TEMP[7].xyzz
 52: MUL TEMP[3].xyz, TEMP[7].zxyy, TEMP[6].yzxx
 53: MAD TEMP[3].xyz, TEMP[7].yzxx, TEMP[6].zxyy, -TEMP[3].xyzz
 54: MUL TEMP[3].xyz, TEMP[3].xyzz, IN[2].wwww
 55: DP3 TEMP[3].x, CONST[17].xyzz, TEMP[3].xyzz
 56: MOV TEMP[0].y, TEMP[3].xxxx
 57: DP3 TEMP[3].x, CONST[17].xyzz, TEMP[6].xyzz
 58: MOV TEMP[0].z, TEMP[3].xxxx
 59: MOV TEMP[0].xyz, TEMP[0].xyzx
 60: MOV TEMP[0].w, TEMP[2].xxxx
 61: MOV TEMP[2].xy, TEMP[2].yzyy
 62: MOV OUT[1], TEMP[1]
 63: MOV OUT[2], TEMP[0]
 64: MOV OUT[3], TEMP[2]
 65: MOV OUT[0], TEMP[5]
 66: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
  %30 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
  %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %5)
  %33 = extractelement <4 x float> %32, i32 0
  %34 = extractelement <4 x float> %32, i32 1
  %35 = extractelement <4 x float> %32, i32 2
  %36 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
  %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %37, i32 0, i32 %5)
  %39 = extractelement <4 x float> %38, i32 0
  %40 = extractelement <4 x float> %38, i32 1
  %41 = extractelement <4 x float> %38, i32 2
  %42 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
  %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %5)
  %45 = extractelement <4 x float> %44, i32 0
  %46 = extractelement <4 x float> %44, i32 1
  %47 = extractelement <4 x float> %44, i32 2
  %48 = extractelement <4 x float> %44, i32 3
  %49 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0
  %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %5)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = extractelement <4 x float> %51, i32 1
  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
  %57 = extractelement <4 x float> %56, i32 0
  %58 = extractelement <4 x float> %56, i32 1
  %59 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
  %61 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %60, i32 0, i32 %5)
  %62 = extractelement <4 x float> %61, i32 0
  %63 = extractelement <4 x float> %61, i32 1
  %64 = extractelement <4 x float> %61, i32 2
  %65 = extractelement <4 x float> %61, i32 3
  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
  %69 = extractelement <4 x float> %68, i32 0
  %70 = extractelement <4 x float> %68, i32 1
  %71 = fmul float %65, 0x3FC45F3060000000
  %72 = fadd float %57, %71
  %73 = fcmp oge float %72, 1.000000e+00
  %74 = sext i1 %73 to i32
  %75 = bitcast i32 %74 to float
  %76 = bitcast float %75 to i32
  %77 = icmp ne i32 %76, 0
  br i1 %77, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %78 = fadd float %72, -1.000000e+00
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp8.0 = phi float [ %78, %IF ], [ %72, %main_body ]
  %79 = fmul float %temp8.0, 5.000000e-01
  %80 = fadd float %79, 7.500000e-01
  %81 = fmul float %34, %80
  %82 = call float @llvm.sin.f32(float %65)
  %83 = call float @llvm.cos.f32(float %65)
  %84 = fmul float %35, %82
  %85 = fsub float -0.000000e+00, %84
  %86 = fmul float %33, %83
  %87 = fadd float %86, %85
  %88 = fmul float %33, %82
  %89 = fmul float %35, %83
  %90 = fadd float %89, %88
  %91 = fmul float %87, %69
  %92 = fmul float %90, %70
  %93 = fadd float %92, %91
  %94 = fadd float %81, %93
  %95 = fadd float %87, %62
  %96 = fadd float %94, %63
  %97 = fadd float %90, %64
  %98 = fmul float %95, %11
  %99 = fmul float %96, %12
  %100 = fadd float %98, %99
  %101 = fmul float %97, %13
  %102 = fadd float %100, %101
  %103 = fmul float 1.000000e+00, %14
  %104 = fadd float %102, %103
  %105 = fmul float %95, %15
  %106 = fmul float %96, %16
  %107 = fadd float %105, %106
  %108 = fmul float %97, %17
  %109 = fadd float %107, %108
  %110 = fmul float 1.000000e+00, %18
  %111 = fadd float %109, %110
  %112 = fmul float %95, %19
  %113 = fmul float %96, %20
  %114 = fadd float %112, %113
  %115 = fmul float %97, %21
  %116 = fadd float %114, %115
  %117 = fmul float 1.000000e+00, %22
  %118 = fadd float %116, %117
  %119 = fmul float %95, %23
  %120 = fmul float %96, %24
  %121 = fadd float %119, %120
  %122 = fmul float %97, %25
  %123 = fadd float %121, %122
  %124 = fmul float 1.000000e+00, %26
  %125 = fadd float %123, %124
  %126 = fmul float %41, %82
  %127 = fsub float -0.000000e+00, %126
  %128 = fmul float %39, %83
  %129 = fadd float %128, %127
  %130 = fmul float %39, %82
  %131 = fmul float %41, %83
  %132 = fadd float %131, %130
  %133 = fmul float %47, %82
  %134 = fsub float -0.000000e+00, %133
  %135 = fmul float %45, %83
  %136 = fadd float %135, %134
  %137 = fmul float %45, %82
  %138 = fmul float %47, %83
  %139 = fadd float %138, %137
  %140 = fadd float %71, %57
  %141 = fadd float 0.000000e+00, %58
  %142 = fmul float %27, %136
  %143 = fmul float %28, %46
  %144 = fadd float %143, %142
  %145 = fmul float %29, %139
  %146 = fadd float %144, %145
  %147 = fmul float %139, %40
  %148 = fmul float %136, %132
  %149 = fmul float %46, %129
  %150 = fsub float -0.000000e+00, %147
  %151 = fmul float %46, %132
  %152 = fadd float %151, %150
  %153 = fsub float -0.000000e+00, %148
  %154 = fmul float %139, %129
  %155 = fadd float %154, %153
  %156 = fsub float -0.000000e+00, %149
  %157 = fmul float %136, %40
  %158 = fadd float %157, %156
  %159 = fmul float %152, %48
  %160 = fmul float %155, %48
  %161 = fmul float %158, %48
  %162 = fmul float %27, %159
  %163 = fmul float %28, %160
  %164 = fadd float %163, %162
  %165 = fmul float %29, %161
  %166 = fadd float %164, %165
  %167 = fmul float %27, %129
  %168 = fmul float %28, %40
  %169 = fadd float %168, %167
  %170 = fmul float %29, %132
  %171 = fadd float %169, %170
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %52, float %53, float %140, float %141)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %146, float %166, float %171, float %95)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %96, float %97, float %97, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %104, float %111, float %118, float %125)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.cos.f32(float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840710
bf8c007f
e00c2000
80021600
c0840714
bf8c0070
e00c2000
80020100
7e0a02ff
3e22f983
bf8c0770
d2820005
045a0b04
d00c0002
0201e505
c0840718
bf8c007f
e00c2000
80020600
c084070c
bf8c0070
e00c2000
80022900
c0840708
bf8c0070
e00c2000
80020e00
c0840704
bf8c0070
e00c2000
80021200
c0820700
bf8c0070
e00c2000
80010a00
106008ff
3e22f983
c0820100
bf8c0070
c2000546
c2008545
c2040544
c204850f
c205050e
c205850d
c206050c
c206850b
c207050a
c2078509
c2080508
c2088507
c2090506
c2098505
c20a0504
c20a8503
c20b0502
c20b8501
c2020500
bf8c007f
7e5a0200
7e5c0201
7e5e0208
7e380209
7e40020a
7e50020b
7e4e020c
7e36020d
7e3e020e
7e4c020f
7e4a0210
7e340211
7e3c0212
7e480213
7e460214
7e000215
7e3a0216
7e440217
7e420204
be802402
8980007e
060a0af3
88fe007e
06602d30
062c2e80
f800020f
16302a29
102e08ff
3e22f983
bf8c070f
7e2c6b17
10302d10
7e2e6d17
10322f0e
08303119
10322d12
d2820019
04662f14
10563318
10522d14
10542f12
0854532a
10522d0e
d2820029
04a62f10
10585529
0856572c
1056232b
10582729
1060330f
08585930
1058232c
1058592f
d282002b
04b2572e
1058550f
10602718
08585930
1058232c
d282002b
04ae592d
1054552f
d2820012
04aa272e
d2820012
044a332d
1026312f
d282000e
044e1f2e
d282000f
043a532d
101c2d0c
10202f0a
08201d10
061c0310
f800021f
0e122b0f
10200d10
bf8c070f
101e2d0a
d282000f
043e2f0c
d2820006
04420f0f
7e0e02ff
3f400000
d2820005
041de105
d2820005
041a0b0b
060a0505
0602070f
7e040280
f800022f
02010105
bf8c070f
10045105
d2820002
040a4f0e
d2820002
040a4101
06043902
10064d05
d2820003
040e4b0e
d2820003
040e3f01
06063703
10084905
d2820004
0412470e
d2820004
04123d01
06083504
100a4505
d2820005
0416430e
d2820001
04163b01
06000101
f80008cf
02030400
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL OUT[3], GENERIC[21]
DCL CONST[0..22]
DCL TEMP[0..8], LOCAL
IMM[0] FLT32 {    0.1592,     1.0000,    -1.0000,     0.5000}
IMM[1] FLT32 {    0.7500,     0.0000,     0.0000,     0.0000}
  0: MUL TEMP[0].x, IN[5].wwww, IMM[0].xxxx
  1: ADD TEMP[1].x, IN[4].xxxx, TEMP[0].xxxx
  2: FSGE TEMP[2].x, TEMP[1].xxxx, IMM[0].yyyy
  3: UIF TEMP[2].xxxx :0
  4:   ADD TEMP[2].x, TEMP[1].xxxx, IMM[0].zzzz
  5: ELSE :0
  6:   MOV TEMP[2].x, TEMP[1].xxxx
  7: ENDIF
  8: MOV TEMP[1].w, IMM[0].yyyy
  9: MAD TEMP[2].x, TEMP[2].xxxx, IMM[0].wwww, IMM[1].xxxx
 10: MUL TEMP[2].x, IN[0].yyyy, TEMP[2].xxxx
 11: SIN TEMP[3].x, IN[5].wwww
 12: COS TEMP[4].x, IN[5].wwww
 13: MUL TEMP[5].x, IN[0].zzzz, TEMP[3].xxxx
 14: MAD TEMP[5].x, IN[0].xxxx, TEMP[4].xxxx, -TEMP[5].xxxx
 15: MUL TEMP[6].x, IN[0].xxxx, TEMP[3].xxxx
 16: MAD TEMP[6].x, IN[0].zzzz, TEMP[4].xxxx, TEMP[6].xxxx
 17: MOV TEMP[5].y, TEMP[6].xxxx
 18: MOV TEMP[1].xz, TEMP[5].xxyx
 19: MUL TEMP[5].x, TEMP[5].xxxx, IN[6].xxxx
 20: MAD TEMP[5].x, TEMP[6].xxxx, IN[6].yyyy, TEMP[5].xxxx
 21: ADD TEMP[2].x, TEMP[2].xxxx, TEMP[5].xxxx
 22: MOV TEMP[1].y, TEMP[2].xxxx
 23: ADD TEMP[1].xyz, TEMP[1].xyzz, IN[5].xyzz
 24: MOV TEMP[2].xyz, TEMP[1].xyzx
 25: DP4 TEMP[5].x, TEMP[1], CONST[0]
 26: DP4 TEMP[6].x, TEMP[1], CONST[1]
 27: MOV TEMP[5].y, TEMP[6].xxxx
 28: DP4 TEMP[6].x, TEMP[1], CONST[2]
 29: MOV TEMP[5].z, TEMP[6].xxxx
 30: DP4 TEMP[1].x, TEMP[1], CONST[3]
 31: MOV TEMP[5].w, TEMP[1].xxxx
 32: MOV TEMP[1].xy, IN[3].xyxx
 33: MOV TEMP[6].y, IN[1].yyyy
 34: MUL TEMP[7].x, IN[1].zzzz, TEMP[3].xxxx
 35: MAD TEMP[7].x, IN[1].xxxx, TEMP[4].xxxx, -TEMP[7].xxxx
 36: MUL TEMP[8].x, IN[1].xxxx, TEMP[3].xxxx
 37: MAD TEMP[8].x, IN[1].zzzz, TEMP[4].xxxx, TEMP[8].xxxx
 38: MOV TEMP[7].y, TEMP[8].xxxx
 39: MOV TEMP[6].xz, TEMP[7].xxyx
 40: MOV TEMP[7].y, IN[2].yyyy
 41: MUL TEMP[8].x, IN[2].zzzz, TEMP[3].xxxx
 42: MAD TEMP[8].x, IN[2].xxxx, TEMP[4].xxxx, -TEMP[8].xxxx
 43: MUL TEMP[3].x, IN[2].xxxx, TEMP[3].xxxx
 44: MAD TEMP[3].x, IN[2].zzzz, TEMP[4].xxxx, TEMP[3].xxxx
 45: MOV TEMP[8].y, TEMP[3].xxxx
 46: MOV TEMP[7].xz, TEMP[8].xxyx
 47: MOV TEMP[3].y, IMM[1].yyyy
 48: MOV TEMP[3].x, TEMP[0].xxxx
 49: ADD TEMP[0].xy, TEMP[3].xyyy, IN[4].xyyy
 50: MOV TEMP[1].zw, TEMP[0].yyxy
 51: DP3 TEMP[0].x, CONST[17].xyzz, TEMP[7].xyzz
 52: MUL TEMP[3].xyz, TEMP[7].zxyy, TEMP[6].yzxx
 53: MAD TEMP[3].xyz, TEMP[7].yzxx, TEMP[6].zxyy, -TEMP[3].xyzz
 54: MUL TEMP[3].xyz, TEMP[3].xyzz, IN[2].wwww
 55: DP3 TEMP[3].x, CONST[17].xyzz, TEMP[3].xyzz
 56: MOV TEMP[0].y, TEMP[3].xxxx
 57: DP3 TEMP[3].x, CONST[17].xyzz, TEMP[6].xyzz
 58: MOV TEMP[0].z, TEMP[3].xxxx
 59: MOV TEMP[0].xyz, TEMP[0].xyzx
 60: MOV TEMP[0].w, TEMP[2].xxxx
 61: MOV TEMP[2].xy, TEMP[2].yzyy
 62: MOV OUT[1], TEMP[1]
 63: MOV OUT[2], TEMP[0]
 64: MOV OUT[3], TEMP[2]
 65: MOV OUT[0], TEMP[5]
 66: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
  %30 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
  %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %5)
  %33 = extractelement <4 x float> %32, i32 0
  %34 = extractelement <4 x float> %32, i32 1
  %35 = extractelement <4 x float> %32, i32 2
  %36 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
  %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %37, i32 0, i32 %5)
  %39 = extractelement <4 x float> %38, i32 0
  %40 = extractelement <4 x float> %38, i32 1
  %41 = extractelement <4 x float> %38, i32 2
  %42 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
  %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %5)
  %45 = extractelement <4 x float> %44, i32 0
  %46 = extractelement <4 x float> %44, i32 1
  %47 = extractelement <4 x float> %44, i32 2
  %48 = extractelement <4 x float> %44, i32 3
  %49 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0
  %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %5)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = extractelement <4 x float> %51, i32 1
  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
  %57 = extractelement <4 x float> %56, i32 0
  %58 = extractelement <4 x float> %56, i32 1
  %59 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
  %61 = add i32 %8, %4
  %62 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %60, i32 0, i32 %61)
  %63 = extractelement <4 x float> %62, i32 0
  %64 = extractelement <4 x float> %62, i32 1
  %65 = extractelement <4 x float> %62, i32 2
  %66 = extractelement <4 x float> %62, i32 3
  %67 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
  %69 = add i32 %8, %4
  %70 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %69)
  %71 = extractelement <4 x float> %70, i32 0
  %72 = extractelement <4 x float> %70, i32 1
  %73 = fmul float %66, 0x3FC45F3060000000
  %74 = fadd float %57, %73
  %75 = fcmp oge float %74, 1.000000e+00
  %76 = sext i1 %75 to i32
  %77 = bitcast i32 %76 to float
  %78 = bitcast float %77 to i32
  %79 = icmp ne i32 %78, 0
  br i1 %79, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %80 = fadd float %74, -1.000000e+00
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp8.0 = phi float [ %80, %IF ], [ %74, %main_body ]
  %81 = fmul float %temp8.0, 5.000000e-01
  %82 = fadd float %81, 7.500000e-01
  %83 = fmul float %34, %82
  %84 = call float @llvm.sin.f32(float %66)
  %85 = call float @llvm.cos.f32(float %66)
  %86 = fmul float %35, %84
  %87 = fsub float -0.000000e+00, %86
  %88 = fmul float %33, %85
  %89 = fadd float %88, %87
  %90 = fmul float %33, %84
  %91 = fmul float %35, %85
  %92 = fadd float %91, %90
  %93 = fmul float %89, %71
  %94 = fmul float %92, %72
  %95 = fadd float %94, %93
  %96 = fadd float %83, %95
  %97 = fadd float %89, %63
  %98 = fadd float %96, %64
  %99 = fadd float %92, %65
  %100 = fmul float %97, %11
  %101 = fmul float %98, %12
  %102 = fadd float %100, %101
  %103 = fmul float %99, %13
  %104 = fadd float %102, %103
  %105 = fmul float 1.000000e+00, %14
  %106 = fadd float %104, %105
  %107 = fmul float %97, %15
  %108 = fmul float %98, %16
  %109 = fadd float %107, %108
  %110 = fmul float %99, %17
  %111 = fadd float %109, %110
  %112 = fmul float 1.000000e+00, %18
  %113 = fadd float %111, %112
  %114 = fmul float %97, %19
  %115 = fmul float %98, %20
  %116 = fadd float %114, %115
  %117 = fmul float %99, %21
  %118 = fadd float %116, %117
  %119 = fmul float 1.000000e+00, %22
  %120 = fadd float %118, %119
  %121 = fmul float %97, %23
  %122 = fmul float %98, %24
  %123 = fadd float %121, %122
  %124 = fmul float %99, %25
  %125 = fadd float %123, %124
  %126 = fmul float 1.000000e+00, %26
  %127 = fadd float %125, %126
  %128 = fmul float %41, %84
  %129 = fsub float -0.000000e+00, %128
  %130 = fmul float %39, %85
  %131 = fadd float %130, %129
  %132 = fmul float %39, %84
  %133 = fmul float %41, %85
  %134 = fadd float %133, %132
  %135 = fmul float %47, %84
  %136 = fsub float -0.000000e+00, %135
  %137 = fmul float %45, %85
  %138 = fadd float %137, %136
  %139 = fmul float %45, %84
  %140 = fmul float %47, %85
  %141 = fadd float %140, %139
  %142 = fadd float %73, %57
  %143 = fadd float 0.000000e+00, %58
  %144 = fmul float %27, %138
  %145 = fmul float %28, %46
  %146 = fadd float %145, %144
  %147 = fmul float %29, %141
  %148 = fadd float %146, %147
  %149 = fmul float %141, %40
  %150 = fmul float %138, %134
  %151 = fmul float %46, %131
  %152 = fsub float -0.000000e+00, %149
  %153 = fmul float %46, %134
  %154 = fadd float %153, %152
  %155 = fsub float -0.000000e+00, %150
  %156 = fmul float %141, %131
  %157 = fadd float %156, %155
  %158 = fsub float -0.000000e+00, %151
  %159 = fmul float %138, %40
  %160 = fadd float %159, %158
  %161 = fmul float %154, %48
  %162 = fmul float %157, %48
  %163 = fmul float %160, %48
  %164 = fmul float %27, %161
  %165 = fmul float %28, %162
  %166 = fadd float %165, %164
  %167 = fmul float %29, %163
  %168 = fadd float %166, %167
  %169 = fmul float %27, %131
  %170 = fmul float %28, %40
  %171 = fadd float %170, %169
  %172 = fmul float %29, %134
  %173 = fadd float %171, %172
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %52, float %53, float %142, float %143)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %148, float %168, float %173, float %97)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %98, float %99, float %99, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %106, float %113, float %120, float %127)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.cos.f32(float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0860710
bf8c007f
e00c2000
80031600
4a0c0608
c0840714
bf8c0070
e00c2000
80020106
7e0a02ff
3e22f983
bf8c0770
d2820005
045a0b04
d00c0002
0201e505
c0840718
bf8c007f
e00c2000
80020606
c084070c
bf8c0070
e00c2000
80022900
c0840708
bf8c0070
e00c2000
80020e00
c0840704
bf8c0070
e00c2000
80021200
c0820700
bf8c0070
e00c2000
80010a00
106008ff
3e22f983
c0820100
bf8c0070
c2000546
c2008545
c2040544
c204850f
c205050e
c205850d
c206050c
c206850b
c207050a
c2078509
c2080508
c2088507
c2090506
c2098505
c20a0504
c20a8503
c20b0502
c20b8501
c2020500
bf8c007f
7e5a0200
7e5c0201
7e5e0208
7e380209
7e40020a
7e50020b
7e4e020c
7e36020d
7e3e020e
7e4c020f
7e4a0210
7e340211
7e3c0212
7e480213
7e460214
7e000215
7e3a0216
7e440217
7e420204
be802402
8980007e
060a0af3
88fe007e
06602d30
062c2e80
f800020f
16302a29
102e08ff
3e22f983
bf8c070f
7e2c6b17
10302d10
7e2e6d17
10322f0e
08303119
10322d12
d2820019
04662f14
10563318
10522d14
10542f12
0854532a
10522d0e
d2820029
04a62f10
10585529
0856572c
1056232b
10582729
1060330f
08585930
1058232c
1058592f
d282002b
04b2572e
1058550f
10602718
08585930
1058232c
d282002b
04ae592d
1054552f
d2820012
04aa272e
d2820012
044a332d
1026312f
d282000e
044e1f2e
d282000f
043a532d
101c2d0c
10202f0a
08201d10
061c0310
f800021f
0e122b0f
10200d10
bf8c070f
101e2d0a
d282000f
043e2f0c
d2820006
04420f0f
7e0e02ff
3f400000
d2820005
041de105
d2820005
041a0b0b
060a0505
0602070f
7e040280
f800022f
02010105
bf8c070f
10045105
d2820002
040a4f0e
d2820002
040a4101
06043902
10064d05
d2820003
040e4b0e
d2820003
040e3f01
06063703
10084905
d2820004
0412470e
d2820004
04123d01
06083504
100a4505
d2820005
0416430e
d2820001
04163b01
06000101
f80008cf
02030400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL SAMP[4]
DCL SAMP[5]
DCL SAMP[6]
DCL SAMP[7]
DCL SAMP[8]
DCL SAMP[9]
DCL CONST[0..25]
DCL CONST[36]
DCL TEMP[0..18], LOCAL
IMM[0] FLT32 {  -16.0000,     0.0000,    -0.5000,   255.0000}
IMM[1] FLT32 {  -98.0000,   100.0000,     0.5000,     0.2500}
IMM[2] FLT32 {    4.0000,   128.0000,   512.0000,     6.0000}
IMM[3] FLT32 {    2.0000,    11.0000,    -1.0000,     1.0000}
IMM[4] FLT32 {    8.0000,    10.0000,     0.0278,     0.1667}
IMM[5] UINT32 {0, 0, 0, 0}
IMM[6] INT32 {36, 6, 0, 0}
IMM[7] FLT32 {    0.1250,    -0.7000, 10000.0000,     3.0000}
IMM[8] FLT32 {    0.8000,     0.2000,     1.2000, -160000.0000}
IMM[9] FLT32 {    0.0000,     0.0200,     0.0039,     0.1000}
IMM[10] FLT32 {    6.2832,     0.0000,     0.0000,     0.0000}
  0: ADD TEMP[0].x, IMM[0].xxxx, IN[1].yyyy
  1: FSLT TEMP[0].x, TEMP[0].xxxx, IMM[0].yyyy
  2: UIF TEMP[0].xxxx :0
  3:   KILL
  4: ENDIF
  5: RCP TEMP[0].x, CONST[16].xxxx
  6: MUL TEMP[0].x, IMM[0].zzzz, TEMP[0].xxxx
  7: RCP TEMP[1].x, CONST[16].yyyy
  8: MUL TEMP[1].x, IMM[0].zzzz, TEMP[1].xxxx
  9: MOV TEMP[0].y, TEMP[1].xxxx
 10: ADD TEMP[0].xy, IN[0].xyyy, TEMP[0].xyyy
 11: MOV TEMP[0].xy, TEMP[0].xyyy
 12: TEX TEMP[0], TEMP[0], SAMP[7], 2D
 13: MUL TEMP[0], TEMP[0], IMM[0].wwww
 14: MOV TEMP[1].xyw, TEMP[0].xyxw
 15: ADD_SAT TEMP[2].x, TEMP[0].zzzz, IMM[1].xxxx
 16: MUL TEMP[3].x, TEMP[2].xxxx, IMM[1].yyyy
 17: ADD TEMP[0].x, TEMP[0].zzzz, -TEMP[3].xxxx
 18: MOV TEMP[1].z, TEMP[0].xxxx
 19: ADD TEMP[0], TEMP[1], IMM[1].zzzz
 20: MUL TEMP[0], TEMP[0], IMM[1].wwww
 21: FLR TEMP[0], TEMP[0]
 22: MUL TEMP[3], TEMP[0], IMM[2].xxxx
 23: ADD TEMP[1], TEMP[1], -TEMP[3]
 24: ADD TEMP[1], TEMP[1], IMM[1].zzzz
 25: FLR TEMP[1], TEMP[1]
 26: MUL TEMP[3].xy, IN[0].zwww, IMM[2].yyyy
 27: MOV TEMP[4].y, TEMP[3].yyyy
 28: RCP TEMP[5].x, CONST[16].yyyy
 29: MUL TEMP[5].x, CONST[16].xxxx, TEMP[5].xxxx
 30: MUL TEMP[4].x, TEMP[3].xxxx, TEMP[5].xxxx
 31: MUL TEMP[5].x, TEMP[4].xxxx, IMM[2].zzzz
 32: DDX TEMP[6].x, TEMP[5].xxxx
 33: ABS TEMP[6].x, TEMP[6].xxxx
 34: MUL TEMP[7], CONST[36].xxxx, TEMP[5].xxxx
 35: DDY TEMP[5].x, TEMP[7]
 36: ABS TEMP[5].x, TEMP[5].xxxx
 37: ADD TEMP[5].x, TEMP[6].xxxx, TEMP[5].xxxx
 38: MUL TEMP[3].x, TEMP[3].yyyy, IMM[2].zzzz
 39: DDX TEMP[6].x, TEMP[3].xxxx
 40: ABS TEMP[6].x, TEMP[6].xxxx
 41: MUL TEMP[7], CONST[36].xxxx, TEMP[3].xxxx
 42: DDY TEMP[3].x, TEMP[7]
 43: ABS TEMP[3].x, TEMP[3].xxxx
 44: ADD TEMP[3].x, TEMP[6].xxxx, TEMP[3].xxxx
 45: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx
 46: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[3].xxxx
 47: MAX TEMP[3].x, TEMP[5].xxxx, TEMP[3].xxxx
 48: LG2 TEMP[3].x, TEMP[3].xxxx
 49: MAD TEMP[3].x, IMM[1].zzzz, TEMP[3].xxxx, IMM[0].zzzz
 50: FLR TEMP[3].x, TEMP[3].xxxx
 51: MIN TEMP[3].x, TEMP[3].xxxx, IMM[2].wwww
 52: MAX TEMP[3].x, TEMP[3].xxxx, IMM[0].yyyy
 53: ADD TEMP[5].x, IMM[3].yyyy, -TEMP[3].xxxx
 54: POW TEMP[5].x, IMM[3].xxxx, TEMP[5].xxxx
 55: MUL TEMP[6].xy, IN[0].zwww, CONST[16].zwww
 56: MOV TEMP[6].xy, TEMP[6].xyyy
 57: TEX TEMP[6].xyz, TEMP[6], SAMP[2], 2D
 58: ADD TEMP[6].xyz, TEMP[6].xzyy, IMM[0].zzzz
 59: DP3 TEMP[7].x, TEMP[6].xyzz, TEMP[6].xyzz
 60: RSQ TEMP[7].x, TEMP[7].xxxx
 61: MUL TEMP[6].xyz, TEMP[6].xyzz, TEMP[7].xxxx
 62: MUL TEMP[7].x, TEMP[5].xxxx, IMM[1].wwww
 63: MOV TEMP[8].x, TEMP[1].wwww
 64: MOV TEMP[8].y, TEMP[0].wwww
 65: RCP TEMP[9].x, TEMP[5].xxxx
 66: FRC TEMP[10].xy, TEMP[4].xyyy
 67: ADD TEMP[11].x, TEMP[7].xxxx, IMM[3].zzzz
 68: RCP TEMP[12].x, TEMP[7].xxxx
 69: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[12].xxxx
 70: MAD TEMP[8].xy, TEMP[10].xyyy, TEMP[11].xxxx, TEMP[8].xyyy
 71: MUL TEMP[8].xy, TEMP[8].xyyy, IMM[1].wwww
 72: MAD TEMP[7].xy, IMM[1].zzzz, TEMP[9].xxxx, TEMP[8].xyyy
 73: MOV TEMP[7].xy, TEMP[7].xyyy
 74: MOV TEMP[7].w, TEMP[3].xxxx
 75: TXL TEMP[7], TEMP[7], SAMP[5], 2D
 76: MOV TEMP[8].xyz, TEMP[7]
 77: MUL TEMP[9].x, TEMP[5].xxxx, IMM[1].wwww
 78: MOV TEMP[10].x, TEMP[1].wwww
 79: MOV TEMP[10].y, TEMP[0].wwww
 80: RCP TEMP[11].x, TEMP[5].xxxx
 81: FRC TEMP[12].xy, TEMP[4].xyyy
 82: ADD TEMP[13].x, TEMP[9].xxxx, IMM[3].zzzz
 83: RCP TEMP[14].x, TEMP[9].xxxx
 84: MUL TEMP[13].x, TEMP[13].xxxx, TEMP[14].xxxx
 85: MAD TEMP[10].xy, TEMP[12].xyyy, TEMP[13].xxxx, TEMP[10].xyyy
 86: MUL TEMP[10].xy, TEMP[10].xyyy, IMM[1].wwww
 87: MAD TEMP[9].xy, IMM[1].zzzz, TEMP[11].xxxx, TEMP[10].xyyy
 88: MOV TEMP[9].xy, TEMP[9].xyyy
 89: MOV TEMP[9].w, TEMP[3].xxxx
 90: TXL TEMP[9].xyz, TEMP[9], SAMP[0], 2D
 91: ADD TEMP[9].xyz, TEMP[9].xzyy, IMM[0].zzzz
 92: FSLT TEMP[2].x, TEMP[2].xxxx, IMM[3].wwww
 93: UIF TEMP[2].xxxx :0
 94:   FSLT TEMP[2].x, CONST[25].zzzz, IMM[4].xxxx
 95: ELSE :0
 96:   MOV TEMP[2].x, IMM[5].xxxx
 97: ENDIF
 98: UIF TEMP[2].xxxx :0
 99:   MUL TEMP[2].x, TEMP[5].xxxx, IMM[1].wwww
100:   MOV TEMP[10].x, TEMP[1].xxxx
101:   MOV TEMP[10].y, TEMP[0].xxxx
102:   RCP TEMP[11].x, TEMP[5].xxxx
103:   FRC TEMP[12].xy, TEMP[4].xyyy
104:   ADD TEMP[13].x, TEMP[2].xxxx, IMM[3].zzzz
105:   RCP TEMP[14].x, TEMP[2].xxxx
106:   MUL TEMP[13].x, TEMP[13].xxxx, TEMP[14].xxxx
107:   MAD TEMP[10].xy, TEMP[12].xyyy, TEMP[13].xxxx, TEMP[10].xyyy
108:   MUL TEMP[10].xy, TEMP[10].xyyy, IMM[1].wwww
109:   MAD TEMP[2].xy, IMM[1].zzzz, TEMP[11].xxxx, TEMP[10].xyyy
110:   MOV TEMP[2].xy, TEMP[2].xyyy
111:   MOV TEMP[2].w, TEMP[3].xxxx
112:   TXL TEMP[2], TEMP[2], SAMP[5], 2D
113:   MUL TEMP[10].x, TEMP[5].xxxx, IMM[1].wwww
114:   MOV TEMP[11].x, TEMP[1].yyyy
115:   MOV TEMP[11].y, TEMP[0].yyyy
116:   RCP TEMP[12].x, TEMP[5].xxxx
117:   FRC TEMP[13].xy, TEMP[4].xyyy
118:   ADD TEMP[14].x, TEMP[10].xxxx, IMM[3].zzzz
119:   RCP TEMP[15].x, TEMP[10].xxxx
120:   MUL TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx
121:   MAD TEMP[11].xy, TEMP[13].xyyy, TEMP[14].xxxx, TEMP[11].xyyy
122:   MUL TEMP[11].xy, TEMP[11].xyyy, IMM[1].wwww
123:   MAD TEMP[10].xy, IMM[1].zzzz, TEMP[12].xxxx, TEMP[11].xyyy
124:   MOV TEMP[10].xy, TEMP[10].xyyy
125:   MOV TEMP[10].w, TEMP[3].xxxx
126:   TXL TEMP[10], TEMP[10], SAMP[5], 2D
127:   MUL TEMP[11].x, TEMP[5].xxxx, IMM[1].wwww
128:   MOV TEMP[12].x, TEMP[1].zzzz
129:   MOV TEMP[12].y, TEMP[0].zzzz
130:   RCP TEMP[13].x, TEMP[5].xxxx
131:   FRC TEMP[14].xy, TEMP[4].xyyy
132:   ADD TEMP[15].x, TEMP[11].xxxx, IMM[3].zzzz
133:   RCP TEMP[16].x, TEMP[11].xxxx
134:   MUL TEMP[15].x, TEMP[15].xxxx, TEMP[16].xxxx
135:   MAD TEMP[12].xy, TEMP[14].xyyy, TEMP[15].xxxx, TEMP[12].xyyy
136:   MUL TEMP[12].xy, TEMP[12].xyyy, IMM[1].wwww
137:   MAD TEMP[11].xy, IMM[1].zzzz, TEMP[13].xxxx, TEMP[12].xyyy
138:   MOV TEMP[11].xy, TEMP[11].xyyy
139:   MOV TEMP[11].w, TEMP[3].xxxx
140:   TXL TEMP[11], TEMP[11], SAMP[5], 2D
141:   MUL TEMP[12].x, TEMP[5].xxxx, IMM[1].wwww
142:   MOV TEMP[13].x, TEMP[1].xxxx
143:   MOV TEMP[13].y, TEMP[0].xxxx
144:   RCP TEMP[14].x, TEMP[5].xxxx
145:   FRC TEMP[15].xy, TEMP[4].xyyy
146:   ADD TEMP[16].x, TEMP[12].xxxx, IMM[3].zzzz
147:   RCP TEMP[17].x, TEMP[12].xxxx
148:   MUL TEMP[16].x, TEMP[16].xxxx, TEMP[17].xxxx
149:   MAD TEMP[13].xy, TEMP[15].xyyy, TEMP[16].xxxx, TEMP[13].xyyy
150:   MUL TEMP[13].xy, TEMP[13].xyyy, IMM[1].wwww
151:   MAD TEMP[12].xy, IMM[1].zzzz, TEMP[14].xxxx, TEMP[13].xyyy
152:   MUL TEMP[13].x, TEMP[5].xxxx, IMM[1].wwww
153:   MOV TEMP[14].x, TEMP[1].yyyy
154:   MOV TEMP[14].y, TEMP[0].yyyy
155:   RCP TEMP[15].x, TEMP[5].xxxx
156:   FRC TEMP[16].xy, TEMP[4].xyyy
157:   ADD TEMP[17].x, TEMP[13].xxxx, IMM[3].zzzz
158:   RCP TEMP[18].x, TEMP[13].xxxx
159:   MUL TEMP[17].x, TEMP[17].xxxx, TEMP[18].xxxx
160:   MAD TEMP[14].xy, TEMP[16].xyyy, TEMP[17].xxxx, TEMP[14].xyyy
161:   MUL TEMP[14].xy, TEMP[14].xyyy, IMM[1].wwww
162:   MAD TEMP[13].xy, IMM[1].zzzz, TEMP[15].xxxx, TEMP[14].xyyy
163:   MUL TEMP[14].x, TEMP[5].xxxx, IMM[1].wwww
164:   MOV TEMP[1].x, TEMP[1].zzzz
165:   MOV TEMP[1].y, TEMP[0].zzzz
166:   RCP TEMP[5].x, TEMP[5].xxxx
167:   FRC TEMP[4].xy, TEMP[4].xyyy
168:   ADD TEMP[15].x, TEMP[14].xxxx, IMM[3].zzzz
169:   RCP TEMP[14].x, TEMP[14].xxxx
170:   MUL TEMP[14].x, TEMP[15].xxxx, TEMP[14].xxxx
171:   MAD TEMP[4].xy, TEMP[4].xyyy, TEMP[14].xxxx, TEMP[1].xyyy
172:   MUL TEMP[4].xy, TEMP[4].xyyy, IMM[1].wwww
173:   MAD TEMP[1].xy, IMM[1].zzzz, TEMP[5].xxxx, TEMP[4].xyyy
174:   MAD TEMP[4].x, IN[0].xxxx, CONST[16].xxxx, IMM[0].zzzz
175:   MAD TEMP[5].x, IN[0].yyyy, CONST[16].yyyy, IMM[0].zzzz
176:   MOV TEMP[4].y, TEMP[5].xxxx
177:   FRC TEMP[4].xy, TEMP[4].xyyy
178:   MUL TEMP[5].x, TEMP[4].xxxx, TEMP[10].wwww
179:   MAD TEMP[5].x, TEMP[5].xxxx, IMM[4].yyyy, TEMP[4].xxxx
180:   ADD TEMP[14].x, IMM[3].wwww, -TEMP[4].xxxx
181:   MUL TEMP[14].x, TEMP[14].xxxx, TEMP[11].wwww
182:   ADD TEMP[15].x, IMM[3].wwww, -TEMP[4].xxxx
183:   MAD TEMP[14].x, TEMP[14].xxxx, IMM[4].yyyy, TEMP[15].xxxx
184:   MUL TEMP[15].x, TEMP[4].xxxx, TEMP[7].wwww
185:   MAD TEMP[15].x, TEMP[15].xxxx, IMM[4].yyyy, TEMP[4].xxxx
186:   ADD TEMP[16].x, IMM[3].wwww, -TEMP[4].xxxx
187:   MUL TEMP[16].x, TEMP[16].xxxx, TEMP[2].wwww
188:   ADD TEMP[17].x, IMM[3].wwww, -TEMP[4].xxxx
189:   MAD TEMP[16].x, TEMP[16].xxxx, IMM[4].yyyy, TEMP[17].xxxx
190:   ADD TEMP[17].x, TEMP[5].xxxx, TEMP[14].xxxx
191:   MUL TEMP[17].x, TEMP[17].xxxx, TEMP[4].yyyy
192:   ADD TEMP[18].x, TEMP[15].xxxx, TEMP[16].xxxx
193:   ADD TEMP[4].x, IMM[3].wwww, -TEMP[4].yyyy
194:   MUL TEMP[4].x, TEMP[18].xxxx, TEMP[4].xxxx
195:   ADD TEMP[14].x, TEMP[5].xxxx, TEMP[14].xxxx
196:   RCP TEMP[14].x, TEMP[14].xxxx
197:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[14].xxxx
198:   ADD TEMP[14].x, TEMP[15].xxxx, TEMP[16].xxxx
199:   RCP TEMP[14].x, TEMP[14].xxxx
200:   MUL TEMP[14].x, TEMP[15].xxxx, TEMP[14].xxxx
201:   ADD TEMP[4].x, TEMP[17].xxxx, TEMP[4].xxxx
202:   RCP TEMP[4].x, TEMP[4].xxxx
203:   MUL TEMP[4].x, TEMP[17].xxxx, TEMP[4].xxxx
204:   LRP TEMP[10], TEMP[5].xxxx, TEMP[10], TEMP[11]
205:   LRP TEMP[2], TEMP[14].xxxx, TEMP[7], TEMP[2]
206:   LRP TEMP[8].xyz, TEMP[4].xxxx, TEMP[2], TEMP[10]
207:   MOV TEMP[2].xy, TEMP[12].xyyy
208:   MOV TEMP[2].w, TEMP[3].xxxx
209:   TXL TEMP[2].xyz, TEMP[2], SAMP[0], 2D
210:   ADD TEMP[2].xyz, TEMP[2].xzyy, IMM[0].zzzz
211:   ADD TEMP[7].x, IMM[3].wwww, -TEMP[14].xxxx
212:   MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[7].xxxx
213:   MAD TEMP[2].xyz, TEMP[9].xyzz, TEMP[14].xxxx, TEMP[2].xyzz
214:   MOV TEMP[7].xy, TEMP[13].xyyy
215:   MOV TEMP[7].w, TEMP[3].xxxx
216:   TXL TEMP[7].xyz, TEMP[7], SAMP[0], 2D
217:   ADD TEMP[7].xyz, TEMP[7].xzyy, IMM[0].zzzz
218:   MOV TEMP[1].xy, TEMP[1].xyyy
219:   MOV TEMP[1].w, TEMP[3].xxxx
220:   TXL TEMP[1].xyz, TEMP[1], SAMP[0], 2D
221:   ADD TEMP[1].xyz, TEMP[1].xzyy, IMM[0].zzzz
222:   ADD TEMP[3].x, IMM[3].wwww, -TEMP[5].xxxx
223:   MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[3].xxxx
224:   MAD TEMP[1].xyz, TEMP[7].xyzz, TEMP[5].xxxx, TEMP[1].xyzz
225:   ADD TEMP[3].x, IMM[3].wwww, -TEMP[4].xxxx
226:   MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[3].xxxx
227:   MAD TEMP[9].xyz, TEMP[2].xyzz, TEMP[4].xxxx, TEMP[1].xyzz
228: ENDIF
229: DP3 TEMP[1].x, TEMP[9].xyzz, TEMP[9].xyzz
230: RSQ TEMP[1].x, TEMP[1].xxxx
231: MUL TEMP[1].xyz, TEMP[9].xyzz, TEMP[1].xxxx
232: MUL TEMP[2].xyz, TEMP[6].yxzz, TEMP[1].xxxx
233: MAD TEMP[2].xyz, TEMP[6].xyzz, TEMP[1].yyyy, TEMP[2].xyzz
234: MAD TEMP[0].xyz, TEMP[6].xzyy, TEMP[1].zzzz, TEMP[2].xyzz
235: MUL TEMP[1].xy, IN[0].zwww, CONST[16].zwww
236: MOV TEMP[1].xy, TEMP[1].xyyy
237: TEX TEMP[1].xyz, TEMP[1], SAMP[3], 2D
238: FSLT TEMP[2].x, TEMP[1].xxxx, IMM[1].zzzz
239: UIF TEMP[2].xxxx :0
240:   MUL TEMP[2].x, IMM[3].xxxx, TEMP[1].xxxx
241:   MUL TEMP[2].x, TEMP[2].xxxx, TEMP[8].xxxx
242: ELSE :0
243:   ADD TEMP[3].x, IMM[3].wwww, -TEMP[1].xxxx
244:   MUL TEMP[3].x, IMM[3].xxxx, TEMP[3].xxxx
245:   ADD TEMP[4].x, IMM[3].wwww, -TEMP[8].xxxx
246:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
247:   ADD TEMP[2].x, IMM[3].wwww, -TEMP[3].xxxx
248: ENDIF
249: MOV TEMP[2].x, TEMP[2].xxxx
250: FSLT TEMP[3].x, TEMP[1].yyyy, IMM[1].zzzz
251: UIF TEMP[3].xxxx :0
252:   MUL TEMP[3].x, IMM[3].xxxx, TEMP[1].yyyy
253:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[8].yyyy
254: ELSE :0
255:   ADD TEMP[4].x, IMM[3].wwww, -TEMP[1].yyyy
256:   MUL TEMP[4].x, IMM[3].xxxx, TEMP[4].xxxx
257:   ADD TEMP[5].x, IMM[3].wwww, -TEMP[8].yyyy
258:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
259:   ADD TEMP[3].x, IMM[3].wwww, -TEMP[4].xxxx
260: ENDIF
261: MOV TEMP[2].y, TEMP[3].xxxx
262: FSLT TEMP[3].x, TEMP[1].zzzz, IMM[1].zzzz
263: UIF TEMP[3].xxxx :0
264:   MUL TEMP[3].x, IMM[3].xxxx, TEMP[1].zzzz
265:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[8].zzzz
266: ELSE :0
267:   ADD TEMP[1].x, IMM[3].wwww, -TEMP[1].zzzz
268:   MUL TEMP[1].x, IMM[3].xxxx, TEMP[1].xxxx
269:   ADD TEMP[4].x, IMM[3].wwww, -TEMP[8].zzzz
270:   MUL TEMP[1].x, TEMP[1].xxxx, TEMP[4].xxxx
271:   ADD TEMP[3].x, IMM[3].wwww, -TEMP[1].xxxx
272: ENDIF
273: MOV TEMP[2].z, TEMP[3].xxxx
274: LRP TEMP[8].xyz, IMM[1].zzzz, TEMP[2].xyzz, TEMP[8].xyzz
275: MOV TEMP[1].xy, IN[0].xyyy
276: TEX TEMP[1].xyz, TEMP[1], SAMP[8], 2D
277: MOV TEMP[2].xy, IN[0].xyyy
278: TEX TEMP[2].w, TEMP[2], SAMP[1], 2D
279: MUL TEMP[1].xyz, TEMP[1].xyzz, IMM[0].wwww
280: MUL TEMP[3].xyz, TEMP[1].xyzz, IMM[4].zzzz
281: F2I TEMP[3].xyz, TEMP[3].xyzz
282: UMUL TEMP[4].xyz, TEMP[3].xyzz, IMM[6].xxxx
283: I2F TEMP[4].xyz, TEMP[4].xyzz
284: ADD TEMP[1].xyz, TEMP[1].xyzz, -TEMP[4].xyzz
285: MUL TEMP[4].xyz, TEMP[1].xyzz, IMM[4].wwww
286: F2I TEMP[4].xyz, TEMP[4].xyzz
287: UMUL TEMP[5].xyz, TEMP[4].xyzz, IMM[6].yyyy
288: I2F TEMP[5].xyz, TEMP[5].xyzz
289: ADD TEMP[1].xyz, TEMP[1].xyzz, -TEMP[5].xyzz
290: F2I TEMP[1].xyz, TEMP[1].xyzz
291: MUL TEMP[5].xy, IN[1].xzzz, IMM[7].xxxx
292: MOV TEMP[5].xy, TEMP[5].xyyy
293: TEX TEMP[5], TEMP[5], SAMP[4], 2D
294: I2F TEMP[6].x, TEMP[3].xxxx
295: I2F TEMP[7].x, TEMP[4].xxxx
296: MOV TEMP[6].y, TEMP[7].xxxx
297: I2F TEMP[7].x, TEMP[1].xxxx
298: MOV TEMP[6].z, TEMP[7].xxxx
299: I2F TEMP[7].x, TEMP[3].yyyy
300: I2F TEMP[9].x, TEMP[4].yyyy
301: MOV TEMP[7].y, TEMP[9].xxxx
302: I2F TEMP[9].x, TEMP[1].yyyy
303: MOV TEMP[7].z, TEMP[9].xxxx
304: I2F TEMP[3].x, TEMP[3].zzzz
305: I2F TEMP[4].x, TEMP[4].zzzz
306: MOV TEMP[3].y, TEMP[4].xxxx
307: I2F TEMP[1].x, TEMP[1].zzzz
308: MOV TEMP[3].z, TEMP[1].xxxx
309: MUL TEMP[1].x, IN[1].xxxx, IMM[1].zzzz
310: FRC TEMP[1].x, TEMP[1].xxxx
311: ADD_SAT TEMP[1].x, TEMP[1].xxxx, IMM[7].yyyy
312: MUL_SAT TEMP[1].x, TEMP[1].xxxx, IMM[7].zzzz
313: MUL TEMP[1].x, IMM[1].zzzz, TEMP[1].xxxx
314: ADD TEMP[1].x, TEMP[2].wwww, -TEMP[1].xxxx
315: MOV_SAT TEMP[1].x, TEMP[1].xxxx
316: MUL_SAT TEMP[1].x, TEMP[1].xxxx, IMM[7].wwww
317: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[5].wwww
318: MUL TEMP[2].xyz, TEMP[6].xyzz, TEMP[5].xxxx
319: MAD TEMP[2].xyz, TEMP[7].xyzz, TEMP[5].yyyy, TEMP[2].xyzz
320: MAD TEMP[2].xyz, TEMP[3].xyzz, TEMP[5].zzzz, TEMP[2].xyzz
321: MUL TEMP[2].xyz, TEMP[2].xyzz, IMM[4].wwww
322: ADD TEMP[3].x, IMM[3].wwww, -TEMP[1].xxxx
323: MUL TEMP[3].xyz, TEMP[8].xyzz, TEMP[3].xxxx
324: MAD TEMP[8].xyz, TEMP[2].xyzz, TEMP[1].xxxx, TEMP[3].xyzz
325: DP3 TEMP[0].x, TEMP[0].xyzz, -CONST[17].xyzz
326: MAD TEMP[0].x, TEMP[0].xxxx, IMM[1].zzzz, IMM[1].zzzz
327: ADD TEMP[1].xyz, CONST[18].xyzz, -IN[1].xyzz
328: ADD TEMP[2].x, IN[1].xxxx, IMM[1].zzzz
329: RCP TEMP[3].x, CONST[16].xxxx
330: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
331: ADD TEMP[3].x, IN[1].zzzz, IMM[1].zzzz
332: RCP TEMP[4].x, CONST[16].yyyy
333: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
334: MOV TEMP[2].y, TEMP[3].xxxx
335: MOV TEMP[3].w, IMM[3].wwww
336: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx
337: MAD TEMP[0].x, IMM[8].xxxx, TEMP[0].xxxx, IMM[8].yyyy
338: MUL TEMP[0].xyz, TEMP[0].xxxx, TEMP[8].xyzz
339: MUL_SAT TEMP[0].xyz, TEMP[0].xyzz, IMM[8].zzzz
340: DP3 TEMP[4].x, TEMP[1].xyzz, TEMP[1].xyzz
341: ADD TEMP[4].x, TEMP[4].xxxx, IMM[8].wwww
342: MUL TEMP[4].x, TEMP[4].xxxx, IMM[9].xxxx
343: MIN TEMP[4].x, TEMP[4].xxxx, IMM[1].zzzz
344: MOV_SAT TEMP[4].x, TEMP[4].xxxx
345: DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[1].xyzz
346: RSQ TEMP[5].x, TEMP[5].xxxx
347: MUL TEMP[1].y, TEMP[1].xyzz, TEMP[5].xxxx
348: ADD TEMP[1].x, IMM[3].wwww, -TEMP[1].yyyy
349: MUL TEMP[1].x, TEMP[4].xxxx, TEMP[1].xxxx
350: LRP TEMP[0].xyz, TEMP[1].xxxx, IMM[1].zzzz, TEMP[0].xyzz
351: MOV TEMP[1].xy, TEMP[2].xyyy
352: TEX TEMP[1].w, TEMP[1], SAMP[9], 2D
353: ADD TEMP[2].xy, IN[1].xzzz, IMM[1].zzzz
354: MUL TEMP[2].xy, TEMP[2].xyyy, IMM[9].zzzz
355: MAD TEMP[2].xy, CONST[22].yyyy, IMM[9].yyyy, TEMP[2].xyyy
356: MOV TEMP[2].xy, TEMP[2].xyyy
357: TEX TEMP[2].x, TEMP[2], SAMP[6], 2D
358: MUL TEMP[4].x, CONST[22].yyyy, IMM[9].wwww
359: FRC TEMP[4].x, TEMP[4].xxxx
360: ADD TEMP[2].x, TEMP[2].xxxx, TEMP[4].xxxx
361: MUL TEMP[2].x, TEMP[2].xxxx, IMM[10].xxxx
362: SIN TEMP[2].x, TEMP[2].xxxx
363: MAD TEMP[2].x, TEMP[2].xxxx, IMM[9].wwww, IMM[1].zzzz
364: ADD_SAT TEMP[1].x, TEMP[1].wwww, TEMP[2].xxxx
365: LRP TEMP[1].x, CONST[22].xxxx, TEMP[1].xxxx, IMM[3].wwww
366: MUL_SAT TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx
367: MOV TEMP[3].xyz, TEMP[0].xyzx
368: MOV OUT[0], TEMP[3]
369: END
warning: failed to translate tgsi opcode DDX to LLVM
Failed to translate shader from TGSI to LLVM
EE si_state.c:2404 si_shader_select - Failed to build shader variant (type=1) -22
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..25]
DCL TEMP[0..5], LOCAL
IMM[0] FLT32 {   -1.0000,     1.0000,     0.5000,     0.0100}
IMM[1] INT32 {0, 1, 2, 3}
  0: MAD TEMP[0].xy, IN[0].xyyy, CONST[23].zzzz, CONST[23].xyyy
  1: ADD TEMP[1].x, IN[0].zzzz, IMM[0].xxxx
  2: F2I TEMP[1].x, TEMP[1].xxxx
  3: USEQ TEMP[1].yzw, TEMP[1].xxxx, IMM[1]
  4: I2F TEMP[2].y, TEMP[1].yyyy
  5: CMP TEMP[2].x, TEMP[2].yyyy, CONST[24].yyyy, CONST[24].xxxx
  6: I2F TEMP[3].z, TEMP[1].zzzz
  7: CMP TEMP[2].x, TEMP[3].zzzz, CONST[24].zzzz, TEMP[2].xxxx
  8: I2F TEMP[1].w, TEMP[1].wwww
  9: CMP TEMP[2].x, TEMP[1].wwww, CONST[24].wwww, TEMP[2].xxxx
 10: MOV_SAT TEMP[1].x, IN[0].zzzz
 11: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
 12: ADD TEMP[2].x, IMM[0].yyyy, -IN[0].wwww
 13: MOV TEMP[2].y, IN[0].wwww
 14: MUL TEMP[2].xy, TEMP[1].xxxx, TEMP[2].xyyy
 15: MAD TEMP[0].xy, TEMP[2].xyyy, CONST[23].zzzz, TEMP[0].xyyy
 16: ADD TEMP[2].x, TEMP[0].xxxx, IMM[0].zzzz
 17: RCP TEMP[3].x, CONST[16].xxxx
 18: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
 19: ADD TEMP[3].x, TEMP[0].yyyy, IMM[0].zzzz
 20: RCP TEMP[4].x, CONST[16].yyyy
 21: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 22: MOV TEMP[2].y, TEMP[3].xxxx
 23: ADD TEMP[3].x, TEMP[0].xxxx, IMM[0].zzzz
 24: RCP TEMP[4].x, CONST[16].xxxx
 25: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 26: ADD TEMP[4].x, TEMP[0].yyyy, IMM[0].zzzz
 27: ADD TEMP[4].x, TEMP[4].xxxx, -CONST[16].yyyy
 28: RCP TEMP[5].x, -CONST[16].yyyy
 29: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 30: MOV TEMP[3].y, TEMP[4].xxxx
 31: MOV TEMP[4].x, TEMP[0].xxxx
 32: ADD TEMP[5].x, IMM[0].yyyy, -TEMP[1].xxxx
 33: MUL TEMP[5].x, IN[1].xxxx, TEMP[5].xxxx
 34: MAD TEMP[1].x, IN[1].yyyy, TEMP[1].xxxx, TEMP[5].xxxx
 35: MUL TEMP[1].x, TEMP[1].xxxx, IMM[0].wwww
 36: MOV TEMP[4].y, TEMP[1].xxxx
 37: MOV TEMP[4].z, TEMP[0].yyyy
 38: MOV TEMP[5].w, IMM[0].yyyy
 39: MOV TEMP[5].x, TEMP[0].xxxx
 40: MOV TEMP[5].y, TEMP[1].xxxx
 41: MOV TEMP[5].z, TEMP[0].yyyy
 42: DP4 TEMP[0].x, TEMP[5], CONST[0]
 43: DP4 TEMP[1].x, TEMP[5], CONST[1]
 44: MOV TEMP[0].y, TEMP[1].xxxx
 45: DP4 TEMP[1].x, TEMP[5], CONST[2]
 46: MOV TEMP[0].z, TEMP[1].xxxx
 47: DP4 TEMP[1].x, TEMP[5], CONST[3]
 48: MOV TEMP[0].w, TEMP[1].xxxx
 49: MOV TEMP[1].xy, TEMP[2].xyxx
 50: MOV TEMP[1].zw, TEMP[3].yyxy
 51: MOV TEMP[2].xyz, TEMP[4].xyzx
 52: MOV OUT[2], TEMP[2]
 53: MOV OUT[0], TEMP[0]
 54: MOV OUT[1], TEMP[1]
 55: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
  %36 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
  %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %37, i32 0, i32 %5)
  %39 = extractelement <4 x float> %38, i32 0
  %40 = extractelement <4 x float> %38, i32 1
  %41 = extractelement <4 x float> %38, i32 2
  %42 = extractelement <4 x float> %38, i32 3
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = fmul float %39, %31
  %49 = fadd float %48, %29
  %50 = fmul float %40, %31
  %51 = fadd float %50, %30
  %52 = fadd float %41, -1.000000e+00
  %53 = fptosi float %52 to i32
  %54 = bitcast i32 %53 to float
  %55 = bitcast float %54 to i32
  %56 = icmp eq i32 %55, 1
  %57 = sext i1 %56 to i32
  %58 = bitcast float %54 to i32
  %59 = icmp eq i32 %58, 2
  %60 = sext i1 %59 to i32
  %61 = bitcast float %54 to i32
  %62 = icmp eq i32 %61, 3
  %63 = sext i1 %62 to i32
  %64 = bitcast i32 %57 to float
  %65 = bitcast i32 %60 to float
  %66 = bitcast i32 %63 to float
  %67 = bitcast float %64 to i32
  %68 = sitofp i32 %67 to float
  %69 = call float @llvm.AMDGPU.cndlt(float %68, float %33, float %32)
  %70 = bitcast float %65 to i32
  %71 = sitofp i32 %70 to float
  %72 = call float @llvm.AMDGPU.cndlt(float %71, float %34, float %69)
  %73 = bitcast float %66 to i32
  %74 = sitofp i32 %73 to float
  %75 = call float @llvm.AMDGPU.cndlt(float %74, float %35, float %72)
  %76 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
  %77 = fmul float %76, %75
  %78 = fsub float -0.000000e+00, %42
  %79 = fadd float 1.000000e+00, %78
  %80 = fmul float %77, %79
  %81 = fmul float %77, %42
  %82 = fmul float %80, %31
  %83 = fadd float %82, %49
  %84 = fmul float %81, %31
  %85 = fadd float %84, %51
  %86 = fadd float %83, 5.000000e-01
  %87 = fdiv float 1.000000e+00, %27
  %88 = fmul float %86, %87
  %89 = fadd float %85, 5.000000e-01
  %90 = fdiv float 1.000000e+00, %28
  %91 = fmul float %89, %90
  %92 = fadd float %83, 5.000000e-01
  %93 = fdiv float 1.000000e+00, %27
  %94 = fmul float %92, %93
  %95 = fadd float %85, 5.000000e-01
  %96 = fsub float -0.000000e+00, %28
  %97 = fadd float %95, %96
  %98 = fsub float -0.000000e+00, %28
  %99 = fdiv float 1.000000e+00, %98
  %100 = fmul float %97, %99
  %101 = fsub float -0.000000e+00, %77
  %102 = fadd float 1.000000e+00, %101
  %103 = fmul float %46, %102
  %104 = fmul float %47, %77
  %105 = fadd float %104, %103
  %106 = fmul float %105, 0x3F847AE140000000
  %107 = fmul float %83, %11
  %108 = fmul float %106, %12
  %109 = fadd float %107, %108
  %110 = fmul float %85, %13
  %111 = fadd float %109, %110
  %112 = fmul float 1.000000e+00, %14
  %113 = fadd float %111, %112
  %114 = fmul float %83, %15
  %115 = fmul float %106, %16
  %116 = fadd float %114, %115
  %117 = fmul float %85, %17
  %118 = fadd float %116, %117
  %119 = fmul float 1.000000e+00, %18
  %120 = fadd float %118, %119
  %121 = fmul float %83, %19
  %122 = fmul float %106, %20
  %123 = fadd float %121, %122
  %124 = fmul float %85, %21
  %125 = fadd float %123, %124
  %126 = fmul float 1.000000e+00, %22
  %127 = fadd float %125, %126
  %128 = fmul float %83, %23
  %129 = fmul float %106, %24
  %130 = fadd float %128, %129
  %131 = fmul float %85, %25
  %132 = fadd float %130, %131
  %133 = fmul float 1.000000e+00, %26
  %134 = fadd float %132, %133
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %88, float %91, float %94, float %100)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %83, float %106, float %85, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %113, float %120, float %127, float %134)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.cndlt(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840700
bf8c007f
e00c2000
80020200
bf8c0770
060208f3
7e021101
d1040002
02010301
d2000006
00098280
7e0c0b06
d0080004
02020c80
c0800100
bf8c007f
c2040161
bf8c007f
7e0c0208
c2040160
bf8c007f
7e0e0208
d2000006
00120d07
d1040004
02010501
d2000007
00118280
7e0e0b07
d0080004
02020e80
c2040162
bf8c007f
7e0e0208
d2000006
00120f06
d1040004
02010701
d2000001
00118280
7e020b01
d0080004
02020280
c2040163
bf8c007f
7e020208
d2000001
00120306
d2060806
02010104
100c0306
10020b06
c202015e
c202815d
bf8c007f
7e0e0205
d2820007
041c0903
d2820001
041c0901
061002f0
c2028141
bf8c007f
7e0e5405
100e0f08
08120af2
10121306
c204015c
bf8c007f
7e140208
d2820002
04280902
d2820002
04080909
060604f0
c2020140
bf8c007f
7e085404
10060903
0a081005
d2060005
22010005
7e0a5505
10080b04
f800020f
04030703
bf8c070f
08060cf2
c0820704
bf8c007f
e00c2000
80010700
bf8c0770
10000707
d2820000
04020d08
100000ff
3c23d70a
7e060280
f800021f
03010002
c202010d
bf8c000f
10060004
c202010c
bf8c007f
d2820003
040c0902
c202010e
bf8c007f
d2820003
040c0901
c202010f
bf8c007f
06060604
c2020109
bf8c007f
10080004
c2020108
bf8c007f
d2820004
04100902
c202010a
bf8c007f
d2820004
04100901
c202010b
bf8c007f
06080804
c2020105
bf8c007f
100a0004
c2020104
bf8c007f
d2820005
04140902
c2020106
bf8c007f
d2820005
04140901
c2020107
bf8c007f
060a0a04
c2020101
bf8c007f
10000004
c2020100
bf8c007f
d2820000
04000902
c2020102
bf8c007f
d2820000
04000901
c2000103
bf8c007f
06000000
f80008cf
03040500
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL IN[3], GENERIC[22], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL SAMP[4]
DCL SAMP[5]
DCL SAMP[6]
DCL SAMP[7]
DCL CONST[0..22]
DCL TEMP[0..9], LOCAL
IMM[0] FLT32 {   -0.5000,    70.0000,     0.2500,     1.0000}
IMM[1] FLT32 {    0.5000,     2.0000,     0.4356,     0.0000}
IMM[2] FLT32 {    0.6600,     0.0500,     0.0200,     0.0039}
IMM[3] FLT32 {    0.1000,     6.2832,     0.8000,     0.2000}
IMM[4] FLT32 {    1.2000, -160000.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xwww
  1: TEX TEMP[0], TEMP[0], SAMP[2], 2D
  2: MUL TEMP[1].xy, IN[1].xyyy, CONST[16].zwww
  3: MOV TEMP[1].xy, TEMP[1].xyyy
  4: TEX TEMP[1].xyz, TEMP[1], SAMP[6], 2D
  5: ADD TEMP[1].xyz, TEMP[1].xzyy, IMM[0].xxxx
  6: DP3 TEMP[2].x, TEMP[1].xyzz, TEMP[1].xyzz
  7: RSQ TEMP[2].x, TEMP[2].xxxx
  8: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xxxx
  9: MOV TEMP[2].xy, IN[0].xyyy
 10: TEX TEMP[2].xyz, TEMP[2], SAMP[0], 2D
 11: ADD TEMP[2].xyz, TEMP[2].xyzz, IMM[0].xxxx
 12: MOV TEMP[3].xy, IN[3].xyyy
 13: TEX TEMP[3].xyz, TEMP[3], SAMP[0], 2D
 14: ADD TEMP[3].xyz, TEMP[3].xyzz, IMM[0].xxxx
 15: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[3].xyzz
 16: RSQ TEMP[4].x, TEMP[4].xxxx
 17: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[2].xyzz
 18: RSQ TEMP[5].x, TEMP[5].xxxx
 19: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[5].xxxx
 20: MAD TEMP[2].xyz, TEMP[3].xyzz, TEMP[4].xxxx, TEMP[2].xyzz
 21: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
 22: RSQ TEMP[3].x, TEMP[3].xxxx
 23: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx
 24: MOV TEMP[3].x, -IN[1].wwww
 25: MOV TEMP[3].y, IN[1].zzzz
 26: MUL TEMP[4].xy, TEMP[2].xxxx, IN[1].zwww
 27: MAD TEMP[3].xy, TEMP[2].yyyy, TEMP[3].xyyy, TEMP[4].xyyy
 28: MUL TEMP[4].xyz, TEMP[1].yxzz, TEMP[3].xxxx
 29: MAD TEMP[2].xyz, TEMP[1].xyzz, TEMP[2].zzzz, TEMP[4].xyzz
 30: MAD TEMP[2].xyz, TEMP[1].xzyy, TEMP[3].yyyy, TEMP[2].xyzz
 31: ADD TEMP[3].xyz, IN[2].xyzz, -CONST[18].xyzz
 32: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[3].xyzz
 33: RSQ TEMP[4].x, TEMP[4].xxxx
 34: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
 35: ADD TEMP[3].xyz, -CONST[17].xyzz, -TEMP[3].xyzz
 36: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[3].xyzz
 37: RSQ TEMP[4].x, TEMP[4].xxxx
 38: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
 39: DP3_SAT TEMP[3].x, TEMP[3].xyzz, TEMP[2].xyzz
 40: POW TEMP[3].x, TEMP[3].xxxx, IMM[0].yyyy
 41: MUL_SAT TEMP[3].x, TEMP[3].xxxx, IMM[0].zzzz
 42: ADD TEMP[4].x, IMM[1].xxxx, -IN[0].wwww
 43: ABS TEMP[4].x, TEMP[4].xxxx
 44: MUL TEMP[4].x, TEMP[4].xxxx, IMM[1].yyyy
 45: ADD TEMP[4].x, IMM[0].wwww, -TEMP[4].xxxx
 46: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 47: DP3 TEMP[4].x, TEMP[2].xyzz, CONST[20].xyzz
 48: DP3 TEMP[5].x, TEMP[2].xyzz, CONST[20].xyzz
 49: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 50: ADD TEMP[4].x, IMM[0].wwww, -TEMP[4].xxxx
 51: MUL TEMP[4].x, TEMP[4].xxxx, IMM[1].zzzz
 52: ADD TEMP[4].x, IMM[0].wwww, -TEMP[4].xxxx
 53: FSLT TEMP[5].x, TEMP[4].xxxx, IMM[1].wwww
 54: UIF TEMP[5].xxxx :0
 55:   MOV TEMP[5].xz, IMM[1].wwww
 56: ELSE :0
 57:   DP3 TEMP[6].x, TEMP[2].xyzz, CONST[20].xyzz
 58:   RSQ TEMP[7].x, TEMP[4].xxxx
 59:   MUL TEMP[7].x, TEMP[7].xxxx, TEMP[4].xxxx
 60:   CMP TEMP[7].x, -TEMP[4].xxxx, TEMP[7].xxxx, IMM[1].wwww
 61:   MAD TEMP[4].x, IMM[2].xxxx, TEMP[6].xxxx, TEMP[7].xxxx
 62:   MUL TEMP[2].xyz, TEMP[4].xxxx, TEMP[2].xyzz
 63:   MAD TEMP[5].xz, IMM[2].xxxx, CONST[20].xyzz, -TEMP[2].xyzz
 64: ENDIF
 65: MOV TEMP[2].x, -IN[1].wwww
 66: MOV TEMP[2].y, IN[1].zzzz
 67: MUL TEMP[4].xy, TEMP[5].xxxx, IN[1].zwww
 68: MAD TEMP[2].xy, TEMP[5].zzzz, TEMP[2].xyyy, TEMP[4].xyyy
 69: MAD TEMP[2].xy, TEMP[2].xyyy, IMM[2].yyyy, IN[0].zwww
 70: MOV TEMP[2].xy, TEMP[2].xyyy
 71: TEX TEMP[2].xyz, TEMP[2], SAMP[7], 2D
 72: MOV TEMP[4].xy, IN[0].zwww
 73: TEX TEMP[4].w, TEMP[4], SAMP[7], 2D
 74: MOV TEMP[5].xy, IN[1].xyyy
 75: TEX TEMP[5].xyz, TEMP[5], SAMP[4], 2D
 76: FSLT TEMP[6].x, TEMP[5].xxxx, IMM[1].xxxx
 77: UIF TEMP[6].xxxx :0
 78:   MUL TEMP[6].x, IMM[1].yyyy, TEMP[5].xxxx
 79:   MUL TEMP[6].x, TEMP[6].xxxx, TEMP[2].xxxx
 80: ELSE :0
 81:   ADD TEMP[7].x, IMM[0].wwww, -TEMP[5].xxxx
 82:   MUL TEMP[7].x, IMM[1].yyyy, TEMP[7].xxxx
 83:   ADD TEMP[8].x, IMM[0].wwww, -TEMP[2].xxxx
 84:   MUL TEMP[7].x, TEMP[7].xxxx, TEMP[8].xxxx
 85:   ADD TEMP[6].x, IMM[0].wwww, -TEMP[7].xxxx
 86: ENDIF
 87: MOV TEMP[6].x, TEMP[6].xxxx
 88: FSLT TEMP[7].x, TEMP[5].yyyy, IMM[1].xxxx
 89: UIF TEMP[7].xxxx :0
 90:   MUL TEMP[7].x, IMM[1].yyyy, TEMP[5].yyyy
 91:   MUL TEMP[7].x, TEMP[7].xxxx, TEMP[2].yyyy
 92: ELSE :0
 93:   ADD TEMP[8].x, IMM[0].wwww, -TEMP[5].yyyy
 94:   MUL TEMP[8].x, IMM[1].yyyy, TEMP[8].xxxx
 95:   ADD TEMP[9].x, IMM[0].wwww, -TEMP[2].yyyy
 96:   MUL TEMP[8].x, TEMP[8].xxxx, TEMP[9].xxxx
 97:   ADD TEMP[7].x, IMM[0].wwww, -TEMP[8].xxxx
 98: ENDIF
 99: MOV TEMP[6].y, TEMP[7].xxxx
100: FSLT TEMP[7].x, TEMP[5].zzzz, IMM[1].xxxx
101: UIF TEMP[7].xxxx :0
102:   MUL TEMP[7].x, IMM[1].yyyy, TEMP[5].zzzz
103:   MUL TEMP[7].x, TEMP[7].xxxx, TEMP[2].zzzz
104: ELSE :0
105:   ADD TEMP[5].x, IMM[0].wwww, -TEMP[5].zzzz
106:   MUL TEMP[5].x, IMM[1].yyyy, TEMP[5].xxxx
107:   ADD TEMP[8].x, IMM[0].wwww, -TEMP[2].zzzz
108:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[8].xxxx
109:   ADD TEMP[7].x, IMM[0].wwww, -TEMP[5].xxxx
110: ENDIF
111: MOV TEMP[6].z, TEMP[7].xxxx
112: MOV TEMP[5].xy, IN[0].zwww
113: TEX TEMP[5].xyz, TEMP[5], SAMP[1], 2D
114: ADD TEMP[5].xyz, TEMP[5].xyzz, IMM[0].xxxx
115: DP3 TEMP[7].x, TEMP[5].xyzz, TEMP[5].xyzz
116: RSQ TEMP[7].x, TEMP[7].xxxx
117: MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[7].xxxx
118: MOV TEMP[7].x, -IN[1].wwww
119: MOV TEMP[7].y, IN[1].zzzz
120: MUL TEMP[8].xy, TEMP[5].xxxx, IN[1].zwww
121: MAD TEMP[7].xy, TEMP[5].yyyy, TEMP[7].xyyy, TEMP[8].xyyy
122: MUL TEMP[8].xyz, TEMP[1].yxzz, TEMP[7].xxxx
123: MAD TEMP[5].xyz, TEMP[1].xyzz, TEMP[5].zzzz, TEMP[8].xyzz
124: MAD TEMP[1].xyz, TEMP[1].xzyy, TEMP[7].yyyy, TEMP[5].xyzz
125: DP3 TEMP[1].x, TEMP[1].xyzz, -CONST[17].xyzz
126: MAD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx, IMM[1].xxxx
127: ADD TEMP[5].x, IN[2].xxxx, IMM[1].xxxx
128: RCP TEMP[7].x, CONST[16].xxxx
129: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[7].xxxx
130: ADD TEMP[7].x, IN[2].zzzz, IMM[1].xxxx
131: RCP TEMP[8].x, CONST[16].yyyy
132: MUL TEMP[7].x, TEMP[7].xxxx, TEMP[8].xxxx
133: MOV TEMP[5].y, TEMP[7].xxxx
134: MOV TEMP[5].xy, TEMP[5].xyyy
135: TEX TEMP[5].w, TEMP[5], SAMP[3], 2D
136: ADD TEMP[7].xy, IN[2].xzzz, IMM[1].xxxx
137: MUL TEMP[7].xy, TEMP[7].xyyy, IMM[2].wwww
138: MAD TEMP[7].xy, CONST[22].yyyy, IMM[2].zzzz, TEMP[7].xyyy
139: MOV TEMP[7].xy, TEMP[7].xyyy
140: TEX TEMP[7].x, TEMP[7], SAMP[5], 2D
141: MUL TEMP[8].x, CONST[22].yyyy, IMM[3].xxxx
142: FRC TEMP[8].x, TEMP[8].xxxx
143: ADD TEMP[7].x, TEMP[7].xxxx, TEMP[8].xxxx
144: MUL TEMP[7].x, TEMP[7].xxxx, IMM[3].yyyy
145: SIN TEMP[7].x, TEMP[7].xxxx
146: MAD TEMP[7].x, TEMP[7].xxxx, IMM[3].xxxx, IMM[1].xxxx
147: ADD_SAT TEMP[5].x, TEMP[5].wwww, TEMP[7].xxxx
148: LRP TEMP[5].x, CONST[22].xxxx, TEMP[5].xxxx, IMM[0].wwww
149: ADD TEMP[7].xyz, CONST[18].xyzz, -IN[2].xyzz
150: ADD TEMP[8].x, IMM[0].wwww, -IN[2].wwww
151: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[8].xxxx
152: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[0].wwww
153: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
154: MAD TEMP[1].x, IMM[3].zzzz, TEMP[1].xxxx, IMM[3].wwww
155: LRP TEMP[2].xyz, IMM[1].xxxx, TEMP[6].xyzz, TEMP[2].xyzz
156: MUL TEMP[6].x, TEMP[0].wwww, IMM[3].zzzz
157: LRP TEMP[0].xyz, TEMP[6].xxxx, TEMP[0].xyzz, TEMP[2].xyzz
158: MUL TEMP[0].xyz, TEMP[1].xxxx, TEMP[0].xyzz
159: MUL_SAT TEMP[0].xyz, TEMP[0].xyzz, IMM[4].xxxx
160: DP3 TEMP[1].x, TEMP[7].xyzz, TEMP[7].xyzz
161: ADD TEMP[1].x, TEMP[1].xxxx, IMM[4].yyyy
162: MUL TEMP[1].x, TEMP[1].xxxx, IMM[4].zzzz
163: MIN TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx
164: MOV_SAT TEMP[1].x, TEMP[1].xxxx
165: DP3 TEMP[2].x, TEMP[7].xyzz, TEMP[7].xyzz
166: RSQ TEMP[2].x, TEMP[2].xxxx
167: MUL TEMP[2].y, TEMP[7].xyzz, TEMP[2].xxxx
168: ADD TEMP[2].x, IMM[0].wwww, -TEMP[2].yyyy
169: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
170: LRP TEMP[0].xyz, TEMP[1].xxxx, IMM[1].xxxx, TEMP[0].xyzz
171: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[5].xxxx
172: MAD_SAT TEMP[0].xyz, TEMP[3].xxxx, TEMP[5].xxxx, TEMP[0].xyzz
173: MOV TEMP[0].xyz, TEMP[0].xyzx
174: ADD TEMP[1].x, IMM[0].wwww, -IN[2].wwww
175: MUL TEMP[1].x, TEMP[4].wwww, TEMP[1].xxxx
176: MOV TEMP[0].w, TEMP[1].xxxx
177: MOV OUT[0], TEMP[0]
178: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 264)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 268)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 276)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 280)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 320)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 324)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 328)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %42 = load <32 x i8> addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %46 = load <32 x i8> addrspace(2)* %45, !tbaa !0
  %47 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %50 = load <32 x i8> addrspace(2)* %49, !tbaa !0
  %51 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
  %54 = load <32 x i8> addrspace(2)* %53, !tbaa !0
  %55 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
  %58 = load <32 x i8> addrspace(2)* %57, !tbaa !0
  %59 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
  %61 = getelementptr <32 x i8> addrspace(2)* %2, i32 6
  %62 = load <32 x i8> addrspace(2)* %61, !tbaa !0
  %63 = getelementptr <16 x i8> addrspace(2)* %1, i32 6
  %64 = load <16 x i8> addrspace(2)* %63, !tbaa !0
  %65 = getelementptr <32 x i8> addrspace(2)* %2, i32 7
  %66 = load <32 x i8> addrspace(2)* %65, !tbaa !0
  %67 = getelementptr <16 x i8> addrspace(2)* %1, i32 7
  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
  %69 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %70 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %71 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %72 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %73 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %74 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %75 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %76 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %77 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %78 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %79 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %80 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %81 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
  %82 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
  %83 = bitcast float %69 to i32
  %84 = bitcast float %72 to i32
  %85 = insertelement <2 x i32> undef, i32 %83, i32 0
  %86 = insertelement <2 x i32> %85, i32 %84, i32 1
  %87 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %86, <32 x i8> %46, <16 x i8> %48, i32 2)
  %88 = extractelement <4 x float> %87, i32 0
  %89 = extractelement <4 x float> %87, i32 1
  %90 = extractelement <4 x float> %87, i32 2
  %91 = extractelement <4 x float> %87, i32 3
  %92 = fmul float %73, %24
  %93 = fmul float %74, %25
  %94 = bitcast float %92 to i32
  %95 = bitcast float %93 to i32
  %96 = insertelement <2 x i32> undef, i32 %94, i32 0
  %97 = insertelement <2 x i32> %96, i32 %95, i32 1
  %98 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %97, <32 x i8> %62, <16 x i8> %64, i32 2)
  %99 = extractelement <4 x float> %98, i32 0
  %100 = extractelement <4 x float> %98, i32 1
  %101 = extractelement <4 x float> %98, i32 2
  %102 = fadd float %99, -5.000000e-01
  %103 = fadd float %101, -5.000000e-01
  %104 = fadd float %100, -5.000000e-01
  %105 = fmul float %102, %102
  %106 = fmul float %103, %103
  %107 = fadd float %106, %105
  %108 = fmul float %104, %104
  %109 = fadd float %107, %108
  %110 = call float @llvm.AMDGPU.rsq(float %109)
  %111 = fmul float %102, %110
  %112 = fmul float %103, %110
  %113 = fmul float %104, %110
  %114 = bitcast float %69 to i32
  %115 = bitcast float %70 to i32
  %116 = insertelement <2 x i32> undef, i32 %114, i32 0
  %117 = insertelement <2 x i32> %116, i32 %115, i32 1
  %118 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %117, <32 x i8> %38, <16 x i8> %40, i32 2)
  %119 = extractelement <4 x float> %118, i32 0
  %120 = extractelement <4 x float> %118, i32 1
  %121 = extractelement <4 x float> %118, i32 2
  %122 = fadd float %119, -5.000000e-01
  %123 = fadd float %120, -5.000000e-01
  %124 = fadd float %121, -5.000000e-01
  %125 = bitcast float %81 to i32
  %126 = bitcast float %82 to i32
  %127 = insertelement <2 x i32> undef, i32 %125, i32 0
  %128 = insertelement <2 x i32> %127, i32 %126, i32 1
  %129 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %128, <32 x i8> %38, <16 x i8> %40, i32 2)
  %130 = extractelement <4 x float> %129, i32 0
  %131 = extractelement <4 x float> %129, i32 1
  %132 = extractelement <4 x float> %129, i32 2
  %133 = fadd float %130, -5.000000e-01
  %134 = fadd float %131, -5.000000e-01
  %135 = fadd float %132, -5.000000e-01
  %136 = fmul float %133, %133
  %137 = fmul float %134, %134
  %138 = fadd float %137, %136
  %139 = fmul float %135, %135
  %140 = fadd float %138, %139
  %141 = call float @llvm.AMDGPU.rsq(float %140)
  %142 = fmul float %122, %122
  %143 = fmul float %123, %123
  %144 = fadd float %143, %142
  %145 = fmul float %124, %124
  %146 = fadd float %144, %145
  %147 = call float @llvm.AMDGPU.rsq(float %146)
  %148 = fmul float %122, %147
  %149 = fmul float %123, %147
  %150 = fmul float %124, %147
  %151 = fmul float %133, %141
  %152 = fadd float %151, %148
  %153 = fmul float %134, %141
  %154 = fadd float %153, %149
  %155 = fmul float %135, %141
  %156 = fadd float %155, %150
  %157 = fmul float %152, %152
  %158 = fmul float %154, %154
  %159 = fadd float %158, %157
  %160 = fmul float %156, %156
  %161 = fadd float %159, %160
  %162 = call float @llvm.AMDGPU.rsq(float %161)
  %163 = fmul float %152, %162
  %164 = fmul float %154, %162
  %165 = fmul float %156, %162
  %166 = fsub float -0.000000e+00, %76
  %167 = fmul float %163, %75
  %168 = fmul float %163, %76
  %169 = fmul float %164, %166
  %170 = fadd float %169, %167
  %171 = fmul float %164, %75
  %172 = fadd float %171, %168
  %173 = fmul float %112, %170
  %174 = fmul float %111, %170
  %175 = fmul float %113, %170
  %176 = fmul float %111, %165
  %177 = fadd float %176, %173
  %178 = fmul float %112, %165
  %179 = fadd float %178, %174
  %180 = fmul float %113, %165
  %181 = fadd float %180, %175
  %182 = fmul float %111, %172
  %183 = fadd float %182, %177
  %184 = fmul float %113, %172
  %185 = fadd float %184, %179
  %186 = fmul float %112, %172
  %187 = fadd float %186, %181
  %188 = fsub float -0.000000e+00, %29
  %189 = fadd float %77, %188
  %190 = fsub float -0.000000e+00, %30
  %191 = fadd float %78, %190
  %192 = fsub float -0.000000e+00, %31
  %193 = fadd float %79, %192
  %194 = fmul float %189, %189
  %195 = fmul float %191, %191
  %196 = fadd float %195, %194
  %197 = fmul float %193, %193
  %198 = fadd float %196, %197
  %199 = call float @llvm.AMDGPU.rsq(float %198)
  %200 = fmul float %189, %199
  %201 = fmul float %191, %199
  %202 = fmul float %193, %199
  %203 = fsub float -0.000000e+00, %26
  %204 = fsub float -0.000000e+00, %200
  %205 = fadd float %203, %204
  %206 = fsub float -0.000000e+00, %27
  %207 = fsub float -0.000000e+00, %201
  %208 = fadd float %206, %207
  %209 = fsub float -0.000000e+00, %28
  %210 = fsub float -0.000000e+00, %202
  %211 = fadd float %209, %210
  %212 = fmul float %205, %205
  %213 = fmul float %208, %208
  %214 = fadd float %213, %212
  %215 = fmul float %211, %211
  %216 = fadd float %214, %215
  %217 = call float @llvm.AMDGPU.rsq(float %216)
  %218 = fmul float %205, %217
  %219 = fmul float %208, %217
  %220 = fmul float %211, %217
  %221 = fmul float %218, %183
  %222 = fmul float %219, %185
  %223 = fadd float %222, %221
  %224 = fmul float %220, %187
  %225 = fadd float %223, %224
  %226 = call float @llvm.AMDIL.clamp.(float %225, float 0.000000e+00, float 1.000000e+00)
  %227 = call float @llvm.pow.f32(float %226, float 7.000000e+01)
  %228 = fmul float %227, 2.500000e-01
  %229 = call float @llvm.AMDIL.clamp.(float %228, float 0.000000e+00, float 1.000000e+00)
  %230 = fsub float -0.000000e+00, %72
  %231 = fadd float 5.000000e-01, %230
  %232 = call float @fabs(float %231)
  %233 = fmul float %232, 2.000000e+00
  %234 = fsub float -0.000000e+00, %233
  %235 = fadd float 1.000000e+00, %234
  %236 = fmul float %229, %235
  %237 = fmul float %183, %32
  %238 = fmul float %185, %33
  %239 = fadd float %238, %237
  %240 = fmul float %187, %34
  %241 = fadd float %239, %240
  %242 = fmul float %183, %32
  %243 = fmul float %185, %33
  %244 = fadd float %243, %242
  %245 = fmul float %187, %34
  %246 = fadd float %244, %245
  %247 = fmul float %241, %246
  %248 = fsub float -0.000000e+00, %247
  %249 = fadd float 1.000000e+00, %248
  %250 = fmul float %249, 0x3FDBE0DF00000000
  %251 = fsub float -0.000000e+00, %250
  %252 = fadd float 1.000000e+00, %251
  %253 = fcmp olt float %252, 0.000000e+00
  %254 = sext i1 %253 to i32
  %255 = bitcast i32 %254 to float
  %256 = bitcast float %255 to i32
  %257 = icmp ne i32 %256, 0
  br i1 %257, label %ENDIF, label %ELSE

ELSE:                                             ; preds = %main_body
  %258 = call float @llvm.AMDGPU.rsq(float %252)
  %259 = fmul float %258, %252
  %260 = fsub float -0.000000e+00, %252
  %261 = call float @llvm.AMDGPU.cndlt(float %260, float %259, float 0.000000e+00)
  %262 = fmul float 0x3FE51EB860000000, %241
  %263 = fadd float %262, %261
  %264 = fmul float %263, %183
  %265 = fmul float %263, %187
  %266 = fsub float -0.000000e+00, %264
  %267 = fmul float 0x3FE51EB860000000, %32
  %268 = fadd float %267, %266
  %269 = fsub float -0.000000e+00, %265
  %270 = fmul float 0x3FE51EB860000000, %34
  %271 = fadd float %270, %269
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %ELSE
  %temp20.0 = phi float [ %268, %ELSE ], [ 0.000000e+00, %main_body ]
  %temp22.0 = phi float [ %271, %ELSE ], [ 0.000000e+00, %main_body ]
  %272 = fsub float -0.000000e+00, %76
  %273 = fmul float %temp20.0, %75
  %274 = fmul float %temp20.0, %76
  %275 = fmul float %temp22.0, %272
  %276 = fadd float %275, %273
  %277 = fmul float %temp22.0, %75
  %278 = fadd float %277, %274
  %279 = fmul float %276, 0x3FA99999A0000000
  %280 = fadd float %279, %71
  %281 = fmul float %278, 0x3FA99999A0000000
  %282 = fadd float %281, %72
  %283 = bitcast float %280 to i32
  %284 = bitcast float %282 to i32
  %285 = insertelement <2 x i32> undef, i32 %283, i32 0
  %286 = insertelement <2 x i32> %285, i32 %284, i32 1
  %287 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %286, <32 x i8> %66, <16 x i8> %68, i32 2)
  %288 = extractelement <4 x float> %287, i32 0
  %289 = extractelement <4 x float> %287, i32 1
  %290 = extractelement <4 x float> %287, i32 2
  %291 = bitcast float %71 to i32
  %292 = bitcast float %72 to i32
  %293 = insertelement <2 x i32> undef, i32 %291, i32 0
  %294 = insertelement <2 x i32> %293, i32 %292, i32 1
  %295 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %294, <32 x i8> %66, <16 x i8> %68, i32 2)
  %296 = extractelement <4 x float> %295, i32 3
  %297 = bitcast float %73 to i32
  %298 = bitcast float %74 to i32
  %299 = insertelement <2 x i32> undef, i32 %297, i32 0
  %300 = insertelement <2 x i32> %299, i32 %298, i32 1
  %301 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %300, <32 x i8> %54, <16 x i8> %56, i32 2)
  %302 = extractelement <4 x float> %301, i32 0
  %303 = extractelement <4 x float> %301, i32 1
  %304 = extractelement <4 x float> %301, i32 2
  %305 = fcmp olt float %302, 5.000000e-01
  %306 = sext i1 %305 to i32
  %307 = bitcast i32 %306 to float
  %308 = bitcast float %307 to i32
  %309 = icmp ne i32 %308, 0
  br i1 %309, label %IF41, label %ELSE42

IF41:                                             ; preds = %ENDIF
  %310 = fmul float 2.000000e+00, %302
  %311 = fmul float %310, %288
  br label %ENDIF40

ELSE42:                                           ; preds = %ENDIF
  %312 = fsub float -0.000000e+00, %302
  %313 = fadd float 1.000000e+00, %312
  %314 = fmul float 2.000000e+00, %313
  %315 = fsub float -0.000000e+00, %288
  %316 = fadd float 1.000000e+00, %315
  %317 = fmul float %314, %316
  %318 = fsub float -0.000000e+00, %317
  %319 = fadd float 1.000000e+00, %318
  br label %ENDIF40

ENDIF40:                                          ; preds = %ELSE42, %IF41
  %temp24.0 = phi float [ %311, %IF41 ], [ %319, %ELSE42 ]
  %320 = fcmp olt float %303, 5.000000e-01
  %321 = sext i1 %320 to i32
  %322 = bitcast i32 %321 to float
  %323 = bitcast float %322 to i32
  %324 = icmp ne i32 %323, 0
  br i1 %324, label %IF44, label %ELSE45

IF44:                                             ; preds = %ENDIF40
  %325 = fmul float 2.000000e+00, %303
  %326 = fmul float %325, %289
  br label %ENDIF43

ELSE45:                                           ; preds = %ENDIF40
  %327 = fsub float -0.000000e+00, %303
  %328 = fadd float 1.000000e+00, %327
  %329 = fmul float 2.000000e+00, %328
  %330 = fsub float -0.000000e+00, %289
  %331 = fadd float 1.000000e+00, %330
  %332 = fmul float %329, %331
  %333 = fsub float -0.000000e+00, %332
  %334 = fadd float 1.000000e+00, %333
  br label %ENDIF43

ENDIF43:                                          ; preds = %ELSE45, %IF44
  %temp28.0 = phi float [ %326, %IF44 ], [ %334, %ELSE45 ]
  %335 = fcmp olt float %304, 5.000000e-01
  %336 = sext i1 %335 to i32
  %337 = bitcast i32 %336 to float
  %338 = bitcast float %337 to i32
  %339 = icmp ne i32 %338, 0
  br i1 %339, label %IF47, label %ELSE48

IF47:                                             ; preds = %ENDIF43
  %340 = fmul float 2.000000e+00, %304
  %341 = fmul float %340, %290
  br label %ENDIF46

ELSE48:                                           ; preds = %ENDIF43
  %342 = fsub float -0.000000e+00, %304
  %343 = fadd float 1.000000e+00, %342
  %344 = fmul float 2.000000e+00, %343
  %345 = fsub float -0.000000e+00, %290
  %346 = fadd float 1.000000e+00, %345
  %347 = fmul float %344, %346
  %348 = fsub float -0.000000e+00, %347
  %349 = fadd float 1.000000e+00, %348
  br label %ENDIF46

ENDIF46:                                          ; preds = %ELSE48, %IF47
  %temp28.1 = phi float [ %341, %IF47 ], [ %349, %ELSE48 ]
  %350 = bitcast float %71 to i32
  %351 = bitcast float %72 to i32
  %352 = insertelement <2 x i32> undef, i32 %350, i32 0
  %353 = insertelement <2 x i32> %352, i32 %351, i32 1
  %354 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %353, <32 x i8> %42, <16 x i8> %44, i32 2)
  %355 = extractelement <4 x float> %354, i32 0
  %356 = extractelement <4 x float> %354, i32 1
  %357 = extractelement <4 x float> %354, i32 2
  %358 = fadd float %355, -5.000000e-01
  %359 = fadd float %356, -5.000000e-01
  %360 = fadd float %357, -5.000000e-01
  %361 = fmul float %358, %358
  %362 = fmul float %359, %359
  %363 = fadd float %362, %361
  %364 = fmul float %360, %360
  %365 = fadd float %363, %364
  %366 = call float @llvm.AMDGPU.rsq(float %365)
  %367 = fmul float %358, %366
  %368 = fmul float %359, %366
  %369 = fmul float %360, %366
  %370 = fsub float -0.000000e+00, %76
  %371 = fmul float %367, %75
  %372 = fmul float %367, %76
  %373 = fmul float %368, %370
  %374 = fadd float %373, %371
  %375 = fmul float %368, %75
  %376 = fadd float %375, %372
  %377 = fmul float %112, %374
  %378 = fmul float %111, %374
  %379 = fmul float %113, %374
  %380 = fmul float %111, %369
  %381 = fadd float %380, %377
  %382 = fmul float %112, %369
  %383 = fadd float %382, %378
  %384 = fmul float %113, %369
  %385 = fadd float %384, %379
  %386 = fmul float %111, %376
  %387 = fadd float %386, %381
  %388 = fmul float %113, %376
  %389 = fadd float %388, %383
  %390 = fmul float %112, %376
  %391 = fadd float %390, %385
  %392 = fsub float -0.000000e+00, %26
  %393 = fsub float -0.000000e+00, %27
  %394 = fsub float -0.000000e+00, %28
  %395 = fmul float %387, %392
  %396 = fmul float %389, %393
  %397 = fadd float %396, %395
  %398 = fmul float %391, %394
  %399 = fadd float %397, %398
  %400 = fmul float %399, 5.000000e-01
  %401 = fadd float %400, 5.000000e-01
  %402 = fadd float %77, 5.000000e-01
  %403 = fdiv float 1.000000e+00, %22
  %404 = fmul float %402, %403
  %405 = fadd float %79, 5.000000e-01
  %406 = fdiv float 1.000000e+00, %23
  %407 = fmul float %405, %406
  %408 = bitcast float %404 to i32
  %409 = bitcast float %407 to i32
  %410 = insertelement <2 x i32> undef, i32 %408, i32 0
  %411 = insertelement <2 x i32> %410, i32 %409, i32 1
  %412 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %411, <32 x i8> %50, <16 x i8> %52, i32 2)
  %413 = extractelement <4 x float> %412, i32 3
  %414 = fadd float %77, 5.000000e-01
  %415 = fadd float %79, 5.000000e-01
  %416 = fmul float %414, 3.906250e-03
  %417 = fmul float %415, 3.906250e-03
  %418 = fmul float %36, 0x3F947AE140000000
  %419 = fadd float %418, %416
  %420 = fmul float %36, 0x3F947AE140000000
  %421 = fadd float %420, %417
  %422 = bitcast float %419 to i32
  %423 = bitcast float %421 to i32
  %424 = insertelement <2 x i32> undef, i32 %422, i32 0
  %425 = insertelement <2 x i32> %424, i32 %423, i32 1
  %426 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %425, <32 x i8> %58, <16 x i8> %60, i32 2)
  %427 = extractelement <4 x float> %426, i32 0
  %428 = fmul float %36, 0x3FB99999A0000000
  %429 = call float @llvm.AMDIL.fraction.(float %428)
  %430 = fadd float %427, %429
  %431 = fmul float %430, 0x401921FB60000000
  %432 = call float @llvm.sin.f32(float %431)
  %433 = fmul float %432, 0x3FB99999A0000000
  %434 = fadd float %433, 5.000000e-01
  %435 = fadd float %413, %434
  %436 = call float @llvm.AMDIL.clamp.(float %435, float 0.000000e+00, float 1.000000e+00)
  %437 = call float @llvm.AMDGPU.lrp(float %35, float %436, float 1.000000e+00)
  %438 = fsub float -0.000000e+00, %77
  %439 = fadd float %29, %438
  %440 = fsub float -0.000000e+00, %78
  %441 = fadd float %30, %440
  %442 = fsub float -0.000000e+00, %79
  %443 = fadd float %31, %442
  %444 = fsub float -0.000000e+00, %80
  %445 = fadd float 1.000000e+00, %444
  %446 = fmul float %236, %445
  %447 = fmul float %446, %91
  %448 = fmul float %401, %401
  %449 = fmul float 0x3FE99999A0000000, %448
  %450 = fadd float %449, 0x3FC99999A0000000
  %451 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp24.0, float %288)
  %452 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp28.0, float %289)
  %453 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp28.1, float %290)
  %454 = fmul float %91, 0x3FE99999A0000000
  %455 = call float @llvm.AMDGPU.lrp(float %454, float %88, float %451)
  %456 = call float @llvm.AMDGPU.lrp(float %454, float %89, float %452)
  %457 = call float @llvm.AMDGPU.lrp(float %454, float %90, float %453)
  %458 = fmul float %450, %455
  %459 = fmul float %450, %456
  %460 = fmul float %450, %457
  %461 = fmul float %458, 0x3FF3333340000000
  %462 = fmul float %459, 0x3FF3333340000000
  %463 = fmul float %460, 0x3FF3333340000000
  %464 = call float @llvm.AMDIL.clamp.(float %461, float 0.000000e+00, float 1.000000e+00)
  %465 = call float @llvm.AMDIL.clamp.(float %462, float 0.000000e+00, float 1.000000e+00)
  %466 = call float @llvm.AMDIL.clamp.(float %463, float 0.000000e+00, float 1.000000e+00)
  %467 = fmul float %439, %439
  %468 = fmul float %441, %441
  %469 = fadd float %468, %467
  %470 = fmul float %443, %443
  %471 = fadd float %469, %470
  %472 = fadd float %471, -1.600000e+05
  %473 = fmul float %472, 0x3EAA36E2E0000000
  %474 = fcmp uge float %473, 5.000000e-01
  %475 = select i1 %474, float 5.000000e-01, float %473
  %476 = call float @llvm.AMDIL.clamp.(float %475, float 0.000000e+00, float 1.000000e+00)
  %477 = fmul float %439, %439
  %478 = fmul float %441, %441
  %479 = fadd float %478, %477
  %480 = fmul float %443, %443
  %481 = fadd float %479, %480
  %482 = call float @llvm.AMDGPU.rsq(float %481)
  %483 = fmul float %441, %482
  %484 = fsub float -0.000000e+00, %483
  %485 = fadd float 1.000000e+00, %484
  %486 = fmul float %476, %485
  %487 = call float @llvm.AMDGPU.lrp(float %486, float 5.000000e-01, float %464)
  %488 = call float @llvm.AMDGPU.lrp(float %486, float 5.000000e-01, float %465)
  %489 = call float @llvm.AMDGPU.lrp(float %486, float 5.000000e-01, float %466)
  %490 = fmul float %487, %437
  %491 = fmul float %488, %437
  %492 = fmul float %489, %437
  %493 = fmul float %447, %437
  %494 = fadd float %493, %490
  %495 = fmul float %447, %437
  %496 = fadd float %495, %491
  %497 = fmul float %447, %437
  %498 = fadd float %497, %492
  %499 = call float @llvm.AMDIL.clamp.(float %494, float 0.000000e+00, float 1.000000e+00)
  %500 = call float @llvm.AMDIL.clamp.(float %496, float 0.000000e+00, float 1.000000e+00)
  %501 = call float @llvm.AMDIL.clamp.(float %498, float 0.000000e+00, float 1.000000e+00)
  %502 = fsub float -0.000000e+00, %80
  %503 = fadd float 1.000000e+00, %502
  %504 = fmul float %296, %503
  %505 = call i32 @llvm.SI.packf16(float %499, float %500)
  %506 = bitcast i32 %505 to float
  %507 = call i32 @llvm.SI.packf16(float %501, float %504)
  %508 = bitcast i32 %507 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %506, float %508, float %506, float %508)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: readonly
declare float @fabs(float) #4

; Function Attrs: readnone
declare float @llvm.AMDGPU.cndlt(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }
attributes #4 = { readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800700
00430802
bf8c0770
060e12f1
060810f1
100a0904
d2820006
04160f07
060a14f1
d2820006
041a0b05
7e0c5b06
100e0d07
c8240d00
c8250d01
c8200c00
c8210c01
f0800700
00430a08
bf8c0770
061016f1
061214f1
101a1309
d282000d
04361108
061418f1
d282000b
0436150a
7e165b0b
d2820008
041e1708
10080d04
d2820004
04121709
100e0904
d2820007
041e1108
100a0d05
d2820006
0416170a
d2820005
041e0d06
7e0e5b05
10100f08
10120f04
c8100700
c8110701
10140909
c8140600
c8150601
d282000a
042a0b08
10100908
10120b09
08161109
c8580500
c8590501
c0860100
bf8c007f
c2000d43
bf8c007f
10122c00
c8540400
c8550401
c2000d42
bf8c007f
10102a00
c0840318
c0c80530
bf8c007f
f0800700
00440c08
bf8c0770
06101cf1
061218f1
101e1309
d282000f
043e1108
06181af1
d282000d
043e190c
7e1c5b0d
10201d09
101e1710
101a0f06
10121d08
d2820006
043e1b09
101c1d0c
d282000c
041a150e
100c1709
d2820006
041a1b10
d2820012
041a1510
c8200900
c8210901
c2000d49
bf8c007f
0a1e1000
c8180800
c8190801
c2008d48
bf8c007f
0a220c01
100e2311
d2820014
041e1f0f
c81c0a00
c81d0a01
c2038d4a
bf8c007f
0a260e07
d2820014
04522713
7e285b14
101e290f
c2040d45
bf8c007f
d2060017
22010008
081e1f17
10222911
c2048d44
bf8c007f
d2060017
22010009
082e2317
10222f17
d2820018
04461f0f
10222913
c2050d46
bf8c007f
d2060013
2201000a
08222313
d2820013
04622311
7e285b13
10262917
10262513
101e290f
d282000f
044e190f
1016170e
d282000b
042e1b0e
d2820013
042e1509
10142911
d282000a
043e270a
d206080a
0201010a
7e144f0a
0e1414ff
428c0000
7e144b0a
101414ff
3e800000
d206080a
0201010a
c80c0300
c80d0301
081606f0
d206010b
0201010b
0616170b
081616f2
101e170a
c2090d50
bf8c007f
10142412
c2058d51
bf8c007f
d282000a
0428170c
c2098d52
bf8c007f
d2820014
04282713
10142914
081414f2
7e1602ff
bedf06f8
d2820017
03ca170a
d0020010
02010117
d200000a
00418280
d104002c
0201010a
c08a0308
c0cc0510
bf8c007f
f0800f00
00a60a02
c8440b00
c8450b01
c8080200
c8090201
c08a031c
c0cc0538
c0900310
c0d20520
c2080d59
c2088d58
c2030d41
c2058d40
7e020280
7e000301
bf8c0070
be8c242c
898c0c7e
bf880016
7e000213
7e020212
7e305b17
10302f18
d2060017
22010117
d008000e
02022e80
d2000017
003a3080
7e3002ff
3f28f5c3
d2820014
045e3114
10262714
100000ff
3f28f5c3
08002700
10242514
100202ff
3f28f5c3
08022501
88fe0c7e
10240900
10260b01
08242513
7e2802ff
3d4ccccd
d2820012
040a2912
10020901
d2820000
04060b00
d2820013
040e2900
f0800700
00a61212
f0800700
01091815
f0800800
00a60002
bf8c0771
d002000c
0201e118
d2000001
00318280
d104000c
02010101
bf8c0770
be8c240c
898c0c7e
080224f2
082a30f2
102a2af5
d2820001
03ca0315
be8c250c
89fe0c7e
06023118
10022501
88fe0c7e
d002000c
0201e119
d2000015
00318280
d104000c
02010115
be8c240c
898c0c7e
082a26f2
082c32f2
102c2cf5
d2820017
03ca2b16
be8c250c
89fe0c7e
062a3319
102e2715
88fe0c7e
d002000c
0201e11a
d2000015
00318280
d104000c
02010115
be92240c
8992127e
082a28f2
082c34f2
102c2cf5
d2820015
03ca2b16
be922512
c08e0314
c0d00528
c086030c
c0ca0518
c0940304
c0d60508
7e3a0210
7e2c0211
7e3c0207
7e400200
7e3e0201
7e42020a
7e440208
7e460209
7e380206
7e36020b
bf8c007f
89fe127e
062a351a
102a2915
88fe127e
f0800700
014b1802
bf8c0770
060432f1
060630f1
10480703
d2820024
04920502
063034f1
d2820019
04923118
7e325b19
10343302
10063303
10040903
d2820002
040a0b1a
1008091a
10060b03
08060903
100a0709
10083318
d2820005
04160910
d2820005
04160510
100a4705
10200710
d2820010
04420909
d2820010
0442050e
d2060018
22010122
10203110
080a0b10
1006070e
d2820003
040e090e
d2820002
040e0509
10044302
08040505
d2820002
03c1e102
10040502
7e0602ff
3e4ccccd
7e0802ff
3f4ccccd
d2820002
040e0902
100626f0
d2820005
040de117
10061aff
3f4ccccd
080806f2
100a0b04
d2820005
04161703
100a0b02
100a0aff
3f99999a
d2060809
02010105
080a1120
08100d1f
10101108
d2820008
04220b05
081c0f1e
d2820008
04221d0e
061c10ff
c81c4000
101c1cff
3551b717
d00c0000
0201e10e
d200000e
0001e10e
d206080e
0201010e
7e105b08
100a1105
080a0af2
100a0b0e
08100af2
10121308
d2820009
0425e105
060e0ef0
10200eff
3b800000
7e1c02ff
3ca3d70a
d2820018
04421d1d
060c0cf0
10200cff
3b800000
d2820017
04421d1d
f0800100
00e80e17
10203aff
3dcccccd
7e204110
bf8c0770
061c210e
101c1cff
40c90fdb
101c1cff
3e22f983
7e1c6b0e
7e2002ff
3dcccccd
d282000e
03c2210e
7e20551c
10302107
7e0e551b
102e0f06
f0800800
00650617
bf8c0770
060c1d06
d2060806
02010106
080e2cf2
d2820006
041e0d16
101c0d09
080e22f2
10120f0f
10121b09
d282000e
043a0d09
d206080e
0201010e
101e24f0
d2820001
043de101
10020304
d2820001
04061503
10020302
100202ff
3f99999a
d2060801
02010101
10020308
d2820001
0405e105
10020d01
d2820001
04060d09
d2060801
02010101
5e021d01
101c28f0
d282000e
0439e115
10081d04
d2820003
04121903
10040702
100404ff
3f99999a
d2060802
02010102
10040508
d2820002
0409e105
10040d02
d2820002
040a0d09
d2060802
02010102
10000f00
5e000102
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL OUT[3], GENERIC[21]
DCL OUT[4], GENERIC[22]
DCL CONST[0..23]
DCL TEMP[0..6], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0500,     0.2000}
IMM[1] FLT32 {    0.9000,     0.1000,     0.5000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xyz, IN[0].xyzx
  2: MOV TEMP[1].xyz, IN[0].xyzx
  3: MOV TEMP[2].w, IMM[0].yyyy
  4: MUL TEMP[2].xyz, CONST[20].xyzz, IMM[0].zzzz
  5: DP4 TEMP[3].x, TEMP[0], CONST[0]
  6: DP4 TEMP[4].x, TEMP[0], CONST[1]
  7: MOV TEMP[3].y, TEMP[4].xxxx
  8: DP4 TEMP[4].x, TEMP[0], CONST[3]
  9: MOV TEMP[3].xy, TEMP[3].xyxx
 10: ADD TEMP[0], TEMP[0], -TEMP[2]
 11: DP4 TEMP[0].x, TEMP[0], CONST[2]
 12: MOV TEMP[3].z, TEMP[0].xxxx
 13: MOV TEMP[3].w, TEMP[4].xxxx
 14: MAD TEMP[0].x, CONST[23].xxxx, CONST[23].yyyy, IN[1].yyyy
 15: MAD TEMP[2].x, CONST[23].xxxx, IMM[0].wwww, IN[1].xxxx
 16: MOV TEMP[0].y, TEMP[2].xxxx
 17: MUL TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz
 18: MUL TEMP[2].x, CONST[23].xxxx, IMM[1].xxxx
 19: MAD TEMP[2].x, TEMP[2].xxxx, CONST[23].yyyy, IN[1].yyyy
 20: MUL TEMP[4].x, CONST[23].xxxx, IMM[1].yyyy
 21: ADD TEMP[4].x, IN[1].xxxx, -TEMP[4].xxxx
 22: MOV TEMP[2].y, TEMP[4].xxxx
 23: MUL TEMP[2].x, TEMP[2].xxxx, IMM[0].zzzz
 24: MOV TEMP[0].w, IN[1].xxxx
 25: MUL TEMP[4].x, IN[1].yyyy, IMM[0].zzzz
 26: MOV TEMP[0].z, TEMP[4].xxxx
 27: ADD TEMP[4].x, IN[0].xxxx, IMM[1].zzzz
 28: RCP TEMP[5].x, CONST[16].xxxx
 29: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 30: ADD TEMP[5].x, IN[0].zzzz, IMM[1].zzzz
 31: ADD TEMP[5].x, TEMP[5].xxxx, -CONST[16].yyyy
 32: RCP TEMP[6].x, -CONST[16].yyyy
 33: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 34: MOV TEMP[4].y, TEMP[5].xxxx
 35: MOV TEMP[4].zw, IN[1].wwzw
 36: ADD_SAT TEMP[5].x, IMM[0].xxxx, -IN[1].yyyy
 37: MOV TEMP[1].w, TEMP[5].xxxx
 38: MOV TEMP[2].xy, TEMP[2].xyxx
 39: MOV OUT[1], TEMP[0]
 40: MOV OUT[2], TEMP[4]
 41: MOV OUT[3], TEMP[1]
 42: MOV OUT[4], TEMP[2]
 43: MOV OUT[0], TEMP[3]
 44: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %41 = load <16 x i8> addrspace(2)* %40, !tbaa !0
  %42 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %41, i32 0, i32 %5)
  %43 = extractelement <4 x float> %42, i32 0
  %44 = extractelement <4 x float> %42, i32 1
  %45 = extractelement <4 x float> %42, i32 2
  %46 = extractelement <4 x float> %42, i32 3
  %47 = fmul float %29, 0x3FA99999A0000000
  %48 = fmul float %30, 0x3FA99999A0000000
  %49 = fmul float %31, 0x3FA99999A0000000
  %50 = fmul float %37, %11
  %51 = fmul float %38, %12
  %52 = fadd float %50, %51
  %53 = fmul float %39, %13
  %54 = fadd float %52, %53
  %55 = fmul float 1.000000e+00, %14
  %56 = fadd float %54, %55
  %57 = fmul float %37, %15
  %58 = fmul float %38, %16
  %59 = fadd float %57, %58
  %60 = fmul float %39, %17
  %61 = fadd float %59, %60
  %62 = fmul float 1.000000e+00, %18
  %63 = fadd float %61, %62
  %64 = fmul float %37, %23
  %65 = fmul float %38, %24
  %66 = fadd float %64, %65
  %67 = fmul float %39, %25
  %68 = fadd float %66, %67
  %69 = fmul float 1.000000e+00, %26
  %70 = fadd float %68, %69
  %71 = fsub float -0.000000e+00, %47
  %72 = fadd float %37, %71
  %73 = fsub float -0.000000e+00, %48
  %74 = fadd float %38, %73
  %75 = fsub float -0.000000e+00, %49
  %76 = fadd float %39, %75
  %77 = fsub float -0.000000e+00, 0.000000e+00
  %78 = fadd float 1.000000e+00, %77
  %79 = fmul float %72, %19
  %80 = fmul float %74, %20
  %81 = fadd float %79, %80
  %82 = fmul float %76, %21
  %83 = fadd float %81, %82
  %84 = fmul float %78, %22
  %85 = fadd float %83, %84
  %86 = fmul float %32, %33
  %87 = fadd float %86, %44
  %88 = fmul float %32, 0x3FC99999A0000000
  %89 = fadd float %88, %43
  %90 = fmul float %87, 0x3FA99999A0000000
  %91 = fmul float %32, 0x3FECCCCCC0000000
  %92 = fmul float %91, %33
  %93 = fadd float %92, %44
  %94 = fmul float %32, 0x3FB99999A0000000
  %95 = fsub float -0.000000e+00, %94
  %96 = fadd float %43, %95
  %97 = fmul float %93, 0x3FA99999A0000000
  %98 = fmul float %44, 0x3FA99999A0000000
  %99 = fadd float %37, 5.000000e-01
  %100 = fdiv float 1.000000e+00, %27
  %101 = fmul float %99, %100
  %102 = fadd float %39, 5.000000e-01
  %103 = fsub float -0.000000e+00, %28
  %104 = fadd float %102, %103
  %105 = fsub float -0.000000e+00, %28
  %106 = fdiv float 1.000000e+00, %105
  %107 = fmul float %104, %106
  %108 = fsub float -0.000000e+00, %44
  %109 = fadd float 1.000000e+00, %108
  %110 = call float @llvm.AMDIL.clamp.(float %109, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %90, float %89, float %98, float %43)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %101, float %107, float %45, float %46)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %37, float %38, float %39, float %110)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %97, float %96, float %49, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %56, float %63, float %85, float %70)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020400
c0800100
bf8c0070
c202015c
7e0202ff
3e4ccccd
bf8c007f
d2820001
04120204
10040aff
3d4ccccd
c202815d
bf8c007f
7e060205
d2820003
04160604
100606ff
3d4ccccd
f800020f
04020103
c0840700
bf8c000f
e00c2000
80020000
bf8c0770
061000f0
c2030140
bf8c007f
7e125406
10101308
061204f0
c2030141
bf8c007f
0a121206
d206000a
22010006
7e14550a
10121509
f800021f
07060908
bf8c070f
08100af2
d2060808
02010108
f800022f
08020100
bf8c070f
7e1002ff
3f666666
10101004
d2820008
04140b08
101010ff
3d4ccccd
7e1202ff
bdcccccd
d2820006
04121204
c2020152
7e0a02ff
3d4ccccd
bf8c007f
10080a04
7e0e0280
f800023f
07040608
c2020150
bf8c000f
100c0a04
080c0d00
c2020151
bf8c007f
100a0a04
080a0b01
c2020109
bf8c007f
100a0a04
c2020108
bf8c007f
d2820005
04140906
08080902
c202010a
bf8c007f
d2820004
04140904
c202010b
bf8c007f
06080804
c202010d
bf8c007f
100a0204
c202010c
bf8c007f
d2820005
04140900
c202010e
bf8c007f
d2820005
04140902
c202010f
bf8c007f
060a0a04
c2020105
bf8c007f
100c0204
c2020104
bf8c007f
d2820006
04180900
c2020106
bf8c007f
d2820006
04180902
c2020107
bf8c007f
060c0c04
c2020101
bf8c007f
100e0204
c2020100
bf8c007f
d2820007
041c0900
c2020102
bf8c007f
d2820000
041c0902
c2000103
bf8c007f
06000000
f80008cf
05040600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL SAMP[4]
DCL SAMP[5]
DCL SAMP[6]
DCL CONST[0..23]
DCL TEMP[0..6], LOCAL
IMM[0] FLT32 {    0.0200,    -1.0000,     0.5000,   120.0000}
IMM[1] FLT32 {    0.9000,     2.1000,     1.8000,     0.4500}
IMM[2] FLT32 {  156.0000,     1.0000,     0.8000,    10.0000}
IMM[3] FLT32 {    0.2000,     2.0000,     5.0000,     0.3000}
IMM[4] FLT32 {    0.0039,     0.1000,     6.2832, -160000.0000}
IMM[5] FLT32 {    0.0000,     0.9000,     3.0000,     2.7215}
IMM[6] FLT32 {   -0.9950,    50.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[1].zwzz
  1: MOV TEMP[0].z, IN[2].xxxx
  2: MUL TEMP[1].x, CONST[23].xxxx, IMM[0].xxxx
  3: MUL TEMP[2].xy, IMM[0].wwww, IN[1].xyyy
  4: MAD TEMP[2].xy, IMM[1].xyyy, TEMP[1].xxxx, TEMP[2].xyyy
  5: MOV TEMP[2].xy, TEMP[2].xyyy
  6: TEX TEMP[2].xyz, TEMP[2], SAMP[3], 2D
  7: ADD TEMP[2].xyz, IMM[0].yyzz, TEMP[2].xyzz
  8: MUL TEMP[3].xy, IMM[2].xxxx, IN[1].xyyy
  9: MAD TEMP[1].xy, IMM[1].zwww, -TEMP[1].xxxx, TEMP[3].xyyy
 10: MOV TEMP[1].xy, TEMP[1].xyyy
 11: TEX TEMP[1].xyz, TEMP[1], SAMP[3], 2D
 12: ADD TEMP[1].xyz, TEMP[2].xyzz, TEMP[1].xyzz
 13: DP3 TEMP[2].x, TEMP[1].xyzz, TEMP[1].xyzz
 14: RSQ TEMP[2].x, TEMP[2].xxxx
 15: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xxxx
 16: ADD TEMP[2].xyz, TEMP[0].xyzz, -CONST[18].xyzz
 17: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
 18: RSQ TEMP[3].x, TEMP[3].xxxx
 19: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx
 20: RCP TEMP[3].x, IN[0].wwww
 21: MUL TEMP[3].xy, IN[0].xyyy, TEMP[3].xxxx
 22: MAD TEMP[3].xy, TEMP[3].xyyy, IMM[0].zzzz, IMM[0].zzzz
 23: MOV TEMP[4].x, TEMP[3].xxxx
 24: ADD TEMP[3].x, IMM[2].yyyy, -TEMP[3].yyyy
 25: MOV TEMP[4].y, TEMP[3].xxxx
 26: ADD TEMP[4].xy, TEMP[4].xyyy, CONST[23].yzzz
 27: DP3_SAT TEMP[3].x, -TEMP[2].xyzz, TEMP[1].xzyy
 28: MUL TEMP[3].x, TEMP[3].xxxx, IMM[0].zzzz
 29: ADD TEMP[3].x, IMM[2].yyyy, -TEMP[3].xxxx
 30: POW TEMP[3].x, TEMP[3].xxxx, IMM[2].wwww
 31: MAD_SAT TEMP[3].x, IMM[2].zzzz, TEMP[3].xxxx, IMM[3].xxxx
 32: ADD TEMP[5].xyz, -CONST[17].xyzz, -TEMP[2].xyzz
 33: DP3 TEMP[6].x, TEMP[1].xzyy, TEMP[2].xyzz
 34: MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[1].xzyy
 35: MUL TEMP[6].xyz, IMM[3].yyyy, TEMP[6].xyzz
 36: ADD TEMP[2].xyz, TEMP[2].xyzz, -TEMP[6].xyzz
 37: MOV TEMP[2].xyz, TEMP[2].xyzz
 38: TEX TEMP[2].xyz, TEMP[2], SAMP[5], CUBE
 39: RCP TEMP[6].x, IN[0].wwww
 40: MUL TEMP[6].x, IN[0].zzzz, TEMP[6].xxxx
 41: MUL TEMP[6].x, TEMP[6].xxxx, IMM[3].zzzz
 42: ADD_SAT TEMP[6].x, IMM[3].zzzz, -TEMP[6].xxxx
 43: MUL TEMP[6].xy, TEMP[1].xyyy, TEMP[6].xxxx
 44: MUL TEMP[6].xy, TEMP[6].xyyy, IMM[3].xxxx
 45: ADD TEMP[4].xy, TEMP[4].xyyy, -TEMP[6].xyyy
 46: MOV TEMP[4].xy, TEMP[4].xyyy
 47: TEX TEMP[4].xyz, TEMP[4], SAMP[1], 2D
 48: MUL TEMP[6].xy, IN[1].xyyy, CONST[16].zwww
 49: MOV TEMP[6].xy, TEMP[6].xyyy
 50: TEX TEMP[6].xyz, TEMP[6], SAMP[4], 2D
 51: LRP TEMP[4].xyz, IMM[3].wwww, TEMP[6].xyzz, TEMP[4].xyzz
 52: ADD TEMP[6].x, IMM[2].yyyy, -TEMP[3].xxxx
 53: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[6].xxxx
 54: MAD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx, TEMP[4].xyzz
 55: ADD TEMP[3].x, IN[1].zzzz, IMM[0].zzzz
 56: RCP TEMP[4].x, CONST[16].xxxx
 57: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 58: ADD TEMP[4].x, IN[2].xxxx, IMM[0].zzzz
 59: RCP TEMP[6].x, CONST[16].yyyy
 60: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[6].xxxx
 61: MOV TEMP[3].y, TEMP[4].xxxx
 62: MOV TEMP[3].xy, TEMP[3].xyyy
 63: TEX TEMP[3].w, TEMP[3], SAMP[6], 2D
 64: ADD TEMP[4].xy, TEMP[0].xzzz, IMM[0].zzzz
 65: MUL TEMP[4].xy, TEMP[4].xyyy, IMM[4].xxxx
 66: MAD TEMP[4].xy, CONST[22].yyyy, IMM[0].xxxx, TEMP[4].xyyy
 67: MOV TEMP[4].xy, TEMP[4].xyyy
 68: TEX TEMP[4].x, TEMP[4], SAMP[2], 2D
 69: MUL TEMP[6].x, CONST[22].yyyy, IMM[4].yyyy
 70: FRC TEMP[6].x, TEMP[6].xxxx
 71: ADD TEMP[4].x, TEMP[4].xxxx, TEMP[6].xxxx
 72: MUL TEMP[4].x, TEMP[4].xxxx, IMM[4].zzzz
 73: SIN TEMP[4].x, TEMP[4].xxxx
 74: MAD TEMP[4].x, TEMP[4].xxxx, IMM[4].yyyy, IMM[0].zzzz
 75: ADD_SAT TEMP[3].x, TEMP[3].wwww, TEMP[4].xxxx
 76: LRP TEMP[3].x, CONST[22].xxxx, TEMP[3].xxxx, IMM[2].yyyy
 77: ADD TEMP[0].xyz, CONST[18].xyzz, -TEMP[0].xyzz
 78: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz
 79: ADD TEMP[4].x, TEMP[4].xxxx, IMM[4].wwww
 80: MUL TEMP[4].x, TEMP[4].xxxx, IMM[5].xxxx
 81: MIN TEMP[4].x, TEMP[4].xxxx, IMM[0].zzzz
 82: MOV_SAT TEMP[4].x, TEMP[4].xxxx
 83: DP3 TEMP[6].x, TEMP[0].xyzz, TEMP[0].xyzz
 84: RSQ TEMP[6].x, TEMP[6].xxxx
 85: MUL TEMP[0].y, TEMP[0].xyzz, TEMP[6].xxxx
 86: ADD TEMP[0].x, IMM[2].yyyy, -TEMP[0].yyyy
 87: MUL TEMP[0].x, TEMP[4].xxxx, TEMP[0].xxxx
 88: LRP TEMP[0].xyz, TEMP[0].xxxx, IMM[0].zzzz, TEMP[2].xyzz
 89: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[3].xxxx
 90: DP3 TEMP[2].x, TEMP[5].xyzz, TEMP[5].xyzz
 91: RSQ TEMP[2].x, TEMP[2].xxxx
 92: MUL TEMP[2].xyz, TEMP[5].xyzz, TEMP[2].xxxx
 93: DP3_SAT TEMP[1].x, TEMP[2].xyzz, TEMP[1].xzyy
 94: MUL TEMP[2].x, CONST[16].xxxx, IMM[5].yyyy
 95: POW TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
 96: MUL_SAT TEMP[1].x, TEMP[1].xxxx, IMM[5].zzzz
 97: MAD_SAT TEMP[0].xyz, TEMP[1].xxxx, TEMP[3].xxxx, TEMP[0].xyzz
 98: MOV TEMP[0].xyz, TEMP[0].xyzx
 99: MUL TEMP[1].xy, IN[1].xyyy, CONST[16].zwww
100: MOV TEMP[1].xy, TEMP[1].xyyy
101: TEX TEMP[1].x, TEMP[1], SAMP[0], 2D
102: MAD TEMP[1].x, TEMP[1].xxxx, IMM[5].wwww, IMM[6].xxxx
103: MUL_SAT TEMP[1].x, TEMP[1].xxxx, IMM[6].yyyy
104: ADD TEMP[1].x, IMM[2].yyyy, -TEMP[1].xxxx
105: MOV TEMP[0].w, TEMP[1].xxxx
106: MOV OUT[0], TEMP[0]
107: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 264)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 268)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 276)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 280)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 368)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 372)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 376)
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %42 = load <32 x i8> addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %46 = load <32 x i8> addrspace(2)* %45, !tbaa !0
  %47 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %50 = load <32 x i8> addrspace(2)* %49, !tbaa !0
  %51 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
  %54 = load <32 x i8> addrspace(2)* %53, !tbaa !0
  %55 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
  %58 = load <32 x i8> addrspace(2)* %57, !tbaa !0
  %59 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
  %61 = getelementptr <32 x i8> addrspace(2)* %2, i32 6
  %62 = load <32 x i8> addrspace(2)* %61, !tbaa !0
  %63 = getelementptr <16 x i8> addrspace(2)* %1, i32 6
  %64 = load <16 x i8> addrspace(2)* %63, !tbaa !0
  %65 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %66 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %67 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %68 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %69 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %70 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %71 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %72 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %73 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %74 = fmul float %34, 0x3F947AE140000000
  %75 = fmul float 1.200000e+02, %69
  %76 = fmul float 1.200000e+02, %70
  %77 = fmul float 0x3FECCCCCE0000000, %74
  %78 = fadd float %77, %75
  %79 = fmul float 0x4000CCCCC0000000, %74
  %80 = fadd float %79, %76
  %81 = bitcast float %78 to i32
  %82 = bitcast float %80 to i32
  %83 = insertelement <2 x i32> undef, i32 %81, i32 0
  %84 = insertelement <2 x i32> %83, i32 %82, i32 1
  %85 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %84, <32 x i8> %50, <16 x i8> %52, i32 2)
  %86 = extractelement <4 x float> %85, i32 0
  %87 = extractelement <4 x float> %85, i32 1
  %88 = extractelement <4 x float> %85, i32 2
  %89 = fadd float -1.000000e+00, %86
  %90 = fadd float -1.000000e+00, %87
  %91 = fadd float 5.000000e-01, %88
  %92 = fmul float 1.560000e+02, %69
  %93 = fmul float 1.560000e+02, %70
  %94 = fsub float -0.000000e+00, %74
  %95 = fmul float 0x3FFCCCCCE0000000, %94
  %96 = fadd float %95, %92
  %97 = fsub float -0.000000e+00, %74
  %98 = fmul float 0x3FDCCCCCE0000000, %97
  %99 = fadd float %98, %93
  %100 = bitcast float %96 to i32
  %101 = bitcast float %99 to i32
  %102 = insertelement <2 x i32> undef, i32 %100, i32 0
  %103 = insertelement <2 x i32> %102, i32 %101, i32 1
  %104 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %103, <32 x i8> %50, <16 x i8> %52, i32 2)
  %105 = extractelement <4 x float> %104, i32 0
  %106 = extractelement <4 x float> %104, i32 1
  %107 = extractelement <4 x float> %104, i32 2
  %108 = fadd float %89, %105
  %109 = fadd float %90, %106
  %110 = fadd float %91, %107
  %111 = fmul float %108, %108
  %112 = fmul float %109, %109
  %113 = fadd float %112, %111
  %114 = fmul float %110, %110
  %115 = fadd float %113, %114
  %116 = call float @llvm.AMDGPU.rsq(float %115)
  %117 = fmul float %108, %116
  %118 = fmul float %109, %116
  %119 = fmul float %110, %116
  %120 = fsub float -0.000000e+00, %29
  %121 = fadd float %71, %120
  %122 = fsub float -0.000000e+00, %30
  %123 = fadd float %72, %122
  %124 = fsub float -0.000000e+00, %31
  %125 = fadd float %73, %124
  %126 = fmul float %121, %121
  %127 = fmul float %123, %123
  %128 = fadd float %127, %126
  %129 = fmul float %125, %125
  %130 = fadd float %128, %129
  %131 = call float @llvm.AMDGPU.rsq(float %130)
  %132 = fmul float %121, %131
  %133 = fmul float %123, %131
  %134 = fmul float %125, %131
  %135 = fdiv float 1.000000e+00, %68
  %136 = fmul float %65, %135
  %137 = fmul float %66, %135
  %138 = fmul float %136, 5.000000e-01
  %139 = fadd float %138, 5.000000e-01
  %140 = fmul float %137, 5.000000e-01
  %141 = fadd float %140, 5.000000e-01
  %142 = fsub float -0.000000e+00, %141
  %143 = fadd float 1.000000e+00, %142
  %144 = fadd float %139, %35
  %145 = fadd float %143, %36
  %146 = fsub float -0.000000e+00, %132
  %147 = fsub float -0.000000e+00, %133
  %148 = fsub float -0.000000e+00, %134
  %149 = fmul float %146, %117
  %150 = fmul float %147, %119
  %151 = fadd float %150, %149
  %152 = fmul float %148, %118
  %153 = fadd float %151, %152
  %154 = call float @llvm.AMDIL.clamp.(float %153, float 0.000000e+00, float 1.000000e+00)
  %155 = fmul float %154, 5.000000e-01
  %156 = fsub float -0.000000e+00, %155
  %157 = fadd float 1.000000e+00, %156
  %158 = call float @llvm.pow.f32(float %157, float 1.000000e+01)
  %159 = fmul float 0x3FE99999A0000000, %158
  %160 = fadd float %159, 0x3FC99999A0000000
  %161 = call float @llvm.AMDIL.clamp.(float %160, float 0.000000e+00, float 1.000000e+00)
  %162 = fsub float -0.000000e+00, %26
  %163 = fsub float -0.000000e+00, %132
  %164 = fadd float %162, %163
  %165 = fsub float -0.000000e+00, %27
  %166 = fsub float -0.000000e+00, %133
  %167 = fadd float %165, %166
  %168 = fsub float -0.000000e+00, %28
  %169 = fsub float -0.000000e+00, %134
  %170 = fadd float %168, %169
  %171 = fmul float %117, %132
  %172 = fmul float %119, %133
  %173 = fadd float %172, %171
  %174 = fmul float %118, %134
  %175 = fadd float %173, %174
  %176 = fmul float %175, %117
  %177 = fmul float %175, %119
  %178 = fmul float %175, %118
  %179 = fmul float 2.000000e+00, %176
  %180 = fmul float 2.000000e+00, %177
  %181 = fmul float 2.000000e+00, %178
  %182 = fsub float -0.000000e+00, %179
  %183 = fadd float %132, %182
  %184 = fsub float -0.000000e+00, %180
  %185 = fadd float %133, %184
  %186 = fsub float -0.000000e+00, %181
  %187 = fadd float %134, %186
  %188 = insertelement <4 x float> undef, float %183, i32 0
  %189 = insertelement <4 x float> %188, float %185, i32 1
  %190 = insertelement <4 x float> %189, float %187, i32 2
  %191 = insertelement <4 x float> %190, float 0.000000e+00, i32 3
  %192 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %191)
  %193 = extractelement <4 x float> %192, i32 0
  %194 = extractelement <4 x float> %192, i32 1
  %195 = extractelement <4 x float> %192, i32 2
  %196 = extractelement <4 x float> %192, i32 3
  %197 = call float @fabs(float %195)
  %198 = fdiv float 1.000000e+00, %197
  %199 = fmul float %193, %198
  %200 = fadd float %199, 1.500000e+00
  %201 = fmul float %194, %198
  %202 = fadd float %201, 1.500000e+00
  %203 = bitcast float %202 to i32
  %204 = bitcast float %200 to i32
  %205 = bitcast float %196 to i32
  %206 = insertelement <4 x i32> undef, i32 %203, i32 0
  %207 = insertelement <4 x i32> %206, i32 %204, i32 1
  %208 = insertelement <4 x i32> %207, i32 %205, i32 2
  %209 = insertelement <4 x i32> %208, i32 undef, i32 3
  %210 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %209, <32 x i8> %58, <16 x i8> %60, i32 4)
  %211 = extractelement <4 x float> %210, i32 0
  %212 = extractelement <4 x float> %210, i32 1
  %213 = extractelement <4 x float> %210, i32 2
  %214 = fdiv float 1.000000e+00, %68
  %215 = fmul float %67, %214
  %216 = fmul float %215, 5.000000e+00
  %217 = fsub float -0.000000e+00, %216
  %218 = fadd float 5.000000e+00, %217
  %219 = call float @llvm.AMDIL.clamp.(float %218, float 0.000000e+00, float 1.000000e+00)
  %220 = fmul float %117, %219
  %221 = fmul float %118, %219
  %222 = fmul float %220, 0x3FC99999A0000000
  %223 = fmul float %221, 0x3FC99999A0000000
  %224 = fsub float -0.000000e+00, %222
  %225 = fadd float %144, %224
  %226 = fsub float -0.000000e+00, %223
  %227 = fadd float %145, %226
  %228 = bitcast float %225 to i32
  %229 = bitcast float %227 to i32
  %230 = insertelement <2 x i32> undef, i32 %228, i32 0
  %231 = insertelement <2 x i32> %230, i32 %229, i32 1
  %232 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %231, <32 x i8> %42, <16 x i8> %44, i32 2)
  %233 = extractelement <4 x float> %232, i32 0
  %234 = extractelement <4 x float> %232, i32 1
  %235 = extractelement <4 x float> %232, i32 2
  %236 = fmul float %69, %24
  %237 = fmul float %70, %25
  %238 = bitcast float %236 to i32
  %239 = bitcast float %237 to i32
  %240 = insertelement <2 x i32> undef, i32 %238, i32 0
  %241 = insertelement <2 x i32> %240, i32 %239, i32 1
  %242 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %241, <32 x i8> %54, <16 x i8> %56, i32 2)
  %243 = extractelement <4 x float> %242, i32 0
  %244 = extractelement <4 x float> %242, i32 1
  %245 = extractelement <4 x float> %242, i32 2
  %246 = call float @llvm.AMDGPU.lrp(float 0x3FD3333340000000, float %243, float %233)
  %247 = call float @llvm.AMDGPU.lrp(float 0x3FD3333340000000, float %244, float %234)
  %248 = call float @llvm.AMDGPU.lrp(float 0x3FD3333340000000, float %245, float %235)
  %249 = fsub float -0.000000e+00, %161
  %250 = fadd float 1.000000e+00, %249
  %251 = fmul float %246, %250
  %252 = fmul float %247, %250
  %253 = fmul float %248, %250
  %254 = fmul float %211, %161
  %255 = fadd float %254, %251
  %256 = fmul float %212, %161
  %257 = fadd float %256, %252
  %258 = fmul float %213, %161
  %259 = fadd float %258, %253
  %260 = fadd float %71, 5.000000e-01
  %261 = fdiv float 1.000000e+00, %22
  %262 = fmul float %260, %261
  %263 = fadd float %73, 5.000000e-01
  %264 = fdiv float 1.000000e+00, %23
  %265 = fmul float %263, %264
  %266 = bitcast float %262 to i32
  %267 = bitcast float %265 to i32
  %268 = insertelement <2 x i32> undef, i32 %266, i32 0
  %269 = insertelement <2 x i32> %268, i32 %267, i32 1
  %270 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %269, <32 x i8> %62, <16 x i8> %64, i32 2)
  %271 = extractelement <4 x float> %270, i32 3
  %272 = fadd float %71, 5.000000e-01
  %273 = fadd float %73, 5.000000e-01
  %274 = fmul float %272, 3.906250e-03
  %275 = fmul float %273, 3.906250e-03
  %276 = fmul float %33, 0x3F947AE140000000
  %277 = fadd float %276, %274
  %278 = fmul float %33, 0x3F947AE140000000
  %279 = fadd float %278, %275
  %280 = bitcast float %277 to i32
  %281 = bitcast float %279 to i32
  %282 = insertelement <2 x i32> undef, i32 %280, i32 0
  %283 = insertelement <2 x i32> %282, i32 %281, i32 1
  %284 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %283, <32 x i8> %46, <16 x i8> %48, i32 2)
  %285 = extractelement <4 x float> %284, i32 0
  %286 = fmul float %33, 0x3FB99999A0000000
  %287 = call float @llvm.AMDIL.fraction.(float %286)
  %288 = fadd float %285, %287
  %289 = fmul float %288, 0x401921FB60000000
  %290 = call float @llvm.sin.f32(float %289)
  %291 = fmul float %290, 0x3FB99999A0000000
  %292 = fadd float %291, 5.000000e-01
  %293 = fadd float %271, %292
  %294 = call float @llvm.AMDIL.clamp.(float %293, float 0.000000e+00, float 1.000000e+00)
  %295 = call float @llvm.AMDGPU.lrp(float %32, float %294, float 1.000000e+00)
  %296 = fsub float -0.000000e+00, %71
  %297 = fadd float %29, %296
  %298 = fsub float -0.000000e+00, %72
  %299 = fadd float %30, %298
  %300 = fsub float -0.000000e+00, %73
  %301 = fadd float %31, %300
  %302 = fmul float %297, %297
  %303 = fmul float %299, %299
  %304 = fadd float %303, %302
  %305 = fmul float %301, %301
  %306 = fadd float %304, %305
  %307 = fadd float %306, -1.600000e+05
  %308 = fmul float %307, 0x3EAA36E2E0000000
  %309 = fcmp uge float %308, 5.000000e-01
  %310 = select i1 %309, float 5.000000e-01, float %308
  %311 = call float @llvm.AMDIL.clamp.(float %310, float 0.000000e+00, float 1.000000e+00)
  %312 = fmul float %297, %297
  %313 = fmul float %299, %299
  %314 = fadd float %313, %312
  %315 = fmul float %301, %301
  %316 = fadd float %314, %315
  %317 = call float @llvm.AMDGPU.rsq(float %316)
  %318 = fmul float %299, %317
  %319 = fsub float -0.000000e+00, %318
  %320 = fadd float 1.000000e+00, %319
  %321 = fmul float %311, %320
  %322 = call float @llvm.AMDGPU.lrp(float %321, float 5.000000e-01, float %255)
  %323 = call float @llvm.AMDGPU.lrp(float %321, float 5.000000e-01, float %257)
  %324 = call float @llvm.AMDGPU.lrp(float %321, float 5.000000e-01, float %259)
  %325 = fmul float %322, %295
  %326 = fmul float %323, %295
  %327 = fmul float %324, %295
  %328 = fmul float %164, %164
  %329 = fmul float %167, %167
  %330 = fadd float %329, %328
  %331 = fmul float %170, %170
  %332 = fadd float %330, %331
  %333 = call float @llvm.AMDGPU.rsq(float %332)
  %334 = fmul float %164, %333
  %335 = fmul float %167, %333
  %336 = fmul float %170, %333
  %337 = fmul float %334, %117
  %338 = fmul float %335, %119
  %339 = fadd float %338, %337
  %340 = fmul float %336, %118
  %341 = fadd float %339, %340
  %342 = call float @llvm.AMDIL.clamp.(float %341, float 0.000000e+00, float 1.000000e+00)
  %343 = fmul float %22, 0x3FECCCCCC0000000
  %344 = call float @llvm.pow.f32(float %342, float %343)
  %345 = fmul float %344, 3.000000e+00
  %346 = call float @llvm.AMDIL.clamp.(float %345, float 0.000000e+00, float 1.000000e+00)
  %347 = fmul float %346, %295
  %348 = fadd float %347, %325
  %349 = fmul float %346, %295
  %350 = fadd float %349, %326
  %351 = fmul float %346, %295
  %352 = fadd float %351, %327
  %353 = call float @llvm.AMDIL.clamp.(float %348, float 0.000000e+00, float 1.000000e+00)
  %354 = call float @llvm.AMDIL.clamp.(float %350, float 0.000000e+00, float 1.000000e+00)
  %355 = call float @llvm.AMDIL.clamp.(float %352, float 0.000000e+00, float 1.000000e+00)
  %356 = fmul float %69, %24
  %357 = fmul float %70, %25
  %358 = bitcast float %356 to i32
  %359 = bitcast float %357 to i32
  %360 = insertelement <2 x i32> undef, i32 %358, i32 0
  %361 = insertelement <2 x i32> %360, i32 %359, i32 1
  %362 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %361, <32 x i8> %38, <16 x i8> %40, i32 2)
  %363 = extractelement <4 x float> %362, i32 0
  %364 = fmul float %363, 0x4005C58860000000
  %365 = fadd float %364, 0xBFEFD70A40000000
  %366 = fmul float %365, 5.000000e+01
  %367 = call float @llvm.AMDIL.clamp.(float %366, float 0.000000e+00, float 1.000000e+00)
  %368 = fsub float -0.000000e+00, %367
  %369 = fadd float 1.000000e+00, %368
  %370 = call i32 @llvm.SI.packf16(float %353, float %354)
  %371 = bitcast i32 %370 to float
  %372 = call i32 @llvm.SI.packf16(float %355, float %369)
  %373 = bitcast i32 %372 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %371, float %373, float %371, float %373)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
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3f333333
d2820005
04161314
100a2f05
d2820005
04161b0a
100a0b18
d2820005
0415e110
100a0705
d2820005
04160702
d2060805
02010105
5e080905
100a26ff
3f333333
d2820005
04161316
100a2f05
d2820005
04161b0c
100a0b18
d2820005
0415e110
100a0705
d2820002
04160702
d2060802
02010102
c0800300
c0c20500
bf8c007f
f0800100
00010000
7e0202ff
bf7eb852
7e0602ff
402e2c43
bf8c0770
d2820000
04060700
100000ff
42480000
d2060800
02010100
080000f2
5e000102
f8001c0f
00040004
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL OUT[3], GENERIC[21]
DCL CONST[0..22]
DCL TEMP[0..5], LOCAL
IMM[0] FLT32 {   19.0000,     1.0000,     0.5000,     0.0000}
  0: MOV TEMP[0].y, IMM[0].xxxx
  1: MOV TEMP[0].x, IN[0].xxxx
  2: MOV TEMP[1].w, IMM[0].yyyy
  3: MOV TEMP[1].x, IN[0].xxxx
  4: MOV TEMP[1].y, IMM[0].xxxx
  5: MOV TEMP[1].z, IN[0].yyyy
  6: DP4 TEMP[2].x, TEMP[1], CONST[0]
  7: DP4 TEMP[3].x, TEMP[1], CONST[1]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[1], CONST[2]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: DP4 TEMP[1].x, TEMP[1], CONST[3]
 12: MOV TEMP[2].w, TEMP[1].xxxx
 13: MOV TEMP[1].xzw, TEMP[2].xxzw
 14: MOV TEMP[1].y, -TEMP[3].xxxx
 15: ADD TEMP[3].x, IN[0].xxxx, IMM[0].zzzz
 16: RCP TEMP[4].x, CONST[16].xxxx
 17: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 18: ADD TEMP[4].x, IN[0].yyyy, IMM[0].zzzz
 19: ADD TEMP[4].x, TEMP[4].xxxx, -CONST[16].yyyy
 20: RCP TEMP[5].x, -CONST[16].yyyy
 21: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 22: MOV TEMP[3].y, TEMP[4].xxxx
 23: MOV TEMP[0].zw, TEMP[0].yyxy
 24: MOV TEMP[4].x, IN[0].yyyy
 25: MOV TEMP[0].xy, TEMP[3].xyxx
 26: MOV OUT[1], TEMP[1]
 27: MOV OUT[3], TEMP[4]
 28: MOV OUT[0], TEMP[2]
 29: MOV OUT[2], TEMP[0]
 30: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
  %29 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %30, i32 0, i32 %5)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = fmul float %32, %11
  %35 = fmul float 1.900000e+01, %12
  %36 = fadd float %34, %35
  %37 = fmul float %33, %13
  %38 = fadd float %36, %37
  %39 = fmul float 1.000000e+00, %14
  %40 = fadd float %38, %39
  %41 = fmul float %32, %15
  %42 = fmul float 1.900000e+01, %16
  %43 = fadd float %41, %42
  %44 = fmul float %33, %17
  %45 = fadd float %43, %44
  %46 = fmul float 1.000000e+00, %18
  %47 = fadd float %45, %46
  %48 = fmul float %32, %19
  %49 = fmul float 1.900000e+01, %20
  %50 = fadd float %48, %49
  %51 = fmul float %33, %21
  %52 = fadd float %50, %51
  %53 = fmul float 1.000000e+00, %22
  %54 = fadd float %52, %53
  %55 = fmul float %32, %23
  %56 = fmul float 1.900000e+01, %24
  %57 = fadd float %55, %56
  %58 = fmul float %33, %25
  %59 = fadd float %57, %58
  %60 = fmul float 1.000000e+00, %26
  %61 = fadd float %59, %60
  %62 = fsub float -0.000000e+00, %47
  %63 = fadd float %32, 5.000000e-01
  %64 = fdiv float 1.000000e+00, %27
  %65 = fmul float %63, %64
  %66 = fadd float %33, 5.000000e-01
  %67 = fsub float -0.000000e+00, %28
  %68 = fadd float %66, %67
  %69 = fsub float -0.000000e+00, %28
  %70 = fdiv float 1.000000e+00, %69
  %71 = fmul float %68, %70
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %40, float %62, float %54, float %61)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %65, float %71, float %32, float 1.900000e+01)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %33, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %40, float %47, float %54, float %61)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800100
bf8c007f
c202010d
7e0202ff
41980000
bf8c007f
100c0204
c0820700
bf8c007f
e00c2000
80010200
c202010c
bf8c0070
d2820000
04180902
c202010e
bf8c007f
d2820000
04000903
c202010f
bf8c007f
06000004
c2020109
bf8c007f
100c0204
c2020108
bf8c007f
d2820006
04180902
c202010a
bf8c007f
d2820006
04180903
c202010b
bf8c007f
060c0c04
c2020101
bf8c007f
100e0204
c2020100
bf8c007f
d2820007
041c0902
c2020102
bf8c007f
d2820007
041c0903
c2020103
bf8c007f
060e0e04
c2020105
bf8c007f
10100204
c2020104
bf8c007f
d2820008
04200902
c2020106
bf8c007f
d2820008
04200903
c2020107
bf8c007f
06101004
d2060009
22010108
f800020f
00060907
bf8c070f
061204f0
c2020140
bf8c007f
7e145404
10121509
061406f0
c2000141
bf8c007f
0a141400
d206000b
22010000
7e16550b
1014170a
f800021f
01020a09
bf8c070f
7e020280
f800022f
01010103
f80008cf
00060807
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..22]
DCL TEMP[0..6], LOCAL
IMM[0] FLT32 {    0.5000, -160000.0000,     0.0000,     1.0000}
IMM[1] FLT32 {    0.0200,     0.0039,     0.1000,     6.2832}
  0: MOV TEMP[0].xy, IN[0].zwzz
  1: MOV TEMP[0].z, IN[1].xxxx
  2: MOV TEMP[1].xy, IN[0].xyyy
  3: TEX TEMP[1], TEMP[1], SAMP[0], 2D
  4: MOV TEMP[2].w, TEMP[1].wwww
  5: ADD TEMP[3].xyz, CONST[18].xyzz, -TEMP[0].xyzz
  6: ADD TEMP[4].x, IN[0].zzzz, IMM[0].xxxx
  7: RCP TEMP[5].x, CONST[16].xxxx
  8: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
  9: ADD TEMP[5].x, IN[1].xxxx, IMM[0].xxxx
 10: RCP TEMP[6].x, CONST[16].yyyy
 11: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 12: MOV TEMP[4].y, TEMP[5].xxxx
 13: DP3 TEMP[5].x, TEMP[3].xyzz, TEMP[3].xyzz
 14: ADD TEMP[5].x, TEMP[5].xxxx, IMM[0].yyyy
 15: MUL TEMP[5].x, TEMP[5].xxxx, IMM[0].zzzz
 16: MIN TEMP[5].x, TEMP[5].xxxx, IMM[0].xxxx
 17: MOV_SAT TEMP[5].x, TEMP[5].xxxx
 18: DP3 TEMP[6].x, TEMP[3].xyzz, TEMP[3].xyzz
 19: RSQ TEMP[6].x, TEMP[6].xxxx
 20: MUL TEMP[3].y, TEMP[3].xyzz, TEMP[6].xxxx
 21: ADD TEMP[3].x, IMM[0].wwww, -TEMP[3].yyyy
 22: MUL TEMP[3].x, TEMP[5].xxxx, TEMP[3].xxxx
 23: LRP TEMP[1].xyz, TEMP[3].xxxx, IMM[0].xxxx, TEMP[1].xyzz
 24: MOV TEMP[3].xy, TEMP[4].xyyy
 25: TEX TEMP[3].w, TEMP[3], SAMP[2], 2D
 26: ADD TEMP[0].xy, TEMP[0].xzzz, IMM[0].xxxx
 27: MUL TEMP[0].xy, TEMP[0].xyyy, IMM[1].yyyy
 28: MAD TEMP[0].xy, CONST[22].yyyy, IMM[1].xxxx, TEMP[0].xyyy
 29: MOV TEMP[0].xy, TEMP[0].xyyy
 30: TEX TEMP[0].x, TEMP[0], SAMP[1], 2D
 31: MUL TEMP[4].x, CONST[22].yyyy, IMM[1].zzzz
 32: FRC TEMP[4].x, TEMP[4].xxxx
 33: ADD TEMP[0].x, TEMP[0].xxxx, TEMP[4].xxxx
 34: MUL TEMP[0].x, TEMP[0].xxxx, IMM[1].wwww
 35: SIN TEMP[0].x, TEMP[0].xxxx
 36: MAD TEMP[0].x, TEMP[0].xxxx, IMM[1].zzzz, IMM[0].xxxx
 37: ADD_SAT TEMP[0].x, TEMP[3].wwww, TEMP[0].xxxx
 38: LRP TEMP[0].x, CONST[22].xxxx, TEMP[0].xxxx, IMM[0].wwww
 39: MUL TEMP[2].xyz, TEMP[1].xyzz, TEMP[0].xxxx
 40: MOV OUT[0], TEMP[2]
 41: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %29 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %30 = load <32 x i8> addrspace(2)* %29, !tbaa !0
  %31 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0
  %35 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %43 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %44 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %45 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %46 = bitcast float %41 to i32
  %47 = bitcast float %42 to i32
  %48 = insertelement <2 x i32> undef, i32 %46, i32 0
  %49 = insertelement <2 x i32> %48, i32 %47, i32 1
  %50 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %49, <32 x i8> %30, <16 x i8> %32, i32 2)
  %51 = extractelement <4 x float> %50, i32 0
  %52 = extractelement <4 x float> %50, i32 1
  %53 = extractelement <4 x float> %50, i32 2
  %54 = extractelement <4 x float> %50, i32 3
  %55 = fsub float -0.000000e+00, %43
  %56 = fadd float %24, %55
  %57 = fsub float -0.000000e+00, %44
  %58 = fadd float %25, %57
  %59 = fsub float -0.000000e+00, %45
  %60 = fadd float %26, %59
  %61 = fadd float %43, 5.000000e-01
  %62 = fdiv float 1.000000e+00, %22
  %63 = fmul float %61, %62
  %64 = fadd float %45, 5.000000e-01
  %65 = fdiv float 1.000000e+00, %23
  %66 = fmul float %64, %65
  %67 = fmul float %56, %56
  %68 = fmul float %58, %58
  %69 = fadd float %68, %67
  %70 = fmul float %60, %60
  %71 = fadd float %69, %70
  %72 = fadd float %71, -1.600000e+05
  %73 = fmul float %72, 0x3EAA36E2E0000000
  %74 = fcmp uge float %73, 5.000000e-01
  %75 = select i1 %74, float 5.000000e-01, float %73
  %76 = call float @llvm.AMDIL.clamp.(float %75, float 0.000000e+00, float 1.000000e+00)
  %77 = fmul float %56, %56
  %78 = fmul float %58, %58
  %79 = fadd float %78, %77
  %80 = fmul float %60, %60
  %81 = fadd float %79, %80
  %82 = call float @llvm.AMDGPU.rsq(float %81)
  %83 = fmul float %58, %82
  %84 = fsub float -0.000000e+00, %83
  %85 = fadd float 1.000000e+00, %84
  %86 = fmul float %76, %85
  %87 = call float @llvm.AMDGPU.lrp(float %86, float 5.000000e-01, float %51)
  %88 = call float @llvm.AMDGPU.lrp(float %86, float 5.000000e-01, float %52)
  %89 = call float @llvm.AMDGPU.lrp(float %86, float 5.000000e-01, float %53)
  %90 = bitcast float %63 to i32
  %91 = bitcast float %66 to i32
  %92 = insertelement <2 x i32> undef, i32 %90, i32 0
  %93 = insertelement <2 x i32> %92, i32 %91, i32 1
  %94 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %93, <32 x i8> %38, <16 x i8> %40, i32 2)
  %95 = extractelement <4 x float> %94, i32 3
  %96 = fadd float %43, 5.000000e-01
  %97 = fadd float %45, 5.000000e-01
  %98 = fmul float %96, 3.906250e-03
  %99 = fmul float %97, 3.906250e-03
  %100 = fmul float %28, 0x3F947AE140000000
  %101 = fadd float %100, %98
  %102 = fmul float %28, 0x3F947AE140000000
  %103 = fadd float %102, %99
  %104 = bitcast float %101 to i32
  %105 = bitcast float %103 to i32
  %106 = insertelement <2 x i32> undef, i32 %104, i32 0
  %107 = insertelement <2 x i32> %106, i32 %105, i32 1
  %108 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %107, <32 x i8> %34, <16 x i8> %36, i32 2)
  %109 = extractelement <4 x float> %108, i32 0
  %110 = fmul float %28, 0x3FB99999A0000000
  %111 = call float @llvm.AMDIL.fraction.(float %110)
  %112 = fadd float %109, %111
  %113 = fmul float %112, 0x401921FB60000000
  %114 = call float @llvm.sin.f32(float %113)
  %115 = fmul float %114, 0x3FB99999A0000000
  %116 = fadd float %115, 5.000000e-01
  %117 = fadd float %95, %116
  %118 = call float @llvm.AMDIL.clamp.(float %117, float 0.000000e+00, float 1.000000e+00)
  %119 = call float @llvm.AMDGPU.lrp(float %27, float %118, float 1.000000e+00)
  %120 = fmul float %87, %119
  %121 = fmul float %88, %119
  %122 = fmul float %89, %119
  %123 = call i32 @llvm.SI.packf16(float %120, float %121)
  %124 = bitcast i32 %123 to float
  %125 = call i32 @llvm.SI.packf16(float %122, float %54)
  %126 = bitcast i32 %125 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %124, float %126, float %124, float %126)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080300
c8090301
c0840100
bf8c007f
c2000949
bf8c007f
08040400
c8200200
c8210201
c2000948
bf8c007f
08061000
10060703
d2820003
040e0502
c8240400
c8250401
c200094a
bf8c007f
08081200
d2820003
040e0904
060806ff
c81c4000
100808ff
3551b717
d00c0000
0201e104
d2000004
0001e104
d2060804
02010104
7e065b03
10040702
080404f2
10040504
080604f2
c8140100
c8150101
c8100000
c8110001
c0860300
c0c80500
bf8c007f
f0800f00
00640404
bf8c0770
10000b03
d2820000
0401e102
060212f0
101202ff
3b800000
c2000959
7e1602ff
3ca3d70a
bf8c007f
d282000a
04261600
061010f0
101810ff
3b800000
d2820009
04321600
c0860304
c0c80508
bf8c007f
f0800100
00640a09
7e1202ff
3dcccccd
10161200
7e16410b
bf8c0770
0614170a
101414ff
40c90fdb
101414ff
3e22f983
7e146b0a
d2820009
03c2130a
c2000941
bf8c007f
7e145400
10161501
c2000940
bf8c007f
7e025400
10140308
c0800308
c0c60510
bf8c007f
f0800800
0003010a
bf8c0770
06021301
d2060801
02010101
c2000958
bf8c007f
d2080008
020000f2
d2820001
04220200
10000300
10100903
d2820008
0421e102
10100308
5e000108
10060d03
d2820002
040de102
10020302
5e020f01
f8001c0f
01000100
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..22]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0100,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xz, IN[0].xyzx
  2: MOV TEMP[0].xzw, TEMP[0].xxzw
  3: ADD TEMP[1].x, IN[0].yyyy, IMM[0].xxxx
  4: MOV TEMP[0].y, TEMP[1].xxxx
  5: DP4 TEMP[1].x, TEMP[0], CONST[0]
  6: DP4 TEMP[2].x, TEMP[0], CONST[1]
  7: MOV TEMP[1].y, TEMP[2].xxxx
  8: DP4 TEMP[2].x, TEMP[0], CONST[3]
  9: MOV TEMP[1].w, TEMP[2].xxxx
 10: MOV TEMP[1].xyw, TEMP[1].xyxw
 11: MOV TEMP[2].w, IMM[0].yyyy
 12: MUL TEMP[2].xyz, CONST[20].xyzz, IMM[0].zzzz
 13: ADD TEMP[2], TEMP[0], -TEMP[2]
 14: DP4 TEMP[2].x, TEMP[2], CONST[2]
 15: MOV TEMP[1].z, TEMP[2].xxxx
 16: MOV TEMP[2].xy, IN[1].xyxx
 17: MOV TEMP[2].zw, TEMP[0].yyxy
 18: MOV TEMP[0].x, TEMP[0].zzzz
 19: MOV OUT[0], TEMP[1]
 20: MOV OUT[2], TEMP[0]
 21: MOV OUT[1], TEMP[2]
 22: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
  %30 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
  %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %5)
  %33 = extractelement <4 x float> %32, i32 0
  %34 = extractelement <4 x float> %32, i32 1
  %35 = extractelement <4 x float> %32, i32 2
  %36 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
  %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %37, i32 0, i32 %5)
  %39 = extractelement <4 x float> %38, i32 0
  %40 = extractelement <4 x float> %38, i32 1
  %41 = fadd float %34, 1.000000e+00
  %42 = fmul float %33, %11
  %43 = fmul float %41, %12
  %44 = fadd float %42, %43
  %45 = fmul float %35, %13
  %46 = fadd float %44, %45
  %47 = fmul float 1.000000e+00, %14
  %48 = fadd float %46, %47
  %49 = fmul float %33, %15
  %50 = fmul float %41, %16
  %51 = fadd float %49, %50
  %52 = fmul float %35, %17
  %53 = fadd float %51, %52
  %54 = fmul float 1.000000e+00, %18
  %55 = fadd float %53, %54
  %56 = fmul float %33, %23
  %57 = fmul float %41, %24
  %58 = fadd float %56, %57
  %59 = fmul float %35, %25
  %60 = fadd float %58, %59
  %61 = fmul float 1.000000e+00, %26
  %62 = fadd float %60, %61
  %63 = fmul float %27, 0x3F847AE140000000
  %64 = fmul float %28, 0x3F847AE140000000
  %65 = fmul float %29, 0x3F847AE140000000
  %66 = fsub float -0.000000e+00, %63
  %67 = fadd float %33, %66
  %68 = fsub float -0.000000e+00, %64
  %69 = fadd float %41, %68
  %70 = fsub float -0.000000e+00, %65
  %71 = fadd float %35, %70
  %72 = fsub float -0.000000e+00, 0.000000e+00
  %73 = fadd float 1.000000e+00, %72
  %74 = fmul float %67, %19
  %75 = fmul float %69, %20
  %76 = fadd float %74, %75
  %77 = fmul float %71, %21
  %78 = fadd float %76, %77
  %79 = fmul float %73, %22
  %80 = fadd float %78, %79
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %39, float %40, float %33, float %41)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %35, float %41, float %35, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %48, float %55, float %80, float %62)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840700
bf8c007f
e00c2000
80020100
c0820704
bf8c0070
e00c2000
80010500
060004f2
bf8c0770
f800020f
00010605
bf8c070f
7e0a02f2
f800021f
05030003
c0800100
bf8c000f
c2020150
7e0a02ff
3c23d70a
bf8c007f
100c0a04
080c0d01
c2020151
bf8c007f
100e0a04
080e0f00
c2020109
bf8c007f
100e0e04
c2020108
bf8c007f
d2820006
041c0906
c2020152
bf8c007f
100a0a04
080a0b03
c202010a
bf8c007f
d2820005
04180905
c202010b
bf8c007f
060a0a04
c202010d
bf8c007f
100c0004
c202010c
bf8c007f
d2820006
04180901
c202010e
bf8c007f
d2820006
04180903
c202010f
bf8c007f
060c0c04
c2020105
bf8c007f
100e0004
c2020104
bf8c007f
d2820007
041c0901
c2020106
bf8c007f
d2820007
041c0903
c2020107
bf8c007f
060e0e04
c2020101
bf8c007f
10000004
c2020100
bf8c007f
d2820000
04000901
c2020102
bf8c007f
d2820000
04000903
c2000103
bf8c007f
06000000
f80008cf
06050700
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..31]
DCL TEMP[0..7], LOCAL
IMM[0] FLT32 {    0.5000,     0.8000,     0.2000,     1.2000}
IMM[1] FLT32 {    1.0000,     0.0200,     0.0039,     0.1000}
IMM[2] FLT32 {    6.2832, -160000.0000,     0.0000,   200.0000}
IMM[3] FLT32 {    3.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].zwzz
  1: MOV TEMP[0].z, IN[1].xxxx
  2: MOV TEMP[1].xy, IN[0].xyyy
  3: TEX TEMP[1], TEMP[1], SAMP[1], 2D
  4: MOV TEMP[2].w, TEMP[1].wwww
  5: MOV TEMP[3].xy, IN[0].xyyy
  6: TEX TEMP[3], TEMP[3], SAMP[0], 2D
  7: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz
  8: RSQ TEMP[4].x, TEMP[4].xxxx
  9: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[4].xxxx
 10: MUL TEMP[4].xyz, TEMP[3].xxxx, CONST[28].xyzz
 11: MUL TEMP[4].xyz, TEMP[1].xyzz, TEMP[4].xyzz
 12: LRP TEMP[1].xyz, TEMP[3].xxxx, TEMP[4].xyzz, TEMP[1].xyzz
 13: MUL TEMP[4].xyz, TEMP[3].yyyy, CONST[29].xyzz
 14: MUL TEMP[4].xyz, TEMP[1].xyzz, TEMP[4].xyzz
 15: LRP TEMP[1].xyz, TEMP[3].yyyy, TEMP[4].xyzz, TEMP[1].xyzz
 16: MUL TEMP[4].xyz, TEMP[3].zzzz, CONST[30].xyzz
 17: MUL TEMP[4].xyz, TEMP[1].xyzz, TEMP[4].xyzz
 18: LRP TEMP[2].xyz, TEMP[3].zzzz, TEMP[4].xyzz, TEMP[1].xyzz
 19: DP3 TEMP[1].x, TEMP[0].xyzz, -CONST[17].xyzz
 20: MAD TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx, IMM[0].xxxx
 21: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 22: MAD TEMP[1].x, IMM[0].yyyy, TEMP[1].xxxx, IMM[0].zzzz
 23: MUL TEMP[1].xyz, TEMP[1].xxxx, TEMP[2].xyzz
 24: MUL_SAT TEMP[1].xyz, TEMP[1].xyzz, IMM[0].wwww
 25: ADD TEMP[4].x, IN[1].yyyy, IMM[0].xxxx
 26: RCP TEMP[5].x, CONST[16].xxxx
 27: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 28: ADD TEMP[5].x, IN[1].wwww, IMM[0].xxxx
 29: RCP TEMP[6].x, CONST[16].yyyy
 30: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 31: MOV TEMP[4].y, TEMP[5].xxxx
 32: MOV TEMP[4].xy, TEMP[4].xyyy
 33: TEX TEMP[4].w, TEMP[4], SAMP[3], 2D
 34: ADD TEMP[5].xy, IN[1].ywww, IMM[0].xxxx
 35: MUL TEMP[5].xy, TEMP[5].xyyy, IMM[1].zzzz
 36: MAD TEMP[5].xy, CONST[22].yyyy, IMM[1].yyyy, TEMP[5].xyyy
 37: MOV TEMP[5].xy, TEMP[5].xyyy
 38: TEX TEMP[5].x, TEMP[5], SAMP[2], 2D
 39: MUL TEMP[6].x, CONST[22].yyyy, IMM[1].wwww
 40: FRC TEMP[6].x, TEMP[6].xxxx
 41: ADD TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 42: MUL TEMP[5].x, TEMP[5].xxxx, IMM[2].xxxx
 43: SIN TEMP[5].x, TEMP[5].xxxx
 44: MAD TEMP[5].x, TEMP[5].xxxx, IMM[1].wwww, IMM[0].xxxx
 45: ADD_SAT TEMP[4].x, TEMP[4].wwww, TEMP[5].xxxx
 46: LRP TEMP[4].x, CONST[22].xxxx, TEMP[4].xxxx, IMM[1].xxxx
 47: ADD TEMP[5].xyz, CONST[18].xyzz, -IN[1].yzww
 48: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
 49: ADD TEMP[6].x, TEMP[6].xxxx, IMM[2].yyyy
 50: MUL TEMP[6].x, TEMP[6].xxxx, IMM[2].zzzz
 51: MIN TEMP[6].x, TEMP[6].xxxx, IMM[0].xxxx
 52: MOV_SAT TEMP[6].x, TEMP[6].xxxx
 53: DP3 TEMP[7].x, TEMP[5].xyzz, TEMP[5].xyzz
 54: RSQ TEMP[7].x, TEMP[7].xxxx
 55: MUL TEMP[5].y, TEMP[5].xyzz, TEMP[7].xxxx
 56: ADD TEMP[5].x, IMM[1].xxxx, -TEMP[5].yyyy
 57: MUL TEMP[5].x, TEMP[6].xxxx, TEMP[5].xxxx
 58: LRP TEMP[1].xyz, TEMP[5].xxxx, IMM[0].xxxx, TEMP[1].xyzz
 59: MUL TEMP[2].xyz, TEMP[1].xyzz, TEMP[4].xxxx
 60: ADD TEMP[1].xyz, IN[1].yzww, -CONST[18].xyzz
 61: DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[1].xyzz
 62: RSQ TEMP[5].x, TEMP[5].xxxx
 63: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[5].xxxx
 64: ADD TEMP[1].xyz, -TEMP[1].xyzz, -CONST[17].xyzz
 65: DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[1].xyzz
 66: RSQ TEMP[5].x, TEMP[5].xxxx
 67: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[5].xxxx
 68: DP3_SAT TEMP[0].x, TEMP[1].xyzz, TEMP[0].xyzz
 69: POW TEMP[0].x, TEMP[0].xxxx, IMM[2].wwww
 70: MUL_SAT TEMP[0].x, TEMP[0].xxxx, IMM[3].xxxx
 71: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[3].wwww
 72: MAD_SAT TEMP[0].xyz, TEMP[0].xxxx, TEMP[4].xxxx, TEMP[2].xyzz
 73: MOV TEMP[2].xyz, TEMP[0].xyzx
 74: MOV OUT[0], TEMP[2]
 75: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 276)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 280)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 448)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 452)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 456)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 484)
  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 488)
  %41 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %42 = load <32 x i8> addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %46 = load <32 x i8> addrspace(2)* %45, !tbaa !0
  %47 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %50 = load <32 x i8> addrspace(2)* %49, !tbaa !0
  %51 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %54 = load <32 x i8> addrspace(2)* %53, !tbaa !0
  %55 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %59 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %60 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %61 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %62 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %63 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %64 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %65 = bitcast float %57 to i32
  %66 = bitcast float %58 to i32
  %67 = insertelement <2 x i32> undef, i32 %65, i32 0
  %68 = insertelement <2 x i32> %67, i32 %66, i32 1
  %69 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %68, <32 x i8> %46, <16 x i8> %48, i32 2)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = extractelement <4 x float> %69, i32 2
  %73 = extractelement <4 x float> %69, i32 3
  %74 = bitcast float %57 to i32
  %75 = bitcast float %58 to i32
  %76 = insertelement <2 x i32> undef, i32 %74, i32 0
  %77 = insertelement <2 x i32> %76, i32 %75, i32 1
  %78 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %77, <32 x i8> %42, <16 x i8> %44, i32 2)
  %79 = extractelement <4 x float> %78, i32 0
  %80 = extractelement <4 x float> %78, i32 1
  %81 = extractelement <4 x float> %78, i32 2
  %82 = extractelement <4 x float> %78, i32 3
  %83 = fmul float %59, %59
  %84 = fmul float %60, %60
  %85 = fadd float %84, %83
  %86 = fmul float %61, %61
  %87 = fadd float %85, %86
  %88 = call float @llvm.AMDGPU.rsq(float %87)
  %89 = fmul float %59, %88
  %90 = fmul float %60, %88
  %91 = fmul float %61, %88
  %92 = fmul float %79, %32
  %93 = fmul float %79, %33
  %94 = fmul float %79, %34
  %95 = fmul float %70, %92
  %96 = fmul float %71, %93
  %97 = fmul float %72, %94
  %98 = call float @llvm.AMDGPU.lrp(float %79, float %95, float %70)
  %99 = call float @llvm.AMDGPU.lrp(float %79, float %96, float %71)
  %100 = call float @llvm.AMDGPU.lrp(float %79, float %97, float %72)
  %101 = fmul float %80, %35
  %102 = fmul float %80, %36
  %103 = fmul float %80, %37
  %104 = fmul float %98, %101
  %105 = fmul float %99, %102
  %106 = fmul float %100, %103
  %107 = call float @llvm.AMDGPU.lrp(float %80, float %104, float %98)
  %108 = call float @llvm.AMDGPU.lrp(float %80, float %105, float %99)
  %109 = call float @llvm.AMDGPU.lrp(float %80, float %106, float %100)
  %110 = fmul float %81, %38
  %111 = fmul float %81, %39
  %112 = fmul float %81, %40
  %113 = fmul float %107, %110
  %114 = fmul float %108, %111
  %115 = fmul float %109, %112
  %116 = call float @llvm.AMDGPU.lrp(float %81, float %113, float %107)
  %117 = call float @llvm.AMDGPU.lrp(float %81, float %114, float %108)
  %118 = call float @llvm.AMDGPU.lrp(float %81, float %115, float %109)
  %119 = fsub float -0.000000e+00, %24
  %120 = fsub float -0.000000e+00, %25
  %121 = fsub float -0.000000e+00, %26
  %122 = fmul float %89, %119
  %123 = fmul float %90, %120
  %124 = fadd float %123, %122
  %125 = fmul float %91, %121
  %126 = fadd float %124, %125
  %127 = fmul float %126, 5.000000e-01
  %128 = fadd float %127, 5.000000e-01
  %129 = fmul float %128, %128
  %130 = fmul float 0x3FE99999A0000000, %129
  %131 = fadd float %130, 0x3FC99999A0000000
  %132 = fmul float %131, %116
  %133 = fmul float %131, %117
  %134 = fmul float %131, %118
  %135 = fmul float %132, 0x3FF3333340000000
  %136 = fmul float %133, 0x3FF3333340000000
  %137 = fmul float %134, 0x3FF3333340000000
  %138 = call float @llvm.AMDIL.clamp.(float %135, float 0.000000e+00, float 1.000000e+00)
  %139 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
  %140 = call float @llvm.AMDIL.clamp.(float %137, float 0.000000e+00, float 1.000000e+00)
  %141 = fadd float %62, 5.000000e-01
  %142 = fdiv float 1.000000e+00, %22
  %143 = fmul float %141, %142
  %144 = fadd float %64, 5.000000e-01
  %145 = fdiv float 1.000000e+00, %23
  %146 = fmul float %144, %145
  %147 = bitcast float %143 to i32
  %148 = bitcast float %146 to i32
  %149 = insertelement <2 x i32> undef, i32 %147, i32 0
  %150 = insertelement <2 x i32> %149, i32 %148, i32 1
  %151 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %150, <32 x i8> %54, <16 x i8> %56, i32 2)
  %152 = extractelement <4 x float> %151, i32 3
  %153 = fadd float %62, 5.000000e-01
  %154 = fadd float %64, 5.000000e-01
  %155 = fmul float %153, 3.906250e-03
  %156 = fmul float %154, 3.906250e-03
  %157 = fmul float %31, 0x3F947AE140000000
  %158 = fadd float %157, %155
  %159 = fmul float %31, 0x3F947AE140000000
  %160 = fadd float %159, %156
  %161 = bitcast float %158 to i32
  %162 = bitcast float %160 to i32
  %163 = insertelement <2 x i32> undef, i32 %161, i32 0
  %164 = insertelement <2 x i32> %163, i32 %162, i32 1
  %165 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %164, <32 x i8> %50, <16 x i8> %52, i32 2)
  %166 = extractelement <4 x float> %165, i32 0
  %167 = fmul float %31, 0x3FB99999A0000000
  %168 = call float @llvm.AMDIL.fraction.(float %167)
  %169 = fadd float %166, %168
  %170 = fmul float %169, 0x401921FB60000000
  %171 = call float @llvm.sin.f32(float %170)
  %172 = fmul float %171, 0x3FB99999A0000000
  %173 = fadd float %172, 5.000000e-01
  %174 = fadd float %152, %173
  %175 = call float @llvm.AMDIL.clamp.(float %174, float 0.000000e+00, float 1.000000e+00)
  %176 = call float @llvm.AMDGPU.lrp(float %30, float %175, float 1.000000e+00)
  %177 = fsub float -0.000000e+00, %62
  %178 = fadd float %27, %177
  %179 = fsub float -0.000000e+00, %63
  %180 = fadd float %28, %179
  %181 = fsub float -0.000000e+00, %64
  %182 = fadd float %29, %181
  %183 = fmul float %178, %178
  %184 = fmul float %180, %180
  %185 = fadd float %184, %183
  %186 = fmul float %182, %182
  %187 = fadd float %185, %186
  %188 = fadd float %187, -1.600000e+05
  %189 = fmul float %188, 0x3EAA36E2E0000000
  %190 = fcmp uge float %189, 5.000000e-01
  %191 = select i1 %190, float 5.000000e-01, float %189
  %192 = call float @llvm.AMDIL.clamp.(float %191, float 0.000000e+00, float 1.000000e+00)
  %193 = fmul float %178, %178
  %194 = fmul float %180, %180
  %195 = fadd float %194, %193
  %196 = fmul float %182, %182
  %197 = fadd float %195, %196
  %198 = call float @llvm.AMDGPU.rsq(float %197)
  %199 = fmul float %180, %198
  %200 = fsub float -0.000000e+00, %199
  %201 = fadd float 1.000000e+00, %200
  %202 = fmul float %192, %201
  %203 = call float @llvm.AMDGPU.lrp(float %202, float 5.000000e-01, float %138)
  %204 = call float @llvm.AMDGPU.lrp(float %202, float 5.000000e-01, float %139)
  %205 = call float @llvm.AMDGPU.lrp(float %202, float 5.000000e-01, float %140)
  %206 = fmul float %203, %176
  %207 = fmul float %204, %176
  %208 = fmul float %205, %176
  %209 = fsub float -0.000000e+00, %27
  %210 = fadd float %62, %209
  %211 = fsub float -0.000000e+00, %28
  %212 = fadd float %63, %211
  %213 = fsub float -0.000000e+00, %29
  %214 = fadd float %64, %213
  %215 = fmul float %210, %210
  %216 = fmul float %212, %212
  %217 = fadd float %216, %215
  %218 = fmul float %214, %214
  %219 = fadd float %217, %218
  %220 = call float @llvm.AMDGPU.rsq(float %219)
  %221 = fmul float %210, %220
  %222 = fmul float %212, %220
  %223 = fmul float %214, %220
  %224 = fsub float -0.000000e+00, %221
  %225 = fsub float -0.000000e+00, %24
  %226 = fadd float %224, %225
  %227 = fsub float -0.000000e+00, %222
  %228 = fsub float -0.000000e+00, %25
  %229 = fadd float %227, %228
  %230 = fsub float -0.000000e+00, %223
  %231 = fsub float -0.000000e+00, %26
  %232 = fadd float %230, %231
  %233 = fmul float %226, %226
  %234 = fmul float %229, %229
  %235 = fadd float %234, %233
  %236 = fmul float %232, %232
  %237 = fadd float %235, %236
  %238 = call float @llvm.AMDGPU.rsq(float %237)
  %239 = fmul float %226, %238
  %240 = fmul float %229, %238
  %241 = fmul float %232, %238
  %242 = fmul float %239, %89
  %243 = fmul float %240, %90
  %244 = fadd float %243, %242
  %245 = fmul float %241, %91
  %246 = fadd float %244, %245
  %247 = call float @llvm.AMDIL.clamp.(float %246, float 0.000000e+00, float 1.000000e+00)
  %248 = call float @llvm.pow.f32(float %247, float 2.000000e+02)
  %249 = fmul float %248, 3.000000e+00
  %250 = call float @llvm.AMDIL.clamp.(float %249, float 0.000000e+00, float 1.000000e+00)
  %251 = fmul float %250, %82
  %252 = fmul float %251, %176
  %253 = fadd float %252, %206
  %254 = fmul float %251, %176
  %255 = fadd float %254, %207
  %256 = fmul float %251, %176
  %257 = fadd float %256, %208
  %258 = call float @llvm.AMDIL.clamp.(float %253, float 0.000000e+00, float 1.000000e+00)
  %259 = call float @llvm.AMDIL.clamp.(float %255, float 0.000000e+00, float 1.000000e+00)
  %260 = call float @llvm.AMDIL.clamp.(float %257, float 0.000000e+00, float 1.000000e+00)
  %261 = call i32 @llvm.SI.packf16(float %258, float %259)
  %262 = bitcast i32 %261 to float
  %263 = call i32 @llvm.SI.packf16(float %260, float %73)
  %264 = bitcast i32 %263 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %262, float %264, float %262, float %264)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c81c0100
c81d0101
c8180000
c8190001
c0840304
c0c60508
bf8c007f
f0800f00
00430206
c0840300
c0c60500
bf8c0070
f0800f00
00430606
bf8c0770
08140cf2
1016070a
c0840100
bf8c007f
c2000971
bf8c007f
10180c00
10181903
d282000c
042e1906
08160ef2
101a190b
c2000975
bf8c007f
101c0e00
10181d0c
d282000d
04361907
081810f2
101c1b0c
c2000979
bf8c007f
101e1000
101a1f0d
d2820011
043a1b08
c8340300
c8350301
c8380200
c8390201
101e1d0e
d282000f
043e1b0d
c8400400
c8410401
d282000f
043e2110
7e245b0f
101c250e
c2000944
bf8c007f
10261c00
101e250d
c2038945
bf8c007f
d206000d
22010007
101a1b0f
081a270d
10202510
c2008946
bf8c007f
10242001
081a250d
d282000d
03c1e10d
101a1b0d
7e2402ff
3e4ccccd
7e2602ff
3f4ccccd
d282000d
044a270d
1022230d
102222ff
3f99999a
d2060811
02010111
c8480600
c8490601
c2060949
bf8c007f
082a240c
c84c0500
c84d0501
c2068948
bf8c007f
0828260d
10282914
d2820016
04522b15
c8500700
c8510701
c203094a
bf8c007f
08002806
d2820000
045a0100
060200ff
c81c4000
100202ff
3551b717
d00c000e
0201e101
d2000001
0039e101
d2060801
02010101
7e005b00
10000115
080000f2
10000101
080200f2
10222301
d2820015
0445e100
062228f0
102c22ff
3b800000
c2070959
7e3202ff
3ca3d70a
bf8c007f
d2820018
045a320e
062c26f0
10342cff
3b800000
d2820017
046a320e
c0880308
c0ca0510
bf8c007f
f0800100
00851817
7e2e02ff
3dcccccd
10322e0e
7e324119
bf8c0770
06303318
103030ff
40c90fdb
103030ff
3e22f983
7e306b18
d2820017
03c22f18
c2070941
bf8c007f
7e30540e
10323111
c2070940
bf8c007f
7e22540e
10302316
c088030c
c0ca0518
bf8c007f
f0800800
00851118
bf8c0770
06222f11
d2060811
02010111
c2010958
bf8c007f
d2080016
020004f2
d2820011
045a2202
102a2315
0a2e240c
0a2c260d
10242d16
d2820013
044a2f17
0a242806
d2820013
044e2512
7e285b13
10262917
d2060013
22010113
0a262607
102c2916
d2060016
22010116
0a2c2c00
102e2d16
d2820017
045e2713
10242912
d2060012
22010112
0a242401
d2820014
045e2512
7e285b14
10262913
102c2916
101c1d16
d282000e
043a1f13
101e2912
d282000e
043a210f
d206080e
0201010e
7e1c4f0e
0e1c1cff
43480000
7e1c4b0e
101c1cff
40400000
d206080e
0201010e
101c130e
d282000f
0456230e
d206080f
0201010f
1020050a
c2000970
bf8c007f
10240c00
10242502
d2820010
04422506
1024210b
c2000974
bf8c007f
10260e00
10202710
d2820010
044a2107
1024210c
c2000978
bf8c007f
10261000
10202710
d2820010
044a2108
1020210d
102020ff
3f99999a
d2060810
02010110
10202101
d2820010
0441e100
10202310
d2820010
0442230e
d2060810
02010110
5e1e1f10
1014090a
c2000972
bf8c007f
10200c00
10202104
d282000a
042a2106
1016150b
c2000976
bf8c007f
10200e00
1014210a
d282000a
042e1507
1016150c
c200097a
bf8c007f
10181000
1014190a
d2820006
042e1508
100c0d0d
100c0cff
3f99999a
d2060806
02010106
10020d01
d2820000
0405e100
10002300
d2820000
0402230e
d2060800
02010100
5e000b00
f8001c0f
000f000f
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..31]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MUL TEMP[0].xyz, IN[0].xyzz, CONST[31].xxxx
  2: DP4 TEMP[1].x, TEMP[0], CONST[23]
  3: DP4 TEMP[2].x, TEMP[0], CONST[24]
  4: MOV TEMP[1].y, TEMP[2].xxxx
  5: DP4 TEMP[2].x, TEMP[0], CONST[25]
  6: MOV TEMP[1].z, TEMP[2].xxxx
  7: DP4 TEMP[0].x, TEMP[0], CONST[26]
  8: MOV TEMP[1].w, TEMP[0].xxxx
  9: DP3 TEMP[0].x, IN[1].xyzz, CONST[23].xyzz
 10: DP3 TEMP[2].x, IN[1].xyzz, CONST[24].xyzz
 11: MOV TEMP[0].y, TEMP[2].xxxx
 12: DP3 TEMP[2].x, IN[1].xyzz, CONST[25].xyzz
 13: MOV TEMP[0].z, TEMP[2].xxxx
 14: DP4 TEMP[2].x, TEMP[1], CONST[0]
 15: DP4 TEMP[3].x, TEMP[1], CONST[1]
 16: MOV TEMP[2].y, TEMP[3].xxxx
 17: DP4 TEMP[3].x, TEMP[1], CONST[2]
 18: MOV TEMP[2].z, TEMP[3].xxxx
 19: DP4 TEMP[3].x, TEMP[1], CONST[3]
 20: MOV TEMP[2].w, TEMP[3].xxxx
 21: DP3 TEMP[3].x, TEMP[0].xyzz, TEMP[0].xyzz
 22: RSQ TEMP[3].x, TEMP[3].xxxx
 23: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[3].xxxx
 24: MOV TEMP[3].xy, IN[2].xyxx
 25: MOV TEMP[3].zw, TEMP[0].yyxy
 26: MOV TEMP[0].x, TEMP[0].zzzz
 27: MOV TEMP[0].yzw, TEMP[1].yxyz
 28: MOV OUT[2], TEMP[0]
 29: MOV OUT[0], TEMP[2]
 30: MOV OUT[1], TEMP[3]
 31: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 428)
  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
  %44 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %45 = load <16 x i8> addrspace(2)* %44, !tbaa !0
  %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %45, i32 0, i32 %5)
  %47 = extractelement <4 x float> %46, i32 0
  %48 = extractelement <4 x float> %46, i32 1
  %49 = extractelement <4 x float> %46, i32 2
  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
  %53 = extractelement <4 x float> %52, i32 0
  %54 = extractelement <4 x float> %52, i32 1
  %55 = extractelement <4 x float> %52, i32 2
  %56 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %57 = load <16 x i8> addrspace(2)* %56, !tbaa !0
  %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %57, i32 0, i32 %5)
  %59 = extractelement <4 x float> %58, i32 0
  %60 = extractelement <4 x float> %58, i32 1
  %61 = fmul float %47, %43
  %62 = fmul float %48, %43
  %63 = fmul float %49, %43
  %64 = fmul float %61, %27
  %65 = fmul float %62, %28
  %66 = fadd float %64, %65
  %67 = fmul float %63, %29
  %68 = fadd float %66, %67
  %69 = fmul float 1.000000e+00, %30
  %70 = fadd float %68, %69
  %71 = fmul float %61, %31
  %72 = fmul float %62, %32
  %73 = fadd float %71, %72
  %74 = fmul float %63, %33
  %75 = fadd float %73, %74
  %76 = fmul float 1.000000e+00, %34
  %77 = fadd float %75, %76
  %78 = fmul float %61, %35
  %79 = fmul float %62, %36
  %80 = fadd float %78, %79
  %81 = fmul float %63, %37
  %82 = fadd float %80, %81
  %83 = fmul float 1.000000e+00, %38
  %84 = fadd float %82, %83
  %85 = fmul float %61, %39
  %86 = fmul float %62, %40
  %87 = fadd float %85, %86
  %88 = fmul float %63, %41
  %89 = fadd float %87, %88
  %90 = fmul float 1.000000e+00, %42
  %91 = fadd float %89, %90
  %92 = fmul float %53, %27
  %93 = fmul float %54, %28
  %94 = fadd float %93, %92
  %95 = fmul float %55, %29
  %96 = fadd float %94, %95
  %97 = fmul float %53, %31
  %98 = fmul float %54, %32
  %99 = fadd float %98, %97
  %100 = fmul float %55, %33
  %101 = fadd float %99, %100
  %102 = fmul float %53, %35
  %103 = fmul float %54, %36
  %104 = fadd float %103, %102
  %105 = fmul float %55, %37
  %106 = fadd float %104, %105
  %107 = fmul float %70, %11
  %108 = fmul float %77, %12
  %109 = fadd float %107, %108
  %110 = fmul float %84, %13
  %111 = fadd float %109, %110
  %112 = fmul float %91, %14
  %113 = fadd float %111, %112
  %114 = fmul float %70, %15
  %115 = fmul float %77, %16
  %116 = fadd float %114, %115
  %117 = fmul float %84, %17
  %118 = fadd float %116, %117
  %119 = fmul float %91, %18
  %120 = fadd float %118, %119
  %121 = fmul float %70, %19
  %122 = fmul float %77, %20
  %123 = fadd float %121, %122
  %124 = fmul float %84, %21
  %125 = fadd float %123, %124
  %126 = fmul float %91, %22
  %127 = fadd float %125, %126
  %128 = fmul float %70, %23
  %129 = fmul float %77, %24
  %130 = fadd float %128, %129
  %131 = fmul float %84, %25
  %132 = fadd float %130, %131
  %133 = fmul float %91, %26
  %134 = fadd float %132, %133
  %135 = fmul float %96, %96
  %136 = fmul float %101, %101
  %137 = fadd float %136, %135
  %138 = fmul float %106, %106
  %139 = fadd float %137, %138
  %140 = call float @llvm.AMDGPU.rsq(float %139)
  %141 = fmul float %96, %140
  %142 = fmul float %101, %140
  %143 = fmul float %106, %140
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %59, float %60, float %141, float %142)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %143, float %70, float %77, float %84)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %113, float %120, float %127, float %134)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020160
bf8c007f
100a0204
c2040161
bf8c007f
d2820005
04141102
c2048162
bf8c007f
d2820005
04141303
c202815c
bf8c007f
100c0205
c205015d
bf8c007f
d2820006
04181502
c205815e
bf8c007f
d2820006
04181703
100e0d06
d2820007
041e0b05
c2060164
bf8c007f
1010020c
c2070165
bf8c007f
d2820008
04201d02
c2068166
bf8c007f
d2820001
04201b03
d2820002
041e0301
7e045b02
10060505
10080506
c0880708
bf8c007f
e00c2000
80040500
bf8c0770
f800020f
03040605
bf8c070f
100c0501
c0880700
bf8c007f
e00c2000
80040700
c203017c
bf8c0070
10060e06
10081006
1000080e
d2820000
04001903
100a1206
d2820000
04001b05
c2030167
bf8c007f
06000006
10020808
d2820001
04040903
d2820001
04041305
c2020163
bf8c007f
06020204
1004080a
d2820002
04080b03
d2820002
04081705
c202015f
bf8c007f
06040404
f800021f
00010206
c202010d
bf8c000f
100c0204
c202010c
bf8c007f
d2820006
04180902
c202010e
bf8c007f
d2820006
04180900
c2020169
bf8c007f
10080804
c2020168
bf8c007f
d2820003
04100903
c202016a
bf8c007f
d2820003
040c0905
c202016b
bf8c007f
06060604
c202010f
bf8c007f
d2820004
04180903
c2020109
bf8c007f
100a0204
c2020108
bf8c007f
d2820005
04140902
c202010a
bf8c007f
d2820005
04140900
c202010b
bf8c007f
d2820005
04140903
c2020105
bf8c007f
100c0204
c2020104
bf8c007f
d2820006
04180902
c2020106
bf8c007f
d2820006
04180900
c2020107
bf8c007f
d2820006
04180903
c2020101
bf8c007f
10020204
c2020100
bf8c007f
d2820001
04040902
c2020102
bf8c007f
d2820000
04040900
c2000103
bf8c007f
d2820000
04000103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..22]
DCL TEMP[0..4], LOCAL
IMM[0] FLT32 {    1.0000,     0.5000, -160000.0000,     0.0000}
IMM[1] FLT32 {    0.0033,     0.0000,     0.0000,     0.0000}
  0: ADD TEMP[0].xyz, IN[0].xyzz, -CONST[18].xyzz
  1: DP3 TEMP[1].x, TEMP[0].xyzz, TEMP[0].xyzz
  2: RSQ TEMP[1].x, TEMP[1].xxxx
  3: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx
  4: MOV TEMP[0].xyz, TEMP[0].xyzz
  5: TEX TEMP[0].xyz, TEMP[0], SAMP[0], CUBE
  6: ADD TEMP[1].xyz, CONST[18].xyzz, -IN[0].xyzz
  7: MOV TEMP[2].w, IMM[0].xxxx
  8: DP3 TEMP[3].x, TEMP[1].xyzz, TEMP[1].xyzz
  9: ADD TEMP[3].x, TEMP[3].xxxx, IMM[0].zzzz
 10: MUL TEMP[3].x, TEMP[3].xxxx, IMM[0].wwww
 11: MIN TEMP[3].x, TEMP[3].xxxx, IMM[0].yyyy
 12: MOV_SAT TEMP[3].x, TEMP[3].xxxx
 13: DP3 TEMP[4].x, TEMP[1].xyzz, TEMP[1].xyzz
 14: RSQ TEMP[4].x, TEMP[4].xxxx
 15: MUL TEMP[1].y, TEMP[1].xyzz, TEMP[4].xxxx
 16: ADD TEMP[1].x, IMM[0].xxxx, -TEMP[1].yyyy
 17: MUL TEMP[1].x, TEMP[3].xxxx, TEMP[1].xxxx
 18: LRP TEMP[1].xyz, TEMP[1].xxxx, IMM[0].yyyy, TEMP[0].xyzz
 19: MUL_SAT TEMP[3].x, IN[0].yyyy, IMM[1].xxxx
 20: LRP TEMP[0].xyz, TEMP[3].xxxx, TEMP[0].xyzz, TEMP[1].xyzz
 21: MOV_SAT TEMP[2].xyz, TEMP[0].xyzz
 22: MOV OUT[0], TEMP[2]
 23: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %25 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %26 = load <32 x i8> addrspace(2)* %25, !tbaa !0
  %27 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %30 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %32 = fsub float -0.000000e+00, %22
  %33 = fadd float %29, %32
  %34 = fsub float -0.000000e+00, %23
  %35 = fadd float %30, %34
  %36 = fsub float -0.000000e+00, %24
  %37 = fadd float %31, %36
  %38 = fmul float %33, %33
  %39 = fmul float %35, %35
  %40 = fadd float %39, %38
  %41 = fmul float %37, %37
  %42 = fadd float %40, %41
  %43 = call float @llvm.AMDGPU.rsq(float %42)
  %44 = fmul float %33, %43
  %45 = fmul float %35, %43
  %46 = fmul float %37, %43
  %47 = insertelement <4 x float> undef, float %44, i32 0
  %48 = insertelement <4 x float> %47, float %45, i32 1
  %49 = insertelement <4 x float> %48, float %46, i32 2
  %50 = insertelement <4 x float> %49, float 0.000000e+00, i32 3
  %51 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %50)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = extractelement <4 x float> %51, i32 1
  %54 = extractelement <4 x float> %51, i32 2
  %55 = extractelement <4 x float> %51, i32 3
  %56 = call float @fabs(float %54)
  %57 = fdiv float 1.000000e+00, %56
  %58 = fmul float %52, %57
  %59 = fadd float %58, 1.500000e+00
  %60 = fmul float %53, %57
  %61 = fadd float %60, 1.500000e+00
  %62 = bitcast float %61 to i32
  %63 = bitcast float %59 to i32
  %64 = bitcast float %55 to i32
  %65 = insertelement <4 x i32> undef, i32 %62, i32 0
  %66 = insertelement <4 x i32> %65, i32 %63, i32 1
  %67 = insertelement <4 x i32> %66, i32 %64, i32 2
  %68 = insertelement <4 x i32> %67, i32 undef, i32 3
  %69 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %68, <32 x i8> %26, <16 x i8> %28, i32 4)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = extractelement <4 x float> %69, i32 2
  %73 = fsub float -0.000000e+00, %29
  %74 = fadd float %22, %73
  %75 = fsub float -0.000000e+00, %30
  %76 = fadd float %23, %75
  %77 = fsub float -0.000000e+00, %31
  %78 = fadd float %24, %77
  %79 = fmul float %74, %74
  %80 = fmul float %76, %76
  %81 = fadd float %80, %79
  %82 = fmul float %78, %78
  %83 = fadd float %81, %82
  %84 = fadd float %83, -1.600000e+05
  %85 = fmul float %84, 0x3EAA36E2E0000000
  %86 = fcmp uge float %85, 5.000000e-01
  %87 = select i1 %86, float 5.000000e-01, float %85
  %88 = call float @llvm.AMDIL.clamp.(float %87, float 0.000000e+00, float 1.000000e+00)
  %89 = fmul float %74, %74
  %90 = fmul float %76, %76
  %91 = fadd float %90, %89
  %92 = fmul float %78, %78
  %93 = fadd float %91, %92
  %94 = call float @llvm.AMDGPU.rsq(float %93)
  %95 = fmul float %76, %94
  %96 = fsub float -0.000000e+00, %95
  %97 = fadd float 1.000000e+00, %96
  %98 = fmul float %88, %97
  %99 = call float @llvm.AMDGPU.lrp(float %98, float 5.000000e-01, float %70)
  %100 = call float @llvm.AMDGPU.lrp(float %98, float 5.000000e-01, float %71)
  %101 = call float @llvm.AMDGPU.lrp(float %98, float 5.000000e-01, float %72)
  %102 = fmul float %30, 0x3F6B4E81C0000000
  %103 = call float @llvm.AMDIL.clamp.(float %102, float 0.000000e+00, float 1.000000e+00)
  %104 = call float @llvm.AMDGPU.lrp(float %103, float %70, float %99)
  %105 = call float @llvm.AMDGPU.lrp(float %103, float %71, float %100)
  %106 = call float @llvm.AMDGPU.lrp(float %103, float %72, float %101)
  %107 = call float @llvm.AMDIL.clamp.(float %104, float 0.000000e+00, float 1.000000e+00)
  %108 = call float @llvm.AMDIL.clamp.(float %105, float 0.000000e+00, float 1.000000e+00)
  %109 = call float @llvm.AMDIL.clamp.(float %106, float 0.000000e+00, float 1.000000e+00)
  %110 = call i32 @llvm.SI.packf16(float %107, float %108)
  %111 = bitcast i32 %110 to float
  %112 = call i32 @llvm.SI.packf16(float %109, float 1.000000e+00)
  %113 = bitcast i32 %112 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %111, float %113, float %111, float %113)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080100
c8090101
c0840100
bf8c007f
c2000949
bf8c007f
0a0a0400
c80c0000
c80d0001
c2008948
bf8c007f
0a0c0601
10080d06
d2820007
04120b05
c8100200
c8110201
c203094a
bf8c007f
0a000806
d2820001
041e0100
7e025b01
101c0305
101a0306
101e0300
7e200280
d28a0006
043e1d0d
d28c0005
043e1d0d
d28e0007
043e1d0d
d2880008
043e1d0d
d2060100
02010107
7e005500
7e0202ff
3fc00000
d2820007
04060105
d2820006
04060106
c0840300
c0c60500
bf8c007f
f0800700
00430506
08000400
08020601
10020301
d2820001
04060100
08060806
d2820001
04060703
060602ff
c81c4000
100606ff
3551b717
d00c0000
0201e103
d2000003
0001e103
d2060803
02010103
7e025b01
10000300
080000f2
10000103
080200f2
bf8c0770
10060d01
d2820004
040de100
100404ff
3b5a740e
d2060802
02010102
080604f2
10080903
d2820004
04120d02
d2060804
02010104
10100b01
d2820008
0421e100
10101103
d2820008
04220b02
d2060808
02010108
5e080908
10020f01
d2820000
0405e100
10000103
d2820000
04020f02
d2060800
02010100
d25e0000
0201e500
f8001c0f
00040004
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..22]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].xxxx
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: DP4 TEMP[1].x, TEMP[0], CONST[12]
  3: DP4 TEMP[2].x, TEMP[0], CONST[13]
  4: MOV TEMP[1].y, TEMP[2].xxxx
  5: DP4 TEMP[2].x, TEMP[0], CONST[14]
  6: MOV TEMP[1].z, TEMP[2].xxxx
  7: DP4 TEMP[2].x, TEMP[0], CONST[15]
  8: RCP TEMP[2].x, TEMP[2].xxxx
  9: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xxxx
 10: MOV TEMP[1].xyz, TEMP[1].xyzx
 11: MOV OUT[1], TEMP[1]
 12: MOV OUT[0], TEMP[0]
 13: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 252)
  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
  %30 = extractelement <4 x float> %29, i32 0
  %31 = extractelement <4 x float> %29, i32 1
  %32 = fmul float %30, %11
  %33 = fmul float %31, %12
  %34 = fadd float %32, %33
  %35 = fmul float 1.000000e+00, %13
  %36 = fadd float %34, %35
  %37 = fmul float 1.000000e+00, %14
  %38 = fadd float %36, %37
  %39 = fmul float %30, %15
  %40 = fmul float %31, %16
  %41 = fadd float %39, %40
  %42 = fmul float 1.000000e+00, %17
  %43 = fadd float %41, %42
  %44 = fmul float 1.000000e+00, %18
  %45 = fadd float %43, %44
  %46 = fmul float %30, %19
  %47 = fmul float %31, %20
  %48 = fadd float %46, %47
  %49 = fmul float 1.000000e+00, %21
  %50 = fadd float %48, %49
  %51 = fmul float 1.000000e+00, %22
  %52 = fadd float %50, %51
  %53 = fmul float %30, %23
  %54 = fmul float %31, %24
  %55 = fadd float %53, %54
  %56 = fmul float 1.000000e+00, %25
  %57 = fadd float %55, %56
  %58 = fmul float 1.000000e+00, %26
  %59 = fadd float %57, %58
  %60 = fdiv float 1.000000e+00, %59
  %61 = fmul float %38, %60
  %62 = fmul float %45, %60
  %63 = fmul float %52, %60
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %61, float %62, float %63, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %30, float %31, float 1.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0820700
bf8c007f
e00c2000
80010000
c0800100
bf8c0070
c2020139
bf8c007f
10080204
c2020138
bf8c007f
d2820004
04100900
c202013a
bf8c007f
06080804
c202013b
bf8c007f
06080804
c202013d
bf8c007f
100a0204
c202013c
bf8c007f
d2820005
04140900
c202013e
bf8c007f
060a0a04
c202013f
bf8c007f
060a0a04
7e0a5505
10080b04
c2020135
bf8c007f
100c0204
c2020134
bf8c007f
d2820006
04180900
c2020136
bf8c007f
060c0c04
c2020137
bf8c007f
060c0c04
100c0b06
c2020131
bf8c007f
100e0204
c2020130
bf8c007f
d2820007
041c0900
c2020132
bf8c007f
060e0e04
c2000133
bf8c007f
060e0e00
100a0b07
7e0e0280
f800020f
07040605
bf8c070f
7e0802f2
f80008cf
04040100
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0..5], LOCAL
IMM[0] FLT32 {    0.0000,     2.0000,     4.0000,     6.0000}
IMM[1] FLT32 {    0.7200,     1.0000,     0.1667,     0.5000}
IMM[2] FLT32 {   -1.0000,     1.0000,     0.0000,     3.0000}
IMM[3] FLT32 {    5.0000,     1.1000,     1.0000,    -0.0300}
IMM[4] FLT32 {    1.2195,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
  2: MOV_SAT TEMP[0].xyz, TEMP[0].xyzz
  3: MOV TEMP[1].xy, IMM[0].xxxx
  4: MAX TEMP[2].x, TEMP[0].yyyy, TEMP[0].zzzz
  5: MAX TEMP[2].x, TEMP[0].xxxx, TEMP[2].xxxx
  6: MOV TEMP[1].z, TEMP[2].xxxx
  7: MIN TEMP[3].x, TEMP[0].yyyy, TEMP[0].zzzz
  8: MIN TEMP[3].x, TEMP[0].xxxx, TEMP[3].xxxx
  9: ADD TEMP[3].x, TEMP[2].xxxx, -TEMP[3].xxxx
 10: FSNE TEMP[4].x, TEMP[3].xxxx, IMM[0].xxxx
 11: UIF TEMP[4].xxxx :0
 12:   RCP TEMP[4].x, TEMP[2].xxxx
 13:   MUL TEMP[4].x, TEMP[3].xxxx, TEMP[4].xxxx
 14:   MOV TEMP[1].y, TEMP[4].xxxx
 15:   ADD TEMP[4].xyz, TEMP[0].yzxx, -TEMP[0].zxyy
 16:   RCP TEMP[3].x, TEMP[3].xxxx
 17:   MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[3].xxxx
 18:   ADD TEMP[4].xy, TEMP[3].yzzz, IMM[0].yzzz
 19:   FSEQ TEMP[5].x, TEMP[0].xxxx, TEMP[2].xxxx
 20:   UIF TEMP[5].xxxx :0
 21:     MOV TEMP[1].x, TEMP[3].xxxx
 22:   ELSE :0
 23:     FSEQ TEMP[0].x, TEMP[0].yyyy, TEMP[2].xxxx
 24:     UIF TEMP[0].xxxx :0
 25:       MOV TEMP[1].x, TEMP[4].xxxx
 26:     ELSE :0
 27:       MOV TEMP[1].x, TEMP[4].yyyy
 28:     ENDIF
 29:   ENDIF
 30: ENDIF
 31: MUL TEMP[0].xy, TEMP[1].yzzz, IMM[1].xyyy
 32: MUL TEMP[2].x, TEMP[1].xxxx, IMM[1].zzzz
 33: FRC TEMP[2].x, TEMP[2].xxxx
 34: MUL TEMP[1].x, IMM[0].wwww, TEMP[2].xxxx
 35: FSNE TEMP[2].x, TEMP[0].xxxx, IMM[0].xxxx
 36: UIF TEMP[2].xxxx :0
 37:   MUL TEMP[2].x, TEMP[0].xxxx, TEMP[0].yyyy
 38:   MUL TEMP[3].x, TEMP[1].xxxx, IMM[1].wwww
 39:   FRC TEMP[3].x, TEMP[3].xxxx
 40:   MAD TEMP[3].x, IMM[0].yyyy, TEMP[3].xxxx, IMM[2].xxxx
 41:   ABS TEMP[3].x, TEMP[3].xxxx
 42:   ADD TEMP[3].x, IMM[1].yyyy, -TEMP[3].xxxx
 43:   FSLT TEMP[4].x, TEMP[1].xxxx, IMM[1].yyyy
 44:   UIF TEMP[4].xxxx :0
 45:     MOV TEMP[4].xz, IMM[2].yyzy
 46:     MOV TEMP[4].y, TEMP[3].xxxx
 47:     MOV TEMP[4].xyz, TEMP[4].xyzx
 48:   ELSE :0
 49:     FSLT TEMP[5].x, TEMP[1].xxxx, IMM[0].yyyy
 50:     UIF TEMP[5].xxxx :0
 51:       MOV TEMP[5].yz, IMM[2].zyzz
 52:       MOV TEMP[5].x, TEMP[3].xxxx
 53:       MOV TEMP[4].xyz, TEMP[5].xyzx
 54:     ELSE :0
 55:       FSLT TEMP[5].x, TEMP[1].xxxx, IMM[2].wwww
 56:       UIF TEMP[5].xxxx :0
 57:         MOV TEMP[5].xy, IMM[2].zyzz
 58:         MOV TEMP[5].z, TEMP[3].xxxx
 59:         MOV TEMP[4].xyz, TEMP[5].xyzx
 60:       ELSE :0
 61:         FSLT TEMP[5].x, TEMP[1].xxxx, IMM[0].zzzz
 62:         UIF TEMP[5].xxxx :0
 63:           MOV TEMP[5].xz, IMM[2].zzyz
 64:           MOV TEMP[5].y, TEMP[3].xxxx
 65:           MOV TEMP[4].xyz, TEMP[5].xyzx
 66:         ELSE :0
 67:           FSLT TEMP[1].x, TEMP[1].xxxx, IMM[3].xxxx
 68:           UIF TEMP[1].xxxx :0
 69:             MOV TEMP[1].yz, IMM[2].yzyy
 70:             MOV TEMP[1].x, TEMP[3].xxxx
 71:             MOV TEMP[4].xyz, TEMP[1].xyzx
 72:           ELSE :0
 73:             MOV TEMP[1].xy, IMM[2].yzyy
 74:             MOV TEMP[1].z, TEMP[3].xxxx
 75:             MOV TEMP[4].xyz, TEMP[1].xyzx
 76:           ENDIF
 77:         ENDIF
 78:       ENDIF
 79:     ENDIF
 80:   ENDIF
 81:   ADD TEMP[1].x, TEMP[0].yyyy, -TEMP[2].xxxx
 82:   MAD_SAT TEMP[1].xyz, TEMP[4].xyzz, TEMP[2].xxxx, TEMP[1].xxxx
 83:   MOV TEMP[1].xyz, TEMP[1].xyzx
 84: ELSE :0
 85:   MOV_SAT TEMP[1].xyz, TEMP[0].yyyy
 86: ENDIF
 87: MOV TEMP[0].w, IMM[1].yyyy
 88: MUL_SAT TEMP[1].xyz, TEMP[1].xyzz, IMM[3].yzzz
 89: ADD_SAT TEMP[1].xyz, TEMP[1].xyzz, IMM[3].wwww
 90: MUL_SAT TEMP[1].xyz, TEMP[1].xyzz, IMM[4].xxxx
 91: MOV TEMP[0].xyz, TEMP[1].xyzx
 92: MOV OUT[0], TEMP[0]
 93: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float 1.000000e+00)
  %35 = call float @llvm.AMDIL.clamp.(float %32, float 0.000000e+00, float 1.000000e+00)
  %36 = call float @llvm.AMDIL.clamp.(float %33, float 0.000000e+00, float 1.000000e+00)
  %37 = fcmp uge float %35, %36
  %38 = select i1 %37, float %35, float %36
  %39 = fcmp uge float %34, %38
  %40 = select i1 %39, float %34, float %38
  %41 = fcmp uge float %35, %36
  %42 = select i1 %41, float %36, float %35
  %43 = fcmp uge float %34, %42
  %44 = select i1 %43, float %42, float %34
  %45 = fsub float -0.000000e+00, %44
  %46 = fadd float %40, %45
  %47 = fcmp une float %46, 0.000000e+00
  %48 = sext i1 %47 to i32
  %49 = bitcast i32 %48 to float
  %50 = bitcast float %49 to i32
  %51 = icmp ne i32 %50, 0
  br i1 %51, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %52 = fdiv float 1.000000e+00, %40
  %53 = fmul float %46, %52
  %54 = fsub float -0.000000e+00, %36
  %55 = fadd float %35, %54
  %56 = fsub float -0.000000e+00, %34
  %57 = fadd float %36, %56
  %58 = fsub float -0.000000e+00, %35
  %59 = fadd float %34, %58
  %60 = fdiv float 1.000000e+00, %46
  %61 = fmul float %55, %60
  %62 = fmul float %57, %60
  %63 = fmul float %59, %60
  %64 = fadd float %62, 2.000000e+00
  %65 = fadd float %63, 4.000000e+00
  %66 = fcmp oeq float %34, %40
  %67 = sext i1 %66 to i32
  %68 = bitcast i32 %67 to float
  %69 = bitcast float %68 to i32
  %70 = icmp ne i32 %69, 0
  br i1 %70, label %ENDIF, label %ELSE26

ENDIF:                                            ; preds = %ELSE26, %IF, %main_body
  %temp4.0 = phi float [ 0.000000e+00, %main_body ], [ %., %ELSE26 ], [ %61, %IF ]
  %temp5.0 = phi float [ 0.000000e+00, %main_body ], [ %53, %IF ], [ %53, %ELSE26 ]
  %71 = fmul float %temp5.0, 0x3FE70A3D80000000
  %72 = fmul float %40, 1.000000e+00
  %73 = fmul float %temp4.0, 0x3FC5555560000000
  %74 = call float @llvm.AMDIL.fraction.(float %73)
  %75 = fmul float 6.000000e+00, %74
  %76 = fcmp une float %71, 0.000000e+00
  %77 = sext i1 %76 to i32
  %78 = bitcast i32 %77 to float
  %79 = bitcast float %78 to i32
  %80 = icmp ne i32 %79, 0
  br i1 %80, label %IF31, label %ELSE32

ELSE26:                                           ; preds = %IF
  %81 = fcmp oeq float %35, %40
  %82 = sext i1 %81 to i32
  %83 = bitcast i32 %82 to float
  %84 = bitcast float %83 to i32
  %85 = icmp ne i32 %84, 0
  %. = select i1 %85, float %64, float %65
  br label %ENDIF

IF31:                                             ; preds = %ENDIF
  %86 = fmul float %71, %72
  %87 = fmul float %75, 5.000000e-01
  %88 = call float @llvm.AMDIL.fraction.(float %87)
  %89 = fmul float 2.000000e+00, %88
  %90 = fadd float %89, -1.000000e+00
  %91 = call float @fabs(float %90)
  %92 = fsub float -0.000000e+00, %91
  %93 = fadd float 1.000000e+00, %92
  %94 = fcmp olt float %75, 1.000000e+00
  %95 = sext i1 %94 to i32
  %96 = bitcast i32 %95 to float
  %97 = bitcast float %96 to i32
  %98 = icmp ne i32 %97, 0
  br i1 %98, label %ENDIF33, label %ELSE35

ELSE32:                                           ; preds = %ENDIF
  %99 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
  %100 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
  %101 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
  br label %ENDIF30

ENDIF30:                                          ; preds = %ELSE32, %ENDIF33
  %temp4.3 = phi float [ %137, %ENDIF33 ], [ %99, %ELSE32 ]
  %temp5.1 = phi float [ %138, %ENDIF33 ], [ %100, %ELSE32 ]
  %temp6.0 = phi float [ %139, %ENDIF33 ], [ %101, %ELSE32 ]
  %102 = fmul float %temp4.3, 0x3FF19999A0000000
  %103 = fmul float %temp5.1, 1.000000e+00
  %104 = fmul float %temp6.0, 1.000000e+00
  %105 = call float @llvm.AMDIL.clamp.(float %102, float 0.000000e+00, float 1.000000e+00)
  %106 = call float @llvm.AMDIL.clamp.(float %103, float 0.000000e+00, float 1.000000e+00)
  %107 = call float @llvm.AMDIL.clamp.(float %104, float 0.000000e+00, float 1.000000e+00)
  %108 = fadd float %105, 0xBF9EB851E0000000
  %109 = fadd float %106, 0xBF9EB851E0000000
  %110 = fadd float %107, 0xBF9EB851E0000000
  %111 = call float @llvm.AMDIL.clamp.(float %108, float 0.000000e+00, float 1.000000e+00)
  %112 = call float @llvm.AMDIL.clamp.(float %109, float 0.000000e+00, float 1.000000e+00)
  %113 = call float @llvm.AMDIL.clamp.(float %110, float 0.000000e+00, float 1.000000e+00)
  %114 = fmul float %111, 0x3FF3831F20000000
  %115 = fmul float %112, 0x3FF3831F20000000
  %116 = fmul float %113, 0x3FF3831F20000000
  %117 = call float @llvm.AMDIL.clamp.(float %114, float 0.000000e+00, float 1.000000e+00)
  %118 = call float @llvm.AMDIL.clamp.(float %115, float 0.000000e+00, float 1.000000e+00)
  %119 = call float @llvm.AMDIL.clamp.(float %116, float 0.000000e+00, float 1.000000e+00)
  %120 = call i32 @llvm.SI.packf16(float %117, float %118)
  %121 = bitcast i32 %120 to float
  %122 = call i32 @llvm.SI.packf16(float %119, float 1.000000e+00)
  %123 = bitcast i32 %122 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %121, float %123, float %121, float %123)
  ret void

ELSE35:                                           ; preds = %IF31
  %124 = fcmp olt float %75, 2.000000e+00
  %125 = sext i1 %124 to i32
  %126 = bitcast i32 %125 to float
  %127 = bitcast float %126 to i32
  %128 = icmp ne i32 %127, 0
  br i1 %128, label %ENDIF33, label %ELSE38

ENDIF33:                                          ; preds = %ELSE44, %ELSE41, %ELSE38, %ELSE35, %IF31
  %temp16.0 = phi float [ 1.000000e+00, %IF31 ], [ %93, %ELSE35 ], [ 0.000000e+00, %ELSE38 ], [ %.48, %ELSE44 ], [ 0.000000e+00, %ELSE41 ]
  %temp17.0 = phi float [ %93, %IF31 ], [ 1.000000e+00, %ELSE35 ], [ 1.000000e+00, %ELSE38 ], [ 0.000000e+00, %ELSE44 ], [ %93, %ELSE41 ]
  %temp18.0 = phi float [ 0.000000e+00, %IF31 ], [ 0.000000e+00, %ELSE35 ], [ %93, %ELSE38 ], [ %.49, %ELSE44 ], [ 1.000000e+00, %ELSE41 ]
  %129 = fsub float -0.000000e+00, %86
  %130 = fadd float %72, %129
  %131 = fmul float %temp16.0, %86
  %132 = fadd float %131, %130
  %133 = fmul float %temp17.0, %86
  %134 = fadd float %133, %130
  %135 = fmul float %temp18.0, %86
  %136 = fadd float %135, %130
  %137 = call float @llvm.AMDIL.clamp.(float %132, float 0.000000e+00, float 1.000000e+00)
  %138 = call float @llvm.AMDIL.clamp.(float %134, float 0.000000e+00, float 1.000000e+00)
  %139 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
  br label %ENDIF30

ELSE38:                                           ; preds = %ELSE35
  %140 = fcmp olt float %75, 3.000000e+00
  %141 = sext i1 %140 to i32
  %142 = bitcast i32 %141 to float
  %143 = bitcast float %142 to i32
  %144 = icmp ne i32 %143, 0
  br i1 %144, label %ENDIF33, label %ELSE41

ELSE41:                                           ; preds = %ELSE38
  %145 = fcmp olt float %75, 4.000000e+00
  %146 = sext i1 %145 to i32
  %147 = bitcast i32 %146 to float
  %148 = bitcast float %147 to i32
  %149 = icmp ne i32 %148, 0
  br i1 %149, label %ENDIF33, label %ELSE44

ELSE44:                                           ; preds = %ELSE41
  %150 = fcmp olt float %75, 5.000000e+00
  %151 = sext i1 %150 to i32
  %152 = bitcast i32 %151 to float
  %153 = bitcast float %152 to i32
  %154 = icmp ne i32 %153, 0
  %.48 = select i1 %154, float %93, float 1.000000e+00
  %.49 = select i1 %154, float 1.000000e+00, float %93
  br label %ENDIF33
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: readonly
declare float @fabs(float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800700
00010502
bf8c0770
d2060804
02010107
d2060801
02010106
d00c0000
02020901
d2000000
00020901
d2060805
02010105
d00c0002
02020105
d2000002
000a0105
d2000000
00020304
d00c0000
02020105
d2000000
00020b00
080c0500
d00a0000
02010106
7e040280
7e060302
be802400
8980007e
bf880018
08060305
7e045506
d2820007
03da0503
08060b04
d2820008
03d20503
08060901
10040503
7e065500
10060706
d0040002
02020105
d2000004
00098280
d1040002
02010104
be822402
8982027e
d0040004
02020101
d2000002
00121107
88fe027e
88fe007e
100204ff
3e2aaaab
7e024101
100402ff
40c00000
100a06ff
3f3851ec
d00a0000
02010105
d2000001
00018280
d1040000
02010101
be802400
8980007e
d2060804
02010100
7e060304
7e020304
be802500
89fe007e
bf880055
10020105
100604f0
7e064103
06060703
060606f3
d2060103
02010103
080606f2
d0020002
0201e502
d2000004
00098280
d1040002
02010104
7e080280
7e0c02f2
be822402
8982027e
bf880034
d0020004
0201e902
d2000004
00118280
d1040004
02010104
7e0a02f2
7e080280
bf8c070f
be842404
8984047e
bf880025
7e0802ff
40400000
d0020006
02020902
d2000004
00198280
d1040006
02010104
7e0c0280
7e0a02f2
7e080303
be862406
8986067e
bf880015
d0020008
0201ed02
d2000004
00218280
d1040008
02010104
7e0c0280
7e0802f2
7e0a0303
be882408
8988087e
7e0802ff
40a00000
d002000a
02020902
d2000004
0029e503
d2000006
002a06f2
7e0a0280
88fe087e
88fe067e
7e060306
88fe047e
7e0c0303
7e060305
88fe027e
08000300
d2820002
04020304
d2060804
02010102
d2820002
04020303
d2060803
02010102
d2820000
04020306
d2060801
02010100
88fe007e
d2060800
02010103
060000ff
bcf5c28f
d2060800
02010100
100000ff
3f9c18f9
d2060800
02010100
100202ff
3f8ccccd
d2060801
02010101
060202ff
bcf5c28f
d2060801
02010101
100202ff
3f9c18f9
d2060801
02010101
5e000101
d2060801
02010104
060202ff
bcf5c28f
d2060801
02010101
100202ff
3f9c18f9
d2060801
02010101
d25e0001
0201e501
f8001c0f
01000100
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.5000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].x, IN[0].xxxx
  2: MOV TEMP[0].y, -IN[0].yyyy
  3: ADD TEMP[1].xy, IN[0].xyyy, IMM[0].yyyy
  4: MUL TEMP[1].xy, TEMP[1].xyyy, IMM[0].zzzz
  5: ADD TEMP[2].x, IMM[0].yyyy, -TEMP[1].yyyy
  6: MOV TEMP[1].y, TEMP[2].xxxx
  7: ADD TEMP[1].xy, TEMP[1].xyyy, CONST[0].xyyy
  8: MOV TEMP[1].xy, TEMP[1].xyxx
  9: MOV OUT[1], TEMP[1]
 10: MOV OUT[0], TEMP[0]
 11: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %14, i32 0, i32 %5)
  %16 = extractelement <4 x float> %15, i32 0
  %17 = extractelement <4 x float> %15, i32 1
  %18 = fsub float -0.000000e+00, %17
  %19 = fadd float %16, 1.000000e+00
  %20 = fadd float %17, 1.000000e+00
  %21 = fmul float %19, 5.000000e-01
  %22 = fmul float %20, 5.000000e-01
  %23 = fsub float -0.000000e+00, %22
  %24 = fadd float 1.000000e+00, %23
  %25 = fadd float %21, %11
  %26 = fadd float %24, %12
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %25, float %26, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %16, float %18, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0820700
bf8c007f
e00c2000
80010000
bf8c0770
060800f2
c0800100
bf8c007f
c2020100
bf8c007f
d2820004
0011e104
060a02f2
100a0af0
080a0af2
c2000101
bf8c007f
060c0a00
7e0a0280
f800020f
05050604
bf8c070f
d2060004
22010101
7e0c02f2
f80008cf
06050400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..5]
DCL TEMP[0], LOCAL
IMM[0] FLT32 {    0.1000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: ADD TEMP[0], TEMP[0], IMM[0].xxxy
  3: MUL TEMP[0], TEMP[0], CONST[4]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %32 = bitcast float %30 to i32
  %33 = bitcast float %31 to i32
  %34 = insertelement <2 x i32> undef, i32 %32, i32 0
  %35 = insertelement <2 x i32> %34, i32 %33, i32 1
  %36 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %27, <16 x i8> %29, i32 2)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = fadd float %37, 0x3FB99999A0000000
  %42 = fadd float %38, 0x3FB99999A0000000
  %43 = fadd float %39, 0x3FB99999A0000000
  %44 = fadd float %40, 0.000000e+00
  %45 = fmul float %41, %22
  %46 = fmul float %42, %23
  %47 = fmul float %43, %24
  %48 = fmul float %44, %25
  %49 = call i32 @llvm.SI.packf16(float %45, float %46)
  %50 = bitcast i32 %49 to float
  %51 = call i32 @llvm.SI.packf16(float %47, float %48)
  %52 = bitcast i32 %51 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %50, float %52, float %50, float %52)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430002
bf8c0770
06080680
c0800100
bf8c007f
c2020113
bf8c007f
10080804
060a04ff
3dcccccd
c2020112
bf8c007f
100a0a04
5e080905
060a02ff
3dcccccd
c2020111
bf8c007f
100a0a04
060000ff
3dcccccd
c2000110
bf8c007f
10000000
5e000b00
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..5]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xyz, IN[0].xyzx
  2: MOV TEMP[1].y, IN[1].yyyy
  3: ADD TEMP[1].x, IN[1].xxxx, CONST[5].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[0]
  5: DP4 TEMP[3].x, TEMP[0], CONST[1]
  6: MOV TEMP[2].y, TEMP[3].xxxx
  7: DP4 TEMP[3].x, TEMP[0], CONST[2]
  8: MOV TEMP[2].z, TEMP[3].xxxx
  9: DP4 TEMP[0].x, TEMP[0], CONST[3]
 10: MOV TEMP[2].w, TEMP[0].xxxx
 11: MOV TEMP[0].xy, TEMP[1].xyxx
 12: MOV OUT[1], TEMP[0]
 13: MOV OUT[0], TEMP[2]
 14: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %28 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %5)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = fadd float %37, %27
  %40 = fmul float %31, %11
  %41 = fmul float %32, %12
  %42 = fadd float %40, %41
  %43 = fmul float %33, %13
  %44 = fadd float %42, %43
  %45 = fmul float 1.000000e+00, %14
  %46 = fadd float %44, %45
  %47 = fmul float %31, %15
  %48 = fmul float %32, %16
  %49 = fadd float %47, %48
  %50 = fmul float %33, %17
  %51 = fadd float %49, %50
  %52 = fmul float 1.000000e+00, %18
  %53 = fadd float %51, %52
  %54 = fmul float %31, %19
  %55 = fmul float %32, %20
  %56 = fadd float %54, %55
  %57 = fmul float %33, %21
  %58 = fadd float %56, %57
  %59 = fmul float 1.000000e+00, %22
  %60 = fadd float %58, %59
  %61 = fmul float %31, %23
  %62 = fmul float %32, %24
  %63 = fadd float %61, %62
  %64 = fmul float %33, %25
  %65 = fadd float %63, %64
  %66 = fmul float 1.000000e+00, %26
  %67 = fadd float %65, %66
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %39, float %38, float %33, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %46, float %53, float %60, float %67)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020400
c0800100
bf8c0070
c2020114
bf8c007f
06100804
c0820700
bf8c007f
e00c2000
80010000
7e1202f2
bf8c0770
f800020f
09020508
c202010d
bf8c000f
10080204
c202010c
bf8c007f
d2820004
04100900
c202010e
bf8c007f
d2820004
04100902
c202010f
bf8c007f
06080804
c2020109
bf8c007f
100a0204
c2020108
bf8c007f
d2820005
04140900
c202010a
bf8c007f
d2820005
04140902
c202010b
bf8c007f
060a0a04
c2020105
bf8c007f
100c0204
c2020104
bf8c007f
d2820006
04180900
c2020106
bf8c007f
d2820006
04180902
c2020107
bf8c007f
060c0c04
c2020101
bf8c007f
100e0204
c2020100
bf8c007f
d2820007
041c0900
c2020102
bf8c007f
d2820000
041c0902
c2000103
bf8c007f
06000000
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..5]
DCL TEMP[0], LOCAL
IMM[0] FLT32 {   -0.1000,    -0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: ADD TEMP[0], TEMP[0], IMM[0].xxxy
  3: MUL TEMP[0], TEMP[0], CONST[4]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %32 = bitcast float %30 to i32
  %33 = bitcast float %31 to i32
  %34 = insertelement <2 x i32> undef, i32 %32, i32 0
  %35 = insertelement <2 x i32> %34, i32 %33, i32 1
  %36 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %27, <16 x i8> %29, i32 2)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = fadd float %37, 0xBFB99999A0000000
  %42 = fadd float %38, 0xBFB99999A0000000
  %43 = fadd float %39, 0xBFB99999A0000000
  %44 = fadd float %40, -0.000000e+00
  %45 = fmul float %41, %22
  %46 = fmul float %42, %23
  %47 = fmul float %43, %24
  %48 = fmul float %44, %25
  %49 = call i32 @llvm.SI.packf16(float %45, float %46)
  %50 = bitcast i32 %49 to float
  %51 = call i32 @llvm.SI.packf16(float %47, float %48)
  %52 = bitcast i32 %51 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %50, float %52, float %50, float %52)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430002
bf8c0770
060806ff
80000000
c0800100
bf8c007f
c2020113
bf8c007f
10080804
060a04ff
bdcccccd
c2020112
bf8c007f
100a0a04
5e080905
060a02ff
bdcccccd
c2020111
bf8c007f
100a0a04
060000ff
bdcccccd
c2000110
bf8c007f
10000000
5e000b00
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..5]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xyz, IN[0].xyzx
  2: MOV TEMP[1].y, IN[1].yyyy
  3: ADD TEMP[1].x, IN[1].xxxx, CONST[5].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[0]
  5: DP4 TEMP[3].x, TEMP[0], CONST[1]
  6: MOV TEMP[2].y, TEMP[3].xxxx
  7: DP4 TEMP[3].x, TEMP[0], CONST[2]
  8: MOV TEMP[2].z, TEMP[3].xxxx
  9: DP4 TEMP[0].x, TEMP[0], CONST[3]
 10: MOV TEMP[2].w, TEMP[0].xxxx
 11: MOV TEMP[0].xy, TEMP[1].xyxx
 12: MOV OUT[1], TEMP[0]
 13: MOV OUT[0], TEMP[2]
 14: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %28 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %5)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = fadd float %37, %27
  %40 = fmul float %31, %11
  %41 = fmul float %32, %12
  %42 = fadd float %40, %41
  %43 = fmul float %33, %13
  %44 = fadd float %42, %43
  %45 = fmul float 1.000000e+00, %14
  %46 = fadd float %44, %45
  %47 = fmul float %31, %15
  %48 = fmul float %32, %16
  %49 = fadd float %47, %48
  %50 = fmul float %33, %17
  %51 = fadd float %49, %50
  %52 = fmul float 1.000000e+00, %18
  %53 = fadd float %51, %52
  %54 = fmul float %31, %19
  %55 = fmul float %32, %20
  %56 = fadd float %54, %55
  %57 = fmul float %33, %21
  %58 = fadd float %56, %57
  %59 = fmul float 1.000000e+00, %22
  %60 = fadd float %58, %59
  %61 = fmul float %31, %23
  %62 = fmul float %32, %24
  %63 = fadd float %61, %62
  %64 = fmul float %33, %25
  %65 = fadd float %63, %64
  %66 = fmul float 1.000000e+00, %26
  %67 = fadd float %65, %66
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %39, float %38, float %33, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %46, float %53, float %60, float %67)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020400
c0800100
bf8c0070
c2020114
bf8c007f
06100804
c0820700
bf8c007f
e00c2000
80010000
7e1202f2
bf8c0770
f800020f
09020508
c202010d
bf8c000f
10080204
c202010c
bf8c007f
d2820004
04100900
c202010e
bf8c007f
d2820004
04100902
c202010f
bf8c007f
06080804
c2020109
bf8c007f
100a0204
c2020108
bf8c007f
d2820005
04140900
c202010a
bf8c007f
d2820005
04140902
c202010b
bf8c007f
060a0a04
c2020105
bf8c007f
100c0204
c2020104
bf8c007f
d2820006
04180900
c2020106
bf8c007f
d2820006
04180902
c2020107
bf8c007f
060c0c04
c2020101
bf8c007f
100e0204
c2020100
bf8c007f
d2820007
041c0900
c2020102
bf8c007f
d2820000
041c0902
c2000103
bf8c007f
06000000
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..5]
DCL TEMP[0..1], LOCAL
IMM[0] FLT32 {    0.2127,     0.7152,     0.0722,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MOV TEMP[1].w, TEMP[0].wwww
  3: DP3 TEMP[0].x, TEMP[0].xyzz, IMM[0].xyzz
  4: MOV TEMP[1].xyz, TEMP[0].xxxx
  5: MUL TEMP[0], TEMP[1], CONST[4]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %32 = bitcast float %30 to i32
  %33 = bitcast float %31 to i32
  %34 = insertelement <2 x i32> undef, i32 %32, i32 0
  %35 = insertelement <2 x i32> %34, i32 %33, i32 1
  %36 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %27, <16 x i8> %29, i32 2)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = fmul float %37, 0x3FCB38CDA0000000
  %42 = fmul float %38, 0x3FE6E29740000000
  %43 = fadd float %42, %41
  %44 = fmul float %39, 0x3FB279AAE0000000
  %45 = fadd float %43, %44
  %46 = fmul float %45, %22
  %47 = fmul float %45, %23
  %48 = fmul float %45, %24
  %49 = fmul float %40, %25
  %50 = call i32 @llvm.SI.packf16(float %46, float %47)
  %51 = bitcast i32 %50 to float
  %52 = call i32 @llvm.SI.packf16(float %48, float %49)
  %53 = bitcast i32 %52 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %51, float %53, float %51, float %53)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430002
bf8c0770
100800ff
3e59c66d
7e0a02ff
3f3714ba
d2820004
04120b01
7e0a02ff
3d93cd57
d2820004
04120b02
c0800100
bf8c007f
c2020111
bf8c007f
100a0804
c2020110
bf8c007f
100c0804
5e0a0b06
c2020112
bf8c007f
10080804
c2000113
bf8c007f
10000600
5e000104
f8001c0f
00050005
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..5]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xyz, IN[0].xyzx
  2: MOV TEMP[1].y, IN[1].yyyy
  3: ADD TEMP[1].x, IN[1].xxxx, CONST[5].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[0]
  5: DP4 TEMP[3].x, TEMP[0], CONST[1]
  6: MOV TEMP[2].y, TEMP[3].xxxx
  7: DP4 TEMP[3].x, TEMP[0], CONST[2]
  8: MOV TEMP[2].z, TEMP[3].xxxx
  9: DP4 TEMP[0].x, TEMP[0], CONST[3]
 10: MOV TEMP[2].w, TEMP[0].xxxx
 11: MOV TEMP[0].xy, TEMP[1].xyxx
 12: MOV OUT[1], TEMP[0]
 13: MOV OUT[0], TEMP[2]
 14: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
  %28 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %5)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = fadd float %37, %27
  %40 = fmul float %31, %11
  %41 = fmul float %32, %12
  %42 = fadd float %40, %41
  %43 = fmul float %33, %13
  %44 = fadd float %42, %43
  %45 = fmul float 1.000000e+00, %14
  %46 = fadd float %44, %45
  %47 = fmul float %31, %15
  %48 = fmul float %32, %16
  %49 = fadd float %47, %48
  %50 = fmul float %33, %17
  %51 = fadd float %49, %50
  %52 = fmul float 1.000000e+00, %18
  %53 = fadd float %51, %52
  %54 = fmul float %31, %19
  %55 = fmul float %32, %20
  %56 = fadd float %54, %55
  %57 = fmul float %33, %21
  %58 = fadd float %56, %57
  %59 = fmul float 1.000000e+00, %22
  %60 = fadd float %58, %59
  %61 = fmul float %31, %23
  %62 = fmul float %32, %24
  %63 = fadd float %61, %62
  %64 = fmul float %33, %25
  %65 = fadd float %63, %64
  %66 = fmul float 1.000000e+00, %26
  %67 = fadd float %65, %66
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %39, float %38, float %33, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %46, float %53, float %60, float %67)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020400
c0800100
bf8c0070
c2020114
bf8c007f
06100804
c0820700
bf8c007f
e00c2000
80010000
7e1202f2
bf8c0770
f800020f
09020508
c202010d
bf8c000f
10080204
c202010c
bf8c007f
d2820004
04100900
c202010e
bf8c007f
d2820004
04100902
c202010f
bf8c007f
06080804
c2020109
bf8c007f
100a0204
c2020108
bf8c007f
d2820005
04140900
c202010a
bf8c007f
d2820005
04140902
c202010b
bf8c007f
060a0a04
c2020105
bf8c007f
100c0204
c2020104
bf8c007f
d2820006
04180900
c2020106
bf8c007f
d2820006
04180902
c2020107
bf8c007f
060c0c04
c2020101
bf8c007f
100e0204
c2020100
bf8c007f
d2820007
041c0900
c2020102
bf8c007f
d2820000
041c0902
c2000103
bf8c007f
06000000
f80008cf
04050600
bf810000
Game removed: AppID 203770 "Crusader Kings II", ProcID 4230 
unlinked 2 orphaned pipes
CAsyncIOManager: 0 threads terminating.  0 reads, 0 writes, 0 deferrals.
CAsyncIOManager: 15230 single object sleeps, 0 multi object sleeps
CAsyncIOManager: 0 single object alertable sleeps, 2 multi object alertable sleeps
Shutting down. . .
[2013-09-08 03:55:21] Shutdown