[2013-09-17 21:33:30] Started bfgminer 3.2.0
 [2013-09-17 21:33:30] CL Platform 0 vendor: Mesa
 [2013-09-17 21:33:30] CL Platform 0 name: Default
 [2013-09-17 21:33:30] CL Platform 0 version: OpenCL 1.1 MESA 9.3.0-devel
 [2013-09-17 21:33:30] Platform 0 devices: 1
 [2013-09-17 21:33:30] 	0	AMD TAHITI
 [2013-09-17 21:33:30] Unable to load ati adl library
 [2013-09-17 21:33:30] Probing for an alive pool
 [2013-09-17 21:33:30] Testing pool stratum+tcp://stratum2.wemineltc.com:3334
 [2013-09-17 21:33:30] HTTP request failed: Protocol stratum+tcp not supported or disabled in libcurl
 [2013-09-17 21:33:30] Stratum authorisation success for pool 0
 [2013-09-17 21:33:30] Pool 0 stratum+tcp://stratum2.wemineltc.com:3334 alive
 [2013-09-17 21:33:31] Unknown stratum msg: {"error": [-3, "Method 'get_transactions' not found for service 'mining'", null], "id": "txlist5cd3", "result": null}
 [2013-09-17 21:33:31] Network difficulty changed to 1.03k ( 7.39Gh/s)
 [2013-09-17 21:33:31] New block: ...d8ccf6c9 #426377 diff 1.03k ( 7.39Gh/s)
 [2013-09-17 21:33:31] Stratum from pool 0 detected new block
 [2013-09-17 21:33:31] Pool 0 is hiding block contents from us
 [2013-09-17 21:33:31] Init GPU thread 0 GPU 0 virtual GPU 0
 [2013-09-17 21:33:31] CL Platform vendor: Mesa
 [2013-09-17 21:33:31] CL Platform name: Default
 [2013-09-17 21:33:31] CL Platform version: OpenCL 1.1 MESA 9.3.0-devel
 [2013-09-17 21:33:31] List of devices:
 [2013-09-17 21:33:31] 	0	AMD TAHITI
 [2013-09-17 21:33:31] Selected 0: AMD TAHITI
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr <16 x i8> addrspace(2)* %4, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800700
bf8c007f
e00c2000
80000000
d2460004
020100c1
480808c1
d22a0005
0201200b
360a0aff
0000007f
d1020000
02020b04
bf8c0770
be802400
8980007e
c0820900
d24a6a04
0202080c
34080882
d2320005
0201040d
4a080b04
bf8c007f
ea245000
80410004
bf8c0700
88fe007e
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
 [2013-09-17 21:33:31] Selecting scrypt kernel
 [2013-09-17 21:33:37] Received kill message
 [2013-09-17 21:33:38] Killing OCL 0