Running Steam on ubuntu 13.04 64-bit
STEAM_RUNTIME is enabled automatically
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
ATTENTION: default value of option vblank_mode overridden by environment.
[2013-09-18 22:26:30] Startup - updater built Sep 16 2013 15:29:29
[2013-09-18 22:26:30] Opted in to client beta 'publicbeta' via beta file
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr <16 x i8> addrspace(2)* %4, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800700
bf8c007f
e00c2000
80000000
d2460004
020100c1
480808c1
d22a0005
0201200b
360a0aff
0000007f
d1020000
02020b04
bf8c0770
be802400
8980007e
c0820900
d24a6a04
0202080c
34080882
d2320005
0201040d
4a080b04
bf8c007f
ea245000
80410004
bf8c0700
88fe007e
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
unlinked 0 orphaned pipes
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
[0918/222630:WARNING:proxy_service.cc(958)] PAC support disabled because there is no system implementation
ATTENTION: default value of option vblank_mode overridden by environment.
[2013-09-18 22:26:30] Verificando instalación...
[2013-09-18 22:26:30] Verification complete
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr <16 x i8> addrspace(2)* %4, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800700
bf8c007f
e00c2000
80000000
d2460004
020100c1
480808c1
d22a0005
0201200b
360a0aff
0000007f
d1020000
02020b04
bf8c0770
be802400
8980007e
c0820900
d24a6a04
0202080c
34080882
d2320005
0201040d
4a080b04
bf8c007f
ea245000
80410004
bf8c0700
88fe007e
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %21 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %22 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %23 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8080300
c8090301
c80c0200
c80d0201
c8100100
c8110101
c8140000
c8150001
f800180f
02030405
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %31, %12
  %43 = fmul float %31, %13
  %44 = fmul float %31, %14
  %45 = fmul float %31, %15
  %46 = fmul float %32, %16
  %47 = fadd float %46, %42
  %48 = fmul float %32, %17
  %49 = fadd float %48, %43
  %50 = fmul float %32, %18
  %51 = fadd float %50, %44
  %52 = fmul float %32, %19
  %53 = fadd float %52, %45
  %54 = fmul float %33, %20
  %55 = fadd float %54, %47
  %56 = fmul float %33, %21
  %57 = fadd float %56, %49
  %58 = fmul float %33, %22
  %59 = fadd float %58, %51
  %60 = fmul float %33, %23
  %61 = fadd float %60, %53
  %62 = fmul float %34, %24
  %63 = fadd float %62, %55
  %64 = fmul float %34, %25
  %65 = fadd float %64, %57
  %66 = fmul float %34, %26
  %67 = fadd float %66, %59
  %68 = fmul float %34, %27
  %69 = fadd float %68, %61
  %70 = call float @llvm.AMDIL.clamp.(float %38, float 0,000000e+00, float 0x3FF0000000000000)
  %71 = call float @llvm.AMDIL.clamp.(float %39, float 0,000000e+00, float 0x3FF0000000000000)
  %72 = call float @llvm.AMDIL.clamp.(float %40, float 0,000000e+00, float 0x3FF0000000000000)
  %73 = call float @llvm.AMDIL.clamp.(float %41, float 0,000000e+00, float 0x3FF0000000000000)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %70, float %71, float %72, float %73)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
7e080204
d2100004
02020900
c2020107
bf8c007f
7e0a0204
d2820004
04120b01
c202010b
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020102
bf8c007f
7e0a0204
d2100005
02020b00
c2020106
bf8c007f
7e0c0204
d2820005
04160d01
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010e
bf8c007f
7e0c0204
d2820005
04160d03
c2020101
bf8c007f
7e0c0204
d2100006
02020d00
c2020105
bf8c007f
7e0e0204
d2820006
041a0f01
c2020109
bf8c007f
7e0e0204
d2820006
041a0f02
c202010d
bf8c007f
7e0e0204
d2820006
041a0f03
c2020100
bf8c007f
7e0e0204
d2100007
02020f00
c2020104
bf8c007f
7e100204
d2820007
041e1101
c2020108
bf8c007f
7e100204
d2820007
041e1102
c200010c
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
  %25 = bitcast i32 %24 to float
  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
  %27 = bitcast i32 %26 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
5e000101
c8060102
c80a0002
5e020302
f8001c0f
00010001
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
  %36 = bitcast i32 %35 to float
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
  %36 = bitcast i32 %35 to float
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[1..4]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: MOV TEMP[0].w, IN[0].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], CONST[4]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %32 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %33 = fdiv float %30, %32
  %34 = fdiv float %31, %32
  %35 = bitcast float %33 to i32
  %36 = bitcast float %34 to i32
  %37 = insertelement <2 x i32> undef, i32 %35, i32 0
  %38 = insertelement <2 x i32> %37, i32 %36, i32 1
  %39 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %38, <32 x i8> %27, <16 x i8> %29, i32 2)
  %40 = extractelement <4 x float> %39, i32 0
  %41 = extractelement <4 x float> %39, i32 1
  %42 = extractelement <4 x float> %39, i32 2
  %43 = extractelement <4 x float> %39, i32 3
  %44 = fmul float %40, %22
  %45 = fmul float %41, %23
  %46 = fmul float %42, %24
  %47 = fmul float %43, %25
  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
  %49 = bitcast i32 %48 to float
  %50 = call i32 @llvm.SI.packf16(float %46, float %47)
  %51 = bitcast i32 %50 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %49, float %51, float %49, float %51)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080100
c8090101
c80c0300
c80d0301
7e065503
100a0702
c8080000
c8090001
10080702
c0840300
c0c60500
bf8c007f
f0800f00
00430004
c0800100
bf8c0070
c2020113
bf8c007f
7e080204
d2100004
02020903
c2020112
bf8c007f
7e0a0204
d2100005
02020b02
5e080905
c2020111
bf8c007f
7e0a0204
d2100005
02020b01
c2000110
bf8c007f
7e0c0200
d2100000
02020d00
5e000b00
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV OUT[1], IN[1]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %31, %12
  %43 = fmul float %31, %13
  %44 = fmul float %31, %14
  %45 = fmul float %31, %15
  %46 = fmul float %32, %16
  %47 = fadd float %46, %42
  %48 = fmul float %32, %17
  %49 = fadd float %48, %43
  %50 = fmul float %32, %18
  %51 = fadd float %50, %44
  %52 = fmul float %32, %19
  %53 = fadd float %52, %45
  %54 = fmul float %33, %20
  %55 = fadd float %54, %47
  %56 = fmul float %33, %21
  %57 = fadd float %56, %49
  %58 = fmul float %33, %22
  %59 = fadd float %58, %51
  %60 = fmul float %33, %23
  %61 = fadd float %60, %53
  %62 = fmul float %34, %24
  %63 = fadd float %62, %55
  %64 = fmul float %34, %25
  %65 = fadd float %64, %57
  %66 = fmul float %34, %26
  %67 = fadd float %66, %59
  %68 = fmul float %34, %27
  %69 = fadd float %68, %61
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %38, float %39, float %40, float %41)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
f800020f
04030201
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
7e080204
d2100004
02020900
c2020107
bf8c007f
7e0a0204
d2820004
04120b01
c202010b
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020102
bf8c007f
7e0a0204
d2100005
02020b00
c2020106
bf8c007f
7e0c0204
d2820005
04160d01
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010e
bf8c007f
7e0c0204
d2820005
04160d03
c2020101
bf8c007f
7e0c0204
d2100006
02020d00
c2020105
bf8c007f
7e0e0204
d2820006
041a0f01
c2020109
bf8c007f
7e0e0204
d2820006
041a0f02
c202010d
bf8c007f
7e0e0204
d2820006
041a0f03
c2020100
bf8c007f
7e0e0204
d2100007
02020f00
c2020104
bf8c007f
7e100204
d2820007
041e1101
c2020108
bf8c007f
7e100204
d2820007
041e1102
c200010c
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
Generating new string page texture 2: 48x256, total string texture memory is 49,15 KB
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: MOV TEMP[0].w, IN[1].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], IN[0]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %31 = fdiv float %28, %30
  %32 = fdiv float %29, %30
  %33 = bitcast float %31 to i32
  %34 = bitcast float %32 to i32
  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %38, %24
  %43 = fmul float %39, %25
  %44 = fmul float %40, %26
  %45 = fmul float %41, %27
  %46 = call i32 @llvm.SI.packf16(float %42, float %43)
  %47 = bitcast i32 %46 to float
  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
  %49 = bitcast i32 %48 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %47, float %49, float %47, float %49)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080500
c8090501
c80c0700
c80d0701
7e065503
100a0702
c8080400
c8090401
10080702
c0800300
c0c40500
bf8c007f
f0800f00
00020204
c8180300
c8190301
bf8c0770
100c0d05
c81c0200
c81d0201
100e0f04
5e0c0d07
c81c0100
c81d0101
100e0f03
c8200000
c8210001
10001102
5e000f00
f8001c0f
06000600
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], GENERIC[0]
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: MOV OUT[2], IN[2]
  6: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
  %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %6)
  %45 = extractelement <4 x float> %44, i32 0
  %46 = extractelement <4 x float> %44, i32 1
  %47 = extractelement <4 x float> %44, i32 2
  %48 = extractelement <4 x float> %44, i32 3
  %49 = fmul float %31, %12
  %50 = fmul float %31, %13
  %51 = fmul float %31, %14
  %52 = fmul float %31, %15
  %53 = fmul float %32, %16
  %54 = fadd float %53, %49
  %55 = fmul float %32, %17
  %56 = fadd float %55, %50
  %57 = fmul float %32, %18
  %58 = fadd float %57, %51
  %59 = fmul float %32, %19
  %60 = fadd float %59, %52
  %61 = fmul float %33, %20
  %62 = fadd float %61, %54
  %63 = fmul float %33, %21
  %64 = fadd float %63, %56
  %65 = fmul float %33, %22
  %66 = fadd float %65, %58
  %67 = fmul float %33, %23
  %68 = fadd float %67, %60
  %69 = fmul float %34, %24
  %70 = fadd float %69, %62
  %71 = fmul float %34, %25
  %72 = fadd float %71, %64
  %73 = fmul float %34, %26
  %74 = fadd float %73, %66
  %75 = fmul float %34, %27
  %76 = fadd float %75, %68
  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0,000000e+00, float 0x3FF0000000000000)
  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0,000000e+00, float 0x3FF0000000000000)
  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0,000000e+00, float 0x3FF0000000000000)
  %80 = call float @llvm.AMDIL.clamp.(float %41, float 0,000000e+00, float 0x3FF0000000000000)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %77, float %78, float %79, float %80)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %45, float %46, float %47, float %48)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %70, float %72, float %74, float %76)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0840708
bf8c000f
e00c2000
80020100
bf8c0770
f800021f
04030201
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
7e080204
d2100004
02020900
c2020107
bf8c007f
7e0a0204
d2820004
04120b01
c202010b
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020102
bf8c007f
7e0a0204
d2100005
02020b00
c2020106
bf8c007f
7e0c0204
d2820005
04160d01
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010e
bf8c007f
7e0c0204
d2820005
04160d03
c2020101
bf8c007f
7e0c0204
d2100006
02020d00
c2020105
bf8c007f
7e0e0204
d2820006
041a0f01
c2020109
bf8c007f
7e0e0204
d2820006
041a0f02
c202010d
bf8c007f
7e0e0204
d2820006
041a0f03
c2020100
bf8c007f
7e0e0204
d2100007
02020f00
c2020104
bf8c007f
7e100204
d2820007
041e1101
c2020108
bf8c007f
7e100204
d2820007
041e1102
c200010c
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
Generating new string page texture 3: 384x256, total string texture memory is 442,37 KB

(steam:3732): Gtk-WARNING **: Imposible encontrar el motor de temas en la ruta al _modulo: «oxygen-gtk»,

(steam:3732): Gtk-WARNING **: Imposible encontrar el motor de temas en la ruta al _modulo: «oxygen-gtk»,
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
`menu_proxy_module_load': /home/jose/.local/share/Steam/ubuntu12_32/steam: undefined symbol: menu_proxy_module_load

(steam:3732): Gtk-WARNING **: Failed to load type module: (null)


(steam:3732): LIBDBUSMENU-GLIB-WARNING **: Translation has an invalid value 'I-->D' for default text direction.  Defaulting to left-to-right.

** (steam:3732): WARNING **: replace_settings: error updating connection /org/freedesktop/NetworkManager/Settings/1 settings: (1) type
roaming config store loaded successfully - 9188 bytes.
migrating temporary roaming config store
Adding license for package 0
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Adding license for package 31052
Adding license for package 31801
ExecCommandLine: "/home/jose/.local/share/Steam/ubuntu12_32/steam"
System startup time: 38,85 seconds
ATTENTION: default value of option vblank_mode overridden by environment.
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr <16 x i8> addrspace(2)* %4, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800700
bf8c007f
e00c2000
80000000
d2460004
020100c1
480808c1
d22a0005
0201200b
360a0aff
0000007f
d1020000
02020b04
bf8c0770
be802400
8980007e
c0820900
d24a6a04
0202080c
34080882
d2320005
0201040d
4a080b04
bf8c007f
ea245000
80410004
bf8c0700
88fe007e
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Generating new string page texture 73: 1024x256, total string texture memory is 1,49 MB
Generating new string page texture 74: 256x256, total string texture memory is 262,14 KB
Generating new string page texture 75: 256x256, total string texture memory is 1,75 MB
Generating new string page texture 76: 128x256, total string texture memory is 1,88 MB
Generating new string page texture 77: 64x256, total string texture memory is 1,95 MB
Generating new string page texture 78: 24x256, total string texture memory is 1,97 MB
Running Steam on ubuntu 13.04 64-bit
STEAM_RUNTIME has been set by the user to: /home/jose/.local/share/Steam/ubuntu12_32/steam-runtime
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
ExecCommandLine: "/home/jose/.steam/root/ubuntu12_32/steam steam://open/driverhelperready"
ExecSteamURL: "steam://open/driverhelperready"
Generating new string page texture 91: 128x256, total string texture memory is 2,11 MB
Generating new string page texture 92: 256x256, total string texture memory is 2,37 MB
Generating new string page texture 94: 32x256, total string texture memory is 2,40 MB
Generating new string page texture 95: 48x256, total string texture memory is 2,45 MB
Generating new string page texture 96: 256x256, total string texture memory is 2,71 MB
Generating new string page texture 104: 512x256, total string texture memory is 3,24 MB
Generating new string page texture 105: 128x256, total string texture memory is 3,37 MB
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Generating new string page texture 139: 256x256, total string texture memory is 3,63 MB
CAPIJobRequestUserStats - Server response failed 2
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Game update: AppID 203770 "Crusader Kings II", ProcID 3842, IP 0.0.0.0:0
Setting breakpad minidump AppID = 203770
Steam_SetMinidumpSteamID:  Caching Steam ID:  76561198042971456 [API loaded no]
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
ATTENTION: default value of option vblank_mode overridden by environment.
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr <16 x i8> addrspace(2)* %4, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800700
bf8c007f
e00c2000
80000000
d2460004
020100c1
480808c1
d22a0005
0201200b
360a0aff
0000007f
d1020000
02020b04
bf8c0770
be802400
8980007e
c0820900
d24a6a04
0202080c
34080882
d2320005
0201040d
4a080b04
bf8c007f
ea245000
80410004
bf8c0700
88fe007e
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr <16 x i8> addrspace(2)* %4, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800700
bf8c007f
e00c2000
80000000
d2460004
020100c1
480808c1
d22a0005
0201200b
360a0aff
0000007f
d1020000
02020b04
bf8c0770
be802400
8980007e
c0820900
d24a6a04
0202080c
34080882
d2320005
0201040d
4a080b04
bf8c007f
ea245000
80410004
bf8c0700
88fe007e
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
ATTENTION: default value of option vblank_mode overridden by environment.
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr <16 x i8> addrspace(2)* %4, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800700
bf8c007f
e00c2000
80000000
d2460004
020100c1
480808c1
d22a0005
0201200b
360a0aff
0000007f
d1020000
02020b04
bf8c0770
be802400
8980007e
c0820900
d24a6a04
0202080c
34080882
d2320005
0201040d
4a080b04
bf8c007f
ea245000
80410004
bf8c0700
88fe007e
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr <16 x i8> addrspace(2)* %4, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800700
bf8c007f
e00c2000
80000000
d2460004
020100c1
480808c1
d22a0005
0201200b
360a0aff
0000007f
d1020000
02020b04
bf8c0770
be802400
8980007e
c0820900
d24a6a04
0202080c
34080882
d2320005
0201040d
4a080b04
bf8c007f
ea245000
80410004
bf8c0700
88fe007e
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr <16 x i8> addrspace(2)* %4, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800700
bf8c007f
e00c2000
80000000
d2460004
020100c1
480808c1
d22a0005
0201200b
360a0aff
0000007f
d1020000
02020b04
bf8c0770
be802400
8980007e
c0820900
d24a6a04
0202080c
34080882
d2320005
0201040d
4a080b04
bf8c007f
ea245000
80410004
bf8c0700
88fe007e
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr <16 x i8> addrspace(2)* %4, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800700
bf8c007f
e00c2000
80000000
d2460004
020100c1
480808c1
d22a0005
0201200b
360a0aff
0000007f
d1020000
02020b04
bf8c0770
be802400
8980007e
c0820900
d24a6a04
0202080c
34080882
d2320005
0201040d
4a080b04
bf8c007f
ea245000
80410004
bf8c0700
88fe007e
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800704
bf8c007f
e00c2000
80000100
bf8c0770
f800020f
04030201
c0800700
bf8c000f
e00c2000
80000000
bf8c0770
f80008cf
03020100
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr <16 x i8> addrspace(2)* %4, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800700
bf8c007f
e00c2000
80000000
d2460004
020100c1
480808c1
d22a0005
0201200b
360a0aff
0000007f
d1020000
02020b04
bf8c0770
be802400
8980007e
c0820900
d24a6a04
0202080c
34080882
d2320005
0201040d
4a080b04
bf8c007f
ea245000
80410004
bf8c0700
88fe007e
f80008cf
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
7e000280
f8001800
00000000
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %32, float %33, float %34)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
f800180f
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %32, float %33, float %34)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
f800180f
03020100
bf810000
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
  %36 = bitcast i32 %35 to float
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800f00
00010002
bf8c0770
5e080702
5e000300
f8001c0f
04000400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
c80a0102
c80e0002
f800180f
00010203
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %31, %12
  %43 = fmul float %31, %13
  %44 = fmul float %31, %14
  %45 = fmul float %31, %15
  %46 = fmul float %32, %16
  %47 = fadd float %46, %42
  %48 = fmul float %32, %17
  %49 = fadd float %48, %43
  %50 = fmul float %32, %18
  %51 = fadd float %50, %44
  %52 = fmul float %32, %19
  %53 = fadd float %52, %45
  %54 = fmul float %33, %20
  %55 = fadd float %54, %47
  %56 = fmul float %33, %21
  %57 = fadd float %56, %49
  %58 = fmul float %33, %22
  %59 = fadd float %58, %51
  %60 = fmul float %33, %23
  %61 = fadd float %60, %53
  %62 = fmul float %34, %24
  %63 = fadd float %62, %55
  %64 = fmul float %34, %25
  %65 = fadd float %64, %57
  %66 = fmul float %34, %26
  %67 = fadd float %66, %59
  %68 = fmul float %34, %27
  %69 = fadd float %68, %61
  %70 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
  %71 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
  %72 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
  %73 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %70, float %71, float %72, float %73)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
7e080204
d2100004
02020900
c2020107
bf8c007f
7e0a0204
d2820004
04120b01
c202010b
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020102
bf8c007f
7e0a0204
d2100005
02020b00
c2020106
bf8c007f
7e0c0204
d2820005
04160d01
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010e
bf8c007f
7e0c0204
d2820005
04160d03
c2020101
bf8c007f
7e0c0204
d2100006
02020d00
c2020105
bf8c007f
7e0e0204
d2820006
041a0f01
c2020109
bf8c007f
7e0e0204
d2820006
041a0f02
c202010d
bf8c007f
7e0e0204
d2820006
041a0f03
c2020100
bf8c007f
7e0e0204
d2100007
02020f00
c2020104
bf8c007f
7e100204
d2820007
041e1101
c2020108
bf8c007f
7e100204
d2820007
041e1102
c200010c
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
  %25 = bitcast i32 %24 to float
  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
  %27 = bitcast i32 %26 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8020302
c8060202
5e000101
c8060102
c80a0002
5e020302
f8001c0f
00010001
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MUL TEMP[0], TEMP[0], IN[0]
  3: MOV OUT[0], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %30 = bitcast float %28 to i32
  %31 = bitcast float %29 to i32
  %32 = insertelement <2 x i32> undef, i32 %30, i32 0
  %33 = insertelement <2 x i32> %32, i32 %31, i32 1
  %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %33, <32 x i8> %21, <16 x i8> %23, i32 2)
  %35 = extractelement <4 x float> %34, i32 0
  %36 = extractelement <4 x float> %34, i32 1
  %37 = extractelement <4 x float> %34, i32 2
  %38 = extractelement <4 x float> %34, i32 3
  %39 = fmul float %35, %24
  %40 = fmul float %36, %25
  %41 = fmul float %37, %26
  %42 = fmul float %38, %27
  %43 = call i32 @llvm.SI.packf16(float %39, float %40)
  %44 = bitcast i32 %43 to float
  %45 = call i32 @llvm.SI.packf16(float %41, float %42)
  %46 = bitcast i32 %45 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %44, float %46, float %44, float %46)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0500
c80d0501
c8080400
c8090401
c0800300
c0c40500
bf8c007f
f0800f00
00020202
c8180300
c8190301
bf8c0770
100c0d05
c81c0200
c81d0201
100e0f04
5e0c0d07
c81c0100
c81d0101
100e0f03
c8200000
c8210001
10001102
5e000f00
f8001c0f
06000600
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..3]
DCL TEMP[0..1], LOCAL
  0: DP4 TEMP[0].x, IN[0], CONST[0]
  1: DP4 TEMP[1].x, IN[0], CONST[1]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: DP4 TEMP[1].x, IN[0], CONST[2]
  4: MOV TEMP[0].z, TEMP[1].xxxx
  5: DP4 TEMP[1].x, IN[0], CONST[3]
  6: MOV TEMP[0].w, TEMP[1].xxxx
  7: MOV TEMP[1].xy, IN[1].xyxx
  8: MOV OUT[1], IN[2]
  9: MOV OUT[2], TEMP[1]
 10: MOV OUT[0], TEMP[0]
 11: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %41 = load <16 x i8> addrspace(2)* %40, !tbaa !0
  %42 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %41, i32 0, i32 %6)
  %43 = extractelement <4 x float> %42, i32 0
  %44 = extractelement <4 x float> %42, i32 1
  %45 = extractelement <4 x float> %42, i32 2
  %46 = extractelement <4 x float> %42, i32 3
  %47 = fmul float %31, %12
  %48 = fmul float %32, %13
  %49 = fadd float %47, %48
  %50 = fmul float %33, %14
  %51 = fadd float %49, %50
  %52 = fmul float %34, %15
  %53 = fadd float %51, %52
  %54 = fmul float %31, %16
  %55 = fmul float %32, %17
  %56 = fadd float %54, %55
  %57 = fmul float %33, %18
  %58 = fadd float %56, %57
  %59 = fmul float %34, %19
  %60 = fadd float %58, %59
  %61 = fmul float %31, %20
  %62 = fmul float %32, %21
  %63 = fadd float %61, %62
  %64 = fmul float %33, %22
  %65 = fadd float %63, %64
  %66 = fmul float %34, %23
  %67 = fadd float %65, %66
  %68 = fmul float %31, %24
  %69 = fmul float %32, %25
  %70 = fadd float %68, %69
  %71 = fmul float %33, %26
  %72 = fadd float %70, %71
  %73 = fmul float %34, %27
  %74 = fadd float %72, %73
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %43, float %44, float %45, float %46)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %38, float %39, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %53, float %60, float %67, float %74)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840708
bf8c007f
e00c2000
80020100
bf8c0770
f800020f
04030201
c0840704
bf8c000f
e00c2000
80020100
7e0a0280
bf8c0770
f800021f
05050201
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c202010d
bf8c007f
7e080204
d2100004
02020901
c202010c
bf8c007f
7e0a0204
d2820004
04120b00
c202010e
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020109
bf8c007f
7e0a0204
d2100005
02020b01
c2020108
bf8c007f
7e0c0204
d2820005
04160d00
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010b
bf8c007f
7e0c0204
d2820005
04160d03
c2020105
bf8c007f
7e0c0204
d2100006
02020d01
c2020104
bf8c007f
7e0e0204
d2820006
041a0f00
c2020106
bf8c007f
7e0e0204
d2820006
041a0f02
c2020107
bf8c007f
7e0e0204
d2820006
041a0f03
c2020101
bf8c007f
7e0e0204
d2100007
02020f01
c2020100
bf8c007f
7e100204
d2820007
041e1100
c2020102
bf8c007f
7e100204
d2820007
041e1102
c2000103
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
Installing breakpad exception handler for appid(gameoverlayui)/version(20130916152938_client)
Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
[0918/222721:WARNING:proxy_service.cc(958)] PAC support disabled because there is no system implementation
































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..5]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MUL TEMP[0], TEMP[0], CONST[4]
  3: MOV OUT[0], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %32 = bitcast float %30 to i32
  %33 = bitcast float %31 to i32
  %34 = insertelement <2 x i32> undef, i32 %32, i32 0
  %35 = insertelement <2 x i32> %34, i32 %33, i32 1
  %36 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %27, <16 x i8> %29, i32 2)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = fmul float %37, %22
  %42 = fmul float %38, %23
  %43 = fmul float %39, %24
  %44 = fmul float %40, %25
  %45 = call i32 @llvm.SI.packf16(float %41, float %42)
  %46 = bitcast i32 %45 to float
  %47 = call i32 @llvm.SI.packf16(float %43, float %44)
  %48 = bitcast i32 %47 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %46, float %48, float %46, float %48)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430002
c0800100
bf8c0070
c2020113
bf8c007f
7e080204
d2100004
02020903
c2020112
bf8c007f
7e0a0204
d2100005
02020b02
5e080905
c2020111
bf8c007f
7e0a0204
d2100005
02020b01
c2000110
bf8c007f
7e0c0200
d2100000
02020d00
5e000b00
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..5]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xyz, IN[0].xyzx
  2: MOV TEMP[1].y, IN[1].yyyy
  3: ADD TEMP[1].x, IN[1].xxxx, CONST[5].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[0]
  5: DP4 TEMP[3].x, TEMP[0], CONST[1]
  6: MOV TEMP[2].y, TEMP[3].xxxx
  7: DP4 TEMP[3].x, TEMP[0], CONST[2]
  8: MOV TEMP[2].z, TEMP[3].xxxx
  9: DP4 TEMP[0].x, TEMP[0], CONST[3]
 10: MOV TEMP[2].w, TEMP[0].xxxx
 11: MOV TEMP[0].xy, TEMP[1].xyxx
 12: MOV OUT[1], TEMP[0]
 13: MOV OUT[0], TEMP[2]
 14: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %29 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %30, i32 0, i32 %6)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = fadd float %38, %28
  %41 = fmul float %32, %12
  %42 = fmul float %33, %13
  %43 = fadd float %41, %42
  %44 = fmul float %34, %14
  %45 = fadd float %43, %44
  %46 = fmul float 1.000000e+00, %15
  %47 = fadd float %45, %46
  %48 = fmul float %32, %16
  %49 = fmul float %33, %17
  %50 = fadd float %48, %49
  %51 = fmul float %34, %18
  %52 = fadd float %50, %51
  %53 = fmul float 1.000000e+00, %19
  %54 = fadd float %52, %53
  %55 = fmul float %32, %20
  %56 = fmul float %33, %21
  %57 = fadd float %55, %56
  %58 = fmul float %34, %22
  %59 = fadd float %57, %58
  %60 = fmul float 1.000000e+00, %23
  %61 = fadd float %59, %60
  %62 = fmul float %32, %24
  %63 = fmul float %33, %25
  %64 = fadd float %62, %63
  %65 = fmul float %34, %26
  %66 = fadd float %64, %65
  %67 = fmul float 1.000000e+00, %27
  %68 = fadd float %66, %67
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %40, float %39, float %34, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %47, float %54, float %61, float %68)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020114
bf8c007f
7e0a0204
d2060005
02020b01
c0820700
bf8c007f
e00c2000
80010600
7e0002f2
bf8c0770
f800020f
00080205
c202010d
bf8c000f
7e000204
d2100000
02020107
c202010c
bf8c007f
7e020204
d2820000
04020306
c202010e
bf8c007f
7e020204
d2820000
04020308
c202010f
bf8c007f
06000004
c2020109
bf8c007f
7e020204
d2100001
02020307
c2020108
bf8c007f
7e040204
d2820001
04060506
c202010a
bf8c007f
7e040204
d2820001
04060508
c202010b
bf8c007f
06020204
c2020105
bf8c007f
7e040204
d2100002
02020507
c2020104
bf8c007f
7e060204
d2820002
040a0706
c2020106
bf8c007f
7e060204
d2820002
040a0708
c2020107
bf8c007f
06040404
c2020101
bf8c007f
7e060204
d2100003
02020707
c2020100
bf8c007f
7e080204
d2820003
040e0906
c2020102
bf8c007f
7e080204
d2820003
040e0908
c2000103
bf8c007f
06060600
f80008cf
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..6]
DCL TEMP[0..1], LOCAL
  0: FSGE TEMP[0].x, CONST[6].xxxx, IN[0].xxxx
  1: UIF TEMP[0].xxxx :0
  2:   MOV TEMP[0].xy, IN[0].xyyy
  3:   TEX TEMP[0], TEMP[0], SAMP[0], 2D
  4:   MOV TEMP[0], TEMP[0]
  5: ELSE :0
  6:   MOV TEMP[1].xy, IN[0].xyyy
  7:   TEX TEMP[1], TEMP[1], SAMP[1], 2D
  8:   MOV TEMP[0], TEMP[1]
  9: ENDIF
 10: MOV OUT[0], TEMP[0]
 11: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
  %23 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %24 = load <32 x i8> addrspace(2)* %23, !tbaa !0
  %25 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %26 = load <16 x i8> addrspace(2)* %25, !tbaa !0
  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %33 = fcmp oge float %22, %31
  %34 = sext i1 %33 to i32
  %35 = bitcast i32 %34 to float
  %36 = bitcast float %35 to i32
  %37 = icmp ne i32 %36, 0
  %38 = bitcast float %31 to i32
  %39 = bitcast float %32 to i32
  %40 = insertelement <2 x i32> undef, i32 %38, i32 0
  %41 = insertelement <2 x i32> %40, i32 %39, i32 1
  br i1 %37, label %IF, label %ELSE

IF:                                               ; preds = %main_body
  %42 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %41, <32 x i8> %24, <16 x i8> %26, i32 2)
  %43 = extractelement <4 x float> %42, i32 0
  %44 = extractelement <4 x float> %42, i32 1
  %45 = extractelement <4 x float> %42, i32 2
  br label %ENDIF

ELSE:                                             ; preds = %main_body
  %46 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %41, <32 x i8> %28, <16 x i8> %30, i32 2)
  %47 = extractelement <4 x float> %46, i32 0
  %48 = extractelement <4 x float> %46, i32 1
  %49 = extractelement <4 x float> %46, i32 2
  br label %ENDIF

ENDIF:                                            ; preds = %ELSE, %IF
  %.sink = phi <4 x float> [ %42, %IF ], [ %46, %ELSE ]
  %temp.0 = phi float [ %43, %IF ], [ %47, %ELSE ]
  %temp1.0 = phi float [ %44, %IF ], [ %48, %ELSE ]
  %temp2.0 = phi float [ %45, %IF ], [ %49, %ELSE ]
  %50 = extractelement <4 x float> %.sink, i32 3
  %51 = call i32 @llvm.SI.packf16(float %temp.0, float %temp1.0)
  %52 = bitcast i32 %51 to float
  %53 = call i32 @llvm.SI.packf16(float %temp2.0, float %50)
  %54 = bitcast i32 %53 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %52, float %54, float %52, float %54)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840100
bf8c007f
c2000918
bf8c007f
d00c0000
02020400
d2000000
00018280
d1040000
02010100
be802400
8980007e
c0840304
c0c60508
bf8c007f
f0800f00
00430402
bf8c0770
be802500
89fe007e
c0840300
c0c60500
bf8c007f
f0800f00
00430402
bf8c0770
88fe007e
5e000f06
d25e0001
02020b04
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..6]
DCL TEMP[0..1], LOCAL
  0: DP4 TEMP[0].x, IN[0], CONST[0]
  1: DP4 TEMP[1].x, IN[0], CONST[1]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: DP4 TEMP[1].x, IN[0], CONST[2]
  4: MOV TEMP[0].z, TEMP[1].xxxx
  5: DP4 TEMP[1].x, IN[0], CONST[3]
  6: MOV TEMP[0].w, TEMP[1].xxxx
  7: MOV TEMP[1].xy, IN[1].xyxx
  8: MOV OUT[1], TEMP[1]
  9: MOV OUT[0], TEMP[0]
 10: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = fmul float %31, %12
  %41 = fmul float %32, %13
  %42 = fadd float %40, %41
  %43 = fmul float %33, %14
  %44 = fadd float %42, %43
  %45 = fmul float %34, %15
  %46 = fadd float %44, %45
  %47 = fmul float %31, %16
  %48 = fmul float %32, %17
  %49 = fadd float %47, %48
  %50 = fmul float %33, %18
  %51 = fadd float %49, %50
  %52 = fmul float %34, %19
  %53 = fadd float %51, %52
  %54 = fmul float %31, %20
  %55 = fmul float %32, %21
  %56 = fadd float %54, %55
  %57 = fmul float %33, %22
  %58 = fadd float %56, %57
  %59 = fmul float %34, %23
  %60 = fadd float %58, %59
  %61 = fmul float %31, %24
  %62 = fmul float %32, %25
  %63 = fadd float %61, %62
  %64 = fmul float %33, %26
  %65 = fadd float %63, %64
  %66 = fmul float %34, %27
  %67 = fadd float %65, %66
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %38, float %39, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %46, float %53, float %60, float %67)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
7e0a0280
bf8c0770
f800020f
05050201
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c202010d
bf8c007f
7e080204
d2100004
02020901
c202010c
bf8c007f
7e0a0204
d2820004
04120b00
c202010e
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020109
bf8c007f
7e0a0204
d2100005
02020b01
c2020108
bf8c007f
7e0c0204
d2820005
04160d00
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010b
bf8c007f
7e0c0204
d2820005
04160d03
c2020105
bf8c007f
7e0c0204
d2100006
02020d01
c2020104
bf8c007f
7e0e0204
d2820006
041a0f00
c2020106
bf8c007f
7e0e0204
d2820006
041a0f02
c2020107
bf8c007f
7e0e0204
d2820006
041a0f03
c2020101
bf8c007f
7e0e0204
d2100007
02020f01
c2020100
bf8c007f
7e100204
d2820007
041e1100
c2020102
bf8c007f
7e100204
d2820007
041e1102
c2000103
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: MOV TEMP[0].w, IN[1].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], IN[0]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %31 = fdiv float %28, %30
  %32 = fdiv float %29, %30
  %33 = bitcast float %31 to i32
  %34 = bitcast float %32 to i32
  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %38, %24
  %43 = fmul float %39, %25
  %44 = fmul float %40, %26
  %45 = fmul float %41, %27
  %46 = call i32 @llvm.SI.packf16(float %42, float %43)
  %47 = bitcast i32 %46 to float
  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
  %49 = bitcast i32 %48 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %47, float %49, float %47, float %49)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080500
c8090501
c80c0700
c80d0701
7e065503
100a0702
c8080400
c8090401
10080702
c0800300
c0c40500
bf8c007f
f0800f00
00020204
c8180300
c8190301
bf8c0770
100c0d05
c81c0200
c81d0201
100e0f04
5e0c0d07
c81c0100
c81d0101
100e0f03
c8200000
c8210001
10001102
5e000f00
f8001c0f
06000600
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], GENERIC[0]
DCL CONST[0..7]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
  9: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 108)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112)
  %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116)
  %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 120)
  %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 124)
  %44 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %45 = load <16 x i8> addrspace(2)* %44, !tbaa !0
  %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %45, i32 0, i32 %6)
  %47 = extractelement <4 x float> %46, i32 0
  %48 = extractelement <4 x float> %46, i32 1
  %49 = extractelement <4 x float> %46, i32 2
  %50 = extractelement <4 x float> %46, i32 3
  %51 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %52, i32 0, i32 %6)
  %54 = extractelement <4 x float> %53, i32 0
  %55 = extractelement <4 x float> %53, i32 1
  %56 = extractelement <4 x float> %53, i32 2
  %57 = extractelement <4 x float> %53, i32 3
  %58 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %59 = load <16 x i8> addrspace(2)* %58, !tbaa !0
  %60 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %59, i32 0, i32 %6)
  %61 = extractelement <4 x float> %60, i32 0
  %62 = extractelement <4 x float> %60, i32 1
  %63 = extractelement <4 x float> %60, i32 2
  %64 = extractelement <4 x float> %60, i32 3
  %65 = fmul float %47, %12
  %66 = fmul float %47, %13
  %67 = fmul float %47, %14
  %68 = fmul float %47, %15
  %69 = fmul float %48, %16
  %70 = fadd float %69, %65
  %71 = fmul float %48, %17
  %72 = fadd float %71, %66
  %73 = fmul float %48, %18
  %74 = fadd float %73, %67
  %75 = fmul float %48, %19
  %76 = fadd float %75, %68
  %77 = fmul float %49, %20
  %78 = fadd float %77, %70
  %79 = fmul float %49, %21
  %80 = fadd float %79, %72
  %81 = fmul float %49, %22
  %82 = fadd float %81, %74
  %83 = fmul float %49, %23
  %84 = fadd float %83, %76
  %85 = fmul float %50, %24
  %86 = fadd float %85, %78
  %87 = fmul float %50, %25
  %88 = fadd float %87, %80
  %89 = fmul float %50, %26
  %90 = fadd float %89, %82
  %91 = fmul float %50, %27
  %92 = fadd float %91, %84
  %93 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
  %94 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00)
  %95 = call float @llvm.AMDIL.clamp.(float %56, float 0.000000e+00, float 1.000000e+00)
  %96 = call float @llvm.AMDIL.clamp.(float %57, float 0.000000e+00, float 1.000000e+00)
  %97 = fmul float %61, %28
  %98 = fmul float %61, %29
  %99 = fmul float %61, %30
  %100 = fmul float %61, %31
  %101 = fmul float %62, %32
  %102 = fadd float %101, %97
  %103 = fmul float %62, %33
  %104 = fadd float %103, %98
  %105 = fmul float %62, %34
  %106 = fadd float %105, %99
  %107 = fmul float %62, %35
  %108 = fadd float %107, %100
  %109 = fmul float %63, %36
  %110 = fadd float %109, %102
  %111 = fmul float %63, %37
  %112 = fadd float %111, %104
  %113 = fmul float %63, %38
  %114 = fadd float %113, %106
  %115 = fmul float %63, %39
  %116 = fadd float %115, %108
  %117 = fmul float %64, %40
  %118 = fadd float %117, %110
  %119 = fmul float %64, %41
  %120 = fadd float %119, %112
  %121 = fmul float %64, %42
  %122 = fadd float %121, %114
  %123 = fmul float %64, %43
  %124 = fadd float %123, %116
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %93, float %94, float %95, float %96)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %118, float %120, float %122, float %124)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %86, float %88, float %90, float %92)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0840708
bf8c000f
e00c2000
80020100
c0800100
bf8c0070
c2020113
bf8c007f
7e0a0204
d2100005
02020b01
c2020117
bf8c007f
7e0c0204
d2820005
04160d02
c202011b
bf8c007f
7e0c0204
d2820005
04160d03
c202011f
bf8c007f
7e0c0204
d2820005
04160d04
c2020112
bf8c007f
7e0c0204
d2100006
02020d01
c2020116
bf8c007f
7e0e0204
d2820006
041a0f02
c202011a
bf8c007f
7e0e0204
d2820006
041a0f03
c202011e
bf8c007f
7e0e0204
d2820006
041a0f04
c2020111
bf8c007f
7e0e0204
d2100007
02020f01
c2020115
bf8c007f
7e100204
d2820007
041e1102
c2020119
bf8c007f
7e100204
d2820007
041e1103
c202011d
bf8c007f
7e100204
d2820007
041e1104
c2020110
bf8c007f
7e100204
d2100008
02021101
c2020114
bf8c007f
7e120204
d2820008
04221302
c2020118
bf8c007f
7e120204
d2820008
04221303
c202011c
bf8c007f
7e120204
d2820001
04221304
f800021f
05060701
c0820700
bf8c000f
e00c2000
80010000
c2020103
bf8c0070
7e080204
d2100004
02020900
c2020107
bf8c007f
7e0a0204
d2820004
04120b01
c202010b
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020102
bf8c007f
7e0a0204
d2100005
02020b00
c2020106
bf8c007f
7e0c0204
d2820005
04160d01
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010e
bf8c007f
7e0c0204
d2820005
04160d03
c2020101
bf8c007f
7e0c0204
d2100006
02020d00
c2020105
bf8c007f
7e0e0204
d2820006
041a0f01
c2020109
bf8c007f
7e0e0204
d2820006
041a0f02
c202010d
bf8c007f
7e0e0204
d2820006
041a0f03
c2020100
bf8c007f
7e0e0204
d2100007
02020f00
c2020104
bf8c007f
7e100204
d2820007
041e1101
c2020108
bf8c007f
7e100204
d2820007
041e1102
c200010c
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[1..4]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: MOV TEMP[0].w, IN[0].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], CONST[4]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %32 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %33 = fdiv float %30, %32
  %34 = fdiv float %31, %32
  %35 = bitcast float %33 to i32
  %36 = bitcast float %34 to i32
  %37 = insertelement <2 x i32> undef, i32 %35, i32 0
  %38 = insertelement <2 x i32> %37, i32 %36, i32 1
  %39 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %38, <32 x i8> %27, <16 x i8> %29, i32 2)
  %40 = extractelement <4 x float> %39, i32 0
  %41 = extractelement <4 x float> %39, i32 1
  %42 = extractelement <4 x float> %39, i32 2
  %43 = extractelement <4 x float> %39, i32 3
  %44 = fmul float %40, %22
  %45 = fmul float %41, %23
  %46 = fmul float %42, %24
  %47 = fmul float %43, %25
  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
  %49 = bitcast i32 %48 to float
  %50 = call i32 @llvm.SI.packf16(float %46, float %47)
  %51 = bitcast i32 %50 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %49, float %51, float %49, float %51)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080100
c8090101
c80c0300
c80d0301
7e065503
100a0702
c8080000
c8090001
10080702
c0840300
c0c60500
bf8c007f
f0800f00
00430004
c0800100
bf8c0070
c2020113
bf8c007f
7e080204
d2100004
02020903
c2020112
bf8c007f
7e0a0204
d2100005
02020b02
5e080905
c2020111
bf8c007f
7e0a0204
d2100005
02020b01
c2000110
bf8c007f
7e0c0200
d2100000
02020d00
5e000b00
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
DCL CONST[0..7]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MUL TEMP[0], IN[1].xxxx, CONST[4]
  5: MAD TEMP[0], IN[1].yyyy, CONST[5], TEMP[0]
  6: MAD TEMP[0], IN[1].zzzz, CONST[6], TEMP[0]
  7: MAD OUT[1], IN[1].wwww, CONST[7], TEMP[0]
  8: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 108)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112)
  %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116)
  %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 120)
  %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 124)
  %44 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %45 = load <16 x i8> addrspace(2)* %44, !tbaa !0
  %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %45, i32 0, i32 %6)
  %47 = extractelement <4 x float> %46, i32 0
  %48 = extractelement <4 x float> %46, i32 1
  %49 = extractelement <4 x float> %46, i32 2
  %50 = extractelement <4 x float> %46, i32 3
  %51 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %52, i32 0, i32 %6)
  %54 = extractelement <4 x float> %53, i32 0
  %55 = extractelement <4 x float> %53, i32 1
  %56 = extractelement <4 x float> %53, i32 2
  %57 = extractelement <4 x float> %53, i32 3
  %58 = fmul float %47, %12
  %59 = fmul float %47, %13
  %60 = fmul float %47, %14
  %61 = fmul float %47, %15
  %62 = fmul float %48, %16
  %63 = fadd float %62, %58
  %64 = fmul float %48, %17
  %65 = fadd float %64, %59
  %66 = fmul float %48, %18
  %67 = fadd float %66, %60
  %68 = fmul float %48, %19
  %69 = fadd float %68, %61
  %70 = fmul float %49, %20
  %71 = fadd float %70, %63
  %72 = fmul float %49, %21
  %73 = fadd float %72, %65
  %74 = fmul float %49, %22
  %75 = fadd float %74, %67
  %76 = fmul float %49, %23
  %77 = fadd float %76, %69
  %78 = fmul float %50, %24
  %79 = fadd float %78, %71
  %80 = fmul float %50, %25
  %81 = fadd float %80, %73
  %82 = fmul float %50, %26
  %83 = fadd float %82, %75
  %84 = fmul float %50, %27
  %85 = fadd float %84, %77
  %86 = fmul float %54, %28
  %87 = fmul float %54, %29
  %88 = fmul float %54, %30
  %89 = fmul float %54, %31
  %90 = fmul float %55, %32
  %91 = fadd float %90, %86
  %92 = fmul float %55, %33
  %93 = fadd float %92, %87
  %94 = fmul float %55, %34
  %95 = fadd float %94, %88
  %96 = fmul float %55, %35
  %97 = fadd float %96, %89
  %98 = fmul float %56, %36
  %99 = fadd float %98, %91
  %100 = fmul float %56, %37
  %101 = fadd float %100, %93
  %102 = fmul float %56, %38
  %103 = fadd float %102, %95
  %104 = fmul float %56, %39
  %105 = fadd float %104, %97
  %106 = fmul float %57, %40
  %107 = fadd float %106, %99
  %108 = fmul float %57, %41
  %109 = fadd float %108, %101
  %110 = fmul float %57, %42
  %111 = fadd float %110, %103
  %112 = fmul float %57, %43
  %113 = fadd float %112, %105
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %107, float %109, float %111, float %113)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %79, float %81, float %83, float %85)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020113
bf8c007f
7e0a0204
d2100005
02020b01
c2020117
bf8c007f
7e0c0204
d2820005
04160d02
c202011b
bf8c007f
7e0c0204
d2820005
04160d03
c202011f
bf8c007f
7e0c0204
d2820005
04160d04
c2020112
bf8c007f
7e0c0204
d2100006
02020d01
c2020116
bf8c007f
7e0e0204
d2820006
041a0f02
c202011a
bf8c007f
7e0e0204
d2820006
041a0f03
c202011e
bf8c007f
7e0e0204
d2820006
041a0f04
c2020111
bf8c007f
7e0e0204
d2100007
02020f01
c2020115
bf8c007f
7e100204
d2820007
041e1102
c2020119
bf8c007f
7e100204
d2820007
041e1103
c202011d
bf8c007f
7e100204
d2820007
041e1104
c2020110
bf8c007f
7e100204
d2100008
02021101
c2020114
bf8c007f
7e120204
d2820008
04221302
c2020118
bf8c007f
7e120204
d2820008
04221303
c202011c
bf8c007f
7e120204
d2820001
04221304
f800020f
05060701
c0820700
bf8c000f
e00c2000
80010000
c2020103
bf8c0070
7e080204
d2100004
02020900
c2020107
bf8c007f
7e0a0204
d2820004
04120b01
c202010b
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020102
bf8c007f
7e0a0204
d2100005
02020b00
c2020106
bf8c007f
7e0c0204
d2820005
04160d01
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010e
bf8c007f
7e0c0204
d2820005
04160d03
c2020101
bf8c007f
7e0c0204
d2100006
02020d00
c2020105
bf8c007f
7e0e0204
d2820006
041a0f01
c2020109
bf8c007f
7e0e0204
d2820006
041a0f02
c202010d
bf8c007f
7e0e0204
d2820006
041a0f03
c2020100
bf8c007f
7e0e0204
d2100007
02020f00
c2020104
bf8c007f
7e100204
d2820007
041e1101
c2020108
bf8c007f
7e100204
d2820007
041e1102
c200010c
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000






































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..22]
DCL TEMP[0..4], LOCAL
IMM[0] FLT32 {   22.0000,     0.0000,    -0.5000,     0.0156}
IMM[1] FLT32 {    0.0001,     0.5000,     1.0000,     0.8000}
IMM[2] FLT32 {    0.2000,   -17.0000,     0.6667,     1.2000}
  0: ADD TEMP[0].x, IMM[0].xxxx, -IN[0].wwww
  1: FSLT TEMP[0].x, TEMP[0].xxxx, IMM[0].yyyy
  2: UIF TEMP[0].xxxx :0
  3:   KILL
  4: ENDIF
  5: MUL TEMP[0].xy, IN[0].xyyy, CONST[16].zwww
  6: MOV TEMP[0].xy, TEMP[0].xyyy
  7: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
  8: ADD TEMP[0].xyz, TEMP[0].xzyy, IMM[0].zzzz
  9: MUL TEMP[1].x, CONST[16].xxxx, IMM[0].wwww
 10: MUL TEMP[2].x, CONST[16].yyyy, IMM[0].wwww
 11: MOV TEMP[1].y, TEMP[2].xxxx
 12: DP3 TEMP[2].x, TEMP[0].xyzz, TEMP[0].xyzz
 13: RSQ TEMP[2].x, TEMP[2].xxxx
 14: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
 15: MUL TEMP[2].x, IN[0].wwww, IN[0].wwww
 16: MUL TEMP[2].x, TEMP[2].xxxx, IN[0].wwww
 17: MUL_SAT TEMP[2].x, IMM[1].xxxx, TEMP[2].xxxx
 18: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
 19: DP3 TEMP[0].x, TEMP[0].xyzz, -CONST[17].xyzz
 20: MAD TEMP[0].x, TEMP[0].xxxx, IMM[1].yyyy, IMM[1].yyyy
 21: MOV TEMP[2].w, IMM[1].zzzz
 22: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx
 23: MAD TEMP[0].x, IMM[1].wwww, TEMP[0].xxxx, IMM[2].xxxx
 24: MUL TEMP[1].xy, IN[0].xyyy, TEMP[1].xyyy
 25: MOV TEMP[1].xy, TEMP[1].xyyy
 26: TEX TEMP[1].xyz, TEMP[1], SAMP[2], 2D
 27: MUL TEMP[3].xy, IN[0].xyyy, CONST[16].zwww
 28: MOV TEMP[3].xy, TEMP[3].xyyy
 29: TEX TEMP[3].xyz, TEMP[3], SAMP[1], 2D
 30: ADD TEMP[4].x, IN[0].wwww, IMM[2].yyyy
 31: MUL TEMP[4].x, TEMP[4].xxxx, IMM[2].zzzz
 32: ADD_SAT TEMP[4].x, IMM[1].zzzz, -TEMP[4].xxxx
 33: LRP TEMP[1].xyz, TEMP[4].xxxx, TEMP[3].xyzz, TEMP[1].xyzz
 34: MUL TEMP[0].xyz, TEMP[0].xxxx, TEMP[1].xyzz
 35: MUL_SAT TEMP[0].xyz, TEMP[0].xyzz, IMM[2].wwww
 36: MOV TEMP[2].xyz, TEMP[0].xyzx
 37: MOV OUT[0], TEMP[2]
 38: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 264)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 268)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 276)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 280)
  %29 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %30 = load <32 x i8> addrspace(2)* %29, !tbaa !0
  %31 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0
  %35 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %43 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %44 = fsub float -0.000000e+00, %43
  %45 = fadd float 2.200000e+01, %44
  %46 = fcmp olt float %45, 0.000000e+00
  %47 = sext i1 %46 to i32
  %48 = bitcast i32 %47 to float
  %49 = bitcast float %48 to i32
  %50 = icmp ne i32 %49, 0
  br i1 %50, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  call void @llvm.AMDGPU.kilp()
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %51 = fmul float %41, %24
  %52 = fmul float %42, %25
  %53 = bitcast float %51 to i32
  %54 = bitcast float %52 to i32
  %55 = insertelement <2 x i32> undef, i32 %53, i32 0
  %56 = insertelement <2 x i32> %55, i32 %54, i32 1
  %57 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %56, <32 x i8> %30, <16 x i8> %32, i32 2)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = extractelement <4 x float> %57, i32 2
  %61 = fadd float %58, -5.000000e-01
  %62 = fadd float %60, -5.000000e-01
  %63 = fadd float %59, -5.000000e-01
  %64 = fmul float %22, 1.562500e-02
  %65 = fmul float %23, 1.562500e-02
  %66 = fmul float %61, %61
  %67 = fmul float %62, %62
  %68 = fadd float %67, %66
  %69 = fmul float %63, %63
  %70 = fadd float %68, %69
  %71 = call float @llvm.AMDGPU.rsq(float %70)
  %72 = fmul float %61, %71
  %73 = fmul float %62, %71
  %74 = fmul float %63, %71
  %75 = fmul float %43, %43
  %76 = fmul float %75, %43
  %77 = fmul float 0x3F231C07C0000000, %76
  %78 = call float @llvm.AMDIL.clamp.(float %77, float 0.000000e+00, float 1.000000e+00)
  %79 = fmul float %72, %78
  %80 = fmul float %73, %78
  %81 = fmul float %74, %78
  %82 = fsub float -0.000000e+00, %26
  %83 = fsub float -0.000000e+00, %27
  %84 = fsub float -0.000000e+00, %28
  %85 = fmul float %79, %82
  %86 = fmul float %80, %83
  %87 = fadd float %86, %85
  %88 = fmul float %81, %84
  %89 = fadd float %87, %88
  %90 = fmul float %89, 5.000000e-01
  %91 = fadd float %90, 5.000000e-01
  %92 = fmul float %91, %91
  %93 = fmul float 0x3FE99999A0000000, %92
  %94 = fadd float %93, 0x3FC99999A0000000
  %95 = fmul float %41, %64
  %96 = fmul float %42, %65
  %97 = bitcast float %95 to i32
  %98 = bitcast float %96 to i32
  %99 = insertelement <2 x i32> undef, i32 %97, i32 0
  %100 = insertelement <2 x i32> %99, i32 %98, i32 1
  %101 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %100, <32 x i8> %38, <16 x i8> %40, i32 2)
  %102 = extractelement <4 x float> %101, i32 0
  %103 = extractelement <4 x float> %101, i32 1
  %104 = extractelement <4 x float> %101, i32 2
  %105 = fmul float %41, %24
  %106 = fmul float %42, %25
  %107 = bitcast float %105 to i32
  %108 = bitcast float %106 to i32
  %109 = insertelement <2 x i32> undef, i32 %107, i32 0
  %110 = insertelement <2 x i32> %109, i32 %108, i32 1
  %111 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %110, <32 x i8> %34, <16 x i8> %36, i32 2)
  %112 = extractelement <4 x float> %111, i32 0
  %113 = extractelement <4 x float> %111, i32 1
  %114 = extractelement <4 x float> %111, i32 2
  %115 = fadd float %43, -1.700000e+01
  %116 = fmul float %115, 0x3FE5555560000000
  %117 = fsub float -0.000000e+00, %116
  %118 = fadd float 1.000000e+00, %117
  %119 = call float @llvm.AMDIL.clamp.(float %118, float 0.000000e+00, float 1.000000e+00)
  %120 = call float @llvm.AMDGPU.lrp(float %119, float %112, float %102)
  %121 = call float @llvm.AMDGPU.lrp(float %119, float %113, float %103)
  %122 = call float @llvm.AMDGPU.lrp(float %119, float %114, float %104)
  %123 = fmul float %94, %120
  %124 = fmul float %94, %121
  %125 = fmul float %94, %122
  %126 = fmul float %123, 0x3FF3333340000000
  %127 = fmul float %124, 0x3FF3333340000000
  %128 = fmul float %125, 0x3FF3333340000000
  %129 = call float @llvm.AMDIL.clamp.(float %126, float 0.000000e+00, float 1.000000e+00)
  %130 = call float @llvm.AMDIL.clamp.(float %127, float 0.000000e+00, float 1.000000e+00)
  %131 = call float @llvm.AMDIL.clamp.(float %128, float 0.000000e+00, float 1.000000e+00)
  %132 = call i32 @llvm.SI.packf16(float %129, float %130)
  %133 = bitcast i32 %132 to float
  %134 = call i32 @llvm.SI.packf16(float %131, float 1.000000e+00)
  %135 = bitcast i32 %134 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %133, float %135, float %133, float %135)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

declare void @llvm.AMDGPU.kilp()

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080100
c8090101
c8100000
c8110001
c80c0300
c80d0301
080006ff
41b00000
d0020006
02010100
c08a0308
c0cc0510
c0840304
c0c60508
c0900300
c0d20500
c0960100
bf8c007f
c2012d46
c201ad45
c2022d44
c202ad43
c2182d42
c200ad41
c2002d40
bf8c007f
7e020205
7e000230
be862406
8986067e
7e0a02f3
7c260a80
88fe067e
d2100006
02020302
d2100005
02020104
f0800700
01090705
bf8c0770
d2060000
0201e309
d2060001
0201e307
10140301
d282000a
042a0100
d2060007
0201e308
d2820008
042a0f07
7e105b08
10021101
d2100009
02020703
10121303
101212ff
3918e03e
d2060809
02010109
10021301
10020204
10001100
10001300
d206000a
22010003
10001500
08000300
10021107
10021301
10020202
08000300
d2820000
03c1e100
10000100
7e0202ff
3e4ccccd
7e0e02ff
3f4ccccd
d2820000
04060f00
7e0202ff
3c800000
100e0201
10100f02
10020200
100e0304
f0800700
00a60707
7e0202ff
c1880000
06020303
7e0402ff
bf2aaaab
d2820001
03ca0501
d2060801
02010101
080402f2
bf8c0770
10061102
f0800700
00430405
bf8c0770
d2820003
040e0b01
10060700
100606ff
3f99999a
d2060803
02010103
10140f02
d282000a
042a0901
10141500
101414ff
3f99999a
d206080a
0201010a
5e06070a
10041302
d2820001
040a0d01
10000300
100000ff
3f99999a
d2060800
02010100
d25e0000
0201e500
f8001c0f
00030003
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..24]
DCL TEMP[0..5], LOCAL
IMM[0] FLT32 {   -1.0000,     1.0000,     0.5000,     0.0100}
IMM[1] INT32 {0, 1, 2, 3}
  0: MAD TEMP[0].xy, IN[0].xyyy, CONST[23].zzzz, CONST[23].xyyy
  1: ADD TEMP[1].x, IN[0].zzzz, IMM[0].xxxx
  2: F2I TEMP[1].x, TEMP[1].xxxx
  3: USEQ TEMP[1].yzw, TEMP[1].xxxx, IMM[1]
  4: I2F TEMP[2].y, TEMP[1].yyyy
  5: CMP TEMP[2].x, TEMP[2].yyyy, CONST[24].yyyy, CONST[24].xxxx
  6: I2F TEMP[3].z, TEMP[1].zzzz
  7: CMP TEMP[2].x, TEMP[3].zzzz, CONST[24].zzzz, TEMP[2].xxxx
  8: I2F TEMP[1].w, TEMP[1].wwww
  9: CMP TEMP[2].x, TEMP[1].wwww, CONST[24].wwww, TEMP[2].xxxx
 10: MOV_SAT TEMP[1].x, IN[0].zzzz
 11: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
 12: ADD TEMP[2].x, IMM[0].yyyy, -IN[0].wwww
 13: MOV TEMP[2].y, IN[0].wwww
 14: MUL TEMP[2].xy, TEMP[1].xxxx, TEMP[2].xyyy
 15: MAD TEMP[0].xy, TEMP[2].xyyy, CONST[23].zzzz, TEMP[0].xyyy
 16: ADD TEMP[2].x, TEMP[0].xxxx, IMM[0].zzzz
 17: RCP TEMP[3].x, CONST[16].xxxx
 18: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
 19: ADD TEMP[3].x, TEMP[0].yyyy, IMM[0].zzzz
 20: ADD TEMP[3].x, TEMP[3].xxxx, -CONST[16].yyyy
 21: RCP TEMP[4].x, -CONST[16].yyyy
 22: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 23: MOV TEMP[2].y, TEMP[3].xxxx
 24: MOV TEMP[3].x, TEMP[0].xxxx
 25: ADD TEMP[4].x, IMM[0].yyyy, -TEMP[1].xxxx
 26: MUL TEMP[4].x, IN[1].xxxx, TEMP[4].xxxx
 27: MAD TEMP[1].x, IN[1].yyyy, TEMP[1].xxxx, TEMP[4].xxxx
 28: MUL TEMP[1].x, TEMP[1].xxxx, IMM[0].wwww
 29: MOV TEMP[3].y, TEMP[1].xxxx
 30: MOV TEMP[4].w, IMM[0].yyyy
 31: MOV TEMP[4].x, TEMP[0].xxxx
 32: MOV TEMP[4].y, TEMP[1].xxxx
 33: MOV TEMP[4].z, TEMP[0].yyyy
 34: DP4 TEMP[1].x, TEMP[4], CONST[0]
 35: DP4 TEMP[5].x, TEMP[4], CONST[1]
 36: MOV TEMP[1].y, TEMP[5].xxxx
 37: DP4 TEMP[5].x, TEMP[4], CONST[2]
 38: MOV TEMP[1].z, TEMP[5].xxxx
 39: DP4 TEMP[4].x, TEMP[4], CONST[3]
 40: MOV TEMP[1].w, TEMP[4].xxxx
 41: MOV TEMP[2].xy, TEMP[2].xyxx
 42: MOV TEMP[2].zw, TEMP[3].yyxy
 43: MOV TEMP[0].x, TEMP[0].yyyy
 44: MOV OUT[0], TEMP[1]
 45: MOV OUT[2], TEMP[0]
 46: MOV OUT[1], TEMP[2]
 47: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 256)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 260)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 368)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 372)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 376)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 384)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 388)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 392)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 396)
  %37 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
  %39 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %6)
  %40 = extractelement <4 x float> %39, i32 0
  %41 = extractelement <4 x float> %39, i32 1
  %42 = extractelement <4 x float> %39, i32 2
  %43 = extractelement <4 x float> %39, i32 3
  %44 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %45 = load <16 x i8> addrspace(2)* %44, !tbaa !0
  %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %45, i32 0, i32 %6)
  %47 = extractelement <4 x float> %46, i32 0
  %48 = extractelement <4 x float> %46, i32 1
  %49 = fmul float %40, %32
  %50 = fadd float %49, %30
  %51 = fmul float %41, %32
  %52 = fadd float %51, %31
  %53 = fadd float %42, -1.000000e+00
  %54 = fptosi float %53 to i32
  %55 = bitcast i32 %54 to float
  %56 = bitcast float %55 to i32
  %57 = icmp eq i32 %56, 1
  %58 = sext i1 %57 to i32
  %59 = bitcast float %55 to i32
  %60 = icmp eq i32 %59, 2
  %61 = sext i1 %60 to i32
  %62 = bitcast float %55 to i32
  %63 = icmp eq i32 %62, 3
  %64 = sext i1 %63 to i32
  %65 = bitcast i32 %58 to float
  %66 = bitcast i32 %61 to float
  %67 = bitcast i32 %64 to float
  %68 = bitcast float %65 to i32
  %69 = sitofp i32 %68 to float
  %70 = call float @llvm.AMDGPU.cndlt(float %69, float %34, float %33)
  %71 = bitcast float %66 to i32
  %72 = sitofp i32 %71 to float
  %73 = call float @llvm.AMDGPU.cndlt(float %72, float %35, float %70)
  %74 = bitcast float %67 to i32
  %75 = sitofp i32 %74 to float
  %76 = call float @llvm.AMDGPU.cndlt(float %75, float %36, float %73)
  %77 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
  %78 = fmul float %77, %76
  %79 = fsub float -0.000000e+00, %43
  %80 = fadd float 1.000000e+00, %79
  %81 = fmul float %78, %80
  %82 = fmul float %78, %43
  %83 = fmul float %81, %32
  %84 = fadd float %83, %50
  %85 = fmul float %82, %32
  %86 = fadd float %85, %52
  %87 = fadd float %84, 5.000000e-01
  %88 = fdiv float 1.000000e+00, %28
  %89 = fmul float %87, %88
  %90 = fadd float %86, 5.000000e-01
  %91 = fsub float -0.000000e+00, %29
  %92 = fadd float %90, %91
  %93 = fsub float -0.000000e+00, %29
  %94 = fdiv float 1.000000e+00, %93
  %95 = fmul float %92, %94
  %96 = fsub float -0.000000e+00, %78
  %97 = fadd float 1.000000e+00, %96
  %98 = fmul float %47, %97
  %99 = fmul float %48, %78
  %100 = fadd float %99, %98
  %101 = fmul float %100, 0x3F847AE140000000
  %102 = fmul float %84, %12
  %103 = fmul float %101, %13
  %104 = fadd float %102, %103
  %105 = fmul float %86, %14
  %106 = fadd float %104, %105
  %107 = fmul float 1.000000e+00, %15
  %108 = fadd float %106, %107
  %109 = fmul float %84, %16
  %110 = fmul float %101, %17
  %111 = fadd float %109, %110
  %112 = fmul float %86, %18
  %113 = fadd float %111, %112
  %114 = fmul float 1.000000e+00, %19
  %115 = fadd float %113, %114
  %116 = fmul float %84, %20
  %117 = fmul float %101, %21
  %118 = fadd float %116, %117
  %119 = fmul float %86, %22
  %120 = fadd float %118, %119
  %121 = fmul float 1.000000e+00, %23
  %122 = fadd float %120, %121
  %123 = fmul float %84, %24
  %124 = fmul float %101, %25
  %125 = fadd float %123, %124
  %126 = fmul float %86, %26
  %127 = fadd float %125, %126
  %128 = fmul float 1.000000e+00, %27
  %129 = fadd float %127, %128
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %89, float %95, float %84, float %101)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %86, float %86, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %108, float %115, float %122, float %129)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.cndlt(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840700
bf8c007f
e00c2000
80020100
bf8c0770
d2060005
0201e703
7e0a1105
d1040002
02010305
d2000006
00098280
7e0c0b06
d0080002
02020c80
c0840100
bf8c007f
c2000961
bf8c007f
7e0c0200
c2000960
bf8c007f
7e0e0200
d2000006
000a0d07
d1040000
02010505
d2000007
00018280
7e0e0b07
d0080000
02020e80
c2010962
bf8c007f
7e0e0202
d2000006
00020f06
d1040000
02010705
d2000005
00018280
7e0a0b05
d0080000
02020a80
c2010963
bf8c007f
7e0a0202
d2000005
00020b06
d2060806
02010103
100a0b06
080c0af2
c0800704
bf8c007f
e00c2000
80000700
bf8c0770
10000d07
d2820000
04020b08
100000ff
3c23d70a
080c08f2
100c0d05
c200095c
bf8c007f
7e0e0200
c200095e
bf8c007f
7e100200
d2820007
041e1101
d2820006
041c0106
060e0cf0
c2008940
bf8c007f
7e125401
100e1307
100a0905
c200895d
bf8c007f
7e120201
d2820001
04261102
d2820001
04040105
060402f0
c2000941
bf8c007f
0a040400
d2060003
22010000
7e065503
10040702
f800020f
00060207
bf8c070f
7e040280
f800021f
02020101
c200090d
bf8c000f
10040000
c200090c
bf8c007f
d2820002
04080106
c200090e
bf8c007f
d2820002
04080101
c200090f
bf8c007f
06040400
c2000909
bf8c007f
10060000
c2000908
bf8c007f
d2820003
040c0106
c200090a
bf8c007f
d2820003
040c0101
c200090b
bf8c007f
06060600
c2000905
bf8c007f
10080000
c2000904
bf8c007f
d2820004
04100106
c2000906
bf8c007f
d2820004
04100101
c2000907
bf8c007f
06080800
c2000901
bf8c007f
10000000
c2000900
bf8c007f
d2820000
04000106
c2000902
bf8c007f
d2820000
04000101
c2000903
bf8c007f
06000000
f80008cf
02030400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL SAMP[4]
DCL SAMP[5]
DCL CONST[0..22]
DCL TEMP[0..7], LOCAL
IMM[0] FLT32 {    0.5000,     2.0000,     1.0000,    -0.5000}
IMM[1] FLT32 {    0.8000,     0.2000,     0.2500,     1.2000}
IMM[2] FLT32 {-160000.0000,     0.0000,     0.0200,     0.0039}
IMM[3] FLT32 {    0.1000,     6.2832,     0.0000,     0.0000}
  0: MOV TEMP[0].x, IN[1].wwww
  1: MOV TEMP[0].yz, IN[2].yxyy
  2: MOV TEMP[1].xy, IN[0].xyyy
  3: TEX TEMP[1].xyz, TEMP[1], SAMP[2], 2D
  4: MOV TEMP[2].xy, IN[0].zwww
  5: TEX TEMP[2].xyz, TEMP[2], SAMP[3], 2D
  6: FSLT TEMP[3].x, TEMP[2].xxxx, IMM[0].xxxx
  7: UIF TEMP[3].xxxx :0
  8:   MUL TEMP[3].x, IMM[0].yyyy, TEMP[2].xxxx
  9:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[1].xxxx
 10: ELSE :0
 11:   ADD TEMP[4].x, IMM[0].zzzz, -TEMP[2].xxxx
 12:   MUL TEMP[4].x, IMM[0].yyyy, TEMP[4].xxxx
 13:   ADD TEMP[5].x, IMM[0].zzzz, -TEMP[1].xxxx
 14:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 15:   ADD TEMP[3].x, IMM[0].zzzz, -TEMP[4].xxxx
 16: ENDIF
 17: MOV TEMP[3].x, TEMP[3].xxxx
 18: FSLT TEMP[4].x, TEMP[2].yyyy, IMM[0].xxxx
 19: UIF TEMP[4].xxxx :0
 20:   MUL TEMP[4].x, IMM[0].yyyy, TEMP[2].yyyy
 21:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[1].yyyy
 22: ELSE :0
 23:   ADD TEMP[5].x, IMM[0].zzzz, -TEMP[2].yyyy
 24:   MUL TEMP[5].x, IMM[0].yyyy, TEMP[5].xxxx
 25:   ADD TEMP[6].x, IMM[0].zzzz, -TEMP[1].yyyy
 26:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 27:   ADD TEMP[4].x, IMM[0].zzzz, -TEMP[5].xxxx
 28: ENDIF
 29: MOV TEMP[3].y, TEMP[4].xxxx
 30: FSLT TEMP[4].x, TEMP[2].zzzz, IMM[0].xxxx
 31: UIF TEMP[4].xxxx :0
 32:   MUL TEMP[4].x, IMM[0].yyyy, TEMP[2].zzzz
 33:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[1].zzzz
 34: ELSE :0
 35:   ADD TEMP[2].x, IMM[0].zzzz, -TEMP[2].zzzz
 36:   MUL TEMP[2].x, IMM[0].yyyy, TEMP[2].xxxx
 37:   ADD TEMP[5].x, IMM[0].zzzz, -TEMP[1].zzzz
 38:   MUL TEMP[2].x, TEMP[2].xxxx, TEMP[5].xxxx
 39:   ADD TEMP[4].x, IMM[0].zzzz, -TEMP[2].xxxx
 40: ENDIF
 41: MOV TEMP[3].z, TEMP[4].xxxx
 42: LRP TEMP[1].xyz, IMM[0].xxxx, TEMP[3].xyzz, TEMP[1].xyzz
 43: MOV TEMP[2].xy, IN[0].xyyy
 44: TEX TEMP[2].xyz, TEMP[2], SAMP[1], 2D
 45: ADD TEMP[2].xyz, TEMP[2].xyzz, IMM[0].wwww
 46: ADD TEMP[3].x, IN[1].wwww, IMM[0].xxxx
 47: RCP TEMP[4].x, CONST[16].xxxx
 48: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 49: ADD TEMP[4].x, IN[2].yyyy, IMM[0].xxxx
 50: ADD TEMP[4].x, TEMP[4].xxxx, -CONST[16].yyyy
 51: RCP TEMP[5].x, -CONST[16].yyyy
 52: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 53: MOV TEMP[3].y, TEMP[4].xxxx
 54: MOV TEMP[3].xy, TEMP[3].xyyy
 55: TEX TEMP[3].xyz, TEMP[3], SAMP[0], 2D
 56: FSLT TEMP[4].x, TEMP[3].xxxx, IMM[0].xxxx
 57: UIF TEMP[4].xxxx :0
 58:   MUL TEMP[4].x, IMM[0].yyyy, TEMP[3].xxxx
 59:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[1].xxxx
 60: ELSE :0
 61:   ADD TEMP[5].x, IMM[0].zzzz, -TEMP[3].xxxx
 62:   MUL TEMP[5].x, IMM[0].yyyy, TEMP[5].xxxx
 63:   ADD TEMP[6].x, IMM[0].zzzz, -TEMP[1].xxxx
 64:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 65:   ADD TEMP[4].x, IMM[0].zzzz, -TEMP[5].xxxx
 66: ENDIF
 67: MOV TEMP[4].x, TEMP[4].xxxx
 68: FSLT TEMP[5].x, TEMP[3].yyyy, IMM[0].xxxx
 69: UIF TEMP[5].xxxx :0
 70:   MUL TEMP[5].x, IMM[0].yyyy, TEMP[3].yyyy
 71:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[1].yyyy
 72: ELSE :0
 73:   ADD TEMP[6].x, IMM[0].zzzz, -TEMP[3].yyyy
 74:   MUL TEMP[6].x, IMM[0].yyyy, TEMP[6].xxxx
 75:   ADD TEMP[7].x, IMM[0].zzzz, -TEMP[1].yyyy
 76:   MUL TEMP[6].x, TEMP[6].xxxx, TEMP[7].xxxx
 77:   ADD TEMP[5].x, IMM[0].zzzz, -TEMP[6].xxxx
 78: ENDIF
 79: MOV TEMP[4].y, TEMP[5].xxxx
 80: FSLT TEMP[5].x, TEMP[3].zzzz, IMM[0].xxxx
 81: UIF TEMP[5].xxxx :0
 82:   MUL TEMP[5].x, IMM[0].yyyy, TEMP[3].zzzz
 83:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[1].zzzz
 84: ELSE :0
 85:   ADD TEMP[3].x, IMM[0].zzzz, -TEMP[3].zzzz
 86:   MUL TEMP[3].x, IMM[0].yyyy, TEMP[3].xxxx
 87:   ADD TEMP[6].x, IMM[0].zzzz, -TEMP[1].zzzz
 88:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
 89:   ADD TEMP[5].x, IMM[0].zzzz, -TEMP[3].xxxx
 90: ENDIF
 91: MOV TEMP[4].z, TEMP[5].xxxx
 92: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
 93: RSQ TEMP[3].x, TEMP[3].xxxx
 94: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx
 95: DP3 TEMP[3].x, IN[1].xyzz, IN[1].xyzz
 96: RSQ TEMP[3].x, TEMP[3].xxxx
 97: MUL TEMP[3].xyz, IN[1].xyzz, TEMP[3].xxxx
 98: DP3 TEMP[2].x, TEMP[2].xyzz, -TEMP[3].xyzz
 99: MAD TEMP[2].x, TEMP[2].xxxx, IMM[0].xxxx, IMM[0].xxxx
100: ADD TEMP[3].xyz, CONST[18].xyzz, -TEMP[0].xyzz
101: ADD TEMP[5].x, IN[1].wwww, IMM[0].xxxx
102: RCP TEMP[6].x, CONST[16].xxxx
103: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
104: ADD TEMP[6].x, IN[2].yyyy, IMM[0].xxxx
105: RCP TEMP[7].x, CONST[16].yyyy
106: MUL TEMP[6].x, TEMP[6].xxxx, TEMP[7].xxxx
107: MOV TEMP[5].y, TEMP[6].xxxx
108: MOV TEMP[6].w, IMM[0].zzzz
109: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
110: MAD TEMP[2].x, IMM[1].xxxx, TEMP[2].xxxx, IMM[1].yyyy
111: LRP TEMP[1].xyz, IMM[1].zzzz, TEMP[4].xyzz, TEMP[1].xyzz
112: MUL TEMP[1].xyz, TEMP[2].xxxx, TEMP[1].xyzz
113: MUL_SAT TEMP[1].xyz, TEMP[1].xyzz, IMM[1].wwww
114: DP3 TEMP[2].x, TEMP[3].xyzz, TEMP[3].xyzz
115: ADD TEMP[2].x, TEMP[2].xxxx, IMM[2].xxxx
116: MUL TEMP[2].x, TEMP[2].xxxx, IMM[2].yyyy
117: MIN TEMP[2].x, TEMP[2].xxxx, IMM[0].xxxx
118: MOV_SAT TEMP[2].x, TEMP[2].xxxx
119: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[3].xyzz
120: RSQ TEMP[4].x, TEMP[4].xxxx
121: MUL TEMP[3].y, TEMP[3].xyzz, TEMP[4].xxxx
122: ADD TEMP[3].x, IMM[0].zzzz, -TEMP[3].yyyy
123: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
124: LRP TEMP[1].xyz, TEMP[2].xxxx, IMM[0].xxxx, TEMP[1].xyzz
125: MOV TEMP[2].xy, TEMP[5].xyyy
126: TEX TEMP[2].w, TEMP[2], SAMP[5], 2D
127: ADD TEMP[0].xy, TEMP[0].xzzz, IMM[0].xxxx
128: MUL TEMP[0].xy, TEMP[0].xyyy, IMM[2].wwww
129: MAD TEMP[0].xy, CONST[22].yyyy, IMM[2].zzzz, TEMP[0].xyyy
130: MOV TEMP[0].xy, TEMP[0].xyyy
131: TEX TEMP[0].x, TEMP[0], SAMP[4], 2D
132: MUL TEMP[3].x, CONST[22].yyyy, IMM[3].xxxx
133: FRC TEMP[3].x, TEMP[3].xxxx
134: ADD TEMP[0].x, TEMP[0].xxxx, TEMP[3].xxxx
135: MUL TEMP[0].x, TEMP[0].xxxx, IMM[3].yyyy
136: SIN TEMP[0].x, TEMP[0].xxxx
137: MAD TEMP[0].x, TEMP[0].xxxx, IMM[3].xxxx, IMM[0].xxxx
138: ADD_SAT TEMP[0].x, TEMP[2].wwww, TEMP[0].xxxx
139: LRP TEMP[0].x, CONST[22].xxxx, TEMP[0].xxxx, IMM[0].zzzz
140: MUL_SAT TEMP[0].xyz, TEMP[1].xyzz, TEMP[0].xxxx
141: MOV TEMP[6].xyz, TEMP[0].xyzx
142: MOV OUT[0], TEMP[6]
143: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %29 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %30 = load <32 x i8> addrspace(2)* %29, !tbaa !0
  %31 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0
  %35 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %42 = load <32 x i8> addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
  %46 = load <32 x i8> addrspace(2)* %45, !tbaa !0
  %47 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
  %50 = load <32 x i8> addrspace(2)* %49, !tbaa !0
  %51 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %54 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %55 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %56 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %57 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %59 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %60 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %61 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %62 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %63 = bitcast float %53 to i32
  %64 = bitcast float %54 to i32
  %65 = insertelement <2 x i32> undef, i32 %63, i32 0
  %66 = insertelement <2 x i32> %65, i32 %64, i32 1
  %67 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %66, <32 x i8> %38, <16 x i8> %40, i32 2)
  %68 = extractelement <4 x float> %67, i32 0
  %69 = extractelement <4 x float> %67, i32 1
  %70 = extractelement <4 x float> %67, i32 2
  %71 = bitcast float %55 to i32
  %72 = bitcast float %56 to i32
  %73 = insertelement <2 x i32> undef, i32 %71, i32 0
  %74 = insertelement <2 x i32> %73, i32 %72, i32 1
  %75 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %74, <32 x i8> %42, <16 x i8> %44, i32 2)
  %76 = extractelement <4 x float> %75, i32 0
  %77 = extractelement <4 x float> %75, i32 1
  %78 = extractelement <4 x float> %75, i32 2
  %79 = fcmp olt float %76, 5.000000e-01
  %80 = sext i1 %79 to i32
  %81 = bitcast i32 %80 to float
  %82 = bitcast float %81 to i32
  %83 = icmp ne i32 %82, 0
  br i1 %83, label %IF, label %ELSE

IF:                                               ; preds = %main_body
  %84 = fmul float 2.000000e+00, %76
  %85 = fmul float %84, %68
  br label %ENDIF

ELSE:                                             ; preds = %main_body
  %86 = fsub float -0.000000e+00, %76
  %87 = fadd float 1.000000e+00, %86
  %88 = fmul float 2.000000e+00, %87
  %89 = fsub float -0.000000e+00, %68
  %90 = fadd float 1.000000e+00, %89
  %91 = fmul float %88, %90
  %92 = fsub float -0.000000e+00, %91
  %93 = fadd float 1.000000e+00, %92
  br label %ENDIF

ENDIF:                                            ; preds = %ELSE, %IF
  %temp12.0 = phi float [ %85, %IF ], [ %93, %ELSE ]
  %94 = fcmp olt float %77, 5.000000e-01
  %95 = sext i1 %94 to i32
  %96 = bitcast i32 %95 to float
  %97 = bitcast float %96 to i32
  %98 = icmp ne i32 %97, 0
  br i1 %98, label %IF33, label %ELSE34

IF33:                                             ; preds = %ENDIF
  %99 = fmul float 2.000000e+00, %77
  %100 = fmul float %99, %69
  br label %ENDIF32

ELSE34:                                           ; preds = %ENDIF
  %101 = fsub float -0.000000e+00, %77
  %102 = fadd float 1.000000e+00, %101
  %103 = fmul float 2.000000e+00, %102
  %104 = fsub float -0.000000e+00, %69
  %105 = fadd float 1.000000e+00, %104
  %106 = fmul float %103, %105
  %107 = fsub float -0.000000e+00, %106
  %108 = fadd float 1.000000e+00, %107
  br label %ENDIF32

ENDIF32:                                          ; preds = %ELSE34, %IF33
  %temp16.0 = phi float [ %100, %IF33 ], [ %108, %ELSE34 ]
  %109 = fcmp olt float %78, 5.000000e-01
  %110 = sext i1 %109 to i32
  %111 = bitcast i32 %110 to float
  %112 = bitcast float %111 to i32
  %113 = icmp ne i32 %112, 0
  br i1 %113, label %IF36, label %ELSE37

IF36:                                             ; preds = %ENDIF32
  %114 = fmul float 2.000000e+00, %78
  %115 = fmul float %114, %70
  br label %ENDIF35

ELSE37:                                           ; preds = %ENDIF32
  %116 = fsub float -0.000000e+00, %78
  %117 = fadd float 1.000000e+00, %116
  %118 = fmul float 2.000000e+00, %117
  %119 = fsub float -0.000000e+00, %70
  %120 = fadd float 1.000000e+00, %119
  %121 = fmul float %118, %120
  %122 = fsub float -0.000000e+00, %121
  %123 = fadd float 1.000000e+00, %122
  br label %ENDIF35

ENDIF35:                                          ; preds = %ELSE37, %IF36
  %temp16.1 = phi float [ %115, %IF36 ], [ %123, %ELSE37 ]
  %124 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp12.0, float %68)
  %125 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp16.0, float %69)
  %126 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp16.1, float %70)
  %127 = bitcast float %53 to i32
  %128 = bitcast float %54 to i32
  %129 = insertelement <2 x i32> undef, i32 %127, i32 0
  %130 = insertelement <2 x i32> %129, i32 %128, i32 1
  %131 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %130, <32 x i8> %34, <16 x i8> %36, i32 2)
  %132 = extractelement <4 x float> %131, i32 0
  %133 = extractelement <4 x float> %131, i32 1
  %134 = extractelement <4 x float> %131, i32 2
  %135 = fadd float %132, -5.000000e-01
  %136 = fadd float %133, -5.000000e-01
  %137 = fadd float %134, -5.000000e-01
  %138 = fadd float %60, 5.000000e-01
  %139 = fdiv float 1.000000e+00, %22
  %140 = fmul float %138, %139
  %141 = fadd float %62, 5.000000e-01
  %142 = fsub float -0.000000e+00, %23
  %143 = fadd float %141, %142
  %144 = fsub float -0.000000e+00, %23
  %145 = fdiv float 1.000000e+00, %144
  %146 = fmul float %143, %145
  %147 = bitcast float %140 to i32
  %148 = bitcast float %146 to i32
  %149 = insertelement <2 x i32> undef, i32 %147, i32 0
  %150 = insertelement <2 x i32> %149, i32 %148, i32 1
  %151 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %150, <32 x i8> %30, <16 x i8> %32, i32 2)
  %152 = extractelement <4 x float> %151, i32 0
  %153 = extractelement <4 x float> %151, i32 1
  %154 = extractelement <4 x float> %151, i32 2
  %155 = fcmp olt float %152, 5.000000e-01
  %156 = sext i1 %155 to i32
  %157 = bitcast i32 %156 to float
  %158 = bitcast float %157 to i32
  %159 = icmp ne i32 %158, 0
  br i1 %159, label %IF39, label %ELSE40

IF39:                                             ; preds = %ENDIF35
  %160 = fmul float 2.000000e+00, %152
  %161 = fmul float %160, %124
  br label %ENDIF38

ELSE40:                                           ; preds = %ENDIF35
  %162 = fsub float -0.000000e+00, %152
  %163 = fadd float 1.000000e+00, %162
  %164 = fmul float 2.000000e+00, %163
  %165 = fsub float -0.000000e+00, %124
  %166 = fadd float 1.000000e+00, %165
  %167 = fmul float %164, %166
  %168 = fsub float -0.000000e+00, %167
  %169 = fadd float 1.000000e+00, %168
  br label %ENDIF38

ENDIF38:                                          ; preds = %ELSE40, %IF39
  %temp16.2 = phi float [ %161, %IF39 ], [ %169, %ELSE40 ]
  %170 = fcmp olt float %153, 5.000000e-01
  %171 = sext i1 %170 to i32
  %172 = bitcast i32 %171 to float
  %173 = bitcast float %172 to i32
  %174 = icmp ne i32 %173, 0
  br i1 %174, label %IF42, label %ELSE43

IF42:                                             ; preds = %ENDIF38
  %175 = fmul float 2.000000e+00, %153
  %176 = fmul float %175, %125
  br label %ENDIF41

ELSE43:                                           ; preds = %ENDIF38
  %177 = fsub float -0.000000e+00, %153
  %178 = fadd float 1.000000e+00, %177
  %179 = fmul float 2.000000e+00, %178
  %180 = fsub float -0.000000e+00, %125
  %181 = fadd float 1.000000e+00, %180
  %182 = fmul float %179, %181
  %183 = fsub float -0.000000e+00, %182
  %184 = fadd float 1.000000e+00, %183
  br label %ENDIF41

ENDIF41:                                          ; preds = %ELSE43, %IF42
  %temp20.0 = phi float [ %176, %IF42 ], [ %184, %ELSE43 ]
  %185 = fcmp olt float %154, 5.000000e-01
  %186 = sext i1 %185 to i32
  %187 = bitcast i32 %186 to float
  %188 = bitcast float %187 to i32
  %189 = icmp ne i32 %188, 0
  br i1 %189, label %IF45, label %ELSE46

IF45:                                             ; preds = %ENDIF41
  %190 = fmul float 2.000000e+00, %154
  %191 = fmul float %190, %126
  br label %ENDIF44

ELSE46:                                           ; preds = %ENDIF41
  %192 = fsub float -0.000000e+00, %154
  %193 = fadd float 1.000000e+00, %192
  %194 = fmul float 2.000000e+00, %193
  %195 = fsub float -0.000000e+00, %126
  %196 = fadd float 1.000000e+00, %195
  %197 = fmul float %194, %196
  %198 = fsub float -0.000000e+00, %197
  %199 = fadd float 1.000000e+00, %198
  br label %ENDIF44

ENDIF44:                                          ; preds = %ELSE46, %IF45
  %temp20.1 = phi float [ %191, %IF45 ], [ %199, %ELSE46 ]
  %200 = fmul float %135, %135
  %201 = fmul float %136, %136
  %202 = fadd float %201, %200
  %203 = fmul float %137, %137
  %204 = fadd float %202, %203
  %205 = call float @llvm.AMDGPU.rsq(float %204)
  %206 = fmul float %135, %205
  %207 = fmul float %136, %205
  %208 = fmul float %137, %205
  %209 = fmul float %57, %57
  %210 = fmul float %58, %58
  %211 = fadd float %210, %209
  %212 = fmul float %59, %59
  %213 = fadd float %211, %212
  %214 = call float @llvm.AMDGPU.rsq(float %213)
  %215 = fmul float %57, %214
  %216 = fmul float %58, %214
  %217 = fmul float %59, %214
  %218 = fsub float -0.000000e+00, %215
  %219 = fsub float -0.000000e+00, %216
  %220 = fsub float -0.000000e+00, %217
  %221 = fmul float %206, %218
  %222 = fmul float %207, %219
  %223 = fadd float %222, %221
  %224 = fmul float %208, %220
  %225 = fadd float %223, %224
  %226 = fmul float %225, 5.000000e-01
  %227 = fadd float %226, 5.000000e-01
  %228 = fsub float -0.000000e+00, %60
  %229 = fadd float %24, %228
  %230 = fsub float -0.000000e+00, %61
  %231 = fadd float %25, %230
  %232 = fsub float -0.000000e+00, %62
  %233 = fadd float %26, %232
  %234 = fadd float %60, 5.000000e-01
  %235 = fdiv float 1.000000e+00, %22
  %236 = fmul float %234, %235
  %237 = fadd float %62, 5.000000e-01
  %238 = fdiv float 1.000000e+00, %23
  %239 = fmul float %237, %238
  %240 = fmul float %227, %227
  %241 = fmul float 0x3FE99999A0000000, %240
  %242 = fadd float %241, 0x3FC99999A0000000
  %243 = call float @llvm.AMDGPU.lrp(float 2.500000e-01, float %temp16.2, float %124)
  %244 = call float @llvm.AMDGPU.lrp(float 2.500000e-01, float %temp20.0, float %125)
  %245 = call float @llvm.AMDGPU.lrp(float 2.500000e-01, float %temp20.1, float %126)
  %246 = fmul float %242, %243
  %247 = fmul float %242, %244
  %248 = fmul float %242, %245
  %249 = fmul float %246, 0x3FF3333340000000
  %250 = fmul float %247, 0x3FF3333340000000
  %251 = fmul float %248, 0x3FF3333340000000
  %252 = call float @llvm.AMDIL.clamp.(float %249, float 0.000000e+00, float 1.000000e+00)
  %253 = call float @llvm.AMDIL.clamp.(float %250, float 0.000000e+00, float 1.000000e+00)
  %254 = call float @llvm.AMDIL.clamp.(float %251, float 0.000000e+00, float 1.000000e+00)
  %255 = fmul float %229, %229
  %256 = fmul float %231, %231
  %257 = fadd float %256, %255
  %258 = fmul float %233, %233
  %259 = fadd float %257, %258
  %260 = fadd float %259, -1.600000e+05
  %261 = fmul float %260, 0x3EAA36E2E0000000
  %262 = fcmp uge float %261, 5.000000e-01
  %263 = select i1 %262, float 5.000000e-01, float %261
  %264 = call float @llvm.AMDIL.clamp.(float %263, float 0.000000e+00, float 1.000000e+00)
  %265 = fmul float %229, %229
  %266 = fmul float %231, %231
  %267 = fadd float %266, %265
  %268 = fmul float %233, %233
  %269 = fadd float %267, %268
  %270 = call float @llvm.AMDGPU.rsq(float %269)
  %271 = fmul float %231, %270
  %272 = fsub float -0.000000e+00, %271
  %273 = fadd float 1.000000e+00, %272
  %274 = fmul float %264, %273
  %275 = call float @llvm.AMDGPU.lrp(float %274, float 5.000000e-01, float %252)
  %276 = call float @llvm.AMDGPU.lrp(float %274, float 5.000000e-01, float %253)
  %277 = call float @llvm.AMDGPU.lrp(float %274, float 5.000000e-01, float %254)
  %278 = bitcast float %236 to i32
  %279 = bitcast float %239 to i32
  %280 = insertelement <2 x i32> undef, i32 %278, i32 0
  %281 = insertelement <2 x i32> %280, i32 %279, i32 1
  %282 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %281, <32 x i8> %50, <16 x i8> %52, i32 2)
  %283 = extractelement <4 x float> %282, i32 3
  %284 = fadd float %60, 5.000000e-01
  %285 = fadd float %62, 5.000000e-01
  %286 = fmul float %284, 3.906250e-03
  %287 = fmul float %285, 3.906250e-03
  %288 = fmul float %28, 0x3F947AE140000000
  %289 = fadd float %288, %286
  %290 = fmul float %28, 0x3F947AE140000000
  %291 = fadd float %290, %287
  %292 = bitcast float %289 to i32
  %293 = bitcast float %291 to i32
  %294 = insertelement <2 x i32> undef, i32 %292, i32 0
  %295 = insertelement <2 x i32> %294, i32 %293, i32 1
  %296 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %295, <32 x i8> %46, <16 x i8> %48, i32 2)
  %297 = extractelement <4 x float> %296, i32 0
  %298 = fmul float %28, 0x3FB99999A0000000
  %299 = call float @llvm.AMDIL.fraction.(float %298)
  %300 = fadd float %297, %299
  %301 = fmul float %300, 0x401921FB60000000
  %302 = call float @llvm.sin.f32(float %301)
  %303 = fmul float %302, 0x3FB99999A0000000
  %304 = fadd float %303, 5.000000e-01
  %305 = fadd float %283, %304
  %306 = call float @llvm.AMDIL.clamp.(float %305, float 0.000000e+00, float 1.000000e+00)
  %307 = call float @llvm.AMDGPU.lrp(float %27, float %306, float 1.000000e+00)
  %308 = fmul float %275, %307
  %309 = fmul float %276, %307
  %310 = fmul float %277, %307
  %311 = call float @llvm.AMDIL.clamp.(float %308, float 0.000000e+00, float 1.000000e+00)
  %312 = call float @llvm.AMDIL.clamp.(float %309, float 0.000000e+00, float 1.000000e+00)
  %313 = call float @llvm.AMDIL.clamp.(float %310, float 0.000000e+00, float 1.000000e+00)
  %314 = call i32 @llvm.SI.packf16(float %311, float %312)
  %315 = bitcast i32 %314 to float
  %316 = call i32 @llvm.SI.packf16(float %313, float 1.000000e+00)
  %317 = bitcast i32 %316 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %315, float %317, float %315, float %317)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0300
c80d0301
c8080200
c8090201
c084030c
c0c60518
bf8c007f
f0800700
00430e02
c8240100
c8250101
c8200000
c8210001
c0840308
c0c60510
bf8c0070
f0800700
00430b08
d0020008
0201e10e
d2000002
00218280
d1040008
02010102
c8080900
c8090901
c8180800
c8190801
c80c0700
c80d0701
c8100600
c8110601
c8140500
c8150501
c81c0400
c81d0401
bf8c0770
be862408
8986067e
d2080000
020216f2
d2080001
02021cf2
100202f5
d2820001
03ca0101
be862506
89fe067e
d2060000
02021d0e
1002010b
88fe067e
d0020006
0201e10f
d2000000
00198280
d1040006
02010100
be862406
8986067e
d2080000
020218f2
d208000a
02021ef2
101414f5
d282000a
03ca010a
be862506
c0840100
bf8c007f
89fe067e
d2060000
02021f0f
1014010c
88fe067e
c2008941
c2000940
d0020006
0201e110
d2000000
00198280
d1040006
02010100
bf8c007f
be862406
8986067e
d2080000
02021af2
d2080011
020220f2
102222f5
d2820000
03ca0111
be862506
c0860304
c0c80508
c08c0300
c0ce0500
bf8c007f
89fe067e
d2060000
02022110
1000010d
88fe067e
7e1c5400
d206000f
0201e103
101c1d0f
d2060010
0201e102
0a202001
d2060011
22010001
7e225511
101e2310
f0800700
00c70e0e
bf8c0770
d0020006
0201e10e
d2000011
00198280
d1040006
02010111
d2100011
0201e10d
d2820000
0445e100
d2100011
0201e10c
d282000a
0445e10a
d210000b
0201e10b
d2820001
042de101
f0800700
00641108
bf8c0770
d2060009
0201e313
d206000b
0201e312
d206000c
0201e311
be862406
8986067e
d2080008
020202f2
d208000d
02021cf2
101a1af5
d2820008
03ca110d
be862506
89fe067e
d2060008
02021d0e
10101101
88fe067e
d0020006
0201e10f
d200000d
00198280
d1040006
0201010d
be8c2406
898c0c7e
d208000d
020214f2
d2080011
02021ef2
102222f5
d2820011
03ca1b11
be8c250c
89fe0c7e
d206000d
02021f0f
10221b0a
88fe0c7e
c2038959
c2030958
d002000c
0201e110
d200000d
00318280
d104000c
0201010d
bf8c007f
bea4240c
89a4247e
d208000d
020200f2
d2080012
020220f2
102424f5
d282000d
03ca1b12
bea42524
c0860314
c0c80528
c08c0310
c0ce0520
c201094a
c2018949
c2020948
bf8c007f
89fe247e
d206000d
02022110
101a1b00
88fe247e
d2080006
02020c03
d208000e
02020604
101c1d0e
d282000e
043a0d06
d208000f
02020402
d282000e
043a1f0f
061e1cff
c81c4000
101e1eff
3551b717
d00c0002
0201e10f
d200000f
0009e10f
d206080f
0201010f
7e1c5b0e
100c1d06
080c0cf2
100c0d0f
081c0cf2
d210000f
02020f07
d282000f
043e0b05
d282000f
043e0904
7e1e5b0f
100e1f07
d2100010
0202190c
d2820010
0442170b
d2820010
04421309
7e205b10
1018210c
100e0f0c
1016210b
100a1f05
d2060005
22010105
100a0b0b
080a0f05
10081f04
100e2109
10080907
08080905
d2820004
03c1e104
10080904
7e0a02ff
3e4ccccd
7e0e02ff
3f4ccccd
d2820004
04160f04
7e0a02ff
3f400000
100e0b0a
7e1202ff
3e800000
d2820007
041e1311
100e0f04
100e0eff
3f99999a
d2060807
02010107
100e0f0e
d2820007
041de106
d2060002
0201e102
101404ff
3b800000
7e1602ff
3ca3d70a
d2820010
042a1607
d2060003
0201e103
101406ff
3b800000
d282000f
042a1607
f0800100
00c70a0f
7e1602ff
3dcccccd
10181607
7e18410c
bf8c0770
0614190a
101414ff
40c90fdb
101414ff
3e22f983
7e146b0a
d282000a
03c2170a
7e165401
10181702
7e045400
10160503
f0800800
0064020b
bf8c0770
06041502
d2060802
02010102
d2080003
02000cf2
d2820002
040e0406
10060507
d2060803
02010103
10020b01
d2820001
04061308
10020304
100202ff
3f99999a
d2060801
02010101
1002030e
d2820001
0405e106
10020501
d2060801
02010101
5e020701
10000b00
d2820000
0402130d
10000104
100000ff
3f99999a
d2060800
02010100
1000010e
d2820000
0401e106
10000500
d2060800
02010100
d25e0000
0201e500
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL OUT[3], GENERIC[21]
DCL CONST[0..22]
DCL TEMP[0..8], LOCAL
IMM[0] FLT32 {    0.1592,     1.0000,    -1.0000,     0.5000}
IMM[1] FLT32 {    0.7500,     0.0000,     0.0000,     0.0000}
  0: MUL TEMP[0].x, IN[5].wwww, IMM[0].xxxx
  1: ADD TEMP[1].x, IN[4].xxxx, TEMP[0].xxxx
  2: FSGE TEMP[2].x, TEMP[1].xxxx, IMM[0].yyyy
  3: UIF TEMP[2].xxxx :0
  4:   ADD TEMP[2].x, TEMP[1].xxxx, IMM[0].zzzz
  5: ELSE :0
  6:   MOV TEMP[2].x, TEMP[1].xxxx
  7: ENDIF
  8: MOV TEMP[1].w, IMM[0].yyyy
  9: MAD TEMP[2].x, TEMP[2].xxxx, IMM[0].wwww, IMM[1].xxxx
 10: MUL TEMP[2].x, IN[0].yyyy, TEMP[2].xxxx
 11: SIN TEMP[3].x, IN[5].wwww
 12: COS TEMP[4].x, IN[5].wwww
 13: MUL TEMP[5].x, IN[0].zzzz, TEMP[3].xxxx
 14: MAD TEMP[5].x, IN[0].xxxx, TEMP[4].xxxx, -TEMP[5].xxxx
 15: MUL TEMP[6].x, IN[0].xxxx, TEMP[3].xxxx
 16: MAD TEMP[6].x, IN[0].zzzz, TEMP[4].xxxx, TEMP[6].xxxx
 17: MOV TEMP[5].y, TEMP[6].xxxx
 18: MOV TEMP[1].xz, TEMP[5].xxyx
 19: MUL TEMP[5].x, TEMP[5].xxxx, IN[6].xxxx
 20: MAD TEMP[5].x, TEMP[6].xxxx, IN[6].yyyy, TEMP[5].xxxx
 21: ADD TEMP[2].x, TEMP[2].xxxx, TEMP[5].xxxx
 22: MOV TEMP[1].y, TEMP[2].xxxx
 23: ADD TEMP[1].xyz, TEMP[1].xyzz, IN[5].xyzz
 24: MOV TEMP[2].xyz, TEMP[1].xyzx
 25: DP4 TEMP[5].x, TEMP[1], CONST[0]
 26: DP4 TEMP[6].x, TEMP[1], CONST[1]
 27: MOV TEMP[5].y, TEMP[6].xxxx
 28: DP4 TEMP[6].x, TEMP[1], CONST[2]
 29: MOV TEMP[5].z, TEMP[6].xxxx
 30: DP4 TEMP[1].x, TEMP[1], CONST[3]
 31: MOV TEMP[5].w, TEMP[1].xxxx
 32: MOV TEMP[1].xy, IN[3].xyxx
 33: MOV TEMP[6].y, IN[1].yyyy
 34: MUL TEMP[7].x, IN[1].zzzz, TEMP[3].xxxx
 35: MAD TEMP[7].x, IN[1].xxxx, TEMP[4].xxxx, -TEMP[7].xxxx
 36: MUL TEMP[8].x, IN[1].xxxx, TEMP[3].xxxx
 37: MAD TEMP[8].x, IN[1].zzzz, TEMP[4].xxxx, TEMP[8].xxxx
 38: MOV TEMP[7].y, TEMP[8].xxxx
 39: MOV TEMP[6].xz, TEMP[7].xxyx
 40: MOV TEMP[7].y, IN[2].yyyy
 41: MUL TEMP[8].x, IN[2].zzzz, TEMP[3].xxxx
 42: MAD TEMP[8].x, IN[2].xxxx, TEMP[4].xxxx, -TEMP[8].xxxx
 43: MUL TEMP[3].x, IN[2].xxxx, TEMP[3].xxxx
 44: MAD TEMP[3].x, IN[2].zzzz, TEMP[4].xxxx, TEMP[3].xxxx
 45: MOV TEMP[8].y, TEMP[3].xxxx
 46: MOV TEMP[7].xz, TEMP[8].xxyx
 47: MOV TEMP[3].y, IMM[1].yyyy
 48: MOV TEMP[3].x, TEMP[0].xxxx
 49: ADD TEMP[0].xy, TEMP[3].xyyy, IN[4].xyyy
 50: MOV TEMP[1].zw, TEMP[0].yyxy
 51: DP3 TEMP[0].x, CONST[17].xyzz, TEMP[7].xyzz
 52: MUL TEMP[3].xyz, TEMP[7].zxyy, TEMP[6].yzxx
 53: MAD TEMP[3].xyz, TEMP[7].yzxx, TEMP[6].zxyy, -TEMP[3].xyzz
 54: MUL TEMP[3].xyz, TEMP[3].xyzz, IN[2].wwww
 55: DP3 TEMP[3].x, CONST[17].xyzz, TEMP[3].xyzz
 56: MOV TEMP[0].y, TEMP[3].xxxx
 57: DP3 TEMP[3].x, CONST[17].xyzz, TEMP[6].xyzz
 58: MOV TEMP[0].z, TEMP[3].xxxx
 59: MOV TEMP[0].xyz, TEMP[0].xyzx
 60: MOV TEMP[0].w, TEMP[2].xxxx
 61: MOV TEMP[2].xy, TEMP[2].yzyy
 62: MOV OUT[1], TEMP[1]
 63: MOV OUT[2], TEMP[0]
 64: MOV OUT[3], TEMP[2]
 65: MOV OUT[0], TEMP[5]
 66: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 272)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 276)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 280)
  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %6)
  %34 = extractelement <4 x float> %33, i32 0
  %35 = extractelement <4 x float> %33, i32 1
  %36 = extractelement <4 x float> %33, i32 2
  %37 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
  %39 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %6)
  %40 = extractelement <4 x float> %39, i32 0
  %41 = extractelement <4 x float> %39, i32 1
  %42 = extractelement <4 x float> %39, i32 2
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %6)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %6)
  %53 = extractelement <4 x float> %52, i32 0
  %54 = extractelement <4 x float> %52, i32 1
  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %6)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
  %62 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %6)
  %63 = extractelement <4 x float> %62, i32 0
  %64 = extractelement <4 x float> %62, i32 1
  %65 = extractelement <4 x float> %62, i32 2
  %66 = extractelement <4 x float> %62, i32 3
  %67 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
  %69 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %6)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = fmul float %66, 0x3FC45F3060000000
  %73 = fadd float %58, %72
  %74 = fcmp oge float %73, 1.000000e+00
  %75 = sext i1 %74 to i32
  %76 = bitcast i32 %75 to float
  %77 = bitcast float %76 to i32
  %78 = icmp ne i32 %77, 0
  br i1 %78, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %79 = fadd float %73, -1.000000e+00
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp8.0 = phi float [ %79, %IF ], [ %73, %main_body ]
  %80 = fmul float %temp8.0, 5.000000e-01
  %81 = fadd float %80, 7.500000e-01
  %82 = fmul float %35, %81
  %83 = call float @llvm.sin.f32(float %66)
  %84 = call float @llvm.cos.f32(float %66)
  %85 = fmul float %36, %83
  %86 = fsub float -0.000000e+00, %85
  %87 = fmul float %34, %84
  %88 = fadd float %87, %86
  %89 = fmul float %34, %83
  %90 = fmul float %36, %84
  %91 = fadd float %90, %89
  %92 = fmul float %88, %70
  %93 = fmul float %91, %71
  %94 = fadd float %93, %92
  %95 = fadd float %82, %94
  %96 = fadd float %88, %63
  %97 = fadd float %95, %64
  %98 = fadd float %91, %65
  %99 = fmul float %96, %12
  %100 = fmul float %97, %13
  %101 = fadd float %99, %100
  %102 = fmul float %98, %14
  %103 = fadd float %101, %102
  %104 = fmul float 1.000000e+00, %15
  %105 = fadd float %103, %104
  %106 = fmul float %96, %16
  %107 = fmul float %97, %17
  %108 = fadd float %106, %107
  %109 = fmul float %98, %18
  %110 = fadd float %108, %109
  %111 = fmul float 1.000000e+00, %19
  %112 = fadd float %110, %111
  %113 = fmul float %96, %20
  %114 = fmul float %97, %21
  %115 = fadd float %113, %114
  %116 = fmul float %98, %22
  %117 = fadd float %115, %116
  %118 = fmul float 1.000000e+00, %23
  %119 = fadd float %117, %118
  %120 = fmul float %96, %24
  %121 = fmul float %97, %25
  %122 = fadd float %120, %121
  %123 = fmul float %98, %26
  %124 = fadd float %122, %123
  %125 = fmul float 1.000000e+00, %27
  %126 = fadd float %124, %125
  %127 = fmul float %42, %83
  %128 = fsub float -0.000000e+00, %127
  %129 = fmul float %40, %84
  %130 = fadd float %129, %128
  %131 = fmul float %40, %83
  %132 = fmul float %42, %84
  %133 = fadd float %132, %131
  %134 = fmul float %48, %83
  %135 = fsub float -0.000000e+00, %134
  %136 = fmul float %46, %84
  %137 = fadd float %136, %135
  %138 = fmul float %46, %83
  %139 = fmul float %48, %84
  %140 = fadd float %139, %138
  %141 = fadd float %72, %58
  %142 = fadd float 0.000000e+00, %59
  %143 = fmul float %28, %137
  %144 = fmul float %29, %47
  %145 = fadd float %144, %143
  %146 = fmul float %30, %140
  %147 = fadd float %145, %146
  %148 = fmul float %140, %41
  %149 = fmul float %137, %133
  %150 = fmul float %47, %130
  %151 = fsub float -0.000000e+00, %148
  %152 = fmul float %47, %133
  %153 = fadd float %152, %151
  %154 = fsub float -0.000000e+00, %149
  %155 = fmul float %140, %130
  %156 = fadd float %155, %154
  %157 = fsub float -0.000000e+00, %150
  %158 = fmul float %137, %41
  %159 = fadd float %158, %157
  %160 = fmul float %153, %49
  %161 = fmul float %156, %49
  %162 = fmul float %159, %49
  %163 = fmul float %28, %160
  %164 = fmul float %29, %161
  %165 = fadd float %164, %163
  %166 = fmul float %30, %162
  %167 = fadd float %165, %166
  %168 = fmul float %28, %130
  %169 = fmul float %29, %41
  %170 = fadd float %169, %168
  %171 = fmul float %30, %133
  %172 = fadd float %170, %171
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %53, float %54, float %141, float %142)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %147, float %167, float %172, float %96)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %97, float %98, float %98, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %105, float %112, float %119, float %126)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.cos.f32(float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840714
bf8c007f
e00c2000
80020100
c0840710
bf8c0070
e00c2000
80021600
7e0c02ff
3e22f983
bf8c0770
d2820005
045a0d04
d00c0014
0201e505
10340d04
c0840718
bf8c007f
e00c2000
80020600
c084070c
bf8c0070
e00c2000
80021b00
c0840708
bf8c0070
e00c2000
80020e00
c0840704
bf8c0070
e00c2000
80021200
c0820700
bf8c0070
e00c2000
80010a00
c08c0100
bf8c0070
c2081946
c2089945
c2091944
c200190f
c202190e
c204190d
c204990c
c200990b
c202990a
c2051909
c2059908
c2011907
c2031906
c2061905
c2069904
c2019903
c2039902
c2071901
c2079900
bf8c007f
be942414
8994147e
d2060005
0201e705
88fe147e
d2060000
02022d1a
d2060016
02010117
f800020f
16001c1b
bf8c070f
7e0002ff
3e22f983
10000104
7e2c6b00
102e2d12
7e006d00
d2820017
045e0114
10302d10
1032010e
08303119
10322f18
10342d0e
d282001a
046a0110
10362d14
10380112
0836371c
1038371a
0832331c
10323311
10383513
103a2f0f
0838391d
10383911
10383812
d2820019
04723211
1038370f
103a3113
0838391d
10383911
d2820019
04663810
10363612
d2820012
046e2611
d2820012
044a2e10
10263012
d282000e
044e1e11
d282000e
043a3410
101e2d0c
1020010a
081e1f10
06201f01
f800021f
1012190e
bf8c070f
101c2d0a
d2820000
043a010c
101c1f06
d2820006
043a0f00
7e0e02ff
3f400000
d2820005
041de105
d2820005
041a0b0b
060a0b02
06000103
7e020280
f800022f
01000005
bf8c070f
10020a08
d2820001
04041310
d2820001
04040900
06020200
10040a0a
d2820002
04081710
d2820002
04080b00
06040401
10060a0c
d2820003
040c1b10
d2820003
040c0d00
06060602
10080a0e
d2820004
04101f10
d2820000
04100f00
06000003
f80008cf
01020300
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL OUT[3], GENERIC[21]
DCL CONST[0..22]
DCL TEMP[0..8], LOCAL
IMM[0] FLT32 {    0.1592,     1.0000,    -1.0000,     0.5000}
IMM[1] FLT32 {    0.7500,     0.0000,     0.0000,     0.0000}
  0: MUL TEMP[0].x, IN[5].wwww, IMM[0].xxxx
  1: ADD TEMP[1].x, IN[4].xxxx, TEMP[0].xxxx
  2: FSGE TEMP[2].x, TEMP[1].xxxx, IMM[0].yyyy
  3: UIF TEMP[2].xxxx :0
  4:   ADD TEMP[2].x, TEMP[1].xxxx, IMM[0].zzzz
  5: ELSE :0
  6:   MOV TEMP[2].x, TEMP[1].xxxx
  7: ENDIF
  8: MOV TEMP[1].w, IMM[0].yyyy
  9: MAD TEMP[2].x, TEMP[2].xxxx, IMM[0].wwww, IMM[1].xxxx
 10: MUL TEMP[2].x, IN[0].yyyy, TEMP[2].xxxx
 11: SIN TEMP[3].x, IN[5].wwww
 12: COS TEMP[4].x, IN[5].wwww
 13: MUL TEMP[5].x, IN[0].zzzz, TEMP[3].xxxx
 14: MAD TEMP[5].x, IN[0].xxxx, TEMP[4].xxxx, -TEMP[5].xxxx
 15: MUL TEMP[6].x, IN[0].xxxx, TEMP[3].xxxx
 16: MAD TEMP[6].x, IN[0].zzzz, TEMP[4].xxxx, TEMP[6].xxxx
 17: MOV TEMP[5].y, TEMP[6].xxxx
 18: MOV TEMP[1].xz, TEMP[5].xxyx
 19: MUL TEMP[5].x, TEMP[5].xxxx, IN[6].xxxx
 20: MAD TEMP[5].x, TEMP[6].xxxx, IN[6].yyyy, TEMP[5].xxxx
 21: ADD TEMP[2].x, TEMP[2].xxxx, TEMP[5].xxxx
 22: MOV TEMP[1].y, TEMP[2].xxxx
 23: ADD TEMP[1].xyz, TEMP[1].xyzz, IN[5].xyzz
 24: MOV TEMP[2].xyz, TEMP[1].xyzx
 25: DP4 TEMP[5].x, TEMP[1], CONST[0]
 26: DP4 TEMP[6].x, TEMP[1], CONST[1]
 27: MOV TEMP[5].y, TEMP[6].xxxx
 28: DP4 TEMP[6].x, TEMP[1], CONST[2]
 29: MOV TEMP[5].z, TEMP[6].xxxx
 30: DP4 TEMP[1].x, TEMP[1], CONST[3]
 31: MOV TEMP[5].w, TEMP[1].xxxx
 32: MOV TEMP[1].xy, IN[3].xyxx
 33: MOV TEMP[6].y, IN[1].yyyy
 34: MUL TEMP[7].x, IN[1].zzzz, TEMP[3].xxxx
 35: MAD TEMP[7].x, IN[1].xxxx, TEMP[4].xxxx, -TEMP[7].xxxx
 36: MUL TEMP[8].x, IN[1].xxxx, TEMP[3].xxxx
 37: MAD TEMP[8].x, IN[1].zzzz, TEMP[4].xxxx, TEMP[8].xxxx
 38: MOV TEMP[7].y, TEMP[8].xxxx
 39: MOV TEMP[6].xz, TEMP[7].xxyx
 40: MOV TEMP[7].y, IN[2].yyyy
 41: MUL TEMP[8].x, IN[2].zzzz, TEMP[3].xxxx
 42: MAD TEMP[8].x, IN[2].xxxx, TEMP[4].xxxx, -TEMP[8].xxxx
 43: MUL TEMP[3].x, IN[2].xxxx, TEMP[3].xxxx
 44: MAD TEMP[3].x, IN[2].zzzz, TEMP[4].xxxx, TEMP[3].xxxx
 45: MOV TEMP[8].y, TEMP[3].xxxx
 46: MOV TEMP[7].xz, TEMP[8].xxyx
 47: MOV TEMP[3].y, IMM[1].yyyy
 48: MOV TEMP[3].x, TEMP[0].xxxx
 49: ADD TEMP[0].xy, TEMP[3].xyyy, IN[4].xyyy
 50: MOV TEMP[1].zw, TEMP[0].yyxy
 51: DP3 TEMP[0].x, CONST[17].xyzz, TEMP[7].xyzz
 52: MUL TEMP[3].xyz, TEMP[7].zxyy, TEMP[6].yzxx
 53: MAD TEMP[3].xyz, TEMP[7].yzxx, TEMP[6].zxyy, -TEMP[3].xyzz
 54: MUL TEMP[3].xyz, TEMP[3].xyzz, IN[2].wwww
 55: DP3 TEMP[3].x, CONST[17].xyzz, TEMP[3].xyzz
 56: MOV TEMP[0].y, TEMP[3].xxxx
 57: DP3 TEMP[3].x, CONST[17].xyzz, TEMP[6].xyzz
 58: MOV TEMP[0].z, TEMP[3].xxxx
 59: MOV TEMP[0].xyz, TEMP[0].xyzx
 60: MOV TEMP[0].w, TEMP[2].xxxx
 61: MOV TEMP[2].xy, TEMP[2].yzyy
 62: MOV OUT[1], TEMP[1]
 63: MOV OUT[2], TEMP[0]
 64: MOV OUT[3], TEMP[2]
 65: MOV OUT[0], TEMP[5]
 66: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 272)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 276)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 280)
  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %6)
  %34 = extractelement <4 x float> %33, i32 0
  %35 = extractelement <4 x float> %33, i32 1
  %36 = extractelement <4 x float> %33, i32 2
  %37 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
  %39 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %6)
  %40 = extractelement <4 x float> %39, i32 0
  %41 = extractelement <4 x float> %39, i32 1
  %42 = extractelement <4 x float> %39, i32 2
  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %6)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %6)
  %53 = extractelement <4 x float> %52, i32 0
  %54 = extractelement <4 x float> %52, i32 1
  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %6)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
  %62 = add i32 %9, %5
  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %62)
  %64 = extractelement <4 x float> %63, i32 0
  %65 = extractelement <4 x float> %63, i32 1
  %66 = extractelement <4 x float> %63, i32 2
  %67 = extractelement <4 x float> %63, i32 3
  %68 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
  %70 = add i32 %9, %5
  %71 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %69, i32 0, i32 %70)
  %72 = extractelement <4 x float> %71, i32 0
  %73 = extractelement <4 x float> %71, i32 1
  %74 = fmul float %67, 0x3FC45F3060000000
  %75 = fadd float %58, %74
  %76 = fcmp oge float %75, 1.000000e+00
  %77 = sext i1 %76 to i32
  %78 = bitcast i32 %77 to float
  %79 = bitcast float %78 to i32
  %80 = icmp ne i32 %79, 0
  br i1 %80, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %81 = fadd float %75, -1.000000e+00
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp8.0 = phi float [ %81, %IF ], [ %75, %main_body ]
  %82 = fmul float %temp8.0, 5.000000e-01
  %83 = fadd float %82, 7.500000e-01
  %84 = fmul float %35, %83
  %85 = call float @llvm.sin.f32(float %67)
  %86 = call float @llvm.cos.f32(float %67)
  %87 = fmul float %36, %85
  %88 = fsub float -0.000000e+00, %87
  %89 = fmul float %34, %86
  %90 = fadd float %89, %88
  %91 = fmul float %34, %85
  %92 = fmul float %36, %86
  %93 = fadd float %92, %91
  %94 = fmul float %90, %72
  %95 = fmul float %93, %73
  %96 = fadd float %95, %94
  %97 = fadd float %84, %96
  %98 = fadd float %90, %64
  %99 = fadd float %97, %65
  %100 = fadd float %93, %66
  %101 = fmul float %98, %12
  %102 = fmul float %99, %13
  %103 = fadd float %101, %102
  %104 = fmul float %100, %14
  %105 = fadd float %103, %104
  %106 = fmul float 1.000000e+00, %15
  %107 = fadd float %105, %106
  %108 = fmul float %98, %16
  %109 = fmul float %99, %17
  %110 = fadd float %108, %109
  %111 = fmul float %100, %18
  %112 = fadd float %110, %111
  %113 = fmul float 1.000000e+00, %19
  %114 = fadd float %112, %113
  %115 = fmul float %98, %20
  %116 = fmul float %99, %21
  %117 = fadd float %115, %116
  %118 = fmul float %100, %22
  %119 = fadd float %117, %118
  %120 = fmul float 1.000000e+00, %23
  %121 = fadd float %119, %120
  %122 = fmul float %98, %24
  %123 = fmul float %99, %25
  %124 = fadd float %122, %123
  %125 = fmul float %100, %26
  %126 = fadd float %124, %125
  %127 = fmul float 1.000000e+00, %27
  %128 = fadd float %126, %127
  %129 = fmul float %42, %85
  %130 = fsub float -0.000000e+00, %129
  %131 = fmul float %40, %86
  %132 = fadd float %131, %130
  %133 = fmul float %40, %85
  %134 = fmul float %42, %86
  %135 = fadd float %134, %133
  %136 = fmul float %48, %85
  %137 = fsub float -0.000000e+00, %136
  %138 = fmul float %46, %86
  %139 = fadd float %138, %137
  %140 = fmul float %46, %85
  %141 = fmul float %48, %86
  %142 = fadd float %141, %140
  %143 = fadd float %74, %58
  %144 = fadd float 0.000000e+00, %59
  %145 = fmul float %28, %139
  %146 = fmul float %29, %47
  %147 = fadd float %146, %145
  %148 = fmul float %30, %142
  %149 = fadd float %147, %148
  %150 = fmul float %142, %41
  %151 = fmul float %139, %135
  %152 = fmul float %47, %132
  %153 = fsub float -0.000000e+00, %150
  %154 = fmul float %47, %135
  %155 = fadd float %154, %153
  %156 = fsub float -0.000000e+00, %151
  %157 = fmul float %142, %132
  %158 = fadd float %157, %156
  %159 = fsub float -0.000000e+00, %152
  %160 = fmul float %139, %41
  %161 = fadd float %160, %159
  %162 = fmul float %155, %49
  %163 = fmul float %158, %49
  %164 = fmul float %161, %49
  %165 = fmul float %28, %162
  %166 = fmul float %29, %163
  %167 = fadd float %166, %165
  %168 = fmul float %30, %164
  %169 = fadd float %167, %168
  %170 = fmul float %28, %132
  %171 = fmul float %29, %41
  %172 = fadd float %171, %170
  %173 = fmul float %30, %135
  %174 = fadd float %172, %173
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %53, float %54, float %143, float %144)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %149, float %169, float %174, float %98)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %99, float %100, float %100, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %107, float %114, float %121, float %128)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.cos.f32(float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
4a0c060a
c0840714
bf8c007f
e00c2000
80020106
c0840710
bf8c0070
e00c2000
80021600
7e0e02ff
3e22f983
bf8c0770
d2820005
045a0f04
d00c0014
0201e505
10340f04
c0840718
bf8c007f
e00c2000
80020606
c084070c
bf8c0070
e00c2000
80021b00
c0840708
bf8c0070
e00c2000
80020e00
c0840704
bf8c0070
e00c2000
80021200
c0820700
bf8c0070
e00c2000
80010a00
c08c0100
bf8c0070
c2081946
c2089945
c2091944
c200190f
c202190e
c204190d
c204990c
c200990b
c202990a
c2051909
c2059908
c2011907
c2031906
c2061905
c2069904
c2019903
c2039902
c2071901
c2079900
bf8c007f
be942414
8994147e
d2060005
0201e705
88fe147e
d2060000
02022d1a
d2060016
02010117
f800020f
16001c1b
bf8c070f
7e0002ff
3e22f983
10000104
7e2c6b00
102e2d12
7e006d00
d2820017
045e0114
10302d10
1032010e
08303119
10322f18
10342d0e
d282001a
046a0110
10362d14
10380112
0836371c
1038371a
0832331c
10323311
10383513
103a2f0f
0838391d
10383911
10383812
d2820019
04723211
1038370f
103a3113
0838391d
10383911
d2820019
04663810
10363612
d2820012
046e2611
d2820012
044a2e10
10263012
d282000e
044e1e11
d282000e
043a3410
101e2d0c
1020010a
081e1f10
06201f01
f800021f
1012190e
bf8c070f
101c2d0a
d2820000
043a010c
101c1f06
d2820006
043a0f00
7e0e02ff
3f400000
d2820005
041de105
d2820005
041a0b0b
060a0b02
06000103
7e020280
f800022f
01000005
bf8c070f
10020a08
d2820001
04041310
d2820001
04040900
06020200
10040a0a
d2820002
04081710
d2820002
04080b00
06040401
10060a0c
d2820003
040c1b10
d2820003
040c0d00
06060602
10080a0e
d2820004
04101f10
d2820000
04100f00
06000003
f80008cf
01020300
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL SAMP[4]
DCL SAMP[5]
DCL SAMP[6]
DCL SAMP[7]
DCL SAMP[8]
DCL SAMP[9]
DCL CONST[0..25]
DCL CONST[36]
DCL TEMP[0..18], LOCAL
IMM[0] FLT32 {  -16.0000,     0.0000,    -0.5000,   255.0000}
IMM[1] FLT32 {  -98.0000,   100.0000,     0.5000,     0.2500}
IMM[2] FLT32 {    4.0000,   128.0000,   512.0000,     6.0000}
IMM[3] FLT32 {    2.0000,    11.0000,    -1.0000,     1.0000}
IMM[4] FLT32 {    8.0000,    10.0000,     0.0278,     0.1667}
IMM[5] UINT32 {0, 0, 0, 0}
IMM[6] INT32 {36, 6, 0, 0}
IMM[7] FLT32 {    0.1250,    -0.7000, 10000.0000,     3.0000}
IMM[8] FLT32 {    0.8000,     0.2000,     1.2000, -160000.0000}
IMM[9] FLT32 {    0.0000,     0.0200,     0.0039,     0.1000}
IMM[10] FLT32 {    6.2832,     0.0000,     0.0000,     0.0000}
  0: ADD TEMP[0].x, IMM[0].xxxx, IN[1].yyyy
  1: FSLT TEMP[0].x, TEMP[0].xxxx, IMM[0].yyyy
  2: UIF TEMP[0].xxxx :0
  3:   KILL
  4: ENDIF
  5: RCP TEMP[0].x, CONST[16].xxxx
  6: MUL TEMP[0].x, IMM[0].zzzz, TEMP[0].xxxx
  7: RCP TEMP[1].x, CONST[16].yyyy
  8: MUL TEMP[1].x, IMM[0].zzzz, TEMP[1].xxxx
  9: MOV TEMP[0].y, TEMP[1].xxxx
 10: ADD TEMP[0].xy, IN[0].xyyy, TEMP[0].xyyy
 11: MOV TEMP[0].xy, TEMP[0].xyyy
 12: TEX TEMP[0], TEMP[0], SAMP[7], 2D
 13: MUL TEMP[0], TEMP[0], IMM[0].wwww
 14: MOV TEMP[1].xyw, TEMP[0].xyxw
 15: ADD_SAT TEMP[2].x, TEMP[0].zzzz, IMM[1].xxxx
 16: MUL TEMP[3].x, TEMP[2].xxxx, IMM[1].yyyy
 17: ADD TEMP[0].x, TEMP[0].zzzz, -TEMP[3].xxxx
 18: MOV TEMP[1].z, TEMP[0].xxxx
 19: ADD TEMP[0], TEMP[1], IMM[1].zzzz
 20: MUL TEMP[0], TEMP[0], IMM[1].wwww
 21: FLR TEMP[0], TEMP[0]
 22: MUL TEMP[3], TEMP[0], IMM[2].xxxx
 23: ADD TEMP[1], TEMP[1], -TEMP[3]
 24: ADD TEMP[1], TEMP[1], IMM[1].zzzz
 25: FLR TEMP[1], TEMP[1]
 26: MUL TEMP[3].xy, IN[0].zwww, IMM[2].yyyy
 27: MOV TEMP[4].y, TEMP[3].yyyy
 28: RCP TEMP[5].x, CONST[16].yyyy
 29: MUL TEMP[5].x, CONST[16].xxxx, TEMP[5].xxxx
 30: MUL TEMP[4].x, TEMP[3].xxxx, TEMP[5].xxxx
 31: MUL TEMP[5].x, TEMP[4].xxxx, IMM[2].zzzz
 32: DDX TEMP[6].x, TEMP[5].xxxx
 33: ABS TEMP[6].x, TEMP[6].xxxx
 34: MUL TEMP[7], CONST[36].xxxx, TEMP[5].xxxx
 35: DDY TEMP[5].x, TEMP[7]
 36: ABS TEMP[5].x, TEMP[5].xxxx
 37: ADD TEMP[5].x, TEMP[6].xxxx, TEMP[5].xxxx
 38: MUL TEMP[3].x, TEMP[3].yyyy, IMM[2].zzzz
 39: DDX TEMP[6].x, TEMP[3].xxxx
 40: ABS TEMP[6].x, TEMP[6].xxxx
 41: MUL TEMP[7], CONST[36].xxxx, TEMP[3].xxxx
 42: DDY TEMP[3].x, TEMP[7]
 43: ABS TEMP[3].x, TEMP[3].xxxx
 44: ADD TEMP[3].x, TEMP[6].xxxx, TEMP[3].xxxx
 45: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx
 46: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[3].xxxx
 47: MAX TEMP[3].x, TEMP[5].xxxx, TEMP[3].xxxx
 48: LG2 TEMP[3].x, TEMP[3].xxxx
 49: MAD TEMP[3].x, IMM[1].zzzz, TEMP[3].xxxx, IMM[0].zzzz
 50: FLR TEMP[3].x, TEMP[3].xxxx
 51: MAX TEMP[3].x, TEMP[3].xxxx, IMM[0].yyyy
 52: MIN TEMP[3].x, TEMP[3].xxxx, IMM[2].wwww
 53: ADD TEMP[5].x, IMM[3].yyyy, -TEMP[3].xxxx
 54: POW TEMP[5].x, IMM[3].xxxx, TEMP[5].xxxx
 55: MUL TEMP[6].xy, IN[0].zwww, CONST[16].zwww
 56: MOV TEMP[6].xy, TEMP[6].xyyy
 57: TEX TEMP[6].xyz, TEMP[6], SAMP[2], 2D
 58: ADD TEMP[6].xyz, TEMP[6].xzyy, IMM[0].zzzz
 59: DP3 TEMP[7].x, TEMP[6].xyzz, TEMP[6].xyzz
 60: RSQ TEMP[7].x, TEMP[7].xxxx
 61: MUL TEMP[6].xyz, TEMP[6].xyzz, TEMP[7].xxxx
 62: MUL TEMP[7].x, TEMP[5].xxxx, IMM[1].wwww
 63: MOV TEMP[8].x, TEMP[1].wwww
 64: MOV TEMP[8].y, TEMP[0].wwww
 65: RCP TEMP[9].x, TEMP[5].xxxx
 66: FRC TEMP[10].xy, TEMP[4].xyyy
 67: ADD TEMP[11].x, TEMP[7].xxxx, IMM[3].zzzz
 68: RCP TEMP[12].x, TEMP[7].xxxx
 69: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[12].xxxx
 70: MAD TEMP[8].xy, TEMP[10].xyyy, TEMP[11].xxxx, TEMP[8].xyyy
 71: MUL TEMP[8].xy, TEMP[8].xyyy, IMM[1].wwww
 72: MAD TEMP[7].xy, IMM[1].zzzz, TEMP[9].xxxx, TEMP[8].xyyy
 73: MOV TEMP[7].xy, TEMP[7].xyyy
 74: MOV TEMP[7].w, TEMP[3].xxxx
 75: TXL TEMP[7], TEMP[7], SAMP[5], 2D
 76: MOV TEMP[8].xyz, TEMP[7]
 77: MUL TEMP[9].x, TEMP[5].xxxx, IMM[1].wwww
 78: MOV TEMP[10].x, TEMP[1].wwww
 79: MOV TEMP[10].y, TEMP[0].wwww
 80: RCP TEMP[11].x, TEMP[5].xxxx
 81: FRC TEMP[12].xy, TEMP[4].xyyy
 82: ADD TEMP[13].x, TEMP[9].xxxx, IMM[3].zzzz
 83: RCP TEMP[14].x, TEMP[9].xxxx
 84: MUL TEMP[13].x, TEMP[13].xxxx, TEMP[14].xxxx
 85: MAD TEMP[10].xy, TEMP[12].xyyy, TEMP[13].xxxx, TEMP[10].xyyy
 86: MUL TEMP[10].xy, TEMP[10].xyyy, IMM[1].wwww
 87: MAD TEMP[9].xy, IMM[1].zzzz, TEMP[11].xxxx, TEMP[10].xyyy
 88: MOV TEMP[9].xy, TEMP[9].xyyy
 89: MOV TEMP[9].w, TEMP[3].xxxx
 90: TXL TEMP[9].xyz, TEMP[9], SAMP[0], 2D
 91: ADD TEMP[9].xyz, TEMP[9].xzyy, IMM[0].zzzz
 92: FSLT TEMP[2].x, TEMP[2].xxxx, IMM[3].wwww
 93: UIF TEMP[2].xxxx :0
 94:   FSLT TEMP[2].x, CONST[25].zzzz, IMM[4].xxxx
 95: ELSE :0
 96:   MOV TEMP[2].x, IMM[5].xxxx
 97: ENDIF
 98: UIF TEMP[2].xxxx :0
 99:   MUL TEMP[2].x, TEMP[5].xxxx, IMM[1].wwww
100:   MOV TEMP[10].x, TEMP[1].xxxx
101:   MOV TEMP[10].y, TEMP[0].xxxx
102:   RCP TEMP[11].x, TEMP[5].xxxx
103:   FRC TEMP[12].xy, TEMP[4].xyyy
104:   ADD TEMP[13].x, TEMP[2].xxxx, IMM[3].zzzz
105:   RCP TEMP[14].x, TEMP[2].xxxx
106:   MUL TEMP[13].x, TEMP[13].xxxx, TEMP[14].xxxx
107:   MAD TEMP[10].xy, TEMP[12].xyyy, TEMP[13].xxxx, TEMP[10].xyyy
108:   MUL TEMP[10].xy, TEMP[10].xyyy, IMM[1].wwww
109:   MAD TEMP[2].xy, IMM[1].zzzz, TEMP[11].xxxx, TEMP[10].xyyy
110:   MOV TEMP[2].xy, TEMP[2].xyyy
111:   MOV TEMP[2].w, TEMP[3].xxxx
112:   TXL TEMP[2], TEMP[2], SAMP[5], 2D
113:   MUL TEMP[10].x, TEMP[5].xxxx, IMM[1].wwww
114:   MOV TEMP[11].x, TEMP[1].yyyy
115:   MOV TEMP[11].y, TEMP[0].yyyy
116:   RCP TEMP[12].x, TEMP[5].xxxx
117:   FRC TEMP[13].xy, TEMP[4].xyyy
118:   ADD TEMP[14].x, TEMP[10].xxxx, IMM[3].zzzz
119:   RCP TEMP[15].x, TEMP[10].xxxx
120:   MUL TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx
121:   MAD TEMP[11].xy, TEMP[13].xyyy, TEMP[14].xxxx, TEMP[11].xyyy
122:   MUL TEMP[11].xy, TEMP[11].xyyy, IMM[1].wwww
123:   MAD TEMP[10].xy, IMM[1].zzzz, TEMP[12].xxxx, TEMP[11].xyyy
124:   MOV TEMP[10].xy, TEMP[10].xyyy
125:   MOV TEMP[10].w, TEMP[3].xxxx
126:   TXL TEMP[10], TEMP[10], SAMP[5], 2D
127:   MUL TEMP[11].x, TEMP[5].xxxx, IMM[1].wwww
128:   MOV TEMP[12].x, TEMP[1].zzzz
129:   MOV TEMP[12].y, TEMP[0].zzzz
130:   RCP TEMP[13].x, TEMP[5].xxxx
131:   FRC TEMP[14].xy, TEMP[4].xyyy
132:   ADD TEMP[15].x, TEMP[11].xxxx, IMM[3].zzzz
133:   RCP TEMP[16].x, TEMP[11].xxxx
134:   MUL TEMP[15].x, TEMP[15].xxxx, TEMP[16].xxxx
135:   MAD TEMP[12].xy, TEMP[14].xyyy, TEMP[15].xxxx, TEMP[12].xyyy
136:   MUL TEMP[12].xy, TEMP[12].xyyy, IMM[1].wwww
137:   MAD TEMP[11].xy, IMM[1].zzzz, TEMP[13].xxxx, TEMP[12].xyyy
138:   MOV TEMP[11].xy, TEMP[11].xyyy
139:   MOV TEMP[11].w, TEMP[3].xxxx
140:   TXL TEMP[11], TEMP[11], SAMP[5], 2D
141:   MUL TEMP[12].x, TEMP[5].xxxx, IMM[1].wwww
142:   MOV TEMP[13].x, TEMP[1].xxxx
143:   MOV TEMP[13].y, TEMP[0].xxxx
144:   RCP TEMP[14].x, TEMP[5].xxxx
145:   FRC TEMP[15].xy, TEMP[4].xyyy
146:   ADD TEMP[16].x, TEMP[12].xxxx, IMM[3].zzzz
147:   RCP TEMP[17].x, TEMP[12].xxxx
148:   MUL TEMP[16].x, TEMP[16].xxxx, TEMP[17].xxxx
149:   MAD TEMP[13].xy, TEMP[15].xyyy, TEMP[16].xxxx, TEMP[13].xyyy
150:   MUL TEMP[13].xy, TEMP[13].xyyy, IMM[1].wwww
151:   MAD TEMP[12].xy, IMM[1].zzzz, TEMP[14].xxxx, TEMP[13].xyyy
152:   MUL TEMP[13].x, TEMP[5].xxxx, IMM[1].wwww
153:   MOV TEMP[14].x, TEMP[1].yyyy
154:   MOV TEMP[14].y, TEMP[0].yyyy
155:   RCP TEMP[15].x, TEMP[5].xxxx
156:   FRC TEMP[16].xy, TEMP[4].xyyy
157:   ADD TEMP[17].x, TEMP[13].xxxx, IMM[3].zzzz
158:   RCP TEMP[18].x, TEMP[13].xxxx
159:   MUL TEMP[17].x, TEMP[17].xxxx, TEMP[18].xxxx
160:   MAD TEMP[14].xy, TEMP[16].xyyy, TEMP[17].xxxx, TEMP[14].xyyy
161:   MUL TEMP[14].xy, TEMP[14].xyyy, IMM[1].wwww
162:   MAD TEMP[13].xy, IMM[1].zzzz, TEMP[15].xxxx, TEMP[14].xyyy
163:   MUL TEMP[14].x, TEMP[5].xxxx, IMM[1].wwww
164:   MOV TEMP[1].x, TEMP[1].zzzz
165:   MOV TEMP[1].y, TEMP[0].zzzz
166:   RCP TEMP[5].x, TEMP[5].xxxx
167:   FRC TEMP[4].xy, TEMP[4].xyyy
168:   ADD TEMP[15].x, TEMP[14].xxxx, IMM[3].zzzz
169:   RCP TEMP[14].x, TEMP[14].xxxx
170:   MUL TEMP[14].x, TEMP[15].xxxx, TEMP[14].xxxx
171:   MAD TEMP[4].xy, TEMP[4].xyyy, TEMP[14].xxxx, TEMP[1].xyyy
172:   MUL TEMP[4].xy, TEMP[4].xyyy, IMM[1].wwww
173:   MAD TEMP[1].xy, IMM[1].zzzz, TEMP[5].xxxx, TEMP[4].xyyy
174:   MAD TEMP[4].x, IN[0].xxxx, CONST[16].xxxx, IMM[0].zzzz
175:   MAD TEMP[5].x, IN[0].yyyy, CONST[16].yyyy, IMM[0].zzzz
176:   MOV TEMP[4].y, TEMP[5].xxxx
177:   FRC TEMP[4].xy, TEMP[4].xyyy
178:   MUL TEMP[5].x, TEMP[4].xxxx, TEMP[10].wwww
179:   MAD TEMP[5].x, TEMP[5].xxxx, IMM[4].yyyy, TEMP[4].xxxx
180:   ADD TEMP[14].x, IMM[3].wwww, -TEMP[4].xxxx
181:   MUL TEMP[14].x, TEMP[14].xxxx, TEMP[11].wwww
182:   ADD TEMP[15].x, IMM[3].wwww, -TEMP[4].xxxx
183:   MAD TEMP[14].x, TEMP[14].xxxx, IMM[4].yyyy, TEMP[15].xxxx
184:   MUL TEMP[15].x, TEMP[4].xxxx, TEMP[7].wwww
185:   MAD TEMP[15].x, TEMP[15].xxxx, IMM[4].yyyy, TEMP[4].xxxx
186:   ADD TEMP[16].x, IMM[3].wwww, -TEMP[4].xxxx
187:   MUL TEMP[16].x, TEMP[16].xxxx, TEMP[2].wwww
188:   ADD TEMP[17].x, IMM[3].wwww, -TEMP[4].xxxx
189:   MAD TEMP[16].x, TEMP[16].xxxx, IMM[4].yyyy, TEMP[17].xxxx
190:   ADD TEMP[17].x, TEMP[5].xxxx, TEMP[14].xxxx
191:   MUL TEMP[17].x, TEMP[17].xxxx, TEMP[4].yyyy
192:   ADD TEMP[18].x, TEMP[15].xxxx, TEMP[16].xxxx
193:   ADD TEMP[4].x, IMM[3].wwww, -TEMP[4].yyyy
194:   MUL TEMP[4].x, TEMP[18].xxxx, TEMP[4].xxxx
195:   ADD TEMP[14].x, TEMP[5].xxxx, TEMP[14].xxxx
196:   RCP TEMP[14].x, TEMP[14].xxxx
197:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[14].xxxx
198:   ADD TEMP[14].x, TEMP[15].xxxx, TEMP[16].xxxx
199:   RCP TEMP[14].x, TEMP[14].xxxx
200:   MUL TEMP[14].x, TEMP[15].xxxx, TEMP[14].xxxx
201:   ADD TEMP[4].x, TEMP[17].xxxx, TEMP[4].xxxx
202:   RCP TEMP[4].x, TEMP[4].xxxx
203:   MUL TEMP[4].x, TEMP[17].xxxx, TEMP[4].xxxx
204:   LRP TEMP[10], TEMP[5].xxxx, TEMP[10], TEMP[11]
205:   LRP TEMP[2], TEMP[14].xxxx, TEMP[7], TEMP[2]
206:   LRP TEMP[8].xyz, TEMP[4].xxxx, TEMP[2], TEMP[10]
207:   MOV TEMP[2].xy, TEMP[12].xyyy
208:   MOV TEMP[2].w, TEMP[3].xxxx
209:   TXL TEMP[2].xyz, TEMP[2], SAMP[0], 2D
210:   ADD TEMP[2].xyz, TEMP[2].xzyy, IMM[0].zzzz
211:   ADD TEMP[7].x, IMM[3].wwww, -TEMP[14].xxxx
212:   MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[7].xxxx
213:   MAD TEMP[2].xyz, TEMP[9].xyzz, TEMP[14].xxxx, TEMP[2].xyzz
214:   MOV TEMP[7].xy, TEMP[13].xyyy
215:   MOV TEMP[7].w, TEMP[3].xxxx
216:   TXL TEMP[7].xyz, TEMP[7], SAMP[0], 2D
217:   ADD TEMP[7].xyz, TEMP[7].xzyy, IMM[0].zzzz
218:   MOV TEMP[1].xy, TEMP[1].xyyy
219:   MOV TEMP[1].w, TEMP[3].xxxx
220:   TXL TEMP[1].xyz, TEMP[1], SAMP[0], 2D
221:   ADD TEMP[1].xyz, TEMP[1].xzyy, IMM[0].zzzz
222:   ADD TEMP[3].x, IMM[3].wwww, -TEMP[5].xxxx
223:   MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[3].xxxx
224:   MAD TEMP[1].xyz, TEMP[7].xyzz, TEMP[5].xxxx, TEMP[1].xyzz
225:   ADD TEMP[3].x, IMM[3].wwww, -TEMP[4].xxxx
226:   MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[3].xxxx
227:   MAD TEMP[9].xyz, TEMP[2].xyzz, TEMP[4].xxxx, TEMP[1].xyzz
228: ENDIF
229: DP3 TEMP[1].x, TEMP[9].xyzz, TEMP[9].xyzz
230: RSQ TEMP[1].x, TEMP[1].xxxx
231: MUL TEMP[1].xyz, TEMP[9].xyzz, TEMP[1].xxxx
232: MUL TEMP[2].xyz, TEMP[6].yxzz, TEMP[1].xxxx
233: MAD TEMP[2].xyz, TEMP[6].xyzz, TEMP[1].yyyy, TEMP[2].xyzz
234: MAD TEMP[0].xyz, TEMP[6].xzyy, TEMP[1].zzzz, TEMP[2].xyzz
235: MUL TEMP[1].xy, IN[0].zwww, CONST[16].zwww
236: MOV TEMP[1].xy, TEMP[1].xyyy
237: TEX TEMP[1].xyz, TEMP[1], SAMP[3], 2D
238: FSLT TEMP[2].x, TEMP[1].xxxx, IMM[1].zzzz
239: UIF TEMP[2].xxxx :0
240:   MUL TEMP[2].x, IMM[3].xxxx, TEMP[1].xxxx
241:   MUL TEMP[2].x, TEMP[2].xxxx, TEMP[8].xxxx
242: ELSE :0
243:   ADD TEMP[3].x, IMM[3].wwww, -TEMP[1].xxxx
244:   MUL TEMP[3].x, IMM[3].xxxx, TEMP[3].xxxx
245:   ADD TEMP[4].x, IMM[3].wwww, -TEMP[8].xxxx
246:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
247:   ADD TEMP[2].x, IMM[3].wwww, -TEMP[3].xxxx
248: ENDIF
249: MOV TEMP[2].x, TEMP[2].xxxx
250: FSLT TEMP[3].x, TEMP[1].yyyy, IMM[1].zzzz
251: UIF TEMP[3].xxxx :0
252:   MUL TEMP[3].x, IMM[3].xxxx, TEMP[1].yyyy
253:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[8].yyyy
254: ELSE :0
255:   ADD TEMP[4].x, IMM[3].wwww, -TEMP[1].yyyy
256:   MUL TEMP[4].x, IMM[3].xxxx, TEMP[4].xxxx
257:   ADD TEMP[5].x, IMM[3].wwww, -TEMP[8].yyyy
258:   MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
259:   ADD TEMP[3].x, IMM[3].wwww, -TEMP[4].xxxx
260: ENDIF
261: MOV TEMP[2].y, TEMP[3].xxxx
262: FSLT TEMP[3].x, TEMP[1].zzzz, IMM[1].zzzz
263: UIF TEMP[3].xxxx :0
264:   MUL TEMP[3].x, IMM[3].xxxx, TEMP[1].zzzz
265:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[8].zzzz
266: ELSE :0
267:   ADD TEMP[1].x, IMM[3].wwww, -TEMP[1].zzzz
268:   MUL TEMP[1].x, IMM[3].xxxx, TEMP[1].xxxx
269:   ADD TEMP[4].x, IMM[3].wwww, -TEMP[8].zzzz
270:   MUL TEMP[1].x, TEMP[1].xxxx, TEMP[4].xxxx
271:   ADD TEMP[3].x, IMM[3].wwww, -TEMP[1].xxxx
272: ENDIF
273: MOV TEMP[2].z, TEMP[3].xxxx
274: LRP TEMP[8].xyz, IMM[1].zzzz, TEMP[2].xyzz, TEMP[8].xyzz
275: MOV TEMP[1].xy, IN[0].xyyy
276: TEX TEMP[1].xyz, TEMP[1], SAMP[8], 2D
277: MOV TEMP[2].xy, IN[0].xyyy
278: TEX TEMP[2].w, TEMP[2], SAMP[1], 2D
279: MUL TEMP[1].xyz, TEMP[1].xyzz, IMM[0].wwww
280: MUL TEMP[3].xyz, TEMP[1].xyzz, IMM[4].zzzz
281: F2I TEMP[3].xyz, TEMP[3].xyzz
282: UMUL TEMP[4].xyz, TEMP[3].xyzz, IMM[6].xxxx
283: I2F TEMP[4].xyz, TEMP[4].xyzz
284: ADD TEMP[1].xyz, TEMP[1].xyzz, -TEMP[4].xyzz
285: MUL TEMP[4].xyz, TEMP[1].xyzz, IMM[4].wwww
286: F2I TEMP[4].xyz, TEMP[4].xyzz
287: UMUL TEMP[5].xyz, TEMP[4].xyzz, IMM[6].yyyy
288: I2F TEMP[5].xyz, TEMP[5].xyzz
289: ADD TEMP[1].xyz, TEMP[1].xyzz, -TEMP[5].xyzz
290: F2I TEMP[1].xyz, TEMP[1].xyzz
291: MUL TEMP[5].xy, IN[1].xzzz, IMM[7].xxxx
292: MOV TEMP[5].xy, TEMP[5].xyyy
293: TEX TEMP[5], TEMP[5], SAMP[4], 2D
294: I2F TEMP[6].x, TEMP[3].xxxx
295: I2F TEMP[7].x, TEMP[4].xxxx
296: MOV TEMP[6].y, TEMP[7].xxxx
297: I2F TEMP[7].x, TEMP[1].xxxx
298: MOV TEMP[6].z, TEMP[7].xxxx
299: I2F TEMP[7].x, TEMP[3].yyyy
300: I2F TEMP[9].x, TEMP[4].yyyy
301: MOV TEMP[7].y, TEMP[9].xxxx
302: I2F TEMP[9].x, TEMP[1].yyyy
303: MOV TEMP[7].z, TEMP[9].xxxx
304: I2F TEMP[3].x, TEMP[3].zzzz
305: I2F TEMP[4].x, TEMP[4].zzzz
306: MOV TEMP[3].y, TEMP[4].xxxx
307: I2F TEMP[1].x, TEMP[1].zzzz
308: MOV TEMP[3].z, TEMP[1].xxxx
309: MUL TEMP[1].x, IN[1].xxxx, IMM[1].zzzz
310: FRC TEMP[1].x, TEMP[1].xxxx
311: ADD_SAT TEMP[1].x, TEMP[1].xxxx, IMM[7].yyyy
312: MUL_SAT TEMP[1].x, TEMP[1].xxxx, IMM[7].zzzz
313: MUL TEMP[1].x, IMM[1].zzzz, TEMP[1].xxxx
314: ADD TEMP[1].x, TEMP[2].wwww, -TEMP[1].xxxx
315: MOV_SAT TEMP[1].x, TEMP[1].xxxx
316: MUL_SAT TEMP[1].x, TEMP[1].xxxx, IMM[7].wwww
317: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[5].wwww
318: MUL TEMP[2].xyz, TEMP[6].xyzz, TEMP[5].xxxx
319: MAD TEMP[2].xyz, TEMP[7].xyzz, TEMP[5].yyyy, TEMP[2].xyzz
320: MAD TEMP[2].xyz, TEMP[3].xyzz, TEMP[5].zzzz, TEMP[2].xyzz
321: MUL TEMP[2].xyz, TEMP[2].xyzz, IMM[4].wwww
322: ADD TEMP[3].x, IMM[3].wwww, -TEMP[1].xxxx
323: MUL TEMP[3].xyz, TEMP[8].xyzz, TEMP[3].xxxx
324: MAD TEMP[8].xyz, TEMP[2].xyzz, TEMP[1].xxxx, TEMP[3].xyzz
325: DP3 TEMP[0].x, TEMP[0].xyzz, -CONST[17].xyzz
326: MAD TEMP[0].x, TEMP[0].xxxx, IMM[1].zzzz, IMM[1].zzzz
327: ADD TEMP[1].xyz, CONST[18].xyzz, -IN[1].xyzz
328: ADD TEMP[2].x, IN[1].xxxx, IMM[1].zzzz
329: RCP TEMP[3].x, CONST[16].xxxx
330: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
331: ADD TEMP[3].x, IN[1].zzzz, IMM[1].zzzz
332: RCP TEMP[4].x, CONST[16].yyyy
333: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
334: MOV TEMP[2].y, TEMP[3].xxxx
335: MOV TEMP[3].w, IMM[3].wwww
336: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx
337: MAD TEMP[0].x, IMM[8].xxxx, TEMP[0].xxxx, IMM[8].yyyy
338: MUL TEMP[0].xyz, TEMP[0].xxxx, TEMP[8].xyzz
339: MUL_SAT TEMP[0].xyz, TEMP[0].xyzz, IMM[8].zzzz
340: DP3 TEMP[4].x, TEMP[1].xyzz, TEMP[1].xyzz
341: ADD TEMP[4].x, TEMP[4].xxxx, IMM[8].wwww
342: MUL TEMP[4].x, TEMP[4].xxxx, IMM[9].xxxx
343: MIN TEMP[4].x, TEMP[4].xxxx, IMM[1].zzzz
344: MOV_SAT TEMP[4].x, TEMP[4].xxxx
345: DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[1].xyzz
346: RSQ TEMP[5].x, TEMP[5].xxxx
347: MUL TEMP[1].y, TEMP[1].xyzz, TEMP[5].xxxx
348: ADD TEMP[1].x, IMM[3].wwww, -TEMP[1].yyyy
349: MUL TEMP[1].x, TEMP[4].xxxx, TEMP[1].xxxx
350: LRP TEMP[0].xyz, TEMP[1].xxxx, IMM[1].zzzz, TEMP[0].xyzz
351: MOV TEMP[1].xy, TEMP[2].xyyy
352: TEX TEMP[1].w, TEMP[1], SAMP[9], 2D
353: ADD TEMP[2].xy, IN[1].xzzz, IMM[1].zzzz
354: MUL TEMP[2].xy, TEMP[2].xyyy, IMM[9].zzzz
355: MAD TEMP[2].xy, CONST[22].yyyy, IMM[9].yyyy, TEMP[2].xyyy
356: MOV TEMP[2].xy, TEMP[2].xyyy
357: TEX TEMP[2].x, TEMP[2], SAMP[6], 2D
358: MUL TEMP[4].x, CONST[22].yyyy, IMM[9].wwww
359: FRC TEMP[4].x, TEMP[4].xxxx
360: ADD TEMP[2].x, TEMP[2].xxxx, TEMP[4].xxxx
361: MUL TEMP[2].x, TEMP[2].xxxx, IMM[10].xxxx
362: SIN TEMP[2].x, TEMP[2].xxxx
363: MAD TEMP[2].x, TEMP[2].xxxx, IMM[9].wwww, IMM[1].zzzz
364: ADD_SAT TEMP[1].x, TEMP[1].wwww, TEMP[2].xxxx
365: LRP TEMP[1].x, CONST[22].xxxx, TEMP[1].xxxx, IMM[3].wwww
366: MUL_SAT TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx
367: MOV TEMP[3].xyz, TEMP[0].xyzx
368: MOV OUT[0], TEMP[3]
369: END
; ModuleID = 'tgsi'

@ddxy_lds = external addrspace(3) global [64 x i32]

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 264)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 268)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 276)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 280)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 408)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 576)
  %36 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %37 = load <32 x i8> addrspace(2)* %36, !tbaa !0
  %38 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
  %40 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0
  %42 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
  %44 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %45 = load <32 x i8> addrspace(2)* %44, !tbaa !0
  %46 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0
  %48 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %49 = load <32 x i8> addrspace(2)* %48, !tbaa !0
  %50 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
  %53 = load <32 x i8> addrspace(2)* %52, !tbaa !0
  %54 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
  %56 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
  %57 = load <32 x i8> addrspace(2)* %56, !tbaa !0
  %58 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
  %59 = load <16 x i8> addrspace(2)* %58, !tbaa !0
  %60 = getelementptr <32 x i8> addrspace(2)* %2, i32 6
  %61 = load <32 x i8> addrspace(2)* %60, !tbaa !0
  %62 = getelementptr <16 x i8> addrspace(2)* %1, i32 6
  %63 = load <16 x i8> addrspace(2)* %62, !tbaa !0
  %64 = getelementptr <32 x i8> addrspace(2)* %2, i32 7
  %65 = load <32 x i8> addrspace(2)* %64, !tbaa !0
  %66 = getelementptr <16 x i8> addrspace(2)* %1, i32 7
  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
  %68 = getelementptr <32 x i8> addrspace(2)* %2, i32 8
  %69 = load <32 x i8> addrspace(2)* %68, !tbaa !0
  %70 = getelementptr <16 x i8> addrspace(2)* %1, i32 8
  %71 = load <16 x i8> addrspace(2)* %70, !tbaa !0
  %72 = getelementptr <32 x i8> addrspace(2)* %2, i32 9
  %73 = load <32 x i8> addrspace(2)* %72, !tbaa !0
  %74 = getelementptr <16 x i8> addrspace(2)* %1, i32 9
  %75 = load <16 x i8> addrspace(2)* %74, !tbaa !0
  %76 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %77 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %78 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %79 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %80 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %81 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %82 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %83 = fadd float -1.600000e+01, %81
  %84 = fcmp olt float %83, 0.000000e+00
  %85 = sext i1 %84 to i32
  %86 = bitcast i32 %85 to float
  %87 = bitcast float %86 to i32
  %88 = icmp ne i32 %87, 0
  br i1 %88, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  call void @llvm.AMDGPU.kilp()
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %89 = fdiv float 1.000000e+00, %22
  %90 = fmul float -5.000000e-01, %89
  %91 = fdiv float 1.000000e+00, %23
  %92 = fmul float -5.000000e-01, %91
  %93 = fadd float %76, %90
  %94 = fadd float %77, %92
  %95 = bitcast float %93 to i32
  %96 = bitcast float %94 to i32
  %97 = insertelement <2 x i32> undef, i32 %95, i32 0
  %98 = insertelement <2 x i32> %97, i32 %96, i32 1
  %99 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %98, <32 x i8> %65, <16 x i8> %67, i32 2)
  %100 = extractelement <4 x float> %99, i32 0
  %101 = extractelement <4 x float> %99, i32 1
  %102 = extractelement <4 x float> %99, i32 2
  %103 = extractelement <4 x float> %99, i32 3
  %104 = fmul float %100, 2.550000e+02
  %105 = fmul float %101, 2.550000e+02
  %106 = fmul float %102, 2.550000e+02
  %107 = fmul float %103, 2.550000e+02
  %108 = fadd float %106, -9.800000e+01
  %109 = call float @llvm.AMDIL.clamp.(float %108, float 0.000000e+00, float 1.000000e+00)
  %110 = fmul float %109, 1.000000e+02
  %111 = fsub float -0.000000e+00, %110
  %112 = fadd float %106, %111
  %113 = fadd float %104, 5.000000e-01
  %114 = fadd float %105, 5.000000e-01
  %115 = fadd float %112, 5.000000e-01
  %116 = fadd float %107, 5.000000e-01
  %117 = fmul float %113, 2.500000e-01
  %118 = fmul float %114, 2.500000e-01
  %119 = fmul float %115, 2.500000e-01
  %120 = fmul float %116, 2.500000e-01
  %121 = call float @floor(float %117)
  %122 = call float @floor(float %118)
  %123 = call float @floor(float %119)
  %124 = call float @floor(float %120)
  %125 = fmul float %121, 4.000000e+00
  %126 = fmul float %122, 4.000000e+00
  %127 = fmul float %123, 4.000000e+00
  %128 = fmul float %124, 4.000000e+00
  %129 = fsub float -0.000000e+00, %125
  %130 = fadd float %104, %129
  %131 = fsub float -0.000000e+00, %126
  %132 = fadd float %105, %131
  %133 = fsub float -0.000000e+00, %127
  %134 = fadd float %112, %133
  %135 = fsub float -0.000000e+00, %128
  %136 = fadd float %107, %135
  %137 = fadd float %130, 5.000000e-01
  %138 = fadd float %132, 5.000000e-01
  %139 = fadd float %134, 5.000000e-01
  %140 = fadd float %136, 5.000000e-01
  %141 = call float @floor(float %137)
  %142 = call float @floor(float %138)
  %143 = call float @floor(float %139)
  %144 = call float @floor(float %140)
  %145 = fmul float %78, 1.280000e+02
  %146 = fmul float %79, 1.280000e+02
  %147 = fdiv float 1.000000e+00, %23
  %148 = fmul float %22, %147
  %149 = fmul float %145, %148
  %150 = fmul float %149, 5.120000e+02
  %151 = call i32 @llvm.SI.tid()
  %152 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %151
  %153 = and i32 %151, -4
  %154 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %153
  %155 = add i32 %153, 1
  %156 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %155
  %157 = bitcast float %150 to i32
  store i32 %157, i32 addrspace(3)* %152
  %158 = load i32 addrspace(3)* %154
  %159 = bitcast i32 %158 to float
  %160 = load i32 addrspace(3)* %156
  %161 = bitcast i32 %160 to float
  %162 = fsub float %161, %159
  %163 = insertelement <4 x float> undef, float %162, i32 0
  %164 = insertelement <4 x float> %163, float %162, i32 1
  %165 = insertelement <4 x float> %164, float %162, i32 2
  %166 = insertelement <4 x float> %165, float %162, i32 3
  %167 = extractelement <4 x float> %166, i32 0
  %168 = call float @fabs(float %167)
  %169 = fmul float %35, %150
  %170 = fmul float %35, %150
  %171 = fmul float %35, %150
  %172 = fmul float %35, %150
  %173 = call i32 @llvm.SI.tid()
  %174 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %173
  %175 = and i32 %173, -4
  %176 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %175
  %177 = add i32 %175, 2
  %178 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %177
  %179 = bitcast float %169 to i32
  store i32 %179, i32 addrspace(3)* %174
  %180 = load i32 addrspace(3)* %176
  %181 = bitcast i32 %180 to float
  %182 = load i32 addrspace(3)* %178
  %183 = bitcast i32 %182 to float
  %184 = fsub float %183, %181
  %185 = bitcast float %170 to i32
  store i32 %185, i32 addrspace(3)* %174
  %186 = load i32 addrspace(3)* %176
  %187 = bitcast i32 %186 to float
  %188 = load i32 addrspace(3)* %178
  %189 = bitcast i32 %188 to float
  %190 = fsub float %189, %187
  %191 = bitcast float %171 to i32
  store i32 %191, i32 addrspace(3)* %174
  %192 = load i32 addrspace(3)* %176
  %193 = bitcast i32 %192 to float
  %194 = load i32 addrspace(3)* %178
  %195 = bitcast i32 %194 to float
  %196 = fsub float %195, %193
  %197 = bitcast float %172 to i32
  store i32 %197, i32 addrspace(3)* %174
  %198 = load i32 addrspace(3)* %176
  %199 = bitcast i32 %198 to float
  %200 = load i32 addrspace(3)* %178
  %201 = bitcast i32 %200 to float
  %202 = fsub float %201, %199
  %203 = insertelement <4 x float> undef, float %184, i32 0
  %204 = insertelement <4 x float> %203, float %190, i32 1
  %205 = insertelement <4 x float> %204, float %196, i32 2
  %206 = insertelement <4 x float> %205, float %202, i32 3
  %207 = extractelement <4 x float> %206, i32 0
  %208 = call float @fabs(float %207)
  %209 = fadd float %168, %208
  %210 = fmul float %146, 5.120000e+02
  %211 = call i32 @llvm.SI.tid()
  %212 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %211
  %213 = and i32 %211, -4
  %214 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %213
  %215 = add i32 %213, 1
  %216 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %215
  %217 = bitcast float %210 to i32
  store i32 %217, i32 addrspace(3)* %212
  %218 = load i32 addrspace(3)* %214
  %219 = bitcast i32 %218 to float
  %220 = load i32 addrspace(3)* %216
  %221 = bitcast i32 %220 to float
  %222 = fsub float %221, %219
  %223 = insertelement <4 x float> undef, float %222, i32 0
  %224 = insertelement <4 x float> %223, float %222, i32 1
  %225 = insertelement <4 x float> %224, float %222, i32 2
  %226 = insertelement <4 x float> %225, float %222, i32 3
  %227 = extractelement <4 x float> %226, i32 0
  %228 = call float @fabs(float %227)
  %229 = fmul float %35, %210
  %230 = fmul float %35, %210
  %231 = fmul float %35, %210
  %232 = fmul float %35, %210
  %233 = call i32 @llvm.SI.tid()
  %234 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %233
  %235 = and i32 %233, -4
  %236 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %235
  %237 = add i32 %235, 2
  %238 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %237
  %239 = bitcast float %229 to i32
  store i32 %239, i32 addrspace(3)* %234
  %240 = load i32 addrspace(3)* %236
  %241 = bitcast i32 %240 to float
  %242 = load i32 addrspace(3)* %238
  %243 = bitcast i32 %242 to float
  %244 = fsub float %243, %241
  %245 = bitcast float %230 to i32
  store i32 %245, i32 addrspace(3)* %234
  %246 = load i32 addrspace(3)* %236
  %247 = bitcast i32 %246 to float
  %248 = load i32 addrspace(3)* %238
  %249 = bitcast i32 %248 to float
  %250 = fsub float %249, %247
  %251 = bitcast float %231 to i32
  store i32 %251, i32 addrspace(3)* %234
  %252 = load i32 addrspace(3)* %236
  %253 = bitcast i32 %252 to float
  %254 = load i32 addrspace(3)* %238
  %255 = bitcast i32 %254 to float
  %256 = fsub float %255, %253
  %257 = bitcast float %232 to i32
  store i32 %257, i32 addrspace(3)* %234
  %258 = load i32 addrspace(3)* %236
  %259 = bitcast i32 %258 to float
  %260 = load i32 addrspace(3)* %238
  %261 = bitcast i32 %260 to float
  %262 = fsub float %261, %259
  %263 = insertelement <4 x float> undef, float %244, i32 0
  %264 = insertelement <4 x float> %263, float %250, i32 1
  %265 = insertelement <4 x float> %264, float %256, i32 2
  %266 = insertelement <4 x float> %265, float %262, i32 3
  %267 = extractelement <4 x float> %266, i32 0
  %268 = call float @fabs(float %267)
  %269 = fadd float %228, %268
  %270 = fmul float %209, %209
  %271 = fmul float %269, %269
  %272 = fcmp uge float %270, %271
  %273 = select i1 %272, float %270, float %271
  %274 = call float @llvm.log2.f32(float %273)
  %275 = fmul float 5.000000e-01, %274
  %276 = fadd float %275, -5.000000e-01
  %277 = call float @floor(float %276)
  %278 = fcmp uge float %277, 0.000000e+00
  %279 = select i1 %278, float %277, float 0.000000e+00
  %280 = fcmp uge float %279, 6.000000e+00
  %281 = select i1 %280, float 6.000000e+00, float %279
  %282 = fsub float -0.000000e+00, %281
  %283 = fadd float 1.100000e+01, %282
  %284 = call float @llvm.pow.f32(float 2.000000e+00, float %283)
  %285 = fmul float %78, %24
  %286 = fmul float %79, %25
  %287 = bitcast float %285 to i32
  %288 = bitcast float %286 to i32
  %289 = insertelement <2 x i32> undef, i32 %287, i32 0
  %290 = insertelement <2 x i32> %289, i32 %288, i32 1
  %291 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %290, <32 x i8> %45, <16 x i8> %47, i32 2)
  %292 = extractelement <4 x float> %291, i32 0
  %293 = extractelement <4 x float> %291, i32 1
  %294 = extractelement <4 x float> %291, i32 2
  %295 = fadd float %292, -5.000000e-01
  %296 = fadd float %294, -5.000000e-01
  %297 = fadd float %293, -5.000000e-01
  %298 = fmul float %295, %295
  %299 = fmul float %296, %296
  %300 = fadd float %299, %298
  %301 = fmul float %297, %297
  %302 = fadd float %300, %301
  %303 = call float @llvm.AMDGPU.rsq(float %302)
  %304 = fmul float %295, %303
  %305 = fmul float %296, %303
  %306 = fmul float %297, %303
  %307 = fmul float %284, 2.500000e-01
  %308 = fdiv float 1.000000e+00, %284
  %309 = call float @llvm.AMDIL.fraction.(float %149)
  %310 = call float @llvm.AMDIL.fraction.(float %146)
  %311 = fadd float %307, -1.000000e+00
  %312 = fdiv float 1.000000e+00, %307
  %313 = fmul float %311, %312
  %314 = fmul float %309, %313
  %315 = fadd float %314, %144
  %316 = fmul float %310, %313
  %317 = fadd float %316, %124
  %318 = fmul float %315, 2.500000e-01
  %319 = fmul float %317, 2.500000e-01
  %320 = fmul float 5.000000e-01, %308
  %321 = fadd float %320, %318
  %322 = fmul float 5.000000e-01, %308
  %323 = fadd float %322, %319
  %324 = bitcast float %321 to i32
  %325 = bitcast float %323 to i32
  %326 = bitcast float %281 to i32
  %327 = insertelement <4 x i32> undef, i32 %324, i32 0
  %328 = insertelement <4 x i32> %327, i32 %325, i32 1
  %329 = insertelement <4 x i32> %328, i32 %326, i32 2
  %330 = insertelement <4 x i32> %329, i32 undef, i32 3
  %331 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %330, <32 x i8> %57, <16 x i8> %59, i32 2)
  %332 = extractelement <4 x float> %331, i32 0
  %333 = extractelement <4 x float> %331, i32 1
  %334 = extractelement <4 x float> %331, i32 2
  %335 = extractelement <4 x float> %331, i32 3
  %336 = fmul float %284, 2.500000e-01
  %337 = fdiv float 1.000000e+00, %284
  %338 = call float @llvm.AMDIL.fraction.(float %149)
  %339 = call float @llvm.AMDIL.fraction.(float %146)
  %340 = fadd float %336, -1.000000e+00
  %341 = fdiv float 1.000000e+00, %336
  %342 = fmul float %340, %341
  %343 = fmul float %338, %342
  %344 = fadd float %343, %144
  %345 = fmul float %339, %342
  %346 = fadd float %345, %124
  %347 = fmul float %344, 2.500000e-01
  %348 = fmul float %346, 2.500000e-01
  %349 = fmul float 5.000000e-01, %337
  %350 = fadd float %349, %347
  %351 = fmul float 5.000000e-01, %337
  %352 = fadd float %351, %348
  %353 = bitcast float %350 to i32
  %354 = bitcast float %352 to i32
  %355 = bitcast float %281 to i32
  %356 = insertelement <4 x i32> undef, i32 %353, i32 0
  %357 = insertelement <4 x i32> %356, i32 %354, i32 1
  %358 = insertelement <4 x i32> %357, i32 %355, i32 2
  %359 = insertelement <4 x i32> %358, i32 undef, i32 3
  %360 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %359, <32 x i8> %37, <16 x i8> %39, i32 2)
  %361 = extractelement <4 x float> %360, i32 0
  %362 = extractelement <4 x float> %360, i32 1
  %363 = extractelement <4 x float> %360, i32 2
  %364 = fadd float %361, -5.000000e-01
  %365 = fadd float %363, -5.000000e-01
  %366 = fadd float %362, -5.000000e-01
  %367 = fcmp olt float %109, 1.000000e+00
  %368 = sext i1 %367 to i32
  %369 = bitcast i32 %368 to float
  %370 = bitcast float %369 to i32
  %371 = icmp ne i32 %370, 0
  br i1 %371, label %IF77, label %ENDIF76

IF77:                                             ; preds = %ENDIF
  %372 = fcmp olt float %34, 8.000000e+00
  %373 = sext i1 %372 to i32
  %374 = bitcast i32 %373 to float
  br label %ENDIF76

ENDIF76:                                          ; preds = %ENDIF, %IF77
  %temp8.0 = phi float [ %374, %IF77 ], [ 0.000000e+00, %ENDIF ]
  %375 = bitcast float %temp8.0 to i32
  %376 = icmp ne i32 %375, 0
  br i1 %376, label %IF80, label %ENDIF79

IF80:                                             ; preds = %ENDIF76
  %377 = fmul float %284, 2.500000e-01
  %378 = fdiv float 1.000000e+00, %284
  %379 = call float @llvm.AMDIL.fraction.(float %149)
  %380 = call float @llvm.AMDIL.fraction.(float %146)
  %381 = fadd float %377, -1.000000e+00
  %382 = fdiv float 1.000000e+00, %377
  %383 = fmul float %381, %382
  %384 = fmul float %379, %383
  %385 = fadd float %384, %141
  %386 = fmul float %380, %383
  %387 = fadd float %386, %121
  %388 = fmul float %385, 2.500000e-01
  %389 = fmul float %387, 2.500000e-01
  %390 = fmul float 5.000000e-01, %378
  %391 = fadd float %390, %388
  %392 = fmul float 5.000000e-01, %378
  %393 = fadd float %392, %389
  %394 = bitcast float %391 to i32
  %395 = bitcast float %393 to i32
  %396 = bitcast float %281 to i32
  %397 = insertelement <4 x i32> undef, i32 %394, i32 0
  %398 = insertelement <4 x i32> %397, i32 %395, i32 1
  %399 = insertelement <4 x i32> %398, i32 %396, i32 2
  %400 = insertelement <4 x i32> %399, i32 undef, i32 3
  %401 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %400, <32 x i8> %57, <16 x i8> %59, i32 2)
  %402 = extractelement <4 x float> %401, i32 0
  %403 = extractelement <4 x float> %401, i32 1
  %404 = extractelement <4 x float> %401, i32 2
  %405 = extractelement <4 x float> %401, i32 3
  %406 = fmul float %284, 2.500000e-01
  %407 = fdiv float 1.000000e+00, %284
  %408 = call float @llvm.AMDIL.fraction.(float %149)
  %409 = call float @llvm.AMDIL.fraction.(float %146)
  %410 = fadd float %406, -1.000000e+00
  %411 = fdiv float 1.000000e+00, %406
  %412 = fmul float %410, %411
  %413 = fmul float %408, %412
  %414 = fadd float %413, %142
  %415 = fmul float %409, %412
  %416 = fadd float %415, %122
  %417 = fmul float %414, 2.500000e-01
  %418 = fmul float %416, 2.500000e-01
  %419 = fmul float 5.000000e-01, %407
  %420 = fadd float %419, %417
  %421 = fmul float 5.000000e-01, %407
  %422 = fadd float %421, %418
  %423 = bitcast float %420 to i32
  %424 = bitcast float %422 to i32
  %425 = bitcast float %281 to i32
  %426 = insertelement <4 x i32> undef, i32 %423, i32 0
  %427 = insertelement <4 x i32> %426, i32 %424, i32 1
  %428 = insertelement <4 x i32> %427, i32 %425, i32 2
  %429 = insertelement <4 x i32> %428, i32 undef, i32 3
  %430 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %429, <32 x i8> %57, <16 x i8> %59, i32 2)
  %431 = extractelement <4 x float> %430, i32 0
  %432 = extractelement <4 x float> %430, i32 1
  %433 = extractelement <4 x float> %430, i32 2
  %434 = extractelement <4 x float> %430, i32 3
  %435 = fmul float %284, 2.500000e-01
  %436 = fdiv float 1.000000e+00, %284
  %437 = call float @llvm.AMDIL.fraction.(float %149)
  %438 = call float @llvm.AMDIL.fraction.(float %146)
  %439 = fadd float %435, -1.000000e+00
  %440 = fdiv float 1.000000e+00, %435
  %441 = fmul float %439, %440
  %442 = fmul float %437, %441
  %443 = fadd float %442, %143
  %444 = fmul float %438, %441
  %445 = fadd float %444, %123
  %446 = fmul float %443, 2.500000e-01
  %447 = fmul float %445, 2.500000e-01
  %448 = fmul float 5.000000e-01, %436
  %449 = fadd float %448, %446
  %450 = fmul float 5.000000e-01, %436
  %451 = fadd float %450, %447
  %452 = bitcast float %449 to i32
  %453 = bitcast float %451 to i32
  %454 = bitcast float %281 to i32
  %455 = insertelement <4 x i32> undef, i32 %452, i32 0
  %456 = insertelement <4 x i32> %455, i32 %453, i32 1
  %457 = insertelement <4 x i32> %456, i32 %454, i32 2
  %458 = insertelement <4 x i32> %457, i32 undef, i32 3
  %459 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %458, <32 x i8> %57, <16 x i8> %59, i32 2)
  %460 = extractelement <4 x float> %459, i32 0
  %461 = extractelement <4 x float> %459, i32 1
  %462 = extractelement <4 x float> %459, i32 2
  %463 = extractelement <4 x float> %459, i32 3
  %464 = fmul float %284, 2.500000e-01
  %465 = fdiv float 1.000000e+00, %284
  %466 = call float @llvm.AMDIL.fraction.(float %149)
  %467 = call float @llvm.AMDIL.fraction.(float %146)
  %468 = fadd float %464, -1.000000e+00
  %469 = fdiv float 1.000000e+00, %464
  %470 = fmul float %468, %469
  %471 = fmul float %466, %470
  %472 = fadd float %471, %141
  %473 = fmul float %467, %470
  %474 = fadd float %473, %121
  %475 = fmul float %472, 2.500000e-01
  %476 = fmul float %474, 2.500000e-01
  %477 = fmul float 5.000000e-01, %465
  %478 = fadd float %477, %475
  %479 = fmul float 5.000000e-01, %465
  %480 = fadd float %479, %476
  %481 = fmul float %284, 2.500000e-01
  %482 = fdiv float 1.000000e+00, %284
  %483 = call float @llvm.AMDIL.fraction.(float %149)
  %484 = call float @llvm.AMDIL.fraction.(float %146)
  %485 = fadd float %481, -1.000000e+00
  %486 = fdiv float 1.000000e+00, %481
  %487 = fmul float %485, %486
  %488 = fmul float %483, %487
  %489 = fadd float %488, %142
  %490 = fmul float %484, %487
  %491 = fadd float %490, %122
  %492 = fmul float %489, 2.500000e-01
  %493 = fmul float %491, 2.500000e-01
  %494 = fmul float 5.000000e-01, %482
  %495 = fadd float %494, %492
  %496 = fmul float 5.000000e-01, %482
  %497 = fadd float %496, %493
  %498 = fmul float %284, 2.500000e-01
  %499 = fdiv float 1.000000e+00, %284
  %500 = call float @llvm.AMDIL.fraction.(float %149)
  %501 = call float @llvm.AMDIL.fraction.(float %146)
  %502 = fadd float %498, -1.000000e+00
  %503 = fdiv float 1.000000e+00, %498
  %504 = fmul float %502, %503
  %505 = fmul float %500, %504
  %506 = fadd float %505, %143
  %507 = fmul float %501, %504
  %508 = fadd float %507, %123
  %509 = fmul float %506, 2.500000e-01
  %510 = fmul float %508, 2.500000e-01
  %511 = fmul float 5.000000e-01, %499
  %512 = fadd float %511, %509
  %513 = fmul float 5.000000e-01, %499
  %514 = fadd float %513, %510
  %515 = fmul float %76, %22
  %516 = fadd float %515, -5.000000e-01
  %517 = fmul float %77, %23
  %518 = fadd float %517, -5.000000e-01
  %519 = call float @llvm.AMDIL.fraction.(float %516)
  %520 = call float @llvm.AMDIL.fraction.(float %518)
  %521 = fmul float %519, %434
  %522 = fmul float %521, 1.000000e+01
  %523 = fadd float %522, %519
  %524 = fsub float -0.000000e+00, %519
  %525 = fadd float 1.000000e+00, %524
  %526 = fmul float %525, %463
  %527 = fsub float -0.000000e+00, %519
  %528 = fadd float 1.000000e+00, %527
  %529 = fmul float %526, 1.000000e+01
  %530 = fadd float %529, %528
  %531 = fmul float %519, %335
  %532 = fmul float %531, 1.000000e+01
  %533 = fadd float %532, %519
  %534 = fsub float -0.000000e+00, %519
  %535 = fadd float 1.000000e+00, %534
  %536 = fmul float %535, %405
  %537 = fsub float -0.000000e+00, %519
  %538 = fadd float 1.000000e+00, %537
  %539 = fmul float %536, 1.000000e+01
  %540 = fadd float %539, %538
  %541 = fadd float %523, %530
  %542 = fmul float %541, %520
  %543 = fadd float %533, %540
  %544 = fsub float -0.000000e+00, %520
  %545 = fadd float 1.000000e+00, %544
  %546 = fmul float %543, %545
  %547 = fadd float %523, %530
  %548 = fdiv float 1.000000e+00, %547
  %549 = fmul float %523, %548
  %550 = fadd float %533, %540
  %551 = fdiv float 1.000000e+00, %550
  %552 = fmul float %533, %551
  %553 = fadd float %542, %546
  %554 = fdiv float 1.000000e+00, %553
  %555 = fmul float %542, %554
  %556 = call float @llvm.AMDGPU.lrp(float %549, float %431, float %460)
  %557 = call float @llvm.AMDGPU.lrp(float %549, float %432, float %461)
  %558 = call float @llvm.AMDGPU.lrp(float %549, float %433, float %462)
  %559 = call float @llvm.AMDGPU.lrp(float %549, float %434, float %463)
  %560 = call float @llvm.AMDGPU.lrp(float %552, float %332, float %402)
  %561 = call float @llvm.AMDGPU.lrp(float %552, float %333, float %403)
  %562 = call float @llvm.AMDGPU.lrp(float %552, float %334, float %404)
  %563 = call float @llvm.AMDGPU.lrp(float %552, float %335, float %405)
  %564 = call float @llvm.AMDGPU.lrp(float %555, float %560, float %556)
  %565 = call float @llvm.AMDGPU.lrp(float %555, float %561, float %557)
  %566 = call float @llvm.AMDGPU.lrp(float %555, float %562, float %558)
  %567 = bitcast float %478 to i32
  %568 = bitcast float %480 to i32
  %569 = bitcast float %281 to i32
  %570 = insertelement <4 x i32> undef, i32 %567, i32 0
  %571 = insertelement <4 x i32> %570, i32 %568, i32 1
  %572 = insertelement <4 x i32> %571, i32 %569, i32 2
  %573 = insertelement <4 x i32> %572, i32 undef, i32 3
  %574 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %573, <32 x i8> %37, <16 x i8> %39, i32 2)
  %575 = extractelement <4 x float> %574, i32 0
  %576 = extractelement <4 x float> %574, i32 1
  %577 = extractelement <4 x float> %574, i32 2
  %578 = fadd float %575, -5.000000e-01
  %579 = fadd float %577, -5.000000e-01
  %580 = fadd float %576, -5.000000e-01
  %581 = fsub float -0.000000e+00, %552
  %582 = fadd float 1.000000e+00, %581
  %583 = fmul float %578, %582
  %584 = fmul float %579, %582
  %585 = fmul float %580, %582
  %586 = fmul float %364, %552
  %587 = fadd float %586, %583
  %588 = fmul float %365, %552
  %589 = fadd float %588, %584
  %590 = fmul float %366, %552
  %591 = fadd float %590, %585
  %592 = bitcast float %495 to i32
  %593 = bitcast float %497 to i32
  %594 = bitcast float %281 to i32
  %595 = insertelement <4 x i32> undef, i32 %592, i32 0
  %596 = insertelement <4 x i32> %595, i32 %593, i32 1
  %597 = insertelement <4 x i32> %596, i32 %594, i32 2
  %598 = insertelement <4 x i32> %597, i32 undef, i32 3
  %599 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %598, <32 x i8> %37, <16 x i8> %39, i32 2)
  %600 = extractelement <4 x float> %599, i32 0
  %601 = extractelement <4 x float> %599, i32 1
  %602 = extractelement <4 x float> %599, i32 2
  %603 = fadd float %600, -5.000000e-01
  %604 = fadd float %602, -5.000000e-01
  %605 = fadd float %601, -5.000000e-01
  %606 = bitcast float %512 to i32
  %607 = bitcast float %514 to i32
  %608 = bitcast float %281 to i32
  %609 = insertelement <4 x i32> undef, i32 %606, i32 0
  %610 = insertelement <4 x i32> %609, i32 %607, i32 1
  %611 = insertelement <4 x i32> %610, i32 %608, i32 2
  %612 = insertelement <4 x i32> %611, i32 undef, i32 3
  %613 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %612, <32 x i8> %37, <16 x i8> %39, i32 2)
  %614 = extractelement <4 x float> %613, i32 0
  %615 = extractelement <4 x float> %613, i32 1
  %616 = extractelement <4 x float> %613, i32 2
  %617 = fadd float %614, -5.000000e-01
  %618 = fadd float %616, -5.000000e-01
  %619 = fadd float %615, -5.000000e-01
  %620 = fsub float -0.000000e+00, %549
  %621 = fadd float 1.000000e+00, %620
  %622 = fmul float %617, %621
  %623 = fmul float %618, %621
  %624 = fmul float %619, %621
  %625 = fmul float %603, %549
  %626 = fadd float %625, %622
  %627 = fmul float %604, %549
  %628 = fadd float %627, %623
  %629 = fmul float %605, %549
  %630 = fadd float %629, %624
  %631 = fsub float -0.000000e+00, %555
  %632 = fadd float 1.000000e+00, %631
  %633 = fmul float %626, %632
  %634 = fmul float %628, %632
  %635 = fmul float %630, %632
  %636 = fmul float %587, %555
  %637 = fadd float %636, %633
  %638 = fmul float %589, %555
  %639 = fadd float %638, %634
  %640 = fmul float %591, %555
  %641 = fadd float %640, %635
  br label %ENDIF79

ENDIF79:                                          ; preds = %ENDIF76, %IF80
  %temp32.0 = phi float [ %564, %IF80 ], [ %332, %ENDIF76 ]
  %temp33.0 = phi float [ %565, %IF80 ], [ %333, %ENDIF76 ]
  %temp34.0 = phi float [ %566, %IF80 ], [ %334, %ENDIF76 ]
  %temp36.0 = phi float [ %637, %IF80 ], [ %364, %ENDIF76 ]
  %temp37.0 = phi float [ %639, %IF80 ], [ %365, %ENDIF76 ]
  %temp38.0 = phi float [ %641, %IF80 ], [ %366, %ENDIF76 ]
  %642 = fmul float %temp36.0, %temp36.0
  %643 = fmul float %temp37.0, %temp37.0
  %644 = fadd float %643, %642
  %645 = fmul float %temp38.0, %temp38.0
  %646 = fadd float %644, %645
  %647 = call float @llvm.AMDGPU.rsq(float %646)
  %648 = fmul float %temp36.0, %647
  %649 = fmul float %temp37.0, %647
  %650 = fmul float %temp38.0, %647
  %651 = fmul float %305, %648
  %652 = fmul float %304, %648
  %653 = fmul float %306, %648
  %654 = fmul float %304, %649
  %655 = fadd float %654, %651
  %656 = fmul float %305, %649
  %657 = fadd float %656, %652
  %658 = fmul float %306, %649
  %659 = fadd float %658, %653
  %660 = fmul float %304, %650
  %661 = fadd float %660, %655
  %662 = fmul float %306, %650
  %663 = fadd float %662, %657
  %664 = fmul float %305, %650
  %665 = fadd float %664, %659
  %666 = fmul float %78, %24
  %667 = fmul float %79, %25
  %668 = bitcast float %666 to i32
  %669 = bitcast float %667 to i32
  %670 = insertelement <2 x i32> undef, i32 %668, i32 0
  %671 = insertelement <2 x i32> %670, i32 %669, i32 1
  %672 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %671, <32 x i8> %49, <16 x i8> %51, i32 2)
  %673 = extractelement <4 x float> %672, i32 0
  %674 = extractelement <4 x float> %672, i32 1
  %675 = extractelement <4 x float> %672, i32 2
  %676 = fcmp olt float %673, 5.000000e-01
  %677 = sext i1 %676 to i32
  %678 = bitcast i32 %677 to float
  %679 = bitcast float %678 to i32
  %680 = icmp ne i32 %679, 0
  br i1 %680, label %IF83, label %ELSE84

IF83:                                             ; preds = %ENDIF79
  %681 = fmul float 2.000000e+00, %673
  %682 = fmul float %681, %temp32.0
  br label %ENDIF82

ELSE84:                                           ; preds = %ENDIF79
  %683 = fsub float -0.000000e+00, %673
  %684 = fadd float 1.000000e+00, %683
  %685 = fmul float 2.000000e+00, %684
  %686 = fsub float -0.000000e+00, %temp32.0
  %687 = fadd float 1.000000e+00, %686
  %688 = fmul float %685, %687
  %689 = fsub float -0.000000e+00, %688
  %690 = fadd float 1.000000e+00, %689
  br label %ENDIF82

ENDIF82:                                          ; preds = %ELSE84, %IF83
  %temp8.1 = phi float [ %682, %IF83 ], [ %690, %ELSE84 ]
  %691 = fcmp olt float %674, 5.000000e-01
  %692 = sext i1 %691 to i32
  %693 = bitcast i32 %692 to float
  %694 = bitcast float %693 to i32
  %695 = icmp ne i32 %694, 0
  br i1 %695, label %IF86, label %ELSE87

IF86:                                             ; preds = %ENDIF82
  %696 = fmul float 2.000000e+00, %674
  %697 = fmul float %696, %temp33.0
  br label %ENDIF85

ELSE87:                                           ; preds = %ENDIF82
  %698 = fsub float -0.000000e+00, %674
  %699 = fadd float 1.000000e+00, %698
  %700 = fmul float 2.000000e+00, %699
  %701 = fsub float -0.000000e+00, %temp33.0
  %702 = fadd float 1.000000e+00, %701
  %703 = fmul float %700, %702
  %704 = fsub float -0.000000e+00, %703
  %705 = fadd float 1.000000e+00, %704
  br label %ENDIF85

ENDIF85:                                          ; preds = %ELSE87, %IF86
  %temp12.0 = phi float [ %697, %IF86 ], [ %705, %ELSE87 ]
  %706 = fcmp olt float %675, 5.000000e-01
  %707 = sext i1 %706 to i32
  %708 = bitcast i32 %707 to float
  %709 = bitcast float %708 to i32
  %710 = icmp ne i32 %709, 0
  br i1 %710, label %IF89, label %ELSE90

IF89:                                             ; preds = %ENDIF85
  %711 = fmul float 2.000000e+00, %675
  %712 = fmul float %711, %temp34.0
  br label %ENDIF88

ELSE90:                                           ; preds = %ENDIF85
  %713 = fsub float -0.000000e+00, %675
  %714 = fadd float 1.000000e+00, %713
  %715 = fmul float 2.000000e+00, %714
  %716 = fsub float -0.000000e+00, %temp34.0
  %717 = fadd float 1.000000e+00, %716
  %718 = fmul float %715, %717
  %719 = fsub float -0.000000e+00, %718
  %720 = fadd float 1.000000e+00, %719
  br label %ENDIF88

ENDIF88:                                          ; preds = %ELSE90, %IF89
  %temp12.1 = phi float [ %712, %IF89 ], [ %720, %ELSE90 ]
  %721 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp8.1, float %temp32.0)
  %722 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp12.0, float %temp33.0)
  %723 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp12.1, float %temp34.0)
  %724 = bitcast float %76 to i32
  %725 = bitcast float %77 to i32
  %726 = insertelement <2 x i32> undef, i32 %724, i32 0
  %727 = insertelement <2 x i32> %726, i32 %725, i32 1
  %728 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %727, <32 x i8> %69, <16 x i8> %71, i32 2)
  %729 = extractelement <4 x float> %728, i32 0
  %730 = extractelement <4 x float> %728, i32 1
  %731 = extractelement <4 x float> %728, i32 2
  %732 = bitcast float %76 to i32
  %733 = bitcast float %77 to i32
  %734 = insertelement <2 x i32> undef, i32 %732, i32 0
  %735 = insertelement <2 x i32> %734, i32 %733, i32 1
  %736 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %735, <32 x i8> %41, <16 x i8> %43, i32 2)
  %737 = extractelement <4 x float> %736, i32 3
  %738 = fmul float %729, 2.550000e+02
  %739 = fmul float %730, 2.550000e+02
  %740 = fmul float %731, 2.550000e+02
  %741 = fmul float %738, 0x3F9C71C720000000
  %742 = fmul float %739, 0x3F9C71C720000000
  %743 = fmul float %740, 0x3F9C71C720000000
  %744 = fptosi float %741 to i32
  %745 = fptosi float %742 to i32
  %746 = fptosi float %743 to i32
  %747 = bitcast i32 %744 to float
  %748 = bitcast i32 %745 to float
  %749 = bitcast i32 %746 to float
  %750 = bitcast float %747 to i32
  %751 = mul i32 %750, 36
  %752 = bitcast float %748 to i32
  %753 = mul i32 %752, 36
  %754 = bitcast float %749 to i32
  %755 = mul i32 %754, 36
  %756 = bitcast i32 %751 to float
  %757 = bitcast i32 %753 to float
  %758 = bitcast i32 %755 to float
  %759 = bitcast float %756 to i32
  %760 = sitofp i32 %759 to float
  %761 = bitcast float %757 to i32
  %762 = sitofp i32 %761 to float
  %763 = bitcast float %758 to i32
  %764 = sitofp i32 %763 to float
  %765 = fsub float -0.000000e+00, %760
  %766 = fadd float %738, %765
  %767 = fsub float -0.000000e+00, %762
  %768 = fadd float %739, %767
  %769 = fsub float -0.000000e+00, %764
  %770 = fadd float %740, %769
  %771 = fmul float %766, 0x3FC5555560000000
  %772 = fmul float %768, 0x3FC5555560000000
  %773 = fmul float %770, 0x3FC5555560000000
  %774 = fptosi float %771 to i32
  %775 = fptosi float %772 to i32
  %776 = fptosi float %773 to i32
  %777 = bitcast i32 %774 to float
  %778 = bitcast i32 %775 to float
  %779 = bitcast i32 %776 to float
  %780 = bitcast float %777 to i32
  %781 = mul i32 %780, 6
  %782 = bitcast float %778 to i32
  %783 = mul i32 %782, 6
  %784 = bitcast float %779 to i32
  %785 = mul i32 %784, 6
  %786 = bitcast i32 %781 to float
  %787 = bitcast i32 %783 to float
  %788 = bitcast i32 %785 to float
  %789 = bitcast float %786 to i32
  %790 = sitofp i32 %789 to float
  %791 = bitcast float %787 to i32
  %792 = sitofp i32 %791 to float
  %793 = bitcast float %788 to i32
  %794 = sitofp i32 %793 to float
  %795 = fsub float -0.000000e+00, %790
  %796 = fadd float %766, %795
  %797 = fsub float -0.000000e+00, %792
  %798 = fadd float %768, %797
  %799 = fsub float -0.000000e+00, %794
  %800 = fadd float %770, %799
  %801 = fptosi float %796 to i32
  %802 = fptosi float %798 to i32
  %803 = fptosi float %800 to i32
  %804 = bitcast i32 %801 to float
  %805 = bitcast i32 %802 to float
  %806 = bitcast i32 %803 to float
  %807 = fmul float %80, 1.250000e-01
  %808 = fmul float %82, 1.250000e-01
  %809 = bitcast float %807 to i32
  %810 = bitcast float %808 to i32
  %811 = insertelement <2 x i32> undef, i32 %809, i32 0
  %812 = insertelement <2 x i32> %811, i32 %810, i32 1
  %813 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %812, <32 x i8> %53, <16 x i8> %55, i32 2)
  %814 = extractelement <4 x float> %813, i32 0
  %815 = extractelement <4 x float> %813, i32 1
  %816 = extractelement <4 x float> %813, i32 2
  %817 = extractelement <4 x float> %813, i32 3
  %818 = bitcast float %747 to i32
  %819 = sitofp i32 %818 to float
  %820 = bitcast float %777 to i32
  %821 = sitofp i32 %820 to float
  %822 = bitcast float %804 to i32
  %823 = sitofp i32 %822 to float
  %824 = bitcast float %748 to i32
  %825 = sitofp i32 %824 to float
  %826 = bitcast float %778 to i32
  %827 = sitofp i32 %826 to float
  %828 = bitcast float %805 to i32
  %829 = sitofp i32 %828 to float
  %830 = bitcast float %749 to i32
  %831 = sitofp i32 %830 to float
  %832 = bitcast float %779 to i32
  %833 = sitofp i32 %832 to float
  %834 = bitcast float %806 to i32
  %835 = sitofp i32 %834 to float
  %836 = fmul float %80, 5.000000e-01
  %837 = call float @llvm.AMDIL.fraction.(float %836)
  %838 = fadd float %837, 0xBFE6666660000000
  %839 = call float @llvm.AMDIL.clamp.(float %838, float 0.000000e+00, float 1.000000e+00)
  %840 = fmul float %839, 1.000000e+04
  %841 = call float @llvm.AMDIL.clamp.(float %840, float 0.000000e+00, float 1.000000e+00)
  %842 = fmul float 5.000000e-01, %841
  %843 = fsub float -0.000000e+00, %842
  %844 = fadd float %737, %843
  %845 = call float @llvm.AMDIL.clamp.(float %844, float 0.000000e+00, float 1.000000e+00)
  %846 = fmul float %845, 3.000000e+00
  %847 = call float @llvm.AMDIL.clamp.(float %846, float 0.000000e+00, float 1.000000e+00)
  %848 = fmul float %847, %817
  %849 = fmul float %819, %814
  %850 = fmul float %821, %814
  %851 = fmul float %823, %814
  %852 = fmul float %825, %815
  %853 = fadd float %852, %849
  %854 = fmul float %827, %815
  %855 = fadd float %854, %850
  %856 = fmul float %829, %815
  %857 = fadd float %856, %851
  %858 = fmul float %831, %816
  %859 = fadd float %858, %853
  %860 = fmul float %833, %816
  %861 = fadd float %860, %855
  %862 = fmul float %835, %816
  %863 = fadd float %862, %857
  %864 = fmul float %859, 0x3FC5555560000000
  %865 = fmul float %861, 0x3FC5555560000000
  %866 = fmul float %863, 0x3FC5555560000000
  %867 = fsub float -0.000000e+00, %848
  %868 = fadd float 1.000000e+00, %867
  %869 = fmul float %721, %868
  %870 = fmul float %722, %868
  %871 = fmul float %723, %868
  %872 = fmul float %864, %848
  %873 = fadd float %872, %869
  %874 = fmul float %865, %848
  %875 = fadd float %874, %870
  %876 = fmul float %866, %848
  %877 = fadd float %876, %871
  %878 = fsub float -0.000000e+00, %26
  %879 = fsub float -0.000000e+00, %27
  %880 = fsub float -0.000000e+00, %28
  %881 = fmul float %661, %878
  %882 = fmul float %663, %879
  %883 = fadd float %882, %881
  %884 = fmul float %665, %880
  %885 = fadd float %883, %884
  %886 = fmul float %885, 5.000000e-01
  %887 = fadd float %886, 5.000000e-01
  %888 = fsub float -0.000000e+00, %80
  %889 = fadd float %29, %888
  %890 = fsub float -0.000000e+00, %81
  %891 = fadd float %30, %890
  %892 = fsub float -0.000000e+00, %82
  %893 = fadd float %31, %892
  %894 = fadd float %80, 5.000000e-01
  %895 = fdiv float 1.000000e+00, %22
  %896 = fmul float %894, %895
  %897 = fadd float %82, 5.000000e-01
  %898 = fdiv float 1.000000e+00, %23
  %899 = fmul float %897, %898
  %900 = fmul float %887, %887
  %901 = fmul float 0x3FE99999A0000000, %900
  %902 = fadd float %901, 0x3FC99999A0000000
  %903 = fmul float %902, %873
  %904 = fmul float %902, %875
  %905 = fmul float %902, %877
  %906 = fmul float %903, 0x3FF3333340000000
  %907 = fmul float %904, 0x3FF3333340000000
  %908 = fmul float %905, 0x3FF3333340000000
  %909 = call float @llvm.AMDIL.clamp.(float %906, float 0.000000e+00, float 1.000000e+00)
  %910 = call float @llvm.AMDIL.clamp.(float %907, float 0.000000e+00, float 1.000000e+00)
  %911 = call float @llvm.AMDIL.clamp.(float %908, float 0.000000e+00, float 1.000000e+00)
  %912 = fmul float %889, %889
  %913 = fmul float %891, %891
  %914 = fadd float %913, %912
  %915 = fmul float %893, %893
  %916 = fadd float %914, %915
  %917 = fadd float %916, -1.600000e+05
  %918 = fmul float %917, 0x3EAA36E2E0000000
  %919 = fcmp uge float %918, 5.000000e-01
  %920 = select i1 %919, float 5.000000e-01, float %918
  %921 = call float @llvm.AMDIL.clamp.(float %920, float 0.000000e+00, float 1.000000e+00)
  %922 = fmul float %889, %889
  %923 = fmul float %891, %891
  %924 = fadd float %923, %922
  %925 = fmul float %893, %893
  %926 = fadd float %924, %925
  %927 = call float @llvm.AMDGPU.rsq(float %926)
  %928 = fmul float %891, %927
  %929 = fsub float -0.000000e+00, %928
  %930 = fadd float 1.000000e+00, %929
  %931 = fmul float %921, %930
  %932 = call float @llvm.AMDGPU.lrp(float %931, float 5.000000e-01, float %909)
  %933 = call float @llvm.AMDGPU.lrp(float %931, float 5.000000e-01, float %910)
  %934 = call float @llvm.AMDGPU.lrp(float %931, float 5.000000e-01, float %911)
  %935 = bitcast float %896 to i32
  %936 = bitcast float %899 to i32
  %937 = insertelement <2 x i32> undef, i32 %935, i32 0
  %938 = insertelement <2 x i32> %937, i32 %936, i32 1
  %939 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %938, <32 x i8> %73, <16 x i8> %75, i32 2)
  %940 = extractelement <4 x float> %939, i32 3
  %941 = fadd float %80, 5.000000e-01
  %942 = fadd float %82, 5.000000e-01
  %943 = fmul float %941, 3.906250e-03
  %944 = fmul float %942, 3.906250e-03
  %945 = fmul float %33, 0x3F947AE140000000
  %946 = fadd float %945, %943
  %947 = fmul float %33, 0x3F947AE140000000
  %948 = fadd float %947, %944
  %949 = bitcast float %946 to i32
  %950 = bitcast float %948 to i32
  %951 = insertelement <2 x i32> undef, i32 %949, i32 0
  %952 = insertelement <2 x i32> %951, i32 %950, i32 1
  %953 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %952, <32 x i8> %61, <16 x i8> %63, i32 2)
  %954 = extractelement <4 x float> %953, i32 0
  %955 = fmul float %33, 0x3FB99999A0000000
  %956 = call float @llvm.AMDIL.fraction.(float %955)
  %957 = fadd float %954, %956
  %958 = fmul float %957, 0x401921FB60000000
  %959 = call float @llvm.sin.f32(float %958)
  %960 = fmul float %959, 0x3FB99999A0000000
  %961 = fadd float %960, 5.000000e-01
  %962 = fadd float %940, %961
  %963 = call float @llvm.AMDIL.clamp.(float %962, float 0.000000e+00, float 1.000000e+00)
  %964 = call float @llvm.AMDGPU.lrp(float %32, float %963, float 1.000000e+00)
  %965 = fmul float %932, %964
  %966 = fmul float %933, %964
  %967 = fmul float %934, %964
  %968 = call float @llvm.AMDIL.clamp.(float %965, float 0.000000e+00, float 1.000000e+00)
  %969 = call float @llvm.AMDIL.clamp.(float %966, float 0.000000e+00, float 1.000000e+00)
  %970 = call float @llvm.AMDIL.clamp.(float %967, float 0.000000e+00, float 1.000000e+00)
  %971 = call i32 @llvm.SI.packf16(float %968, float %969)
  %972 = bitcast i32 %971 to float
  %973 = call i32 @llvm.SI.packf16(float %970, float 1.000000e+00)
  %974 = bitcast i32 %973 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %972, float %974, float %972, float %974)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

declare void @llvm.AMDGPU.kilp()

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readonly
declare float @floor(float) #3

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

; Function Attrs: readonly
declare float @fabs(float) #3

; Function Attrs: nounwind readonly
declare float @llvm.log2.f32(float) #4

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #4

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.samplel.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #4

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { readonly }
attributes #4 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
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083a431d
063a3af0
7e42491d
103a3922
d282001c
03c23922
103838ff
3e800000
7e38491c
104438f6
083a451d
063a3af0
7e3a491d
d0020000
0201e526
7e440280
be802400
8980007e
c2030966
7e4402ff
41000000
bf8c007f
d0020006
02024406
d2000022
00198280
88fe007e
c092030c
c0d40518
d10a0000
02010122
bf8c007f
be802400
8980007e
bf8800ae
7e4402ff
3e800000
d2820023
03ce451b
1044451b
7e445522
10444523
7e34411a
d282001f
047e451a
103e3eff
3e800000
7e36551b
d2820016
047de11b
7e324119
d282001e
047a4519
103c3cff
3e800000
d2820015
0479e11b
f0900f00
00c72315
d282001e
03c60104
7e3c411e
083e3cf2
bf8c0770
104e4d1f
7e5002ff
41200000
d2820027
047e5127
d2820020
0482451a
104040ff
3e800000
d282002a
0481e11b
d2820020
04864519
104040ff
3e800000
d2820029
0481e11b
7e560317
f0900f00
00c72d29
bf8c0770
1040611e
d2820020
047a5120
06424f20
7e4e5521
10404f20
084e40f2
f0900700
00643115
bf8c0770
d2060034
0201e332
10684f34
f0900700
00642929
bf8c0770
d206002c
0201e32a
d282002c
04d2412c
d2820034
03c60305
7e684134
106a6921
d282001a
0472451a
103434ff
3e800000
d2820016
0469e11b
d2820019
04764519
103232ff
3e800000
d2820015
0465e11b
f0900f00
00c71915
bf8c0770
103a391f
d282001d
047e511d
103e3d09
d282001e
047a511f
063a3b1e
083e68f2
103e3f1d
d282001f
047e6921
7e3e551f
103e3f35
08423ef2
1044432c
f0900700
00641515
bf8c0770
d2060018
0201e316
7e3a551d
103a3b1e
083c3af2
10303d18
d282000f
04623b0f
d282000f
048a3f0f
d2060018
0201e333
10304f18
d2060022
0201e32b
d2820018
04624122
10304318
d2060022
0201e317
10443d22
d2820010
048a3b10
d2820010
04623f10
d2060018
0201e331
10304f18
d2060022
0201e329
d2820018
04624122
10304318
d2060015
0201e315
102a3d15
d2820011
04563b11
d2820011
04623f11
102a4b27
d2820015
04565f20
102a2b21
102c371e
d2820016
045a111d
d2820008
04562d1f
102a4927
d2820015
04565d20
102a2b21
102c351e
d2820016
045a0f1d
d2820007
04562d1f
102a4727
d2820015
04565b20
102a2b21
102c331e
d2820016
045a0d1d
d2820006
04562d1f
88fe007e
d2100015
02022311
d2820015
04562110
d2820015
04561f0f
7e2a5b15
102c2b10
10222b11
10202314
d2820010
04422d14
102a2b0f
d282000f
04422b13
10202312
d2820010
04422d13
d2820010
04422b14
10222313
d2820011
04462d12
d2820011
04462b12
d2100013
02021d0b
d2100012
02021b0c
f0800700
012a1212
bf8c0770
d0020000
0201e112
d200000b
00018280
d1040000
0201010b
be802400
8980007e
d208000b
02020cf2
d208000c
020224f2
101818f5
d282000d
03ca170c
be802500
89fe007e
d206000b
02022512
101a1706
88fe007e
d0020000
0201e113
d200000b
00018280
d1040000
0201010b
be862400
8986067e
d208000b
02020ef2
d208000c
020226f2
101818f5
d282000b
03ca170c
be862506
89fe067e
d206000b
02022713
10161707
88fe067e
c2008959
c2000958
c2240946
c2248944
d0020006
0201e114
d200000c
00198280
d1040006
0201010c
bf8c007f
be862406
8986067e
d208000c
020210f2
d208000e
020228f2
101c1cf5
d282000c
03ca190e
be862506
c0860324
c0c80548
c0980320
c0da0540
c08c0318
c0ce0530
c09e0310
c0e00520
c0920304
c0d40508
c201894a
c2020949
c2028948
c2010945
7e1c0248
7e2a0249
bf8c007f
89fe067e
d206000c
02022914
10181908
88fe067e
d208000a
02021404
d2080012
02020605
10242512
d2820012
044a150a
d2080013
02020403
d2820012
044a2713
062624ff
c81c4000
102626ff
3551b717
d00c0004
0201e113
d2000013
0011e113
d2060813
02010113
7e245b12
1014250a
081414f2
10141513
082414f2
7e2602ff
3e000000
102e2702
102c2703
f0800f00
01f01616
f0800700
018d1a04
7e2602ff
437f0000
bf8c0770
1028271a
103a28ff
3ce38e39
7e3a111d
7e3c0b1d
103c2d1e
103e271b
10403eff
3ce38e39
7e401120
7e420b20
d282001e
047a2f21
1026271c
103426ff
3ce38e39
7e34111a
7e360b1a
d282001b
047a311b
103636ff
3e2aaaab
f0800800
012a0404
d2100005
0201e103
7e0a4105
060a0aff
bf333333
d2060805
02010105
100a0aff
461c4000
d2060805
02010105
100a0af0
bf8c0770
08080b04
d2060804
02010104
100808ff
40400000
d2060804
02010104
10083304
080a08f2
d210001c
0201e106
d282000d
0471e10d
101a0b0d
d282000d
0436091b
d2100011
02022b11
d2060015
22010002
10202b10
08202310
d210000e
02021d0f
081c1d10
d282000e
03c1e10e
101c1d0e
7e1e02ff
3e4ccccd
7e2002ff
3f4ccccd
d282000e
043e210e
101a1b0e
101a1aff
3f99999a
d206080d
0201010d
101a1b12
d282000d
0435e10a
d2060002
0201e102
101e04ff
3b800000
7e2002ff
3ca3d70a
d282001c
043e2001
d2060003
0201e103
101e06ff
3b800000
d282001b
043e2001
f0800100
00c70f1b
7e2002ff
3dcccccd
10222001
7e224111
bf8c0770
061e230f
101e1eff
40c90fdb
101e1eff
3e22f983
7e1e6b0f
d282000f
03c2210f
7e025501
10040302
7e005500
10020103
f0800800
00640001
bf8c0770
06001f00
d2060800
02010100
d2080001
020000f2
d2820000
04060000
1002010d
d2060801
02010101
d2d60002
0201491d
7e040b02
08040514
100604ff
3e2aaaab
7e061103
7e1a0b03
101a2d0d
d2d6000f
02014920
7e1e0b0f
081e1f1f
10201eff
3e2aaaab
7e201110
7e220b10
d282000d
04362f11
d2d60011
0201491a
7e220b11
08222313
102622ff
3e2aaaab
7e261113
7e280b13
d282000d
04363114
101a1aff
3e2aaaab
d2100014
0201e107
d282000b
0451e10b
10160b0b
d282000b
042e090d
1016170e
101616ff
3f99999a
d206080b
0201010b
10161712
d282000b
042de10a
1016010b
d206080b
0201010b
5e021701
d2d60003
02010d03
7e060b03
08040702
7e041102
7e040b02
10042d02
d2d60003
02010d10
7e060b03
0806070f
7e061103
7e060b03
d2820002
040a2f03
d2d60003
02010d13
7e060b03
08060711
7e061103
7e060b03
d2820002
040a3103
100404ff
3e2aaaab
d2100003
0201e108
d2820003
040de10c
10060b03
d2820002
040e0902
1004050e
100404ff
3f99999a
d2060802
02010102
10040512
d2820002
0409e10a
10000102
d2060800
02010100
d25e0000
0201e500
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..25]
DCL TEMP[0..5], LOCAL
IMM[0] FLT32 {   -1.0000,     1.0000,     0.5000,     0.0100}
IMM[1] INT32 {0, 1, 2, 3}
  0: MAD TEMP[0].xy, IN[0].xyyy, CONST[23].zzzz, CONST[23].xyyy
  1: ADD TEMP[1].x, IN[0].zzzz, IMM[0].xxxx
  2: F2I TEMP[1].x, TEMP[1].xxxx
  3: USEQ TEMP[1].yzw, TEMP[1].xxxx, IMM[1]
  4: I2F TEMP[2].y, TEMP[1].yyyy
  5: CMP TEMP[2].x, TEMP[2].yyyy, CONST[24].yyyy, CONST[24].xxxx
  6: I2F TEMP[3].z, TEMP[1].zzzz
  7: CMP TEMP[2].x, TEMP[3].zzzz, CONST[24].zzzz, TEMP[2].xxxx
  8: I2F TEMP[1].w, TEMP[1].wwww
  9: CMP TEMP[2].x, TEMP[1].wwww, CONST[24].wwww, TEMP[2].xxxx
 10: MOV_SAT TEMP[1].x, IN[0].zzzz
 11: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
 12: ADD TEMP[2].x, IMM[0].yyyy, -IN[0].wwww
 13: MOV TEMP[2].y, IN[0].wwww
 14: MUL TEMP[2].xy, TEMP[1].xxxx, TEMP[2].xyyy
 15: MAD TEMP[0].xy, TEMP[2].xyyy, CONST[23].zzzz, TEMP[0].xyyy
 16: ADD TEMP[2].x, TEMP[0].xxxx, IMM[0].zzzz
 17: RCP TEMP[3].x, CONST[16].xxxx
 18: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
 19: ADD TEMP[3].x, TEMP[0].yyyy, IMM[0].zzzz
 20: RCP TEMP[4].x, CONST[16].yyyy
 21: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 22: MOV TEMP[2].y, TEMP[3].xxxx
 23: ADD TEMP[3].x, TEMP[0].xxxx, IMM[0].zzzz
 24: RCP TEMP[4].x, CONST[16].xxxx
 25: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 26: ADD TEMP[4].x, TEMP[0].yyyy, IMM[0].zzzz
 27: ADD TEMP[4].x, TEMP[4].xxxx, -CONST[16].yyyy
 28: RCP TEMP[5].x, -CONST[16].yyyy
 29: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 30: MOV TEMP[3].y, TEMP[4].xxxx
 31: MOV TEMP[4].x, TEMP[0].xxxx
 32: ADD TEMP[5].x, IMM[0].yyyy, -TEMP[1].xxxx
 33: MUL TEMP[5].x, IN[1].xxxx, TEMP[5].xxxx
 34: MAD TEMP[1].x, IN[1].yyyy, TEMP[1].xxxx, TEMP[5].xxxx
 35: MUL TEMP[1].x, TEMP[1].xxxx, IMM[0].wwww
 36: MOV TEMP[4].y, TEMP[1].xxxx
 37: MOV TEMP[4].z, TEMP[0].yyyy
 38: MOV TEMP[5].w, IMM[0].yyyy
 39: MOV TEMP[5].x, TEMP[0].xxxx
 40: MOV TEMP[5].y, TEMP[1].xxxx
 41: MOV TEMP[5].z, TEMP[0].yyyy
 42: DP4 TEMP[0].x, TEMP[5], CONST[0]
 43: DP4 TEMP[1].x, TEMP[5], CONST[1]
 44: MOV TEMP[0].y, TEMP[1].xxxx
 45: DP4 TEMP[1].x, TEMP[5], CONST[2]
 46: MOV TEMP[0].z, TEMP[1].xxxx
 47: DP4 TEMP[1].x, TEMP[5], CONST[3]
 48: MOV TEMP[0].w, TEMP[1].xxxx
 49: MOV TEMP[1].xy, TEMP[2].xyxx
 50: MOV TEMP[1].zw, TEMP[3].yyxy
 51: MOV TEMP[2].xyz, TEMP[4].xyzx
 52: MOV OUT[2], TEMP[2]
 53: MOV OUT[0], TEMP[0]
 54: MOV OUT[1], TEMP[1]
 55: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 256)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 260)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 368)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 372)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 376)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 384)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 388)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 392)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 396)
  %37 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
  %39 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %6)
  %40 = extractelement <4 x float> %39, i32 0
  %41 = extractelement <4 x float> %39, i32 1
  %42 = extractelement <4 x float> %39, i32 2
  %43 = extractelement <4 x float> %39, i32 3
  %44 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %45 = load <16 x i8> addrspace(2)* %44, !tbaa !0
  %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %45, i32 0, i32 %6)
  %47 = extractelement <4 x float> %46, i32 0
  %48 = extractelement <4 x float> %46, i32 1
  %49 = fmul float %40, %32
  %50 = fadd float %49, %30
  %51 = fmul float %41, %32
  %52 = fadd float %51, %31
  %53 = fadd float %42, -1.000000e+00
  %54 = fptosi float %53 to i32
  %55 = bitcast i32 %54 to float
  %56 = bitcast float %55 to i32
  %57 = icmp eq i32 %56, 1
  %58 = sext i1 %57 to i32
  %59 = bitcast float %55 to i32
  %60 = icmp eq i32 %59, 2
  %61 = sext i1 %60 to i32
  %62 = bitcast float %55 to i32
  %63 = icmp eq i32 %62, 3
  %64 = sext i1 %63 to i32
  %65 = bitcast i32 %58 to float
  %66 = bitcast i32 %61 to float
  %67 = bitcast i32 %64 to float
  %68 = bitcast float %65 to i32
  %69 = sitofp i32 %68 to float
  %70 = call float @llvm.AMDGPU.cndlt(float %69, float %34, float %33)
  %71 = bitcast float %66 to i32
  %72 = sitofp i32 %71 to float
  %73 = call float @llvm.AMDGPU.cndlt(float %72, float %35, float %70)
  %74 = bitcast float %67 to i32
  %75 = sitofp i32 %74 to float
  %76 = call float @llvm.AMDGPU.cndlt(float %75, float %36, float %73)
  %77 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
  %78 = fmul float %77, %76
  %79 = fsub float -0.000000e+00, %43
  %80 = fadd float 1.000000e+00, %79
  %81 = fmul float %78, %80
  %82 = fmul float %78, %43
  %83 = fmul float %81, %32
  %84 = fadd float %83, %50
  %85 = fmul float %82, %32
  %86 = fadd float %85, %52
  %87 = fadd float %84, 5.000000e-01
  %88 = fdiv float 1.000000e+00, %28
  %89 = fmul float %87, %88
  %90 = fadd float %86, 5.000000e-01
  %91 = fdiv float 1.000000e+00, %29
  %92 = fmul float %90, %91
  %93 = fadd float %84, 5.000000e-01
  %94 = fdiv float 1.000000e+00, %28
  %95 = fmul float %93, %94
  %96 = fadd float %86, 5.000000e-01
  %97 = fsub float -0.000000e+00, %29
  %98 = fadd float %96, %97
  %99 = fsub float -0.000000e+00, %29
  %100 = fdiv float 1.000000e+00, %99
  %101 = fmul float %98, %100
  %102 = fsub float -0.000000e+00, %78
  %103 = fadd float 1.000000e+00, %102
  %104 = fmul float %47, %103
  %105 = fmul float %48, %78
  %106 = fadd float %105, %104
  %107 = fmul float %106, 0x3F847AE140000000
  %108 = fmul float %84, %12
  %109 = fmul float %107, %13
  %110 = fadd float %108, %109
  %111 = fmul float %86, %14
  %112 = fadd float %110, %111
  %113 = fmul float 1.000000e+00, %15
  %114 = fadd float %112, %113
  %115 = fmul float %84, %16
  %116 = fmul float %107, %17
  %117 = fadd float %115, %116
  %118 = fmul float %86, %18
  %119 = fadd float %117, %118
  %120 = fmul float 1.000000e+00, %19
  %121 = fadd float %119, %120
  %122 = fmul float %84, %20
  %123 = fmul float %107, %21
  %124 = fadd float %122, %123
  %125 = fmul float %86, %22
  %126 = fadd float %124, %125
  %127 = fmul float 1.000000e+00, %23
  %128 = fadd float %126, %127
  %129 = fmul float %84, %24
  %130 = fmul float %107, %25
  %131 = fadd float %129, %130
  %132 = fmul float %86, %26
  %133 = fadd float %131, %132
  %134 = fmul float 1.000000e+00, %27
  %135 = fadd float %133, %134
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %89, float %92, float %95, float %101)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %84, float %107, float %86, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %114, float %121, float %128, float %135)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.cndlt(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840700
bf8c007f
e00c2000
80020100
bf8c0770
d2060005
0201e703
7e0a1105
d1040002
02010305
d2000006
00098280
7e0c0b06
d0080002
02020c80
c0840100
bf8c007f
c2000961
bf8c007f
7e0c0200
c2000960
bf8c007f
7e0e0200
d2000006
000a0d07
d1040000
02010505
d2000007
00018280
7e0e0b07
d0080000
02020e80
c2010962
bf8c007f
7e0e0202
d2000006
00020f06
d1040000
02010705
d2000005
00018280
7e0a0b05
d0080000
02020a80
c2010963
bf8c007f
7e0a0202
d2000005
00020b06
d2060806
02010103
100a0b06
100c0905
c200095d
bf8c007f
7e0e0200
c200095e
bf8c007f
7e100200
d2820007
041e1102
d2820006
041c0106
060e0cf0
c2008941
bf8c007f
7e125401
10121307
081408f2
10141505
c201095c
bf8c007f
7e160202
d2820001
042e1101
d2820001
0404010a
060402f0
c2000940
bf8c007f
7e065400
10040702
0a060e01
d2060004
22010001
7e085504
10060903
f800020f
03020902
bf8c070f
08040af2
c0800704
bf8c007f
e00c2000
80000700
bf8c0770
10000507
d2820000
04020b08
100000ff
3c23d70a
7e040280
f800021f
02060001
c200090d
bf8c000f
10040000
c200090c
bf8c007f
d2820002
04080101
c200090e
bf8c007f
d2820002
04080106
c200090f
bf8c007f
06040400
c2000909
bf8c007f
10060000
c2000908
bf8c007f
d2820003
040c0101
c200090a
bf8c007f
d2820003
040c0106
c200090b
bf8c007f
06060600
c2000905
bf8c007f
10080000
c2000904
bf8c007f
d2820004
04100101
c2000906
bf8c007f
d2820004
04100106
c2000907
bf8c007f
06080800
c2000901
bf8c007f
10000000
c2000900
bf8c007f
d2820000
04000101
c2000902
bf8c007f
d2820000
04000106
c2000903
bf8c007f
06000000
f80008cf
02030400
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..25]
DCL TEMP[0..5], LOCAL
IMM[0] FLT32 {   -1.0000,     1.0000,     0.5000,     0.0100}
IMM[1] INT32 {0, 1, 2, 3}
  0: MAD TEMP[0].xy, IN[0].xyyy, CONST[23].zzzz, CONST[23].xyyy
  1: ADD TEMP[1].x, IN[0].zzzz, IMM[0].xxxx
  2: F2I TEMP[1].x, TEMP[1].xxxx
  3: USEQ TEMP[1].yzw, TEMP[1].xxxx, IMM[1]
  4: I2F TEMP[2].y, TEMP[1].yyyy
  5: CMP TEMP[2].x, TEMP[2].yyyy, CONST[24].yyyy, CONST[24].xxxx
  6: I2F TEMP[3].z, TEMP[1].zzzz
  7: CMP TEMP[2].x, TEMP[3].zzzz, CONST[24].zzzz, TEMP[2].xxxx
  8: I2F TEMP[1].w, TEMP[1].wwww
  9: CMP TEMP[2].x, TEMP[1].wwww, CONST[24].wwww, TEMP[2].xxxx
 10: MOV_SAT TEMP[1].x, IN[0].zzzz
 11: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
 12: ADD TEMP[2].x, IMM[0].yyyy, -IN[0].wwww
 13: MOV TEMP[2].y, IN[0].wwww
 14: MUL TEMP[2].xy, TEMP[1].xxxx, TEMP[2].xyyy
 15: MAD TEMP[0].xy, TEMP[2].xyyy, CONST[23].zzzz, TEMP[0].xyyy
 16: ADD TEMP[2].x, TEMP[0].xxxx, IMM[0].zzzz
 17: RCP TEMP[3].x, CONST[16].xxxx
 18: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
 19: ADD TEMP[3].x, TEMP[0].yyyy, IMM[0].zzzz
 20: RCP TEMP[4].x, CONST[16].yyyy
 21: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 22: MOV TEMP[2].y, TEMP[3].xxxx
 23: ADD TEMP[3].x, TEMP[0].xxxx, IMM[0].zzzz
 24: RCP TEMP[4].x, CONST[16].xxxx
 25: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 26: ADD TEMP[4].x, TEMP[0].yyyy, IMM[0].zzzz
 27: ADD TEMP[4].x, TEMP[4].xxxx, -CONST[16].yyyy
 28: RCP TEMP[5].x, -CONST[16].yyyy
 29: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 30: MOV TEMP[3].y, TEMP[4].xxxx
 31: MOV TEMP[4].x, TEMP[0].xxxx
 32: ADD TEMP[5].x, IMM[0].yyyy, -TEMP[1].xxxx
 33: MUL TEMP[5].x, IN[1].xxxx, TEMP[5].xxxx
 34: MAD TEMP[1].x, IN[1].yyyy, TEMP[1].xxxx, TEMP[5].xxxx
 35: MUL TEMP[1].x, TEMP[1].xxxx, IMM[0].wwww
 36: MOV TEMP[4].y, TEMP[1].xxxx
 37: MOV TEMP[4].z, TEMP[0].yyyy
 38: MOV TEMP[5].w, IMM[0].yyyy
 39: MOV TEMP[5].x, TEMP[0].xxxx
 40: MOV TEMP[5].y, TEMP[1].xxxx
 41: MOV TEMP[5].z, TEMP[0].yyyy
 42: DP4 TEMP[0].x, TEMP[5], CONST[0]
 43: DP4 TEMP[1].x, TEMP[5], CONST[1]
 44: MOV TEMP[0].y, TEMP[1].xxxx
 45: DP4 TEMP[1].x, TEMP[5], CONST[2]
 46: MOV TEMP[0].z, TEMP[1].xxxx
 47: DP4 TEMP[1].x, TEMP[5], CONST[3]
 48: MOV TEMP[0].w, TEMP[1].xxxx
 49: MOV TEMP[1].xy, TEMP[2].xyxx
 50: MOV TEMP[1].zw, TEMP[3].yyxy
 51: MOV TEMP[2].xyz, TEMP[4].xyzx
 52: MOV OUT[2], TEMP[2]
 53: MOV OUT[0], TEMP[0]
 54: MOV OUT[1], TEMP[1]
 55: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 256)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 260)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 368)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 372)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 376)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 384)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 388)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 392)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 396)
  %37 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
  %39 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %6)
  %40 = extractelement <4 x float> %39, i32 0
  %41 = extractelement <4 x float> %39, i32 1
  %42 = extractelement <4 x float> %39, i32 2
  %43 = extractelement <4 x float> %39, i32 3
  %44 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %45 = load <16 x i8> addrspace(2)* %44, !tbaa !0
  %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %45, i32 0, i32 %6)
  %47 = extractelement <4 x float> %46, i32 0
  %48 = extractelement <4 x float> %46, i32 1
  %49 = fmul float %40, %32
  %50 = fadd float %49, %30
  %51 = fmul float %41, %32
  %52 = fadd float %51, %31
  %53 = fadd float %42, -1.000000e+00
  %54 = fptosi float %53 to i32
  %55 = bitcast i32 %54 to float
  %56 = bitcast float %55 to i32
  %57 = icmp eq i32 %56, 1
  %58 = sext i1 %57 to i32
  %59 = bitcast float %55 to i32
  %60 = icmp eq i32 %59, 2
  %61 = sext i1 %60 to i32
  %62 = bitcast float %55 to i32
  %63 = icmp eq i32 %62, 3
  %64 = sext i1 %63 to i32
  %65 = bitcast i32 %58 to float
  %66 = bitcast i32 %61 to float
  %67 = bitcast i32 %64 to float
  %68 = bitcast float %65 to i32
  %69 = sitofp i32 %68 to float
  %70 = call float @llvm.AMDGPU.cndlt(float %69, float %34, float %33)
  %71 = bitcast float %66 to i32
  %72 = sitofp i32 %71 to float
  %73 = call float @llvm.AMDGPU.cndlt(float %72, float %35, float %70)
  %74 = bitcast float %67 to i32
  %75 = sitofp i32 %74 to float
  %76 = call float @llvm.AMDGPU.cndlt(float %75, float %36, float %73)
  %77 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00)
  %78 = fmul float %77, %76
  %79 = fsub float -0.000000e+00, %43
  %80 = fadd float 1.000000e+00, %79
  %81 = fmul float %78, %80
  %82 = fmul float %78, %43
  %83 = fmul float %81, %32
  %84 = fadd float %83, %50
  %85 = fmul float %82, %32
  %86 = fadd float %85, %52
  %87 = fadd float %84, 5.000000e-01
  %88 = fdiv float 1.000000e+00, %28
  %89 = fmul float %87, %88
  %90 = fadd float %86, 5.000000e-01
  %91 = fdiv float 1.000000e+00, %29
  %92 = fmul float %90, %91
  %93 = fadd float %84, 5.000000e-01
  %94 = fdiv float 1.000000e+00, %28
  %95 = fmul float %93, %94
  %96 = fadd float %86, 5.000000e-01
  %97 = fsub float -0.000000e+00, %29
  %98 = fadd float %96, %97
  %99 = fsub float -0.000000e+00, %29
  %100 = fdiv float 1.000000e+00, %99
  %101 = fmul float %98, %100
  %102 = fsub float -0.000000e+00, %78
  %103 = fadd float 1.000000e+00, %102
  %104 = fmul float %47, %103
  %105 = fmul float %48, %78
  %106 = fadd float %105, %104
  %107 = fmul float %106, 0x3F847AE140000000
  %108 = fmul float %84, %12
  %109 = fmul float %107, %13
  %110 = fadd float %108, %109
  %111 = fmul float %86, %14
  %112 = fadd float %110, %111
  %113 = fmul float 1.000000e+00, %15
  %114 = fadd float %112, %113
  %115 = fmul float %84, %16
  %116 = fmul float %107, %17
  %117 = fadd float %115, %116
  %118 = fmul float %86, %18
  %119 = fadd float %117, %118
  %120 = fmul float 1.000000e+00, %19
  %121 = fadd float %119, %120
  %122 = fmul float %84, %20
  %123 = fmul float %107, %21
  %124 = fadd float %122, %123
  %125 = fmul float %86, %22
  %126 = fadd float %124, %125
  %127 = fmul float 1.000000e+00, %23
  %128 = fadd float %126, %127
  %129 = fmul float %84, %24
  %130 = fmul float %107, %25
  %131 = fadd float %129, %130
  %132 = fmul float %86, %26
  %133 = fadd float %131, %132
  %134 = fmul float 1.000000e+00, %27
  %135 = fadd float %133, %134
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %89, float %92, float %95, float %101)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %84, float %107, float %86, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %114, float %121, float %128, float %135)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.cndlt(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840700
bf8c007f
e00c2000
80020100
bf8c0770
d2060005
0201e703
7e0a1105
d1040002
02010305
d2000006
00098280
7e0c0b06
d0080002
02020c80
c0840100
bf8c007f
c2000961
bf8c007f
7e0c0200
c2000960
bf8c007f
7e0e0200
d2000006
000a0d07
d1040000
02010505
d2000007
00018280
7e0e0b07
d0080000
02020e80
c2010962
bf8c007f
7e0e0202
d2000006
00020f06
d1040000
02010705
d2000005
00018280
7e0a0b05
d0080000
02020a80
c2010963
bf8c007f
7e0a0202
d2000005
00020b06
d2060806
02010103
100a0b06
100c0905
c200095d
bf8c007f
7e0e0200
c200095e
bf8c007f
7e100200
d2820007
041e1102
d2820006
041c0106
060e0cf0
c2008941
bf8c007f
7e125401
10121307
081408f2
10141505
c201095c
bf8c007f
7e160202
d2820001
042e1101
d2820001
0404010a
060402f0
c2000940
bf8c007f
7e065400
10040702
0a060e01
d2060004
22010001
7e085504
10060903
f800020f
03020902
bf8c070f
08040af2
c0800704
bf8c007f
e00c2000
80000700
bf8c0770
10000507
d2820000
04020b08
100000ff
3c23d70a
7e040280
f800021f
02060001
c200090d
bf8c000f
10040000
c200090c
bf8c007f
d2820002
04080101
c200090e
bf8c007f
d2820002
04080106
c200090f
bf8c007f
06040400
c2000909
bf8c007f
10060000
c2000908
bf8c007f
d2820003
040c0101
c200090a
bf8c007f
d2820003
040c0106
c200090b
bf8c007f
06060600
c2000905
bf8c007f
10080000
c2000904
bf8c007f
d2820004
04100101
c2000906
bf8c007f
d2820004
04100106
c2000907
bf8c007f
06080800
c2000901
bf8c007f
10000000
c2000900
bf8c007f
d2820000
04000101
c2000902
bf8c007f
d2820000
04000106
c2000903
bf8c007f
06000000
f80008cf
02030400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL IN[3], GENERIC[22], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL SAMP[4]
DCL SAMP[5]
DCL SAMP[6]
DCL SAMP[7]
DCL CONST[0..22]
DCL TEMP[0..9], LOCAL
IMM[0] FLT32 {   -0.5000,    70.0000,     0.2500,     1.0000}
IMM[1] FLT32 {    0.5000,     2.0000,     0.4356,     0.0000}
IMM[2] FLT32 {    0.6600,     0.0500,     0.0200,     0.0039}
IMM[3] FLT32 {    0.1000,     6.2832,     0.8000,     0.2000}
IMM[4] FLT32 {    1.2000, -160000.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xwww
  1: TEX TEMP[0], TEMP[0], SAMP[2], 2D
  2: MUL TEMP[1].xy, IN[1].xyyy, CONST[16].zwww
  3: MOV TEMP[1].xy, TEMP[1].xyyy
  4: TEX TEMP[1].xyz, TEMP[1], SAMP[6], 2D
  5: ADD TEMP[1].xyz, TEMP[1].xzyy, IMM[0].xxxx
  6: DP3 TEMP[2].x, TEMP[1].xyzz, TEMP[1].xyzz
  7: RSQ TEMP[2].x, TEMP[2].xxxx
  8: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xxxx
  9: MOV TEMP[2].xy, IN[0].xyyy
 10: TEX TEMP[2].xyz, TEMP[2], SAMP[0], 2D
 11: ADD TEMP[2].xyz, TEMP[2].xyzz, IMM[0].xxxx
 12: MOV TEMP[3].xy, IN[3].xyyy
 13: TEX TEMP[3].xyz, TEMP[3], SAMP[0], 2D
 14: ADD TEMP[3].xyz, TEMP[3].xyzz, IMM[0].xxxx
 15: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[3].xyzz
 16: RSQ TEMP[4].x, TEMP[4].xxxx
 17: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[2].xyzz
 18: RSQ TEMP[5].x, TEMP[5].xxxx
 19: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[5].xxxx
 20: MAD TEMP[2].xyz, TEMP[3].xyzz, TEMP[4].xxxx, TEMP[2].xyzz
 21: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
 22: RSQ TEMP[3].x, TEMP[3].xxxx
 23: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx
 24: MOV TEMP[3].x, -IN[1].wwww
 25: MOV TEMP[3].y, IN[1].zzzz
 26: MUL TEMP[4].xy, TEMP[2].xxxx, IN[1].zwww
 27: MAD TEMP[3].xy, TEMP[2].yyyy, TEMP[3].xyyy, TEMP[4].xyyy
 28: MUL TEMP[4].xyz, TEMP[1].yxzz, TEMP[3].xxxx
 29: MAD TEMP[2].xyz, TEMP[1].xyzz, TEMP[2].zzzz, TEMP[4].xyzz
 30: MAD TEMP[2].xyz, TEMP[1].xzyy, TEMP[3].yyyy, TEMP[2].xyzz
 31: ADD TEMP[3].xyz, IN[2].xyzz, -CONST[18].xyzz
 32: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[3].xyzz
 33: RSQ TEMP[4].x, TEMP[4].xxxx
 34: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
 35: ADD TEMP[3].xyz, -CONST[17].xyzz, -TEMP[3].xyzz
 36: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[3].xyzz
 37: RSQ TEMP[4].x, TEMP[4].xxxx
 38: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
 39: DP3_SAT TEMP[3].x, TEMP[3].xyzz, TEMP[2].xyzz
 40: POW TEMP[3].x, TEMP[3].xxxx, IMM[0].yyyy
 41: MUL_SAT TEMP[3].x, TEMP[3].xxxx, IMM[0].zzzz
 42: ADD TEMP[4].x, IMM[1].xxxx, -IN[0].wwww
 43: ABS TEMP[4].x, TEMP[4].xxxx
 44: MUL TEMP[4].x, TEMP[4].xxxx, IMM[1].yyyy
 45: ADD TEMP[4].x, IMM[0].wwww, -TEMP[4].xxxx
 46: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 47: DP3 TEMP[4].x, TEMP[2].xyzz, CONST[20].xyzz
 48: MUL TEMP[5].x, TEMP[4].xxxx, TEMP[4].xxxx
 49: ADD TEMP[5].x, IMM[0].wwww, -TEMP[5].xxxx
 50: MUL TEMP[5].x, TEMP[5].xxxx, IMM[1].zzzz
 51: ADD TEMP[5].x, IMM[0].wwww, -TEMP[5].xxxx
 52: FSLT TEMP[6].x, TEMP[5].xxxx, IMM[1].wwww
 53: UIF TEMP[6].xxxx :0
 54:   MOV TEMP[6].xz, IMM[1].wwww
 55: ELSE :0
 56:   RSQ TEMP[7].x, TEMP[5].xxxx
 57:   MUL TEMP[7].x, TEMP[7].xxxx, TEMP[5].xxxx
 58:   CMP TEMP[7].x, -TEMP[5].xxxx, TEMP[7].xxxx, IMM[1].wwww
 59:   MAD TEMP[4].x, IMM[2].xxxx, TEMP[4].xxxx, TEMP[7].xxxx
 60:   MUL TEMP[2].xyz, TEMP[4].xxxx, TEMP[2].xyzz
 61:   MAD TEMP[6].xz, IMM[2].xxxx, CONST[20].xyzz, -TEMP[2].xyzz
 62: ENDIF
 63: MOV TEMP[2].x, -IN[1].wwww
 64: MOV TEMP[2].y, IN[1].zzzz
 65: MUL TEMP[4].xy, TEMP[6].xxxx, IN[1].zwww
 66: MAD TEMP[2].xy, TEMP[6].zzzz, TEMP[2].xyyy, TEMP[4].xyyy
 67: MAD TEMP[2].xy, TEMP[2].xyyy, IMM[2].yyyy, IN[0].zwww
 68: MOV TEMP[2].xy, TEMP[2].xyyy
 69: TEX TEMP[2].xyz, TEMP[2], SAMP[7], 2D
 70: MOV TEMP[4].xy, IN[0].zwww
 71: TEX TEMP[4].w, TEMP[4], SAMP[7], 2D
 72: MOV TEMP[5].xy, IN[1].xyyy
 73: TEX TEMP[5].xyz, TEMP[5], SAMP[4], 2D
 74: FSLT TEMP[6].x, TEMP[5].xxxx, IMM[1].xxxx
 75: UIF TEMP[6].xxxx :0
 76:   MUL TEMP[6].x, IMM[1].yyyy, TEMP[5].xxxx
 77:   MUL TEMP[6].x, TEMP[6].xxxx, TEMP[2].xxxx
 78: ELSE :0
 79:   ADD TEMP[7].x, IMM[0].wwww, -TEMP[5].xxxx
 80:   MUL TEMP[7].x, IMM[1].yyyy, TEMP[7].xxxx
 81:   ADD TEMP[8].x, IMM[0].wwww, -TEMP[2].xxxx
 82:   MUL TEMP[7].x, TEMP[7].xxxx, TEMP[8].xxxx
 83:   ADD TEMP[6].x, IMM[0].wwww, -TEMP[7].xxxx
 84: ENDIF
 85: MOV TEMP[6].x, TEMP[6].xxxx
 86: FSLT TEMP[7].x, TEMP[5].yyyy, IMM[1].xxxx
 87: UIF TEMP[7].xxxx :0
 88:   MUL TEMP[7].x, IMM[1].yyyy, TEMP[5].yyyy
 89:   MUL TEMP[7].x, TEMP[7].xxxx, TEMP[2].yyyy
 90: ELSE :0
 91:   ADD TEMP[8].x, IMM[0].wwww, -TEMP[5].yyyy
 92:   MUL TEMP[8].x, IMM[1].yyyy, TEMP[8].xxxx
 93:   ADD TEMP[9].x, IMM[0].wwww, -TEMP[2].yyyy
 94:   MUL TEMP[8].x, TEMP[8].xxxx, TEMP[9].xxxx
 95:   ADD TEMP[7].x, IMM[0].wwww, -TEMP[8].xxxx
 96: ENDIF
 97: MOV TEMP[6].y, TEMP[7].xxxx
 98: FSLT TEMP[7].x, TEMP[5].zzzz, IMM[1].xxxx
 99: UIF TEMP[7].xxxx :0
100:   MUL TEMP[7].x, IMM[1].yyyy, TEMP[5].zzzz
101:   MUL TEMP[7].x, TEMP[7].xxxx, TEMP[2].zzzz
102: ELSE :0
103:   ADD TEMP[5].x, IMM[0].wwww, -TEMP[5].zzzz
104:   MUL TEMP[5].x, IMM[1].yyyy, TEMP[5].xxxx
105:   ADD TEMP[8].x, IMM[0].wwww, -TEMP[2].zzzz
106:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[8].xxxx
107:   ADD TEMP[7].x, IMM[0].wwww, -TEMP[5].xxxx
108: ENDIF
109: MOV TEMP[6].z, TEMP[7].xxxx
110: MOV TEMP[5].xy, IN[0].zwww
111: TEX TEMP[5].xyz, TEMP[5], SAMP[1], 2D
112: ADD TEMP[5].xyz, TEMP[5].xyzz, IMM[0].xxxx
113: DP3 TEMP[7].x, TEMP[5].xyzz, TEMP[5].xyzz
114: RSQ TEMP[7].x, TEMP[7].xxxx
115: MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[7].xxxx
116: MOV TEMP[7].x, -IN[1].wwww
117: MOV TEMP[7].y, IN[1].zzzz
118: MUL TEMP[8].xy, TEMP[5].xxxx, IN[1].zwww
119: MAD TEMP[7].xy, TEMP[5].yyyy, TEMP[7].xyyy, TEMP[8].xyyy
120: MUL TEMP[8].xyz, TEMP[1].yxzz, TEMP[7].xxxx
121: MAD TEMP[5].xyz, TEMP[1].xyzz, TEMP[5].zzzz, TEMP[8].xyzz
122: MAD TEMP[1].xyz, TEMP[1].xzyy, TEMP[7].yyyy, TEMP[5].xyzz
123: DP3 TEMP[1].x, TEMP[1].xyzz, -CONST[17].xyzz
124: MAD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx, IMM[1].xxxx
125: ADD TEMP[5].x, IN[2].xxxx, IMM[1].xxxx
126: RCP TEMP[7].x, CONST[16].xxxx
127: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[7].xxxx
128: ADD TEMP[7].x, IN[2].zzzz, IMM[1].xxxx
129: RCP TEMP[8].x, CONST[16].yyyy
130: MUL TEMP[7].x, TEMP[7].xxxx, TEMP[8].xxxx
131: MOV TEMP[5].y, TEMP[7].xxxx
132: MOV TEMP[5].xy, TEMP[5].xyyy
133: TEX TEMP[5].w, TEMP[5], SAMP[3], 2D
134: ADD TEMP[7].xy, IN[2].xzzz, IMM[1].xxxx
135: MUL TEMP[7].xy, TEMP[7].xyyy, IMM[2].wwww
136: MAD TEMP[7].xy, CONST[22].yyyy, IMM[2].zzzz, TEMP[7].xyyy
137: MOV TEMP[7].xy, TEMP[7].xyyy
138: TEX TEMP[7].x, TEMP[7], SAMP[5], 2D
139: MUL TEMP[8].x, CONST[22].yyyy, IMM[3].xxxx
140: FRC TEMP[8].x, TEMP[8].xxxx
141: ADD TEMP[7].x, TEMP[7].xxxx, TEMP[8].xxxx
142: MUL TEMP[7].x, TEMP[7].xxxx, IMM[3].yyyy
143: SIN TEMP[7].x, TEMP[7].xxxx
144: MAD TEMP[7].x, TEMP[7].xxxx, IMM[3].xxxx, IMM[1].xxxx
145: ADD_SAT TEMP[5].x, TEMP[5].wwww, TEMP[7].xxxx
146: LRP TEMP[5].x, CONST[22].xxxx, TEMP[5].xxxx, IMM[0].wwww
147: ADD TEMP[7].xyz, CONST[18].xyzz, -IN[2].xyzz
148: ADD TEMP[8].x, IMM[0].wwww, -IN[2].wwww
149: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[8].xxxx
150: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[0].wwww
151: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
152: MAD TEMP[1].x, IMM[3].zzzz, TEMP[1].xxxx, IMM[3].wwww
153: LRP TEMP[2].xyz, IMM[1].xxxx, TEMP[6].xyzz, TEMP[2].xyzz
154: MUL TEMP[6].x, TEMP[0].wwww, IMM[3].zzzz
155: LRP TEMP[0].xyz, TEMP[6].xxxx, TEMP[0].xyzz, TEMP[2].xyzz
156: MUL TEMP[0].xyz, TEMP[1].xxxx, TEMP[0].xyzz
157: MUL_SAT TEMP[0].xyz, TEMP[0].xyzz, IMM[4].xxxx
158: DP3 TEMP[1].x, TEMP[7].xyzz, TEMP[7].xyzz
159: ADD TEMP[1].x, TEMP[1].xxxx, IMM[4].yyyy
160: MUL TEMP[1].x, TEMP[1].xxxx, IMM[4].zzzz
161: MIN TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx
162: MOV_SAT TEMP[1].x, TEMP[1].xxxx
163: DP3 TEMP[2].x, TEMP[7].xyzz, TEMP[7].xyzz
164: RSQ TEMP[2].x, TEMP[2].xxxx
165: MUL TEMP[2].y, TEMP[7].xyzz, TEMP[2].xxxx
166: ADD TEMP[2].x, IMM[0].wwww, -TEMP[2].yyyy
167: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
168: LRP TEMP[0].xyz, TEMP[1].xxxx, IMM[1].xxxx, TEMP[0].xyzz
169: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[5].xxxx
170: MAD_SAT TEMP[0].xyz, TEMP[3].xxxx, TEMP[5].xxxx, TEMP[0].xyzz
171: MOV TEMP[0].xyz, TEMP[0].xyzx
172: ADD TEMP[1].x, IMM[0].wwww, -IN[2].wwww
173: MUL TEMP[1].x, TEMP[4].wwww, TEMP[1].xxxx
174: MOV TEMP[0].w, TEMP[1].xxxx
175: MOV OUT[0], TEMP[0]
176: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 264)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 268)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 276)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 280)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 320)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 324)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 328)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %42 = load <32 x i8> addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %46 = load <32 x i8> addrspace(2)* %45, !tbaa !0
  %47 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %50 = load <32 x i8> addrspace(2)* %49, !tbaa !0
  %51 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
  %54 = load <32 x i8> addrspace(2)* %53, !tbaa !0
  %55 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
  %58 = load <32 x i8> addrspace(2)* %57, !tbaa !0
  %59 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
  %61 = getelementptr <32 x i8> addrspace(2)* %2, i32 6
  %62 = load <32 x i8> addrspace(2)* %61, !tbaa !0
  %63 = getelementptr <16 x i8> addrspace(2)* %1, i32 6
  %64 = load <16 x i8> addrspace(2)* %63, !tbaa !0
  %65 = getelementptr <32 x i8> addrspace(2)* %2, i32 7
  %66 = load <32 x i8> addrspace(2)* %65, !tbaa !0
  %67 = getelementptr <16 x i8> addrspace(2)* %1, i32 7
  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
  %69 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %70 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %71 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %72 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %73 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %74 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %75 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %76 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %77 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %78 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %79 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %80 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %81 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
  %82 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
  %83 = bitcast float %69 to i32
  %84 = bitcast float %72 to i32
  %85 = insertelement <2 x i32> undef, i32 %83, i32 0
  %86 = insertelement <2 x i32> %85, i32 %84, i32 1
  %87 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %86, <32 x i8> %46, <16 x i8> %48, i32 2)
  %88 = extractelement <4 x float> %87, i32 0
  %89 = extractelement <4 x float> %87, i32 1
  %90 = extractelement <4 x float> %87, i32 2
  %91 = extractelement <4 x float> %87, i32 3
  %92 = fmul float %73, %24
  %93 = fmul float %74, %25
  %94 = bitcast float %92 to i32
  %95 = bitcast float %93 to i32
  %96 = insertelement <2 x i32> undef, i32 %94, i32 0
  %97 = insertelement <2 x i32> %96, i32 %95, i32 1
  %98 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %97, <32 x i8> %62, <16 x i8> %64, i32 2)
  %99 = extractelement <4 x float> %98, i32 0
  %100 = extractelement <4 x float> %98, i32 1
  %101 = extractelement <4 x float> %98, i32 2
  %102 = fadd float %99, -5.000000e-01
  %103 = fadd float %101, -5.000000e-01
  %104 = fadd float %100, -5.000000e-01
  %105 = fmul float %102, %102
  %106 = fmul float %103, %103
  %107 = fadd float %106, %105
  %108 = fmul float %104, %104
  %109 = fadd float %107, %108
  %110 = call float @llvm.AMDGPU.rsq(float %109)
  %111 = fmul float %102, %110
  %112 = fmul float %103, %110
  %113 = fmul float %104, %110
  %114 = bitcast float %69 to i32
  %115 = bitcast float %70 to i32
  %116 = insertelement <2 x i32> undef, i32 %114, i32 0
  %117 = insertelement <2 x i32> %116, i32 %115, i32 1
  %118 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %117, <32 x i8> %38, <16 x i8> %40, i32 2)
  %119 = extractelement <4 x float> %118, i32 0
  %120 = extractelement <4 x float> %118, i32 1
  %121 = extractelement <4 x float> %118, i32 2
  %122 = fadd float %119, -5.000000e-01
  %123 = fadd float %120, -5.000000e-01
  %124 = fadd float %121, -5.000000e-01
  %125 = bitcast float %81 to i32
  %126 = bitcast float %82 to i32
  %127 = insertelement <2 x i32> undef, i32 %125, i32 0
  %128 = insertelement <2 x i32> %127, i32 %126, i32 1
  %129 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %128, <32 x i8> %38, <16 x i8> %40, i32 2)
  %130 = extractelement <4 x float> %129, i32 0
  %131 = extractelement <4 x float> %129, i32 1
  %132 = extractelement <4 x float> %129, i32 2
  %133 = fadd float %130, -5.000000e-01
  %134 = fadd float %131, -5.000000e-01
  %135 = fadd float %132, -5.000000e-01
  %136 = fmul float %133, %133
  %137 = fmul float %134, %134
  %138 = fadd float %137, %136
  %139 = fmul float %135, %135
  %140 = fadd float %138, %139
  %141 = call float @llvm.AMDGPU.rsq(float %140)
  %142 = fmul float %122, %122
  %143 = fmul float %123, %123
  %144 = fadd float %143, %142
  %145 = fmul float %124, %124
  %146 = fadd float %144, %145
  %147 = call float @llvm.AMDGPU.rsq(float %146)
  %148 = fmul float %122, %147
  %149 = fmul float %123, %147
  %150 = fmul float %124, %147
  %151 = fmul float %133, %141
  %152 = fadd float %151, %148
  %153 = fmul float %134, %141
  %154 = fadd float %153, %149
  %155 = fmul float %135, %141
  %156 = fadd float %155, %150
  %157 = fmul float %152, %152
  %158 = fmul float %154, %154
  %159 = fadd float %158, %157
  %160 = fmul float %156, %156
  %161 = fadd float %159, %160
  %162 = call float @llvm.AMDGPU.rsq(float %161)
  %163 = fmul float %152, %162
  %164 = fmul float %154, %162
  %165 = fmul float %156, %162
  %166 = fsub float -0.000000e+00, %76
  %167 = fmul float %163, %75
  %168 = fmul float %163, %76
  %169 = fmul float %164, %166
  %170 = fadd float %169, %167
  %171 = fmul float %164, %75
  %172 = fadd float %171, %168
  %173 = fmul float %112, %170
  %174 = fmul float %111, %170
  %175 = fmul float %113, %170
  %176 = fmul float %111, %165
  %177 = fadd float %176, %173
  %178 = fmul float %112, %165
  %179 = fadd float %178, %174
  %180 = fmul float %113, %165
  %181 = fadd float %180, %175
  %182 = fmul float %111, %172
  %183 = fadd float %182, %177
  %184 = fmul float %113, %172
  %185 = fadd float %184, %179
  %186 = fmul float %112, %172
  %187 = fadd float %186, %181
  %188 = fsub float -0.000000e+00, %29
  %189 = fadd float %77, %188
  %190 = fsub float -0.000000e+00, %30
  %191 = fadd float %78, %190
  %192 = fsub float -0.000000e+00, %31
  %193 = fadd float %79, %192
  %194 = fmul float %189, %189
  %195 = fmul float %191, %191
  %196 = fadd float %195, %194
  %197 = fmul float %193, %193
  %198 = fadd float %196, %197
  %199 = call float @llvm.AMDGPU.rsq(float %198)
  %200 = fmul float %189, %199
  %201 = fmul float %191, %199
  %202 = fmul float %193, %199
  %203 = fsub float -0.000000e+00, %26
  %204 = fsub float -0.000000e+00, %200
  %205 = fadd float %203, %204
  %206 = fsub float -0.000000e+00, %27
  %207 = fsub float -0.000000e+00, %201
  %208 = fadd float %206, %207
  %209 = fsub float -0.000000e+00, %28
  %210 = fsub float -0.000000e+00, %202
  %211 = fadd float %209, %210
  %212 = fmul float %205, %205
  %213 = fmul float %208, %208
  %214 = fadd float %213, %212
  %215 = fmul float %211, %211
  %216 = fadd float %214, %215
  %217 = call float @llvm.AMDGPU.rsq(float %216)
  %218 = fmul float %205, %217
  %219 = fmul float %208, %217
  %220 = fmul float %211, %217
  %221 = fmul float %218, %183
  %222 = fmul float %219, %185
  %223 = fadd float %222, %221
  %224 = fmul float %220, %187
  %225 = fadd float %223, %224
  %226 = call float @llvm.AMDIL.clamp.(float %225, float 0.000000e+00, float 1.000000e+00)
  %227 = call float @llvm.pow.f32(float %226, float 7.000000e+01)
  %228 = fmul float %227, 2.500000e-01
  %229 = call float @llvm.AMDIL.clamp.(float %228, float 0.000000e+00, float 1.000000e+00)
  %230 = fsub float -0.000000e+00, %72
  %231 = fadd float 5.000000e-01, %230
  %232 = call float @fabs(float %231)
  %233 = fmul float %232, 2.000000e+00
  %234 = fsub float -0.000000e+00, %233
  %235 = fadd float 1.000000e+00, %234
  %236 = fmul float %229, %235
  %237 = fmul float %183, %32
  %238 = fmul float %185, %33
  %239 = fadd float %238, %237
  %240 = fmul float %187, %34
  %241 = fadd float %239, %240
  %242 = fmul float %241, %241
  %243 = fsub float -0.000000e+00, %242
  %244 = fadd float 1.000000e+00, %243
  %245 = fmul float %244, 0x3FDBE0DF00000000
  %246 = fsub float -0.000000e+00, %245
  %247 = fadd float 1.000000e+00, %246
  %248 = fcmp olt float %247, 0.000000e+00
  %249 = sext i1 %248 to i32
  %250 = bitcast i32 %249 to float
  %251 = bitcast float %250 to i32
  %252 = icmp ne i32 %251, 0
  br i1 %252, label %ENDIF, label %ELSE

ELSE:                                             ; preds = %main_body
  %253 = call float @llvm.AMDGPU.rsq(float %247)
  %254 = fmul float %253, %247
  %255 = fsub float -0.000000e+00, %247
  %256 = call float @llvm.AMDGPU.cndlt(float %255, float %254, float 0.000000e+00)
  %257 = fmul float 0x3FE51EB860000000, %241
  %258 = fadd float %257, %256
  %259 = fmul float %258, %183
  %260 = fmul float %258, %187
  %261 = fsub float -0.000000e+00, %259
  %262 = fmul float 0x3FE51EB860000000, %32
  %263 = fadd float %262, %261
  %264 = fsub float -0.000000e+00, %260
  %265 = fmul float 0x3FE51EB860000000, %34
  %266 = fadd float %265, %264
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %ELSE
  %temp24.0 = phi float [ %263, %ELSE ], [ 0.000000e+00, %main_body ]
  %temp26.0 = phi float [ %266, %ELSE ], [ 0.000000e+00, %main_body ]
  %267 = fsub float -0.000000e+00, %76
  %268 = fmul float %temp24.0, %75
  %269 = fmul float %temp24.0, %76
  %270 = fmul float %temp26.0, %267
  %271 = fadd float %270, %268
  %272 = fmul float %temp26.0, %75
  %273 = fadd float %272, %269
  %274 = fmul float %271, 0x3FA99999A0000000
  %275 = fadd float %274, %71
  %276 = fmul float %273, 0x3FA99999A0000000
  %277 = fadd float %276, %72
  %278 = bitcast float %275 to i32
  %279 = bitcast float %277 to i32
  %280 = insertelement <2 x i32> undef, i32 %278, i32 0
  %281 = insertelement <2 x i32> %280, i32 %279, i32 1
  %282 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %281, <32 x i8> %66, <16 x i8> %68, i32 2)
  %283 = extractelement <4 x float> %282, i32 0
  %284 = extractelement <4 x float> %282, i32 1
  %285 = extractelement <4 x float> %282, i32 2
  %286 = bitcast float %71 to i32
  %287 = bitcast float %72 to i32
  %288 = insertelement <2 x i32> undef, i32 %286, i32 0
  %289 = insertelement <2 x i32> %288, i32 %287, i32 1
  %290 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %289, <32 x i8> %66, <16 x i8> %68, i32 2)
  %291 = extractelement <4 x float> %290, i32 3
  %292 = bitcast float %73 to i32
  %293 = bitcast float %74 to i32
  %294 = insertelement <2 x i32> undef, i32 %292, i32 0
  %295 = insertelement <2 x i32> %294, i32 %293, i32 1
  %296 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %295, <32 x i8> %54, <16 x i8> %56, i32 2)
  %297 = extractelement <4 x float> %296, i32 0
  %298 = extractelement <4 x float> %296, i32 1
  %299 = extractelement <4 x float> %296, i32 2
  %300 = fcmp olt float %297, 5.000000e-01
  %301 = sext i1 %300 to i32
  %302 = bitcast i32 %301 to float
  %303 = bitcast float %302 to i32
  %304 = icmp ne i32 %303, 0
  br i1 %304, label %IF41, label %ELSE42

IF41:                                             ; preds = %ENDIF
  %305 = fmul float 2.000000e+00, %297
  %306 = fmul float %305, %283
  br label %ENDIF40

ELSE42:                                           ; preds = %ENDIF
  %307 = fsub float -0.000000e+00, %297
  %308 = fadd float 1.000000e+00, %307
  %309 = fmul float 2.000000e+00, %308
  %310 = fsub float -0.000000e+00, %283
  %311 = fadd float 1.000000e+00, %310
  %312 = fmul float %309, %311
  %313 = fsub float -0.000000e+00, %312
  %314 = fadd float 1.000000e+00, %313
  br label %ENDIF40

ENDIF40:                                          ; preds = %ELSE42, %IF41
  %temp24.1 = phi float [ %306, %IF41 ], [ %314, %ELSE42 ]
  %315 = fcmp olt float %298, 5.000000e-01
  %316 = sext i1 %315 to i32
  %317 = bitcast i32 %316 to float
  %318 = bitcast float %317 to i32
  %319 = icmp ne i32 %318, 0
  br i1 %319, label %IF44, label %ELSE45

IF44:                                             ; preds = %ENDIF40
  %320 = fmul float 2.000000e+00, %298
  %321 = fmul float %320, %284
  br label %ENDIF43

ELSE45:                                           ; preds = %ENDIF40
  %322 = fsub float -0.000000e+00, %298
  %323 = fadd float 1.000000e+00, %322
  %324 = fmul float 2.000000e+00, %323
  %325 = fsub float -0.000000e+00, %284
  %326 = fadd float 1.000000e+00, %325
  %327 = fmul float %324, %326
  %328 = fsub float -0.000000e+00, %327
  %329 = fadd float 1.000000e+00, %328
  br label %ENDIF43

ENDIF43:                                          ; preds = %ELSE45, %IF44
  %temp28.0 = phi float [ %321, %IF44 ], [ %329, %ELSE45 ]
  %330 = fcmp olt float %299, 5.000000e-01
  %331 = sext i1 %330 to i32
  %332 = bitcast i32 %331 to float
  %333 = bitcast float %332 to i32
  %334 = icmp ne i32 %333, 0
  br i1 %334, label %IF47, label %ELSE48

IF47:                                             ; preds = %ENDIF43
  %335 = fmul float 2.000000e+00, %299
  %336 = fmul float %335, %285
  br label %ENDIF46

ELSE48:                                           ; preds = %ENDIF43
  %337 = fsub float -0.000000e+00, %299
  %338 = fadd float 1.000000e+00, %337
  %339 = fmul float 2.000000e+00, %338
  %340 = fsub float -0.000000e+00, %285
  %341 = fadd float 1.000000e+00, %340
  %342 = fmul float %339, %341
  %343 = fsub float -0.000000e+00, %342
  %344 = fadd float 1.000000e+00, %343
  br label %ENDIF46

ENDIF46:                                          ; preds = %ELSE48, %IF47
  %temp28.1 = phi float [ %336, %IF47 ], [ %344, %ELSE48 ]
  %345 = bitcast float %71 to i32
  %346 = bitcast float %72 to i32
  %347 = insertelement <2 x i32> undef, i32 %345, i32 0
  %348 = insertelement <2 x i32> %347, i32 %346, i32 1
  %349 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %348, <32 x i8> %42, <16 x i8> %44, i32 2)
  %350 = extractelement <4 x float> %349, i32 0
  %351 = extractelement <4 x float> %349, i32 1
  %352 = extractelement <4 x float> %349, i32 2
  %353 = fadd float %350, -5.000000e-01
  %354 = fadd float %351, -5.000000e-01
  %355 = fadd float %352, -5.000000e-01
  %356 = fmul float %353, %353
  %357 = fmul float %354, %354
  %358 = fadd float %357, %356
  %359 = fmul float %355, %355
  %360 = fadd float %358, %359
  %361 = call float @llvm.AMDGPU.rsq(float %360)
  %362 = fmul float %353, %361
  %363 = fmul float %354, %361
  %364 = fmul float %355, %361
  %365 = fsub float -0.000000e+00, %76
  %366 = fmul float %362, %75
  %367 = fmul float %362, %76
  %368 = fmul float %363, %365
  %369 = fadd float %368, %366
  %370 = fmul float %363, %75
  %371 = fadd float %370, %367
  %372 = fmul float %112, %369
  %373 = fmul float %111, %369
  %374 = fmul float %113, %369
  %375 = fmul float %111, %364
  %376 = fadd float %375, %372
  %377 = fmul float %112, %364
  %378 = fadd float %377, %373
  %379 = fmul float %113, %364
  %380 = fadd float %379, %374
  %381 = fmul float %111, %371
  %382 = fadd float %381, %376
  %383 = fmul float %113, %371
  %384 = fadd float %383, %378
  %385 = fmul float %112, %371
  %386 = fadd float %385, %380
  %387 = fsub float -0.000000e+00, %26
  %388 = fsub float -0.000000e+00, %27
  %389 = fsub float -0.000000e+00, %28
  %390 = fmul float %382, %387
  %391 = fmul float %384, %388
  %392 = fadd float %391, %390
  %393 = fmul float %386, %389
  %394 = fadd float %392, %393
  %395 = fmul float %394, 5.000000e-01
  %396 = fadd float %395, 5.000000e-01
  %397 = fadd float %77, 5.000000e-01
  %398 = fdiv float 1.000000e+00, %22
  %399 = fmul float %397, %398
  %400 = fadd float %79, 5.000000e-01
  %401 = fdiv float 1.000000e+00, %23
  %402 = fmul float %400, %401
  %403 = bitcast float %399 to i32
  %404 = bitcast float %402 to i32
  %405 = insertelement <2 x i32> undef, i32 %403, i32 0
  %406 = insertelement <2 x i32> %405, i32 %404, i32 1
  %407 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %406, <32 x i8> %50, <16 x i8> %52, i32 2)
  %408 = extractelement <4 x float> %407, i32 3
  %409 = fadd float %77, 5.000000e-01
  %410 = fadd float %79, 5.000000e-01
  %411 = fmul float %409, 3.906250e-03
  %412 = fmul float %410, 3.906250e-03
  %413 = fmul float %36, 0x3F947AE140000000
  %414 = fadd float %413, %411
  %415 = fmul float %36, 0x3F947AE140000000
  %416 = fadd float %415, %412
  %417 = bitcast float %414 to i32
  %418 = bitcast float %416 to i32
  %419 = insertelement <2 x i32> undef, i32 %417, i32 0
  %420 = insertelement <2 x i32> %419, i32 %418, i32 1
  %421 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %420, <32 x i8> %58, <16 x i8> %60, i32 2)
  %422 = extractelement <4 x float> %421, i32 0
  %423 = fmul float %36, 0x3FB99999A0000000
  %424 = call float @llvm.AMDIL.fraction.(float %423)
  %425 = fadd float %422, %424
  %426 = fmul float %425, 0x401921FB60000000
  %427 = call float @llvm.sin.f32(float %426)
  %428 = fmul float %427, 0x3FB99999A0000000
  %429 = fadd float %428, 5.000000e-01
  %430 = fadd float %408, %429
  %431 = call float @llvm.AMDIL.clamp.(float %430, float 0.000000e+00, float 1.000000e+00)
  %432 = call float @llvm.AMDGPU.lrp(float %35, float %431, float 1.000000e+00)
  %433 = fsub float -0.000000e+00, %77
  %434 = fadd float %29, %433
  %435 = fsub float -0.000000e+00, %78
  %436 = fadd float %30, %435
  %437 = fsub float -0.000000e+00, %79
  %438 = fadd float %31, %437
  %439 = fsub float -0.000000e+00, %80
  %440 = fadd float 1.000000e+00, %439
  %441 = fmul float %236, %440
  %442 = fmul float %441, %91
  %443 = fmul float %396, %396
  %444 = fmul float 0x3FE99999A0000000, %443
  %445 = fadd float %444, 0x3FC99999A0000000
  %446 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp24.1, float %283)
  %447 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp28.0, float %284)
  %448 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp28.1, float %285)
  %449 = fmul float %91, 0x3FE99999A0000000
  %450 = call float @llvm.AMDGPU.lrp(float %449, float %88, float %446)
  %451 = call float @llvm.AMDGPU.lrp(float %449, float %89, float %447)
  %452 = call float @llvm.AMDGPU.lrp(float %449, float %90, float %448)
  %453 = fmul float %445, %450
  %454 = fmul float %445, %451
  %455 = fmul float %445, %452
  %456 = fmul float %453, 0x3FF3333340000000
  %457 = fmul float %454, 0x3FF3333340000000
  %458 = fmul float %455, 0x3FF3333340000000
  %459 = call float @llvm.AMDIL.clamp.(float %456, float 0.000000e+00, float 1.000000e+00)
  %460 = call float @llvm.AMDIL.clamp.(float %457, float 0.000000e+00, float 1.000000e+00)
  %461 = call float @llvm.AMDIL.clamp.(float %458, float 0.000000e+00, float 1.000000e+00)
  %462 = fmul float %434, %434
  %463 = fmul float %436, %436
  %464 = fadd float %463, %462
  %465 = fmul float %438, %438
  %466 = fadd float %464, %465
  %467 = fadd float %466, -1.600000e+05
  %468 = fmul float %467, 0x3EAA36E2E0000000
  %469 = fcmp uge float %468, 5.000000e-01
  %470 = select i1 %469, float 5.000000e-01, float %468
  %471 = call float @llvm.AMDIL.clamp.(float %470, float 0.000000e+00, float 1.000000e+00)
  %472 = fmul float %434, %434
  %473 = fmul float %436, %436
  %474 = fadd float %473, %472
  %475 = fmul float %438, %438
  %476 = fadd float %474, %475
  %477 = call float @llvm.AMDGPU.rsq(float %476)
  %478 = fmul float %436, %477
  %479 = fsub float -0.000000e+00, %478
  %480 = fadd float 1.000000e+00, %479
  %481 = fmul float %471, %480
  %482 = call float @llvm.AMDGPU.lrp(float %481, float 5.000000e-01, float %459)
  %483 = call float @llvm.AMDGPU.lrp(float %481, float 5.000000e-01, float %460)
  %484 = call float @llvm.AMDGPU.lrp(float %481, float 5.000000e-01, float %461)
  %485 = fmul float %482, %432
  %486 = fmul float %483, %432
  %487 = fmul float %484, %432
  %488 = fmul float %442, %432
  %489 = fadd float %488, %485
  %490 = fmul float %442, %432
  %491 = fadd float %490, %486
  %492 = fmul float %442, %432
  %493 = fadd float %492, %487
  %494 = call float @llvm.AMDIL.clamp.(float %489, float 0.000000e+00, float 1.000000e+00)
  %495 = call float @llvm.AMDIL.clamp.(float %491, float 0.000000e+00, float 1.000000e+00)
  %496 = call float @llvm.AMDIL.clamp.(float %493, float 0.000000e+00, float 1.000000e+00)
  %497 = fsub float -0.000000e+00, %80
  %498 = fadd float 1.000000e+00, %497
  %499 = fmul float %291, %498
  %500 = call i32 @llvm.SI.packf16(float %494, float %495)
  %501 = bitcast i32 %500 to float
  %502 = call i32 @llvm.SI.packf16(float %496, float %499)
  %503 = bitcast i32 %502 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %501, float %503, float %501, float %503)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: readonly
declare float @fabs(float) #4

; Function Attrs: readnone
declare float @llvm.AMDGPU.cndlt(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }
attributes #4 = { readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
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d00c0000
0201e10a
d200000a
0001e10a
d206080a
0201010a
7e125b09
10101308
081010f2
1010110a
081210f2
10060709
d2820003
040de108
d2060007
0201e107
10140eff
3b800000
7e1e02ff
3ca3d70a
d2820017
042a1e0f
d2060006
0201e106
10140cff
3b800000
d2820016
042a1e0f
f0800100
00e80a16
7e1e02ff
3dcccccd
102c1e0f
7e2c4116
bf8c0770
06142d0a
101414ff
40c90fdb
101414ff
3e22f983
7e146b0a
d282000a
03c21f0a
7e1e5403
102e1f07
7e0e5402
102c0f06
f0800800
00850616
bf8c0770
060c1506
d2060806
02010106
d2080007
02000cf2
d2820006
041e0c06
10060d03
d2080007
020222f2
10140f10
1014150e
d2820003
040e0d0a
d2060803
02010103
d210000f
0201e112
d2820001
043de101
10020305
d2820001
04061704
10020302
100202ff
3f99999a
d2060801
02010101
10020309
d2820001
0405e108
10020d01
d2820001
04060d0a
d2060801
02010101
5e020701
d2100003
0201e114
d2820003
040de115
10060705
d2820003
040e1b04
10040702
100404ff
3f99999a
d2060802
02010102
10040509
d2820002
0409e108
10040d02
d2820002
040a0d0a
d2060802
02010102
10000f00
5e000102
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL OUT[3], GENERIC[21]
DCL OUT[4], GENERIC[22]
DCL CONST[0..23]
DCL TEMP[0..6], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0500,     0.2000}
IMM[1] FLT32 {    0.9000,     0.1000,     0.5000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xyz, IN[0].xyzx
  2: MOV TEMP[1].xyz, IN[0].xyzx
  3: MOV TEMP[2].w, IMM[0].yyyy
  4: MUL TEMP[2].xyz, CONST[20].xyzz, IMM[0].zzzz
  5: DP4 TEMP[3].x, TEMP[0], CONST[0]
  6: DP4 TEMP[4].x, TEMP[0], CONST[1]
  7: MOV TEMP[3].y, TEMP[4].xxxx
  8: DP4 TEMP[4].x, TEMP[0], CONST[3]
  9: MOV TEMP[3].xy, TEMP[3].xyxx
 10: ADD TEMP[0], TEMP[0], -TEMP[2]
 11: DP4 TEMP[0].x, TEMP[0], CONST[2]
 12: MOV TEMP[3].z, TEMP[0].xxxx
 13: MOV TEMP[3].w, TEMP[4].xxxx
 14: MAD TEMP[0].x, CONST[23].xxxx, CONST[23].yyyy, IN[1].yyyy
 15: MAD TEMP[2].x, CONST[23].xxxx, IMM[0].wwww, IN[1].xxxx
 16: MOV TEMP[0].y, TEMP[2].xxxx
 17: MUL TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz
 18: MUL TEMP[2].x, CONST[23].xxxx, IMM[1].xxxx
 19: MAD TEMP[2].x, TEMP[2].xxxx, CONST[23].yyyy, IN[1].yyyy
 20: MUL TEMP[4].x, CONST[23].xxxx, IMM[1].yyyy
 21: ADD TEMP[4].x, IN[1].xxxx, -TEMP[4].xxxx
 22: MOV TEMP[2].y, TEMP[4].xxxx
 23: MUL TEMP[2].x, TEMP[2].xxxx, IMM[0].zzzz
 24: MOV TEMP[0].w, IN[1].xxxx
 25: MUL TEMP[4].x, IN[1].yyyy, IMM[0].zzzz
 26: MOV TEMP[0].z, TEMP[4].xxxx
 27: ADD TEMP[4].x, IN[0].xxxx, IMM[1].zzzz
 28: RCP TEMP[5].x, CONST[16].xxxx
 29: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 30: ADD TEMP[5].x, IN[0].zzzz, IMM[1].zzzz
 31: ADD TEMP[5].x, TEMP[5].xxxx, -CONST[16].yyyy
 32: RCP TEMP[6].x, -CONST[16].yyyy
 33: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 34: MOV TEMP[4].y, TEMP[5].xxxx
 35: MOV TEMP[4].zw, IN[1].wwzw
 36: ADD_SAT TEMP[5].x, IMM[0].xxxx, -IN[1].yyyy
 37: MOV TEMP[1].w, TEMP[5].xxxx
 38: MOV TEMP[2].xy, TEMP[2].xyxx
 39: MOV OUT[1], TEMP[0]
 40: MOV OUT[2], TEMP[4]
 41: MOV OUT[3], TEMP[1]
 42: MOV OUT[4], TEMP[2]
 43: MOV OUT[0], TEMP[3]
 44: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 256)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 260)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 320)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 324)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 328)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 368)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 372)
  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %6)
  %44 = extractelement <4 x float> %43, i32 0
  %45 = extractelement <4 x float> %43, i32 1
  %46 = extractelement <4 x float> %43, i32 2
  %47 = extractelement <4 x float> %43, i32 3
  %48 = fmul float %30, 0x3FA99999A0000000
  %49 = fmul float %31, 0x3FA99999A0000000
  %50 = fmul float %32, 0x3FA99999A0000000
  %51 = fmul float %38, %12
  %52 = fmul float %39, %13
  %53 = fadd float %51, %52
  %54 = fmul float %40, %14
  %55 = fadd float %53, %54
  %56 = fmul float 1.000000e+00, %15
  %57 = fadd float %55, %56
  %58 = fmul float %38, %16
  %59 = fmul float %39, %17
  %60 = fadd float %58, %59
  %61 = fmul float %40, %18
  %62 = fadd float %60, %61
  %63 = fmul float 1.000000e+00, %19
  %64 = fadd float %62, %63
  %65 = fmul float %38, %24
  %66 = fmul float %39, %25
  %67 = fadd float %65, %66
  %68 = fmul float %40, %26
  %69 = fadd float %67, %68
  %70 = fmul float 1.000000e+00, %27
  %71 = fadd float %69, %70
  %72 = fsub float -0.000000e+00, %48
  %73 = fadd float %38, %72
  %74 = fsub float -0.000000e+00, %49
  %75 = fadd float %39, %74
  %76 = fsub float -0.000000e+00, %50
  %77 = fadd float %40, %76
  %78 = fsub float -0.000000e+00, 0.000000e+00
  %79 = fadd float 1.000000e+00, %78
  %80 = fmul float %73, %20
  %81 = fmul float %75, %21
  %82 = fadd float %80, %81
  %83 = fmul float %77, %22
  %84 = fadd float %82, %83
  %85 = fmul float %79, %23
  %86 = fadd float %84, %85
  %87 = fmul float %33, %34
  %88 = fadd float %87, %45
  %89 = fmul float %33, 0x3FC99999A0000000
  %90 = fadd float %89, %44
  %91 = fmul float %88, 0x3FA99999A0000000
  %92 = fmul float %33, 0x3FECCCCCC0000000
  %93 = fmul float %92, %34
  %94 = fadd float %93, %45
  %95 = fmul float %33, 0x3FB99999A0000000
  %96 = fsub float -0.000000e+00, %95
  %97 = fadd float %44, %96
  %98 = fmul float %94, 0x3FA99999A0000000
  %99 = fmul float %45, 0x3FA99999A0000000
  %100 = fadd float %38, 5.000000e-01
  %101 = fdiv float 1.000000e+00, %28
  %102 = fmul float %100, %101
  %103 = fadd float %40, 5.000000e-01
  %104 = fsub float -0.000000e+00, %29
  %105 = fadd float %103, %104
  %106 = fsub float -0.000000e+00, %29
  %107 = fdiv float 1.000000e+00, %106
  %108 = fmul float %105, %107
  %109 = fsub float -0.000000e+00, %45
  %110 = fadd float 1.000000e+00, %109
  %111 = call float @llvm.AMDIL.clamp.(float %110, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %91, float %90, float %99, float %44)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %102, float %108, float %46, float %47)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %38, float %39, float %40, float %111)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %98, float %97, float %50, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %57, float %64, float %86, float %71)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c202015c
7e0a02ff
3e4ccccd
bf8c007f
d2820005
04060a04
7e0c02ff
3d4ccccd
100e0d02
c202815d
bf8c007f
7e100205
d2820008
040a1004
101010ff
3d4ccccd
f800020f
01070508
c0840700
bf8c000f
e00c2000
80020700
bf8c0770
d2060000
0201e107
c2030140
bf8c007f
7e0a5406
10000b00
d2060005
0201e109
c2030141
bf8c007f
0a0a0a06
d206000b
22010006
7e16550b
100a1705
f800021f
04030500
bf8c070f
080004f2
d2060800
02010100
f800022f
00090807
bf8c070f
7e0002ff
3f666666
10000004
d2820000
04080b00
100000ff
3d4ccccd
7e0a02ff
bdcccccd
d2820001
04060a04
c2020152
bf8c007f
10040c04
7e060280
f800023f
03020100
c2020150
bf8c000f
10000c04
08000107
c2020151
bf8c007f
10020c04
08020308
c2020109
bf8c007f
10020204
c2020108
bf8c007f
d2820000
04040900
08020509
c202010a
bf8c007f
d2820000
04000901
c202010b
bf8c007f
06000004
c202010d
bf8c007f
7e020204
d2100001
02020308
c202010c
bf8c007f
7e040204
d2820001
04060507
c202010e
bf8c007f
7e040204
d2820001
04060509
c202010f
bf8c007f
06020204
c2020105
bf8c007f
7e040204
d2100002
02020508
c2020104
bf8c007f
7e060204
d2820002
040a0707
c2020106
bf8c007f
7e060204
d2820002
040a0709
c2020107
bf8c007f
06040404
c2020101
bf8c007f
7e060204
d2100003
02020708
c2020100
bf8c007f
7e080204
d2820003
040e0907
c2020102
bf8c007f
7e080204
d2820003
040e0909
c2000103
bf8c007f
06060600
f80008cf
01000203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL SAMP[4]
DCL SAMP[5]
DCL SAMP[6]
DCL CONST[0..23]
DCL TEMP[0..6], LOCAL
IMM[0] FLT32 {    0.0200,    -1.0000,     0.5000,   120.0000}
IMM[1] FLT32 {    0.9000,     2.1000,     1.8000,     0.4500}
IMM[2] FLT32 {  156.0000,     1.0000,     0.8000,    10.0000}
IMM[3] FLT32 {    0.2000,     2.0000,     5.0000,     0.3000}
IMM[4] FLT32 {    0.0039,     0.1000,     6.2832, -160000.0000}
IMM[5] FLT32 {    0.0000,     0.9000,     3.0000,     2.7215}
IMM[6] FLT32 {   -0.9950,    50.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[1].zwzz
  1: MOV TEMP[0].z, IN[2].xxxx
  2: MUL TEMP[1].x, CONST[23].xxxx, IMM[0].xxxx
  3: MUL TEMP[2].xy, IMM[0].wwww, IN[1].xyyy
  4: MAD TEMP[2].xy, IMM[1].xyyy, TEMP[1].xxxx, TEMP[2].xyyy
  5: MOV TEMP[2].xy, TEMP[2].xyyy
  6: TEX TEMP[2].xyz, TEMP[2], SAMP[3], 2D
  7: ADD TEMP[2].xyz, IMM[0].yyzz, TEMP[2].xyzz
  8: MUL TEMP[3].xy, IMM[2].xxxx, IN[1].xyyy
  9: MAD TEMP[1].xy, IMM[1].zwww, -TEMP[1].xxxx, TEMP[3].xyyy
 10: MOV TEMP[1].xy, TEMP[1].xyyy
 11: TEX TEMP[1].xyz, TEMP[1], SAMP[3], 2D
 12: ADD TEMP[1].xyz, TEMP[2].xyzz, TEMP[1].xyzz
 13: DP3 TEMP[2].x, TEMP[1].xyzz, TEMP[1].xyzz
 14: RSQ TEMP[2].x, TEMP[2].xxxx
 15: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xxxx
 16: ADD TEMP[2].xyz, TEMP[0].xyzz, -CONST[18].xyzz
 17: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
 18: RSQ TEMP[3].x, TEMP[3].xxxx
 19: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx
 20: RCP TEMP[3].x, IN[0].wwww
 21: MUL TEMP[3].xy, IN[0].xyyy, TEMP[3].xxxx
 22: MAD TEMP[3].xy, TEMP[3].xyyy, IMM[0].zzzz, IMM[0].zzzz
 23: MOV TEMP[4].x, TEMP[3].xxxx
 24: ADD TEMP[3].x, IMM[2].yyyy, -TEMP[3].yyyy
 25: MOV TEMP[4].y, TEMP[3].xxxx
 26: ADD TEMP[4].xy, TEMP[4].xyyy, CONST[23].yzzz
 27: DP3_SAT TEMP[3].x, -TEMP[2].xyzz, TEMP[1].xzyy
 28: MUL TEMP[3].x, TEMP[3].xxxx, IMM[0].zzzz
 29: ADD TEMP[3].x, IMM[2].yyyy, -TEMP[3].xxxx
 30: POW TEMP[3].x, TEMP[3].xxxx, IMM[2].wwww
 31: MAD_SAT TEMP[3].x, IMM[2].zzzz, TEMP[3].xxxx, IMM[3].xxxx
 32: ADD TEMP[5].xyz, -CONST[17].xyzz, -TEMP[2].xyzz
 33: DP3 TEMP[6].x, TEMP[1].xzyy, TEMP[2].xyzz
 34: MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[1].xzyy
 35: MUL TEMP[6].xyz, IMM[3].yyyy, TEMP[6].xyzz
 36: ADD TEMP[2].xyz, TEMP[2].xyzz, -TEMP[6].xyzz
 37: MOV TEMP[2].xyz, TEMP[2].xyzz
 38: TEX TEMP[2].xyz, TEMP[2], SAMP[5], CUBE
 39: RCP TEMP[6].x, IN[0].wwww
 40: MUL TEMP[6].x, IN[0].zzzz, TEMP[6].xxxx
 41: MUL TEMP[6].x, TEMP[6].xxxx, IMM[3].zzzz
 42: ADD_SAT TEMP[6].x, IMM[3].zzzz, -TEMP[6].xxxx
 43: MUL TEMP[6].xy, TEMP[1].xyyy, TEMP[6].xxxx
 44: MUL TEMP[6].xy, TEMP[6].xyyy, IMM[3].xxxx
 45: ADD TEMP[4].xy, TEMP[4].xyyy, -TEMP[6].xyyy
 46: MOV TEMP[4].xy, TEMP[4].xyyy
 47: TEX TEMP[4].xyz, TEMP[4], SAMP[1], 2D
 48: MUL TEMP[6].xy, IN[1].xyyy, CONST[16].zwww
 49: MOV TEMP[6].xy, TEMP[6].xyyy
 50: TEX TEMP[6].xyz, TEMP[6], SAMP[4], 2D
 51: LRP TEMP[4].xyz, IMM[3].wwww, TEMP[6].xyzz, TEMP[4].xyzz
 52: ADD TEMP[6].x, IMM[2].yyyy, -TEMP[3].xxxx
 53: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[6].xxxx
 54: MAD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx, TEMP[4].xyzz
 55: ADD TEMP[3].x, IN[1].zzzz, IMM[0].zzzz
 56: RCP TEMP[4].x, CONST[16].xxxx
 57: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 58: ADD TEMP[4].x, IN[2].xxxx, IMM[0].zzzz
 59: RCP TEMP[6].x, CONST[16].yyyy
 60: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[6].xxxx
 61: MOV TEMP[3].y, TEMP[4].xxxx
 62: MOV TEMP[3].xy, TEMP[3].xyyy
 63: TEX TEMP[3].w, TEMP[3], SAMP[6], 2D
 64: ADD TEMP[4].xy, TEMP[0].xzzz, IMM[0].zzzz
 65: MUL TEMP[4].xy, TEMP[4].xyyy, IMM[4].xxxx
 66: MAD TEMP[4].xy, CONST[22].yyyy, IMM[0].xxxx, TEMP[4].xyyy
 67: MOV TEMP[4].xy, TEMP[4].xyyy
 68: TEX TEMP[4].x, TEMP[4], SAMP[2], 2D
 69: MUL TEMP[6].x, CONST[22].yyyy, IMM[4].yyyy
 70: FRC TEMP[6].x, TEMP[6].xxxx
 71: ADD TEMP[4].x, TEMP[4].xxxx, TEMP[6].xxxx
 72: MUL TEMP[4].x, TEMP[4].xxxx, IMM[4].zzzz
 73: SIN TEMP[4].x, TEMP[4].xxxx
 74: MAD TEMP[4].x, TEMP[4].xxxx, IMM[4].yyyy, IMM[0].zzzz
 75: ADD_SAT TEMP[3].x, TEMP[3].wwww, TEMP[4].xxxx
 76: LRP TEMP[3].x, CONST[22].xxxx, TEMP[3].xxxx, IMM[2].yyyy
 77: ADD TEMP[0].xyz, CONST[18].xyzz, -TEMP[0].xyzz
 78: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz
 79: ADD TEMP[4].x, TEMP[4].xxxx, IMM[4].wwww
 80: MUL TEMP[4].x, TEMP[4].xxxx, IMM[5].xxxx
 81: MIN TEMP[4].x, TEMP[4].xxxx, IMM[0].zzzz
 82: MOV_SAT TEMP[4].x, TEMP[4].xxxx
 83: DP3 TEMP[6].x, TEMP[0].xyzz, TEMP[0].xyzz
 84: RSQ TEMP[6].x, TEMP[6].xxxx
 85: MUL TEMP[0].y, TEMP[0].xyzz, TEMP[6].xxxx
 86: ADD TEMP[0].x, IMM[2].yyyy, -TEMP[0].yyyy
 87: MUL TEMP[0].x, TEMP[4].xxxx, TEMP[0].xxxx
 88: LRP TEMP[0].xyz, TEMP[0].xxxx, IMM[0].zzzz, TEMP[2].xyzz
 89: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[3].xxxx
 90: DP3 TEMP[2].x, TEMP[5].xyzz, TEMP[5].xyzz
 91: RSQ TEMP[2].x, TEMP[2].xxxx
 92: MUL TEMP[2].xyz, TEMP[5].xyzz, TEMP[2].xxxx
 93: DP3_SAT TEMP[1].x, TEMP[2].xyzz, TEMP[1].xzyy
 94: MUL TEMP[2].x, CONST[16].xxxx, IMM[5].yyyy
 95: POW TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
 96: MUL_SAT TEMP[1].x, TEMP[1].xxxx, IMM[5].zzzz
 97: MAD_SAT TEMP[0].xyz, TEMP[1].xxxx, TEMP[3].xxxx, TEMP[0].xyzz
 98: MOV TEMP[0].xyz, TEMP[0].xyzx
 99: MUL TEMP[1].xy, IN[1].xyyy, CONST[16].zwww
100: MOV TEMP[1].xy, TEMP[1].xyyy
101: TEX TEMP[1].x, TEMP[1], SAMP[0], 2D
102: MAD TEMP[1].x, TEMP[1].xxxx, IMM[5].wwww, IMM[6].xxxx
103: MUL_SAT TEMP[1].x, TEMP[1].xxxx, IMM[6].yyyy
104: ADD TEMP[1].x, IMM[2].yyyy, -TEMP[1].xxxx
105: MOV TEMP[0].w, TEMP[1].xxxx
106: MOV OUT[0], TEMP[0]
107: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 264)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 268)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 276)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 280)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 368)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 372)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 376)
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %42 = load <32 x i8> addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %46 = load <32 x i8> addrspace(2)* %45, !tbaa !0
  %47 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %50 = load <32 x i8> addrspace(2)* %49, !tbaa !0
  %51 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
  %54 = load <32 x i8> addrspace(2)* %53, !tbaa !0
  %55 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
  %58 = load <32 x i8> addrspace(2)* %57, !tbaa !0
  %59 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
  %61 = getelementptr <32 x i8> addrspace(2)* %2, i32 6
  %62 = load <32 x i8> addrspace(2)* %61, !tbaa !0
  %63 = getelementptr <16 x i8> addrspace(2)* %1, i32 6
  %64 = load <16 x i8> addrspace(2)* %63, !tbaa !0
  %65 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %66 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %67 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %68 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %69 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %70 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %71 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %72 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %73 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %74 = fmul float %34, 0x3F947AE140000000
  %75 = fmul float 1.200000e+02, %69
  %76 = fmul float 1.200000e+02, %70
  %77 = fmul float 0x3FECCCCCE0000000, %74
  %78 = fadd float %77, %75
  %79 = fmul float 0x4000CCCCC0000000, %74
  %80 = fadd float %79, %76
  %81 = bitcast float %78 to i32
  %82 = bitcast float %80 to i32
  %83 = insertelement <2 x i32> undef, i32 %81, i32 0
  %84 = insertelement <2 x i32> %83, i32 %82, i32 1
  %85 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %84, <32 x i8> %50, <16 x i8> %52, i32 2)
  %86 = extractelement <4 x float> %85, i32 0
  %87 = extractelement <4 x float> %85, i32 1
  %88 = extractelement <4 x float> %85, i32 2
  %89 = fadd float -1.000000e+00, %86
  %90 = fadd float -1.000000e+00, %87
  %91 = fadd float 5.000000e-01, %88
  %92 = fmul float 1.560000e+02, %69
  %93 = fmul float 1.560000e+02, %70
  %94 = fsub float -0.000000e+00, %74
  %95 = fmul float 0x3FFCCCCCE0000000, %94
  %96 = fadd float %95, %92
  %97 = fsub float -0.000000e+00, %74
  %98 = fmul float 0x3FDCCCCCE0000000, %97
  %99 = fadd float %98, %93
  %100 = bitcast float %96 to i32
  %101 = bitcast float %99 to i32
  %102 = insertelement <2 x i32> undef, i32 %100, i32 0
  %103 = insertelement <2 x i32> %102, i32 %101, i32 1
  %104 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %103, <32 x i8> %50, <16 x i8> %52, i32 2)
  %105 = extractelement <4 x float> %104, i32 0
  %106 = extractelement <4 x float> %104, i32 1
  %107 = extractelement <4 x float> %104, i32 2
  %108 = fadd float %89, %105
  %109 = fadd float %90, %106
  %110 = fadd float %91, %107
  %111 = fmul float %108, %108
  %112 = fmul float %109, %109
  %113 = fadd float %112, %111
  %114 = fmul float %110, %110
  %115 = fadd float %113, %114
  %116 = call float @llvm.AMDGPU.rsq(float %115)
  %117 = fmul float %108, %116
  %118 = fmul float %109, %116
  %119 = fmul float %110, %116
  %120 = fsub float -0.000000e+00, %29
  %121 = fadd float %71, %120
  %122 = fsub float -0.000000e+00, %30
  %123 = fadd float %72, %122
  %124 = fsub float -0.000000e+00, %31
  %125 = fadd float %73, %124
  %126 = fmul float %121, %121
  %127 = fmul float %123, %123
  %128 = fadd float %127, %126
  %129 = fmul float %125, %125
  %130 = fadd float %128, %129
  %131 = call float @llvm.AMDGPU.rsq(float %130)
  %132 = fmul float %121, %131
  %133 = fmul float %123, %131
  %134 = fmul float %125, %131
  %135 = fdiv float 1.000000e+00, %68
  %136 = fmul float %65, %135
  %137 = fmul float %66, %135
  %138 = fmul float %136, 5.000000e-01
  %139 = fadd float %138, 5.000000e-01
  %140 = fmul float %137, 5.000000e-01
  %141 = fadd float %140, 5.000000e-01
  %142 = fsub float -0.000000e+00, %141
  %143 = fadd float 1.000000e+00, %142
  %144 = fadd float %139, %35
  %145 = fadd float %143, %36
  %146 = fsub float -0.000000e+00, %132
  %147 = fsub float -0.000000e+00, %133
  %148 = fsub float -0.000000e+00, %134
  %149 = fmul float %146, %117
  %150 = fmul float %147, %119
  %151 = fadd float %150, %149
  %152 = fmul float %148, %118
  %153 = fadd float %151, %152
  %154 = call float @llvm.AMDIL.clamp.(float %153, float 0.000000e+00, float 1.000000e+00)
  %155 = fmul float %154, 5.000000e-01
  %156 = fsub float -0.000000e+00, %155
  %157 = fadd float 1.000000e+00, %156
  %158 = call float @llvm.pow.f32(float %157, float 1.000000e+01)
  %159 = fmul float 0x3FE99999A0000000, %158
  %160 = fadd float %159, 0x3FC99999A0000000
  %161 = call float @llvm.AMDIL.clamp.(float %160, float 0.000000e+00, float 1.000000e+00)
  %162 = fsub float -0.000000e+00, %26
  %163 = fsub float -0.000000e+00, %132
  %164 = fadd float %162, %163
  %165 = fsub float -0.000000e+00, %27
  %166 = fsub float -0.000000e+00, %133
  %167 = fadd float %165, %166
  %168 = fsub float -0.000000e+00, %28
  %169 = fsub float -0.000000e+00, %134
  %170 = fadd float %168, %169
  %171 = fmul float %117, %132
  %172 = fmul float %119, %133
  %173 = fadd float %172, %171
  %174 = fmul float %118, %134
  %175 = fadd float %173, %174
  %176 = fmul float %175, %117
  %177 = fmul float %175, %119
  %178 = fmul float %175, %118
  %179 = fmul float 2.000000e+00, %176
  %180 = fmul float 2.000000e+00, %177
  %181 = fmul float 2.000000e+00, %178
  %182 = fsub float -0.000000e+00, %179
  %183 = fadd float %132, %182
  %184 = fsub float -0.000000e+00, %180
  %185 = fadd float %133, %184
  %186 = fsub float -0.000000e+00, %181
  %187 = fadd float %134, %186
  %188 = insertelement <4 x float> undef, float %183, i32 0
  %189 = insertelement <4 x float> %188, float %185, i32 1
  %190 = insertelement <4 x float> %189, float %187, i32 2
  %191 = insertelement <4 x float> %190, float 0.000000e+00, i32 3
  %192 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %191)
  %193 = extractelement <4 x float> %192, i32 0
  %194 = extractelement <4 x float> %192, i32 1
  %195 = extractelement <4 x float> %192, i32 2
  %196 = extractelement <4 x float> %192, i32 3
  %197 = call float @fabs(float %195)
  %198 = fdiv float 1.000000e+00, %197
  %199 = fmul float %193, %198
  %200 = fadd float %199, 1.500000e+00
  %201 = fmul float %194, %198
  %202 = fadd float %201, 1.500000e+00
  %203 = bitcast float %202 to i32
  %204 = bitcast float %200 to i32
  %205 = bitcast float %196 to i32
  %206 = insertelement <4 x i32> undef, i32 %203, i32 0
  %207 = insertelement <4 x i32> %206, i32 %204, i32 1
  %208 = insertelement <4 x i32> %207, i32 %205, i32 2
  %209 = insertelement <4 x i32> %208, i32 undef, i32 3
  %210 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %209, <32 x i8> %58, <16 x i8> %60, i32 4)
  %211 = extractelement <4 x float> %210, i32 0
  %212 = extractelement <4 x float> %210, i32 1
  %213 = extractelement <4 x float> %210, i32 2
  %214 = fdiv float 1.000000e+00, %68
  %215 = fmul float %67, %214
  %216 = fmul float %215, 5.000000e+00
  %217 = fsub float -0.000000e+00, %216
  %218 = fadd float 5.000000e+00, %217
  %219 = call float @llvm.AMDIL.clamp.(float %218, float 0.000000e+00, float 1.000000e+00)
  %220 = fmul float %117, %219
  %221 = fmul float %118, %219
  %222 = fmul float %220, 0x3FC99999A0000000
  %223 = fmul float %221, 0x3FC99999A0000000
  %224 = fsub float -0.000000e+00, %222
  %225 = fadd float %144, %224
  %226 = fsub float -0.000000e+00, %223
  %227 = fadd float %145, %226
  %228 = bitcast float %225 to i32
  %229 = bitcast float %227 to i32
  %230 = insertelement <2 x i32> undef, i32 %228, i32 0
  %231 = insertelement <2 x i32> %230, i32 %229, i32 1
  %232 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %231, <32 x i8> %42, <16 x i8> %44, i32 2)
  %233 = extractelement <4 x float> %232, i32 0
  %234 = extractelement <4 x float> %232, i32 1
  %235 = extractelement <4 x float> %232, i32 2
  %236 = fmul float %69, %24
  %237 = fmul float %70, %25
  %238 = bitcast float %236 to i32
  %239 = bitcast float %237 to i32
  %240 = insertelement <2 x i32> undef, i32 %238, i32 0
  %241 = insertelement <2 x i32> %240, i32 %239, i32 1
  %242 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %241, <32 x i8> %54, <16 x i8> %56, i32 2)
  %243 = extractelement <4 x float> %242, i32 0
  %244 = extractelement <4 x float> %242, i32 1
  %245 = extractelement <4 x float> %242, i32 2
  %246 = call float @llvm.AMDGPU.lrp(float 0x3FD3333340000000, float %243, float %233)
  %247 = call float @llvm.AMDGPU.lrp(float 0x3FD3333340000000, float %244, float %234)
  %248 = call float @llvm.AMDGPU.lrp(float 0x3FD3333340000000, float %245, float %235)
  %249 = fsub float -0.000000e+00, %161
  %250 = fadd float 1.000000e+00, %249
  %251 = fmul float %246, %250
  %252 = fmul float %247, %250
  %253 = fmul float %248, %250
  %254 = fmul float %211, %161
  %255 = fadd float %254, %251
  %256 = fmul float %212, %161
  %257 = fadd float %256, %252
  %258 = fmul float %213, %161
  %259 = fadd float %258, %253
  %260 = fadd float %71, 5.000000e-01
  %261 = fdiv float 1.000000e+00, %22
  %262 = fmul float %260, %261
  %263 = fadd float %73, 5.000000e-01
  %264 = fdiv float 1.000000e+00, %23
  %265 = fmul float %263, %264
  %266 = bitcast float %262 to i32
  %267 = bitcast float %265 to i32
  %268 = insertelement <2 x i32> undef, i32 %266, i32 0
  %269 = insertelement <2 x i32> %268, i32 %267, i32 1
  %270 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %269, <32 x i8> %62, <16 x i8> %64, i32 2)
  %271 = extractelement <4 x float> %270, i32 3
  %272 = fadd float %71, 5.000000e-01
  %273 = fadd float %73, 5.000000e-01
  %274 = fmul float %272, 3.906250e-03
  %275 = fmul float %273, 3.906250e-03
  %276 = fmul float %33, 0x3F947AE140000000
  %277 = fadd float %276, %274
  %278 = fmul float %33, 0x3F947AE140000000
  %279 = fadd float %278, %275
  %280 = bitcast float %277 to i32
  %281 = bitcast float %279 to i32
  %282 = insertelement <2 x i32> undef, i32 %280, i32 0
  %283 = insertelement <2 x i32> %282, i32 %281, i32 1
  %284 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %283, <32 x i8> %46, <16 x i8> %48, i32 2)
  %285 = extractelement <4 x float> %284, i32 0
  %286 = fmul float %33, 0x3FB99999A0000000
  %287 = call float @llvm.AMDIL.fraction.(float %286)
  %288 = fadd float %285, %287
  %289 = fmul float %288, 0x401921FB60000000
  %290 = call float @llvm.sin.f32(float %289)
  %291 = fmul float %290, 0x3FB99999A0000000
  %292 = fadd float %291, 5.000000e-01
  %293 = fadd float %271, %292
  %294 = call float @llvm.AMDIL.clamp.(float %293, float 0.000000e+00, float 1.000000e+00)
  %295 = call float @llvm.AMDGPU.lrp(float %32, float %294, float 1.000000e+00)
  %296 = fsub float -0.000000e+00, %71
  %297 = fadd float %29, %296
  %298 = fsub float -0.000000e+00, %72
  %299 = fadd float %30, %298
  %300 = fsub float -0.000000e+00, %73
  %301 = fadd float %31, %300
  %302 = fmul float %297, %297
  %303 = fmul float %299, %299
  %304 = fadd float %303, %302
  %305 = fmul float %301, %301
  %306 = fadd float %304, %305
  %307 = fadd float %306, -1.600000e+05
  %308 = fmul float %307, 0x3EAA36E2E0000000
  %309 = fcmp uge float %308, 5.000000e-01
  %310 = select i1 %309, float 5.000000e-01, float %308
  %311 = call float @llvm.AMDIL.clamp.(float %310, float 0.000000e+00, float 1.000000e+00)
  %312 = fmul float %297, %297
  %313 = fmul float %299, %299
  %314 = fadd float %313, %312
  %315 = fmul float %301, %301
  %316 = fadd float %314, %315
  %317 = call float @llvm.AMDGPU.rsq(float %316)
  %318 = fmul float %299, %317
  %319 = fsub float -0.000000e+00, %318
  %320 = fadd float 1.000000e+00, %319
  %321 = fmul float %311, %320
  %322 = call float @llvm.AMDGPU.lrp(float %321, float 5.000000e-01, float %255)
  %323 = call float @llvm.AMDGPU.lrp(float %321, float 5.000000e-01, float %257)
  %324 = call float @llvm.AMDGPU.lrp(float %321, float 5.000000e-01, float %259)
  %325 = fmul float %322, %295
  %326 = fmul float %323, %295
  %327 = fmul float %324, %295
  %328 = fmul float %164, %164
  %329 = fmul float %167, %167
  %330 = fadd float %329, %328
  %331 = fmul float %170, %170
  %332 = fadd float %330, %331
  %333 = call float @llvm.AMDGPU.rsq(float %332)
  %334 = fmul float %164, %333
  %335 = fmul float %167, %333
  %336 = fmul float %170, %333
  %337 = fmul float %334, %117
  %338 = fmul float %335, %119
  %339 = fadd float %338, %337
  %340 = fmul float %336, %118
  %341 = fadd float %339, %340
  %342 = call float @llvm.AMDIL.clamp.(float %341, float 0.000000e+00, float 1.000000e+00)
  %343 = fmul float %22, 0x3FECCCCCC0000000
  %344 = call float @llvm.pow.f32(float %342, float %343)
  %345 = fmul float %344, 3.000000e+00
  %346 = call float @llvm.AMDIL.clamp.(float %345, float 0.000000e+00, float 1.000000e+00)
  %347 = fmul float %346, %295
  %348 = fadd float %347, %325
  %349 = fmul float %346, %295
  %350 = fadd float %349, %326
  %351 = fmul float %346, %295
  %352 = fadd float %351, %327
  %353 = call float @llvm.AMDIL.clamp.(float %348, float 0.000000e+00, float 1.000000e+00)
  %354 = call float @llvm.AMDIL.clamp.(float %350, float 0.000000e+00, float 1.000000e+00)
  %355 = call float @llvm.AMDIL.clamp.(float %352, float 0.000000e+00, float 1.000000e+00)
  %356 = fmul float %69, %24
  %357 = fmul float %70, %25
  %358 = bitcast float %356 to i32
  %359 = bitcast float %357 to i32
  %360 = insertelement <2 x i32> undef, i32 %358, i32 0
  %361 = insertelement <2 x i32> %360, i32 %359, i32 1
  %362 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %361, <32 x i8> %38, <16 x i8> %40, i32 2)
  %363 = extractelement <4 x float> %362, i32 0
  %364 = fmul float %363, 0x4005C58860000000
  %365 = fadd float %364, 0xBFEFD70A40000000
  %366 = fmul float %365, 5.000000e+01
  %367 = call float @llvm.AMDIL.clamp.(float %366, float 0.000000e+00, float 1.000000e+00)
  %368 = fsub float -0.000000e+00, %367
  %369 = fadd float 1.000000e+00, %368
  %370 = call i32 @llvm.SI.packf16(float %353, float %354)
  %371 = bitcast i32 %370 to float
  %372 = call i32 @llvm.SI.packf16(float %355, float %369)
  %373 = bitcast i32 %372 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %371, float %373, float %371, float %373)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080500
c8090501
c0840100
bf8c007f
c200095c
7e0602ff
3ca3d70a
bf8c007f
10080600
100a08ff
bee66667
7e0c02ff
431c0000
d2820006
04160d02
c81c0400
c81d0401
10100eff
431c0000
7e1202ff
bca3d70a
10121200
7e1402ff
3fe66667
d2820005
04221509
c086030c
c0c80518
bf8c007f
f0800700
00640805
100a04ff
42f00000
7e0c02ff
40066666
d2820006
04160d04
10160eff
42f00000
7e1802ff
3f666667
d2820005
042e1904
f0800700
00640405
bf8c0770
d206000b
0201e705
0616130b
d206000c
0201e704
0618110c
101a190c
d282000d
0436170b
d2060004
0201e106
06081504
d2820005
04360904
7e0a5b05
10080b04
100c0b0c
c8200700
c8210701
c2000949
bf8c007f
0a121000
c8280600
c8290601
c2008948
bf8c007f
0a181401
101a190c
d282000d
04361309
c8380800
c8390801
c203894a
bf8c007f
0a1e1c07
d282000d
04361f0f
7e1a5b0d
10181b0c
10200d0c
10121b09
d2820011
04421304
100a0b0b
10161b0f
d282000d
04460b0b
101e0b0d
d282000f
043e0b0d
08261f0b
101e090d
d282000f
043e090d
08241f09
101e0d0d
d282000d
043e0d0d
08221b0c
7e280280
d28a0016
044e2511
d28c0015
044e2511
d28e0017
044e2511
d2880018
044e2511
d206010d
02010117
7e1a550d
7e1e02ff
3fc00000
d2820017
043e1b15
d2820016
043e1b16
c0860314
c0c80528
bf8c007f
f0800700
00641116
c8340200
c8350201
c83c0300
c83d0301
7e1e550f
101a1f0d
101a1aff
40a00000
081a1aff
40a00000
d206080d
0201010d
10281b05
102828ff
3e4ccccd
c8540100
c8550101
102a1f15
d2820015
03c1e115
082a2af2
c206095e
bf8c0070
062a2a0c
082a2915
101a1b06
101a1aff
3e4ccccd
c8580000
c8590001
10001f16
d2820000
03c1e100
c203095d
bf8c007f
06000006
08281b00
c0860304
c0c80508
bf8c007f
f0800700
00641414
7e0002ff
3f333333
bf8c0770
10020115
c2030943
bf8c007f
10300406
c2030942
bf8c007f
102e0e06
c0860310
c0c80520
bf8c007f
f0800700
00641917
7e0402ff
3e99999a
bf8c0770
d2820001
0406051a
d2060007
22010109
100e0907
080e2107
101a0b0b
080e1b07
d2060807
02010107
100e0ef0
080e0ef2
7e0e4f07
0e0e0eff
41200000
7e0e4b07
7e1a02ff
3e4ccccd
7e1e02ff
3f4ccccd
d2820007
04361f07
d2060807
02010107
081a0ef2
10021b01
d2820001
04060f12
08101000
081e1401
101e1f0f
d282000f
043e1108
08201c07
d282000f
043e2110
06201eff
c81c4000
102020ff
3551b717
d00c0000
0201e110
d2000010
0001e110
d2060810
02010110
7e1e5b0f
10101f08
081010f2
10101110
081e10f2
1002030f
d2820001
0405e108
061c1cf0
10201cff
3b800000
c2000959
bf8c007f
d282001d
04420600
061414f0
102014ff
3b800000
d282001c
04420600
c0860308
c0c80510
bf8c007f
f0800100
0064031c
7e2002ff
3dcccccd
10382000
7e38411c
bf8c0770
06063903
100606ff
40c90fdb
100606ff
3e22f983
7e066b03
d2820003
03c22103
c2000941
bf8c007f
7e205400
103a210e
c2000940
bf8c007f
7e1c5400
10381d0a
c0860318
c0c80530
bf8c007f
f0800800
00640a1c
bf8c0770
0606070a
d2060803
02010103
c2008958
bf8c007f
d208000a
020002f2
d2820003
042a0601
10020701
c2008945
bf8c007f
d206000a
22010001
0812130a
c2008944
bf8c007f
d206000a
22010001
0814190a
1018150a
d282000c
04321309
c2008946
bf8c007f
d206000e
22010001
0816170e
d282000c
0432170b
7e185b0c
1014190a
100c0d0a
10121909
d2820004
041a0909
100c190b
d2820004
04120b06
d2060804
02010104
7e084f04
7e0a02ff
3f666666
100a0a00
0e080905
7e084b04
100808ff
40400000
d2060804
02010104
d2820001
04060704
d2060801
02010101
100a0114
d2820005
04160519
100a1b05
d2820005
04160f11
100a0b0f
d2820005
0415e108
100a0705
d2820005
04160704
d2060805
02010105
5e020305
10000116
d2820000
0402051b
10001b00
d2820000
04020f13
1000010f
d2820000
0401e108
10000700
d2820000
04020704
d2060800
02010100
c0800300
c0c20500
bf8c007f
f0800100
00010217
7e0602ff
bf7eb852
7e0802ff
402e2c43
bf8c0770
d2820002
040e0902
100404ff
42480000
d2060802
02010102
080404f2
5e000500
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL OUT[3], GENERIC[21]
DCL CONST[0..22]
DCL TEMP[0..5], LOCAL
IMM[0] FLT32 {   19.0000,     1.0000,     0.5000,     0.0000}
  0: MOV TEMP[0].y, IMM[0].xxxx
  1: MOV TEMP[0].x, IN[0].xxxx
  2: MOV TEMP[1].w, IMM[0].yyyy
  3: MOV TEMP[1].x, IN[0].xxxx
  4: MOV TEMP[1].y, IMM[0].xxxx
  5: MOV TEMP[1].z, IN[0].yyyy
  6: DP4 TEMP[2].x, TEMP[1], CONST[0]
  7: DP4 TEMP[3].x, TEMP[1], CONST[1]
  8: MOV TEMP[2].y, TEMP[3].xxxx
  9: DP4 TEMP[4].x, TEMP[1], CONST[2]
 10: MOV TEMP[2].z, TEMP[4].xxxx
 11: DP4 TEMP[1].x, TEMP[1], CONST[3]
 12: MOV TEMP[2].w, TEMP[1].xxxx
 13: MOV TEMP[1].xzw, TEMP[2].xxzw
 14: MOV TEMP[1].y, -TEMP[3].xxxx
 15: ADD TEMP[3].x, IN[0].xxxx, IMM[0].zzzz
 16: RCP TEMP[4].x, CONST[16].xxxx
 17: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 18: ADD TEMP[4].x, IN[0].yyyy, IMM[0].zzzz
 19: ADD TEMP[4].x, TEMP[4].xxxx, -CONST[16].yyyy
 20: RCP TEMP[5].x, -CONST[16].yyyy
 21: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 22: MOV TEMP[3].y, TEMP[4].xxxx
 23: MOV TEMP[0].zw, TEMP[0].yyxy
 24: MOV TEMP[4].x, IN[0].yyyy
 25: MOV TEMP[0].xy, TEMP[3].xyxx
 26: MOV OUT[1], TEMP[1]
 27: MOV OUT[3], TEMP[4]
 28: MOV OUT[0], TEMP[2]
 29: MOV OUT[2], TEMP[0]
 30: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 256)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 260)
  %30 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
  %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %6)
  %33 = extractelement <4 x float> %32, i32 0
  %34 = extractelement <4 x float> %32, i32 1
  %35 = fmul float %33, %12
  %36 = fmul float 1.900000e+01, %13
  %37 = fadd float %35, %36
  %38 = fmul float %34, %14
  %39 = fadd float %37, %38
  %40 = fmul float 1.000000e+00, %15
  %41 = fadd float %39, %40
  %42 = fmul float %33, %16
  %43 = fmul float 1.900000e+01, %17
  %44 = fadd float %42, %43
  %45 = fmul float %34, %18
  %46 = fadd float %44, %45
  %47 = fmul float 1.000000e+00, %19
  %48 = fadd float %46, %47
  %49 = fmul float %33, %20
  %50 = fmul float 1.900000e+01, %21
  %51 = fadd float %49, %50
  %52 = fmul float %34, %22
  %53 = fadd float %51, %52
  %54 = fmul float 1.000000e+00, %23
  %55 = fadd float %53, %54
  %56 = fmul float %33, %24
  %57 = fmul float 1.900000e+01, %25
  %58 = fadd float %56, %57
  %59 = fmul float %34, %26
  %60 = fadd float %58, %59
  %61 = fmul float 1.000000e+00, %27
  %62 = fadd float %60, %61
  %63 = fsub float -0.000000e+00, %48
  %64 = fadd float %33, 5.000000e-01
  %65 = fdiv float 1.000000e+00, %28
  %66 = fmul float %64, %65
  %67 = fadd float %34, 5.000000e-01
  %68 = fsub float -0.000000e+00, %29
  %69 = fadd float %67, %68
  %70 = fsub float -0.000000e+00, %29
  %71 = fdiv float 1.000000e+00, %70
  %72 = fmul float %69, %71
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %41, float %63, float %55, float %62)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %66, float %72, float %33, float 1.900000e+01)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %34, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %41, float %48, float %55, float %62)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0800100
bf8c007f
c202010d
7e0202ff
41980000
bf8c007f
10040204
c0820700
bf8c007f
e00c2000
80010300
c202010c
bf8c0070
7e000204
d2820000
040a0103
c202010e
bf8c007f
7e040204
d2820000
04020504
c202010f
bf8c007f
06000004
c2020109
bf8c007f
10040204
c2020108
bf8c007f
7e0e0204
d2820002
040a0f03
c202010a
bf8c007f
7e0e0204
d2820002
040a0f04
c202010b
bf8c007f
06040404
c2020101
bf8c007f
100e0204
c2020100
bf8c007f
7e100204
d2820007
041e1103
c2020102
bf8c007f
7e100204
d2820007
041e1104
c2020103
bf8c007f
060e0e04
c2020105
bf8c007f
10100204
c2020104
bf8c007f
7e120204
d2820008
04221303
c2020106
bf8c007f
7e120204
d2820008
04221304
c2020107
bf8c007f
06101004
d2060009
22010108
f800020f
00020907
bf8c070f
d2060009
0201e103
c2020140
bf8c007f
7e145404
10121509
d206000a
0201e104
c2000141
bf8c007f
0a141400
d206000b
22010000
7e16550b
1014170a
f800021f
01030a09
bf8c070f
7e020280
f800022f
01010104
f80008cf
00020807
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..22]
DCL TEMP[0..6], LOCAL
IMM[0] FLT32 {    0.5000, -160000.0000,     0.0000,     1.0000}
IMM[1] FLT32 {    0.0200,     0.0039,     0.1000,     6.2832}
  0: MOV TEMP[0].xy, IN[0].zwzz
  1: MOV TEMP[0].z, IN[1].xxxx
  2: MOV TEMP[1].xy, IN[0].xyyy
  3: TEX TEMP[1], TEMP[1], SAMP[0], 2D
  4: MOV TEMP[2].w, TEMP[1].wwww
  5: ADD TEMP[3].xyz, CONST[18].xyzz, -TEMP[0].xyzz
  6: ADD TEMP[4].x, IN[0].zzzz, IMM[0].xxxx
  7: RCP TEMP[5].x, CONST[16].xxxx
  8: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
  9: ADD TEMP[5].x, IN[1].xxxx, IMM[0].xxxx
 10: RCP TEMP[6].x, CONST[16].yyyy
 11: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 12: MOV TEMP[4].y, TEMP[5].xxxx
 13: DP3 TEMP[5].x, TEMP[3].xyzz, TEMP[3].xyzz
 14: ADD TEMP[5].x, TEMP[5].xxxx, IMM[0].yyyy
 15: MUL TEMP[5].x, TEMP[5].xxxx, IMM[0].zzzz
 16: MIN TEMP[5].x, TEMP[5].xxxx, IMM[0].xxxx
 17: MOV_SAT TEMP[5].x, TEMP[5].xxxx
 18: DP3 TEMP[6].x, TEMP[3].xyzz, TEMP[3].xyzz
 19: RSQ TEMP[6].x, TEMP[6].xxxx
 20: MUL TEMP[3].y, TEMP[3].xyzz, TEMP[6].xxxx
 21: ADD TEMP[3].x, IMM[0].wwww, -TEMP[3].yyyy
 22: MUL TEMP[3].x, TEMP[5].xxxx, TEMP[3].xxxx
 23: LRP TEMP[1].xyz, TEMP[3].xxxx, IMM[0].xxxx, TEMP[1].xyzz
 24: MOV TEMP[3].xy, TEMP[4].xyyy
 25: TEX TEMP[3].w, TEMP[3], SAMP[2], 2D
 26: ADD TEMP[0].xy, TEMP[0].xzzz, IMM[0].xxxx
 27: MUL TEMP[0].xy, TEMP[0].xyyy, IMM[1].yyyy
 28: MAD TEMP[0].xy, CONST[22].yyyy, IMM[1].xxxx, TEMP[0].xyyy
 29: MOV TEMP[0].xy, TEMP[0].xyyy
 30: TEX TEMP[0].x, TEMP[0], SAMP[1], 2D
 31: MUL TEMP[4].x, CONST[22].yyyy, IMM[1].zzzz
 32: FRC TEMP[4].x, TEMP[4].xxxx
 33: ADD TEMP[0].x, TEMP[0].xxxx, TEMP[4].xxxx
 34: MUL TEMP[0].x, TEMP[0].xxxx, IMM[1].wwww
 35: SIN TEMP[0].x, TEMP[0].xxxx
 36: MAD TEMP[0].x, TEMP[0].xxxx, IMM[1].zzzz, IMM[0].xxxx
 37: ADD_SAT TEMP[0].x, TEMP[3].wwww, TEMP[0].xxxx
 38: LRP TEMP[0].x, CONST[22].xxxx, TEMP[0].xxxx, IMM[0].wwww
 39: MUL TEMP[2].xyz, TEMP[1].xyzz, TEMP[0].xxxx
 40: MOV OUT[0], TEMP[2]
 41: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %29 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %30 = load <32 x i8> addrspace(2)* %29, !tbaa !0
  %31 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0
  %35 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %43 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %44 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %45 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %46 = bitcast float %41 to i32
  %47 = bitcast float %42 to i32
  %48 = insertelement <2 x i32> undef, i32 %46, i32 0
  %49 = insertelement <2 x i32> %48, i32 %47, i32 1
  %50 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %49, <32 x i8> %30, <16 x i8> %32, i32 2)
  %51 = extractelement <4 x float> %50, i32 0
  %52 = extractelement <4 x float> %50, i32 1
  %53 = extractelement <4 x float> %50, i32 2
  %54 = extractelement <4 x float> %50, i32 3
  %55 = fsub float -0.000000e+00, %43
  %56 = fadd float %24, %55
  %57 = fsub float -0.000000e+00, %44
  %58 = fadd float %25, %57
  %59 = fsub float -0.000000e+00, %45
  %60 = fadd float %26, %59
  %61 = fadd float %43, 5.000000e-01
  %62 = fdiv float 1.000000e+00, %22
  %63 = fmul float %61, %62
  %64 = fadd float %45, 5.000000e-01
  %65 = fdiv float 1.000000e+00, %23
  %66 = fmul float %64, %65
  %67 = fmul float %56, %56
  %68 = fmul float %58, %58
  %69 = fadd float %68, %67
  %70 = fmul float %60, %60
  %71 = fadd float %69, %70
  %72 = fadd float %71, -1.600000e+05
  %73 = fmul float %72, 0x3EAA36E2E0000000
  %74 = fcmp uge float %73, 5.000000e-01
  %75 = select i1 %74, float 5.000000e-01, float %73
  %76 = call float @llvm.AMDIL.clamp.(float %75, float 0.000000e+00, float 1.000000e+00)
  %77 = fmul float %56, %56
  %78 = fmul float %58, %58
  %79 = fadd float %78, %77
  %80 = fmul float %60, %60
  %81 = fadd float %79, %80
  %82 = call float @llvm.AMDGPU.rsq(float %81)
  %83 = fmul float %58, %82
  %84 = fsub float -0.000000e+00, %83
  %85 = fadd float 1.000000e+00, %84
  %86 = fmul float %76, %85
  %87 = call float @llvm.AMDGPU.lrp(float %86, float 5.000000e-01, float %51)
  %88 = call float @llvm.AMDGPU.lrp(float %86, float 5.000000e-01, float %52)
  %89 = call float @llvm.AMDGPU.lrp(float %86, float 5.000000e-01, float %53)
  %90 = bitcast float %63 to i32
  %91 = bitcast float %66 to i32
  %92 = insertelement <2 x i32> undef, i32 %90, i32 0
  %93 = insertelement <2 x i32> %92, i32 %91, i32 1
  %94 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %93, <32 x i8> %38, <16 x i8> %40, i32 2)
  %95 = extractelement <4 x float> %94, i32 3
  %96 = fadd float %43, 5.000000e-01
  %97 = fadd float %45, 5.000000e-01
  %98 = fmul float %96, 3.906250e-03
  %99 = fmul float %97, 3.906250e-03
  %100 = fmul float %28, 0x3F947AE140000000
  %101 = fadd float %100, %98
  %102 = fmul float %28, 0x3F947AE140000000
  %103 = fadd float %102, %99
  %104 = bitcast float %101 to i32
  %105 = bitcast float %103 to i32
  %106 = insertelement <2 x i32> undef, i32 %104, i32 0
  %107 = insertelement <2 x i32> %106, i32 %105, i32 1
  %108 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %107, <32 x i8> %34, <16 x i8> %36, i32 2)
  %109 = extractelement <4 x float> %108, i32 0
  %110 = fmul float %28, 0x3FB99999A0000000
  %111 = call float @llvm.AMDIL.fraction.(float %110)
  %112 = fadd float %109, %111
  %113 = fmul float %112, 0x401921FB60000000
  %114 = call float @llvm.sin.f32(float %113)
  %115 = fmul float %114, 0x3FB99999A0000000
  %116 = fadd float %115, 5.000000e-01
  %117 = fadd float %95, %116
  %118 = call float @llvm.AMDIL.clamp.(float %117, float 0.000000e+00, float 1.000000e+00)
  %119 = call float @llvm.AMDGPU.lrp(float %27, float %118, float 1.000000e+00)
  %120 = fmul float %87, %119
  %121 = fmul float %88, %119
  %122 = fmul float %89, %119
  %123 = call i32 @llvm.SI.packf16(float %120, float %121)
  %124 = bitcast i32 %123 to float
  %125 = call i32 @llvm.SI.packf16(float %122, float %54)
  %126 = bitcast i32 %125 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %124, float %126, float %124, float %126)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080300
c8090301
c0840100
bf8c007f
c2000949
bf8c007f
08040400
c80c0200
c80d0201
c2000948
bf8c007f
08080600
10080904
d2820004
04120502
c8140400
c8150401
c200094a
bf8c007f
080c0a00
d2820004
04120d06
060c08ff
c81c4000
100c0cff
3551b717
d00c0000
0201e106
d2000006
0001e106
d2060806
02010106
7e085b04
10040902
080404f2
10040506
080804f2
c81c0100
c81d0101
c8180000
c8190001
c0860300
c0c80500
bf8c007f
f0800f00
00640606
bf8c0770
10000f04
d2820000
0401e102
06020af0
100a02ff
3b800000
c2000959
7e1402ff
3ca3d70a
bf8c007f
d282000c
04161400
060606f0
100a06ff
3b800000
d282000b
04161400
c0860304
c0c80508
bf8c007f
f0800100
0064050b
7e1402ff
3dcccccd
10161400
7e16410b
bf8c0770
060a1705
100a0aff
40c90fdb
100a0aff
3e22f983
7e0a6b05
d2820005
03c21505
c2000941
bf8c007f
7e145400
10161501
c2000940
bf8c007f
7e025400
10140303
c0800308
c0c60510
bf8c007f
f0800800
0003010a
bf8c0770
06020b01
d2060801
02010101
c2000958
bf8c007f
d2080003
020000f2
d2820001
040e0200
10000300
10060d04
d2820003
040de102
10060303
5e000103
10061104
d2820002
040de102
10020302
5e021301
f8001c0f
01000100
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..22]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0100,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xz, IN[0].xyzx
  2: MOV TEMP[0].xzw, TEMP[0].xxzw
  3: ADD TEMP[1].x, IN[0].yyyy, IMM[0].xxxx
  4: MOV TEMP[0].y, TEMP[1].xxxx
  5: DP4 TEMP[1].x, TEMP[0], CONST[0]
  6: DP4 TEMP[2].x, TEMP[0], CONST[1]
  7: MOV TEMP[1].y, TEMP[2].xxxx
  8: DP4 TEMP[2].x, TEMP[0], CONST[3]
  9: MOV TEMP[1].w, TEMP[2].xxxx
 10: MOV TEMP[1].xyw, TEMP[1].xyxw
 11: MOV TEMP[2].w, IMM[0].yyyy
 12: MUL TEMP[2].xyz, CONST[20].xyzz, IMM[0].zzzz
 13: ADD TEMP[2], TEMP[0], -TEMP[2]
 14: DP4 TEMP[2].x, TEMP[2], CONST[2]
 15: MOV TEMP[1].z, TEMP[2].xxxx
 16: MOV TEMP[2].xy, IN[1].xyxx
 17: MOV TEMP[2].zw, TEMP[0].yyxy
 18: MOV TEMP[0].x, TEMP[0].zzzz
 19: MOV OUT[0], TEMP[1]
 20: MOV OUT[2], TEMP[0]
 21: MOV OUT[1], TEMP[2]
 22: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 320)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 324)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 328)
  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %6)
  %34 = extractelement <4 x float> %33, i32 0
  %35 = extractelement <4 x float> %33, i32 1
  %36 = extractelement <4 x float> %33, i32 2
  %37 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
  %39 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %6)
  %40 = extractelement <4 x float> %39, i32 0
  %41 = extractelement <4 x float> %39, i32 1
  %42 = fadd float %35, 1.000000e+00
  %43 = fmul float %34, %12
  %44 = fmul float %42, %13
  %45 = fadd float %43, %44
  %46 = fmul float %36, %14
  %47 = fadd float %45, %46
  %48 = fmul float 1.000000e+00, %15
  %49 = fadd float %47, %48
  %50 = fmul float %34, %16
  %51 = fmul float %42, %17
  %52 = fadd float %50, %51
  %53 = fmul float %36, %18
  %54 = fadd float %52, %53
  %55 = fmul float 1.000000e+00, %19
  %56 = fadd float %54, %55
  %57 = fmul float %34, %24
  %58 = fmul float %42, %25
  %59 = fadd float %57, %58
  %60 = fmul float %36, %26
  %61 = fadd float %59, %60
  %62 = fmul float 1.000000e+00, %27
  %63 = fadd float %61, %62
  %64 = fmul float %28, 0x3F847AE140000000
  %65 = fmul float %29, 0x3F847AE140000000
  %66 = fmul float %30, 0x3F847AE140000000
  %67 = fsub float -0.000000e+00, %64
  %68 = fadd float %34, %67
  %69 = fsub float -0.000000e+00, %65
  %70 = fadd float %42, %69
  %71 = fsub float -0.000000e+00, %66
  %72 = fadd float %36, %71
  %73 = fsub float -0.000000e+00, 0.000000e+00
  %74 = fadd float 1.000000e+00, %73
  %75 = fmul float %68, %20
  %76 = fmul float %70, %21
  %77 = fadd float %75, %76
  %78 = fmul float %72, %22
  %79 = fadd float %77, %78
  %80 = fmul float %74, %23
  %81 = fadd float %79, %80
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %40, float %41, float %34, float %42)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %36, float %42, float %36, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %49, float %56, float %81, float %63)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840700
bf8c007f
e00c2000
80020100
c0820704
bf8c0070
e00c2000
80010500
d2060000
0201e502
bf8c0770
f800020f
00010605
bf8c070f
7e0a02f2
f800021f
05030003
c0800100
bf8c000f
c2020150
7e0a02ff
3c23d70a
bf8c007f
100c0a04
080c0d01
c2020151
bf8c007f
100e0a04
080e0f00
c2020109
bf8c007f
100e0e04
c2020108
bf8c007f
d2820006
041c0906
c2020152
bf8c007f
100a0a04
080a0b03
c202010a
bf8c007f
d2820005
04180905
c202010b
bf8c007f
060a0a04
c202010d
bf8c007f
100c0004
c202010c
bf8c007f
7e0e0204
d2820006
041a0f01
c202010e
bf8c007f
7e0e0204
d2820006
041a0f03
c202010f
bf8c007f
060c0c04
c2020105
bf8c007f
100e0004
c2020104
bf8c007f
7e100204
d2820007
041e1101
c2020106
bf8c007f
7e100204
d2820007
041e1103
c2020107
bf8c007f
060e0e04
c2020101
bf8c007f
10000004
c2020100
bf8c007f
7e100204
d2820000
04021101
c2020102
bf8c007f
7e100204
d2820000
04021103
c2000103
bf8c007f
06000000
f80008cf
06050700
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..31]
DCL TEMP[0..7], LOCAL
IMM[0] FLT32 {    0.5000,     0.8000,     0.2000,     1.2000}
IMM[1] FLT32 {    1.0000,     0.0200,     0.0039,     0.1000}
IMM[2] FLT32 {    6.2832, -160000.0000,     0.0000,   200.0000}
IMM[3] FLT32 {    3.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].zwzz
  1: MOV TEMP[0].z, IN[1].xxxx
  2: MOV TEMP[1].xy, IN[0].xyyy
  3: TEX TEMP[1], TEMP[1], SAMP[1], 2D
  4: MOV TEMP[2].w, TEMP[1].wwww
  5: MOV TEMP[3].xy, IN[0].xyyy
  6: TEX TEMP[3], TEMP[3], SAMP[0], 2D
  7: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz
  8: RSQ TEMP[4].x, TEMP[4].xxxx
  9: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[4].xxxx
 10: MUL TEMP[4].xyz, TEMP[3].xxxx, CONST[28].xyzz
 11: MUL TEMP[4].xyz, TEMP[1].xyzz, TEMP[4].xyzz
 12: LRP TEMP[1].xyz, TEMP[3].xxxx, TEMP[4].xyzz, TEMP[1].xyzz
 13: MUL TEMP[4].xyz, TEMP[3].yyyy, CONST[29].xyzz
 14: MUL TEMP[4].xyz, TEMP[1].xyzz, TEMP[4].xyzz
 15: LRP TEMP[1].xyz, TEMP[3].yyyy, TEMP[4].xyzz, TEMP[1].xyzz
 16: MUL TEMP[4].xyz, TEMP[3].zzzz, CONST[30].xyzz
 17: MUL TEMP[4].xyz, TEMP[1].xyzz, TEMP[4].xyzz
 18: LRP TEMP[2].xyz, TEMP[3].zzzz, TEMP[4].xyzz, TEMP[1].xyzz
 19: DP3 TEMP[1].x, TEMP[0].xyzz, -CONST[17].xyzz
 20: MAD TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx, IMM[0].xxxx
 21: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 22: MAD TEMP[1].x, IMM[0].yyyy, TEMP[1].xxxx, IMM[0].zzzz
 23: MUL TEMP[1].xyz, TEMP[1].xxxx, TEMP[2].xyzz
 24: MUL_SAT TEMP[1].xyz, TEMP[1].xyzz, IMM[0].wwww
 25: ADD TEMP[4].x, IN[1].yyyy, IMM[0].xxxx
 26: RCP TEMP[5].x, CONST[16].xxxx
 27: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 28: ADD TEMP[5].x, IN[1].wwww, IMM[0].xxxx
 29: RCP TEMP[6].x, CONST[16].yyyy
 30: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 31: MOV TEMP[4].y, TEMP[5].xxxx
 32: MOV TEMP[4].xy, TEMP[4].xyyy
 33: TEX TEMP[4].w, TEMP[4], SAMP[3], 2D
 34: ADD TEMP[5].xy, IN[1].ywww, IMM[0].xxxx
 35: MUL TEMP[5].xy, TEMP[5].xyyy, IMM[1].zzzz
 36: MAD TEMP[5].xy, CONST[22].yyyy, IMM[1].yyyy, TEMP[5].xyyy
 37: MOV TEMP[5].xy, TEMP[5].xyyy
 38: TEX TEMP[5].x, TEMP[5], SAMP[2], 2D
 39: MUL TEMP[6].x, CONST[22].yyyy, IMM[1].wwww
 40: FRC TEMP[6].x, TEMP[6].xxxx
 41: ADD TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 42: MUL TEMP[5].x, TEMP[5].xxxx, IMM[2].xxxx
 43: SIN TEMP[5].x, TEMP[5].xxxx
 44: MAD TEMP[5].x, TEMP[5].xxxx, IMM[1].wwww, IMM[0].xxxx
 45: ADD_SAT TEMP[4].x, TEMP[4].wwww, TEMP[5].xxxx
 46: LRP TEMP[4].x, CONST[22].xxxx, TEMP[4].xxxx, IMM[1].xxxx
 47: ADD TEMP[5].xyz, CONST[18].xyzz, -IN[1].yzww
 48: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
 49: ADD TEMP[6].x, TEMP[6].xxxx, IMM[2].yyyy
 50: MUL TEMP[6].x, TEMP[6].xxxx, IMM[2].zzzz
 51: MIN TEMP[6].x, TEMP[6].xxxx, IMM[0].xxxx
 52: MOV_SAT TEMP[6].x, TEMP[6].xxxx
 53: DP3 TEMP[7].x, TEMP[5].xyzz, TEMP[5].xyzz
 54: RSQ TEMP[7].x, TEMP[7].xxxx
 55: MUL TEMP[5].y, TEMP[5].xyzz, TEMP[7].xxxx
 56: ADD TEMP[5].x, IMM[1].xxxx, -TEMP[5].yyyy
 57: MUL TEMP[5].x, TEMP[6].xxxx, TEMP[5].xxxx
 58: LRP TEMP[1].xyz, TEMP[5].xxxx, IMM[0].xxxx, TEMP[1].xyzz
 59: MUL TEMP[2].xyz, TEMP[1].xyzz, TEMP[4].xxxx
 60: ADD TEMP[1].xyz, IN[1].yzww, -CONST[18].xyzz
 61: DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[1].xyzz
 62: RSQ TEMP[5].x, TEMP[5].xxxx
 63: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[5].xxxx
 64: ADD TEMP[1].xyz, -TEMP[1].xyzz, -CONST[17].xyzz
 65: DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[1].xyzz
 66: RSQ TEMP[5].x, TEMP[5].xxxx
 67: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[5].xxxx
 68: DP3_SAT TEMP[0].x, TEMP[1].xyzz, TEMP[0].xyzz
 69: POW TEMP[0].x, TEMP[0].xxxx, IMM[2].wwww
 70: MUL_SAT TEMP[0].x, TEMP[0].xxxx, IMM[3].xxxx
 71: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[3].wwww
 72: MAD_SAT TEMP[0].xyz, TEMP[0].xxxx, TEMP[4].xxxx, TEMP[2].xyzz
 73: MOV TEMP[2].xyz, TEMP[0].xyzx
 74: MOV OUT[0], TEMP[2]
 75: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 276)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 280)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 448)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 452)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 456)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 484)
  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 488)
  %41 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %42 = load <32 x i8> addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %46 = load <32 x i8> addrspace(2)* %45, !tbaa !0
  %47 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %50 = load <32 x i8> addrspace(2)* %49, !tbaa !0
  %51 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %54 = load <32 x i8> addrspace(2)* %53, !tbaa !0
  %55 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %59 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %60 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %61 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %62 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %63 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %64 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %65 = bitcast float %57 to i32
  %66 = bitcast float %58 to i32
  %67 = insertelement <2 x i32> undef, i32 %65, i32 0
  %68 = insertelement <2 x i32> %67, i32 %66, i32 1
  %69 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %68, <32 x i8> %46, <16 x i8> %48, i32 2)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = extractelement <4 x float> %69, i32 2
  %73 = extractelement <4 x float> %69, i32 3
  %74 = bitcast float %57 to i32
  %75 = bitcast float %58 to i32
  %76 = insertelement <2 x i32> undef, i32 %74, i32 0
  %77 = insertelement <2 x i32> %76, i32 %75, i32 1
  %78 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %77, <32 x i8> %42, <16 x i8> %44, i32 2)
  %79 = extractelement <4 x float> %78, i32 0
  %80 = extractelement <4 x float> %78, i32 1
  %81 = extractelement <4 x float> %78, i32 2
  %82 = extractelement <4 x float> %78, i32 3
  %83 = fmul float %59, %59
  %84 = fmul float %60, %60
  %85 = fadd float %84, %83
  %86 = fmul float %61, %61
  %87 = fadd float %85, %86
  %88 = call float @llvm.AMDGPU.rsq(float %87)
  %89 = fmul float %59, %88
  %90 = fmul float %60, %88
  %91 = fmul float %61, %88
  %92 = fmul float %79, %32
  %93 = fmul float %79, %33
  %94 = fmul float %79, %34
  %95 = fmul float %70, %92
  %96 = fmul float %71, %93
  %97 = fmul float %72, %94
  %98 = call float @llvm.AMDGPU.lrp(float %79, float %95, float %70)
  %99 = call float @llvm.AMDGPU.lrp(float %79, float %96, float %71)
  %100 = call float @llvm.AMDGPU.lrp(float %79, float %97, float %72)
  %101 = fmul float %80, %35
  %102 = fmul float %80, %36
  %103 = fmul float %80, %37
  %104 = fmul float %98, %101
  %105 = fmul float %99, %102
  %106 = fmul float %100, %103
  %107 = call float @llvm.AMDGPU.lrp(float %80, float %104, float %98)
  %108 = call float @llvm.AMDGPU.lrp(float %80, float %105, float %99)
  %109 = call float @llvm.AMDGPU.lrp(float %80, float %106, float %100)
  %110 = fmul float %81, %38
  %111 = fmul float %81, %39
  %112 = fmul float %81, %40
  %113 = fmul float %107, %110
  %114 = fmul float %108, %111
  %115 = fmul float %109, %112
  %116 = call float @llvm.AMDGPU.lrp(float %81, float %113, float %107)
  %117 = call float @llvm.AMDGPU.lrp(float %81, float %114, float %108)
  %118 = call float @llvm.AMDGPU.lrp(float %81, float %115, float %109)
  %119 = fsub float -0.000000e+00, %24
  %120 = fsub float -0.000000e+00, %25
  %121 = fsub float -0.000000e+00, %26
  %122 = fmul float %89, %119
  %123 = fmul float %90, %120
  %124 = fadd float %123, %122
  %125 = fmul float %91, %121
  %126 = fadd float %124, %125
  %127 = fmul float %126, 5.000000e-01
  %128 = fadd float %127, 5.000000e-01
  %129 = fmul float %128, %128
  %130 = fmul float 0x3FE99999A0000000, %129
  %131 = fadd float %130, 0x3FC99999A0000000
  %132 = fmul float %131, %116
  %133 = fmul float %131, %117
  %134 = fmul float %131, %118
  %135 = fmul float %132, 0x3FF3333340000000
  %136 = fmul float %133, 0x3FF3333340000000
  %137 = fmul float %134, 0x3FF3333340000000
  %138 = call float @llvm.AMDIL.clamp.(float %135, float 0.000000e+00, float 1.000000e+00)
  %139 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
  %140 = call float @llvm.AMDIL.clamp.(float %137, float 0.000000e+00, float 1.000000e+00)
  %141 = fadd float %62, 5.000000e-01
  %142 = fdiv float 1.000000e+00, %22
  %143 = fmul float %141, %142
  %144 = fadd float %64, 5.000000e-01
  %145 = fdiv float 1.000000e+00, %23
  %146 = fmul float %144, %145
  %147 = bitcast float %143 to i32
  %148 = bitcast float %146 to i32
  %149 = insertelement <2 x i32> undef, i32 %147, i32 0
  %150 = insertelement <2 x i32> %149, i32 %148, i32 1
  %151 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %150, <32 x i8> %54, <16 x i8> %56, i32 2)
  %152 = extractelement <4 x float> %151, i32 3
  %153 = fadd float %62, 5.000000e-01
  %154 = fadd float %64, 5.000000e-01
  %155 = fmul float %153, 3.906250e-03
  %156 = fmul float %154, 3.906250e-03
  %157 = fmul float %31, 0x3F947AE140000000
  %158 = fadd float %157, %155
  %159 = fmul float %31, 0x3F947AE140000000
  %160 = fadd float %159, %156
  %161 = bitcast float %158 to i32
  %162 = bitcast float %160 to i32
  %163 = insertelement <2 x i32> undef, i32 %161, i32 0
  %164 = insertelement <2 x i32> %163, i32 %162, i32 1
  %165 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %164, <32 x i8> %50, <16 x i8> %52, i32 2)
  %166 = extractelement <4 x float> %165, i32 0
  %167 = fmul float %31, 0x3FB99999A0000000
  %168 = call float @llvm.AMDIL.fraction.(float %167)
  %169 = fadd float %166, %168
  %170 = fmul float %169, 0x401921FB60000000
  %171 = call float @llvm.sin.f32(float %170)
  %172 = fmul float %171, 0x3FB99999A0000000
  %173 = fadd float %172, 5.000000e-01
  %174 = fadd float %152, %173
  %175 = call float @llvm.AMDIL.clamp.(float %174, float 0.000000e+00, float 1.000000e+00)
  %176 = call float @llvm.AMDGPU.lrp(float %30, float %175, float 1.000000e+00)
  %177 = fsub float -0.000000e+00, %62
  %178 = fadd float %27, %177
  %179 = fsub float -0.000000e+00, %63
  %180 = fadd float %28, %179
  %181 = fsub float -0.000000e+00, %64
  %182 = fadd float %29, %181
  %183 = fmul float %178, %178
  %184 = fmul float %180, %180
  %185 = fadd float %184, %183
  %186 = fmul float %182, %182
  %187 = fadd float %185, %186
  %188 = fadd float %187, -1.600000e+05
  %189 = fmul float %188, 0x3EAA36E2E0000000
  %190 = fcmp uge float %189, 5.000000e-01
  %191 = select i1 %190, float 5.000000e-01, float %189
  %192 = call float @llvm.AMDIL.clamp.(float %191, float 0.000000e+00, float 1.000000e+00)
  %193 = fmul float %178, %178
  %194 = fmul float %180, %180
  %195 = fadd float %194, %193
  %196 = fmul float %182, %182
  %197 = fadd float %195, %196
  %198 = call float @llvm.AMDGPU.rsq(float %197)
  %199 = fmul float %180, %198
  %200 = fsub float -0.000000e+00, %199
  %201 = fadd float 1.000000e+00, %200
  %202 = fmul float %192, %201
  %203 = call float @llvm.AMDGPU.lrp(float %202, float 5.000000e-01, float %138)
  %204 = call float @llvm.AMDGPU.lrp(float %202, float 5.000000e-01, float %139)
  %205 = call float @llvm.AMDGPU.lrp(float %202, float 5.000000e-01, float %140)
  %206 = fmul float %203, %176
  %207 = fmul float %204, %176
  %208 = fmul float %205, %176
  %209 = fsub float -0.000000e+00, %27
  %210 = fadd float %62, %209
  %211 = fsub float -0.000000e+00, %28
  %212 = fadd float %63, %211
  %213 = fsub float -0.000000e+00, %29
  %214 = fadd float %64, %213
  %215 = fmul float %210, %210
  %216 = fmul float %212, %212
  %217 = fadd float %216, %215
  %218 = fmul float %214, %214
  %219 = fadd float %217, %218
  %220 = call float @llvm.AMDGPU.rsq(float %219)
  %221 = fmul float %210, %220
  %222 = fmul float %212, %220
  %223 = fmul float %214, %220
  %224 = fsub float -0.000000e+00, %221
  %225 = fsub float -0.000000e+00, %24
  %226 = fadd float %224, %225
  %227 = fsub float -0.000000e+00, %222
  %228 = fsub float -0.000000e+00, %25
  %229 = fadd float %227, %228
  %230 = fsub float -0.000000e+00, %223
  %231 = fsub float -0.000000e+00, %26
  %232 = fadd float %230, %231
  %233 = fmul float %226, %226
  %234 = fmul float %229, %229
  %235 = fadd float %234, %233
  %236 = fmul float %232, %232
  %237 = fadd float %235, %236
  %238 = call float @llvm.AMDGPU.rsq(float %237)
  %239 = fmul float %226, %238
  %240 = fmul float %229, %238
  %241 = fmul float %232, %238
  %242 = fmul float %239, %89
  %243 = fmul float %240, %90
  %244 = fadd float %243, %242
  %245 = fmul float %241, %91
  %246 = fadd float %244, %245
  %247 = call float @llvm.AMDIL.clamp.(float %246, float 0.000000e+00, float 1.000000e+00)
  %248 = call float @llvm.pow.f32(float %247, float 2.000000e+02)
  %249 = fmul float %248, 3.000000e+00
  %250 = call float @llvm.AMDIL.clamp.(float %249, float 0.000000e+00, float 1.000000e+00)
  %251 = fmul float %250, %82
  %252 = fmul float %251, %176
  %253 = fadd float %252, %206
  %254 = fmul float %251, %176
  %255 = fadd float %254, %207
  %256 = fmul float %251, %176
  %257 = fadd float %256, %208
  %258 = call float @llvm.AMDIL.clamp.(float %253, float 0.000000e+00, float 1.000000e+00)
  %259 = call float @llvm.AMDIL.clamp.(float %255, float 0.000000e+00, float 1.000000e+00)
  %260 = call float @llvm.AMDIL.clamp.(float %257, float 0.000000e+00, float 1.000000e+00)
  %261 = call i32 @llvm.SI.packf16(float %258, float %259)
  %262 = bitcast i32 %261 to float
  %263 = call i32 @llvm.SI.packf16(float %260, float %73)
  %264 = bitcast i32 %263 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %262, float %264, float %262, float %264)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840304
c0c60508
bf8c007f
f0800f00
00430402
c0840300
c0c60500
bf8c0070
f0800f00
00430802
bf8c0770
080410f2
10060b02
c0840100
bf8c007f
c2000971
bf8c007f
7e180200
d210000c
02021908
10181905
d2820003
040e1908
081812f2
101a070c
c2000975
bf8c007f
7e1c0200
d210000e
02021d09
10061d03
d2820003
04360709
081a14f2
101c070d
c2000979
bf8c007f
7e1e0200
d210000f
02021f0a
10061f03
d2820003
043a070a
c8380300
c8390301
c83c0200
c83d0201
10201f0f
d2820010
04421d0e
c8440400
c8450401
d2820010
04422311
7e205b10
101e210f
c2000944
bf8c007f
10241e00
101c210e
c2008945
bf8c007f
d2060013
22010001
1026270e
08242513
10202111
c2038946
bf8c007f
10222007
08222312
d2820011
03c1e111
10222311
7e2402ff
3e4ccccd
7e2602ff
3f4ccccd
d2820011
044a2711
10060711
100606ff
3f99999a
d2060803
02010103
c8480600
c8490601
c2060949
bf8c007f
0826240c
c8500500
c8510501
c2068948
bf8c007f
082a280d
102a2b15
d2820015
04562713
c8580700
c8590701
c203094a
bf8c007f
08002c06
d2820000
04560100
060200ff
c81c4000
100202ff
3551b717
d00c000e
0201e101
d2000001
0039e101
d2060801
02010101
7e005b00
10000113
080000f2
10000101
080200f2
10060701
d2820003
040de100
06262cf0
102a26ff
3b800000
c2070959
7e2e02ff
3ca3d70a
bf8c007f
d2820019
04562e0e
062a28f0
10342aff
3b800000
d2820018
046a2e0e
c0880308
c0ca0510
bf8c007f
f0800100
00851718
7e3002ff
3dcccccd
1032300e
7e324119
bf8c0770
062e3317
102e2eff
40c90fdb
102e2eff
3e22f983
7e2e6b17
d2820017
03c23117
c2070941
bf8c007f
7e30540e
10323113
c2070940
bf8c007f
7e26540e
10302715
c088030c
c0ca0518
bf8c007f
f0800800
00851318
bf8c0770
06262f13
d2060813
02010113
c2010958
bf8c007f
d2080015
020004f2
d2820013
04562602
10062703
0a24240c
0a28280d
102a2914
d2820015
04562512
0a2c2c06
d2820015
04562d16
7e2a5b15
10242b12
d2060012
22010112
0a242401
10282b14
d2060014
22010114
0a282800
102e2914
d2820017
045e2512
102a2b16
d2060015
22010115
0a2a2a07
d2820016
045e2b15
7e2c5b16
10242d12
10282d14
101e1f14
d282000e
043e1d12
101e2d15
d282000e
043a210f
d206080e
0201010e
7e1c4f0e
0e1c1cff
43480000
7e1c4b0e
101c1cff
40400000
d206080e
0201010e
101c170e
d2820003
040e270e
d2060803
02010103
101e0902
c2000970
bf8c007f
7e200200
d2100010
02022108
10202104
d282000f
043e2108
10201f0c
c2000974
bf8c007f
7e240200
d2100012
02022509
101e250f
d282000f
04421f09
10201f0d
c2000978
bf8c007f
7e240200
d2100012
0202250a
101e250f
d282000f
04421f0a
101e1f11
101e1eff
3f99999a
d206080f
0201010f
101e1f01
d282000f
043de100
101e270f
d282000f
043e270e
d206080f
0201010f
5e06070f
10040d02
c2000972
bf8c007f
7e1e0200
d210000f
02021f08
101e1f06
d2820002
040a1f08
1018050c
c2000976
bf8c007f
7e1e0200
d210000f
02021f09
10041f02
d2820002
04320509
1018050d
c200097a
bf8c007f
7e1a0200
d210000d
02021b0a
10041b02
d2820002
0432050a
10040511
100404ff
3f99999a
d2060802
02010102
10020501
d2820000
0405e100
10002700
d2820000
0402270e
d2060800
02010100
5e000f00
f8001c0f
00030003
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..31]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MUL TEMP[0].xyz, IN[0].xyzz, CONST[31].xxxx
  2: DP4 TEMP[1].x, TEMP[0], CONST[23]
  3: DP4 TEMP[2].x, TEMP[0], CONST[24]
  4: MOV TEMP[1].y, TEMP[2].xxxx
  5: DP4 TEMP[2].x, TEMP[0], CONST[25]
  6: MOV TEMP[1].z, TEMP[2].xxxx
  7: DP4 TEMP[0].x, TEMP[0], CONST[26]
  8: MOV TEMP[1].w, TEMP[0].xxxx
  9: DP3 TEMP[0].x, IN[1].xyzz, CONST[23].xyzz
 10: DP3 TEMP[2].x, IN[1].xyzz, CONST[24].xyzz
 11: MOV TEMP[0].y, TEMP[2].xxxx
 12: DP3 TEMP[2].x, IN[1].xyzz, CONST[25].xyzz
 13: MOV TEMP[0].z, TEMP[2].xxxx
 14: DP4 TEMP[2].x, TEMP[1], CONST[0]
 15: DP4 TEMP[3].x, TEMP[1], CONST[1]
 16: MOV TEMP[2].y, TEMP[3].xxxx
 17: DP4 TEMP[3].x, TEMP[1], CONST[2]
 18: MOV TEMP[2].z, TEMP[3].xxxx
 19: DP4 TEMP[3].x, TEMP[1], CONST[3]
 20: MOV TEMP[2].w, TEMP[3].xxxx
 21: DP3 TEMP[3].x, TEMP[0].xyzz, TEMP[0].xyzz
 22: RSQ TEMP[3].x, TEMP[3].xxxx
 23: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[3].xxxx
 24: MOV TEMP[3].xy, IN[2].xyxx
 25: MOV TEMP[3].zw, TEMP[0].yyxy
 26: MOV TEMP[0].x, TEMP[0].zzzz
 27: MOV TEMP[0].yzw, TEMP[1].yxyz
 28: MOV OUT[2], TEMP[0]
 29: MOV OUT[0], TEMP[2]
 30: MOV OUT[1], TEMP[3]
 31: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 368)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 372)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 376)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 380)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 384)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 388)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 392)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 396)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 400)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 404)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 408)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 412)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 416)
  %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 420)
  %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 424)
  %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 428)
  %44 = call float @llvm.SI.load.const(<16 x i8> %11, i32 496)
  %45 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
  %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %6)
  %48 = extractelement <4 x float> %47, i32 0
  %49 = extractelement <4 x float> %47, i32 1
  %50 = extractelement <4 x float> %47, i32 2
  %51 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %52, i32 0, i32 %6)
  %54 = extractelement <4 x float> %53, i32 0
  %55 = extractelement <4 x float> %53, i32 1
  %56 = extractelement <4 x float> %53, i32 2
  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %6)
  %60 = extractelement <4 x float> %59, i32 0
  %61 = extractelement <4 x float> %59, i32 1
  %62 = fmul float %48, %44
  %63 = fmul float %49, %44
  %64 = fmul float %50, %44
  %65 = fmul float %62, %28
  %66 = fmul float %63, %29
  %67 = fadd float %65, %66
  %68 = fmul float %64, %30
  %69 = fadd float %67, %68
  %70 = fmul float 1.000000e+00, %31
  %71 = fadd float %69, %70
  %72 = fmul float %62, %32
  %73 = fmul float %63, %33
  %74 = fadd float %72, %73
  %75 = fmul float %64, %34
  %76 = fadd float %74, %75
  %77 = fmul float 1.000000e+00, %35
  %78 = fadd float %76, %77
  %79 = fmul float %62, %36
  %80 = fmul float %63, %37
  %81 = fadd float %79, %80
  %82 = fmul float %64, %38
  %83 = fadd float %81, %82
  %84 = fmul float 1.000000e+00, %39
  %85 = fadd float %83, %84
  %86 = fmul float %62, %40
  %87 = fmul float %63, %41
  %88 = fadd float %86, %87
  %89 = fmul float %64, %42
  %90 = fadd float %88, %89
  %91 = fmul float 1.000000e+00, %43
  %92 = fadd float %90, %91
  %93 = fmul float %54, %28
  %94 = fmul float %55, %29
  %95 = fadd float %94, %93
  %96 = fmul float %56, %30
  %97 = fadd float %95, %96
  %98 = fmul float %54, %32
  %99 = fmul float %55, %33
  %100 = fadd float %99, %98
  %101 = fmul float %56, %34
  %102 = fadd float %100, %101
  %103 = fmul float %54, %36
  %104 = fmul float %55, %37
  %105 = fadd float %104, %103
  %106 = fmul float %56, %38
  %107 = fadd float %105, %106
  %108 = fmul float %71, %12
  %109 = fmul float %78, %13
  %110 = fadd float %108, %109
  %111 = fmul float %85, %14
  %112 = fadd float %110, %111
  %113 = fmul float %92, %15
  %114 = fadd float %112, %113
  %115 = fmul float %71, %16
  %116 = fmul float %78, %17
  %117 = fadd float %115, %116
  %118 = fmul float %85, %18
  %119 = fadd float %117, %118
  %120 = fmul float %92, %19
  %121 = fadd float %119, %120
  %122 = fmul float %71, %20
  %123 = fmul float %78, %21
  %124 = fadd float %122, %123
  %125 = fmul float %85, %22
  %126 = fadd float %124, %125
  %127 = fmul float %92, %23
  %128 = fadd float %126, %127
  %129 = fmul float %71, %24
  %130 = fmul float %78, %25
  %131 = fadd float %129, %130
  %132 = fmul float %85, %26
  %133 = fadd float %131, %132
  %134 = fmul float %92, %27
  %135 = fadd float %133, %134
  %136 = fmul float %97, %97
  %137 = fmul float %102, %102
  %138 = fadd float %137, %136
  %139 = fmul float %107, %107
  %140 = fadd float %138, %139
  %141 = call float @llvm.AMDGPU.rsq(float %140)
  %142 = fmul float %97, %141
  %143 = fmul float %102, %141
  %144 = fmul float %107, %141
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %60, float %61, float %142, float %143)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %144, float %71, float %78, float %85)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %114, float %121, float %128, float %135)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020160
bf8c007f
7e0a0204
d2100005
02020b01
c2028161
bf8c007f
7e0c0205
d2820005
04160d02
c2040162
bf8c007f
7e0c0208
d2820005
04160d03
c204815c
bf8c007f
7e0c0209
d2100006
02020d01
c205015d
bf8c007f
7e0e020a
d2820006
041a0f02
c205815e
bf8c007f
7e0e020b
d2820006
041a0f03
100e0d06
d2820007
041e0b05
c2060164
bf8c007f
7e10020c
d2100008
02021101
c2068165
bf8c007f
7e12020d
d2820008
04221302
c2070166
bf8c007f
7e12020e
d2820001
04221303
d2820002
041e0301
7e045b02
10060505
10080506
c0880708
bf8c007f
e00c2000
80040500
bf8c0770
f800020f
03040605
10020501
c0880700
bf8c000f
e00c2000
80040200
c203017c
bf8c0070
7e000206
d2100006
02020102
d2100007
02020103
10100e0d
d2820008
04201906
d2100000
02020104
d2820002
04201d00
c2030167
bf8c007f
06040406
10060e05
d2820003
040c0906
d2820003
040c1100
c2020163
bf8c007f
06060604
10080e0a
d2820004
04101306
d2820004
04101700
c202015f
bf8c007f
06080804
f800021f
02030401
c202010d
bf8c000f
10020604
c202010c
bf8c007f
d2820001
04040904
c202010e
bf8c007f
d2820001
04040902
c2020169
bf8c007f
100a0e04
c2020168
bf8c007f
d2820005
04140906
c202016a
bf8c007f
d2820000
04140900
c202016b
bf8c007f
06000004
c202010f
bf8c007f
d2820001
04040900
c2020109
bf8c007f
100a0604
c2020108
bf8c007f
d2820005
04140904
c202010a
bf8c007f
d2820005
04140902
c202010b
bf8c007f
d2820005
04140900
c2020105
bf8c007f
100c0604
c2020104
bf8c007f
d2820006
04180904
c2020106
bf8c007f
d2820006
04180902
c2020107
bf8c007f
d2820006
04180900
c2020101
bf8c007f
10060604
c2020100
bf8c007f
d2820003
040c0904
c2020102
bf8c007f
d2820002
040c0902
c2000103
bf8c007f
d2820000
04080100
f80008cf
01050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..22]
DCL TEMP[0..4], LOCAL
IMM[0] FLT32 {    1.0000,     0.5000, -160000.0000,     0.0000}
IMM[1] FLT32 {    0.0033,     0.0000,     0.0000,     0.0000}
  0: ADD TEMP[0].xyz, IN[0].xyzz, -CONST[18].xyzz
  1: DP3 TEMP[1].x, TEMP[0].xyzz, TEMP[0].xyzz
  2: RSQ TEMP[1].x, TEMP[1].xxxx
  3: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx
  4: MOV TEMP[0].xyz, TEMP[0].xyzz
  5: TEX TEMP[0].xyz, TEMP[0], SAMP[0], CUBE
  6: ADD TEMP[1].xyz, CONST[18].xyzz, -IN[0].xyzz
  7: MOV TEMP[2].w, IMM[0].xxxx
  8: DP3 TEMP[3].x, TEMP[1].xyzz, TEMP[1].xyzz
  9: ADD TEMP[3].x, TEMP[3].xxxx, IMM[0].zzzz
 10: MUL TEMP[3].x, TEMP[3].xxxx, IMM[0].wwww
 11: MIN TEMP[3].x, TEMP[3].xxxx, IMM[0].yyyy
 12: MOV_SAT TEMP[3].x, TEMP[3].xxxx
 13: DP3 TEMP[4].x, TEMP[1].xyzz, TEMP[1].xyzz
 14: RSQ TEMP[4].x, TEMP[4].xxxx
 15: MUL TEMP[1].y, TEMP[1].xyzz, TEMP[4].xxxx
 16: ADD TEMP[1].x, IMM[0].xxxx, -TEMP[1].yyyy
 17: MUL TEMP[1].x, TEMP[3].xxxx, TEMP[1].xxxx
 18: LRP TEMP[1].xyz, TEMP[1].xxxx, IMM[0].yyyy, TEMP[0].xyzz
 19: MUL_SAT TEMP[3].x, IN[0].yyyy, IMM[1].xxxx
 20: LRP TEMP[0].xyz, TEMP[3].xxxx, TEMP[0].xyzz, TEMP[1].xyzz
 21: MOV_SAT TEMP[2].xyz, TEMP[0].xyzz
 22: MOV OUT[0], TEMP[2]
 23: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %25 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %26 = load <32 x i8> addrspace(2)* %25, !tbaa !0
  %27 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %30 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %32 = fsub float -0.000000e+00, %22
  %33 = fadd float %29, %32
  %34 = fsub float -0.000000e+00, %23
  %35 = fadd float %30, %34
  %36 = fsub float -0.000000e+00, %24
  %37 = fadd float %31, %36
  %38 = fmul float %33, %33
  %39 = fmul float %35, %35
  %40 = fadd float %39, %38
  %41 = fmul float %37, %37
  %42 = fadd float %40, %41
  %43 = call float @llvm.AMDGPU.rsq(float %42)
  %44 = fmul float %33, %43
  %45 = fmul float %35, %43
  %46 = fmul float %37, %43
  %47 = insertelement <4 x float> undef, float %44, i32 0
  %48 = insertelement <4 x float> %47, float %45, i32 1
  %49 = insertelement <4 x float> %48, float %46, i32 2
  %50 = insertelement <4 x float> %49, float 0.000000e+00, i32 3
  %51 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %50)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = extractelement <4 x float> %51, i32 1
  %54 = extractelement <4 x float> %51, i32 2
  %55 = extractelement <4 x float> %51, i32 3
  %56 = call float @fabs(float %54)
  %57 = fdiv float 1.000000e+00, %56
  %58 = fmul float %52, %57
  %59 = fadd float %58, 1.500000e+00
  %60 = fmul float %53, %57
  %61 = fadd float %60, 1.500000e+00
  %62 = bitcast float %61 to i32
  %63 = bitcast float %59 to i32
  %64 = bitcast float %55 to i32
  %65 = insertelement <4 x i32> undef, i32 %62, i32 0
  %66 = insertelement <4 x i32> %65, i32 %63, i32 1
  %67 = insertelement <4 x i32> %66, i32 %64, i32 2
  %68 = insertelement <4 x i32> %67, i32 undef, i32 3
  %69 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %68, <32 x i8> %26, <16 x i8> %28, i32 4)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = extractelement <4 x float> %69, i32 2
  %73 = fsub float -0.000000e+00, %29
  %74 = fadd float %22, %73
  %75 = fsub float -0.000000e+00, %30
  %76 = fadd float %23, %75
  %77 = fsub float -0.000000e+00, %31
  %78 = fadd float %24, %77
  %79 = fmul float %74, %74
  %80 = fmul float %76, %76
  %81 = fadd float %80, %79
  %82 = fmul float %78, %78
  %83 = fadd float %81, %82
  %84 = fadd float %83, -1.600000e+05
  %85 = fmul float %84, 0x3EAA36E2E0000000
  %86 = fcmp uge float %85, 5.000000e-01
  %87 = select i1 %86, float 5.000000e-01, float %85
  %88 = call float @llvm.AMDIL.clamp.(float %87, float 0.000000e+00, float 1.000000e+00)
  %89 = fmul float %74, %74
  %90 = fmul float %76, %76
  %91 = fadd float %90, %89
  %92 = fmul float %78, %78
  %93 = fadd float %91, %92
  %94 = call float @llvm.AMDGPU.rsq(float %93)
  %95 = fmul float %76, %94
  %96 = fsub float -0.000000e+00, %95
  %97 = fadd float 1.000000e+00, %96
  %98 = fmul float %88, %97
  %99 = call float @llvm.AMDGPU.lrp(float %98, float 5.000000e-01, float %70)
  %100 = call float @llvm.AMDGPU.lrp(float %98, float 5.000000e-01, float %71)
  %101 = call float @llvm.AMDGPU.lrp(float %98, float 5.000000e-01, float %72)
  %102 = fmul float %30, 0x3F6B4E81C0000000
  %103 = call float @llvm.AMDIL.clamp.(float %102, float 0.000000e+00, float 1.000000e+00)
  %104 = call float @llvm.AMDGPU.lrp(float %103, float %70, float %99)
  %105 = call float @llvm.AMDGPU.lrp(float %103, float %71, float %100)
  %106 = call float @llvm.AMDGPU.lrp(float %103, float %72, float %101)
  %107 = call float @llvm.AMDIL.clamp.(float %104, float 0.000000e+00, float 1.000000e+00)
  %108 = call float @llvm.AMDIL.clamp.(float %105, float 0.000000e+00, float 1.000000e+00)
  %109 = call float @llvm.AMDIL.clamp.(float %106, float 0.000000e+00, float 1.000000e+00)
  %110 = call i32 @llvm.SI.packf16(float %107, float %108)
  %111 = bitcast i32 %110 to float
  %112 = call i32 @llvm.SI.packf16(float %109, float 1.000000e+00)
  %113 = bitcast i32 %112 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %111, float %113, float %111, float %113)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080100
c8090101
c0840100
bf8c007f
c2000949
bf8c007f
0a060400
c8100000
c8110001
c2008948
bf8c007f
0a0a0801
100c0b05
d2820006
041a0703
c81c0200
c81d0201
c203094a
bf8c007f
0a000e06
d2820001
041a0100
7e025b01
10140300
10120303
10100305
7e160280
d28a000d
042a1308
d28c000c
042a1308
d28e000e
042a1308
d288000f
042a1308
d2060100
0201010e
7e005500
7e0202ff
3fc00000
d282000e
0406010c
d282000d
0406010d
c0840300
c0c60500
bf8c007f
f0800700
0043080d
08000400
08020801
10020301
d2820001
04060100
08060e06
d2820001
04060703
060602ff
c81c4000
100606ff
3551b717
d00c0000
0201e103
d2000003
0001e103
d2060803
02010103
7e025b01
10000300
080000f2
10000103
080200f2
bf8c0770
10061301
d2820003
040de100
100404ff
3b5a740e
d2060802
02010102
080804f2
10060704
d2820003
040e1302
d2060803
02010103
100a1101
d2820005
0415e100
100a0b04
d2820005
04161102
d2060805
02010105
5e060705
10021501
d2820000
0405e100
10000104
d2820000
04021502
d2060800
02010100
d25e0000
0201e500
f8001c0f
00030003
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..22]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].xxxx
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: DP4 TEMP[1].x, TEMP[0], CONST[12]
  3: DP4 TEMP[2].x, TEMP[0], CONST[13]
  4: MOV TEMP[1].y, TEMP[2].xxxx
  5: DP4 TEMP[2].x, TEMP[0], CONST[14]
  6: MOV TEMP[1].z, TEMP[2].xxxx
  7: DP4 TEMP[2].x, TEMP[0], CONST[15]
  8: RCP TEMP[2].x, TEMP[2].xxxx
  9: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xxxx
 10: MOV TEMP[1].xyz, TEMP[1].xyzx
 11: MOV OUT[1], TEMP[1]
 12: MOV OUT[0], TEMP[0]
 13: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 192)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 196)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 200)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 204)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 208)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 212)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 216)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 220)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 224)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 228)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 232)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 236)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 240)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 244)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 248)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 252)
  %28 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = fmul float %31, %12
  %34 = fmul float %32, %13
  %35 = fadd float %33, %34
  %36 = fmul float 1.000000e+00, %14
  %37 = fadd float %35, %36
  %38 = fmul float 1.000000e+00, %15
  %39 = fadd float %37, %38
  %40 = fmul float %31, %16
  %41 = fmul float %32, %17
  %42 = fadd float %40, %41
  %43 = fmul float 1.000000e+00, %18
  %44 = fadd float %42, %43
  %45 = fmul float 1.000000e+00, %19
  %46 = fadd float %44, %45
  %47 = fmul float %31, %20
  %48 = fmul float %32, %21
  %49 = fadd float %47, %48
  %50 = fmul float 1.000000e+00, %22
  %51 = fadd float %49, %50
  %52 = fmul float 1.000000e+00, %23
  %53 = fadd float %51, %52
  %54 = fmul float %31, %24
  %55 = fmul float %32, %25
  %56 = fadd float %54, %55
  %57 = fmul float 1.000000e+00, %26
  %58 = fadd float %56, %57
  %59 = fmul float 1.000000e+00, %27
  %60 = fadd float %58, %59
  %61 = fdiv float 1.000000e+00, %60
  %62 = fmul float %39, %61
  %63 = fmul float %46, %61
  %64 = fmul float %53, %61
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %62, float %63, float %64, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %31, float %32, float 1.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0820700
bf8c007f
e00c2000
80010000
c0800100
bf8c0070
c2020139
bf8c007f
7e080204
d2100004
02020901
c2020138
bf8c007f
7e0a0204
d2820004
04120b00
c202013a
bf8c007f
06080804
c202013b
bf8c007f
06080804
c202013d
bf8c007f
7e0a0204
d2100005
02020b01
c202013c
bf8c007f
7e0c0204
d2820005
04160d00
c202013e
bf8c007f
060a0a04
c202013f
bf8c007f
060a0a04
7e0a5505
10080b04
c2020135
bf8c007f
7e0c0204
d2100006
02020d01
c2020134
bf8c007f
7e0e0204
d2820006
041a0f00
c2020136
bf8c007f
060c0c04
c2020137
bf8c007f
060c0c04
100c0b06
c2020131
bf8c007f
7e0e0204
d2100007
02020f01
c2020130
bf8c007f
7e100204
d2820007
041e1100
c2020132
bf8c007f
060e0e04
c2000133
bf8c007f
060e0e00
100a0b07
7e0e0280
f800020f
07040605
bf8c070f
7e0802f2
f80008cf
04040100
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0..5], LOCAL
IMM[0] FLT32 {    0.0000,     2.0000,     4.0000,     6.0000}
IMM[1] FLT32 {    0.7200,     1.0000,     0.1667,     0.5000}
IMM[2] FLT32 {   -1.0000,     1.0000,     0.0000,     3.0000}
IMM[3] FLT32 {    5.0000,     1.1000,     1.0000,    -0.0300}
IMM[4] FLT32 {    1.2195,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
  2: MOV_SAT TEMP[0].xyz, TEMP[0].xyzz
  3: MOV TEMP[1].xy, IMM[0].xxxx
  4: MAX TEMP[2].x, TEMP[0].yyyy, TEMP[0].zzzz
  5: MAX TEMP[2].x, TEMP[0].xxxx, TEMP[2].xxxx
  6: MOV TEMP[1].z, TEMP[2].xxxx
  7: MIN TEMP[3].x, TEMP[0].yyyy, TEMP[0].zzzz
  8: MIN TEMP[3].x, TEMP[0].xxxx, TEMP[3].xxxx
  9: ADD TEMP[3].x, TEMP[2].xxxx, -TEMP[3].xxxx
 10: FSNE TEMP[4].x, TEMP[3].xxxx, IMM[0].xxxx
 11: UIF TEMP[4].xxxx :0
 12:   RCP TEMP[4].x, TEMP[2].xxxx
 13:   MUL TEMP[4].x, TEMP[3].xxxx, TEMP[4].xxxx
 14:   MOV TEMP[1].y, TEMP[4].xxxx
 15:   ADD TEMP[4].xyz, TEMP[0].yzxx, -TEMP[0].zxyy
 16:   RCP TEMP[3].x, TEMP[3].xxxx
 17:   MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[3].xxxx
 18:   ADD TEMP[4].xy, TEMP[3].yzzz, IMM[0].yzzz
 19:   FSEQ TEMP[5].x, TEMP[0].xxxx, TEMP[2].xxxx
 20:   UIF TEMP[5].xxxx :0
 21:     MOV TEMP[1].x, TEMP[3].xxxx
 22:   ELSE :0
 23:     FSEQ TEMP[0].x, TEMP[0].yyyy, TEMP[2].xxxx
 24:     UIF TEMP[0].xxxx :0
 25:       MOV TEMP[1].x, TEMP[4].xxxx
 26:     ELSE :0
 27:       MOV TEMP[1].x, TEMP[4].yyyy
 28:     ENDIF
 29:   ENDIF
 30: ENDIF
 31: MUL TEMP[0].xy, TEMP[1].yzzz, IMM[1].xyyy
 32: MUL TEMP[2].x, TEMP[1].xxxx, IMM[1].zzzz
 33: FRC TEMP[2].x, TEMP[2].xxxx
 34: MUL TEMP[1].x, IMM[0].wwww, TEMP[2].xxxx
 35: FSNE TEMP[2].x, TEMP[0].xxxx, IMM[0].xxxx
 36: UIF TEMP[2].xxxx :0
 37:   MUL TEMP[2].x, TEMP[0].xxxx, TEMP[0].yyyy
 38:   MUL TEMP[3].x, TEMP[1].xxxx, IMM[1].wwww
 39:   FRC TEMP[3].x, TEMP[3].xxxx
 40:   MAD TEMP[3].x, IMM[0].yyyy, TEMP[3].xxxx, IMM[2].xxxx
 41:   ABS TEMP[3].x, TEMP[3].xxxx
 42:   ADD TEMP[3].x, IMM[1].yyyy, -TEMP[3].xxxx
 43:   FSLT TEMP[4].x, TEMP[1].xxxx, IMM[1].yyyy
 44:   UIF TEMP[4].xxxx :0
 45:     MOV TEMP[4].xz, IMM[2].yyzy
 46:     MOV TEMP[4].y, TEMP[3].xxxx
 47:     MOV TEMP[4].xyz, TEMP[4].xyzx
 48:   ELSE :0
 49:     FSLT TEMP[5].x, TEMP[1].xxxx, IMM[0].yyyy
 50:     UIF TEMP[5].xxxx :0
 51:       MOV TEMP[5].yz, IMM[2].zyzz
 52:       MOV TEMP[5].x, TEMP[3].xxxx
 53:       MOV TEMP[4].xyz, TEMP[5].xyzx
 54:     ELSE :0
 55:       FSLT TEMP[5].x, TEMP[1].xxxx, IMM[2].wwww
 56:       UIF TEMP[5].xxxx :0
 57:         MOV TEMP[5].xy, IMM[2].zyzz
 58:         MOV TEMP[5].z, TEMP[3].xxxx
 59:         MOV TEMP[4].xyz, TEMP[5].xyzx
 60:       ELSE :0
 61:         FSLT TEMP[5].x, TEMP[1].xxxx, IMM[0].zzzz
 62:         UIF TEMP[5].xxxx :0
 63:           MOV TEMP[5].xz, IMM[2].zzyz
 64:           MOV TEMP[5].y, TEMP[3].xxxx
 65:           MOV TEMP[4].xyz, TEMP[5].xyzx
 66:         ELSE :0
 67:           FSLT TEMP[1].x, TEMP[1].xxxx, IMM[3].xxxx
 68:           UIF TEMP[1].xxxx :0
 69:             MOV TEMP[1].yz, IMM[2].yzyy
 70:             MOV TEMP[1].x, TEMP[3].xxxx
 71:             MOV TEMP[4].xyz, TEMP[1].xyzx
 72:           ELSE :0
 73:             MOV TEMP[1].xy, IMM[2].yzyy
 74:             MOV TEMP[1].z, TEMP[3].xxxx
 75:             MOV TEMP[4].xyz, TEMP[1].xyzx
 76:           ENDIF
 77:         ENDIF
 78:       ENDIF
 79:     ENDIF
 80:   ENDIF
 81:   ADD TEMP[1].x, TEMP[0].yyyy, -TEMP[2].xxxx
 82:   MAD_SAT TEMP[1].xyz, TEMP[4].xyzz, TEMP[2].xxxx, TEMP[1].xxxx
 83:   MOV TEMP[1].xyz, TEMP[1].xyzx
 84: ELSE :0
 85:   MOV_SAT TEMP[1].xyz, TEMP[0].yyyy
 86: ENDIF
 87: MOV TEMP[0].w, IMM[1].yyyy
 88: MUL_SAT TEMP[1].xyz, TEMP[1].xyzz, IMM[3].yzzz
 89: ADD_SAT TEMP[1].xyz, TEMP[1].xyzz, IMM[3].wwww
 90: MUL_SAT TEMP[1].xyz, TEMP[1].xyzz, IMM[4].xxxx
 91: MOV TEMP[0].xyz, TEMP[1].xyzx
 92: MOV OUT[0], TEMP[0]
 93: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %26 = bitcast float %24 to i32
  %27 = bitcast float %25 to i32
  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float 1.000000e+00)
  %35 = call float @llvm.AMDIL.clamp.(float %32, float 0.000000e+00, float 1.000000e+00)
  %36 = call float @llvm.AMDIL.clamp.(float %33, float 0.000000e+00, float 1.000000e+00)
  %37 = fcmp uge float %35, %36
  %38 = select i1 %37, float %35, float %36
  %39 = fcmp uge float %34, %38
  %40 = select i1 %39, float %34, float %38
  %41 = fcmp uge float %35, %36
  %42 = select i1 %41, float %36, float %35
  %43 = fcmp uge float %34, %42
  %44 = select i1 %43, float %42, float %34
  %45 = fsub float -0.000000e+00, %44
  %46 = fadd float %40, %45
  %47 = fcmp une float %46, 0.000000e+00
  %48 = sext i1 %47 to i32
  %49 = bitcast i32 %48 to float
  %50 = bitcast float %49 to i32
  %51 = icmp ne i32 %50, 0
  br i1 %51, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %52 = fdiv float 1.000000e+00, %40
  %53 = fmul float %46, %52
  %54 = fsub float -0.000000e+00, %36
  %55 = fadd float %35, %54
  %56 = fsub float -0.000000e+00, %34
  %57 = fadd float %36, %56
  %58 = fsub float -0.000000e+00, %35
  %59 = fadd float %34, %58
  %60 = fdiv float 1.000000e+00, %46
  %61 = fmul float %55, %60
  %62 = fmul float %57, %60
  %63 = fmul float %59, %60
  %64 = fadd float %62, 2.000000e+00
  %65 = fadd float %63, 4.000000e+00
  %66 = fcmp oeq float %34, %40
  %67 = sext i1 %66 to i32
  %68 = bitcast i32 %67 to float
  %69 = bitcast float %68 to i32
  %70 = icmp ne i32 %69, 0
  br i1 %70, label %ENDIF, label %ELSE26

ENDIF:                                            ; preds = %ELSE26, %IF, %main_body
  %temp4.0 = phi float [ 0.000000e+00, %main_body ], [ %., %ELSE26 ], [ %61, %IF ]
  %temp5.0 = phi float [ 0.000000e+00, %main_body ], [ %53, %IF ], [ %53, %ELSE26 ]
  %71 = fmul float %temp5.0, 0x3FE70A3D80000000
  %72 = fmul float %40, 1.000000e+00
  %73 = fmul float %temp4.0, 0x3FC5555560000000
  %74 = call float @llvm.AMDIL.fraction.(float %73)
  %75 = fmul float 6.000000e+00, %74
  %76 = fcmp une float %71, 0.000000e+00
  %77 = sext i1 %76 to i32
  %78 = bitcast i32 %77 to float
  %79 = bitcast float %78 to i32
  %80 = icmp ne i32 %79, 0
  br i1 %80, label %IF31, label %ELSE32

ELSE26:                                           ; preds = %IF
  %81 = fcmp oeq float %35, %40
  %82 = sext i1 %81 to i32
  %83 = bitcast i32 %82 to float
  %84 = bitcast float %83 to i32
  %85 = icmp ne i32 %84, 0
  %. = select i1 %85, float %64, float %65
  br label %ENDIF

IF31:                                             ; preds = %ENDIF
  %86 = fmul float %71, %72
  %87 = fmul float %75, 5.000000e-01
  %88 = call float @llvm.AMDIL.fraction.(float %87)
  %89 = fmul float 2.000000e+00, %88
  %90 = fadd float %89, -1.000000e+00
  %91 = call float @fabs(float %90)
  %92 = fsub float -0.000000e+00, %91
  %93 = fadd float 1.000000e+00, %92
  %94 = fcmp olt float %75, 1.000000e+00
  %95 = sext i1 %94 to i32
  %96 = bitcast i32 %95 to float
  %97 = bitcast float %96 to i32
  %98 = icmp ne i32 %97, 0
  br i1 %98, label %ENDIF33, label %ELSE35

ELSE32:                                           ; preds = %ENDIF
  %99 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
  %100 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
  %101 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
  br label %ENDIF30

ENDIF30:                                          ; preds = %ELSE32, %ENDIF33
  %temp4.3 = phi float [ %137, %ENDIF33 ], [ %99, %ELSE32 ]
  %temp5.1 = phi float [ %138, %ENDIF33 ], [ %100, %ELSE32 ]
  %temp6.0 = phi float [ %139, %ENDIF33 ], [ %101, %ELSE32 ]
  %102 = fmul float %temp4.3, 0x3FF19999A0000000
  %103 = fmul float %temp5.1, 1.000000e+00
  %104 = fmul float %temp6.0, 1.000000e+00
  %105 = call float @llvm.AMDIL.clamp.(float %102, float 0.000000e+00, float 1.000000e+00)
  %106 = call float @llvm.AMDIL.clamp.(float %103, float 0.000000e+00, float 1.000000e+00)
  %107 = call float @llvm.AMDIL.clamp.(float %104, float 0.000000e+00, float 1.000000e+00)
  %108 = fadd float %105, 0xBF9EB851E0000000
  %109 = fadd float %106, 0xBF9EB851E0000000
  %110 = fadd float %107, 0xBF9EB851E0000000
  %111 = call float @llvm.AMDIL.clamp.(float %108, float 0.000000e+00, float 1.000000e+00)
  %112 = call float @llvm.AMDIL.clamp.(float %109, float 0.000000e+00, float 1.000000e+00)
  %113 = call float @llvm.AMDIL.clamp.(float %110, float 0.000000e+00, float 1.000000e+00)
  %114 = fmul float %111, 0x3FF3831F20000000
  %115 = fmul float %112, 0x3FF3831F20000000
  %116 = fmul float %113, 0x3FF3831F20000000
  %117 = call float @llvm.AMDIL.clamp.(float %114, float 0.000000e+00, float 1.000000e+00)
  %118 = call float @llvm.AMDIL.clamp.(float %115, float 0.000000e+00, float 1.000000e+00)
  %119 = call float @llvm.AMDIL.clamp.(float %116, float 0.000000e+00, float 1.000000e+00)
  %120 = call i32 @llvm.SI.packf16(float %117, float %118)
  %121 = bitcast i32 %120 to float
  %122 = call i32 @llvm.SI.packf16(float %119, float 1.000000e+00)
  %123 = bitcast i32 %122 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %121, float %123, float %121, float %123)
  ret void

ELSE35:                                           ; preds = %IF31
  %124 = fcmp olt float %75, 2.000000e+00
  %125 = sext i1 %124 to i32
  %126 = bitcast i32 %125 to float
  %127 = bitcast float %126 to i32
  %128 = icmp ne i32 %127, 0
  br i1 %128, label %ENDIF33, label %ELSE38

ENDIF33:                                          ; preds = %ELSE44, %ELSE41, %ELSE38, %ELSE35, %IF31
  %temp16.0 = phi float [ 1.000000e+00, %IF31 ], [ %93, %ELSE35 ], [ 0.000000e+00, %ELSE38 ], [ %.48, %ELSE44 ], [ 0.000000e+00, %ELSE41 ]
  %temp17.0 = phi float [ %93, %IF31 ], [ 1.000000e+00, %ELSE35 ], [ 1.000000e+00, %ELSE38 ], [ 0.000000e+00, %ELSE44 ], [ %93, %ELSE41 ]
  %temp18.0 = phi float [ 0.000000e+00, %IF31 ], [ 0.000000e+00, %ELSE35 ], [ %93, %ELSE38 ], [ %.49, %ELSE44 ], [ 1.000000e+00, %ELSE41 ]
  %129 = fsub float -0.000000e+00, %86
  %130 = fadd float %72, %129
  %131 = fmul float %temp16.0, %86
  %132 = fadd float %131, %130
  %133 = fmul float %temp17.0, %86
  %134 = fadd float %133, %130
  %135 = fmul float %temp18.0, %86
  %136 = fadd float %135, %130
  %137 = call float @llvm.AMDIL.clamp.(float %132, float 0.000000e+00, float 1.000000e+00)
  %138 = call float @llvm.AMDIL.clamp.(float %134, float 0.000000e+00, float 1.000000e+00)
  %139 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
  br label %ENDIF30

ELSE38:                                           ; preds = %ELSE35
  %140 = fcmp olt float %75, 3.000000e+00
  %141 = sext i1 %140 to i32
  %142 = bitcast i32 %141 to float
  %143 = bitcast float %142 to i32
  %144 = icmp ne i32 %143, 0
  br i1 %144, label %ENDIF33, label %ELSE41

ELSE41:                                           ; preds = %ELSE38
  %145 = fcmp olt float %75, 4.000000e+00
  %146 = sext i1 %145 to i32
  %147 = bitcast i32 %146 to float
  %148 = bitcast float %147 to i32
  %149 = icmp ne i32 %148, 0
  br i1 %149, label %ENDIF33, label %ELSE44

ELSE44:                                           ; preds = %ELSE41
  %150 = fcmp olt float %75, 5.000000e+00
  %151 = sext i1 %150 to i32
  %152 = bitcast i32 %151 to float
  %153 = bitcast float %152 to i32
  %154 = icmp ne i32 %153, 0
  %.48 = select i1 %154, float %93, float 1.000000e+00
  %.49 = select i1 %154, float 1.000000e+00, float %93
  br label %ENDIF33
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: readonly
declare float @fabs(float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0800300
c0c20500
bf8c007f
f0800700
00010302
bf8c0770
d2060802
02010105
d2060801
02010104
d00c0000
02020501
d2000000
00020501
d2060805
02010103
d00c0002
02020105
d2000003
000a0105
d2000000
00020302
d00c0000
02020105
d2000000
00020b00
080c0700
d00a0000
02010106
7e080280
7e060304
be802400
8980007e
bf88001b
7e065500
10060706
d2080004
02020305
7e105506
d2820006
03da1104
d2080004
02020b02
d2820007
03d21104
d2080002
02020501
10081102
d0040002
02020105
d2000002
00098280
d1040002
02010102
be822402
8982027e
d0040004
02020101
d2000004
00120f06
88fe027e
88fe007e
7e0202ff
3e2aaaab
10020304
7e024101
100402ff
40c00000
7e0202ff
3f3851ec
10020303
d00a0000
02010101
d2000003
00018280
d1040000
02010103
be802400
8980007e
d2060804
02010100
7e060304
7e0a0304
be802500
89fe007e
bf880058
d2100001
02020101
d2100003
0201e102
7e064103
06060703
060606f3
d2060103
02010103
080606f2
d0020002
0201e502
d2000004
00098280
d1040002
02010104
7e080280
7e0c02f2
be822402
8982027e
bf880034
d0020004
0201e902
d2000004
00118280
d1040004
02010104
7e0a02f2
7e080280
bf8c070f
be842404
8984047e
bf880025
7e0802ff
40400000
d0020006
02020902
d2000004
00198280
d1040006
02010104
7e0c0280
7e0a02f2
7e080303
be862406
8986067e
bf880015
d0020008
0201ed02
d2000004
00218280
d1040008
02010104
7e0c0280
7e0802f2
7e0a0303
be882408
8988087e
7e0802ff
40a00000
d002000a
02020902
d2000004
0029e503
d2000006
002a06f2
7e0a0280
88fe087e
88fe067e
7e060306
88fe047e
7e0c0303
7e060305
88fe027e
d2080000
02020300
d2820002
04020304
d2060804
02010102
d2820002
04020303
d2060803
02010102
d2820000
04020306
d2060805
02010100
88fe007e
7e0002ff
3f8ccccd
10000105
d2060800
02010100
060000ff
bcf5c28f
d2060800
02010100
100000ff
3f9c18f9
d2060800
02010100
d2060801
02010103
060202ff
bcf5c28f
d2060801
02010101
100202ff
3f9c18f9
d2060801
02010101
5e000300
d2060801
02010104
060202ff
bcf5c28f
d2060801
02010101
100202ff
3f9c18f9
d2060801
02010101
d25e0001
0201e501
f8001c0f
01000100
bf810000
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.5000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].x, IN[0].xxxx
  2: MOV TEMP[0].y, -IN[0].yyyy
  3: ADD TEMP[1].xy, IN[0].xyyy, IMM[0].yyyy
  4: MUL TEMP[1].xy, TEMP[1].xyyy, IMM[0].zzzz
  5: ADD TEMP[2].x, IMM[0].yyyy, -TEMP[1].yyyy
  6: MOV TEMP[1].y, TEMP[2].xxxx
  7: ADD TEMP[1].xy, TEMP[1].xyyy, CONST[0].xyyy
  8: MOV TEMP[1].xy, TEMP[1].xyxx
  9: MOV OUT[1], TEMP[1]
 10: MOV OUT[0], TEMP[0]
 11: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %15 = load <16 x i8> addrspace(2)* %14, !tbaa !0
  %16 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %15, i32 0, i32 %6)
  %17 = extractelement <4 x float> %16, i32 0
  %18 = extractelement <4 x float> %16, i32 1
  %19 = fsub float -0.000000e+00, %18
  %20 = fadd float %17, 1.000000e+00
  %21 = fadd float %18, 1.000000e+00
  %22 = fmul float %20, 5.000000e-01
  %23 = fmul float %21, 5.000000e-01
  %24 = fsub float -0.000000e+00, %23
  %25 = fadd float 1.000000e+00, %24
  %26 = fadd float %22, %12
  %27 = fadd float %25, %13
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %26, float %27, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %17, float %19, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0820700
bf8c007f
e00c2000
80010000
bf8c0770
d2060004
0201e500
c0800100
bf8c007f
c2020100
bf8c007f
d2820004
0011e104
d2060005
0201e501
100a0af0
080a0af2
c2000101
bf8c007f
060a0a00
7e0c0280
f800020f
06060504
bf8c070f
d2060004
22010101
7e0a02f2
f80008cf
05060400
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..5]
DCL TEMP[0], LOCAL
IMM[0] FLT32 {    0.1000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: ADD TEMP[0], TEMP[0], IMM[0].xxxy
  3: MUL TEMP[0], TEMP[0], CONST[4]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %32 = bitcast float %30 to i32
  %33 = bitcast float %31 to i32
  %34 = insertelement <2 x i32> undef, i32 %32, i32 0
  %35 = insertelement <2 x i32> %34, i32 %33, i32 1
  %36 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %27, <16 x i8> %29, i32 2)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = fadd float %37, 0x3FB99999A0000000
  %42 = fadd float %38, 0x3FB99999A0000000
  %43 = fadd float %39, 0x3FB99999A0000000
  %44 = fadd float %40, 0.000000e+00
  %45 = fmul float %41, %22
  %46 = fmul float %42, %23
  %47 = fmul float %43, %24
  %48 = fmul float %44, %25
  %49 = call i32 @llvm.SI.packf16(float %45, float %46)
  %50 = bitcast i32 %49 to float
  %51 = call i32 @llvm.SI.packf16(float %47, float %48)
  %52 = bitcast i32 %51 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %50, float %52, float %50, float %52)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430002
bf8c0770
d2060004
02010103
c0800100
bf8c007f
c2020113
bf8c007f
10080804
7e0a02ff
3dcccccd
060c0b02
c2020112
bf8c007f
100c0c04
5e080906
060c0b01
c2020111
bf8c007f
100c0c04
06000b00
c2000110
bf8c007f
10000000
5e000d00
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..5]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xyz, IN[0].xyzx
  2: MOV TEMP[1].y, IN[1].yyyy
  3: ADD TEMP[1].x, IN[1].xxxx, CONST[5].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[0]
  5: DP4 TEMP[3].x, TEMP[0], CONST[1]
  6: MOV TEMP[2].y, TEMP[3].xxxx
  7: DP4 TEMP[3].x, TEMP[0], CONST[2]
  8: MOV TEMP[2].z, TEMP[3].xxxx
  9: DP4 TEMP[0].x, TEMP[0], CONST[3]
 10: MOV TEMP[2].w, TEMP[0].xxxx
 11: MOV TEMP[0].xy, TEMP[1].xyxx
 12: MOV OUT[1], TEMP[0]
 13: MOV OUT[0], TEMP[2]
 14: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %29 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %30, i32 0, i32 %6)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = fadd float %38, %28
  %41 = fmul float %32, %12
  %42 = fmul float %33, %13
  %43 = fadd float %41, %42
  %44 = fmul float %34, %14
  %45 = fadd float %43, %44
  %46 = fmul float 1.000000e+00, %15
  %47 = fadd float %45, %46
  %48 = fmul float %32, %16
  %49 = fmul float %33, %17
  %50 = fadd float %48, %49
  %51 = fmul float %34, %18
  %52 = fadd float %50, %51
  %53 = fmul float 1.000000e+00, %19
  %54 = fadd float %52, %53
  %55 = fmul float %32, %20
  %56 = fmul float %33, %21
  %57 = fadd float %55, %56
  %58 = fmul float %34, %22
  %59 = fadd float %57, %58
  %60 = fmul float 1.000000e+00, %23
  %61 = fadd float %59, %60
  %62 = fmul float %32, %24
  %63 = fmul float %33, %25
  %64 = fadd float %62, %63
  %65 = fmul float %34, %26
  %66 = fadd float %64, %65
  %67 = fmul float 1.000000e+00, %27
  %68 = fadd float %66, %67
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %40, float %39, float %34, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %47, float %54, float %61, float %68)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020114
bf8c007f
7e0a0204
d2060005
02020b01
c0820700
bf8c007f
e00c2000
80010600
7e0002f2
bf8c0770
f800020f
00080205
c202010d
bf8c000f
7e000204
d2100000
02020107
c202010c
bf8c007f
7e020204
d2820000
04020306
c202010e
bf8c007f
7e020204
d2820000
04020308
c202010f
bf8c007f
06000004
c2020109
bf8c007f
7e020204
d2100001
02020307
c2020108
bf8c007f
7e040204
d2820001
04060506
c202010a
bf8c007f
7e040204
d2820001
04060508
c202010b
bf8c007f
06020204
c2020105
bf8c007f
7e040204
d2100002
02020507
c2020104
bf8c007f
7e060204
d2820002
040a0706
c2020106
bf8c007f
7e060204
d2820002
040a0708
c2020107
bf8c007f
06040404
c2020101
bf8c007f
7e060204
d2100003
02020707
c2020100
bf8c007f
7e080204
d2820003
040e0906
c2020102
bf8c007f
7e080204
d2820003
040e0908
c2000103
bf8c007f
06060600
f80008cf
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..5]
DCL TEMP[0], LOCAL
IMM[0] FLT32 {   -0.1000,    -0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: ADD TEMP[0], TEMP[0], IMM[0].xxxy
  3: MUL TEMP[0], TEMP[0], CONST[4]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %32 = bitcast float %30 to i32
  %33 = bitcast float %31 to i32
  %34 = insertelement <2 x i32> undef, i32 %32, i32 0
  %35 = insertelement <2 x i32> %34, i32 %33, i32 1
  %36 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %27, <16 x i8> %29, i32 2)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = fadd float %37, 0xBFB99999A0000000
  %42 = fadd float %38, 0xBFB99999A0000000
  %43 = fadd float %39, 0xBFB99999A0000000
  %44 = fadd float %40, -0.000000e+00
  %45 = fmul float %41, %22
  %46 = fmul float %42, %23
  %47 = fmul float %43, %24
  %48 = fmul float %44, %25
  %49 = call i32 @llvm.SI.packf16(float %45, float %46)
  %50 = bitcast i32 %49 to float
  %51 = call i32 @llvm.SI.packf16(float %47, float %48)
  %52 = bitcast i32 %51 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %50, float %52, float %50, float %52)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430002
7e0802ff
80000000
bf8c0770
06080903
c0800100
bf8c007f
c2020113
bf8c007f
10080804
7e0a02ff
bdcccccd
060c0b02
c2020112
bf8c007f
100c0c04
5e080906
060c0b01
c2020111
bf8c007f
100c0c04
06000b00
c2000110
bf8c007f
10000000
5e000d00
f8001c0f
04000400
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..5]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xyz, IN[0].xyzx
  2: MOV TEMP[1].y, IN[1].yyyy
  3: ADD TEMP[1].x, IN[1].xxxx, CONST[5].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[0]
  5: DP4 TEMP[3].x, TEMP[0], CONST[1]
  6: MOV TEMP[2].y, TEMP[3].xxxx
  7: DP4 TEMP[3].x, TEMP[0], CONST[2]
  8: MOV TEMP[2].z, TEMP[3].xxxx
  9: DP4 TEMP[0].x, TEMP[0], CONST[3]
 10: MOV TEMP[2].w, TEMP[0].xxxx
 11: MOV TEMP[0].xy, TEMP[1].xyxx
 12: MOV OUT[1], TEMP[0]
 13: MOV OUT[0], TEMP[2]
 14: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %29 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %30, i32 0, i32 %6)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = fadd float %38, %28
  %41 = fmul float %32, %12
  %42 = fmul float %33, %13
  %43 = fadd float %41, %42
  %44 = fmul float %34, %14
  %45 = fadd float %43, %44
  %46 = fmul float 1.000000e+00, %15
  %47 = fadd float %45, %46
  %48 = fmul float %32, %16
  %49 = fmul float %33, %17
  %50 = fadd float %48, %49
  %51 = fmul float %34, %18
  %52 = fadd float %50, %51
  %53 = fmul float 1.000000e+00, %19
  %54 = fadd float %52, %53
  %55 = fmul float %32, %20
  %56 = fmul float %33, %21
  %57 = fadd float %55, %56
  %58 = fmul float %34, %22
  %59 = fadd float %57, %58
  %60 = fmul float 1.000000e+00, %23
  %61 = fadd float %59, %60
  %62 = fmul float %32, %24
  %63 = fmul float %33, %25
  %64 = fadd float %62, %63
  %65 = fmul float %34, %26
  %66 = fadd float %64, %65
  %67 = fmul float 1.000000e+00, %27
  %68 = fadd float %66, %67
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %40, float %39, float %34, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %47, float %54, float %61, float %68)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020114
bf8c007f
7e0a0204
d2060005
02020b01
c0820700
bf8c007f
e00c2000
80010600
7e0002f2
bf8c0770
f800020f
00080205
c202010d
bf8c000f
7e000204
d2100000
02020107
c202010c
bf8c007f
7e020204
d2820000
04020306
c202010e
bf8c007f
7e020204
d2820000
04020308
c202010f
bf8c007f
06000004
c2020109
bf8c007f
7e020204
d2100001
02020307
c2020108
bf8c007f
7e040204
d2820001
04060506
c202010a
bf8c007f
7e040204
d2820001
04060508
c202010b
bf8c007f
06020204
c2020105
bf8c007f
7e040204
d2100002
02020507
c2020104
bf8c007f
7e060204
d2820002
040a0706
c2020106
bf8c007f
7e060204
d2820002
040a0708
c2020107
bf8c007f
06040404
c2020101
bf8c007f
7e060204
d2100003
02020707
c2020100
bf8c007f
7e080204
d2820003
040e0906
c2020102
bf8c007f
7e080204
d2820003
040e0908
c2000103
bf8c007f
06060600
f80008cf
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..30]
DCL TEMP[0..7], LOCAL
IMM[0] FLT32 {    0.1000,     2.5000,     0.1500,     0.8000}
IMM[1] FLT32 {   -0.5000,     3.0000,     2.0000,     0.3500}
IMM[2] FLT32 {    0.5000, -160000.0000,     0.0000,     1.0000}
IMM[3] FLT32 {    0.0200,     0.0039,     6.2832,    -0.2000}
  0: MUL TEMP[0].x, IN[0].yyyy, IMM[0].xxxx
  1: MOV TEMP[0].y, IN[0].xxxx
  2: MOV TEMP[0].xy, TEMP[0].xyyy
  3: TEX TEMP[0], TEMP[0], SAMP[3], 2D
  4: MUL TEMP[1].x, IN[0].yyyy, IMM[0].xxxx
  5: MOV TEMP[1].y, IN[0].xxxx
  6: MOV TEMP[1].xy, TEMP[1].xyyy
  7: TEX TEMP[1], TEMP[1], SAMP[1], 2D
  8: MUL TEMP[2], TEMP[1].xxxx, CONST[23]
  9: MAD TEMP[2], TEMP[1].yyyy, CONST[24], TEMP[2]
 10: MAD TEMP[2], TEMP[1].zzzz, CONST[25], TEMP[2]
 11: MUL TEMP[3], TEMP[1].xxxx, CONST[26]
 12: MAD TEMP[3], TEMP[1].yyyy, CONST[27], TEMP[3]
 13: MAD TEMP[3], TEMP[1].zzzz, CONST[28], TEMP[3]
 14: LRP TEMP[2].xyz, TEMP[1].wwww, TEMP[3], TEMP[2]
 15: ADD TEMP[2].xyz, TEMP[0].xyzz, TEMP[2].xyzz
 16: LRP TEMP[1].x, TEMP[1].wwww, CONST[26].wwww, CONST[23].wwww
 17: MUL TEMP[0].x, TEMP[0].wwww, TEMP[1].xxxx
 18: MUL TEMP[1].x, CONST[30].xxxx, IMM[0].yyyy
 19: SIN TEMP[1].x, TEMP[1].xxxx
 20: ADD TEMP[3].x, IN[0].xxxx, IMM[1].xxxx
 21: ABS TEMP[3].x, TEMP[3].xxxx
 22: ADD TEMP[3].x, IMM[0].wwww, -TEMP[3].xxxx
 23: MAD_SAT TEMP[1].x, TEMP[1].xxxx, IMM[0].zzzz, TEMP[3].xxxx
 24: MUL TEMP[3].x, IMM[1].zzzz, TEMP[1].xxxx
 25: ADD TEMP[3].x, IMM[1].yyyy, -TEMP[3].xxxx
 26: MUL TEMP[3].x, TEMP[1].xxxx, TEMP[3].xxxx
 27: MUL_SAT TEMP[1].x, TEMP[1].xxxx, TEMP[3].xxxx
 28: MUL TEMP[1].x, TEMP[1].xxxx, CONST[29].wwww
 29: MUL TEMP[3].x, TEMP[0].xxxx, IMM[1].wwww
 30: ADD_SAT TEMP[3].x, TEMP[1].xxxx, -TEMP[3].xxxx
 31: MAD_SAT TEMP[3].xyz, CONST[29].xyzz, TEMP[3].xxxx, TEMP[2].xyzz
 32: ADD TEMP[4].xyz, CONST[18].xyzz, -IN[1].xyzz
 33: ADD TEMP[5].x, IN[1].xxxx, IMM[2].xxxx
 34: RCP TEMP[6].x, CONST[16].xxxx
 35: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 36: ADD TEMP[6].x, IN[1].zzzz, IMM[2].xxxx
 37: RCP TEMP[7].x, CONST[16].yyyy
 38: MUL TEMP[6].x, TEMP[6].xxxx, TEMP[7].xxxx
 39: MOV TEMP[5].y, TEMP[6].xxxx
 40: DP3 TEMP[6].x, TEMP[4].xyzz, TEMP[4].xyzz
 41: ADD TEMP[6].x, TEMP[6].xxxx, IMM[2].yyyy
 42: MUL TEMP[6].x, TEMP[6].xxxx, IMM[2].zzzz
 43: MIN TEMP[6].x, TEMP[6].xxxx, IMM[2].xxxx
 44: MOV_SAT TEMP[6].x, TEMP[6].xxxx
 45: DP3 TEMP[7].x, TEMP[4].xyzz, TEMP[4].xyzz
 46: RSQ TEMP[7].x, TEMP[7].xxxx
 47: MUL TEMP[4].y, TEMP[4].xyzz, TEMP[7].xxxx
 48: ADD TEMP[4].x, IMM[2].wwww, -TEMP[4].yyyy
 49: MUL TEMP[4].x, TEMP[6].xxxx, TEMP[4].xxxx
 50: LRP TEMP[3].xyz, TEMP[4].xxxx, IMM[2].xxxx, TEMP[3].xyzz
 51: MOV TEMP[4].xy, TEMP[5].xyyy
 52: TEX TEMP[4].w, TEMP[4], SAMP[0], 2D
 53: ADD TEMP[5].xy, IN[1].xzzz, IMM[2].xxxx
 54: MUL TEMP[5].xy, TEMP[5].xyyy, IMM[3].yyyy
 55: MAD TEMP[5].xy, CONST[22].yyyy, IMM[3].xxxx, TEMP[5].xyyy
 56: MOV TEMP[5].xy, TEMP[5].xyyy
 57: TEX TEMP[5].x, TEMP[5], SAMP[2], 2D
 58: MUL TEMP[6].x, CONST[22].yyyy, IMM[0].xxxx
 59: FRC TEMP[6].x, TEMP[6].xxxx
 60: ADD TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 61: MUL TEMP[5].x, TEMP[5].xxxx, IMM[3].zzzz
 62: SIN TEMP[5].x, TEMP[5].xxxx
 63: MAD TEMP[5].x, TEMP[5].xxxx, IMM[0].xxxx, IMM[2].xxxx
 64: ADD_SAT TEMP[4].x, TEMP[4].wwww, TEMP[5].xxxx
 65: LRP TEMP[4].x, CONST[22].xxxx, TEMP[4].xxxx, IMM[2].wwww
 66: MAX TEMP[4].x, TEMP[4].xxxx, TEMP[1].xxxx
 67: MUL TEMP[2].xyz, TEMP[3].xyzz, TEMP[4].xxxx
 68: MOV_SAT TEMP[2].xyz, TEMP[2].xyzz
 69: ADD TEMP[1].x, TEMP[1].xxxx, IMM[3].wwww
 70: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
 71: MOV TEMP[2].w, TEMP[0].xxxx
 72: MOV OUT[0], TEMP[2]
 73: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 368)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 372)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 376)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 380)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 384)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 388)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 392)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 400)
  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 404)
  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 408)
  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 416)
  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 420)
  %41 = call float @llvm.SI.load.const(<16 x i8> %21, i32 424)
  %42 = call float @llvm.SI.load.const(<16 x i8> %21, i32 428)
  %43 = call float @llvm.SI.load.const(<16 x i8> %21, i32 432)
  %44 = call float @llvm.SI.load.const(<16 x i8> %21, i32 436)
  %45 = call float @llvm.SI.load.const(<16 x i8> %21, i32 440)
  %46 = call float @llvm.SI.load.const(<16 x i8> %21, i32 448)
  %47 = call float @llvm.SI.load.const(<16 x i8> %21, i32 452)
  %48 = call float @llvm.SI.load.const(<16 x i8> %21, i32 456)
  %49 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %50 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %51 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %52 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
  %53 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %54 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %55 = load <32 x i8> addrspace(2)* %54, !tbaa !0
  %56 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %57 = load <16 x i8> addrspace(2)* %56, !tbaa !0
  %58 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %59 = load <32 x i8> addrspace(2)* %58, !tbaa !0
  %60 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
  %62 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %63 = load <32 x i8> addrspace(2)* %62, !tbaa !0
  %64 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
  %66 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %67 = load <32 x i8> addrspace(2)* %66, !tbaa !0
  %68 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
  %70 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %71 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %72 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %73 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %74 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %75 = fmul float %71, 0x3FB99999A0000000
  %76 = bitcast float %75 to i32
  %77 = bitcast float %70 to i32
  %78 = insertelement <2 x i32> undef, i32 %76, i32 0
  %79 = insertelement <2 x i32> %78, i32 %77, i32 1
  %80 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %79, <32 x i8> %67, <16 x i8> %69, i32 2)
  %81 = extractelement <4 x float> %80, i32 0
  %82 = extractelement <4 x float> %80, i32 1
  %83 = extractelement <4 x float> %80, i32 2
  %84 = extractelement <4 x float> %80, i32 3
  %85 = fmul float %71, 0x3FB99999A0000000
  %86 = bitcast float %85 to i32
  %87 = bitcast float %70 to i32
  %88 = insertelement <2 x i32> undef, i32 %86, i32 0
  %89 = insertelement <2 x i32> %88, i32 %87, i32 1
  %90 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %89, <32 x i8> %59, <16 x i8> %61, i32 2)
  %91 = extractelement <4 x float> %90, i32 0
  %92 = extractelement <4 x float> %90, i32 1
  %93 = extractelement <4 x float> %90, i32 2
  %94 = extractelement <4 x float> %90, i32 3
  %95 = fmul float %91, %29
  %96 = fmul float %91, %30
  %97 = fmul float %91, %31
  %98 = fmul float %92, %33
  %99 = fadd float %98, %95
  %100 = fmul float %92, %34
  %101 = fadd float %100, %96
  %102 = fmul float %92, %35
  %103 = fadd float %102, %97
  %104 = fmul float %93, %36
  %105 = fadd float %104, %99
  %106 = fmul float %93, %37
  %107 = fadd float %106, %101
  %108 = fmul float %93, %38
  %109 = fadd float %108, %103
  %110 = fmul float %91, %39
  %111 = fmul float %91, %40
  %112 = fmul float %91, %41
  %113 = fmul float %92, %43
  %114 = fadd float %113, %110
  %115 = fmul float %92, %44
  %116 = fadd float %115, %111
  %117 = fmul float %92, %45
  %118 = fadd float %117, %112
  %119 = fmul float %93, %46
  %120 = fadd float %119, %114
  %121 = fmul float %93, %47
  %122 = fadd float %121, %116
  %123 = fmul float %93, %48
  %124 = fadd float %123, %118
  %125 = call float @llvm.AMDGPU.lrp(float %94, float %120, float %105)
  %126 = call float @llvm.AMDGPU.lrp(float %94, float %122, float %107)
  %127 = call float @llvm.AMDGPU.lrp(float %94, float %124, float %109)
  %128 = fadd float %81, %125
  %129 = fadd float %82, %126
  %130 = fadd float %83, %127
  %131 = call float @llvm.AMDGPU.lrp(float %94, float %42, float %32)
  %132 = fmul float %84, %131
  %133 = fmul float %53, 2.500000e+00
  %134 = call float @llvm.sin.f32(float %133)
  %135 = fadd float %70, -5.000000e-01
  %136 = call float @fabs(float %135)
  %137 = fsub float -0.000000e+00, %136
  %138 = fadd float 0x3FE99999A0000000, %137
  %139 = fmul float %134, 0x3FC3333340000000
  %140 = fadd float %139, %138
  %141 = call float @llvm.AMDIL.clamp.(float %140, float 0.000000e+00, float 1.000000e+00)
  %142 = fmul float 2.000000e+00, %141
  %143 = fsub float -0.000000e+00, %142
  %144 = fadd float 3.000000e+00, %143
  %145 = fmul float %141, %144
  %146 = fmul float %141, %145
  %147 = call float @llvm.AMDIL.clamp.(float %146, float 0.000000e+00, float 1.000000e+00)
  %148 = fmul float %147, %52
  %149 = fmul float %132, 0x3FD6666660000000
  %150 = fsub float -0.000000e+00, %149
  %151 = fadd float %148, %150
  %152 = call float @llvm.AMDIL.clamp.(float %151, float 0.000000e+00, float 1.000000e+00)
  %153 = fmul float %49, %152
  %154 = fadd float %153, %128
  %155 = fmul float %50, %152
  %156 = fadd float %155, %129
  %157 = fmul float %51, %152
  %158 = fadd float %157, %130
  %159 = call float @llvm.AMDIL.clamp.(float %154, float 0.000000e+00, float 1.000000e+00)
  %160 = call float @llvm.AMDIL.clamp.(float %156, float 0.000000e+00, float 1.000000e+00)
  %161 = call float @llvm.AMDIL.clamp.(float %158, float 0.000000e+00, float 1.000000e+00)
  %162 = fsub float -0.000000e+00, %72
  %163 = fadd float %24, %162
  %164 = fsub float -0.000000e+00, %73
  %165 = fadd float %25, %164
  %166 = fsub float -0.000000e+00, %74
  %167 = fadd float %26, %166
  %168 = fadd float %72, 5.000000e-01
  %169 = fdiv float 1.000000e+00, %22
  %170 = fmul float %168, %169
  %171 = fadd float %74, 5.000000e-01
  %172 = fdiv float 1.000000e+00, %23
  %173 = fmul float %171, %172
  %174 = fmul float %163, %163
  %175 = fmul float %165, %165
  %176 = fadd float %175, %174
  %177 = fmul float %167, %167
  %178 = fadd float %176, %177
  %179 = fadd float %178, -1.600000e+05
  %180 = fmul float %179, 0x3EAA36E2E0000000
  %181 = fcmp uge float %180, 5.000000e-01
  %182 = select i1 %181, float 5.000000e-01, float %180
  %183 = call float @llvm.AMDIL.clamp.(float %182, float 0.000000e+00, float 1.000000e+00)
  %184 = fmul float %163, %163
  %185 = fmul float %165, %165
  %186 = fadd float %185, %184
  %187 = fmul float %167, %167
  %188 = fadd float %186, %187
  %189 = call float @llvm.AMDGPU.rsq(float %188)
  %190 = fmul float %165, %189
  %191 = fsub float -0.000000e+00, %190
  %192 = fadd float 1.000000e+00, %191
  %193 = fmul float %183, %192
  %194 = call float @llvm.AMDGPU.lrp(float %193, float 5.000000e-01, float %159)
  %195 = call float @llvm.AMDGPU.lrp(float %193, float 5.000000e-01, float %160)
  %196 = call float @llvm.AMDGPU.lrp(float %193, float 5.000000e-01, float %161)
  %197 = bitcast float %170 to i32
  %198 = bitcast float %173 to i32
  %199 = insertelement <2 x i32> undef, i32 %197, i32 0
  %200 = insertelement <2 x i32> %199, i32 %198, i32 1
  %201 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %200, <32 x i8> %55, <16 x i8> %57, i32 2)
  %202 = extractelement <4 x float> %201, i32 3
  %203 = fadd float %72, 5.000000e-01
  %204 = fadd float %74, 5.000000e-01
  %205 = fmul float %203, 3.906250e-03
  %206 = fmul float %204, 3.906250e-03
  %207 = fmul float %28, 0x3F947AE140000000
  %208 = fadd float %207, %205
  %209 = fmul float %28, 0x3F947AE140000000
  %210 = fadd float %209, %206
  %211 = bitcast float %208 to i32
  %212 = bitcast float %210 to i32
  %213 = insertelement <2 x i32> undef, i32 %211, i32 0
  %214 = insertelement <2 x i32> %213, i32 %212, i32 1
  %215 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %214, <32 x i8> %63, <16 x i8> %65, i32 2)
  %216 = extractelement <4 x float> %215, i32 0
  %217 = fmul float %28, 0x3FB99999A0000000
  %218 = call float @llvm.AMDIL.fraction.(float %217)
  %219 = fadd float %216, %218
  %220 = fmul float %219, 0x401921FB60000000
  %221 = call float @llvm.sin.f32(float %220)
  %222 = fmul float %221, 0x3FB99999A0000000
  %223 = fadd float %222, 5.000000e-01
  %224 = fadd float %202, %223
  %225 = call float @llvm.AMDIL.clamp.(float %224, float 0.000000e+00, float 1.000000e+00)
  %226 = call float @llvm.AMDGPU.lrp(float %27, float %225, float 1.000000e+00)
  %227 = fcmp uge float %226, %148
  %228 = select i1 %227, float %226, float %148
  %229 = fmul float %194, %228
  %230 = fmul float %195, %228
  %231 = fmul float %196, %228
  %232 = call float @llvm.AMDIL.clamp.(float %229, float 0.000000e+00, float 1.000000e+00)
  %233 = call float @llvm.AMDIL.clamp.(float %230, float 0.000000e+00, float 1.000000e+00)
  %234 = call float @llvm.AMDIL.clamp.(float %231, float 0.000000e+00, float 1.000000e+00)
  %235 = fadd float %148, 0xBFC99999A0000000
  %236 = fcmp uge float %132, %235
  %237 = select i1 %236, float %132, float %235
  %238 = call i32 @llvm.SI.packf16(float %232, float %233)
  %239 = bitcast i32 %238 to float
  %240 = call i32 @llvm.SI.packf16(float %234, float %237)
  %241 = bitcast i32 %240 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %239, float %241, float %239, float %241)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: readonly
declare float @fabs(float) #4

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }
attributes #4 = { readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080600
c8090601
060604f0
100806ff
3b800000
c0840100
bf8c007f
c2000959
7e0a02ff
3ca3d70a
bf8c007f
d2820007
04120a00
c8100400
c8110401
061008f0
101210ff
3b800000
d2820006
04260a00
c0860308
c0c80510
bf8c007f
f0800100
00640506
7e0c02ff
3dcccccd
100e0c00
7e0e4107
bf8c0770
060a0f05
100a0aff
40c90fdb
100a0aff
3e22f983
7e0a6b05
d2820005
03c20d05
c2000941
bf8c007f
7e0c5400
100e0d03
c2000940
bf8c007f
7e065400
100c0708
c0860300
c0c80500
bf8c007f
f0800800
00640306
bf8c0770
06060b03
d2060803
02010103
c2000958
bf8c007f
d2080005
020000f2
d2820003
04160600
c8180000
c8190001
060e0cf1
d2060107
02010107
080e0eff
3f4ccccd
c2000978
7e1002ff
40200000
bf8c007f
10101000
101010ff
3e22f983
7e106b08
7e1202ff
3e19999a
d2820007
041e1308
d2060807
02010107
06100f07
081010ff
40400000
10101107
100e1107
d2060807
02010107
c2000977
bf8c007f
10100e00
d00c000c
02021103
d2000003
00320708
c8200100
c8210101
100a10ff
3dcccccd
c0860304
c0c80508
bf8c007f
f0800f00
00640805
c2008969
bf8c0070
7e180201
d210000c
02021908
c200896d
bf8c007f
7e1a0201
d282000c
04321b09
c2008971
bf8c007f
7e1a0201
d282000c
04321b0a
c200895d
bf8c007f
7e1a0201
d210000d
02021b08
c2008961
bf8c007f
7e1c0201
d282000d
04361d09
c2008965
bf8c007f
7e1c0201
d282000d
04361d0a
081c16f2
101a1b0e
d282000c
0436190b
c086030c
c0c80518
bf8c007f
f0800f00
00640f05
bf8c0770
060a1910
c200895f
bf8c007f
100c1c01
c200896b
bf8c007f
7e180201
d2820006
041a190b
100c0d12
10180cff
beb33333
d282000c
04300107
d206080c
0201010c
c2008975
bf8c007f
d2820005
04161801
d2060805
02010105
c8340500
c8350501
c2008949
bf8c007f
08001a01
c2008948
bf8c007f
08020801
10020301
d2820001
04060100
c200894a
bf8c007f
08040401
d2820001
04060502
060402ff
c81c4000
100404ff
3551b717
d00c0002
0201e102
d2000002
0009e102
d2060802
02010102
7e025b01
10000300
080000f2
10000102
080200f2
10040b01
d2820002
0409e100
10040702
d2060802
02010102
c2008968
bf8c007f
7e080201
d2100004
02020908
c200896c
bf8c007f
7e0a0201
d2820004
04120b09
c2008970
bf8c007f
7e0a0201
d2820004
04120b0a
c200895c
bf8c007f
7e0a0201
d2100005
02020b08
c2008960
bf8c007f
7e1a0201
d2820005
04161b09
c2008964
bf8c007f
7e1a0201
d2820005
04161b0a
100a0b0e
d2820004
0416090b
0608090f
c2008974
bf8c007f
d2820004
04121801
d2060804
02010104
10080901
d2820004
0411e100
10080704
d2060804
02010104
5e040504
c200896a
bf8c007f
7e080201
d2100004
02020908
c200896e
bf8c007f
7e0a0201
d2820004
04120b09
c2008972
bf8c007f
7e0a0201
d2820004
04120b0a
c200895e
bf8c007f
7e0a0201
d2100005
02020b08
c2008962
bf8c007f
7e1a0201
d2820005
04161b09
c2008966
bf8c007f
7e1a0201
d2820005
04161b0a
100a0b0e
d2820004
0416090b
06080911
c2008976
bf8c007f
d2820004
04121801
d2060804
02010104
10020901
d2820000
0405e100
10000700
d2060800
02010100
7e0202ff
be4ccccd
d2820001
04040107
d00c0000
02020306
d2000001
00020d01
5e000300
f8001c0f
00020002
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..22]
DCL TEMP[0..4], LOCAL
IMM[0] FLT32 {    1.0000,    19.0000, 10000.0000,     0.0000}
IMM[1] FLT32 {    0.0500,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xz, IN[0].xyzx
  2: MOV TEMP[0].xzw, TEMP[0].xxzw
  3: ADD TEMP[1].x, IMM[0].yyyy, -IN[0].yyyy
  4: MUL_SAT TEMP[1].x, TEMP[1].xxxx, IMM[0].zzzz
  5: ADD TEMP[2].x, IMM[0].xxxx, -TEMP[1].xxxx
  6: MUL TEMP[1].x, TEMP[1].xxxx, IMM[0].yyyy
  7: MAD TEMP[1].x, TEMP[2].xxxx, IN[0].yyyy, TEMP[1].xxxx
  8: MOV TEMP[0].y, TEMP[1].xxxx
  9: MOV TEMP[1].xyz, TEMP[0].xyzx
 10: MOV TEMP[2].w, IMM[0].wwww
 11: MUL TEMP[2].xyz, CONST[20].xyzz, IMM[1].xxxx
 12: ADD TEMP[2], TEMP[0], -TEMP[2]
 13: DP4 TEMP[3].x, TEMP[0], CONST[0]
 14: DP4 TEMP[4].x, TEMP[0], CONST[1]
 15: MOV TEMP[3].y, TEMP[4].xxxx
 16: DP4 TEMP[0].x, TEMP[0], CONST[3]
 17: MOV TEMP[3].xy, TEMP[3].xyxx
 18: DP4 TEMP[2].x, TEMP[2], CONST[2]
 19: MOV TEMP[3].z, TEMP[2].xxxx
 20: MOV TEMP[3].w, TEMP[0].xxxx
 21: MOV TEMP[0].xyz, TEMP[1].xyzx
 22: MOV OUT[1], IN[1]
 23: MOV OUT[2], TEMP[0]
 24: MOV OUT[0], TEMP[3]
 25: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 320)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 324)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 328)
  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %6)
  %34 = extractelement <4 x float> %33, i32 0
  %35 = extractelement <4 x float> %33, i32 1
  %36 = extractelement <4 x float> %33, i32 2
  %37 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
  %39 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %6)
  %40 = extractelement <4 x float> %39, i32 0
  %41 = extractelement <4 x float> %39, i32 1
  %42 = extractelement <4 x float> %39, i32 2
  %43 = extractelement <4 x float> %39, i32 3
  %44 = fsub float -0.000000e+00, %35
  %45 = fadd float 1.900000e+01, %44
  %46 = fmul float %45, 1.000000e+04
  %47 = call float @llvm.AMDIL.clamp.(float %46, float 0.000000e+00, float 1.000000e+00)
  %48 = fsub float -0.000000e+00, %47
  %49 = fadd float 1.000000e+00, %48
  %50 = fmul float %47, 1.900000e+01
  %51 = fmul float %49, %35
  %52 = fadd float %51, %50
  %53 = fmul float %28, 0x3FA99999A0000000
  %54 = fmul float %29, 0x3FA99999A0000000
  %55 = fmul float %30, 0x3FA99999A0000000
  %56 = fsub float -0.000000e+00, %53
  %57 = fadd float %34, %56
  %58 = fsub float -0.000000e+00, %54
  %59 = fadd float %52, %58
  %60 = fsub float -0.000000e+00, %55
  %61 = fadd float %36, %60
  %62 = fsub float -0.000000e+00, 0.000000e+00
  %63 = fadd float 1.000000e+00, %62
  %64 = fmul float %34, %12
  %65 = fmul float %52, %13
  %66 = fadd float %64, %65
  %67 = fmul float %36, %14
  %68 = fadd float %66, %67
  %69 = fmul float 1.000000e+00, %15
  %70 = fadd float %68, %69
  %71 = fmul float %34, %16
  %72 = fmul float %52, %17
  %73 = fadd float %71, %72
  %74 = fmul float %36, %18
  %75 = fadd float %73, %74
  %76 = fmul float 1.000000e+00, %19
  %77 = fadd float %75, %76
  %78 = fmul float %34, %24
  %79 = fmul float %52, %25
  %80 = fadd float %78, %79
  %81 = fmul float %36, %26
  %82 = fadd float %80, %81
  %83 = fmul float 1.000000e+00, %27
  %84 = fadd float %82, %83
  %85 = fmul float %57, %20
  %86 = fmul float %59, %21
  %87 = fadd float %85, %86
  %88 = fmul float %61, %22
  %89 = fadd float %87, %88
  %90 = fmul float %63, %23
  %91 = fadd float %89, %90
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %40, float %41, float %42, float %43)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %34, float %52, float %36, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %70, float %77, float %91, float %84)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
f800020f
04030201
c0820700
bf8c000f
e00c2000
80010000
bf8c0770
080802ff
41980000
100808ff
461c4000
d2060804
02010104
100a08ff
41980000
080808f2
d2820004
04160304
7e0a02f2
f800021f
05020400
c0800100
bf8c000f
c202010d
bf8c007f
100a0804
c202010c
bf8c007f
7e0c0204
d2820005
04160d00
c202010e
bf8c007f
7e0c0204
d2820005
04160d02
c202010f
bf8c007f
060a0a04
c2020105
bf8c007f
100c0804
c2020104
bf8c007f
7e0e0204
d2820006
041a0f00
c2020106
bf8c007f
7e0e0204
d2820006
041a0f02
c2020107
bf8c007f
060c0c04
c2020101
bf8c007f
100e0804
c2020100
bf8c007f
7e100204
d2820007
041e1100
c2020102
bf8c007f
7e100204
d2820007
041e1102
c2020103
bf8c007f
060e0e04
c2020151
7e1002ff
3d4ccccd
bf8c007f
10121004
08081304
c2020109
bf8c007f
10080804
c2020150
bf8c007f
10121004
08121300
c2020108
bf8c007f
d2820004
04100909
c2020152
bf8c007f
10101004
08001102
c202010a
bf8c007f
d2820000
04100900
c200010b
bf8c007f
06000000
f80008cf
05000607
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..22]
DCL CONST[26]
DCL TEMP[0..6], LOCAL
IMM[0] FLT32 {    0.5000, -160000.0000,     0.0000,     1.0000}
IMM[1] FLT32 {    0.0200,     0.0039,     0.1000,     6.2832}
  0: MOV TEMP[0].xy, IN[0].zwzz
  1: MOV TEMP[0].z, IN[1].xxxx
  2: MOV TEMP[1].xy, IN[0].xyyy
  3: TEX TEMP[1], TEMP[1], SAMP[0], 2D
  4: MUL TEMP[2].x, CONST[26].xxxx, CONST[26].yyyy
  5: MUL TEMP[2].x, TEMP[1].wwww, TEMP[2].xxxx
  6: MOV TEMP[2].w, TEMP[2].xxxx
  7: ADD TEMP[3].xyz, CONST[18].xyzz, -TEMP[0].xyzz
  8: ADD TEMP[4].x, IN[0].zzzz, IMM[0].xxxx
  9: RCP TEMP[5].x, CONST[16].xxxx
 10: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 11: ADD TEMP[5].x, IN[1].xxxx, IMM[0].xxxx
 12: RCP TEMP[6].x, CONST[16].yyyy
 13: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 14: MOV TEMP[4].y, TEMP[5].xxxx
 15: DP3 TEMP[5].x, TEMP[3].xyzz, TEMP[3].xyzz
 16: ADD TEMP[5].x, TEMP[5].xxxx, IMM[0].yyyy
 17: MUL TEMP[5].x, TEMP[5].xxxx, IMM[0].zzzz
 18: MIN TEMP[5].x, TEMP[5].xxxx, IMM[0].xxxx
 19: MOV_SAT TEMP[5].x, TEMP[5].xxxx
 20: DP3 TEMP[6].x, TEMP[3].xyzz, TEMP[3].xyzz
 21: RSQ TEMP[6].x, TEMP[6].xxxx
 22: MUL TEMP[3].y, TEMP[3].xyzz, TEMP[6].xxxx
 23: ADD TEMP[3].x, IMM[0].wwww, -TEMP[3].yyyy
 24: MUL TEMP[3].x, TEMP[5].xxxx, TEMP[3].xxxx
 25: LRP TEMP[1].xyz, TEMP[3].xxxx, IMM[0].xxxx, TEMP[1].xyzz
 26: MOV TEMP[3].xy, TEMP[4].xyyy
 27: TEX TEMP[3].w, TEMP[3], SAMP[2], 2D
 28: ADD TEMP[0].xy, TEMP[0].xzzz, IMM[0].xxxx
 29: MUL TEMP[0].xy, TEMP[0].xyyy, IMM[1].yyyy
 30: MAD TEMP[0].xy, CONST[22].yyyy, IMM[1].xxxx, TEMP[0].xyyy
 31: MOV TEMP[0].xy, TEMP[0].xyyy
 32: TEX TEMP[0].x, TEMP[0], SAMP[1], 2D
 33: MUL TEMP[4].x, CONST[22].yyyy, IMM[1].zzzz
 34: FRC TEMP[4].x, TEMP[4].xxxx
 35: ADD TEMP[0].x, TEMP[0].xxxx, TEMP[4].xxxx
 36: MUL TEMP[0].x, TEMP[0].xxxx, IMM[1].wwww
 37: SIN TEMP[0].x, TEMP[0].xxxx
 38: MAD TEMP[0].x, TEMP[0].xxxx, IMM[1].zzzz, IMM[0].xxxx
 39: ADD_SAT TEMP[0].x, TEMP[3].wwww, TEMP[0].xxxx
 40: LRP TEMP[0].x, CONST[22].xxxx, TEMP[0].xxxx, IMM[0].wwww
 41: MUL TEMP[2].xyz, TEMP[1].xyzz, TEMP[0].xxxx
 42: MOV OUT[0], TEMP[2]
 43: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 416)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 420)
  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
  %35 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %36 = load <32 x i8> addrspace(2)* %35, !tbaa !0
  %37 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %40 = load <32 x i8> addrspace(2)* %39, !tbaa !0
  %41 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
  %43 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %44 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %45 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %46 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %47 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %48 = bitcast float %43 to i32
  %49 = bitcast float %44 to i32
  %50 = insertelement <2 x i32> undef, i32 %48, i32 0
  %51 = insertelement <2 x i32> %50, i32 %49, i32 1
  %52 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %51, <32 x i8> %32, <16 x i8> %34, i32 2)
  %53 = extractelement <4 x float> %52, i32 0
  %54 = extractelement <4 x float> %52, i32 1
  %55 = extractelement <4 x float> %52, i32 2
  %56 = extractelement <4 x float> %52, i32 3
  %57 = fmul float %29, %30
  %58 = fmul float %56, %57
  %59 = fsub float -0.000000e+00, %45
  %60 = fadd float %24, %59
  %61 = fsub float -0.000000e+00, %46
  %62 = fadd float %25, %61
  %63 = fsub float -0.000000e+00, %47
  %64 = fadd float %26, %63
  %65 = fadd float %45, 5.000000e-01
  %66 = fdiv float 1.000000e+00, %22
  %67 = fmul float %65, %66
  %68 = fadd float %47, 5.000000e-01
  %69 = fdiv float 1.000000e+00, %23
  %70 = fmul float %68, %69
  %71 = fmul float %60, %60
  %72 = fmul float %62, %62
  %73 = fadd float %72, %71
  %74 = fmul float %64, %64
  %75 = fadd float %73, %74
  %76 = fadd float %75, -1.600000e+05
  %77 = fmul float %76, 0x3EAA36E2E0000000
  %78 = fcmp uge float %77, 5.000000e-01
  %79 = select i1 %78, float 5.000000e-01, float %77
  %80 = call float @llvm.AMDIL.clamp.(float %79, float 0.000000e+00, float 1.000000e+00)
  %81 = fmul float %60, %60
  %82 = fmul float %62, %62
  %83 = fadd float %82, %81
  %84 = fmul float %64, %64
  %85 = fadd float %83, %84
  %86 = call float @llvm.AMDGPU.rsq(float %85)
  %87 = fmul float %62, %86
  %88 = fsub float -0.000000e+00, %87
  %89 = fadd float 1.000000e+00, %88
  %90 = fmul float %80, %89
  %91 = call float @llvm.AMDGPU.lrp(float %90, float 5.000000e-01, float %53)
  %92 = call float @llvm.AMDGPU.lrp(float %90, float 5.000000e-01, float %54)
  %93 = call float @llvm.AMDGPU.lrp(float %90, float 5.000000e-01, float %55)
  %94 = bitcast float %67 to i32
  %95 = bitcast float %70 to i32
  %96 = insertelement <2 x i32> undef, i32 %94, i32 0
  %97 = insertelement <2 x i32> %96, i32 %95, i32 1
  %98 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %97, <32 x i8> %40, <16 x i8> %42, i32 2)
  %99 = extractelement <4 x float> %98, i32 3
  %100 = fadd float %45, 5.000000e-01
  %101 = fadd float %47, 5.000000e-01
  %102 = fmul float %100, 3.906250e-03
  %103 = fmul float %101, 3.906250e-03
  %104 = fmul float %28, 0x3F947AE140000000
  %105 = fadd float %104, %102
  %106 = fmul float %28, 0x3F947AE140000000
  %107 = fadd float %106, %103
  %108 = bitcast float %105 to i32
  %109 = bitcast float %107 to i32
  %110 = insertelement <2 x i32> undef, i32 %108, i32 0
  %111 = insertelement <2 x i32> %110, i32 %109, i32 1
  %112 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %111, <32 x i8> %36, <16 x i8> %38, i32 2)
  %113 = extractelement <4 x float> %112, i32 0
  %114 = fmul float %28, 0x3FB99999A0000000
  %115 = call float @llvm.AMDIL.fraction.(float %114)
  %116 = fadd float %113, %115
  %117 = fmul float %116, 0x401921FB60000000
  %118 = call float @llvm.sin.f32(float %117)
  %119 = fmul float %118, 0x3FB99999A0000000
  %120 = fadd float %119, 5.000000e-01
  %121 = fadd float %99, %120
  %122 = call float @llvm.AMDIL.clamp.(float %121, float 0.000000e+00, float 1.000000e+00)
  %123 = call float @llvm.AMDGPU.lrp(float %27, float %122, float 1.000000e+00)
  %124 = fmul float %91, %123
  %125 = fmul float %92, %123
  %126 = fmul float %93, %123
  %127 = call i32 @llvm.SI.packf16(float %124, float %125)
  %128 = bitcast i32 %127 to float
  %129 = call i32 @llvm.SI.packf16(float %126, float %58)
  %130 = bitcast i32 %129 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %128, float %130, float %128, float %130)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080300
c8090301
c0840100
bf8c007f
c2000949
bf8c007f
08040400
c80c0200
c80d0201
c2000948
bf8c007f
08080600
10080904
d2820004
04120502
c8140400
c8150401
c200094a
bf8c007f
080c0a00
d2820004
04120d06
060c08ff
c81c4000
100c0cff
3551b717
d00c0000
0201e106
d2000006
0001e106
d2060806
02010106
7e085b04
10040902
080404f2
10040506
080804f2
c81c0100
c81d0101
c8180000
c8190001
c0860300
c0c80500
bf8c007f
f0800f00
00640606
bf8c0770
10000f04
d2820000
0401e102
06020af0
100a02ff
3b800000
c2000959
7e1402ff
3ca3d70a
bf8c007f
d282000c
04161400
060606f0
100a06ff
3b800000
d282000b
04161400
c0860304
c0c80508
bf8c007f
f0800100
0064050b
7e1402ff
3dcccccd
10161400
7e16410b
bf8c0770
060a1705
100a0aff
40c90fdb
100a0aff
3e22f983
7e0a6b05
d2820005
03c21505
c2000941
bf8c007f
7e145400
10161501
c2000940
bf8c007f
7e025400
10140303
c0800308
c0c60510
bf8c007f
f0800800
0003010a
bf8c0770
06020b01
d2060801
02010101
c2000958
bf8c007f
d2080003
020000f2
d2820001
040e0200
10000300
10060d04
d2820003
040de102
10060303
5e000103
10061104
d2820002
040de102
10020302
c2000968
c2008969
bf8c007f
7e040201
d2100002
02020400
10040509
5e020501
f8001c0f
01000100
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..22]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.5000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xyz, IN[0].xyzx
  2: MOV TEMP[1].w, IMM[0].yyyy
  3: MUL TEMP[1].xyz, CONST[20].xyzz, IMM[0].zzzz
  4: DP4 TEMP[2].x, TEMP[0], CONST[0]
  5: DP4 TEMP[3].x, TEMP[0], CONST[1]
  6: MOV TEMP[2].y, TEMP[3].xxxx
  7: DP4 TEMP[3].x, TEMP[0], CONST[3]
  8: MOV TEMP[2].xy, TEMP[2].xyxx
  9: ADD TEMP[0], TEMP[0], -TEMP[1]
 10: DP4 TEMP[0].x, TEMP[0], CONST[2]
 11: MOV TEMP[2].z, TEMP[0].xxxx
 12: MOV TEMP[2].w, TEMP[3].xxxx
 13: MOV TEMP[0].zw, IN[0].yyxy
 14: MOV TEMP[1].x, IN[0].zzzz
 15: MOV TEMP[0].xy, IN[1].xyxx
 16: MOV OUT[2], TEMP[1]
 17: MOV OUT[0], TEMP[2]
 18: MOV OUT[1], TEMP[0]
 19: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 320)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 324)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 328)
  %31 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %6)
  %34 = extractelement <4 x float> %33, i32 0
  %35 = extractelement <4 x float> %33, i32 1
  %36 = extractelement <4 x float> %33, i32 2
  %37 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
  %39 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %6)
  %40 = extractelement <4 x float> %39, i32 0
  %41 = extractelement <4 x float> %39, i32 1
  %42 = fmul float %28, 5.000000e-01
  %43 = fmul float %29, 5.000000e-01
  %44 = fmul float %30, 5.000000e-01
  %45 = fmul float %34, %12
  %46 = fmul float %35, %13
  %47 = fadd float %45, %46
  %48 = fmul float %36, %14
  %49 = fadd float %47, %48
  %50 = fmul float 1.000000e+00, %15
  %51 = fadd float %49, %50
  %52 = fmul float %34, %16
  %53 = fmul float %35, %17
  %54 = fadd float %52, %53
  %55 = fmul float %36, %18
  %56 = fadd float %54, %55
  %57 = fmul float 1.000000e+00, %19
  %58 = fadd float %56, %57
  %59 = fmul float %34, %24
  %60 = fmul float %35, %25
  %61 = fadd float %59, %60
  %62 = fmul float %36, %26
  %63 = fadd float %61, %62
  %64 = fmul float 1.000000e+00, %27
  %65 = fadd float %63, %64
  %66 = fsub float -0.000000e+00, %42
  %67 = fadd float %34, %66
  %68 = fsub float -0.000000e+00, %43
  %69 = fadd float %35, %68
  %70 = fsub float -0.000000e+00, %44
  %71 = fadd float %36, %70
  %72 = fsub float -0.000000e+00, 0.000000e+00
  %73 = fadd float 1.000000e+00, %72
  %74 = fmul float %67, %20
  %75 = fmul float %69, %21
  %76 = fadd float %74, %75
  %77 = fmul float %71, %22
  %78 = fadd float %76, %77
  %79 = fmul float %73, %23
  %80 = fadd float %78, %79
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %40, float %41, float %34, float %35)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %36, float %43, float %44, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %51, float %58, float %80, float %65)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840700
bf8c007f
e00c2000
80020100
c0820704
bf8c0070
e00c2000
80010500
bf8c0770
f800020f
02010605
c0800100
bf8c000f
c2020152
bf8c007f
d2100000
0201e004
c2020151
bf8c007f
d2100005
0201e004
7e0c0280
f800021f
06000503
c202010d
bf8c000f
7e0c0204
d2100006
02020d02
c202010c
bf8c007f
7e0e0204
d2820006
041a0f01
c202010e
bf8c007f
7e0e0204
d2820006
041a0f03
c202010f
bf8c007f
060c0c04
c2020105
bf8c007f
7e0e0204
d2100007
02020f02
c2020104
bf8c007f
7e100204
d2820007
041e1101
c2020106
bf8c007f
7e100204
d2820007
041e1103
c2020107
bf8c007f
060e0e04
c2020101
bf8c007f
7e100204
d2100008
02021102
c2020100
bf8c007f
7e120204
d2820008
04221301
c2020102
bf8c007f
7e120204
d2820008
04221303
c2020103
bf8c007f
06101004
c2020150
bf8c007f
d2100009
0201e004
08121301
080a0b02
c2020109
bf8c007f
100a0a04
c2020108
bf8c007f
d2820005
04140909
08000103
c202010a
bf8c007f
d2820000
04140900
c200010b
bf8c007f
06000000
f80008cf
06000708
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..8]
DCL TEMP[0..1], LOCAL
IMM[0] FLT32 {    0.1000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MOV TEMP[1].xyz, TEMP[0].xyzx
  3: MUL TEMP[0].x, TEMP[0].wwww, CONST[8].yyyy
  4: MOV TEMP[1].w, TEMP[0].xxxx
  5: MAD TEMP[0], CONST[8].xxxx, IMM[0].xxxy, TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %30 = bitcast float %28 to i32
  %31 = bitcast float %29 to i32
  %32 = insertelement <2 x i32> undef, i32 %30, i32 0
  %33 = insertelement <2 x i32> %32, i32 %31, i32 1
  %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %33, <32 x i8> %25, <16 x i8> %27, i32 2)
  %35 = extractelement <4 x float> %34, i32 0
  %36 = extractelement <4 x float> %34, i32 1
  %37 = extractelement <4 x float> %34, i32 2
  %38 = extractelement <4 x float> %34, i32 3
  %39 = fmul float %38, %23
  %40 = fmul float %22, 0x3FB99999A0000000
  %41 = fadd float %40, %35
  %42 = fmul float %22, 0x3FB99999A0000000
  %43 = fadd float %42, %36
  %44 = fmul float %22, 0x3FB99999A0000000
  %45 = fadd float %44, %37
  %46 = fmul float %22, 0.000000e+00
  %47 = fadd float %46, %39
  %48 = call i32 @llvm.SI.packf16(float %41, float %43)
  %49 = bitcast i32 %48 to float
  %50 = call i32 @llvm.SI.packf16(float %45, float %47)
  %51 = bitcast i32 %50 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %49, float %51, float %49, float %51)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430002
c0800100
bf8c0070
c2020120
7e0802ff
3dcccccd
bf8c007f
d2820005
040a0804
c2000121
bf8c007f
7e0c0200
d2100006
02020d03
d2820006
04190004
5e0a0d05
d2820006
04060804
d2820000
04020804
5e000d00
f8001c0f
05000500
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..9]
DCL TEMP[0..2], LOCAL
  0: RCP TEMP[0].x, CONST[9].xxxx
  1: MAD TEMP[0].x, IN[1].xxxx, TEMP[0].xxxx, CONST[9].zzzz
  2: RCP TEMP[1].x, CONST[9].yyyy
  3: MAD TEMP[1].x, IN[1].yyyy, TEMP[1].xxxx, CONST[9].wwww
  4: MOV TEMP[0].y, TEMP[1].xxxx
  5: DP4 TEMP[1].x, IN[0], CONST[0]
  6: DP4 TEMP[2].x, IN[0], CONST[1]
  7: MOV TEMP[1].y, TEMP[2].xxxx
  8: DP4 TEMP[2].x, IN[0], CONST[2]
  9: MOV TEMP[1].z, TEMP[2].xxxx
 10: DP4 TEMP[2].x, IN[0], CONST[3]
 11: MOV TEMP[1].w, TEMP[2].xxxx
 12: MOV TEMP[0].xy, TEMP[0].xyxx
 13: MOV OUT[1], TEMP[0]
 14: MOV OUT[0], TEMP[1]
 15: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 144)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 148)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 152)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 156)
  %32 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0
  %34 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %33, i32 0, i32 %6)
  %35 = extractelement <4 x float> %34, i32 0
  %36 = extractelement <4 x float> %34, i32 1
  %37 = extractelement <4 x float> %34, i32 2
  %38 = extractelement <4 x float> %34, i32 3
  %39 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %40, i32 0, i32 %6)
  %42 = extractelement <4 x float> %41, i32 0
  %43 = extractelement <4 x float> %41, i32 1
  %44 = fdiv float 1.000000e+00, %28
  %45 = fmul float %42, %44
  %46 = fadd float %45, %30
  %47 = fdiv float 1.000000e+00, %29
  %48 = fmul float %43, %47
  %49 = fadd float %48, %31
  %50 = fmul float %35, %12
  %51 = fmul float %36, %13
  %52 = fadd float %50, %51
  %53 = fmul float %37, %14
  %54 = fadd float %52, %53
  %55 = fmul float %38, %15
  %56 = fadd float %54, %55
  %57 = fmul float %35, %16
  %58 = fmul float %36, %17
  %59 = fadd float %57, %58
  %60 = fmul float %37, %18
  %61 = fadd float %59, %60
  %62 = fmul float %38, %19
  %63 = fadd float %61, %62
  %64 = fmul float %35, %20
  %65 = fmul float %36, %21
  %66 = fadd float %64, %65
  %67 = fmul float %37, %22
  %68 = fadd float %66, %67
  %69 = fmul float %38, %23
  %70 = fadd float %68, %69
  %71 = fmul float %35, %24
  %72 = fmul float %36, %25
  %73 = fadd float %71, %72
  %74 = fmul float %37, %26
  %75 = fadd float %73, %74
  %76 = fmul float %38, %27
  %77 = fadd float %75, %76
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %46, float %49, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %56, float %63, float %70, float %77)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020127
bf8c007f
7e0a0204
c2020125
bf8c007f
7e0c5404
d2820005
04160d02
c2020126
bf8c007f
7e0c0204
c2020124
bf8c007f
7e0e5404
d2820001
041a0f01
7e040280
f800020f
02020501
c0820700
bf8c000f
e00c2000
80010000
c202010d
bf8c0070
7e080204
d2100004
02020901
c202010c
bf8c007f
7e0a0204
d2820004
04120b00
c202010e
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020109
bf8c007f
7e0a0204
d2100005
02020b01
c2020108
bf8c007f
7e0c0204
d2820005
04160d00
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010b
bf8c007f
7e0c0204
d2820005
04160d03
c2020105
bf8c007f
7e0c0204
d2100006
02020d01
c2020104
bf8c007f
7e0e0204
d2820006
041a0f00
c2020106
bf8c007f
7e0e0204
d2820006
041a0f02
c2020107
bf8c007f
7e0e0204
d2820006
041a0f03
c2020101
bf8c007f
7e0e0204
d2100007
02020f01
c2020100
bf8c007f
7e100204
d2820007
041e1100
c2020102
bf8c007f
7e100204
d2820007
041e1102
c2000103
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..8]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    2.0000,    -0.5000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0].yw, TEMP[0], SAMP[0], 2D
  2: MUL_SAT TEMP[1].x, TEMP[0].yyyy, IMM[0].xxxx
  3: LRP TEMP[1], TEMP[1].xxxx, CONST[5], CONST[4]
  4: ADD TEMP[2].x, TEMP[0].yyyy, IMM[0].yyyy
  5: MUL_SAT TEMP[2].x, TEMP[2].xxxx, IMM[0].xxxx
  6: LRP TEMP[1].xyz, TEMP[2].xxxx, CONST[6], TEMP[1]
  7: MOV TEMP[1].xyz, TEMP[1].xyzx
  8: MUL TEMP[0].x, TEMP[0].wwww, CONST[8].yyyy
  9: MOV TEMP[1].w, TEMP[0].xxxx
 10: MOV OUT[0], TEMP[1]
 11: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 92)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 100)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 104)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
  %34 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %35 = load <32 x i8> addrspace(2)* %34, !tbaa !0
  %36 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
  %38 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %39 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %40 = bitcast float %38 to i32
  %41 = bitcast float %39 to i32
  %42 = insertelement <2 x i32> undef, i32 %40, i32 0
  %43 = insertelement <2 x i32> %42, i32 %41, i32 1
  %44 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %43, <32 x i8> %35, <16 x i8> %37, i32 2)
  %45 = extractelement <4 x float> %44, i32 1
  %46 = extractelement <4 x float> %44, i32 3
  %47 = fmul float %45, 2.000000e+00
  %48 = call float @llvm.AMDIL.clamp.(float %47, float 0.000000e+00, float 1.000000e+00)
  %49 = call float @llvm.AMDGPU.lrp(float %48, float %26, float %22)
  %50 = call float @llvm.AMDGPU.lrp(float %48, float %27, float %23)
  %51 = call float @llvm.AMDGPU.lrp(float %48, float %28, float %24)
  %52 = call float @llvm.AMDGPU.lrp(float %48, float %29, float %25)
  %53 = fadd float %45, -5.000000e-01
  %54 = fmul float %53, 2.000000e+00
  %55 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00)
  %56 = call float @llvm.AMDGPU.lrp(float %55, float %30, float %49)
  %57 = call float @llvm.AMDGPU.lrp(float %55, float %31, float %50)
  %58 = call float @llvm.AMDGPU.lrp(float %55, float %32, float %51)
  %59 = fmul float %46, %33
  %60 = call i32 @llvm.SI.packf16(float %56, float %57)
  %61 = bitcast i32 %60 to float
  %62 = call i32 @llvm.SI.packf16(float %58, float %59)
  %63 = bitcast i32 %62 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %61, float %63, float %61, float %63)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800300
00430002
bf8c0770
06040100
d2060802
02010102
080604f2
c0800100
bf8c007f
c2020111
bf8c007f
10080604
c2020115
bf8c007f
d2820004
04100902
d2060005
0201e300
060a0b05
d2060805
02010105
080c0af2
10080906
c2020119
bf8c007f
d2820004
04100905
c2020110
bf8c007f
100e0604
c2020114
bf8c007f
d2820007
041c0902
100e0f06
c2020118
bf8c007f
d2820007
041c0905
5e080907
c2020112
bf8c007f
10060604
c2020116
bf8c007f
d2820002
040c0902
10040506
c202011a
bf8c007f
d2820002
04080905
c2000121
bf8c007f
7e060200
d2100000
02020701
5e000102
f8001c0f
00040004
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..9]
DCL TEMP[0..2], LOCAL
  0: RCP TEMP[0].x, CONST[9].xxxx
  1: MAD TEMP[0].x, IN[1].xxxx, TEMP[0].xxxx, CONST[9].zzzz
  2: RCP TEMP[1].x, CONST[9].yyyy
  3: MAD TEMP[1].x, IN[1].yyyy, TEMP[1].xxxx, CONST[9].wwww
  4: MOV TEMP[0].y, TEMP[1].xxxx
  5: DP4 TEMP[1].x, IN[0], CONST[0]
  6: DP4 TEMP[2].x, IN[0], CONST[1]
  7: MOV TEMP[1].y, TEMP[2].xxxx
  8: DP4 TEMP[2].x, IN[0], CONST[2]
  9: MOV TEMP[1].z, TEMP[2].xxxx
 10: DP4 TEMP[2].x, IN[0], CONST[3]
 11: MOV TEMP[1].w, TEMP[2].xxxx
 12: MOV TEMP[0].xy, TEMP[0].xyxx
 13: MOV OUT[1], TEMP[0]
 14: MOV OUT[0], TEMP[1]
 15: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 144)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 148)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 152)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 156)
  %32 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0
  %34 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %33, i32 0, i32 %6)
  %35 = extractelement <4 x float> %34, i32 0
  %36 = extractelement <4 x float> %34, i32 1
  %37 = extractelement <4 x float> %34, i32 2
  %38 = extractelement <4 x float> %34, i32 3
  %39 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %40, i32 0, i32 %6)
  %42 = extractelement <4 x float> %41, i32 0
  %43 = extractelement <4 x float> %41, i32 1
  %44 = fdiv float 1.000000e+00, %28
  %45 = fmul float %42, %44
  %46 = fadd float %45, %30
  %47 = fdiv float 1.000000e+00, %29
  %48 = fmul float %43, %47
  %49 = fadd float %48, %31
  %50 = fmul float %35, %12
  %51 = fmul float %36, %13
  %52 = fadd float %50, %51
  %53 = fmul float %37, %14
  %54 = fadd float %52, %53
  %55 = fmul float %38, %15
  %56 = fadd float %54, %55
  %57 = fmul float %35, %16
  %58 = fmul float %36, %17
  %59 = fadd float %57, %58
  %60 = fmul float %37, %18
  %61 = fadd float %59, %60
  %62 = fmul float %38, %19
  %63 = fadd float %61, %62
  %64 = fmul float %35, %20
  %65 = fmul float %36, %21
  %66 = fadd float %64, %65
  %67 = fmul float %37, %22
  %68 = fadd float %66, %67
  %69 = fmul float %38, %23
  %70 = fadd float %68, %69
  %71 = fmul float %35, %24
  %72 = fmul float %36, %25
  %73 = fadd float %71, %72
  %74 = fmul float %37, %26
  %75 = fadd float %73, %74
  %76 = fmul float %38, %27
  %77 = fadd float %75, %76
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %46, float %49, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %56, float %63, float %70, float %77)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020127
bf8c007f
7e0a0204
c2020125
bf8c007f
7e0c5404
d2820005
04160d02
c2020126
bf8c007f
7e0c0204
c2020124
bf8c007f
7e0e5404
d2820001
041a0f01
7e040280
f800020f
02020501
c0820700
bf8c000f
e00c2000
80010000
c202010d
bf8c0070
7e080204
d2100004
02020901
c202010c
bf8c007f
7e0a0204
d2820004
04120b00
c202010e
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020109
bf8c007f
7e0a0204
d2100005
02020b01
c2020108
bf8c007f
7e0c0204
d2820005
04160d00
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010b
bf8c007f
7e0c0204
d2820005
04160d03
c2020105
bf8c007f
7e0c0204
d2100006
02020d01
c2020104
bf8c007f
7e0e0204
d2820006
041a0f00
c2020106
bf8c007f
7e0e0204
d2820006
041a0f02
c2020107
bf8c007f
7e0e0204
d2820006
041a0f03
c2020101
bf8c007f
7e0e0204
d2100007
02020f01
c2020100
bf8c007f
7e100204
d2820007
041e1100
c2020102
bf8c007f
7e100204
d2820007
041e1102
c2000103
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..8]
DCL TEMP[0..1], LOCAL
IMM[0] FLT32 {    0.1000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0].xw, TEMP[0], SAMP[0], 2D
  2: MUL TEMP[1].xyz, CONST[7].xyzz, TEMP[0].xxxx
  3: MUL TEMP[0].x, TEMP[0].wwww, CONST[8].yyyy
  4: MOV TEMP[1].w, TEMP[0].xxxx
  5: MAD TEMP[0], CONST[8].xxxx, IMM[0].xxxy, TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 112)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 116)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 120)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %33 = bitcast float %31 to i32
  %34 = bitcast float %32 to i32
  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %28, <16 x i8> %30, i32 2)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 3
  %40 = fmul float %22, %38
  %41 = fmul float %23, %38
  %42 = fmul float %24, %38
  %43 = fmul float %39, %26
  %44 = fmul float %25, 0x3FB99999A0000000
  %45 = fadd float %44, %40
  %46 = fmul float %25, 0x3FB99999A0000000
  %47 = fadd float %46, %41
  %48 = fmul float %25, 0x3FB99999A0000000
  %49 = fadd float %48, %42
  %50 = fmul float %25, 0.000000e+00
  %51 = fadd float %50, %43
  %52 = call i32 @llvm.SI.packf16(float %45, float %47)
  %53 = bitcast i32 %52 to float
  %54 = call i32 @llvm.SI.packf16(float %49, float %51)
  %55 = bitcast i32 %54 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %53, float %55, float %53, float %55)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800300
00430002
c0800100
bf8c0070
c202011e
bf8c007f
10040004
c2020120
7e0602ff
3dcccccd
bf8c007f
d2820002
040a0604
c2028121
bf8c007f
7e080205
d2100004
02020901
d2820004
04110004
5e040902
c202811d
bf8c007f
10080005
d2820004
04120604
c200011c
bf8c007f
10000000
d2820000
04020604
5e000900
f8001c0f
02000200
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..9]
DCL TEMP[0..2], LOCAL
  0: RCP TEMP[0].x, CONST[9].xxxx
  1: MAD TEMP[0].x, IN[1].xxxx, TEMP[0].xxxx, CONST[9].zzzz
  2: RCP TEMP[1].x, CONST[9].yyyy
  3: MAD TEMP[1].x, IN[1].yyyy, TEMP[1].xxxx, CONST[9].wwww
  4: MOV TEMP[0].y, TEMP[1].xxxx
  5: DP4 TEMP[1].x, IN[0], CONST[0]
  6: DP4 TEMP[2].x, IN[0], CONST[1]
  7: MOV TEMP[1].y, TEMP[2].xxxx
  8: DP4 TEMP[2].x, IN[0], CONST[2]
  9: MOV TEMP[1].z, TEMP[2].xxxx
 10: DP4 TEMP[2].x, IN[0], CONST[3]
 11: MOV TEMP[1].w, TEMP[2].xxxx
 12: MOV TEMP[0].xy, TEMP[0].xyxx
 13: MOV OUT[1], TEMP[0]
 14: MOV OUT[0], TEMP[1]
 15: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 144)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 148)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 152)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 156)
  %32 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0
  %34 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %33, i32 0, i32 %6)
  %35 = extractelement <4 x float> %34, i32 0
  %36 = extractelement <4 x float> %34, i32 1
  %37 = extractelement <4 x float> %34, i32 2
  %38 = extractelement <4 x float> %34, i32 3
  %39 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
  %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %40, i32 0, i32 %6)
  %42 = extractelement <4 x float> %41, i32 0
  %43 = extractelement <4 x float> %41, i32 1
  %44 = fdiv float 1.000000e+00, %28
  %45 = fmul float %42, %44
  %46 = fadd float %45, %30
  %47 = fdiv float 1.000000e+00, %29
  %48 = fmul float %43, %47
  %49 = fadd float %48, %31
  %50 = fmul float %35, %12
  %51 = fmul float %36, %13
  %52 = fadd float %50, %51
  %53 = fmul float %37, %14
  %54 = fadd float %52, %53
  %55 = fmul float %38, %15
  %56 = fadd float %54, %55
  %57 = fmul float %35, %16
  %58 = fmul float %36, %17
  %59 = fadd float %57, %58
  %60 = fmul float %37, %18
  %61 = fadd float %59, %60
  %62 = fmul float %38, %19
  %63 = fadd float %61, %62
  %64 = fmul float %35, %20
  %65 = fmul float %36, %21
  %66 = fadd float %64, %65
  %67 = fmul float %37, %22
  %68 = fadd float %66, %67
  %69 = fmul float %38, %23
  %70 = fadd float %68, %69
  %71 = fmul float %35, %24
  %72 = fmul float %36, %25
  %73 = fadd float %71, %72
  %74 = fmul float %37, %26
  %75 = fadd float %73, %74
  %76 = fmul float %38, %27
  %77 = fadd float %75, %76
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %46, float %49, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %56, float %63, float %70, float %77)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020127
bf8c007f
7e0a0204
c2020125
bf8c007f
7e0c5404
d2820005
04160d02
c2020126
bf8c007f
7e0c0204
c2020124
bf8c007f
7e0e5404
d2820001
041a0f01
7e040280
f800020f
02020501
c0820700
bf8c000f
e00c2000
80010000
c202010d
bf8c0070
7e080204
d2100004
02020901
c202010c
bf8c007f
7e0a0204
d2820004
04120b00
c202010e
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020109
bf8c007f
7e0a0204
d2100005
02020b01
c2020108
bf8c007f
7e0c0204
d2820005
04160d00
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010b
bf8c007f
7e0c0204
d2820005
04160d03
c2020105
bf8c007f
7e0c0204
d2100006
02020d01
c2020104
bf8c007f
7e0e0204
d2820006
041a0f00
c2020106
bf8c007f
7e0e0204
d2820006
041a0f02
c2020107
bf8c007f
7e0e0204
d2820006
041a0f03
c2020101
bf8c007f
7e0e0204
d2100007
02020f01
c2020100
bf8c007f
7e100204
d2820007
041e1100
c2020102
bf8c007f
7e100204
d2820007
041e1102
c2000103
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL TEMP[0..1], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
  2: MOV TEMP[0].xyz, TEMP[0].xyzx
  3: MOV TEMP[1].xy, IN[0].zwww
  4: TEX TEMP[1].w, TEMP[1], SAMP[1], 2D
  5: MOV TEMP[0].w, TEMP[1].wwww
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %32 = bitcast float %28 to i32
  %33 = bitcast float %29 to i32
  %34 = insertelement <2 x i32> undef, i32 %32, i32 0
  %35 = insertelement <2 x i32> %34, i32 %33, i32 1
  %36 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %21, <16 x i8> %23, i32 2)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = bitcast float %30 to i32
  %41 = bitcast float %31 to i32
  %42 = insertelement <2 x i32> undef, i32 %40, i32 0
  %43 = insertelement <2 x i32> %42, i32 %41, i32 1
  %44 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %43, <32 x i8> %25, <16 x i8> %27, i32 2)
  %45 = extractelement <4 x float> %44, i32 3
  %46 = call i32 @llvm.SI.packf16(float %37, float %38)
  %47 = bitcast i32 %46 to float
  %48 = call i32 @llvm.SI.packf16(float %39, float %45)
  %49 = bitcast i32 %48 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %47, float %49, float %47, float %49)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0300
c80d0301
c8080200
c8090201
c0840304
c0c60508
bf8c007f
f0800800
00430202
c8100100
c8110101
c80c0000
c80d0001
c0800300
c0c20500
bf8c0070
f0800700
00010303
bf8c0770
5e000505
5e020903
f8001c0f
00010001
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..5]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.5000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IN[1].wwzw
  1: RCP TEMP[1].x, CONST[4].xxxx
  2: RCP TEMP[1].y, CONST[4].yyyy
  3: MUL TEMP[0].xy, IN[1].xyyy, TEMP[1].xyyy
  4: RCP TEMP[1].x, CONST[5].xxxx
  5: RCP TEMP[1].y, CONST[5].yyyy
  6: MUL TEMP[1].xy, IN[1].xyyy, TEMP[1].xyyy
  7: ADD TEMP[0].xy, TEMP[0].xyyy, -TEMP[1].xyyy
  8: RCP TEMP[1].x, CONST[5].xxxx
  9: RCP TEMP[1].y, CONST[5].yyyy
 10: MAD TEMP[1].xy, IMM[0].xxxx, TEMP[1].xyyy, CONST[4].zwww
 11: ADD TEMP[0].xy, TEMP[0].xyyy, TEMP[1].xyyy
 12: DP4 TEMP[1].x, IN[0], CONST[0]
 13: DP4 TEMP[2].x, IN[0], CONST[1]
 14: MOV TEMP[1].y, TEMP[2].xxxx
 15: DP4 TEMP[2].x, IN[0], CONST[2]
 16: MOV TEMP[1].z, TEMP[2].xxxx
 17: DP4 TEMP[2].x, IN[0], CONST[3]
 18: MOV TEMP[1].w, TEMP[2].xxxx
 19: MOV OUT[1], TEMP[0]
 20: MOV OUT[0], TEMP[1]
 21: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %6)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %6)
  %44 = extractelement <4 x float> %43, i32 0
  %45 = extractelement <4 x float> %43, i32 1
  %46 = extractelement <4 x float> %43, i32 2
  %47 = extractelement <4 x float> %43, i32 3
  %48 = fdiv float 1.000000e+00, %28
  %49 = fdiv float 1.000000e+00, %29
  %50 = fmul float %44, %48
  %51 = fmul float %45, %49
  %52 = fdiv float 1.000000e+00, %32
  %53 = fdiv float 1.000000e+00, %33
  %54 = fmul float %44, %52
  %55 = fmul float %45, %53
  %56 = fsub float -0.000000e+00, %54
  %57 = fadd float %50, %56
  %58 = fsub float -0.000000e+00, %55
  %59 = fadd float %51, %58
  %60 = fdiv float 1.000000e+00, %32
  %61 = fdiv float 1.000000e+00, %33
  %62 = fmul float 5.000000e-01, %60
  %63 = fadd float %62, %30
  %64 = fmul float 5.000000e-01, %61
  %65 = fadd float %64, %31
  %66 = fadd float %57, %63
  %67 = fadd float %59, %65
  %68 = fmul float %37, %12
  %69 = fmul float %38, %13
  %70 = fadd float %68, %69
  %71 = fmul float %39, %14
  %72 = fadd float %70, %71
  %73 = fmul float %40, %15
  %74 = fadd float %72, %73
  %75 = fmul float %37, %16
  %76 = fmul float %38, %17
  %77 = fadd float %75, %76
  %78 = fmul float %39, %18
  %79 = fadd float %77, %78
  %80 = fmul float %40, %19
  %81 = fadd float %79, %80
  %82 = fmul float %37, %20
  %83 = fmul float %38, %21
  %84 = fadd float %82, %83
  %85 = fmul float %39, %22
  %86 = fadd float %84, %85
  %87 = fmul float %40, %23
  %88 = fadd float %86, %87
  %89 = fmul float %37, %24
  %90 = fmul float %38, %25
  %91 = fadd float %89, %90
  %92 = fmul float %39, %26
  %93 = fadd float %91, %92
  %94 = fmul float %40, %27
  %95 = fadd float %93, %94
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %66, float %67, float %46, float %47)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %74, float %81, float %88, float %95)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020115
bf8c007f
7e0a5404
100c0b02
c2020111
bf8c007f
7e0e5404
100e0f02
080c0d07
c2020113
bf8c007f
d2820005
0011e105
060a0b06
c2020114
bf8c007f
7e0c5404
100e0d01
c2020110
bf8c007f
7e105404
10101101
080e0f08
c2020112
bf8c007f
d2820006
0011e106
060c0d07
f800020f
04030506
c0820700
bf8c000f
e00c2000
80010000
c202010d
bf8c0070
7e080204
d2100004
02020901
c202010c
bf8c007f
7e0a0204
d2820004
04120b00
c202010e
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020109
bf8c007f
7e0a0204
d2100005
02020b01
c2020108
bf8c007f
7e0c0204
d2820005
04160d00
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010b
bf8c007f
7e0c0204
d2820005
04160d03
c2020105
bf8c007f
7e0c0204
d2100006
02020d01
c2020104
bf8c007f
7e0e0204
d2820006
041a0f00
c2020106
bf8c007f
7e0e0204
d2820006
041a0f02
c2020107
bf8c007f
7e0e0204
d2820006
041a0f03
c2020101
bf8c007f
7e0e0204
d2100007
02020f01
c2020100
bf8c007f
7e100204
d2820007
041e1100
c2020102
bf8c007f
7e100204
d2820007
041e1102
c2000103
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..5]
DCL TEMP[0..1], LOCAL
IMM[0] FLT32 {    0.2127,     0.7152,     0.0722,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MOV TEMP[1].w, TEMP[0].wwww
  3: DP3 TEMP[0].x, TEMP[0].xyzz, IMM[0].xyzz
  4: MOV TEMP[1].xyz, TEMP[0].xxxx
  5: MUL TEMP[0], TEMP[1], CONST[4]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %32 = bitcast float %30 to i32
  %33 = bitcast float %31 to i32
  %34 = insertelement <2 x i32> undef, i32 %32, i32 0
  %35 = insertelement <2 x i32> %34, i32 %33, i32 1
  %36 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %27, <16 x i8> %29, i32 2)
  %37 = extractelement <4 x float> %36, i32 0
  %38 = extractelement <4 x float> %36, i32 1
  %39 = extractelement <4 x float> %36, i32 2
  %40 = extractelement <4 x float> %36, i32 3
  %41 = fmul float %37, 0x3FCB38CDA0000000
  %42 = fmul float %38, 0x3FE6E29740000000
  %43 = fadd float %42, %41
  %44 = fmul float %39, 0x3FB279AAE0000000
  %45 = fadd float %43, %44
  %46 = fmul float %45, %22
  %47 = fmul float %45, %23
  %48 = fmul float %45, %24
  %49 = fmul float %40, %25
  %50 = call i32 @llvm.SI.packf16(float %46, float %47)
  %51 = bitcast i32 %50 to float
  %52 = call i32 @llvm.SI.packf16(float %48, float %49)
  %53 = bitcast i32 %52 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %51, float %53, float %51, float %53)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430002
7e0802ff
3e59c66d
bf8c0770
10080900
7e0a02ff
3f3714ba
d2820004
04120b01
7e0a02ff
3d93cd57
d2820004
04120b02
c0800100
bf8c007f
c2020111
bf8c007f
100a0804
c2020110
bf8c007f
100c0804
5e0a0b06
c2020112
bf8c007f
10080804
c2000113
bf8c007f
7e0c0200
d2100000
02020d03
5e000104
f8001c0f
00050005
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..5]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].xyz, IN[0].xyzx
  2: MOV TEMP[1].y, IN[1].yyyy
  3: ADD TEMP[1].x, IN[1].xxxx, CONST[5].xxxx
  4: DP4 TEMP[2].x, TEMP[0], CONST[0]
  5: DP4 TEMP[3].x, TEMP[0], CONST[1]
  6: MOV TEMP[2].y, TEMP[3].xxxx
  7: DP4 TEMP[3].x, TEMP[0], CONST[2]
  8: MOV TEMP[2].z, TEMP[3].xxxx
  9: DP4 TEMP[0].x, TEMP[0], CONST[3]
 10: MOV TEMP[2].w, TEMP[0].xxxx
 11: MOV TEMP[0].xy, TEMP[1].xyxx
 12: MOV OUT[1], TEMP[0]
 13: MOV OUT[0], TEMP[2]
 14: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %29 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %30, i32 0, i32 %6)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = fadd float %38, %28
  %41 = fmul float %32, %12
  %42 = fmul float %33, %13
  %43 = fadd float %41, %42
  %44 = fmul float %34, %14
  %45 = fadd float %43, %44
  %46 = fmul float 1.000000e+00, %15
  %47 = fadd float %45, %46
  %48 = fmul float %32, %16
  %49 = fmul float %33, %17
  %50 = fadd float %48, %49
  %51 = fmul float %34, %18
  %52 = fadd float %50, %51
  %53 = fmul float 1.000000e+00, %19
  %54 = fadd float %52, %53
  %55 = fmul float %32, %20
  %56 = fmul float %33, %21
  %57 = fadd float %55, %56
  %58 = fmul float %34, %22
  %59 = fadd float %57, %58
  %60 = fmul float 1.000000e+00, %23
  %61 = fadd float %59, %60
  %62 = fmul float %32, %24
  %63 = fmul float %33, %25
  %64 = fadd float %62, %63
  %65 = fmul float %34, %26
  %66 = fadd float %64, %65
  %67 = fmul float 1.000000e+00, %27
  %68 = fadd float %66, %67
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %40, float %39, float %34, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %47, float %54, float %61, float %68)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020114
bf8c007f
7e0a0204
d2060005
02020b01
c0820700
bf8c007f
e00c2000
80010600
7e0002f2
bf8c0770
f800020f
00080205
c202010d
bf8c000f
7e000204
d2100000
02020107
c202010c
bf8c007f
7e020204
d2820000
04020306
c202010e
bf8c007f
7e020204
d2820000
04020308
c202010f
bf8c007f
06000004
c2020109
bf8c007f
7e020204
d2100001
02020307
c2020108
bf8c007f
7e040204
d2820001
04060506
c202010a
bf8c007f
7e040204
d2820001
04060508
c202010b
bf8c007f
06020204
c2020105
bf8c007f
7e040204
d2100002
02020507
c2020104
bf8c007f
7e060204
d2820002
040a0706
c2020106
bf8c007f
7e060204
d2820002
040a0708
c2020107
bf8c007f
06040404
c2020101
bf8c007f
7e060204
d2100003
02020707
c2020100
bf8c007f
7e080204
d2820003
040e0906
c2020102
bf8c007f
7e080204
d2820003
040e0908
c2000103
bf8c007f
06060600
f80008cf
00010203
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..10]
DCL TEMP[0..1], LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[2], 2D
  2: MOV TEMP[1].xy, IN[0].xyyy
  3: TEX TEMP[1], TEMP[1], SAMP[1], 2D
  4: LRP TEMP[0].xyz, TEMP[0].wwww, TEMP[0], TEMP[1]
  5: MOV TEMP[0].xyz, TEMP[0].xyzx
  6: MOV TEMP[1].xy, IN[0].zwww
  7: TEX TEMP[1].x, TEMP[1], SAMP[0], 2D
  8: MUL TEMP[1].x, TEMP[1].xxxx, CONST[10].yyyy
  9: MOV TEMP[0].w, TEMP[1].xxxx
 10: MOV OUT[0], TEMP[0]
 11: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 164)
  %23 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %24 = load <32 x i8> addrspace(2)* %23, !tbaa !0
  %25 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %26 = load <16 x i8> addrspace(2)* %25, !tbaa !0
  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %37 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %38 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %39 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %40 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %41 = bitcast float %39 to i32
  %42 = bitcast float %40 to i32
  %43 = insertelement <2 x i32> undef, i32 %41, i32 0
  %44 = insertelement <2 x i32> %43, i32 %42, i32 1
  %45 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %44, <32 x i8> %32, <16 x i8> %34, i32 2)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = extractelement <4 x float> %45, i32 2
  %49 = extractelement <4 x float> %45, i32 3
  %50 = bitcast float %35 to i32
  %51 = bitcast float %36 to i32
  %52 = insertelement <2 x i32> undef, i32 %50, i32 0
  %53 = insertelement <2 x i32> %52, i32 %51, i32 1
  %54 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %53, <32 x i8> %28, <16 x i8> %30, i32 2)
  %55 = extractelement <4 x float> %54, i32 0
  %56 = extractelement <4 x float> %54, i32 1
  %57 = extractelement <4 x float> %54, i32 2
  %58 = call float @llvm.AMDGPU.lrp(float %49, float %46, float %55)
  %59 = call float @llvm.AMDGPU.lrp(float %49, float %47, float %56)
  %60 = call float @llvm.AMDGPU.lrp(float %49, float %48, float %57)
  %61 = bitcast float %37 to i32
  %62 = bitcast float %38 to i32
  %63 = insertelement <2 x i32> undef, i32 %61, i32 0
  %64 = insertelement <2 x i32> %63, i32 %62, i32 1
  %65 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %64, <32 x i8> %24, <16 x i8> %26, i32 2)
  %66 = extractelement <4 x float> %65, i32 0
  %67 = fmul float %66, %22
  %68 = call i32 @llvm.SI.packf16(float %58, float %59)
  %69 = bitcast i32 %68 to float
  %70 = call i32 @llvm.SI.packf16(float %60, float %67)
  %71 = bitcast i32 %70 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %69, float %71, float %69, float %71)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840304
c0c60508
bf8c007f
f0800700
00430202
c8180500
c8190501
c8140400
c8150401
c0840308
c0c60510
bf8c0070
f0800f00
00430505
bf8c0770
081210f2
10140709
d282000a
042a0d08
10160509
d282000b
042e0b08
5e14150b
10040909
d2820002
040a0f08
c8100300
c8110301
c80c0200
c80d0201
c0840300
c0c60500
bf8c007f
f0800100
00430003
c0800100
bf8c0070
c2000129
bf8c007f
10000000
5e000102
f8001c0f
000a000a
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..10]
DCL TEMP[0..4], LOCAL
  0: RCP TEMP[0].x, CONST[4].xxxx
  1: MAD TEMP[0].x, IN[1].xxxx, TEMP[0].xxxx, CONST[4].zzzz
  2: RCP TEMP[1].x, CONST[4].yyyy
  3: MAD TEMP[1].x, IN[1].yyyy, TEMP[1].xxxx, CONST[4].wwww
  4: MOV TEMP[0].y, TEMP[1].xxxx
  5: RCP TEMP[1].x, CONST[6].yyyy
  6: ADD TEMP[2].x, IN[1].xxxx, -CONST[5].xxxx
  7: MUL TEMP[3].x, CONST[5].zzzz, CONST[6].yyyy
  8: RCP TEMP[3].x, TEMP[3].xxxx
  9: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
 10: MAD TEMP[1].x, CONST[6].xxxx, TEMP[1].xxxx, TEMP[2].xxxx
 11: RCP TEMP[2].x, CONST[6].wwww
 12: ADD TEMP[3].x, IN[1].yyyy, -CONST[5].yyyy
 13: MUL TEMP[4].x, CONST[5].wwww, CONST[6].wwww
 14: RCP TEMP[4].x, TEMP[4].xxxx
 15: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 16: MAD TEMP[2].x, CONST[6].zzzz, TEMP[2].xxxx, TEMP[3].xxxx
 17: MOV TEMP[1].y, TEMP[2].xxxx
 18: DP4 TEMP[2].x, IN[0], CONST[0]
 19: DP4 TEMP[3].x, IN[0], CONST[1]
 20: MOV TEMP[2].y, TEMP[3].xxxx
 21: DP4 TEMP[3].x, IN[0], CONST[2]
 22: MOV TEMP[2].z, TEMP[3].xxxx
 23: DP4 TEMP[3].x, IN[0], CONST[3]
 24: MOV TEMP[2].w, TEMP[3].xxxx
 25: MOV TEMP[0].xy, TEMP[0].xyxx
 26: MOV TEMP[0].zw, IN[2].yyxy
 27: MOV TEMP[1].xy, TEMP[1].xyxx
 28: MOV OUT[2], TEMP[1]
 29: MOV OUT[0], TEMP[2]
 30: MOV OUT[1], TEMP[0]
 31: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 108)
  %40 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %41 = load <16 x i8> addrspace(2)* %40, !tbaa !0
  %42 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %41, i32 0, i32 %6)
  %43 = extractelement <4 x float> %42, i32 0
  %44 = extractelement <4 x float> %42, i32 1
  %45 = extractelement <4 x float> %42, i32 2
  %46 = extractelement <4 x float> %42, i32 3
  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %6)
  %50 = extractelement <4 x float> %49, i32 0
  %51 = extractelement <4 x float> %49, i32 1
  %52 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %53 = load <16 x i8> addrspace(2)* %52, !tbaa !0
  %54 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %53, i32 0, i32 %6)
  %55 = extractelement <4 x float> %54, i32 0
  %56 = extractelement <4 x float> %54, i32 1
  %57 = fdiv float 1.000000e+00, %28
  %58 = fmul float %50, %57
  %59 = fadd float %58, %30
  %60 = fdiv float 1.000000e+00, %29
  %61 = fmul float %51, %60
  %62 = fadd float %61, %31
  %63 = fdiv float 1.000000e+00, %37
  %64 = fsub float -0.000000e+00, %32
  %65 = fadd float %50, %64
  %66 = fmul float %34, %37
  %67 = fdiv float 1.000000e+00, %66
  %68 = fmul float %65, %67
  %69 = fmul float %36, %63
  %70 = fadd float %69, %68
  %71 = fdiv float 1.000000e+00, %39
  %72 = fsub float -0.000000e+00, %33
  %73 = fadd float %51, %72
  %74 = fmul float %35, %39
  %75 = fdiv float 1.000000e+00, %74
  %76 = fmul float %73, %75
  %77 = fmul float %38, %71
  %78 = fadd float %77, %76
  %79 = fmul float %43, %12
  %80 = fmul float %44, %13
  %81 = fadd float %79, %80
  %82 = fmul float %45, %14
  %83 = fadd float %81, %82
  %84 = fmul float %46, %15
  %85 = fadd float %83, %84
  %86 = fmul float %43, %16
  %87 = fmul float %44, %17
  %88 = fadd float %86, %87
  %89 = fmul float %45, %18
  %90 = fadd float %88, %89
  %91 = fmul float %46, %19
  %92 = fadd float %90, %91
  %93 = fmul float %43, %20
  %94 = fmul float %44, %21
  %95 = fadd float %93, %94
  %96 = fmul float %45, %22
  %97 = fadd float %95, %96
  %98 = fmul float %46, %23
  %99 = fadd float %97, %98
  %100 = fmul float %43, %24
  %101 = fmul float %44, %25
  %102 = fadd float %100, %101
  %103 = fmul float %45, %26
  %104 = fadd float %102, %103
  %105 = fmul float %46, %27
  %106 = fadd float %104, %105
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %59, float %62, float %55, float %56)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %70, float %78, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %85, float %92, float %99, float %106)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020113
bf8c007f
7e0a0204
c2020111
bf8c007f
7e0c5404
d2820005
04160d02
c2020112
bf8c007f
7e0c0204
c2020110
bf8c007f
7e0e5404
d2820006
041a0f01
c0840708
bf8c007f
e00c2000
80020700
bf8c0770
f800020f
08070506
c2020115
bf8c000f
7e0a0204
d2080005
02020b02
c2020117
c202811b
bf8c007f
7e0c0205
d2100006
02020c04
7e0c5506
100a0d05
c202011a
7e0c5405
bf8c007f
d2820005
04160c04
c2020114
bf8c007f
7e0c0204
d2080001
02020d01
c2020116
c2028119
bf8c007f
7e040205
d2100002
02020404
7e045502
10020501
c2020118
7e045405
bf8c007f
d2820001
04060404
7e040280
f800021f
02020501
c0820700
bf8c000f
e00c2000
80010000
c202010d
bf8c0070
7e080204
d2100004
02020901
c202010c
bf8c007f
7e0a0204
d2820004
04120b00
c202010e
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020109
bf8c007f
7e0a0204
d2100005
02020b01
c2020108
bf8c007f
7e0c0204
d2820005
04160d00
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010b
bf8c007f
7e0c0204
d2820005
04160d03
c2020105
bf8c007f
7e0c0204
d2100006
02020d01
c2020104
bf8c007f
7e0e0204
d2820006
041a0f00
c2020106
bf8c007f
7e0e0204
d2820006
041a0f02
c2020107
bf8c007f
7e0e0204
d2820006
041a0f03
c2020101
bf8c007f
7e0e0204
d2100007
02020f01
c2020100
bf8c007f
7e100204
d2820007
041e1100
c2020102
bf8c007f
7e100204
d2820007
041e1102
c2000103
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..10]
DCL TEMP[0..1], LOCAL
IMM[0] FLT32 {    0.1000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MOV TEMP[1].xyz, TEMP[0].xyzx
  3: MUL TEMP[0].x, TEMP[0].wwww, CONST[10].yyyy
  4: MOV TEMP[1].w, TEMP[0].xxxx
  5: MAD TEMP[0], CONST[10].xxxx, IMM[0].xxxy, TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 160)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 164)
  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %30 = bitcast float %28 to i32
  %31 = bitcast float %29 to i32
  %32 = insertelement <2 x i32> undef, i32 %30, i32 0
  %33 = insertelement <2 x i32> %32, i32 %31, i32 1
  %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %33, <32 x i8> %25, <16 x i8> %27, i32 2)
  %35 = extractelement <4 x float> %34, i32 0
  %36 = extractelement <4 x float> %34, i32 1
  %37 = extractelement <4 x float> %34, i32 2
  %38 = extractelement <4 x float> %34, i32 3
  %39 = fmul float %38, %23
  %40 = fmul float %22, 0x3FB99999A0000000
  %41 = fadd float %40, %35
  %42 = fmul float %22, 0x3FB99999A0000000
  %43 = fadd float %42, %36
  %44 = fmul float %22, 0x3FB99999A0000000
  %45 = fadd float %44, %37
  %46 = fmul float %22, 0.000000e+00
  %47 = fadd float %46, %39
  %48 = call i32 @llvm.SI.packf16(float %41, float %43)
  %49 = bitcast i32 %48 to float
  %50 = call i32 @llvm.SI.packf16(float %45, float %47)
  %51 = bitcast i32 %50 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %49, float %51, float %49, float %51)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840300
c0c60500
bf8c007f
f0800f00
00430002
c0800100
bf8c0070
c2020128
7e0802ff
3dcccccd
bf8c007f
d2820005
040a0804
c2000129
bf8c007f
7e0c0200
d2100006
02020d03
d2820006
04190004
5e0a0d05
d2820006
04060804
d2820000
04020804
5e000d00
f8001c0f
05000500
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..10]
DCL TEMP[0..1], LOCAL
  0: DP4 TEMP[0].x, IN[0], CONST[0]
  1: DP4 TEMP[1].x, IN[0], CONST[1]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: DP4 TEMP[1].x, IN[0], CONST[2]
  4: MOV TEMP[0].z, TEMP[1].xxxx
  5: DP4 TEMP[1].x, IN[0], CONST[3]
  6: MOV TEMP[0].w, TEMP[1].xxxx
  7: MOV TEMP[1].xy, IN[1].xyxx
  8: MOV OUT[1], TEMP[1]
  9: MOV OUT[0], TEMP[0]
 10: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = fmul float %31, %12
  %41 = fmul float %32, %13
  %42 = fadd float %40, %41
  %43 = fmul float %33, %14
  %44 = fadd float %42, %43
  %45 = fmul float %34, %15
  %46 = fadd float %44, %45
  %47 = fmul float %31, %16
  %48 = fmul float %32, %17
  %49 = fadd float %47, %48
  %50 = fmul float %33, %18
  %51 = fadd float %49, %50
  %52 = fmul float %34, %19
  %53 = fadd float %51, %52
  %54 = fmul float %31, %20
  %55 = fmul float %32, %21
  %56 = fadd float %54, %55
  %57 = fmul float %33, %22
  %58 = fadd float %56, %57
  %59 = fmul float %34, %23
  %60 = fadd float %58, %59
  %61 = fmul float %31, %24
  %62 = fmul float %32, %25
  %63 = fadd float %61, %62
  %64 = fmul float %33, %26
  %65 = fadd float %63, %64
  %66 = fmul float %34, %27
  %67 = fadd float %65, %66
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %38, float %39, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %46, float %53, float %60, float %67)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
7e0a0280
bf8c0770
f800020f
05050201
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c202010d
bf8c007f
7e080204
d2100004
02020901
c202010c
bf8c007f
7e0a0204
d2820004
04120b00
c202010e
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020109
bf8c007f
7e0a0204
d2100005
02020b01
c2020108
bf8c007f
7e0c0204
d2820005
04160d00
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010b
bf8c007f
7e0c0204
d2820005
04160d03
c2020105
bf8c007f
7e0c0204
d2100006
02020d01
c2020104
bf8c007f
7e0e0204
d2820006
041a0f00
c2020106
bf8c007f
7e0e0204
d2820006
041a0f02
c2020107
bf8c007f
7e0e0204
d2820006
041a0f03
c2020101
bf8c007f
7e0e0204
d2100007
02020f01
c2020100
bf8c007f
7e100204
d2820007
041e1100
c2020102
bf8c007f
7e100204
d2820007
041e1102
c2000103
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..10]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    1.0000,     0.1000,     0.0000,     0.0000}
  0: MOV TEMP[0].y, IN[1].yyyy
  1: RCP TEMP[1].x, CONST[6].yyyy
  2: MUL TEMP[1].x, CONST[6].xxxx, TEMP[1].xxxx
  3: MAX TEMP[1].x, IN[1].xxxx, TEMP[1].xxxx
  4: ADD TEMP[2].x, CONST[6].xxxx, IMM[0].xxxx
  5: RCP TEMP[3].x, CONST[6].yyyy
  6: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
  7: MIN TEMP[0].x, TEMP[1].xxxx, TEMP[2].xxxx
  8: MOV TEMP[1].xy, IN[0].xyyy
  9: TEX TEMP[1].xyz, TEMP[1], SAMP[1], 2D
 10: MOV TEMP[0].xy, TEMP[0].xyyy
 11: TEX TEMP[0], TEMP[0], SAMP[2], 2D
 12: MUL TEMP[2], TEMP[1].xxxx, CONST[7]
 13: MAD TEMP[2], TEMP[1].yyyy, CONST[8], TEMP[2]
 14: MAD TEMP[1], TEMP[1].zzzz, CONST[9], TEMP[2]
 15: LRP TEMP[0].xyz, TEMP[0].wwww, TEMP[0], TEMP[1]
 16: MOV TEMP[0].xyz, TEMP[0].xyzx
 17: MOV TEMP[1].xy, IN[0].zwww
 18: TEX TEMP[1].x, TEMP[1], SAMP[0], 2D
 19: MUL TEMP[1].x, TEMP[1].xxxx, CONST[10].yyyy
 20: MOV TEMP[0].w, TEMP[1].xxxx
 21: MAD TEMP[0], CONST[10].xxxx, IMM[0].yyyz, TEMP[0]
 22: MOV OUT[0], TEMP[0]
 23: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 100)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 112)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 116)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 120)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 136)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 144)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 148)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 152)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 160)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 164)
  %35 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %36 = load <32 x i8> addrspace(2)* %35, !tbaa !0
  %37 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
  %39 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %40 = load <32 x i8> addrspace(2)* %39, !tbaa !0
  %41 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %44 = load <32 x i8> addrspace(2)* %43, !tbaa !0
  %45 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0
  %47 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %48 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %49 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %50 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %51 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %52 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %53 = fdiv float 1.000000e+00, %23
  %54 = fmul float %22, %53
  %55 = fcmp uge float %51, %54
  %56 = select i1 %55, float %51, float %54
  %57 = fadd float %22, 1.000000e+00
  %58 = fdiv float 1.000000e+00, %23
  %59 = fmul float %57, %58
  %60 = fcmp uge float %56, %59
  %61 = select i1 %60, float %59, float %56
  %62 = bitcast float %47 to i32
  %63 = bitcast float %48 to i32
  %64 = insertelement <2 x i32> undef, i32 %62, i32 0
  %65 = insertelement <2 x i32> %64, i32 %63, i32 1
  %66 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %65, <32 x i8> %40, <16 x i8> %42, i32 2)
  %67 = extractelement <4 x float> %66, i32 0
  %68 = extractelement <4 x float> %66, i32 1
  %69 = extractelement <4 x float> %66, i32 2
  %70 = bitcast float %61 to i32
  %71 = bitcast float %52 to i32
  %72 = insertelement <2 x i32> undef, i32 %70, i32 0
  %73 = insertelement <2 x i32> %72, i32 %71, i32 1
  %74 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %73, <32 x i8> %44, <16 x i8> %46, i32 2)
  %75 = extractelement <4 x float> %74, i32 0
  %76 = extractelement <4 x float> %74, i32 1
  %77 = extractelement <4 x float> %74, i32 2
  %78 = extractelement <4 x float> %74, i32 3
  %79 = fmul float %67, %24
  %80 = fmul float %67, %25
  %81 = fmul float %67, %26
  %82 = fmul float %68, %27
  %83 = fadd float %82, %79
  %84 = fmul float %68, %28
  %85 = fadd float %84, %80
  %86 = fmul float %68, %29
  %87 = fadd float %86, %81
  %88 = fmul float %69, %30
  %89 = fadd float %88, %83
  %90 = fmul float %69, %31
  %91 = fadd float %90, %85
  %92 = fmul float %69, %32
  %93 = fadd float %92, %87
  %94 = call float @llvm.AMDGPU.lrp(float %78, float %75, float %89)
  %95 = call float @llvm.AMDGPU.lrp(float %78, float %76, float %91)
  %96 = call float @llvm.AMDGPU.lrp(float %78, float %77, float %93)
  %97 = bitcast float %49 to i32
  %98 = bitcast float %50 to i32
  %99 = insertelement <2 x i32> undef, i32 %97, i32 0
  %100 = insertelement <2 x i32> %99, i32 %98, i32 1
  %101 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %100, <32 x i8> %36, <16 x i8> %38, i32 2)
  %102 = extractelement <4 x float> %101, i32 0
  %103 = fmul float %102, %34
  %104 = fmul float %33, 0x3FB99999A0000000
  %105 = fadd float %104, %94
  %106 = fmul float %33, 0x3FB99999A0000000
  %107 = fadd float %106, %95
  %108 = fmul float %33, 0x3FB99999A0000000
  %109 = fadd float %108, %96
  %110 = fmul float %33, 0.000000e+00
  %111 = fadd float %110, %103
  %112 = call i32 @llvm.SI.packf16(float %105, float %107)
  %113 = bitcast i32 %112 to float
  %114 = call i32 @llvm.SI.packf16(float %109, float %111)
  %115 = bitcast i32 %114 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %113, float %115, float %113, float %115)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840304
c0c60508
bf8c007f
f0800700
00430202
c0840100
bf8c0070
c200091d
bf8c007f
7e0a0200
d2100005
02020b02
c2000921
bf8c007f
7e0c0200
d2820005
04160d03
c2000925
bf8c007f
7e0c0200
d2820005
04160d04
c8180400
c8190401
c2000918
c2008919
bf8c007f
7e0e5401
10100e00
d00c000c
02021106
d2000006
00320d08
d2060008
0201e400
100e0f08
d00c0000
02020f06
d2000006
00020f06
c81c0500
c81d0501
c0860308
c0c80510
bf8c007f
f0800f00
00640606
bf8c0770
081412f2
100a0b0a
d2820005
04160f09
c2000928
7e1602ff
3dcccccd
bf8c007f
d2820005
04161600
c200891c
bf8c007f
7e180201
d210000c
02021902
c2008920
bf8c007f
7e1a0201
d282000c
04321b03
c2008924
bf8c007f
7e1a0201
d282000c
04321b04
1018190a
d282000c
04320d09
d282000c
04321600
5e0a0b0c
c200891e
bf8c007f
7e180201
d210000c
02021902
c2008922
bf8c007f
7e1a0201
d282000c
04321b03
c2008926
bf8c007f
7e1a0201
d2820002
04321b04
1004050a
d2820002
040a1109
d2820002
040a1600
c8100300
c8110301
c80c0200
c80d0201
c0860300
c0c80500
bf8c007f
f0800100
00640003
c2008929
bf8c0070
10000001
d2820000
04010000
5e000102
f8001c0f
00050005
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..10]
DCL TEMP[0..4], LOCAL
  0: RCP TEMP[0].x, CONST[4].xxxx
  1: MAD TEMP[0].x, IN[1].xxxx, TEMP[0].xxxx, CONST[4].zzzz
  2: RCP TEMP[1].x, CONST[4].yyyy
  3: MAD TEMP[1].x, IN[1].yyyy, TEMP[1].xxxx, CONST[4].wwww
  4: MOV TEMP[0].y, TEMP[1].xxxx
  5: RCP TEMP[1].x, CONST[6].yyyy
  6: ADD TEMP[2].x, IN[1].xxxx, -CONST[5].xxxx
  7: MUL TEMP[3].x, CONST[5].zzzz, CONST[6].yyyy
  8: RCP TEMP[3].x, TEMP[3].xxxx
  9: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
 10: MAD TEMP[1].x, CONST[6].xxxx, TEMP[1].xxxx, TEMP[2].xxxx
 11: RCP TEMP[2].x, CONST[6].wwww
 12: ADD TEMP[3].x, IN[1].yyyy, -CONST[5].yyyy
 13: MUL TEMP[4].x, CONST[5].wwww, CONST[6].wwww
 14: RCP TEMP[4].x, TEMP[4].xxxx
 15: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
 16: MAD TEMP[2].x, CONST[6].zzzz, TEMP[2].xxxx, TEMP[3].xxxx
 17: MOV TEMP[1].y, TEMP[2].xxxx
 18: DP4 TEMP[2].x, IN[0], CONST[0]
 19: DP4 TEMP[3].x, IN[0], CONST[1]
 20: MOV TEMP[2].y, TEMP[3].xxxx
 21: DP4 TEMP[3].x, IN[0], CONST[2]
 22: MOV TEMP[2].z, TEMP[3].xxxx
 23: DP4 TEMP[3].x, IN[0], CONST[3]
 24: MOV TEMP[2].w, TEMP[3].xxxx
 25: MOV TEMP[0].xy, TEMP[0].xyxx
 26: MOV TEMP[0].zw, IN[2].yyxy
 27: MOV TEMP[1].xy, TEMP[1].xyxx
 28: MOV OUT[2], TEMP[1]
 29: MOV OUT[0], TEMP[2]
 30: MOV OUT[1], TEMP[0]
 31: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 108)
  %40 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %41 = load <16 x i8> addrspace(2)* %40, !tbaa !0
  %42 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %41, i32 0, i32 %6)
  %43 = extractelement <4 x float> %42, i32 0
  %44 = extractelement <4 x float> %42, i32 1
  %45 = extractelement <4 x float> %42, i32 2
  %46 = extractelement <4 x float> %42, i32 3
  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %6)
  %50 = extractelement <4 x float> %49, i32 0
  %51 = extractelement <4 x float> %49, i32 1
  %52 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %53 = load <16 x i8> addrspace(2)* %52, !tbaa !0
  %54 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %53, i32 0, i32 %6)
  %55 = extractelement <4 x float> %54, i32 0
  %56 = extractelement <4 x float> %54, i32 1
  %57 = fdiv float 1.000000e+00, %28
  %58 = fmul float %50, %57
  %59 = fadd float %58, %30
  %60 = fdiv float 1.000000e+00, %29
  %61 = fmul float %51, %60
  %62 = fadd float %61, %31
  %63 = fdiv float 1.000000e+00, %37
  %64 = fsub float -0.000000e+00, %32
  %65 = fadd float %50, %64
  %66 = fmul float %34, %37
  %67 = fdiv float 1.000000e+00, %66
  %68 = fmul float %65, %67
  %69 = fmul float %36, %63
  %70 = fadd float %69, %68
  %71 = fdiv float 1.000000e+00, %39
  %72 = fsub float -0.000000e+00, %33
  %73 = fadd float %51, %72
  %74 = fmul float %35, %39
  %75 = fdiv float 1.000000e+00, %74
  %76 = fmul float %73, %75
  %77 = fmul float %38, %71
  %78 = fadd float %77, %76
  %79 = fmul float %43, %12
  %80 = fmul float %44, %13
  %81 = fadd float %79, %80
  %82 = fmul float %45, %14
  %83 = fadd float %81, %82
  %84 = fmul float %46, %15
  %85 = fadd float %83, %84
  %86 = fmul float %43, %16
  %87 = fmul float %44, %17
  %88 = fadd float %86, %87
  %89 = fmul float %45, %18
  %90 = fadd float %88, %89
  %91 = fmul float %46, %19
  %92 = fadd float %90, %91
  %93 = fmul float %43, %20
  %94 = fmul float %44, %21
  %95 = fadd float %93, %94
  %96 = fmul float %45, %22
  %97 = fadd float %95, %96
  %98 = fmul float %46, %23
  %99 = fadd float %97, %98
  %100 = fmul float %43, %24
  %101 = fmul float %44, %25
  %102 = fadd float %100, %101
  %103 = fmul float %45, %26
  %104 = fadd float %102, %103
  %105 = fmul float %46, %27
  %106 = fadd float %104, %105
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %59, float %62, float %55, float %56)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %70, float %78, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %85, float %92, float %99, float %106)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020113
bf8c007f
7e0a0204
c2020111
bf8c007f
7e0c5404
d2820005
04160d02
c2020112
bf8c007f
7e0c0204
c2020110
bf8c007f
7e0e5404
d2820006
041a0f01
c0840708
bf8c007f
e00c2000
80020700
bf8c0770
f800020f
08070506
c2020115
bf8c000f
7e0a0204
d2080005
02020b02
c2020117
c202811b
bf8c007f
7e0c0205
d2100006
02020c04
7e0c5506
100a0d05
c202011a
7e0c5405
bf8c007f
d2820005
04160c04
c2020114
bf8c007f
7e0c0204
d2080001
02020d01
c2020116
c2028119
bf8c007f
7e040205
d2100002
02020404
7e045502
10020501
c2020118
7e045405
bf8c007f
d2820001
04060404
7e040280
f800021f
02020501
c0820700
bf8c000f
e00c2000
80010000
c202010d
bf8c0070
7e080204
d2100004
02020901
c202010c
bf8c007f
7e0a0204
d2820004
04120b00
c202010e
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020109
bf8c007f
7e0a0204
d2100005
02020b01
c2020108
bf8c007f
7e0c0204
d2820005
04160d00
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010b
bf8c007f
7e0c0204
d2820005
04160d03
c2020105
bf8c007f
7e0c0204
d2100006
02020d01
c2020104
bf8c007f
7e0e0204
d2820006
041a0f00
c2020106
bf8c007f
7e0e0204
d2820006
041a0f02
c2020107
bf8c007f
7e0e0204
d2820006
041a0f03
c2020101
bf8c007f
7e0e0204
d2100007
02020f01
c2020100
bf8c007f
7e100204
d2820007
041e1100
c2020102
bf8c007f
7e100204
d2820007
041e1102
c2000103
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL IN[3], GENERIC[22], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL SAMP[4]
DCL SAMP[5]
DCL CONST[0..31]
DCL TEMP[0..8], LOCAL
IMM[0] FLT32 {   -0.5000,     0.5000,     1.0000,     0.0200}
IMM[1] FLT32 {    0.0039,     0.1000,     6.2832,     0.8000}
IMM[2] FLT32 {    0.2000,     1.2000, -160000.0000,     0.0000}
IMM[3] FLT32 {  200.0000,     3.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].x, IN[1].wwww
  1: MOV TEMP[0].yz, IN[2].yxyy
  2: MOV TEMP[1].xy, IN[2].zwzz
  3: MOV TEMP[1].z, IN[3].xxxx
  4: MOV TEMP[2].xy, IN[0].xyyy
  5: TEX TEMP[2], TEMP[2], SAMP[2], 2D
  6: RCP TEMP[3].x, CONST[27].xxxx
  7: MAD TEMP[3].x, IN[0].zzzz, TEMP[3].xxxx, CONST[27].zzzz
  8: RCP TEMP[4].x, CONST[27].yyyy
  9: MAD TEMP[4].x, IN[0].wwww, TEMP[4].xxxx, CONST[27].wwww
 10: MOV TEMP[3].y, TEMP[4].xxxx
 11: DP3 TEMP[4].x, IN[1].xyzz, IN[1].xyzz
 12: RSQ TEMP[4].x, TEMP[4].xxxx
 13: MUL TEMP[4].xyz, IN[1].xyzz, TEMP[4].xxxx
 14: DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[1].xyzz
 15: RSQ TEMP[5].x, TEMP[5].xxxx
 16: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[5].xxxx
 17: MOV TEMP[5].xy, IN[0].xyyy
 18: TEX TEMP[5].xyz, TEMP[5], SAMP[1], 2D
 19: ADD TEMP[5].xyz, TEMP[5].xzyy, IMM[0].xxxx
 20: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
 21: RSQ TEMP[6].x, TEMP[6].xxxx
 22: MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xxxx
 23: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[1].xyzz
 24: DP3 TEMP[7].x, TEMP[5].xyzz, TEMP[4].xyzz
 25: MOV TEMP[6].y, TEMP[7].xxxx
 26: MUL TEMP[7].xyz, TEMP[1].zxyy, TEMP[4].yzxx
 27: MAD TEMP[1].xyz, TEMP[1].yzxx, TEMP[4].zxyy, -TEMP[7].xyzz
 28: DP3 TEMP[1].x, TEMP[5].xyzz, TEMP[1].xyzz
 29: MOV TEMP[6].z, TEMP[1].xxxx
 30: DP3 TEMP[1].x, TEMP[6].xyzz, -CONST[17].xyzz
 31: MAD TEMP[1].x, TEMP[1].xxxx, IMM[0].yyyy, IMM[0].yyyy
 32: ADD TEMP[4].x, IN[1].wwww, IMM[0].yyyy
 33: RCP TEMP[5].x, CONST[16].xxxx
 34: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 35: ADD TEMP[5].x, IN[2].yyyy, IMM[0].yyyy
 36: RCP TEMP[7].x, CONST[16].yyyy
 37: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[7].xxxx
 38: MOV TEMP[4].y, TEMP[5].xxxx
 39: MOV TEMP[4].xy, TEMP[4].xyyy
 40: TEX TEMP[4].w, TEMP[4], SAMP[5], 2D
 41: ADD TEMP[5].xy, TEMP[0].xzzz, IMM[0].yyyy
 42: MUL TEMP[5].xy, TEMP[5].xyyy, IMM[1].xxxx
 43: MAD TEMP[5].xy, CONST[22].yyyy, IMM[0].wwww, TEMP[5].xyyy
 44: MOV TEMP[5].xy, TEMP[5].xyyy
 45: TEX TEMP[5].x, TEMP[5], SAMP[3], 2D
 46: MUL TEMP[7].x, CONST[22].yyyy, IMM[1].yyyy
 47: FRC TEMP[7].x, TEMP[7].xxxx
 48: ADD TEMP[5].x, TEMP[5].xxxx, TEMP[7].xxxx
 49: MUL TEMP[5].x, TEMP[5].xxxx, IMM[1].zzzz
 50: SIN TEMP[5].x, TEMP[5].xxxx
 51: MAD TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy, IMM[0].yyyy
 52: ADD_SAT TEMP[4].x, TEMP[4].wwww, TEMP[5].xxxx
 53: LRP TEMP[4].x, CONST[22].xxxx, TEMP[4].xxxx, IMM[0].zzzz
 54: ADD TEMP[5].xyz, CONST[18].xyzz, -TEMP[0].xyzz
 55: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 56: MAD TEMP[1].x, IMM[1].wwww, TEMP[1].xxxx, IMM[2].xxxx
 57: MUL TEMP[7].xyz, TEMP[2].xyzz, TEMP[2].wwww
 58: MOV TEMP[3].xy, TEMP[3].xyyy
 59: TEX TEMP[3].xyz, TEMP[3], SAMP[4], 2D
 60: ADD TEMP[8].x, IMM[0].zzzz, -TEMP[2].wwww
 61: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[8].xxxx
 62: MAD TEMP[2].xyz, TEMP[7].xyzz, TEMP[3].xyzz, TEMP[2].xyzz
 63: MUL TEMP[1].xyz, TEMP[1].xxxx, TEMP[2].xyzz
 64: MUL_SAT TEMP[1].xyz, TEMP[1].xyzz, IMM[2].yyyy
 65: DP3 TEMP[2].x, TEMP[5].xyzz, TEMP[5].xyzz
 66: ADD TEMP[2].x, TEMP[2].xxxx, IMM[2].zzzz
 67: MUL TEMP[2].x, TEMP[2].xxxx, IMM[2].wwww
 68: MIN TEMP[2].x, TEMP[2].xxxx, IMM[0].yyyy
 69: MOV_SAT TEMP[2].x, TEMP[2].xxxx
 70: DP3 TEMP[3].x, TEMP[5].xyzz, TEMP[5].xyzz
 71: RSQ TEMP[3].x, TEMP[3].xxxx
 72: MUL TEMP[3].y, TEMP[5].xyzz, TEMP[3].xxxx
 73: ADD TEMP[3].x, IMM[0].zzzz, -TEMP[3].yyyy
 74: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
 75: LRP TEMP[1].xyz, TEMP[2].xxxx, IMM[0].yyyy, TEMP[1].xyzz
 76: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[4].xxxx
 77: ADD TEMP[0].xyz, TEMP[0].xyzz, -CONST[18].xyzz
 78: DP3 TEMP[2].x, TEMP[0].xyzz, TEMP[0].xyzz
 79: RSQ TEMP[2].x, TEMP[2].xxxx
 80: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
 81: ADD TEMP[0].xyz, -TEMP[0].xyzz, -CONST[17].xyzz
 82: DP3 TEMP[2].x, TEMP[0].xyzz, TEMP[0].xyzz
 83: RSQ TEMP[2].x, TEMP[2].xxxx
 84: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
 85: DP3_SAT TEMP[0].x, TEMP[0].xyzz, TEMP[6].xyzz
 86: POW TEMP[0].x, TEMP[0].xxxx, IMM[3].xxxx
 87: MUL_SAT TEMP[0].x, TEMP[0].xxxx, IMM[3].yyyy
 88: MOV TEMP[2].xy, IN[0].xyyy
 89: TEX TEMP[2].x, TEMP[2], SAMP[0], 2D
 90: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[2].xxxx
 91: MAD_SAT TEMP[0].xyz, TEMP[0].xxxx, TEMP[4].xxxx, TEMP[1].xyzz
 92: MOV TEMP[1].w, IMM[0].zzzz
 93: MOV TEMP[1].xyz, TEMP[0].xyzx
 94: MOV OUT[0], TEMP[1]
 95: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 276)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 280)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 432)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 436)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 440)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 444)
  %36 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %37 = load <32 x i8> addrspace(2)* %36, !tbaa !0
  %38 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
  %40 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0
  %42 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
  %44 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %45 = load <32 x i8> addrspace(2)* %44, !tbaa !0
  %46 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0
  %48 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %49 = load <32 x i8> addrspace(2)* %48, !tbaa !0
  %50 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
  %52 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
  %53 = load <32 x i8> addrspace(2)* %52, !tbaa !0
  %54 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
  %56 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
  %57 = load <32 x i8> addrspace(2)* %56, !tbaa !0
  %58 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
  %59 = load <16 x i8> addrspace(2)* %58, !tbaa !0
  %60 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %61 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %62 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %63 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %64 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %65 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %66 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %67 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %68 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
  %69 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
  %70 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
  %71 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
  %72 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
  %73 = bitcast float %60 to i32
  %74 = bitcast float %61 to i32
  %75 = insertelement <2 x i32> undef, i32 %73, i32 0
  %76 = insertelement <2 x i32> %75, i32 %74, i32 1
  %77 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %76, <32 x i8> %45, <16 x i8> %47, i32 2)
  %78 = extractelement <4 x float> %77, i32 0
  %79 = extractelement <4 x float> %77, i32 1
  %80 = extractelement <4 x float> %77, i32 2
  %81 = extractelement <4 x float> %77, i32 3
  %82 = fdiv float 1.000000e+00, %32
  %83 = fmul float %62, %82
  %84 = fadd float %83, %34
  %85 = fdiv float 1.000000e+00, %33
  %86 = fmul float %63, %85
  %87 = fadd float %86, %35
  %88 = fmul float %64, %64
  %89 = fmul float %65, %65
  %90 = fadd float %89, %88
  %91 = fmul float %66, %66
  %92 = fadd float %90, %91
  %93 = call float @llvm.AMDGPU.rsq(float %92)
  %94 = fmul float %64, %93
  %95 = fmul float %65, %93
  %96 = fmul float %66, %93
  %97 = fmul float %70, %70
  %98 = fmul float %71, %71
  %99 = fadd float %98, %97
  %100 = fmul float %72, %72
  %101 = fadd float %99, %100
  %102 = call float @llvm.AMDGPU.rsq(float %101)
  %103 = fmul float %70, %102
  %104 = fmul float %71, %102
  %105 = fmul float %72, %102
  %106 = bitcast float %60 to i32
  %107 = bitcast float %61 to i32
  %108 = insertelement <2 x i32> undef, i32 %106, i32 0
  %109 = insertelement <2 x i32> %108, i32 %107, i32 1
  %110 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %109, <32 x i8> %41, <16 x i8> %43, i32 2)
  %111 = extractelement <4 x float> %110, i32 0
  %112 = extractelement <4 x float> %110, i32 1
  %113 = extractelement <4 x float> %110, i32 2
  %114 = fadd float %111, -5.000000e-01
  %115 = fadd float %113, -5.000000e-01
  %116 = fadd float %112, -5.000000e-01
  %117 = fmul float %114, %114
  %118 = fmul float %115, %115
  %119 = fadd float %118, %117
  %120 = fmul float %116, %116
  %121 = fadd float %119, %120
  %122 = call float @llvm.AMDGPU.rsq(float %121)
  %123 = fmul float %114, %122
  %124 = fmul float %115, %122
  %125 = fmul float %116, %122
  %126 = fmul float %123, %103
  %127 = fmul float %124, %104
  %128 = fadd float %127, %126
  %129 = fmul float %125, %105
  %130 = fadd float %128, %129
  %131 = fmul float %123, %94
  %132 = fmul float %124, %95
  %133 = fadd float %132, %131
  %134 = fmul float %125, %96
  %135 = fadd float %133, %134
  %136 = fmul float %105, %95
  %137 = fmul float %103, %96
  %138 = fmul float %104, %94
  %139 = fsub float -0.000000e+00, %136
  %140 = fmul float %104, %96
  %141 = fadd float %140, %139
  %142 = fsub float -0.000000e+00, %137
  %143 = fmul float %105, %94
  %144 = fadd float %143, %142
  %145 = fsub float -0.000000e+00, %138
  %146 = fmul float %103, %95
  %147 = fadd float %146, %145
  %148 = fmul float %123, %141
  %149 = fmul float %124, %144
  %150 = fadd float %149, %148
  %151 = fmul float %125, %147
  %152 = fadd float %150, %151
  %153 = fsub float -0.000000e+00, %24
  %154 = fsub float -0.000000e+00, %25
  %155 = fsub float -0.000000e+00, %26
  %156 = fmul float %130, %153
  %157 = fmul float %135, %154
  %158 = fadd float %157, %156
  %159 = fmul float %152, %155
  %160 = fadd float %158, %159
  %161 = fmul float %160, 5.000000e-01
  %162 = fadd float %161, 5.000000e-01
  %163 = fadd float %67, 5.000000e-01
  %164 = fdiv float 1.000000e+00, %22
  %165 = fmul float %163, %164
  %166 = fadd float %69, 5.000000e-01
  %167 = fdiv float 1.000000e+00, %23
  %168 = fmul float %166, %167
  %169 = bitcast float %165 to i32
  %170 = bitcast float %168 to i32
  %171 = insertelement <2 x i32> undef, i32 %169, i32 0
  %172 = insertelement <2 x i32> %171, i32 %170, i32 1
  %173 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %172, <32 x i8> %57, <16 x i8> %59, i32 2)
  %174 = extractelement <4 x float> %173, i32 3
  %175 = fadd float %67, 5.000000e-01
  %176 = fadd float %69, 5.000000e-01
  %177 = fmul float %175, 3.906250e-03
  %178 = fmul float %176, 3.906250e-03
  %179 = fmul float %31, 0x3F947AE140000000
  %180 = fadd float %179, %177
  %181 = fmul float %31, 0x3F947AE140000000
  %182 = fadd float %181, %178
  %183 = bitcast float %180 to i32
  %184 = bitcast float %182 to i32
  %185 = insertelement <2 x i32> undef, i32 %183, i32 0
  %186 = insertelement <2 x i32> %185, i32 %184, i32 1
  %187 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %186, <32 x i8> %49, <16 x i8> %51, i32 2)
  %188 = extractelement <4 x float> %187, i32 0
  %189 = fmul float %31, 0x3FB99999A0000000
  %190 = call float @llvm.AMDIL.fraction.(float %189)
  %191 = fadd float %188, %190
  %192 = fmul float %191, 0x401921FB60000000
  %193 = call float @llvm.sin.f32(float %192)
  %194 = fmul float %193, 0x3FB99999A0000000
  %195 = fadd float %194, 5.000000e-01
  %196 = fadd float %174, %195
  %197 = call float @llvm.AMDIL.clamp.(float %196, float 0.000000e+00, float 1.000000e+00)
  %198 = call float @llvm.AMDGPU.lrp(float %30, float %197, float 1.000000e+00)
  %199 = fsub float -0.000000e+00, %67
  %200 = fadd float %27, %199
  %201 = fsub float -0.000000e+00, %68
  %202 = fadd float %28, %201
  %203 = fsub float -0.000000e+00, %69
  %204 = fadd float %29, %203
  %205 = fmul float %162, %162
  %206 = fmul float 0x3FE99999A0000000, %205
  %207 = fadd float %206, 0x3FC99999A0000000
  %208 = fmul float %78, %81
  %209 = fmul float %79, %81
  %210 = fmul float %80, %81
  %211 = bitcast float %84 to i32
  %212 = bitcast float %87 to i32
  %213 = insertelement <2 x i32> undef, i32 %211, i32 0
  %214 = insertelement <2 x i32> %213, i32 %212, i32 1
  %215 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %214, <32 x i8> %53, <16 x i8> %55, i32 2)
  %216 = extractelement <4 x float> %215, i32 0
  %217 = extractelement <4 x float> %215, i32 1
  %218 = extractelement <4 x float> %215, i32 2
  %219 = fsub float -0.000000e+00, %81
  %220 = fadd float 1.000000e+00, %219
  %221 = fmul float %78, %220
  %222 = fmul float %79, %220
  %223 = fmul float %80, %220
  %224 = fmul float %208, %216
  %225 = fadd float %224, %221
  %226 = fmul float %209, %217
  %227 = fadd float %226, %222
  %228 = fmul float %210, %218
  %229 = fadd float %228, %223
  %230 = fmul float %207, %225
  %231 = fmul float %207, %227
  %232 = fmul float %207, %229
  %233 = fmul float %230, 0x3FF3333340000000
  %234 = fmul float %231, 0x3FF3333340000000
  %235 = fmul float %232, 0x3FF3333340000000
  %236 = call float @llvm.AMDIL.clamp.(float %233, float 0.000000e+00, float 1.000000e+00)
  %237 = call float @llvm.AMDIL.clamp.(float %234, float 0.000000e+00, float 1.000000e+00)
  %238 = call float @llvm.AMDIL.clamp.(float %235, float 0.000000e+00, float 1.000000e+00)
  %239 = fmul float %200, %200
  %240 = fmul float %202, %202
  %241 = fadd float %240, %239
  %242 = fmul float %204, %204
  %243 = fadd float %241, %242
  %244 = fadd float %243, -1.600000e+05
  %245 = fmul float %244, 0x3EAA36E2E0000000
  %246 = fcmp uge float %245, 5.000000e-01
  %247 = select i1 %246, float 5.000000e-01, float %245
  %248 = call float @llvm.AMDIL.clamp.(float %247, float 0.000000e+00, float 1.000000e+00)
  %249 = fmul float %200, %200
  %250 = fmul float %202, %202
  %251 = fadd float %250, %249
  %252 = fmul float %204, %204
  %253 = fadd float %251, %252
  %254 = call float @llvm.AMDGPU.rsq(float %253)
  %255 = fmul float %202, %254
  %256 = fsub float -0.000000e+00, %255
  %257 = fadd float 1.000000e+00, %256
  %258 = fmul float %248, %257
  %259 = call float @llvm.AMDGPU.lrp(float %258, float 5.000000e-01, float %236)
  %260 = call float @llvm.AMDGPU.lrp(float %258, float 5.000000e-01, float %237)
  %261 = call float @llvm.AMDGPU.lrp(float %258, float 5.000000e-01, float %238)
  %262 = fmul float %259, %198
  %263 = fmul float %260, %198
  %264 = fmul float %261, %198
  %265 = fsub float -0.000000e+00, %27
  %266 = fadd float %67, %265
  %267 = fsub float -0.000000e+00, %28
  %268 = fadd float %68, %267
  %269 = fsub float -0.000000e+00, %29
  %270 = fadd float %69, %269
  %271 = fmul float %266, %266
  %272 = fmul float %268, %268
  %273 = fadd float %272, %271
  %274 = fmul float %270, %270
  %275 = fadd float %273, %274
  %276 = call float @llvm.AMDGPU.rsq(float %275)
  %277 = fmul float %266, %276
  %278 = fmul float %268, %276
  %279 = fmul float %270, %276
  %280 = fsub float -0.000000e+00, %277
  %281 = fsub float -0.000000e+00, %24
  %282 = fadd float %280, %281
  %283 = fsub float -0.000000e+00, %278
  %284 = fsub float -0.000000e+00, %25
  %285 = fadd float %283, %284
  %286 = fsub float -0.000000e+00, %279
  %287 = fsub float -0.000000e+00, %26
  %288 = fadd float %286, %287
  %289 = fmul float %282, %282
  %290 = fmul float %285, %285
  %291 = fadd float %290, %289
  %292 = fmul float %288, %288
  %293 = fadd float %291, %292
  %294 = call float @llvm.AMDGPU.rsq(float %293)
  %295 = fmul float %282, %294
  %296 = fmul float %285, %294
  %297 = fmul float %288, %294
  %298 = fmul float %295, %130
  %299 = fmul float %296, %135
  %300 = fadd float %299, %298
  %301 = fmul float %297, %152
  %302 = fadd float %300, %301
  %303 = call float @llvm.AMDIL.clamp.(float %302, float 0.000000e+00, float 1.000000e+00)
  %304 = call float @llvm.pow.f32(float %303, float 2.000000e+02)
  %305 = fmul float %304, 3.000000e+00
  %306 = call float @llvm.AMDIL.clamp.(float %305, float 0.000000e+00, float 1.000000e+00)
  %307 = bitcast float %60 to i32
  %308 = bitcast float %61 to i32
  %309 = insertelement <2 x i32> undef, i32 %307, i32 0
  %310 = insertelement <2 x i32> %309, i32 %308, i32 1
  %311 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %310, <32 x i8> %37, <16 x i8> %39, i32 2)
  %312 = extractelement <4 x float> %311, i32 0
  %313 = fmul float %306, %312
  %314 = fmul float %313, %198
  %315 = fadd float %314, %262
  %316 = fmul float %313, %198
  %317 = fadd float %316, %263
  %318 = fmul float %313, %198
  %319 = fadd float %318, %264
  %320 = call float @llvm.AMDIL.clamp.(float %315, float 0.000000e+00, float 1.000000e+00)
  %321 = call float @llvm.AMDIL.clamp.(float %317, float 0.000000e+00, float 1.000000e+00)
  %322 = call float @llvm.AMDIL.clamp.(float %319, float 0.000000e+00, float 1.000000e+00)
  %323 = call i32 @llvm.SI.packf16(float %320, float %321)
  %324 = bitcast i32 %323 to float
  %325 = call i32 @llvm.SI.packf16(float %322, float 1.000000e+00)
  %326 = bitcast i32 %325 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %324, float %326, float %324, float %326)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c8080500
c8090501
c80c0400
c80d0401
10080703
d2820004
04120502
c8140600
c8150601
d2820004
04120b05
7e085b04
100a0905
c8180b00
c8190b01
c81c0a00
c81d0a01
10100f07
d2820008
04220d06
c8240c00
c8250c01
d2820008
04221309
7e105b08
100e1107
10140b07
10060903
10121109
10160709
0814150b
10040902
10080509
100c1106
10100b06
08080908
c8300100
c8310101
c82c0000
c82d0001
c0840304
c0c60508
bf8c007f
f0800700
00430d0b
bf8c0770
d2060008
0201e30f
d2060010
0201e30d
10222110
d2820011
04461108
d206000d
0201e30e
d282000e
04461b0d
7e1c5b0e
101e1d10
1008090f
10101d08
d2820004
04121508
10140706
10200507
08141510
101a1d0d
d2820004
0412150d
1006070f
d2820002
040e0508
d2820002
040a0b0d
10060f0f
d2820003
040e0d08
d2820003
040e130d
c8140800
c8150801
c0840100
bf8c007f
c2000949
bf8c007f
0a0c0a00
c81c0700
c81d0701
c2008948
bf8c007f
0a100e01
10121108
d2820009
04260d06
c8280900
c8290901
c203894a
bf8c007f
0a1a1407
d2820009
04261b0d
7e125b09
100c1306
d2060006
22010106
c2060945
bf8c007f
0a0c0c0c
10101308
d2060008
22010108
c2068944
bf8c007f
0a10100d
101c1108
d282000e
043a0d06
1012130d
d2060009
22010109
c2070946
bf8c007f
0a12120e
d282000d
043a1309
7e1a5b0d
10101b08
10100708
100c1b06
d2820006
04220506
10101b09
d2820006
041a0908
d2060806
02010106
7e0c4f06
0e0c0cff
43480000
7e0c4b06
100c0cff
40400000
d2060806
02010106
c0880300
c0ca0500
bf8c007f
f0800100
0085080b
bf8c0770
100c1106
1008080e
1006060d
d2060008
2201000c
10041102
08040702
08040902
d2820002
03c1e102
10040502
7e0602ff
3e4ccccd
7e0802ff
3f4ccccd
d2820002
040e0902
c0860308
c0c80510
bf8c007f
f0800f00
00640b0b
bf8c0770
10061d0c
08081cf2
1010090c
c8240300
c8250301
c206096f
c206896d
bf8c007f
7e1e540d
d2820010
00321f09
c8240200
c8250201
c203096e
c206096c
bf8c007f
7e00540c
d282000f
001a0109
c0860310
c0c80520
bf8c007f
f0800700
00640f0f
bf8c0770
d2820000
04222103
10000102
100000ff
3f99999a
d2060800
02010100
08020a00
08060e01
10060703
d2820003
040e0301
080a1407
d2820003
040e0b05
060a06ff
c81c4000
100a0aff
3551b717
d00c0000
0201e105
d2000005
0001e105
d2060805
02010105
7e065b03
10020701
080202f2
10020305
080602f2
10000103
d2820000
0401e101
060a14f0
10100aff
3b800000
c2000959
7e1202ff
3ca3d70a
bf8c007f
d2820013
04221200
060e0ef0
10100eff
3b800000
d2820012
04221200
c086030c
c0c80518
bf8c007f
f0800100
00640812
7e1202ff
3dcccccd
10141200
7e14410a
bf8c0770
06101508
101010ff
40c90fdb
101010ff
3e22f983
7e106b08
d2820008
03c21308
c2000941
bf8c007f
7e125400
10141305
c2000940
bf8c007f
7e0a5400
10120b07
c0800314
c0c60528
bf8c007f
f0800800
00030509
bf8c0770
060a1105
d2060805
02010105
c2000958
bf8c007f
d2080007
020000f2
d2820005
041e0a00
10000b00
d2820000
04020b06
d2060800
02010100
100e1d0b
1010090b
d2820007
04221f07
100e0f02
100e0eff
3f99999a
d2060807
02010107
100e0f03
d2820007
041de101
100e0b07
d2820007
041e0b06
d2060807
02010107
5e000107
100e1d0d
1008090d
d2820004
04122307
10040902
100404ff
3f99999a
d2060802
02010102
10040503
d2820001
0409e101
10020b01
d2820001
04060b06
d2060801
02010101
d25e0001
0201e501
f8001c0f
01000100
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL OUT[3], GENERIC[21]
DCL OUT[4], GENERIC[22]
DCL CONST[0..31]
DCL TEMP[0..5], LOCAL
IMM[0] FLT32 {    1.0000,     0.0020,     0.3500,     0.4500}
IMM[1] FLT32 {    2.2000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MUL TEMP[1].xyz, IN[0].xyzz, CONST[31].xxxx
  2: MAD TEMP[2].x, CONST[18].yyyy, IMM[0].yyyy, IMM[0].zzzz
  3: MAX TEMP[2].x, TEMP[2].xxxx, IMM[0].wwww
  4: MIN TEMP[2].x, TEMP[2].xxxx, IMM[1].xxxx
  5: MUL TEMP[0].xyz, TEMP[1].xyzz, TEMP[2].xxxx
  6: MOV TEMP[1].x, CONST[4].xxxx
  7: MOV TEMP[1].y, CONST[5].xxxx
  8: MOV TEMP[1].z, CONST[6].xxxx
  9: MOV TEMP[1].w, IMM[1].yyyy
 10: MOV TEMP[2].x, CONST[4].yyyy
 11: MOV TEMP[2].y, CONST[5].yyyy
 12: MOV TEMP[2].z, CONST[6].yyyy
 13: MOV TEMP[2].w, IMM[1].yyyy
 14: MOV TEMP[3].x, CONST[4].zzzz
 15: MOV TEMP[3].y, CONST[5].zzzz
 16: MOV TEMP[3].z, CONST[6].zzzz
 17: MOV TEMP[3].w, IMM[1].yyyy
 18: DP4 TEMP[4].x, TEMP[0], TEMP[1]
 19: DP4 TEMP[5].x, TEMP[0], TEMP[2]
 20: MOV TEMP[4].y, TEMP[5].xxxx
 21: DP4 TEMP[0].x, TEMP[0], TEMP[3]
 22: MOV TEMP[4].z, TEMP[0].xxxx
 23: MOV TEMP[4].w, IMM[0].xxxx
 24: DP4 TEMP[0].x, TEMP[4], CONST[23]
 25: DP4 TEMP[5].x, TEMP[4], CONST[24]
 26: MOV TEMP[0].y, TEMP[5].xxxx
 27: DP4 TEMP[5].x, TEMP[4], CONST[25]
 28: MOV TEMP[0].z, TEMP[5].xxxx
 29: DP4 TEMP[4].x, TEMP[4], CONST[26]
 30: MOV TEMP[0].w, TEMP[4].xxxx
 31: DP3 TEMP[4].x, IN[1].xyzz, TEMP[1].xyzz
 32: DP3 TEMP[5].x, IN[1].xyzz, TEMP[2].xyzz
 33: MOV TEMP[4].y, TEMP[5].xxxx
 34: DP3 TEMP[5].x, IN[1].xyzz, TEMP[3].xyzz
 35: MOV TEMP[4].z, TEMP[5].xxxx
 36: DP3 TEMP[1].x, IN[2].xyzz, TEMP[1].xyzz
 37: DP3 TEMP[2].x, IN[2].xyzz, TEMP[2].xyzz
 38: MOV TEMP[1].y, TEMP[2].xxxx
 39: DP3 TEMP[2].x, IN[2].xyzz, TEMP[3].xyzz
 40: MOV TEMP[1].z, TEMP[2].xxxx
 41: DP4 TEMP[2].x, TEMP[0], CONST[0]
 42: DP4 TEMP[3].x, TEMP[0], CONST[1]
 43: MOV TEMP[2].y, TEMP[3].xxxx
 44: DP4 TEMP[3].x, TEMP[0], CONST[2]
 45: MOV TEMP[2].z, TEMP[3].xxxx
 46: DP4 TEMP[3].x, TEMP[0], CONST[3]
 47: MOV TEMP[2].w, TEMP[3].xxxx
 48: DP3 TEMP[3].x, TEMP[1].xyzz, TEMP[1].xyzz
 49: RSQ TEMP[3].x, TEMP[3].xxxx
 50: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[3].xxxx
 51: MUL TEMP[1].xyz, TEMP[1].xyzz, IN[2].wwww
 52: MOV TEMP[3].xy, IN[3].xyxx
 53: MOV TEMP[3].zw, IN[4].yyxy
 54: DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz
 55: RSQ TEMP[5].x, TEMP[5].xxxx
 56: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xxxx
 57: MOV TEMP[4].w, TEMP[0].xxxx
 58: MOV TEMP[0].xy, TEMP[0].yzyy
 59: MOV TEMP[0].zw, TEMP[1].yyxy
 60: MOV TEMP[1].x, TEMP[1].zzzz
 61: MOV OUT[4], TEMP[1]
 62: MOV OUT[3], TEMP[0]
 63: MOV OUT[2], TEMP[4]
 64: MOV OUT[0], TEMP[2]
 65: MOV OUT[1], TEMP[3]
 66: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 292)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 368)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 372)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 376)
  %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 380)
  %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 384)
  %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 388)
  %44 = call float @llvm.SI.load.const(<16 x i8> %11, i32 392)
  %45 = call float @llvm.SI.load.const(<16 x i8> %11, i32 396)
  %46 = call float @llvm.SI.load.const(<16 x i8> %11, i32 400)
  %47 = call float @llvm.SI.load.const(<16 x i8> %11, i32 404)
  %48 = call float @llvm.SI.load.const(<16 x i8> %11, i32 408)
  %49 = call float @llvm.SI.load.const(<16 x i8> %11, i32 412)
  %50 = call float @llvm.SI.load.const(<16 x i8> %11, i32 416)
  %51 = call float @llvm.SI.load.const(<16 x i8> %11, i32 420)
  %52 = call float @llvm.SI.load.const(<16 x i8> %11, i32 424)
  %53 = call float @llvm.SI.load.const(<16 x i8> %11, i32 428)
  %54 = call float @llvm.SI.load.const(<16 x i8> %11, i32 496)
  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %6)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = extractelement <4 x float> %57, i32 2
  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %6)
  %64 = extractelement <4 x float> %63, i32 0
  %65 = extractelement <4 x float> %63, i32 1
  %66 = extractelement <4 x float> %63, i32 2
  %67 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
  %69 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %6)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = extractelement <4 x float> %69, i32 2
  %73 = extractelement <4 x float> %69, i32 3
  %74 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
  %75 = load <16 x i8> addrspace(2)* %74, !tbaa !0
  %76 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %75, i32 0, i32 %6)
  %77 = extractelement <4 x float> %76, i32 0
  %78 = extractelement <4 x float> %76, i32 1
  %79 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
  %80 = load <16 x i8> addrspace(2)* %79, !tbaa !0
  %81 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %80, i32 0, i32 %6)
  %82 = extractelement <4 x float> %81, i32 0
  %83 = extractelement <4 x float> %81, i32 1
  %84 = fmul float %58, %54
  %85 = fmul float %59, %54
  %86 = fmul float %60, %54
  %87 = fmul float %37, 0x3F60624DE0000000
  %88 = fadd float %87, 0x3FD6666660000000
  %89 = fcmp uge float %88, 0x3FDCCCCCC0000000
  %90 = select i1 %89, float %88, float 0x3FDCCCCCC0000000
  %91 = fcmp uge float %90, 0x40019999A0000000
  %92 = select i1 %91, float 0x40019999A0000000, float %90
  %93 = fmul float %84, %92
  %94 = fmul float %85, %92
  %95 = fmul float %86, %92
  %96 = fmul float %93, %28
  %97 = fmul float %94, %31
  %98 = fadd float %96, %97
  %99 = fmul float %95, %34
  %100 = fadd float %98, %99
  %101 = fmul float 1.000000e+00, 0.000000e+00
  %102 = fadd float %100, %101
  %103 = fmul float %93, %29
  %104 = fmul float %94, %32
  %105 = fadd float %103, %104
  %106 = fmul float %95, %35
  %107 = fadd float %105, %106
  %108 = fmul float 1.000000e+00, 0.000000e+00
  %109 = fadd float %107, %108
  %110 = fmul float %93, %30
  %111 = fmul float %94, %33
  %112 = fadd float %110, %111
  %113 = fmul float %95, %36
  %114 = fadd float %112, %113
  %115 = fmul float 1.000000e+00, 0.000000e+00
  %116 = fadd float %114, %115
  %117 = fmul float %102, %38
  %118 = fmul float %109, %39
  %119 = fadd float %117, %118
  %120 = fmul float %116, %40
  %121 = fadd float %119, %120
  %122 = fmul float 1.000000e+00, %41
  %123 = fadd float %121, %122
  %124 = fmul float %102, %42
  %125 = fmul float %109, %43
  %126 = fadd float %124, %125
  %127 = fmul float %116, %44
  %128 = fadd float %126, %127
  %129 = fmul float 1.000000e+00, %45
  %130 = fadd float %128, %129
  %131 = fmul float %102, %46
  %132 = fmul float %109, %47
  %133 = fadd float %131, %132
  %134 = fmul float %116, %48
  %135 = fadd float %133, %134
  %136 = fmul float 1.000000e+00, %49
  %137 = fadd float %135, %136
  %138 = fmul float %102, %50
  %139 = fmul float %109, %51
  %140 = fadd float %138, %139
  %141 = fmul float %116, %52
  %142 = fadd float %140, %141
  %143 = fmul float 1.000000e+00, %53
  %144 = fadd float %142, %143
  %145 = fmul float %64, %28
  %146 = fmul float %65, %31
  %147 = fadd float %146, %145
  %148 = fmul float %66, %34
  %149 = fadd float %147, %148
  %150 = fmul float %64, %29
  %151 = fmul float %65, %32
  %152 = fadd float %151, %150
  %153 = fmul float %66, %35
  %154 = fadd float %152, %153
  %155 = fmul float %64, %30
  %156 = fmul float %65, %33
  %157 = fadd float %156, %155
  %158 = fmul float %66, %36
  %159 = fadd float %157, %158
  %160 = fmul float %70, %28
  %161 = fmul float %71, %31
  %162 = fadd float %161, %160
  %163 = fmul float %72, %34
  %164 = fadd float %162, %163
  %165 = fmul float %70, %29
  %166 = fmul float %71, %32
  %167 = fadd float %166, %165
  %168 = fmul float %72, %35
  %169 = fadd float %167, %168
  %170 = fmul float %70, %30
  %171 = fmul float %71, %33
  %172 = fadd float %171, %170
  %173 = fmul float %72, %36
  %174 = fadd float %172, %173
  %175 = fmul float %123, %12
  %176 = fmul float %130, %13
  %177 = fadd float %175, %176
  %178 = fmul float %137, %14
  %179 = fadd float %177, %178
  %180 = fmul float %144, %15
  %181 = fadd float %179, %180
  %182 = fmul float %123, %16
  %183 = fmul float %130, %17
  %184 = fadd float %182, %183
  %185 = fmul float %137, %18
  %186 = fadd float %184, %185
  %187 = fmul float %144, %19
  %188 = fadd float %186, %187
  %189 = fmul float %123, %20
  %190 = fmul float %130, %21
  %191 = fadd float %189, %190
  %192 = fmul float %137, %22
  %193 = fadd float %191, %192
  %194 = fmul float %144, %23
  %195 = fadd float %193, %194
  %196 = fmul float %123, %24
  %197 = fmul float %130, %25
  %198 = fadd float %196, %197
  %199 = fmul float %137, %26
  %200 = fadd float %198, %199
  %201 = fmul float %144, %27
  %202 = fadd float %200, %201
  %203 = fmul float %164, %164
  %204 = fmul float %169, %169
  %205 = fadd float %204, %203
  %206 = fmul float %174, %174
  %207 = fadd float %205, %206
  %208 = call float @llvm.AMDGPU.rsq(float %207)
  %209 = fmul float %164, %208
  %210 = fmul float %169, %208
  %211 = fmul float %174, %208
  %212 = fmul float %209, %73
  %213 = fmul float %210, %73
  %214 = fmul float %211, %73
  %215 = fmul float %149, %149
  %216 = fmul float %154, %154
  %217 = fadd float %216, %215
  %218 = fmul float %159, %159
  %219 = fadd float %217, %218
  %220 = call float @llvm.AMDGPU.rsq(float %219)
  %221 = fmul float %149, %220
  %222 = fmul float %154, %220
  %223 = fmul float %159, %220
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %77, float %78, float %82, float %83)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %221, float %222, float %223, float %123)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %130, float %137, float %212, float %213)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %214, float %213, float %214, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %181, float %188, float %195, float %202)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840710
bf8c007f
e00c2000
80020100
c084070c
bf8c0070
e00c2000
80020500
bf8c0770
f800020f
02010605
c0800100
bf8c000f
c2020149
7e0202ff
3eb33333
7e0402ff
3b03126f
bf8c007f
d2820001
04060404
7e0402ff
3ee66666
d00c0004
02020501
d2000001
00120302
7e0402ff
400ccccd
d00c0004
02020501
d2000001
00120501
c0840700
bf8c007f
e00c2000
80020200
c202017c
bf8c0070
7e0c0204
d2100007
02020d02
100e0307
d2100008
02020d03
10100308
c2020115
bf8c007f
10121004
c2028111
bf8c007f
d2820009
04240b07
d2100002
02020d04
10020302
c2040119
bf8c007f
d2820002
04241101
06040480
c204815d
bf8c007f
10060409
c2048114
bf8c007f
10081009
c2050110
bf8c007f
d2820004
04101507
c2058118
bf8c007f
d2820004
04101701
06080880
c206015c
bf8c007f
d2820003
040c1904
c2060116
bf8c007f
100a100c
c2068112
bf8c007f
d2820005
04141b07
c207011a
bf8c007f
d2820001
04141d01
06020280
c207815e
bf8c007f
d2820003
040c1f01
c207815f
bf8c007f
0606060f
c0880704
bf8c007f
e00c2000
80040500
7e120205
bf8c0770
d210000a
02021305
7e160204
d282000a
042a1706
7e180208
d282000a
042a1907
7e1a020a
d210000e
02021b05
7e1e0209
d282000e
043a1f06
7e20020b
d282000e
043a2107
10221d0e
d2820011
0446150a
7e24020d
d2100013
02022505
7e28020c
d2820013
044e2906
7e2a020e
d2820005
044e2b07
d2820006
04460b05
7e0c5b06
100a0d05
100e0d0a
100c0d0e
f800021f
03050706
c2020165
bf8c000f
100a0404
c2020164
bf8c007f
d2820005
04140904
c2020166
bf8c007f
d2820005
04140901
c2020167
bf8c007f
060a0a04
c2020161
bf8c007f
100c0404
c2020160
bf8c007f
d2820006
04180904
c2020162
bf8c007f
d2820006
04180901
c2020163
bf8c007f
060c0c04
c0820708
bf8c007f
e00c2000
80011600
bf8c0770
d2100000
02021316
d2820000
04021717
d2820000
04021918
d2100007
02021b16
d2820007
041e1f17
d2820007
041e2118
10100f07
d2820008
04220100
d2100009
02022516
d2820009
04262917
d2820009
04262b18
d2820008
04221309
7e105b08
10001100
10003300
100e1107
100e3307
f800022f
00070506
bf8c070f
100e1109
100e3307
7e100280
f800023f
08070007
c202010d
bf8c000f
10000c04
c202010c
bf8c007f
d2820000
04000903
c202010e
bf8c007f
d2820000
04000905
c2020169
bf8c007f
10040404
c2020168
bf8c007f
d2820002
04080904
c202016a
bf8c007f
d2820001
04080901
c202016b
bf8c007f
06020204
c202010f
bf8c007f
d2820000
04000901
c2020109
bf8c007f
10040c04
c2020108
bf8c007f
d2820002
04080903
c202010a
bf8c007f
d2820002
04080905
c202010b
bf8c007f
d2820002
04080901
c2020105
bf8c007f
10080c04
c2020104
bf8c007f
d2820004
04100903
c2020106
bf8c007f
d2820004
04100905
c2020107
bf8c007f
d2820004
04100901
c2020101
bf8c007f
100c0c04
c2020100
bf8c007f
d2820003
04180903
c2020102
bf8c007f
d2820003
040c0905
c2000103
bf8c007f
d2820001
040c0101
f80008cf
00020401
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[0..31]
DCL TEMP[0..7], LOCAL
IMM[0] FLT32 {    0.5000,     0.8000,     0.2000,     1.2000}
IMM[1] FLT32 {    1.0000,     0.0200,     0.0039,     0.1000}
IMM[2] FLT32 {    6.2832, -160000.0000,     0.0000,   200.0000}
IMM[3] FLT32 {    3.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].zwzz
  1: MOV TEMP[0].z, IN[1].xxxx
  2: MOV TEMP[1].xy, IN[0].xyyy
  3: TEX TEMP[1], TEMP[1], SAMP[1], 2D
  4: MOV TEMP[2].w, TEMP[1].wwww
  5: MOV TEMP[3].xy, IN[0].xyyy
  6: TEX TEMP[3], TEMP[3], SAMP[0], 2D
  7: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz
  8: RSQ TEMP[4].x, TEMP[4].xxxx
  9: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[4].xxxx
 10: MUL TEMP[4].xyz, TEMP[3].xxxx, CONST[28].xyzz
 11: MUL TEMP[4].xyz, TEMP[1].xyzz, TEMP[4].xyzz
 12: LRP TEMP[1].xyz, TEMP[3].xxxx, TEMP[4].xyzz, TEMP[1].xyzz
 13: MUL TEMP[4].xyz, TEMP[3].yyyy, CONST[29].xyzz
 14: MUL TEMP[4].xyz, TEMP[1].xyzz, TEMP[4].xyzz
 15: LRP TEMP[1].xyz, TEMP[3].yyyy, TEMP[4].xyzz, TEMP[1].xyzz
 16: MUL TEMP[4].xyz, TEMP[3].zzzz, CONST[30].xyzz
 17: MUL TEMP[4].xyz, TEMP[1].xyzz, TEMP[4].xyzz
 18: LRP TEMP[2].xyz, TEMP[3].zzzz, TEMP[4].xyzz, TEMP[1].xyzz
 19: DP3 TEMP[1].x, TEMP[0].xyzz, -CONST[17].xyzz
 20: MAD TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx, IMM[0].xxxx
 21: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx
 22: MAD TEMP[1].x, IMM[0].yyyy, TEMP[1].xxxx, IMM[0].zzzz
 23: MUL TEMP[1].xyz, TEMP[1].xxxx, TEMP[2].xyzz
 24: MUL_SAT TEMP[1].xyz, TEMP[1].xyzz, IMM[0].wwww
 25: ADD TEMP[4].x, IN[1].yyyy, IMM[0].xxxx
 26: RCP TEMP[5].x, CONST[16].xxxx
 27: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
 28: ADD TEMP[5].x, IN[1].wwww, IMM[0].xxxx
 29: RCP TEMP[6].x, CONST[16].yyyy
 30: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 31: MOV TEMP[4].y, TEMP[5].xxxx
 32: MOV TEMP[4].xy, TEMP[4].xyyy
 33: TEX TEMP[4].w, TEMP[4], SAMP[3], 2D
 34: ADD TEMP[5].xy, IN[1].ywww, IMM[0].xxxx
 35: MUL TEMP[5].xy, TEMP[5].xyyy, IMM[1].zzzz
 36: MAD TEMP[5].xy, CONST[22].yyyy, IMM[1].yyyy, TEMP[5].xyyy
 37: MOV TEMP[5].xy, TEMP[5].xyyy
 38: TEX TEMP[5].x, TEMP[5], SAMP[2], 2D
 39: MUL TEMP[6].x, CONST[22].yyyy, IMM[1].wwww
 40: FRC TEMP[6].x, TEMP[6].xxxx
 41: ADD TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 42: MUL TEMP[5].x, TEMP[5].xxxx, IMM[2].xxxx
 43: SIN TEMP[5].x, TEMP[5].xxxx
 44: MAD TEMP[5].x, TEMP[5].xxxx, IMM[1].wwww, IMM[0].xxxx
 45: ADD_SAT TEMP[4].x, TEMP[4].wwww, TEMP[5].xxxx
 46: LRP TEMP[4].x, CONST[22].xxxx, TEMP[4].xxxx, IMM[1].xxxx
 47: ADD TEMP[5].xyz, CONST[18].xyzz, -IN[1].yzww
 48: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
 49: ADD TEMP[6].x, TEMP[6].xxxx, IMM[2].yyyy
 50: MUL TEMP[6].x, TEMP[6].xxxx, IMM[2].zzzz
 51: MIN TEMP[6].x, TEMP[6].xxxx, IMM[0].xxxx
 52: MOV_SAT TEMP[6].x, TEMP[6].xxxx
 53: DP3 TEMP[7].x, TEMP[5].xyzz, TEMP[5].xyzz
 54: RSQ TEMP[7].x, TEMP[7].xxxx
 55: MUL TEMP[5].y, TEMP[5].xyzz, TEMP[7].xxxx
 56: ADD TEMP[5].x, IMM[1].xxxx, -TEMP[5].yyyy
 57: MUL TEMP[5].x, TEMP[6].xxxx, TEMP[5].xxxx
 58: LRP TEMP[1].xyz, TEMP[5].xxxx, IMM[0].xxxx, TEMP[1].xyzz
 59: MUL TEMP[2].xyz, TEMP[1].xyzz, TEMP[4].xxxx
 60: ADD TEMP[1].xyz, IN[1].yzww, -CONST[18].xyzz
 61: DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[1].xyzz
 62: RSQ TEMP[5].x, TEMP[5].xxxx
 63: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[5].xxxx
 64: ADD TEMP[1].xyz, -TEMP[1].xyzz, -CONST[17].xyzz
 65: DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[1].xyzz
 66: RSQ TEMP[5].x, TEMP[5].xxxx
 67: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[5].xxxx
 68: DP3_SAT TEMP[0].x, TEMP[1].xyzz, TEMP[0].xyzz
 69: POW TEMP[0].x, TEMP[0].xxxx, IMM[2].wwww
 70: MUL_SAT TEMP[0].x, TEMP[0].xxxx, IMM[3].xxxx
 71: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[3].wwww
 72: MAD_SAT TEMP[0].xyz, TEMP[0].xxxx, TEMP[4].xxxx, TEMP[2].xyzz
 73: MOV TEMP[2].xyz, TEMP[0].xyzx
 74: MOV OUT[0], TEMP[2]
 75: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 276)
  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 280)
  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 448)
  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 452)
  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 456)
  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 484)
  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 488)
  %41 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
  %42 = load <32 x i8> addrspace(2)* %41, !tbaa !0
  %43 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
  %46 = load <32 x i8> addrspace(2)* %45, !tbaa !0
  %47 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
  %50 = load <32 x i8> addrspace(2)* %49, !tbaa !0
  %51 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
  %54 = load <32 x i8> addrspace(2)* %53, !tbaa !0
  %55 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %58 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %59 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %60 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %61 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
  %62 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
  %63 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
  %64 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
  %65 = bitcast float %57 to i32
  %66 = bitcast float %58 to i32
  %67 = insertelement <2 x i32> undef, i32 %65, i32 0
  %68 = insertelement <2 x i32> %67, i32 %66, i32 1
  %69 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %68, <32 x i8> %46, <16 x i8> %48, i32 2)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = extractelement <4 x float> %69, i32 2
  %73 = extractelement <4 x float> %69, i32 3
  %74 = bitcast float %57 to i32
  %75 = bitcast float %58 to i32
  %76 = insertelement <2 x i32> undef, i32 %74, i32 0
  %77 = insertelement <2 x i32> %76, i32 %75, i32 1
  %78 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %77, <32 x i8> %42, <16 x i8> %44, i32 2)
  %79 = extractelement <4 x float> %78, i32 0
  %80 = extractelement <4 x float> %78, i32 1
  %81 = extractelement <4 x float> %78, i32 2
  %82 = extractelement <4 x float> %78, i32 3
  %83 = fmul float %59, %59
  %84 = fmul float %60, %60
  %85 = fadd float %84, %83
  %86 = fmul float %61, %61
  %87 = fadd float %85, %86
  %88 = call float @llvm.AMDGPU.rsq(float %87)
  %89 = fmul float %59, %88
  %90 = fmul float %60, %88
  %91 = fmul float %61, %88
  %92 = fmul float %79, %32
  %93 = fmul float %79, %33
  %94 = fmul float %79, %34
  %95 = fmul float %70, %92
  %96 = fmul float %71, %93
  %97 = fmul float %72, %94
  %98 = call float @llvm.AMDGPU.lrp(float %79, float %95, float %70)
  %99 = call float @llvm.AMDGPU.lrp(float %79, float %96, float %71)
  %100 = call float @llvm.AMDGPU.lrp(float %79, float %97, float %72)
  %101 = fmul float %80, %35
  %102 = fmul float %80, %36
  %103 = fmul float %80, %37
  %104 = fmul float %98, %101
  %105 = fmul float %99, %102
  %106 = fmul float %100, %103
  %107 = call float @llvm.AMDGPU.lrp(float %80, float %104, float %98)
  %108 = call float @llvm.AMDGPU.lrp(float %80, float %105, float %99)
  %109 = call float @llvm.AMDGPU.lrp(float %80, float %106, float %100)
  %110 = fmul float %81, %38
  %111 = fmul float %81, %39
  %112 = fmul float %81, %40
  %113 = fmul float %107, %110
  %114 = fmul float %108, %111
  %115 = fmul float %109, %112
  %116 = call float @llvm.AMDGPU.lrp(float %81, float %113, float %107)
  %117 = call float @llvm.AMDGPU.lrp(float %81, float %114, float %108)
  %118 = call float @llvm.AMDGPU.lrp(float %81, float %115, float %109)
  %119 = fsub float -0.000000e+00, %24
  %120 = fsub float -0.000000e+00, %25
  %121 = fsub float -0.000000e+00, %26
  %122 = fmul float %89, %119
  %123 = fmul float %90, %120
  %124 = fadd float %123, %122
  %125 = fmul float %91, %121
  %126 = fadd float %124, %125
  %127 = fmul float %126, 5.000000e-01
  %128 = fadd float %127, 5.000000e-01
  %129 = fmul float %128, %128
  %130 = fmul float 0x3FE99999A0000000, %129
  %131 = fadd float %130, 0x3FC99999A0000000
  %132 = fmul float %131, %116
  %133 = fmul float %131, %117
  %134 = fmul float %131, %118
  %135 = fmul float %132, 0x3FF3333340000000
  %136 = fmul float %133, 0x3FF3333340000000
  %137 = fmul float %134, 0x3FF3333340000000
  %138 = call float @llvm.AMDIL.clamp.(float %135, float 0.000000e+00, float 1.000000e+00)
  %139 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
  %140 = call float @llvm.AMDIL.clamp.(float %137, float 0.000000e+00, float 1.000000e+00)
  %141 = fadd float %62, 5.000000e-01
  %142 = fdiv float 1.000000e+00, %22
  %143 = fmul float %141, %142
  %144 = fadd float %64, 5.000000e-01
  %145 = fdiv float 1.000000e+00, %23
  %146 = fmul float %144, %145
  %147 = bitcast float %143 to i32
  %148 = bitcast float %146 to i32
  %149 = insertelement <2 x i32> undef, i32 %147, i32 0
  %150 = insertelement <2 x i32> %149, i32 %148, i32 1
  %151 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %150, <32 x i8> %54, <16 x i8> %56, i32 2)
  %152 = extractelement <4 x float> %151, i32 3
  %153 = fadd float %62, 5.000000e-01
  %154 = fadd float %64, 5.000000e-01
  %155 = fmul float %153, 3.906250e-03
  %156 = fmul float %154, 3.906250e-03
  %157 = fmul float %31, 0x3F947AE140000000
  %158 = fadd float %157, %155
  %159 = fmul float %31, 0x3F947AE140000000
  %160 = fadd float %159, %156
  %161 = bitcast float %158 to i32
  %162 = bitcast float %160 to i32
  %163 = insertelement <2 x i32> undef, i32 %161, i32 0
  %164 = insertelement <2 x i32> %163, i32 %162, i32 1
  %165 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %164, <32 x i8> %50, <16 x i8> %52, i32 2)
  %166 = extractelement <4 x float> %165, i32 0
  %167 = fmul float %31, 0x3FB99999A0000000
  %168 = call float @llvm.AMDIL.fraction.(float %167)
  %169 = fadd float %166, %168
  %170 = fmul float %169, 0x401921FB60000000
  %171 = call float @llvm.sin.f32(float %170)
  %172 = fmul float %171, 0x3FB99999A0000000
  %173 = fadd float %172, 5.000000e-01
  %174 = fadd float %152, %173
  %175 = call float @llvm.AMDIL.clamp.(float %174, float 0.000000e+00, float 1.000000e+00)
  %176 = call float @llvm.AMDGPU.lrp(float %30, float %175, float 1.000000e+00)
  %177 = fsub float -0.000000e+00, %62
  %178 = fadd float %27, %177
  %179 = fsub float -0.000000e+00, %63
  %180 = fadd float %28, %179
  %181 = fsub float -0.000000e+00, %64
  %182 = fadd float %29, %181
  %183 = fmul float %178, %178
  %184 = fmul float %180, %180
  %185 = fadd float %184, %183
  %186 = fmul float %182, %182
  %187 = fadd float %185, %186
  %188 = fadd float %187, -1.600000e+05
  %189 = fmul float %188, 0x3EAA36E2E0000000
  %190 = fcmp uge float %189, 5.000000e-01
  %191 = select i1 %190, float 5.000000e-01, float %189
  %192 = call float @llvm.AMDIL.clamp.(float %191, float 0.000000e+00, float 1.000000e+00)
  %193 = fmul float %178, %178
  %194 = fmul float %180, %180
  %195 = fadd float %194, %193
  %196 = fmul float %182, %182
  %197 = fadd float %195, %196
  %198 = call float @llvm.AMDGPU.rsq(float %197)
  %199 = fmul float %180, %198
  %200 = fsub float -0.000000e+00, %199
  %201 = fadd float 1.000000e+00, %200
  %202 = fmul float %192, %201
  %203 = call float @llvm.AMDGPU.lrp(float %202, float 5.000000e-01, float %138)
  %204 = call float @llvm.AMDGPU.lrp(float %202, float 5.000000e-01, float %139)
  %205 = call float @llvm.AMDGPU.lrp(float %202, float 5.000000e-01, float %140)
  %206 = fmul float %203, %176
  %207 = fmul float %204, %176
  %208 = fmul float %205, %176
  %209 = fsub float -0.000000e+00, %27
  %210 = fadd float %62, %209
  %211 = fsub float -0.000000e+00, %28
  %212 = fadd float %63, %211
  %213 = fsub float -0.000000e+00, %29
  %214 = fadd float %64, %213
  %215 = fmul float %210, %210
  %216 = fmul float %212, %212
  %217 = fadd float %216, %215
  %218 = fmul float %214, %214
  %219 = fadd float %217, %218
  %220 = call float @llvm.AMDGPU.rsq(float %219)
  %221 = fmul float %210, %220
  %222 = fmul float %212, %220
  %223 = fmul float %214, %220
  %224 = fsub float -0.000000e+00, %221
  %225 = fsub float -0.000000e+00, %24
  %226 = fadd float %224, %225
  %227 = fsub float -0.000000e+00, %222
  %228 = fsub float -0.000000e+00, %25
  %229 = fadd float %227, %228
  %230 = fsub float -0.000000e+00, %223
  %231 = fsub float -0.000000e+00, %26
  %232 = fadd float %230, %231
  %233 = fmul float %226, %226
  %234 = fmul float %229, %229
  %235 = fadd float %234, %233
  %236 = fmul float %232, %232
  %237 = fadd float %235, %236
  %238 = call float @llvm.AMDGPU.rsq(float %237)
  %239 = fmul float %226, %238
  %240 = fmul float %229, %238
  %241 = fmul float %232, %238
  %242 = fmul float %239, %89
  %243 = fmul float %240, %90
  %244 = fadd float %243, %242
  %245 = fmul float %241, %91
  %246 = fadd float %244, %245
  %247 = call float @llvm.AMDIL.clamp.(float %246, float 0.000000e+00, float 1.000000e+00)
  %248 = call float @llvm.pow.f32(float %247, float 2.000000e+02)
  %249 = fmul float %248, 3.000000e+00
  %250 = call float @llvm.AMDIL.clamp.(float %249, float 0.000000e+00, float 1.000000e+00)
  %251 = fmul float %250, %82
  %252 = fmul float %251, %176
  %253 = fadd float %252, %206
  %254 = fmul float %251, %176
  %255 = fadd float %254, %207
  %256 = fmul float %251, %176
  %257 = fadd float %256, %208
  %258 = call float @llvm.AMDIL.clamp.(float %253, float 0.000000e+00, float 1.000000e+00)
  %259 = call float @llvm.AMDIL.clamp.(float %255, float 0.000000e+00, float 1.000000e+00)
  %260 = call float @llvm.AMDIL.clamp.(float %257, float 0.000000e+00, float 1.000000e+00)
  %261 = call i32 @llvm.SI.packf16(float %258, float %259)
  %262 = bitcast i32 %261 to float
  %263 = call i32 @llvm.SI.packf16(float %260, float %73)
  %264 = bitcast i32 %263 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %262, float %264, float %262, float %264)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #3

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
befe0a7e
befc0306
c80c0100
c80d0101
c8080000
c8090001
c0840304
c0c60508
bf8c007f
f0800f00
00430402
c0840300
c0c60500
bf8c0070
f0800f00
00430802
bf8c0770
080410f2
10060b02
c0840100
bf8c007f
c2000971
bf8c007f
7e180200
d210000c
02021908
10181905
d2820003
040e1908
081812f2
101a070c
c2000975
bf8c007f
7e1c0200
d210000e
02021d09
10061d03
d2820003
04360709
081a14f2
101c070d
c2000979
bf8c007f
7e1e0200
d210000f
02021f0a
10061f03
d2820003
043a070a
c8380300
c8390301
c83c0200
c83d0201
10201f0f
d2820010
04421d0e
c8440400
c8450401
d2820010
04422311
7e205b10
101e210f
c2000944
bf8c007f
10241e00
101c210e
c2008945
bf8c007f
d2060013
22010001
1026270e
08242513
10202111
c2038946
bf8c007f
10222007
08222312
d2820011
03c1e111
10222311
7e2402ff
3e4ccccd
7e2602ff
3f4ccccd
d2820011
044a2711
10060711
100606ff
3f99999a
d2060803
02010103
c8480600
c8490601
c2060949
bf8c007f
0826240c
c8500500
c8510501
c2068948
bf8c007f
082a280d
102a2b15
d2820015
04562713
c8580700
c8590701
c203094a
bf8c007f
08002c06
d2820000
04560100
060200ff
c81c4000
100202ff
3551b717
d00c000e
0201e101
d2000001
0039e101
d2060801
02010101
7e005b00
10000113
080000f2
10000101
080200f2
10060701
d2820003
040de100
06262cf0
102a26ff
3b800000
c2070959
7e2e02ff
3ca3d70a
bf8c007f
d2820019
04562e0e
062a28f0
10342aff
3b800000
d2820018
046a2e0e
c0880308
c0ca0510
bf8c007f
f0800100
00851718
7e3002ff
3dcccccd
1032300e
7e324119
bf8c0770
062e3317
102e2eff
40c90fdb
102e2eff
3e22f983
7e2e6b17
d2820017
03c23117
c2070941
bf8c007f
7e30540e
10323113
c2070940
bf8c007f
7e26540e
10302715
c088030c
c0ca0518
bf8c007f
f0800800
00851318
bf8c0770
06262f13
d2060813
02010113
c2010958
bf8c007f
d2080015
020004f2
d2820013
04562602
10062703
0a24240c
0a28280d
102a2914
d2820015
04562512
0a2c2c06
d2820015
04562d16
7e2a5b15
10242b12
d2060012
22010112
0a242401
10282b14
d2060014
22010114
0a282800
102e2914
d2820017
045e2512
102a2b16
d2060015
22010115
0a2a2a07
d2820016
045e2b15
7e2c5b16
10242d12
10282d14
101e1f14
d282000e
043e1d12
101e2d15
d282000e
043a210f
d206080e
0201010e
7e1c4f0e
0e1c1cff
43480000
7e1c4b0e
101c1cff
40400000
d206080e
0201010e
101c170e
d2820003
040e270e
d2060803
02010103
101e0902
c2000970
bf8c007f
7e200200
d2100010
02022108
10202104
d282000f
043e2108
10201f0c
c2000974
bf8c007f
7e240200
d2100012
02022509
101e250f
d282000f
04421f09
10201f0d
c2000978
bf8c007f
7e240200
d2100012
0202250a
101e250f
d282000f
04421f0a
101e1f11
101e1eff
3f99999a
d206080f
0201010f
101e1f01
d282000f
043de100
101e270f
d282000f
043e270e
d206080f
0201010f
5e06070f
10040d02
c2000972
bf8c007f
7e1e0200
d210000f
02021f08
101e1f06
d2820002
040a1f08
1018050c
c2000976
bf8c007f
7e1e0200
d210000f
02021f09
10041f02
d2820002
04320509
1018050d
c200097a
bf8c007f
7e1a0200
d210000d
02021b0a
10041b02
d2820002
0432050a
10040511
100404ff
3f99999a
d2060802
02010102
10020501
d2820000
0405e100
10002700
d2820000
0402270e
d2060800
02010100
5e000f00
f8001c0f
00030003
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL OUT[2], GENERIC[20]
DCL CONST[0..31]
DCL TEMP[0..5], LOCAL
IMM[0] FLT32 {    1.0000,     0.0020,     0.3500,     0.4500}
IMM[1] FLT32 {    2.2000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MUL TEMP[1].xyz, IN[0].xyzz, CONST[31].xxxx
  2: MAD TEMP[2].x, CONST[18].yyyy, IMM[0].yyyy, IMM[0].zzzz
  3: MAX TEMP[2].x, TEMP[2].xxxx, IMM[0].wwww
  4: MIN TEMP[2].x, TEMP[2].xxxx, IMM[1].xxxx
  5: MUL TEMP[0].xyz, TEMP[1].xyzz, TEMP[2].xxxx
  6: MOV TEMP[1].x, CONST[4].xxxx
  7: MOV TEMP[1].y, CONST[5].xxxx
  8: MOV TEMP[1].z, CONST[6].xxxx
  9: MOV TEMP[1].w, IMM[1].yyyy
 10: MOV TEMP[2].x, CONST[4].yyyy
 11: MOV TEMP[2].y, CONST[5].yyyy
 12: MOV TEMP[2].z, CONST[6].yyyy
 13: MOV TEMP[2].w, IMM[1].yyyy
 14: MOV TEMP[3].x, CONST[4].zzzz
 15: MOV TEMP[3].y, CONST[5].zzzz
 16: MOV TEMP[3].z, CONST[6].zzzz
 17: MOV TEMP[3].w, IMM[1].yyyy
 18: DP4 TEMP[4].x, TEMP[0], TEMP[1]
 19: DP4 TEMP[5].x, TEMP[0], TEMP[2]
 20: MOV TEMP[4].y, TEMP[5].xxxx
 21: DP4 TEMP[0].x, TEMP[0], TEMP[3]
 22: MOV TEMP[4].z, TEMP[0].xxxx
 23: MOV TEMP[4].w, IMM[0].xxxx
 24: DP4 TEMP[0].x, TEMP[4], CONST[23]
 25: DP4 TEMP[5].x, TEMP[4], CONST[24]
 26: MOV TEMP[0].y, TEMP[5].xxxx
 27: DP4 TEMP[5].x, TEMP[4], CONST[25]
 28: MOV TEMP[0].z, TEMP[5].xxxx
 29: DP4 TEMP[4].x, TEMP[4], CONST[26]
 30: MOV TEMP[0].w, TEMP[4].xxxx
 31: DP3 TEMP[1].x, IN[1].xyzz, TEMP[1].xyzz
 32: DP3 TEMP[2].x, IN[1].xyzz, TEMP[2].xyzz
 33: MOV TEMP[1].y, TEMP[2].xxxx
 34: DP3 TEMP[2].x, IN[1].xyzz, TEMP[3].xyzz
 35: MOV TEMP[1].z, TEMP[2].xxxx
 36: DP4 TEMP[2].x, TEMP[0], CONST[0]
 37: DP4 TEMP[3].x, TEMP[0], CONST[1]
 38: MOV TEMP[2].y, TEMP[3].xxxx
 39: DP4 TEMP[3].x, TEMP[0], CONST[2]
 40: MOV TEMP[2].z, TEMP[3].xxxx
 41: DP4 TEMP[3].x, TEMP[0], CONST[3]
 42: MOV TEMP[2].w, TEMP[3].xxxx
 43: DP3 TEMP[3].x, TEMP[1].xyzz, TEMP[1].xyzz
 44: RSQ TEMP[3].x, TEMP[3].xxxx
 45: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[3].xxxx
 46: MOV TEMP[3].xy, IN[2].xyxx
 47: MOV TEMP[3].zw, TEMP[1].yyxy
 48: MOV TEMP[1].x, TEMP[1].zzzz
 49: MOV TEMP[1].yzw, TEMP[0].yxyz
 50: MOV OUT[2], TEMP[1]
 51: MOV OUT[0], TEMP[2]
 52: MOV OUT[1], TEMP[3]
 53: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 292)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 368)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 372)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 376)
  %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 380)
  %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 384)
  %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 388)
  %44 = call float @llvm.SI.load.const(<16 x i8> %11, i32 392)
  %45 = call float @llvm.SI.load.const(<16 x i8> %11, i32 396)
  %46 = call float @llvm.SI.load.const(<16 x i8> %11, i32 400)
  %47 = call float @llvm.SI.load.const(<16 x i8> %11, i32 404)
  %48 = call float @llvm.SI.load.const(<16 x i8> %11, i32 408)
  %49 = call float @llvm.SI.load.const(<16 x i8> %11, i32 412)
  %50 = call float @llvm.SI.load.const(<16 x i8> %11, i32 416)
  %51 = call float @llvm.SI.load.const(<16 x i8> %11, i32 420)
  %52 = call float @llvm.SI.load.const(<16 x i8> %11, i32 424)
  %53 = call float @llvm.SI.load.const(<16 x i8> %11, i32 428)
  %54 = call float @llvm.SI.load.const(<16 x i8> %11, i32 496)
  %55 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %6)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = extractelement <4 x float> %57, i32 2
  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %6)
  %64 = extractelement <4 x float> %63, i32 0
  %65 = extractelement <4 x float> %63, i32 1
  %66 = extractelement <4 x float> %63, i32 2
  %67 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
  %69 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %6)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = fmul float %58, %54
  %73 = fmul float %59, %54
  %74 = fmul float %60, %54
  %75 = fmul float %37, 0x3F60624DE0000000
  %76 = fadd float %75, 0x3FD6666660000000
  %77 = fcmp uge float %76, 0x3FDCCCCCC0000000
  %78 = select i1 %77, float %76, float 0x3FDCCCCCC0000000
  %79 = fcmp uge float %78, 0x40019999A0000000
  %80 = select i1 %79, float 0x40019999A0000000, float %78
  %81 = fmul float %72, %80
  %82 = fmul float %73, %80
  %83 = fmul float %74, %80
  %84 = fmul float %81, %28
  %85 = fmul float %82, %31
  %86 = fadd float %84, %85
  %87 = fmul float %83, %34
  %88 = fadd float %86, %87
  %89 = fmul float 1.000000e+00, 0.000000e+00
  %90 = fadd float %88, %89
  %91 = fmul float %81, %29
  %92 = fmul float %82, %32
  %93 = fadd float %91, %92
  %94 = fmul float %83, %35
  %95 = fadd float %93, %94
  %96 = fmul float 1.000000e+00, 0.000000e+00
  %97 = fadd float %95, %96
  %98 = fmul float %81, %30
  %99 = fmul float %82, %33
  %100 = fadd float %98, %99
  %101 = fmul float %83, %36
  %102 = fadd float %100, %101
  %103 = fmul float 1.000000e+00, 0.000000e+00
  %104 = fadd float %102, %103
  %105 = fmul float %90, %38
  %106 = fmul float %97, %39
  %107 = fadd float %105, %106
  %108 = fmul float %104, %40
  %109 = fadd float %107, %108
  %110 = fmul float 1.000000e+00, %41
  %111 = fadd float %109, %110
  %112 = fmul float %90, %42
  %113 = fmul float %97, %43
  %114 = fadd float %112, %113
  %115 = fmul float %104, %44
  %116 = fadd float %114, %115
  %117 = fmul float 1.000000e+00, %45
  %118 = fadd float %116, %117
  %119 = fmul float %90, %46
  %120 = fmul float %97, %47
  %121 = fadd float %119, %120
  %122 = fmul float %104, %48
  %123 = fadd float %121, %122
  %124 = fmul float 1.000000e+00, %49
  %125 = fadd float %123, %124
  %126 = fmul float %90, %50
  %127 = fmul float %97, %51
  %128 = fadd float %126, %127
  %129 = fmul float %104, %52
  %130 = fadd float %128, %129
  %131 = fmul float 1.000000e+00, %53
  %132 = fadd float %130, %131
  %133 = fmul float %64, %28
  %134 = fmul float %65, %31
  %135 = fadd float %134, %133
  %136 = fmul float %66, %34
  %137 = fadd float %135, %136
  %138 = fmul float %64, %29
  %139 = fmul float %65, %32
  %140 = fadd float %139, %138
  %141 = fmul float %66, %35
  %142 = fadd float %140, %141
  %143 = fmul float %64, %30
  %144 = fmul float %65, %33
  %145 = fadd float %144, %143
  %146 = fmul float %66, %36
  %147 = fadd float %145, %146
  %148 = fmul float %111, %12
  %149 = fmul float %118, %13
  %150 = fadd float %148, %149
  %151 = fmul float %125, %14
  %152 = fadd float %150, %151
  %153 = fmul float %132, %15
  %154 = fadd float %152, %153
  %155 = fmul float %111, %16
  %156 = fmul float %118, %17
  %157 = fadd float %155, %156
  %158 = fmul float %125, %18
  %159 = fadd float %157, %158
  %160 = fmul float %132, %19
  %161 = fadd float %159, %160
  %162 = fmul float %111, %20
  %163 = fmul float %118, %21
  %164 = fadd float %162, %163
  %165 = fmul float %125, %22
  %166 = fadd float %164, %165
  %167 = fmul float %132, %23
  %168 = fadd float %166, %167
  %169 = fmul float %111, %24
  %170 = fmul float %118, %25
  %171 = fadd float %169, %170
  %172 = fmul float %125, %26
  %173 = fadd float %171, %172
  %174 = fmul float %132, %27
  %175 = fadd float %173, %174
  %176 = fmul float %137, %137
  %177 = fmul float %142, %142
  %178 = fadd float %177, %176
  %179 = fmul float %147, %147
  %180 = fadd float %178, %179
  %181 = call float @llvm.AMDGPU.rsq(float %180)
  %182 = fmul float %137, %181
  %183 = fmul float %142, %181
  %184 = fmul float %147, %181
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %70, float %71, float %182, float %183)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %184, float %111, float %118, float %125)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %154, float %161, float %168, float %175)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
c0800100
bf8c0070
c2020111
bf8c007f
7e0a0204
d2100005
02020b01
c2028115
bf8c007f
7e0c0205
d2820005
04160d02
c2040119
bf8c007f
7e0c0208
d2820005
04160d03
c2048110
bf8c007f
7e0c0209
d2100006
02020d01
c2050114
bf8c007f
7e0e020a
d2820006
041a0f02
c2058118
bf8c007f
7e0e020b
d2820006
041a0f03
100e0d06
d2820007
041e0b05
c2060112
bf8c007f
7e10020c
d2100008
02021101
c2068116
bf8c007f
7e12020d
d2820008
04221302
c207011a
bf8c007f
7e12020e
d2820001
04221303
d2820002
041e0301
7e045b02
10060505
10080506
c0880708
bf8c007f
e00c2000
80040500
bf8c0770
f800020f
03040605
c2078149
bf8c070f
7e0602ff
3eb33333
7e0802ff
3b03126f
bf8c007f
d2820003
040e080f
7e0802ff
3ee66666
d00c0010
02020903
d2000003
00420704
7e0802ff
400ccccd
d00c0010
02020903
d2000003
00420903
c0880700
bf8c007f
e00c2000
80040400
c203017c
bf8c0070
7e000206
d2100008
02020104
10100708
d2100009
02020105
10120709
10141205
d282000a
04280908
d2100000
02020106
10000700
d2820003
04281100
06060680
c2020165
bf8c007f
10080604
100a120a
d2820005
04141308
d2820005
04141700
060a0a80
c2020164
bf8c007f
d2820004
04100905
100c120d
d2820006
04181908
d2820000
04181d00
06000080
c2020166
bf8c007f
d2820004
04100900
c2020167
bf8c007f
06080804
c2020161
bf8c007f
100c0604
c2020160
bf8c007f
d2820006
04180905
c2020162
bf8c007f
d2820006
04180900
c2020163
bf8c007f
060c0c04
c202015d
bf8c007f
100e0604
c202015c
bf8c007f
d2820007
041c0905
c202015e
bf8c007f
d2820007
041c0900
c202015f
bf8c007f
060e0e04
10020501
f800021f
04060701
c202010d
bf8c000f
10020c04
c202010c
bf8c007f
d2820001
04040907
c202010e
bf8c007f
d2820001
04040904
c2020169
bf8c007f
10040604
c2020168
bf8c007f
d2820002
04080905
c202016a
bf8c007f
d2820000
04080900
c202016b
bf8c007f
06000004
c202010f
bf8c007f
d2820001
04040900
c2020109
bf8c007f
10040c04
c2020108
bf8c007f
d2820002
04080907
c202010a
bf8c007f
d2820002
04080904
c202010b
bf8c007f
d2820002
04080900
c2020105
bf8c007f
10060c04
c2020104
bf8c007f
d2820003
040c0907
c2020106
bf8c007f
d2820003
040c0904
c2020107
bf8c007f
d2820003
040c0900
c2020101
bf8c007f
100a0c04
c2020100
bf8c007f
d2820005
04140907
c2020102
bf8c007f
d2820004
04140904
c2000103
bf8c007f
d2820000
04100100
f80008cf
01020300
bf810000
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %31, %12
  %43 = fmul float %31, %13
  %44 = fmul float %31, %14
  %45 = fmul float %31, %15
  %46 = fmul float %32, %16
  %47 = fadd float %46, %42
  %48 = fmul float %32, %17
  %49 = fadd float %48, %43
  %50 = fmul float %32, %18
  %51 = fadd float %50, %44
  %52 = fmul float %32, %19
  %53 = fadd float %52, %45
  %54 = fmul float %33, %20
  %55 = fadd float %54, %47
  %56 = fmul float %33, %21
  %57 = fadd float %56, %49
  %58 = fmul float %33, %22
  %59 = fadd float %58, %51
  %60 = fmul float %33, %23
  %61 = fadd float %60, %53
  %62 = fmul float %34, %24
  %63 = fadd float %62, %55
  %64 = fmul float %34, %25
  %65 = fadd float %64, %57
  %66 = fmul float %34, %26
  %67 = fadd float %66, %59
  %68 = fmul float %34, %27
  %69 = fadd float %68, %61
  %70 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
  %71 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
  %72 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
  %73 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %70, float %71, float %72, float %73)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
SI CODE:
c0840704
bf8c007f
e00c2000
80020100
bf8c0770
d2060805
02010104
d2060806
02010103
d2060807
02010102
d2060801
02010101
f800020f
05060701
c0820700
bf8c000f
e00c2000
80010000
c0800100
bf8c0070
c2020103
bf8c007f
7e080204
d2100004
02020900
c2020107
bf8c007f
7e0a0204
d2820004
04120b01
c202010b
bf8c007f
7e0a0204
d2820004
04120b02
c202010f
bf8c007f
7e0a0204
d2820004
04120b03
c2020102
bf8c007f
7e0a0204
d2100005
02020b00
c2020106
bf8c007f
7e0c0204
d2820005
04160d01
c202010a
bf8c007f
7e0c0204
d2820005
04160d02
c202010e
bf8c007f
7e0c0204
d2820005
04160d03
c2020101
bf8c007f
7e0c0204
d2100006
02020d00
c2020105
bf8c007f
7e0e0204
d2820006
041a0f01
c2020109
bf8c007f
7e0e0204
d2820006
041a0f02
c202010d
bf8c007f
7e0e0204
d2820006
041a0f03
c2020100
bf8c007f
7e0e0204
d2100007
02020f00
c2020104
bf8c007f
7e100204
d2820007
041e1101
c2020108
bf8c007f
7e100204
d2820007
041e1102
c200010c
bf8c007f
7e100200
d2820000
041e1103
f80008cf
04050600
bf810000
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %20 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
  %21 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
  %22 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
  %23 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
  %25 = bitcast i32 %24 to float
  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
  %27 = bitcast i32 %26 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
SI CODE:
befe0a7e
befc0306
c8080300
c8090301
c80c0200
c80d0201
5e040503
c80c0100
c80d0101
c8100000
c8110001
5e000704
f8001c0f
02000200
bf810000
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Inconsistency detected by ld.so: dl-close.c: 765: _dl_close: Assertion `map->l_init_called' failed!
Game removed: AppID 203770 "Crusader Kings II", ProcID 3843 
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Installing breakpad exception handler for appid(steam)/version(1379375637_client)
Generating new string page texture 181: 128x256, total string texture memory is 393,22 KB
unlinked 2 orphaned pipes
CAsyncIOManager: 0 threads terminating.  0 reads, 0 writes, 0 deferrals.
CAsyncIOManager: 18237 single object sleeps, 0 multi object sleeps
CAsyncIOManager: 0 single object alertable sleeps, 4 multi object alertable sleeps
Shutting down. . .
[2013-09-18 22:29:44] Shutdown