diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index 6c398a4..83568e0 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -1055,6 +1055,8 @@ static int ni_restrict_performance_levels_before_switch(struct radeon_device *rd
 int ni_dpm_force_performance_level(struct radeon_device *rdev,
 				   enum radeon_dpm_forced_level level)
 {
+	return 0;
+
 	if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
 		if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
 			return -EINVAL;
@@ -2188,6 +2190,12 @@ static int ni_populate_mclk_value(struct radeon_device *rdev,
 	if (ret)
 		return ret;
 
+	printk("pll params: m %u, ref %u, pd %u, epd %u, dithen %u, fb %u.%u, ref %u, vco %u\n",
+	       memory_clock, rdev->clock.mpll.reference_freq, dividers.post_div,
+	       dividers.enable_post_div, dividers.enable_dithen,
+	       dividers.whole_fb_div, dividers.frac_fb_div, dividers.ref_div,
+	       dividers.vco_mode);
+
 	if (!strobe_mode) {
 		mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
 
@@ -2195,8 +2203,16 @@ static int ni_populate_mclk_value(struct radeon_device *rdev,
 			dividers.post_div = 1;
 	}
 
+	printk("pll params: m %u, ref %u, pd %u, epd %u, dithen %u, fb %u.%u, ref %u, vco %u\n",
+	       memory_clock, rdev->clock.mpll.reference_freq, dividers.post_div,
+	       dividers.enable_post_div, dividers.enable_dithen,
+	       dividers.whole_fb_div, dividers.frac_fb_div, dividers.ref_div,
+	       dividers.vco_mode);
+
 	ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
 
+	printk("ibias: 0x%x", ibias);
+
 	mpll_ad_func_cntl &= ~(CLKR_MASK |
 			       YCLK_POST_DIV_MASK |
 			       CLKF_MASK |
@@ -2248,6 +2264,9 @@ static int ni_populate_mclk_value(struct radeon_device *rdev,
 			u32 clk_v = ss.percentage *
 				(0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
 
+			printk("ss: s 0x%x v 0x%x rate %u, percent %u\n", clk_s, clk_v,
+			       ss.rate, ss.percentage);
+
 			mpll_ss1 &= ~CLKV_MASK;
 			mpll_ss1 |= CLKV(clk_v);
 
@@ -2874,7 +2893,7 @@ static int ni_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
 static int ni_initialize_mc_reg_table(struct radeon_device *rdev)
 {
 	struct ni_power_info *ni_pi = ni_get_pi(rdev);
-	int ret;
+	int ret, i, j;
 	struct atom_mc_reg_table *table;
 	struct ni_mc_reg_table *ni_table = &ni_pi->mc_reg_table;
 	u8 module_index = rv770_get_memory_module_index(rdev);
@@ -2902,6 +2921,20 @@ static int ni_initialize_mc_reg_table(struct radeon_device *rdev)
         if (ret)
                 goto init_mc_done;
 
+	printk("module_index %d\n", module_index);
+	for (i = 0; i < table->last; i++) {
+		printk("%d reg: 0x%x, 0x%x\n", i,
+		       table->mc_reg_address[i].s1, table->mc_reg_address[i].pre_reg_data);
+	}
+	for (i = 0; i < table->num_entries; i++) {
+		printk("%d mclk: %u\n", i,
+		       table->mc_reg_table_entry[i].mclk_max);
+		for (j = 0; j < table->last; j++) {
+			printk(" %d mc_data: 0x%08x\n", j,
+			       table->mc_reg_table_entry[i].mc_data[j]);
+		}
+	}
+
 	ret = ni_copy_vbios_mc_reg_table(table, ni_table);
 
         if (ret)