From e58cb5a002f45dfb85748055b1bdeeb10a8a886d Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Fri, 27 Sep 2013 17:19:53 -0700 Subject: [PATCH] XXX: R600: Simplify handling of private memory --- lib/Target/R600/AMDGPUInstrInfo.cpp | 2 +- lib/Target/R600/AMDGPUTargetMachine.cpp | 2 +- lib/Target/R600/R600InstrInfo.cpp | 50 ++++++++++++++++++++++++++++++++- lib/Target/R600/R600InstrInfo.h | 4 +++ lib/Target/R600/R600Packetizer.cpp | 8 ++++++ lib/Target/R600/R600RegisterInfo.cpp | 1 + 6 files changed, 64 insertions(+), 3 deletions(-) diff --git a/lib/Target/R600/AMDGPUInstrInfo.cpp b/lib/Target/R600/AMDGPUInstrInfo.cpp index 61437e9..8d3f740 100644 --- a/lib/Target/R600/AMDGPUInstrInfo.cpp +++ b/lib/Target/R600/AMDGPUInstrInfo.cpp @@ -28,7 +28,7 @@ using namespace llvm; AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm) - : AMDGPUGenInstrInfo(0,0), RI(tm), TM(tm) { } + : AMDGPUGenInstrInfo(-1,-1), RI(tm), TM(tm) { } const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const { return RI; diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp index d77cddd..efacf88 100644 --- a/lib/Target/R600/AMDGPUTargetMachine.cpp +++ b/lib/Target/R600/AMDGPUTargetMachine.cpp @@ -136,7 +136,7 @@ bool AMDGPUPassConfig::addInstSelector() { const AMDGPUSubtarget &ST = TM->getSubtarget(); if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) { // This callbacks this pass uses are not implemented yet on SI. - addPass(createAMDGPUIndirectAddressingPass(*TM)); +// addPass(createAMDGPUIndirectAddressingPass(*TM)); } return false; } diff --git a/lib/Target/R600/R600InstrInfo.cpp b/lib/Target/R600/R600InstrInfo.cpp index 93931e4..a44b260 100644 --- a/lib/Target/R600/R600InstrInfo.cpp +++ b/lib/Target/R600/R600InstrInfo.cpp @@ -77,6 +77,46 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, } } +bool R600InstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const { + MachineBasicBlock *MBB = MI->getParent(); + switch(MI->getOpcode()) { + default: return false; + case AMDGPU::R600_RegisterLoad: { + unsigned RegIndex = MI->getOperand(2).getImm(); + unsigned Channel = MI->getOperand(3).getImm(); + unsigned Address = calculateIndirectAddress(RegIndex, Channel); + unsigned OffsetReg = MI->getOperand(1).getReg(); + if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { + buildDefaultInstruction(*MBB, MI, AMDGPU::MOV, + MI->getOperand(0).getReg(), + getIndirectAddrLoadRegClass()->getRegister(Address)); + } else { + buildIndirectRead(MBB, MI, MI->getOperand(0).getReg(), + Address, OffsetReg); + } + break; + } + case AMDGPU::R600_RegisterStore: { + unsigned RegIndex = MI->getOperand(2).getImm(); + unsigned Channel = MI->getOperand(3).getImm(); + unsigned Address = calculateIndirectAddress(RegIndex, Channel); + unsigned OffsetReg = MI->getOperand(1).getReg(); + if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { + buildDefaultInstruction(*MBB, MI, AMDGPU::MOV, + getIndirectAddrLoadRegClass()->getRegister(Address), + MI->getOperand(0).getReg()); + } else { + buildIndirectWrite(MBB, MI, MI->getOperand(0).getReg(), + calculateIndirectAddress(RegIndex, Channel), + OffsetReg); + } + break; + } + } + MBB->erase(MI); + return true; +} + MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, int64_t Imm) const { MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc()); @@ -204,6 +244,14 @@ bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const { } } +bool R600InstrInfo::usesAddressRegister(MachineInstr *MI) const { + return MI->findRegisterUseOperandIdx(AMDGPU::AR_X) != -1; +} + +bool R600InstrInfo::definesAddressRegister(MachineInstr *MI) const { + return MI->findRegisterDefOperandIdx(AMDGPU::AR_X) != -1; +} + bool R600InstrInfo::readsLDSSrcReg(const MachineInstr *MI) const { if (!isALUInstr(MI->getOpcode())) { return false; @@ -1073,7 +1121,7 @@ const TargetRegisterClass * R600InstrInfo::getIndirectAddrStoreRegClass( } const TargetRegisterClass *R600InstrInfo::getIndirectAddrLoadRegClass() const { - return &AMDGPU::TRegMemRegClass; + return &AMDGPU::R600_TReg32_XRegClass; } MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB, diff --git a/lib/Target/R600/R600InstrInfo.h b/lib/Target/R600/R600InstrInfo.h index 0d1ffc8..c195f1b 100644 --- a/lib/Target/R600/R600InstrInfo.h +++ b/lib/Target/R600/R600InstrInfo.h @@ -56,6 +56,8 @@ namespace llvm { unsigned DestReg, unsigned SrcReg, bool KillSrc) const; + virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; + bool isTrig(const MachineInstr &MI) const; bool isPlaceHolderOpcode(unsigned opcode) const; bool isReductionOp(unsigned opcode) const; @@ -78,6 +80,8 @@ namespace llvm { bool usesTextureCache(const MachineInstr *MI) const; bool mustBeLastInClause(unsigned Opcode) const; + bool usesAddressRegister(MachineInstr *MI) const; + bool definesAddressRegister(MachineInstr *MI) const; bool readsLDSSrcReg(const MachineInstr *MI) const; /// \returns The operand index for the given source number. Legal values diff --git a/lib/Target/R600/R600Packetizer.cpp b/lib/Target/R600/R600Packetizer.cpp index bed9115..3a07adc 100644 --- a/lib/Target/R600/R600Packetizer.cpp +++ b/lib/Target/R600/R600Packetizer.cpp @@ -206,6 +206,14 @@ public: return false; } } + + bool ARDef = TII->definesAddressRegister(MII) || + TII->definesAddressRegister(MIJ); + bool ARUse = TII->usesAddressRegister(MII) || + TII->usesAddressRegister(MIJ); + if (ARDef && ARUse) + return false; + return true; } diff --git a/lib/Target/R600/R600RegisterInfo.cpp b/lib/Target/R600/R600RegisterInfo.cpp index 4dc63fe..506e6c0 100644 --- a/lib/Target/R600/R600RegisterInfo.cpp +++ b/lib/Target/R600/R600RegisterInfo.cpp @@ -41,6 +41,7 @@ BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(AMDGPU::PRED_SEL_OFF); Reserved.set(AMDGPU::PRED_SEL_ZERO); Reserved.set(AMDGPU::PRED_SEL_ONE); + Reserved.set(AMDGPU::INDIRECT_BASE_ADDR); for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(), E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) { -- 1.7.11.4