From 17524e7eaeeb6733fdef90aebeb1c8b2d5d27bfb Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 7 Oct 2013 12:28:46 +0300 Subject: [PATCH] save/restore some more backlight registers Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Cc: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/i915_suspend.c | 16 ++++++++++++++++ 3 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ed8653f..f884a25 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -719,6 +719,10 @@ struct i915_suspend_saved_registers { u32 saveBLC_PWM_CTL2; u32 saveBLC_CPU_PWM_CTL; u32 saveBLC_CPU_PWM_CTL2; + u32 saveHSW_BLC_PWM2_CTL; + u32 saveHSW_BLC_PWM2_DATA; + u32 saveHSW_BLC_MISC_CTL; + u32 saveUTIL_PIN_CTL; u32 saveFPB0; u32 saveFPB1; u32 saveDPLL_B; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4be72b2..4a56653 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2358,6 +2358,8 @@ #define BLC_PWM_CPU_CTL 0x48254 #define HSW_BLC_PWM2_CTL 0x48350 +#define HSW_BLC_PWM2_DATA 0x48354 +#define HSW_BLC_MISC_CTL 0x48360 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 3538370..66f3ac7 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -212,6 +212,14 @@ static void i915_save_display(struct drm_device *dev) dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2); dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL); dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2); + + if (IS_HASWELL(dev)) { + dev_priv->regfile.saveHSW_BLC_PWM2_CTL = I915_READ(HSW_BLC_PWM2_CTL); + dev_priv->regfile.saveHSW_BLC_PWM2_DATA = I915_READ(HSW_BLC_PWM2_DATA); + dev_priv->regfile.saveHSW_BLC_MISC_CTL = I915_READ(HSW_BLC_MISC_CTL); + dev_priv->regfile.saveUTIL_PIN_CTL = I915_READ(UTIL_PIN_CTL); + } + if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); } else { @@ -296,6 +304,14 @@ static void i915_restore_display(struct drm_device *dev) */ I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2); I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL); + + if (IS_HASWELL(dev)) { + I915_WRITE(HSW_BLC_PWM2_CTL, dev_priv->regfile.saveHSW_BLC_PWM2_CTL); + I915_WRITE(HSW_BLC_PWM2_DATA, dev_priv->regfile.saveHSW_BLC_PWM2_DATA); + I915_WRITE(HSW_BLC_MISC_CTL, dev_priv->regfile.saveHSW_BLC_MISC_CTL); + I915_WRITE(UTIL_PIN_CTL, dev_priv->regfile.saveUTIL_PIN_CTL); + } + I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); -- 1.7.9.5