Index: lib/Target/R600/AMDILISelLowering.cpp
===================================================================
--- lib/Target/R600/AMDILISelLowering.cpp	(revision 192535)
+++ lib/Target/R600/AMDILISelLowering.cpp	(working copy)
@@ -82,10 +82,16 @@
     (int)MVT::v2f64,
     (int)MVT::v2i64
   };
+  //64 bit types, unsupported in R600 and others
+  static const int LongTypes[] = {
+    (int)MVT::i64,
+    (int)MVT::v2i64
+  };
   const size_t NumTypes = array_lengthof(types);
   const size_t NumFloatTypes = array_lengthof(FloatTypes);
   const size_t NumIntTypes = array_lengthof(IntTypes);
   const size_t NumVectorTypes = array_lengthof(VectorTypes);
+  const size_t NumLongTypes = array_lengthof(LongTypes);
 
   const AMDGPUSubtarget &STM = getTargetMachine().getSubtarget<AMDGPUSubtarget>();
   // These are the current register classes that are
@@ -106,11 +112,15 @@
     setOperationAction(ISD::BRIND, VT, Expand);
     // TODO: Implement custom UREM/SREM routines
     setOperationAction(ISD::SREM, VT, Expand);
+    setOperationAction(ISD::UREM, VT, Expand);
     setOperationAction(ISD::SMUL_LOHI, VT, Expand);
     setOperationAction(ISD::UMUL_LOHI, VT, Expand);
     if (VT != MVT::i64 && VT != MVT::v2i64) {
       setOperationAction(ISD::SDIV, VT, Custom);
+    } else {
+      setOperationAction(ISD::SDIV, VT, Expand);
     }
+    setOperationAction(ISD::UDIV, VT, Expand);
   }
   for (unsigned int x = 0; x < NumFloatTypes; ++x) {
     MVT::SimpleValueType VT = (MVT::SimpleValueType)FloatTypes[x];
@@ -132,6 +142,7 @@
 
     // GPU also does not have divrem function for signed or unsigned
     setOperationAction(ISD::SDIVREM, VT, Expand);
+    setOperationAction(ISD::UDIVREM, VT, Expand);
 
     // GPU does not have [S|U]MUL_LOHI functions as a single instruction
     setOperationAction(ISD::SMUL_LOHI, VT, Expand);
@@ -150,19 +161,37 @@
 
     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
     setOperationAction(ISD::SDIVREM, VT, Expand);
+    setOperationAction(ISD::UDIVREM, VT, Expand);
     setOperationAction(ISD::SMUL_LOHI, VT, Expand);
     // setOperationAction(ISD::VSETCC, VT, Expand);
     setOperationAction(ISD::SELECT_CC, VT, Expand);
 
   }
-  setOperationAction(ISD::MULHU, MVT::i64, Expand);
-  setOperationAction(ISD::MULHU, MVT::v2i64, Expand);
-  setOperationAction(ISD::MULHS, MVT::i64, Expand);
-  setOperationAction(ISD::MULHS, MVT::v2i64, Expand);
-  setOperationAction(ISD::ADD, MVT::v2i64, Expand);
-  setOperationAction(ISD::SREM, MVT::v2i64, Expand);
+  for (unsigned int x  = 0; x < NumLongTypes; ++x) {
+    MVT::SimpleValueType VT = (MVT::SimpleValueType)LongTypes[x];
+    setOperationAction(ISD::MULHU, VT, Expand);
+    setOperationAction(ISD::MULHS, VT, Expand);
+    setOperationAction(ISD::ADD, VT, Expand);
+    setOperationAction(ISD::AND, VT, Expand);
+    setOperationAction(ISD::OR, VT, Expand);
+    setOperationAction(ISD::XOR, VT, Expand);
+    setOperationAction(ISD::SUB, VT, Expand);
+    setOperationAction(ISD::MUL, VT, Expand);
+    setOperationAction(ISD::TRUNCATE, VT, Expand);
+    setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
+    setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
+    setOperationAction(ISD::ANY_EXTEND, VT, Expand);
+    setOperationAction(ISD::SHL, VT, Expand);
+    setOperationAction(ISD::SRA, VT, Expand);
+    setOperationAction(ISD::SRL, VT, Expand);
+    setOperationAction(ISD::ROTL, VT, Expand);
+    setOperationAction(ISD::ROTR, VT, Expand);
+    setOperationAction(ISD::BSWAP, VT, Expand);
+    setOperationAction(ISD::CTTZ, VT, Expand);
+    setOperationAction(ISD::CTLZ, VT, Expand);
+    setOperationAction(ISD::CTPOP, VT, Expand);
+  }
   setOperationAction(ISD::Constant          , MVT::i64  , Legal);
-  setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
   setOperationAction(ISD::TRUNCATE, MVT::v2i64, Expand);
   setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand);
   setOperationAction(ISD::ZERO_EXTEND, MVT::v2i64, Expand);