; ModuleID = 'radeon' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64" target triple = "r600--" %struct.Block = type { i32, i32, i32 } ; Function Attrs: nounwind define void @struct_field_copy(%struct.Block addrspace(1)* nocapture readonly %ip, i32 addrspace(1)* nocapture %out) #0 { entry: %f0 = getelementptr inbounds %struct.Block addrspace(1)* %ip, i32 0, i32 0 %0 = load i32 addrspace(1)* %f0, align 4, !tbaa !5 %1 = load i32 addrspace(1)* %out, align 4, !tbaa !5 %cmp.i = icmp eq i32 %0, 42 %. = select i1 %cmp.i, i32 1, i32 %1 store i32 %., i32 addrspace(1)* %out, align 4, !tbaa !5 ret void } attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } !opencl.kernels = !{!0, !1, !2, !3, !4} !0 = metadata !{void (%struct.Block addrspace(1)*, i32 addrspace(1)*)* @struct_field_copy} !1 = metadata !{null} !2 = metadata !{null} !3 = metadata !{null} !4 = metadata !{null} !5 = metadata !{metadata !6, metadata !6, i64 0} !6 = metadata !{metadata !"int", metadata !7, i64 0} !7 = metadata !{metadata !"omnipotent char", metadata !8, i64 0} !8 = metadata !{metadata !"Simple C/C++ TBAA"} # Machine code for function struct_field_copy: Post SSA, not tracking liveness BB#0: derived from LLVM BB %entry CF_ALU 10, 0, 0, 2, 0, 0, 0, 1, 1 CF_TC_EG 6, 1 CF_ALU 12, 0, 0, 2, 0, 0, 0, 4, 1 RAT_WRITE_CACHELESS_32_eg %T0_X, %T1_X, 1 CF_END_EG PAD FETCH_CLAUSE 6 %T1_X = VTX_READ_GLOBAL_32_eg %T1_X, 0; mem:LD4[%out](tbaa=) %T0_X = VTX_READ_GLOBAL_32_eg %T0_X, 0; mem:LD4[%f01](tbaa=) ALU_CLAUSE 10 %T0_X = MOV 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, 0, pred:%PRED_SEL_OFF, 0, 0 %T1_X = MOV 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, 1, pred:%PRED_SEL_OFF, 0, 0 ALU_CLAUSE 12 %T0_W = SETE_INT 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 42, 0 LITERALS 42, 0 %T0_X = CNDE_INT 0, 0, %PV_W, 0, 0, -1, %T1_X, 0, 0, -1, %ONE_INT, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T1_X = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0 LITERALS 2, 0 # End machine code for function struct_field_copy. Shader Disassembly: ALU 1, @10, KC0[CB0:0-32], KC1[] ; 8000000A A0040000 TEX 1 @6 ; 00000006 80400400 ALU 4, @12, KC0[CB0:0-32], KC1[] ; 8000000C A0100000 MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 ; 00802020 95E01000 CF_END ; 00000000 80200000 PAD ; 00000000 00000000 Fetch clause starting at 6: ; VTX_READ_32 T1.X, T1.X, 0 ; 10010140 135FF001 00080000 00000000 VTX_READ_32 T0.X, T0.X, 0 ; 10000140 135FF000 00080000 00000000 ALU clause starting at 10: ; MOV T0.X, KC0[2].Y, ; 00000482 00000C90 MOV * T1.X, KC0[2].Z, ; 80000882 00200C90 ALU clause starting at 12: ; SETE_INT * T0.W, T0.X, literal.x, ; 801FA000 60001D10 42(5.885454e-44), 0(0.000000e+00) ; 0000002A 00000000 CNDE_INT T0.X, PV.W, T1.X, 1, ; 00002CFE 000380FA LSHR * T1.X, KC0[2].Z, literal.x, ; 801FA882 00200B10 2(2.802597e-45), 0(0.000000e+00) ; 00000002 00000000 bytecode 34 dw -- 2 gprs -- 1 nstack ------------- shader 0 -- E -------------------------------------- ; ModuleID = 'radeon' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64" target triple = "r600--" %struct.Block = type { i32, i32, i32 } ; Function Attrs: nounwind define void @struct_assign_copy(%struct.Block addrspace(1)* nocapture readonly %ip, i32 addrspace(1)* nocapture %out) #0 { entry: %0 = bitcast %struct.Block addrspace(1)* %ip to i8 addrspace(1)* %block.sroa.0.0.cast = bitcast i8 addrspace(1)* %0 to i32* %block.sroa.0.0.copyload = load i32* %block.sroa.0.0.cast, align 4 %1 = load i32 addrspace(1)* %out, align 4, !tbaa !5 %cmp.i = icmp eq i32 %block.sroa.0.0.copyload, 42 %. = select i1 %cmp.i, i32 1, i32 %1 store i32 %., i32 addrspace(1)* %out, align 4, !tbaa !5 ret void } attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } !opencl.kernels = !{!0, !1, !2, !3, !4} !0 = metadata !{null} !1 = metadata !{void (%struct.Block addrspace(1)*, i32 addrspace(1)*)* @struct_assign_copy} !2 = metadata !{null} !3 = metadata !{null} !4 = metadata !{null} !5 = metadata !{metadata !6, metadata !6, i64 0} !6 = metadata !{metadata !"int", metadata !7, i64 0} !7 = metadata !{metadata !"omnipotent char", metadata !8, i64 0} !8 = metadata !{metadata !"Simple C/C++ TBAA"} # Machine code for function struct_assign_copy: Post SSA, not tracking liveness BB#0: derived from LLVM BB %entry CF_ALU 8, 0, 0, 2, 0, 0, 0, 4, 1 CF_TC_EG 6, 0 CF_ALU 13, 0, 0, 2, 0, 0, 0, 4, 1 RAT_WRITE_CACHELESS_32_eg %T0_X, %T1_X, 1 CF_END_EG PAD FETCH_CLAUSE 6 %T1_X = VTX_READ_GLOBAL_32_eg %T1_X, 0; mem:LD4[%out](tbaa=) ALU_CLAUSE 8 %T0_W = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0 LITERALS 2, 0 %AR_X = MOVA_INT_eg 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T0_X = MOV 1, 0, 0, 0, %Addr0_X, 0, 1, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0, %AR_X %T1_X = MOV 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, 1, pred:%PRED_SEL_OFF, 0, 0 ALU_CLAUSE 13 %T0_W = SETE_INT 0, 0, 1, 0, 0, 0, %T0_X, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 42, 0 LITERALS 42, 0 %T0_X = CNDE_INT 0, 0, %PV_W, 0, 0, -1, %T1_X, 0, 0, -1, %ONE_INT, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T1_X = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0 LITERALS 2, 0 # End machine code for function struct_assign_copy. Shader Disassembly: ALU 4, @8, KC0[CB0:0-32], KC1[] ; 80000008 A0100000 TEX 0 @6 ; 00000006 80400000 ALU 4, @13, KC0[CB0:0-32], KC1[] ; 8000000D A0100000 MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 ; 00802020 95E01000 CF_END ; 00000000 80200000 PAD ; 00000000 00000000 Fetch clause starting at 6: ; VTX_READ_32 T1.X, T1.X, 0 ; 10010140 135FF001 00080000 00000000 ALU clause starting at 8: ; LSHR * T0.W, KC0[2].Y, literal.x, ; 801FA482 60000B10 2(2.802597e-45), 0(0.000000e+00) ; 00000002 00000000 MOVA_INT * AR.x (MASKED), PV.W, ; 80000CFE 00006600 MOV T0.X, T(0 + AR.x).X+, ; 00000200 00000C90 MOV * T1.X, KC0[2].Z, ; 80000882 00200C90 ALU clause starting at 13: ; SETE_INT * T0.W, T0.X, literal.x, ; 801FA000 60001D10 42(5.885454e-44), 0(0.000000e+00) ; 0000002A 00000000 CNDE_INT T0.X, PV.W, T1.X, 1, ; 00002CFE 000380FA LSHR * T1.X, KC0[2].Z, literal.x, ; 801FA882 00200B10 2(2.802597e-45), 0(0.000000e+00) ; 00000002 00000000 bytecode 36 dw -- 2 gprs -- 1 nstack ------------- shader 1 -- E -------------------------------------- ; ModuleID = 'radeon' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64" target triple = "r600--" %struct.Block = type { i32, i32, i32 } ; Function Attrs: nounwind define void @struct_pass_copy(%struct.Block addrspace(1)* nocapture readonly %ip, i32 addrspace(1)* nocapture %out) #0 { entry: %0 = load i32 addrspace(1)* %out, align 4, !tbaa !5 %1 = bitcast %struct.Block addrspace(1)* %ip to i8 addrspace(1)* %tmp2.sroa.0.0.cast = bitcast i8 addrspace(1)* %1 to i32* %tmp2.sroa.0.0.copyload = load i32* %tmp2.sroa.0.0.cast, align 4 %cmp.i = icmp eq i32 %tmp2.sroa.0.0.copyload, 42 %. = select i1 %cmp.i, i32 1, i32 %0 store i32 %., i32 addrspace(1)* %out, align 4, !tbaa !5 ret void } attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } !opencl.kernels = !{!0, !1, !2, !3, !4} !0 = metadata !{null} !1 = metadata !{null} !2 = metadata !{void (%struct.Block addrspace(1)*, i32 addrspace(1)*)* @struct_pass_copy} !3 = metadata !{null} !4 = metadata !{null} !5 = metadata !{metadata !6, metadata !6, i64 0} !6 = metadata !{metadata !"int", metadata !7, i64 0} !7 = metadata !{metadata !"omnipotent char", metadata !8, i64 0} !8 = metadata !{metadata !"Simple C/C++ TBAA"} # Machine code for function struct_pass_copy: Post SSA, not tracking liveness BB#0: derived from LLVM BB %entry CF_ALU 8, 0, 0, 2, 0, 0, 0, 0, 1 CF_TC_EG 6, 0 CF_ALU 9, 0, 0, 2, 0, 0, 0, 8, 1 RAT_WRITE_CACHELESS_32_eg %T0_X, %T1_X, 1 CF_END_EG PAD FETCH_CLAUSE 6 %T0_X = VTX_READ_GLOBAL_32_eg %T0_X, 0; mem:LD4[%out](tbaa=) ALU_CLAUSE 8 %T0_X = MOV 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, 1, pred:%PRED_SEL_OFF, 0, 0 ALU_CLAUSE 9 %T0_W = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0 LITERALS 2, 0 %AR_X = MOVA_INT_eg 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T0_Y = MOV 1, 0, 0, 0, %Addr0_X, 0, 1, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %AR_X %T0_W = SETE_INT 0, 0, 1, 0, 0, 0, %PV_Y, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 42, 0 LITERALS 42, 0 %T0_X = CNDE_INT 0, 0, %PV_W, 0, 0, -1, %T0_X, 0, 0, -1, %ONE_INT, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 0, 0 %T1_X = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0 LITERALS 2, 0 # End machine code for function struct_pass_copy. Shader Disassembly: ALU 0, @8, KC0[CB0:0-32], KC1[] ; 80000008 A0000000 TEX 0 @6 ; 00000006 80400000 ALU 8, @9, KC0[CB0:0-32], KC1[] ; 80000009 A0200000 MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 ; 00802020 95E01000 CF_END ; 00000000 80200000 PAD ; 00000000 00000000 Fetch clause starting at 6: ; VTX_READ_32 T0.X, T0.X, 0 ; 10000140 135FF000 00080000 00000000 ALU clause starting at 8: ; MOV * T0.X, KC0[2].Z, ; 80000882 00000C90 ALU clause starting at 9: ; LSHR * T0.W, KC0[2].Y, literal.x, ; 801FA482 60000B10 2(2.802597e-45), 0(0.000000e+00) ; 00000002 00000000 MOVA_INT * AR.x (MASKED), PV.W, ; 80000CFE 00006600 MOV * T0.Y, T(0 + AR.x).X+, ; 80000200 20000C90 SETE_INT * T0.W, PV.Y, literal.x, ; 801FA4FE 60001D10 42(5.885454e-44), 0(0.000000e+00) ; 0000002A 00000000 CNDE_INT T0.X, PV.W, T0.X, 1, ; 00000CFE 000380FA LSHR * T1.X, KC0[2].Z, literal.x, ; 801FA882 00200B10 2(2.802597e-45), 0(0.000000e+00) ; 00000002 00000000 bytecode 36 dw -- 2 gprs -- 1 nstack ------------- shader 2 -- E -------------------------------------- ; ModuleID = 'radeon' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64" target triple = "r600--" %struct.Block = type { i32, i32, i32 } ; Function Attrs: nounwind define void @struct_local_copy(%struct.Block addrspace(1)* nocapture readonly %ip, i32 addrspace(1)* nocapture %out) #0 { entry: %0 = bitcast %struct.Block addrspace(1)* %ip to i8 addrspace(1)* %block.sroa.0.0.cast = bitcast i8 addrspace(1)* %0 to i32* %block.sroa.0.0.copyload = load i32* %block.sroa.0.0.cast, align 4 store i32 %block.sroa.0.0.copyload, i32 addrspace(1)* %out, align 4, !tbaa !5 ret void } attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } !opencl.kernels = !{!0, !1, !2, !3, !4} !0 = metadata !{null} !1 = metadata !{null} !2 = metadata !{null} !3 = metadata !{void (%struct.Block addrspace(1)*, i32 addrspace(1)*)* @struct_local_copy} !4 = metadata !{null} !5 = metadata !{metadata !6, metadata !6, i64 0} !6 = metadata !{metadata !"int", metadata !7, i64 0} !7 = metadata !{metadata !"omnipotent char", metadata !8, i64 0} !8 = metadata !{metadata !"Simple C/C++ TBAA"} # Machine code for function struct_local_copy: Post SSA, not tracking liveness BB#0: derived from LLVM BB %entry CF_ALU 4, 0, 0, 2, 0, 0, 0, 4, 1 RAT_WRITE_CACHELESS_32_eg %T1_X, %T0_X, 1 CF_END_EG PAD ALU_CLAUSE 4 %T0_X = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, %ALU_LITERAL_X, 0, 0, 0, -1, 0, pred:%PRED_SEL_OFF, 2, 0 %T0_W = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0 LITERALS 2, 0 %AR_X = MOVA_INT_eg 0, 0, 0, 0, %PV_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0 %T1_X = MOV 1, 0, 0, 0, %Addr0_X, 0, 1, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %AR_X # End machine code for function struct_local_copy. Shader Disassembly: ALU 4, @4, KC0[CB0:0-32], KC1[] ; 80000004 A0100000 MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 ; 0000A020 95E01000 CF_END ; 00000000 80200000 PAD ; 00000000 00000000 ALU clause starting at 4: ; LSHR T0.X, KC0[2].Z, literal.x, ; 001FA882 00000B10 LSHR * T0.W, KC0[2].Y, literal.x, ; 801FA482 60000B10 2(2.802597e-45), 0(0.000000e+00) ; 00000002 00000000 MOVA_INT * AR.x (MASKED), PV.W, ; 80000CFE 00006600 MOV * T1.X, T(0 + AR.x).X+, ; 80000200 00200C90 bytecode 18 dw -- 2 gprs -- 1 nstack ------------- shader 3 -- E -------------------------------------- ; ModuleID = 'radeon' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64" target triple = "r600--" %struct.Block = type { i32, i32, i32 } ; Function Attrs: nounwind define void @struct_extract_field(%struct.Block addrspace(1)* nocapture readonly %ip, i32 addrspace(1)* nocapture %out) #0 { entry: %f0 = getelementptr inbounds %struct.Block addrspace(1)* %ip, i32 0, i32 0 %0 = load i32 addrspace(1)* %f0, align 4, !tbaa !5 store i32 %0, i32 addrspace(1)* %out, align 4, !tbaa !5 ret void } attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } !opencl.kernels = !{!0, !1, !2, !3, !4} !0 = metadata !{null} !1 = metadata !{null} !2 = metadata !{null} !3 = metadata !{null} !4 = metadata !{void (%struct.Block addrspace(1)*, i32 addrspace(1)*)* @struct_extract_field} !5 = metadata !{metadata !6, metadata !6, i64 0} !6 = metadata !{metadata !"int", metadata !7, i64 0} !7 = metadata !{metadata !"omnipotent char", metadata !8, i64 0} !8 = metadata !{metadata !"Simple C/C++ TBAA"} # Machine code for function struct_extract_field: Post SSA, not tracking liveness BB#0: derived from LLVM BB %entry CF_ALU 8, 0, 0, 2, 0, 0, 0, 0, 1 CF_TC_EG 6, 0 CF_ALU 9, 0, 0, 2, 0, 0, 0, 1, 1 RAT_WRITE_CACHELESS_32_eg %T0_X, %T1_X, 1 CF_END_EG PAD FETCH_CLAUSE 6 %T0_X = VTX_READ_GLOBAL_32_eg %T0_X, 0; mem:LD4[%f01](tbaa=) ALU_CLAUSE 8 %T0_X = MOV 1, 0, 0, 0, %KC0_130_Y, 0, 0, 0, 2057, 1, pred:%PRED_SEL_OFF, 0, 0 ALU_CLAUSE 9 %T1_X = LSHR_eg 0, 0, 1, 0, 0, 0, %KC0_130_Z, 0, 0, 0, 2058, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 2, 0 LITERALS 2, 0 # End machine code for function struct_extract_field. Shader Disassembly: ALU 0, @8, KC0[CB0:0-32], KC1[] ; 80000008 A0000000 TEX 0 @6 ; 00000006 80400000 ALU 1, @9, KC0[CB0:0-32], KC1[] ; 80000009 A0040000 MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 ; 00802020 95E01000 CF_END ; 00000000 80200000 PAD ; 00000000 00000000 Fetch clause starting at 6: ; VTX_READ_32 T0.X, T0.X, 0 ; 10000140 135FF000 00080000 00000000 ALU clause starting at 8: ; MOV * T0.X, KC0[2].Y, ; 80000482 00000C90 ALU clause starting at 9: ; LSHR * T1.X, KC0[2].Z, literal.x, ; 801FA882 00200B10 2(2.802597e-45), 0(0.000000e+00) ; 00000002 00000000 bytecode 22 dw -- 2 gprs -- 1 nstack ------------- shader 4 -- E --------------------------------------