FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR1_VGPR2_VGPR3_VGPR4, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, VGPR1, VGPR2, VGPR3, VGPR4 ; F800020F 04030201 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 V_MBCNT_LO_U32_B32_e64 VGPR4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 VGPR4, -1, VGPR4 ; 480808C1 V_LSHR_B32_e64 VGPR5, SGPR11, 16, 0, 0, 0, 0 ; D22A0005 0201200B V_AND_B32_e32 VGPR5, 127, VGPR5 ; 360A0AFF 0000007F V_CMP_LT_I32_e64 SGPR0_SGPR1, VGPR4, VGPR5, 0, 0, 0, 0 ; D1020000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 SGPR0_SGPR1, SGPR0_SGPR1 ; BE802400 S_XOR_B64 SGPR0_SGPR1, EXEC, SGPR0_SGPR1 ; 8980007E V_ADD_I32_e64 VGPR4, SGPR12, VGPR4, 0, 0, 0, 0 ; D24A6A04 0202080C V_LSHLREV_B32_e32 VGPR4, 2, VGPR4 ; 34080882 V_LSHL_B32_e64 VGPR5, SGPR13, 2, 0, 0, 0, 0 ; D2320005 0201040D V_ADD_I32_e32 VGPR4, VGPR4, VGPR5 ; 4A080B04 S_LOAD_DWORDX4 SGPR4_SGPR5_SGPR6_SGPR7, SGPR8_SGPR9, 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X VGPR0, 0, -1, 0, -1, 0, 4, 4, VGPR4, SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 EXEC, EXEC, SGPR0_SGPR1 ; 88FE007E EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR7 ; BEFC0307 V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302 V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202 V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102 V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002 EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR1_VGPR2_VGPR3_VGPR4, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, VGPR1, VGPR2, VGPR3, VGPR4 ; F800020F 04030201 S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR6_SGPR7, 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW VGPR0_VGPR1_VGPR2_VGPR3, SGPR0_SGPR1_SGPR2_SGPR3[VGPR0] + 0 ; E00C2000 80000000 V_MBCNT_LO_U32_B32_e64 VGPR4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 VGPR4, -1, VGPR4 ; 480808C1 V_LSHR_B32_e64 VGPR5, SGPR11, 16, 0, 0, 0, 0 ; D22A0005 0201200B V_AND_B32_e32 VGPR5, 127, VGPR5 ; 360A0AFF 0000007F V_CMP_LT_I32_e64 SGPR0_SGPR1, VGPR4, VGPR5, 0, 0, 0, 0 ; D1020000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 SGPR0_SGPR1, SGPR0_SGPR1 ; BE802400 S_XOR_B64 SGPR0_SGPR1, EXEC, SGPR0_SGPR1 ; 8980007E V_ADD_I32_e64 VGPR4, SGPR12, VGPR4, 0, 0, 0, 0 ; D24A6A04 0202080C V_LSHLREV_B32_e32 VGPR4, 2, VGPR4 ; 34080882 V_LSHL_B32_e64 VGPR5, SGPR13, 2, 0, 0, 0, 0 ; D2320005 0201040D V_ADD_I32_e32 VGPR4, VGPR4, VGPR5 ; 4A080B04 S_LOAD_DWORDX4 SGPR4_SGPR5_SGPR6_SGPR7, SGPR8_SGPR9, 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X VGPR0, 0, -1, 0, -1, 0, 4, 4, VGPR4, SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 EXEC, EXEC, SGPR0_SGPR1 ; 88FE007E EXP 15, 12, 0, 1, 0, VGPR0, VGPR1, VGPR2, VGPR3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 VGPR0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, VGPR0, VGPR0, VGPR0, VGPR0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL OUT[0], COLOR DCL CONST[0..3] 0: MOV OUT[0], CONST[3] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0 %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 48) %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 52) %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 56) %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 60) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %23, float %24, float %25, float %26) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 SGPR0_SGPR1_SGPR2_SGPR3, SGPR0_SGPR1, 0 ; C0800100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD SGPR4, SGPR0_SGPR1_SGPR2_SGPR3, 15 ; C202010F S_BUFFER_LOAD_DWORD SGPR5, SGPR0_SGPR1_SGPR2_SGPR3, 14 ; C202810E S_BUFFER_LOAD_DWORD SGPR6, SGPR0_SGPR1_SGPR2_SGPR3, 13 ; C203010D S_BUFFER_LOAD_DWORD SGPR0, SGPR0_SGPR1_SGPR2_SGPR3, 12 ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 VGPR0, SGPR0 ; 7E000200 V_MOV_B32_e32 VGPR1, SGPR6 ; 7E020206 V_MOV_B32_e32 VGPR2, SGPR5 ; 7E040205 V_MOV_B32_e32 VGPR3, SGPR4 ; 7E060204 EXP 15, 0, 0, 1, 1, VGPR0, VGPR1, VGPR2, VGPR3 ; F800180F 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[19] DCL CONST[0] DCL TEMP[0..9], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} IMM[1] UINT32 {0, 1, 2, 3} IMM[2] UINT32 {2147483647, 0, 0, 0} 0: MOV TEMP[0], IMM[0].xxxx 1: MOV TEMP[1].x, IN[0].xxxx 2: USEQ TEMP[2].x, IN[0].xxxx, IMM[1].xxxx 3: UIF TEMP[2].xxxx :0 4: MOV TEMP[1].x, IMM[1].yyyy 5: ENDIF 6: MOV TEMP[2].x, IMM[1].xxxx 7: MOV TEMP[3].x, IMM[1].yyyy 8: BGNLOOP :0 9: USEQ TEMP[4].x, TEMP[1].xxxx, IMM[1].yyyy 10: UIF TEMP[4].xxxx :0 11: BRK 12: ENDIF 13: UADD TEMP[2].x, TEMP[2].xxxx, IMM[1].yyyy 14: UMOD TEMP[5].x, TEMP[1].xxxx, IMM[1].zzzz 15: USEQ TEMP[6].x, TEMP[5].xxxx, IMM[1].xxxx 16: UIF TEMP[6].xxxx :0 17: UDIV TEMP[1].x, TEMP[1].xxxx, IMM[1].zzzz 18: ELSE :0 19: UMAD TEMP[1].x, IMM[1].wwww, TEMP[1].xxxx, IMM[1].yyyy 20: ENDIF 21: MOV TEMP[7].x, IMM[1].xxxx 22: BGNLOOP :0 23: USGE TEMP[8].x, TEMP[7].xxxx, CONST[0].xxxx 24: UIF TEMP[8].xxxx :0 25: BRK 26: ENDIF 27: UMUL TEMP[9].x, TEMP[3].xxxx, IMM[1].zzzz 28: UMOD TEMP[3].x, TEMP[9].xxxx, IMM[2].xxxx 29: UADD TEMP[7].x, TEMP[7].xxxx, IMM[1].yyyy 30: ENDLOOP :0 31: ENDLOOP :0 32: MOV TEMP[1].x, IN[0].xxxx 33: MOV TEMP[1].y, TEMP[2].xxxx 34: MOV TEMP[1].z, TEMP[3].xxxx 35: MOV OUT[1], TEMP[1] 36: MOV OUT[0], TEMP[0] 37: END STREAMOUT 0: BUF0[0..0] <- OUT[1].x 1: BUF0[1..1] <- OUT[1].y 2: BUF0[2..2] <- OUT[1].z ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = call float @llvm.SI.load.const(<16 x i8> %14, i32 0) %16 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0 %18 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %19 = load <16 x i8> addrspace(2)* %18, !tbaa !0 %20 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %19, i32 0, i32 %9) %21 = extractelement <4 x float> %20, i32 0 %22 = bitcast float %21 to i32 %23 = icmp eq i32 %22, 0 %24 = sext i1 %23 to i32 %25 = bitcast i32 %24 to float %26 = bitcast float %25 to i32 %27 = icmp ne i32 %26, 0 %. = select i1 %27, float 0x36A0000000000000, float %21 %28 = bitcast float %15 to i32 br label %LOOP LOOP: ; preds = %LOOP47, %main_body %temp12.0 = phi float [ 0x36A0000000000000, %main_body ], [ %temp12.1, %LOOP47 ] %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %48, %LOOP47 ] %temp4.1 = phi float [ %., %main_body ], [ %62, %LOOP47 ] %29 = bitcast float %temp4.1 to i32 %30 = icmp eq i32 %29, 1 %31 = sext i1 %30 to i32 %32 = bitcast i32 %31 to float %33 = bitcast float %32 to i32 %34 = icmp ne i32 %33, 0 br i1 %34, label %IF41, label %ENDIF40 if-true-block: ; preds = %IF41 %35 = add i32 %7, %44 %36 = mul i32 %8, 4 %37 = mul i32 %35, 12 %38 = add i32 %37, %36 %39 = bitcast float %21 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %17, i32 %39, i32 1, i32 %38, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) %40 = bitcast float %temp8.0 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %17, i32 %40, i32 1, i32 %38, i32 0, i32 4, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) %41 = bitcast float %temp12.0 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %17, i32 %41, i32 1, i32 %38, i32 0, i32 8, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %IF41, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %21, float %temp8.0, float %temp12.0, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) ret void IF41: ; preds = %LOOP %42 = lshr i32 %6, 16 %43 = and i32 %42, 127 %44 = call i32 @llvm.SI.tid() %45 = icmp ult i32 %44, %43 br i1 %45, label %if-true-block, label %endif-block ENDIF40: ; preds = %LOOP %46 = bitcast float %temp8.0 to i32 %47 = add i32 %46, 1 %48 = bitcast i32 %47 to float %49 = bitcast float %temp4.1 to i32 %50 = urem i32 %49, 2 %51 = bitcast i32 %50 to float %52 = bitcast float %51 to i32 %53 = icmp eq i32 %52, 0 %54 = sext i1 %53 to i32 %55 = bitcast i32 %54 to float %56 = bitcast float %55 to i32 %57 = icmp ne i32 %56, 0 %58 = bitcast float %temp4.1 to i32 br i1 %57, label %IF44, label %ELSE45 IF44: ; preds = %ENDIF40 %59 = udiv i32 %58, 2 br label %ENDIF43 ELSE45: ; preds = %ENDIF40 %60 = mul i32 3, %58 %61 = add i32 %60, 1 br label %ENDIF43 ENDIF43: ; preds = %ELSE45, %IF44 %.sink = phi i32 [ %59, %IF44 ], [ %61, %ELSE45 ] %62 = bitcast i32 %.sink to float br label %LOOP47 LOOP47: ; preds = %ENDIF48, %ENDIF43 %temp12.1 = phi float [ %temp12.0, %ENDIF43 ], [ %74, %ENDIF48 ] %temp28.0 = phi float [ 0.000000e+00, %ENDIF43 ], [ %77, %ENDIF48 ] %63 = bitcast float %temp28.0 to i32 %64 = icmp uge i32 %63, %28 %65 = sext i1 %64 to i32 %66 = bitcast i32 %65 to float %67 = bitcast float %66 to i32 %68 = icmp ne i32 %67, 0 br i1 %68, label %LOOP, label %ENDIF48 ENDIF48: ; preds = %LOOP47 %69 = bitcast float %temp12.1 to i32 %70 = mul i32 %69, 2 %71 = bitcast i32 %70 to float %72 = bitcast float %71 to i32 %73 = urem i32 %72, 2147483647 %74 = bitcast i32 %73 to float %75 = bitcast float %temp28.0 to i32 %76 = add i32 %75, 1 %77 = bitcast i32 %76 to float br label %LOOP47 } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} LLVM ERROR: Cannot select: 0x194aba0: i1 = truncate 0x194c3c0 [ORD=40] [ID=16] 0x194c3c0: i32 = bitcast 0x1949e80 [ORD=36] [ID=15] 0x1949e80: f32,ch = CopyFromReg 0x1908560, 0x194c7c0 [ORD=36] [ID=13] 0x194c7c0: f32 = Register %vreg10 [ID=1] In function: main